APFloat.h		APFloat.h
	//== llvm/Support/APFloat.h - Arbitrary Precision Floating Point -*- C++ -* -==//		//== llvm/Support/APFloat.h - Arbitrary Precision Floating Point -*- C++ -* -==//
	//		//
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		///
	// This file declares a class to represent arbitrary precision floating		/// \file
	// point values and provide a variety of arithmetic operations on them.		/// \brief
	//		/// This file declares a class to represent arbitrary precision floating po
			int
			/// values and provide a variety of arithmetic operations on them.
			///
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	/* A self-contained host- and target-independent arbitrary-precision
	floating-point software implementation. It uses bignum integer
	arithmetic as provided by static functions in the APInt class.
	The library will work with bignum integers whose parts are any
	unsigned type at least 16 bits wide, but 64 bits is recommended.
	Written for clarity rather than speed, in particular with a view
	to use in the front-end of a cross compiler so that target
	arithmetic can be correctly performed on the host. Performance
	should nonetheless be reasonable, particularly for its intended
	use. It may be useful as a base implementation for a run-time
	library during development of a faster target-specific one.
	All 5 rounding modes in the IEEE-754R draft are handled correctly
	for all implemented operations. Currently implemented operations
	are add, subtract, multiply, divide, fused-multiply-add,
	conversion-to-float, conversion-to-integer and
	conversion-from-integer. New rounding modes (e.g. away from zero)
	can be added with three or four lines of code.
	Four formats are built-in: IEEE single precision, double
	precision, quadruple precision, and x87 80-bit extended double
	(when operating with full extended precision). Adding a new
	format that obeys IEEE semantics only requires adding two lines of
	code: a declaration and definition of the format.
	All operations return the status of that operation as an exception
	bit-mask, so multiple operations can be done consecutively with
	their results or-ed together. The returned status can be useful
	for compiler diagnostics; e.g., inexact, underflow and overflow
	can be easily diagnosed on constant folding, and compiler
	optimizers can determine what exceptions would be raised by
	folding operations and optimize, or perhaps not optimize,
	accordingly.
	At present, underflow tininess is detected after rounding; it
	should be straight forward to add support for the before-rounding
	case too.
	The library reads hexadecimal floating point numbers as per C99,
	and correctly rounds if necessary according to the specified
	rounding mode. Syntax is required to have been validated by the
	caller. It also converts floating point numbers to hexadecimal
	text as per the C99 %a and %A conversions. The output precision
	(or alternatively the natural minimal precision) can be specified;
	if the requested precision is less than the natural precision the
	output is correctly rounded for the specified rounding mode.
	It also reads decimal floating point numbers and correctly rounds
	according to the specified rounding mode.
	Conversion to decimal text is not currently implemented.
	Non-zero finite numbers are represented internally as a sign bit,
	a 16-bit signed exponent, and the significand as an array of
	integer parts. After normalization of a number of precision P the
	exponent is within the range of the format, and if the number is
	not denormal the P-th bit of the significand is set as an explicit
	integer bit. For denormals the most significant bit is shifted
	right so that the exponent is maintained at the format's minimum,
	so that the smallest denormal has just the least significant bit
	of the significand set. The sign of zeroes and infinities is
	significant; the exponent and significand of such numbers is not
	stored, but has a known implicit (deterministic) value: 0 for the
	significands, 0 for zero exponent, all 1 bits for infinity
	exponent. For NaNs the sign and significand are deterministic,
	although not really meaningful, and preserved in non-conversion
	operations. The exponent is implicitly all 1 bits.
	TODO
	====
	Some features that may or may not be worth adding:
	Binary to decimal conversion (hard).
	Optional ability to detect underflow tininess before rounding.
	New formats: x87 in single and double precision mode (IEEE apart
	from extended exponent range) (hard).
	New operations: sqrt, IEEE remainder, C90 fmod, nextafter,
	nexttoward.
	*/
	#ifndef LLVM_ADT_APFLOAT_H		#ifndef LLVM_ADT_APFLOAT_H
	#define LLVM_ADT_APFLOAT_H		#define LLVM_ADT_APFLOAT_H
	// APInt contains static functions implementing bignum arithmetic.
	#include "llvm/ADT/APInt.h"		#include "llvm/ADT/APInt.h"
	namespace llvm {		namespace llvm {
	/* Exponents are stored as signed numbers. */		struct fltSemantics;
	typedef signed short exponent_t;		class APSInt;
			class StringRef;
			/// Enum that represents what fraction of the LSB truncated bits of an fp n
			umber
			/// represent.
			///
			/// This essentially combines the roles of guard and sticky bits.
			enum lostFraction { // Example of truncated bits:
			lfExactlyZero, // 000000
			lfLessThanHalf, // 0xxxxx x's not all zero
			lfExactlyHalf, // 100000
			lfMoreThanHalf // 1xxxxx x's not all zero
			};
			/// \brief A self-contained host- and target-independent arbitrary-precisio
			n
			/// floating-point software implementation.
			///
			/// APFloat uses bignum integer arithmetic as provided by static functions
			in
			/// the APInt class. The library will work with bignum integers whose part
			s are
			/// any unsigned type at least 16 bits wide, but 64 bits is recommended.
			///
			/// Written for clarity rather than speed, in particular with a view to use
			in
			/// the front-end of a cross compiler so that target arithmetic can be corr
			ectly
			/// performed on the host. Performance should nonetheless be reasonable,
			/// particularly for its intended use. It may be useful as a base
			/// implementation for a run-time library during development of a faster
			/// target-specific one.
			///
			/// All 5 rounding modes in the IEEE-754R draft are handled correctly for a
			ll
			/// implemented operations. Currently implemented operations are add, subt
			ract,
			/// multiply, divide, fused-multiply-add, conversion-to-float,
			/// conversion-to-integer and conversion-from-integer. New rounding modes
			/// (e.g. away from zero) can be added with three or four lines of code.
			///
			/// Four formats are built-in: IEEE single precision, double precision,
			/// quadruple precision, and x87 80-bit extended double (when operating wit
			h
			/// full extended precision). Adding a new format that obeys IEEE semantic
			s
			/// only requires adding two lines of code: a declaration and definition of
			the
			/// format.
			///
			/// All operations return the status of that operation as an exception bit-
			mask,
			/// so multiple operations can be done consecutively with their results or-
			ed
			/// together. The returned status can be useful for compiler diagnostics;
			e.g.,
			/// inexact, underflow and overflow can be easily diagnosed on constant fol
			ding,
			/// and compiler optimizers can determine what exceptions would be raised b
			y
			/// folding operations and optimize, or perhaps not optimize, accordingly.
			///
			/// At present, underflow tininess is detected after rounding; it should be
			/// straight forward to add support for the before-rounding case too.
			///
			/// The library reads hexadecimal floating point numbers as per C99, and
			/// correctly rounds if necessary according to the specified rounding mode.
			/// Syntax is required to have been validated by the caller. It also conve
			rts
			/// floating point numbers to hexadecimal text as per the C99 %a and %A
			/// conversions. The output precision (or alternatively the natural minima
			l
			/// precision) can be specified; if the requested precision is less than th
			e
			/// natural precision the output is correctly rounded for the specified rou
			nding
			/// mode.
			///
			/// It also reads decimal floating point numbers and correctly rounds accor
			ding
			/// to the specified rounding mode.
			///
			/// Conversion to decimal text is not currently implemented.
			///
			/// Non-zero finite numbers are represented internally as a sign bit, a 16-
			bit
			/// signed exponent, and the significand as an array of integer parts. Aft
			er
			/// normalization of a number of precision P the exponent is within the ran
			ge of
			/// the format, and if the number is not denormal the P-th bit of the
			/// significand is set as an explicit integer bit. For denormals the most
			/// significant bit is shifted right so that the exponent is maintained at
			the
			/// format's minimum, so that the smallest denormal has just the least
			/// significant bit of the significand set. The sign of zeroes and infinit
			ies
			/// is significant; the exponent and significand of such numbers is not sto
			red,
			/// but has a known implicit (deterministic) value: 0 for the significands,
			0
			/// for zero exponent, all 1 bits for infinity exponent. For NaNs the sign
			and
			/// significand are deterministic, although not really meaningful, and pres
			erved
			/// in non-conversion operations. The exponent is implicitly all 1 bits.
			///
			/// APFloat does not provide any exception handling beyond default exceptio
			n
			/// handling. We represent Signaling NaNs via IEEE-754R 2008 6.2.1 should c
			lause
			/// by encoding Signaling NaNs with the first bit of its trailing significa
			nd as
			/// 0.
			///
			/// TODO
			/// ====
			///
			/// Some features that may or may not be worth adding:
			///
			/// Binary to decimal conversion (hard).
			///
			/// Optional ability to detect underflow tininess before rounding.
			///
			/// New formats: x87 in single and double precision mode (IEEE apart from
			/// extended exponent range) (hard).
			///
			/// New operations: sqrt, IEEE remainder, C90 fmod, nexttoward.
			///
			class APFloat {
			public:
			/// A signed type to represent a floating point numbers unbiased exponent
			.
			typedef signed short ExponentType;
			/// \name Floating Point Semantics.
			/// @{
			static const fltSemantics IEEEhalf;
			static const fltSemantics IEEEsingle;
			static const fltSemantics IEEEdouble;
			static const fltSemantics IEEEquad;
			static const fltSemantics PPCDoubleDouble;
			static const fltSemantics x87DoubleExtended;
			/// A Pseudo fltsemantic used to construct APFloats that cannot conflict
			with
			/// anything real.
			static const fltSemantics Bogus;
			/// @}
			static unsigned int semanticsPrecision(const fltSemantics &);
			/// IEEE-754R 5.11: Floating Point Comparison Relations.
			enum cmpResult {
			cmpLessThan,
			cmpEqual,
			cmpGreaterThan,
			cmpUnordered
			};
	struct fltSemantics;		/// IEEE-754R 4.3: Rounding-direction attributes.
	class APSInt;		enum roundingMode {
	class StringRef;		rmNearestTiesToEven,
			rmTowardPositive,
	/* When bits of a floating point number are truncated, this enum is		rmTowardNegative,
	used to indicate what fraction of the LSB those bits represented.		rmTowardZero,
	It essentially combines the roles of guard and sticky bits. */		rmNearestTiesToAway
	enum lostFraction { // Example of truncated bits:
	lfExactlyZero, // 000000
	lfLessThanHalf, // 0xxxxx x's not all zero
	lfExactlyHalf, // 100000
	lfMoreThanHalf // 1xxxxx x's not all zero
	};		};
	class APFloat {		/// IEEE-754R 7: Default exception handling.
	public:		///
			/// opUnderflow or opOverflow are always returned or-ed with opInexact.
			enum opStatus {
			opOK = 0x00,
			opInvalidOp = 0x01,
			opDivByZero = 0x02,
			opOverflow = 0x04,
			opUnderflow = 0x08,
			opInexact = 0x10
			};
	/* We support the following floating point semantics. */		/// Category of internally-represented number.
	static const fltSemantics IEEEhalf;		enum fltCategory {
	static const fltSemantics IEEEsingle;		fcInfinity,
	static const fltSemantics IEEEdouble;		fcNaN,
	static const fltSemantics IEEEquad;		fcNormal,
	static const fltSemantics PPCDoubleDouble;		fcZero
	static const fltSemantics x87DoubleExtended;		};
	/* And this pseudo, used to construct APFloats that cannot
	conflict with anything real. */
	static const fltSemantics Bogus;
	static unsigned int semanticsPrecision(const fltSemantics &);
	/* Floating point numbers have a four-state comparison relation. */
	enum cmpResult {
	cmpLessThan,
	cmpEqual,
	cmpGreaterThan,
	cmpUnordered
	};
	/* IEEE-754R gives five rounding modes. */
	enum roundingMode {
	rmNearestTiesToEven,
	rmTowardPositive,
	rmTowardNegative,
	rmTowardZero,
	rmNearestTiesToAway
	};
	// Operation status. opUnderflow or opOverflow are always returned
	// or-ed with opInexact.
	enum opStatus {
	opOK = 0x00,
	opInvalidOp = 0x01,
	opDivByZero = 0x02,
	opOverflow = 0x04,
	opUnderflow = 0x08,
	opInexact = 0x10
	};
	// Category of internally-represented number.
	enum fltCategory {
	fcInfinity,
	fcNaN,
	fcNormal,
	fcZero
	};
	enum uninitializedTag {
	uninitialized
	};
	// Constructors.
	APFloat(const fltSemantics &); // Default construct to 0.0
	APFloat(const fltSemantics &, StringRef);
	APFloat(const fltSemantics &, integerPart);
	APFloat(const fltSemantics &, fltCategory, bool negative);
	APFloat(const fltSemantics &, uninitializedTag);
	APFloat(const fltSemantics &, const APInt &);
	explicit APFloat(double d);
	explicit APFloat(float f);
	APFloat(const APFloat &);
	~APFloat();
	// Convenience "constructors"
	static APFloat getZero(const fltSemantics &Sem, bool Negative = false)
	{
	return APFloat(Sem, fcZero, Negative);
	}
	static APFloat getInf(const fltSemantics &Sem, bool Negative = false) {
	return APFloat(Sem, fcInfinity, Negative);
	}
	/// getNaN - Factory for QNaN values.		/// Convenience enum used to construct an uninitialized APFloat.
	///		enum uninitializedTag {
	/// \param Negative - True iff the NaN generated should be negative.		uninitialized
	/// \param type - The unspecified fill bits for creating the NaN, 0 by		};
	/// default. The value is truncated as necessary.
	static APFloat getNaN(const fltSemantics &Sem, bool Negative = false,
	unsigned type = 0) {
	if (type) {
	APInt fill(64, type);
	return getQNaN(Sem, Negative, &fill);
	} else {
	return getQNaN(Sem, Negative, 0);
	}
	}
	/// getQNan - Factory for QNaN values.		/// \name Constructors
	static APFloat getQNaN(const fltSemantics &Sem,		/// @{
	bool Negative = false,
	const APInt *payload = 0) {
	return makeNaN(Sem, false, Negative, payload);
	}
	/// getSNan - Factory for SNaN values.		APFloat(const fltSemantics &); // Default construct to 0.0
	static APFloat getSNaN(const fltSemantics &Sem,		APFloat(const fltSemantics &, StringRef);
	bool Negative = false,		APFloat(const fltSemantics &, integerPart);
	const APInt *payload = 0) {		APFloat(const fltSemantics &, uninitializedTag);
	return makeNaN(Sem, true, Negative, payload);		APFloat(const fltSemantics &, const APInt &);
			explicit APFloat(double d);
			explicit APFloat(float f);
			APFloat(const APFloat &);
			~APFloat();
			/// @}
			/// \brief Returns whether this instance allocated memory.
			bool needsCleanup() const { return partCount() > 1; }
			/// \name Convenience "constructors"
			/// @{
			/// Factory for Positive and Negative Zero.
			///
			/// \param Negative True iff the number should be negative.
			static APFloat getZero(const fltSemantics &Sem, bool Negative = false) {
			APFloat Val(Sem, uninitialized);
			Val.makeZero(Negative);
			return Val;
			}
			/// Factory for Positive and Negative Infinity.
			///
			/// \param Negative True iff the number should be negative.
			static APFloat getInf(const fltSemantics &Sem, bool Negative = false) {
			APFloat Val(Sem, uninitialized);
			Val.makeInf(Negative);
			return Val;
			}
			/// Factory for QNaN values.
			///
			/// \param Negative - True iff the NaN generated should be negative.
			/// \param type - The unspecified fill bits for creating the NaN, 0 by
			/// default. The value is truncated as necessary.
			static APFloat getNaN(const fltSemantics &Sem, bool Negative = false,
			unsigned type = 0) {
			if (type) {
			APInt fill(64, type);
			return getQNaN(Sem, Negative, &fill);
			} else {
			return getQNaN(Sem, Negative, 0);
	}		}
			}
	/// getLargest - Returns the largest finite number in the given		/// Factory for QNaN values.
	/// semantics.		static APFloat getQNaN(const fltSemantics &Sem, bool Negative = false,
	///		const APInt *payload = 0) {
	/// \param Negative - True iff the number should be negative		return makeNaN(Sem, false, Negative, payload);
	static APFloat getLargest(const fltSemantics &Sem, bool Negative = fals		}
	e);
			/// Factory for SNaN values.
	/// getSmallest - Returns the smallest (by magnitude) finite number		static APFloat getSNaN(const fltSemantics &Sem, bool Negative = false,
	/// in the given semantics. Might be denormalized, which implies a		const APInt *payload = 0) {
	/// relative loss of precision.		return makeNaN(Sem, true, Negative, payload);
	///		}
	/// \param Negative - True iff the number should be negative
	static APFloat getSmallest(const fltSemantics &Sem, bool Negative = fal		/// Returns the largest finite number in the given semantics.
	se);		///
			/// \param Negative - True iff the number should be negative
	/// getSmallestNormalized - Returns the smallest (by magnitude)		static APFloat getLargest(const fltSemantics &Sem, bool Negative = false)
	/// normalized finite number in the given semantics.		;
	///
	/// \param Negative - True iff the number should be negative		/// Returns the smallest (by magnitude) finite number in the given semant
	static APFloat getSmallestNormalized(const fltSemantics &Sem,		ics.
	bool Negative = false);		/// Might be denormalized, which implies a relative loss of precision.
			///
	/// getAllOnesValue - Returns a float which is bitcasted from		/// \param Negative - True iff the number should be negative
	/// an all one value int.		static APFloat getSmallest(const fltSemantics &Sem, bool Negative = false
	///		);
	/// \param BitWidth - Select float type
	/// \param isIEEE - If 128 bit number, select between PPC and IEEE		/// Returns the smallest (by magnitude) normalized finite number in the g
	static APFloat getAllOnesValue(unsigned BitWidth, bool isIEEE = false);		iven
			/// semantics.
	/// Profile - Used to insert APFloat objects, or objects that contain		///
	/// APFloat objects, into FoldingSets.		/// \param Negative - True iff the number should be negative
	void Profile(FoldingSetNodeID& NID) const;		static APFloat getSmallestNormalized(const fltSemantics &Sem,
			bool Negative = false);
	/// @brief Used by the Bitcode serializer to emit APInts to Bitcode.
	void Emit(Serializer& S) const;		/// Returns a float which is bitcasted from an all one value int.
			///
	/// @brief Used by the Bitcode deserializer to deserialize APInts.		/// \param BitWidth - Select float type
	static APFloat ReadVal(Deserializer& D);		/// \param isIEEE - If 128 bit number, select between PPC and IEEE
			static APFloat getAllOnesValue(unsigned BitWidth, bool isIEEE = false);
	/* Arithmetic. */
	opStatus add(const APFloat &, roundingMode);		/// @}
	opStatus subtract(const APFloat &, roundingMode);
	opStatus multiply(const APFloat &, roundingMode);		/// Used to insert APFloat objects, or objects that contain APFloat objec
	opStatus divide(const APFloat &, roundingMode);		ts,
	/* IEEE remainder. */		/// into FoldingSets.
	opStatus remainder(const APFloat &);		void Profile(FoldingSetNodeID &NID) const;
	/* C fmod, or llvm frem. */
	opStatus mod(const APFloat &, roundingMode);		/// \brief Used by the Bitcode serializer to emit APInts to Bitcode.
	opStatus fusedMultiplyAdd(const APFloat &, const APFloat &, roundingMod		void Emit(Serializer &S) const;
	e);
	opStatus roundToIntegral(roundingMode);		/// \brief Used by the Bitcode deserializer to deserialize APInts.
			static APFloat ReadVal(Deserializer &D);
	/* Sign operations. */
	void changeSign();		/// \name Arithmetic
	void clearSign();		/// @{
	void copySign(const APFloat &);
			opStatus add(const APFloat &, roundingMode);
	/* Conversions. */		opStatus subtract(const APFloat &, roundingMode);
	opStatus convert(const fltSemantics &, roundingMode, bool *);		opStatus multiply(const APFloat &, roundingMode);
	opStatus convertToInteger(integerPart *, unsigned int, bool,		opStatus divide(const APFloat &, roundingMode);
	roundingMode, bool *) const;		/// IEEE remainder.
	opStatus convertToInteger(APSInt&, roundingMode, bool *) const;		opStatus remainder(const APFloat &);
	opStatus convertFromAPInt(const APInt &,		/// C fmod, or llvm frem.
	bool, roundingMode);		opStatus mod(const APFloat &, roundingMode);
	opStatus convertFromSignExtendedInteger(const integerPart *, unsigned i		opStatus fusedMultiplyAdd(const APFloat &, const APFloat &, roundingMode)
	nt,		;
	bool, roundingMode);		opStatus roundToIntegral(roundingMode);
	opStatus convertFromZeroExtendedInteger(const integerPart *, unsigned i		/// IEEE-754R 5.3.1: nextUp/nextDown.
	nt,		opStatus next(bool nextDown);
	bool, roundingMode);
	opStatus convertFromString(StringRef, roundingMode);		/// @}
	APInt bitcastToAPInt() const;
	double convertToDouble() const;		/// \name Sign operations.
	float convertToFloat() const;		/// @{
	/* The definition of equality is not straightforward for floating point		void changeSign();
	,		void clearSign();
	so we won't use operator==. Use one of the following, or write		void copySign(const APFloat &);
	whatever it is you really mean. */
	bool operator==(const APFloat &) const LLVM_DELETED_FUNCTION;		/// @}
	/* IEEE comparison with another floating point number (NaNs		/// \name Conversions
	compare unordered, 0==-0). */		/// @{
	cmpResult compare(const APFloat &) const;
			opStatus convert(const fltSemantics &, roundingMode, bool *);
	/* Bitwise comparison for equality (QNaNs compare equal, 0!=-0). */		opStatus convertToInteger(integerPart *, unsigned int, bool, roundingMode
	bool bitwiseIsEqual(const APFloat &) const;		,
			bool *) const;
	/* Write out a hexadecimal representation of the floating point		opStatus convertToInteger(APSInt &, roundingMode, bool *) const;
	value to DST, which must be of sufficient size, in the C99 form		opStatus convertFromAPInt(const APInt &, bool, roundingMode);
	[-]0xh.hhhhp[+-]d. Return the number of characters written,		opStatus convertFromSignExtendedInteger(const integerPart *, unsigned int
	excluding the terminating NUL. */		,
	unsigned int convertToHexString(char *dst, unsigned int hexDigits,		bool, roundingMode);
	bool upperCase, roundingMode) const;		opStatus convertFromZeroExtendedInteger(const integerPart *, unsigned int
			,
	/* Simple queries. */		bool, roundingMode);
	fltCategory getCategory() const { return category; }		opStatus convertFromString(StringRef, roundingMode);
	const fltSemantics &getSemantics() const { return *semantics; }		APInt bitcastToAPInt() const;
	bool isZero() const { return category == fcZero; }		double convertToDouble() const;
	bool isNonZero() const { return category != fcZero; }		float convertToFloat() const;
	bool isNormal() const { return category == fcNormal; }
	bool isNaN() const { return category == fcNaN; }		/// @}
	bool isInfinity() const { return category == fcInfinity; }
	bool isNegative() const { return sign; }		/// The definition of equality is not straightforward for floating point,
	bool isPosZero() const { return isZero() && !isNegative(); }		so
	bool isNegZero() const { return isZero() && isNegative(); }		/// we won't use operator==. Use one of the following, or write whatever
	bool isDenormal() const;		it
			/// is you really mean.
	APFloat& operator=(const APFloat &);		bool operator==(const APFloat &) const LLVM_DELETED_FUNCTION;
	/// \brief Overload to compute a hash code for an APFloat value.		/// IEEE comparison with another floating point number (NaNs compare
	///		/// unordered, 0==-0).
	/// Note that the use of hash codes for floating point values is in gen		cmpResult compare(const APFloat &) const;
	eral
	/// frought with peril. Equality is hard to define for these values. Fo		/// Bitwise comparison for equality (QNaNs compare equal, 0!=-0).
	r		bool bitwiseIsEqual(const APFloat &) const;
	/// example, should negative and positive zero hash to different codes?
	Are		/// Write out a hexadecimal representation of the floating point value to
	/// they equal or not? This hash value implementation specifically		DST,
	/// emphasizes producing different codes for different inputs in order		/// which must be of sufficient size, in the C99 form [-]0xh.hhhhp[+-]d.
	to		/// Return the number of characters written, excluding the terminating NU
	/// be used in canonicalization and memoization. As such, equality is		L.
	/// bitwiseIsEqual, and 0 != -0.		unsigned int convertToHexString(char *dst, unsigned int hexDigits,
	friend hash_code hash_value(const APFloat &Arg);		bool upperCase, roundingMode) const;
	/// Converts this value into a decimal string.		/// \name IEEE-754R 5.7.2 General operations.
	///		/// @{
	/// \param FormatPrecision The maximum number of digits of
	/// precision to output. If there are fewer digits available,		/// IEEE-754R isSignMinus: Returns true if and only if the current value
	/// zero padding will not be used unless the value is		is
	/// integral and small enough to be expressed in		/// negative.
	/// FormatPrecision digits. 0 means to use the natural		///
	/// precision of the number.		/// This applies to zeros and NaNs as well.
	/// \param FormatMaxPadding The maximum number of zeros to		bool isNegative() const { return sign; }
	/// consider inserting before falling back to scientific
	/// notation. 0 means to always use scientific notation.		/// IEEE-754R isNormal: Returns true if and only if the current value is
	///		normal.
	/// Number Precision MaxPadding Result		///
	/// ------ --------- ---------- ------		/// This implies that the current value of the float is not zero, subnorm
	/// 1.01E+4 5 2 10100		al,
	/// 1.01E+4 4 2 1.01E+4		/// infinite, or NaN following the definition of normality from IEEE-754R
	/// 1.01E+4 5 1 1.01E+4		.
	/// 1.01E-2 5 2 0.0101		bool isNormal() const { return !isDenormal() && isFiniteNonZero(); }
	/// 1.01E-2 4 2 0.0101
	/// 1.01E-2 4 1 1.01E-2		/// Returns true if and only if the current value is zero, subnormal, or
	void toString(SmallVectorImpl<char> &Str,		/// normal.
	unsigned FormatPrecision = 0,		///
	unsigned FormatMaxPadding = 3) const;		/// This means that the value is not infinite or NaN.
			bool isFinite() const { return !isNaN() && !isInfinity(); }
	/// getExactInverse - If this value has an exact multiplicative inverse
	,		/// Returns true if and only if the float is plus or minus zero.
	/// store it in inv and return true.		bool isZero() const { return category == fcZero; }
	bool getExactInverse(APFloat *inv) const;
			/// IEEE-754R isSubnormal(): Returns true if and only if the float is a
	private:		/// denormal.
			bool isDenormal() const;
	/* Trivial queries. */
	integerPart *significandParts();		/// IEEE-754R isInfinite(): Returns true if and only if the float is infi
	const integerPart *significandParts() const;		nity.
	unsigned int partCount() const;		bool isInfinity() const { return category == fcInfinity; }
	/* Significand operations. */		/// Returns true if and only if the float is a quiet or signaling NaN.
	integerPart addSignificand(const APFloat &);		bool isNaN() const { return category == fcNaN; }
	integerPart subtractSignificand(const APFloat &, integerPart);
	lostFraction addOrSubtractSignificand(const APFloat &, bool subtract);		/// Returns true if and only if the float is a signaling NaN.
	lostFraction multiplySignificand(const APFloat &, const APFloat *);		bool isSignaling() const;
	lostFraction divideSignificand(const APFloat &);
	void incrementSignificand();		/// @}
	void initialize(const fltSemantics *);
	void shiftSignificandLeft(unsigned int);		/// \name Simple Queries
	lostFraction shiftSignificandRight(unsigned int);		/// @{
	unsigned int significandLSB() const;
	unsigned int significandMSB() const;		fltCategory getCategory() const { return category; }
	void zeroSignificand();		const fltSemantics &getSemantics() const { return *semantics; }
			bool isNonZero() const { return category != fcZero; }
	/* Arithmetic on special values. */		bool isFiniteNonZero() const { return isFinite() && !isZero(); }
	opStatus addOrSubtractSpecials(const APFloat &, bool subtract);		bool isPosZero() const { return isZero() && !isNegative(); }
	opStatus divideSpecials(const APFloat &);		bool isNegZero() const { return isZero() && isNegative(); }
	opStatus multiplySpecials(const APFloat &);
	opStatus modSpecials(const APFloat &);		/// Returns true if and only if the number has the smallest possible non-
			zero
	/* Miscellany. */		/// magnitude in the current semantics.
	static APFloat makeNaN(const fltSemantics &Sem, bool SNaN, bool Negativ		bool isSmallest() const;
	e,
	const APInt *fill);		/// Returns true if and only if the number has the largest possible finit
	void makeNaN(bool SNaN = false, bool Neg = false, const APInt *fill = 0		e
	);		/// magnitude in the current semantics.
	opStatus normalize(roundingMode, lostFraction);		bool isLargest() const;
	opStatus addOrSubtract(const APFloat &, roundingMode, bool subtract);
	cmpResult compareAbsoluteValue(const APFloat &) const;		/// @}
	opStatus handleOverflow(roundingMode);
	bool roundAwayFromZero(roundingMode, lostFraction, unsigned int) const;		APFloat &operator=(const APFloat &);
	opStatus convertToSignExtendedInteger(integerPart *, unsigned int, bool
	,		/// \brief Overload to compute a hash code for an APFloat value.
	roundingMode, bool *) const;		///
	opStatus convertFromUnsignedParts(const integerPart *, unsigned int,		/// Note that the use of hash codes for floating point values is in gener
	roundingMode);		al
	opStatus convertFromHexadecimalString(StringRef, roundingMode);		/// frought with peril. Equality is hard to define for these values. For
	opStatus convertFromDecimalString(StringRef, roundingMode);		/// example, should negative and positive zero hash to different codes? A
	char *convertNormalToHexString(char *, unsigned int, bool,		re
	roundingMode) const;		/// they equal or not? This hash value implementation specifically
	opStatus roundSignificandWithExponent(const integerPart *, unsigned int		/// emphasizes producing different codes for different inputs in order to
	,		/// be used in canonicalization and memoization. As such, equality is
	int, roundingMode);		/// bitwiseIsEqual, and 0 != -0.
			friend hash_code hash_value(const APFloat &Arg);
	APInt convertHalfAPFloatToAPInt() const;
	APInt convertFloatAPFloatToAPInt() const;		/// Converts this value into a decimal string.
	APInt convertDoubleAPFloatToAPInt() const;		///
	APInt convertQuadrupleAPFloatToAPInt() const;		/// \param FormatPrecision The maximum number of digits of
	APInt convertF80LongDoubleAPFloatToAPInt() const;		/// precision to output. If there are fewer digits available,
	APInt convertPPCDoubleDoubleAPFloatToAPInt() const;		/// zero padding will not be used unless the value is
	void initFromAPInt(const fltSemantics *Sem, const APInt& api);		/// integral and small enough to be expressed in
	void initFromHalfAPInt(const APInt& api);		/// FormatPrecision digits. 0 means to use the natural
	void initFromFloatAPInt(const APInt& api);		/// precision of the number.
	void initFromDoubleAPInt(const APInt& api);		/// \param FormatMaxPadding The maximum number of zeros to
	void initFromQuadrupleAPInt(const APInt &api);		/// consider inserting before falling back to scientific
	void initFromF80LongDoubleAPInt(const APInt& api);		/// notation. 0 means to always use scientific notation.
	void initFromPPCDoubleDoubleAPInt(const APInt& api);		///
			/// Number Precision MaxPadding Result
	void assign(const APFloat &);		/// ------ --------- ---------- ------
	void copySignificand(const APFloat &);		/// 1.01E+4 5 2 10100
	void freeSignificand();		/// 1.01E+4 4 2 1.01E+4
			/// 1.01E+4 5 1 1.01E+4
	/* What kind of semantics does this value obey? */		/// 1.01E-2 5 2 0.0101
	const fltSemantics *semantics;		/// 1.01E-2 4 2 0.0101
			/// 1.01E-2 4 1 1.01E-2
	/* Significand - the fraction with an explicit integer bit. Must be		void toString(SmallVectorImpl<char> &Str, unsigned FormatPrecision = 0,
	at least one bit wider than the target precision. */		unsigned FormatMaxPadding = 3) const;
	union Significand
	{		/// If this value has an exact multiplicative inverse, store it in inv an
	integerPart part;		d
	integerPart *parts;		/// return true.
	} significand;		bool getExactInverse(APFloat *inv) const;
	/* The exponent - a signed number. */		private:
	exponent_t exponent;
			/// \name Simple Queries
	/* What kind of floating point number this is. */		/// @{
	/* Only 2 bits are required, but VisualStudio incorrectly sign extends
	it. Using the extra bit keeps it from failing under VisualStudio */		integerPart *significandParts();
	fltCategory category: 3;		const integerPart *significandParts() const;
			unsigned int partCount() const;
	/* The sign bit of this number. */
	unsigned int sign: 1;		/// @}
	};
			/// \name Significand operations.
	// See friend declaration above. This additional declaration is required		/// @{
	in
	// order to compile LLVM with IBM xlC compiler.		integerPart addSignificand(const APFloat &);
	hash_code hash_value(const APFloat &Arg);		integerPart subtractSignificand(const APFloat &, integerPart);
	} /* namespace llvm */		lostFraction addOrSubtractSignificand(const APFloat &, bool subtract);
			lostFraction multiplySignificand(const APFloat &, const APFloat *);
			lostFraction divideSignificand(const APFloat &);
			void incrementSignificand();
			void initialize(const fltSemantics *);
			void shiftSignificandLeft(unsigned int);
			lostFraction shiftSignificandRight(unsigned int);
			unsigned int significandLSB() const;
			unsigned int significandMSB() const;
			void zeroSignificand();
			/// Return true if the significand excluding the integral bit is all ones
			.
			bool isSignificandAllOnes() const;
			/// Return true if the significand excluding the integral bit is all zero
			s.
			bool isSignificandAllZeros() const;
			/// @}
			/// \name Arithmetic on special values.
			/// @{
			opStatus addOrSubtractSpecials(const APFloat &, bool subtract);
			opStatus divideSpecials(const APFloat &);
			opStatus multiplySpecials(const APFloat &);
			opStatus modSpecials(const APFloat &);
			/// @}
			/// \name Special value setters.
			/// @{
			void makeLargest(bool Neg = false);
			void makeSmallest(bool Neg = false);
			void makeNaN(bool SNaN = false, bool Neg = false, const APInt *fill = 0);
			static APFloat makeNaN(const fltSemantics &Sem, bool SNaN, bool Negative,
			const APInt *fill);
			void makeInf(bool Neg = false);
			void makeZero(bool Neg = false);
			/// @}
			/// \name Miscellany
			/// @{
			bool convertFromStringSpecials(StringRef str);
			opStatus normalize(roundingMode, lostFraction);
			opStatus addOrSubtract(const APFloat &, roundingMode, bool subtract);
			cmpResult compareAbsoluteValue(const APFloat &) const;
			opStatus handleOverflow(roundingMode);
			bool roundAwayFromZero(roundingMode, lostFraction, unsigned int) const;
			opStatus convertToSignExtendedInteger(integerPart *, unsigned int, bool,
			roundingMode, bool *) const;
			opStatus convertFromUnsignedParts(const integerPart *, unsigned int,
			roundingMode);
			opStatus convertFromHexadecimalString(StringRef, roundingMode);
			opStatus convertFromDecimalString(StringRef, roundingMode);
			char *convertNormalToHexString(char *, unsigned int, bool,
			roundingMode) const;
			opStatus roundSignificandWithExponent(const integerPart *, unsigned int,
			int,
			roundingMode);
			/// @}
			APInt convertHalfAPFloatToAPInt() const;
			APInt convertFloatAPFloatToAPInt() const;
			APInt convertDoubleAPFloatToAPInt() const;
			APInt convertQuadrupleAPFloatToAPInt() const;
			APInt convertF80LongDoubleAPFloatToAPInt() const;
			APInt convertPPCDoubleDoubleAPFloatToAPInt() const;
			void initFromAPInt(const fltSemantics *Sem, const APInt &api);
			void initFromHalfAPInt(const APInt &api);
			void initFromFloatAPInt(const APInt &api);
			void initFromDoubleAPInt(const APInt &api);
			void initFromQuadrupleAPInt(const APInt &api);
			void initFromF80LongDoubleAPInt(const APInt &api);
			void initFromPPCDoubleDoubleAPInt(const APInt &api);
			void assign(const APFloat &);
			void copySignificand(const APFloat &);
			void freeSignificand();
			/// The semantics that this value obeys.
			const fltSemantics *semantics;
			/// A binary fraction with an explicit integer bit.
			///
			/// The significand must be at least one bit wider than the target precis
			ion.
			union Significand {
			integerPart part;
			integerPart *parts;
			} significand;
			/// The signed unbiased exponent of the value.
			ExponentType exponent;
			/// What kind of floating point number this is.
			///
			/// Only 2 bits are required, but VisualStudio incorrectly sign extends i
			t.
			/// Using the extra bit keeps it from failing under VisualStudio.
			fltCategory category : 3;
			/// Sign bit of the number.
			unsigned int sign : 1;
			};
			/// See friend declaration above.
			///
			/// This additional declaration is required in order to compile LLVM with I
			BM
			/// xlC compiler.
			hash_code hash_value(const APFloat &Arg);
			} // namespace llvm
	#endif /* LLVM_ADT_APFLOAT_H */		#endif // LLVM_ADT_APFLOAT_H
End of changes. 13 change blocks.
	455 lines changed or deleted		617 lines changed or added

	APInt.h		APInt.h
	//===-- llvm/ADT/APInt.h - For Arbitrary Precision Integer -----*- C++ -*-- ===//		//===-- llvm/ADT/APInt.h - For Arbitrary Precision Integer -----*- C++ -*-- ===//
	//		//
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		///
	// This file implements a class to represent arbitrary precision integral		/// \file
	// constant values and operations on them.		/// \brief This file implements a class to represent arbitrary precision
	//		/// integral constant values and operations on them.
			///
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_ADT_APINT_H		#ifndef LLVM_ADT_APINT_H
	#define LLVM_ADT_APINT_H		#define LLVM_ADT_APINT_H
	#include "llvm/ADT/ArrayRef.h"		#include "llvm/ADT/ArrayRef.h"
	#include "llvm/Support/Compiler.h"		#include "llvm/Support/Compiler.h"
	#include "llvm/Support/MathExtras.h"		#include "llvm/Support/MathExtras.h"
	#include <cassert>		#include <cassert>
	#include <climits>		#include <climits>
	#include <cstring>		#include <cstring>
	#include <string>		#include <string>
	namespace llvm {		namespace llvm {
	class Deserializer;		class Deserializer;
	class FoldingSetNodeID;		class FoldingSetNodeID;
	class Serializer;		class Serializer;
	class StringRef;		class StringRef;
	class hash_code;		class hash_code;
	class raw_ostream;		class raw_ostream;
	template<typename T>		template <typename T> class SmallVectorImpl;
	class SmallVectorImpl;
			// An unsigned host type used as a single part of a multi-part
	// An unsigned host type used as a single part of a multi-part		// bignum.
	// bignum.		typedef uint64_t integerPart;
	typedef uint64_t integerPart;
			const unsigned int host_char_bit = 8;
	const unsigned int host_char_bit = 8;		const unsigned int integerPartWidth =
	const unsigned int integerPartWidth = host_char_bit *		host_char_bit * static_cast<unsigned int>(sizeof(integerPart));
	static_cast<unsigned int>(sizeof(integerPart));
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// APInt Class		// APInt Class
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	/// APInt - This class represents arbitrary precision constant integral val		/// \brief Class for arbitrary precision integers.
	ues.		///
	/// It is a functional replacement for common case unsigned integer type li		/// APInt is a functional replacement for common case unsigned integer type
	ke		like
	/// "unsigned", "unsigned long" or "uint64_t", but also allows non-byte-wid th		/// "unsigned", "unsigned long" or "uint64_t", but also allows non-byte-wid th
	/// integer sizes and large integer value types such as 3-bits, 15-bits, or more		/// integer sizes and large integer value types such as 3-bits, 15-bits, or more
	/// than 64-bits of precision. APInt provides a variety of arithmetic opera tors		/// than 64-bits of precision. APInt provides a variety of arithmetic opera tors
	/// and methods to manipulate integer values of any bit-width. It supports both		/// and methods to manipulate integer values of any bit-width. It supports both
	/// the typical integer arithmetic and comparison operations as well as bit wise		/// the typical integer arithmetic and comparison operations as well as bit wise
	/// manipulation.		/// manipulation.
	///		///
	/// The class has several invariants worth noting:		/// The class has several invariants worth noting:
	/// * All bit, byte, and word positions are zero-based.		/// * All bit, byte, and word positions are zero-based.
	/// * Once the bit width is set, it doesn't change except by the Truncate ,		/// * Once the bit width is set, it doesn't change except by the Truncate ,
	skipping to change at line 74		skipping to change at line 75
	/// widths will yield an assertion.		/// widths will yield an assertion.
	/// * The value is stored canonically as an unsigned value. For operation s		/// * The value is stored canonically as an unsigned value. For operation s
	/// where it makes a difference, there are both signed and unsigned var iants		/// where it makes a difference, there are both signed and unsigned var iants
	/// of the operation. For example, sdiv and udiv. However, because the bit		/// of the operation. For example, sdiv and udiv. However, because the bit
	/// widths must be the same, operations such as Mul and Add produce the same		/// widths must be the same, operations such as Mul and Add produce the same
	/// results regardless of whether the values are interpreted as signed or		/// results regardless of whether the values are interpreted as signed or
	/// not.		/// not.
	/// * In general, the class tries to follow the style of computation that LLVM		/// * In general, the class tries to follow the style of computation that LLVM
	/// uses in its IR. This simplifies its use for LLVM.		/// uses in its IR. This simplifies its use for LLVM.
	///		///
	/// @brief Class for arbitrary precision integers.
	class APInt {		class APInt {
	unsigned BitWidth; ///< The number of bits in this APInt.		unsigned BitWidth; ///< The number of bits in this APInt.
	/// This union is used to store the integer value. When the		/// This union is used to store the integer value. When the
	/// integer bit-width <= 64, it uses VAL, otherwise it uses pVal.		/// integer bit-width <= 64, it uses VAL, otherwise it uses pVal.
	union {		union {
	uint64_t VAL; ///< Used to store the <= 64 bits integer value.		uint64_t VAL; ///< Used to store the <= 64 bits integer value.
	uint64_t *pVal; ///< Used to store the >64 bits integer value.		uint64_t *pVal; ///< Used to store the >64 bits integer value.
	};		};
	/// This enum is used to hold the constants we needed for APInt.		/// This enum is used to hold the constants we needed for APInt.
	enum {		enum {
	/// Bits in a word		/// Bits in a word
	APINT_BITS_PER_WORD = static_cast<unsigned int>(sizeof(uint64_t)) *		APINT_BITS_PER_WORD =
	CHAR_BIT,		static_cast<unsigned int>(sizeof(uint64_t)) * CHAR_BIT,
	/// Byte size of a word		/// Byte size of a word
	APINT_WORD_SIZE = static_cast<unsigned int>(sizeof(uint64_t))		APINT_WORD_SIZE = static_cast<unsigned int>(sizeof(uint64_t))
	};		};
			/// \brief Fast internal constructor
			///
	/// This constructor is used only internally for speed of construction of		/// This constructor is used only internally for speed of construction of
	/// temporaries. It is unsafe for general use so it is not public.		/// temporaries. It is unsafe for general use so it is not public.
	/// @brief Fast internal constructor		APInt(uint64_t *val, unsigned bits) : BitWidth(bits), pVal(val) {}
	APInt(uint64_t* val, unsigned bits) : BitWidth(bits), pVal(val) { }
	/// @returns true if the number of bits <= 64, false otherwise.		/// \brief Determine if this APInt just has one word to store value.
	/// @brief Determine if this APInt just has one word to store value.		///
	bool isSingleWord() const {		/// \returns true if the number of bits <= 64, false otherwise.
	return BitWidth <= APINT_BITS_PER_WORD;		bool isSingleWord() const { return BitWidth <= APINT_BITS_PER_WORD; }
	}
	/// @returns the word position for the specified bit position.		/// \brief Determine which word a bit is in.
	/// @brief Determine which word a bit is in.		///
			/// \returns the word position for the specified bit position.
	static unsigned whichWord(unsigned bitPosition) {		static unsigned whichWord(unsigned bitPosition) {
	return bitPosition / APINT_BITS_PER_WORD;		return bitPosition / APINT_BITS_PER_WORD;
	}		}
	/// @returns the bit position in a word for the specified bit position		/// \brief Determine which bit in a word a bit is in.
			///
			/// \returns the bit position in a word for the specified bit position
	/// in the APInt.		/// in the APInt.
	/// @brief Determine which bit in a word a bit is in.
	static unsigned whichBit(unsigned bitPosition) {		static unsigned whichBit(unsigned bitPosition) {
	return bitPosition % APINT_BITS_PER_WORD;		return bitPosition % APINT_BITS_PER_WORD;
	}		}
			/// \brief Get a single bit mask.
			///
			/// \returns a uint64_t with only bit at "whichBit(bitPosition)" set
	/// This method generates and returns a uint64_t (word) mask for a single		/// This method generates and returns a uint64_t (word) mask for a single
	/// bit at a specific bit position. This is used to mask the bit in the		/// bit at a specific bit position. This is used to mask the bit in the
	/// corresponding word.		/// corresponding word.
	/// @returns a uint64_t with only bit at "whichBit(bitPosition)" set
	/// @brief Get a single bit mask.
	static uint64_t maskBit(unsigned bitPosition) {		static uint64_t maskBit(unsigned bitPosition) {
	return 1ULL << whichBit(bitPosition);		return 1ULL << whichBit(bitPosition);
	}		}
			/// \brief Clear unused high order bits
			///
	/// This method is used internally to clear the to "N" bits in the high o rder		/// This method is used internally to clear the to "N" bits in the high o rder
	/// word that are not used by the APInt. This is needed after the most		/// word that are not used by the APInt. This is needed after the most
	/// significant word is assigned a value to ensure that those bits are		/// significant word is assigned a value to ensure that those bits are
	/// zero'd out.		/// zero'd out.
	/// @brief Clear unused high order bits		APInt &clearUnusedBits() {
	APInt& clearUnusedBits() {
	// Compute how many bits are used in the final word		// Compute how many bits are used in the final word
	unsigned wordBits = BitWidth % APINT_BITS_PER_WORD;		unsigned wordBits = BitWidth % APINT_BITS_PER_WORD;
	if (wordBits == 0)		if (wordBits == 0)
	// If all bits are used, we want to leave the value alone. This also		// If all bits are used, we want to leave the value alone. This also
	// avoids the undefined behavior of >> when the shift is the same siz e as		// avoids the undefined behavior of >> when the shift is the same siz e as
	// the word size (64).		// the word size (64).
	return *this;		return *this;
	// Mask out the high bits.		// Mask out the high bits.
	uint64_t mask = ~uint64_t(0ULL) >> (APINT_BITS_PER_WORD - wordBits);		uint64_t mask = ~uint64_t(0ULL) >> (APINT_BITS_PER_WORD - wordBits);
	if (isSingleWord())		if (isSingleWord())
	VAL &= mask;		VAL &= mask;
	else		else
	pVal[getNumWords() - 1] &= mask;		pVal[getNumWords() - 1] &= mask;
	return *this;		return *this;
	}		}
	/// @returns the corresponding word for the specified bit position.		/// \brief Get the word corresponding to a bit position
	/// @brief Get the word corresponding to a bit position		/// \returns the corresponding word for the specified bit position.
	uint64_t getWord(unsigned bitPosition) const {		uint64_t getWord(unsigned bitPosition) const {
	return isSingleWord() ? VAL : pVal[whichWord(bitPosition)];		return isSingleWord() ? VAL : pVal[whichWord(bitPosition)];
	}		}
			/// \brief Convert a char array into an APInt
			///
			/// \param radix 2, 8, 10, 16, or 36
	/// Converts a string into a number. The string must be non-empty		/// Converts a string into a number. The string must be non-empty
	/// and well-formed as a number of the given base. The bit-width		/// and well-formed as a number of the given base. The bit-width
	/// must be sufficient to hold the result.		/// must be sufficient to hold the result.
	///		///
	/// This is used by the constructors that take string arguments.		/// This is used by the constructors that take string arguments.
	///		///
	/// StringRef::getAsInteger is superficially similar but (1) does		/// StringRef::getAsInteger is superficially similar but (1) does
	/// not assume that the string is well-formed and (2) grows the		/// not assume that the string is well-formed and (2) grows the
	/// result to hold the input.		/// result to hold the input.
	///
	/// @param radix 2, 8, 10, 16, or 36
	/// @brief Convert a char array into an APInt
	void fromString(unsigned numBits, StringRef str, uint8_t radix);		void fromString(unsigned numBits, StringRef str, uint8_t radix);
			/// \brief An internal division function for dividing APInts.
			///
	/// This is used by the toString method to divide by the radix. It simply		/// This is used by the toString method to divide by the radix. It simply
	/// provides a more convenient form of divide for internal use since Knut hDiv		/// provides a more convenient form of divide for internal use since Knut hDiv
	/// has specific constraints on its inputs. If those constraints are not met		/// has specific constraints on its inputs. If those constraints are not met
	/// then it provides a simpler form of divide.		/// then it provides a simpler form of divide.
	/// @brief An internal division function for dividing APInts.		static void divide(const APInt LHS, unsigned lhsWords, const APInt &RHS,
	static void divide(const APInt LHS, unsigned lhsWords,		unsigned rhsWords, APInt *Quotient, APInt *Remainder);
	const APInt &RHS, unsigned rhsWords,
	APInt *Quotient, APInt *Remainder);
	/// out-of-line slow case for inline constructor		/// out-of-line slow case for inline constructor
	void initSlowCase(unsigned numBits, uint64_t val, bool isSigned);		void initSlowCase(unsigned numBits, uint64_t val, bool isSigned);
	/// shared code between two array constructors		/// shared code between two array constructors
	void initFromArray(ArrayRef<uint64_t> array);		void initFromArray(ArrayRef<uint64_t> array);
	/// out-of-line slow case for inline copy constructor		/// out-of-line slow case for inline copy constructor
	void initSlowCase(const APInt& that);		void initSlowCase(const APInt &that);
	/// out-of-line slow case for shl		/// out-of-line slow case for shl
	APInt shlSlowCase(unsigned shiftAmt) const;		APInt shlSlowCase(unsigned shiftAmt) const;
	/// out-of-line slow case for operator&		/// out-of-line slow case for operator&
	APInt AndSlowCase(const APInt& RHS) const;		APInt AndSlowCase(const APInt &RHS) const;
	/// out-of-line slow case for operator|		/// out-of-line slow case for operator|
	APInt OrSlowCase(const APInt& RHS) const;		APInt OrSlowCase(const APInt &RHS) const;
	/// out-of-line slow case for operator^		/// out-of-line slow case for operator^
	APInt XorSlowCase(const APInt& RHS) const;		APInt XorSlowCase(const APInt &RHS) const;
	/// out-of-line slow case for operator=		/// out-of-line slow case for operator=
	APInt& AssignSlowCase(const APInt& RHS);		APInt &AssignSlowCase(const APInt &RHS);
	/// out-of-line slow case for operator==		/// out-of-line slow case for operator==
	bool EqualSlowCase(const APInt& RHS) const;		bool EqualSlowCase(const APInt &RHS) const;
	/// out-of-line slow case for operator==		/// out-of-line slow case for operator==
	bool EqualSlowCase(uint64_t Val) const;		bool EqualSlowCase(uint64_t Val) const;
	/// out-of-line slow case for countLeadingZeros		/// out-of-line slow case for countLeadingZeros
	unsigned countLeadingZerosSlowCase() const;		unsigned countLeadingZerosSlowCase() const;
	/// out-of-line slow case for countTrailingOnes		/// out-of-line slow case for countTrailingOnes
	unsigned countTrailingOnesSlowCase() const;		unsigned countTrailingOnesSlowCase() const;
	/// out-of-line slow case for countPopulation		/// out-of-line slow case for countPopulation
	unsigned countPopulationSlowCase() const;		unsigned countPopulationSlowCase() const;
	public:		public:
	/// @name Constructors		/// \name Constructors
	/// @{		/// @{
			/// \brief Create a new APInt of numBits width, initialized as val.
			///
	/// If isSigned is true then val is treated as if it were a signed value		/// If isSigned is true then val is treated as if it were a signed value
	/// (i.e. as an int64_t) and the appropriate sign extension to the bit wi dth		/// (i.e. as an int64_t) and the appropriate sign extension to the bit wi dth
	/// will be done. Otherwise, no sign extension occurs (high order bits be yond		/// will be done. Otherwise, no sign extension occurs (high order bits be yond
	/// the range of val are zero filled).		/// the range of val are zero filled).
	/// @param numBits the bit width of the constructed APInt		///
	/// @param val the initial value of the APInt		/// \param numBits the bit width of the constructed APInt
	/// @param isSigned how to treat signedness of val		/// \param val the initial value of the APInt
	/// @brief Create a new APInt of numBits width, initialized as val.		/// \param isSigned how to treat signedness of val
	APInt(unsigned numBits, uint64_t val, bool isSigned = false)		APInt(unsigned numBits, uint64_t val, bool isSigned = false)
	: BitWidth(numBits), VAL(0) {		: BitWidth(numBits), VAL(0) {
	assert(BitWidth && "bitwidth too small");		assert(BitWidth && "bitwidth too small");
	if (isSingleWord())		if (isSingleWord())
	VAL = val;		VAL = val;
	else		else
	initSlowCase(numBits, val, isSigned);		initSlowCase(numBits, val, isSigned);
	clearUnusedBits();		clearUnusedBits();
	}		}
			/// \brief Construct an APInt of numBits width, initialized as bigVal[].
			///
	/// Note that bigVal.size() can be smaller or larger than the correspondi ng		/// Note that bigVal.size() can be smaller or larger than the correspondi ng
	/// bit width but any extraneous bits will be dropped.		/// bit width but any extraneous bits will be dropped.
	/// @param numBits the bit width of the constructed APInt		///
	/// @param bigVal a sequence of words to form the initial value of the AP		/// \param numBits the bit width of the constructed APInt
	Int		/// \param bigVal a sequence of words to form the initial value of the AP
	/// @brief Construct an APInt of numBits width, initialized as bigVal[].		Int
	APInt(unsigned numBits, ArrayRef<uint64_t> bigVal);		APInt(unsigned numBits, ArrayRef<uint64_t> bigVal);
	/// Equivalent to APInt(numBits, ArrayRef<uint64_t>(bigVal, numWords)), b ut		/// Equivalent to APInt(numBits, ArrayRef<uint64_t>(bigVal, numWords)), b ut
	/// deprecated because this constructor is prone to ambiguity with the		/// deprecated because this constructor is prone to ambiguity with the
	/// APInt(unsigned, uint64_t, bool) constructor.		/// APInt(unsigned, uint64_t, bool) constructor.
	///		///
	/// If this overload is ever deleted, care should be taken to prevent cal ls		/// If this overload is ever deleted, care should be taken to prevent cal ls
	/// from being incorrectly captured by the APInt(unsigned, uint64_t, bool )		/// from being incorrectly captured by the APInt(unsigned, uint64_t, bool )
	/// constructor.		/// constructor.
	APInt(unsigned numBits, unsigned numWords, const uint64_t bigVal[]);		APInt(unsigned numBits, unsigned numWords, const uint64_t bigVal[]);
			/// \brief Construct an APInt from a string representation.
			///
	/// This constructor interprets the string \p str in the given radix. The		/// This constructor interprets the string \p str in the given radix. The
	/// interpretation stops when the first character that is not suitable fo r the		/// interpretation stops when the first character that is not suitable fo r the
	/// radix is encountered, or the end of the string. Acceptable radix valu es		/// radix is encountered, or the end of the string. Acceptable radix valu es
	/// are 2, 8, 10, 16, and 36. It is an error for the value implied by the		/// are 2, 8, 10, 16, and 36. It is an error for the value implied by the
	/// string to require more bits than numBits.		/// string to require more bits than numBits.
	///		///
	/// @param numBits the bit width of the constructed APInt		/// \param numBits the bit width of the constructed APInt
	/// @param str the string to be interpreted		/// \param str the string to be interpreted
	/// @param radix the radix to use for the conversion		/// \param radix the radix to use for the conversion
	/// @brief Construct an APInt from a string representation.
	APInt(unsigned numBits, StringRef str, uint8_t radix);		APInt(unsigned numBits, StringRef str, uint8_t radix);
	/// Simply makes *this a copy of that.		/// Simply makes *this a copy of that.
	/// @brief Copy Constructor.		/// @brief Copy Constructor.
	APInt(const APInt& that)		APInt(const APInt &that) : BitWidth(that.BitWidth), VAL(0) {
	: BitWidth(that.BitWidth), VAL(0) {
	assert(BitWidth && "bitwidth too small");		assert(BitWidth && "bitwidth too small");
	if (isSingleWord())		if (isSingleWord())
	VAL = that.VAL;		VAL = that.VAL;
	else		else
	initSlowCase(that);		initSlowCase(that);
	}		}
	#if LLVM_HAS_RVALUE_REFERENCES		#if LLVM_HAS_RVALUE_REFERENCES
	/// @brief Move Constructor.		/// \brief Move Constructor.
	APInt(APInt&& that) : BitWidth(that.BitWidth), VAL(that.VAL) {		APInt(APInt &&that) : BitWidth(that.BitWidth), VAL(that.VAL) {
	that.BitWidth = 0;		that.BitWidth = 0;
	}		}
	#endif		#endif
	/// @brief Destructor.		/// \brief Destructor.
	~APInt() {		~APInt() {
	if (!isSingleWord())		if (needsCleanup())
	delete [] pVal;		delete[] pVal;
	}		}
	/// Default constructor that creates an uninitialized APInt. This is use		/// \brief Default constructor that creates an uninitialized APInt.
	ful		///
	/// for object deserialization (pair this with the static method Read).		/// This is useful for object deserialization (pair this with the static
			/// method Read).
	explicit APInt() : BitWidth(1) {}		explicit APInt() : BitWidth(1) {}
	/// Profile - Used to insert APInt objects, or objects that contain APInt		/// \brief Returns whether this instance allocated memory.
	/// objects, into FoldingSets.		bool needsCleanup() const { return !isSingleWord(); }
	void Profile(FoldingSetNodeID& id) const;
			/// Used to insert APInt objects, or objects that contain APInt objects,
			into
			/// FoldingSets.
			void Profile(FoldingSetNodeID &id) const;
	/// @}		/// @}
	/// @name Value Tests		/// \name Value Tests
	/// @{		/// @{
			/// \brief Determine sign of this APInt.
			///
	/// This tests the high bit of this APInt to determine if it is set.		/// This tests the high bit of this APInt to determine if it is set.
	/// @returns true if this APInt is negative, false otherwise		///
	/// @brief Determine sign of this APInt.		/// \returns true if this APInt is negative, false otherwise
	bool isNegative() const {		bool isNegative() const { return (*this)[BitWidth - 1]; }
	return (*this)[BitWidth - 1];
	}
			/// \brief Determine if this APInt Value is non-negative (>= 0)
			///
	/// This tests the high bit of the APInt to determine if it is unset.		/// This tests the high bit of the APInt to determine if it is unset.
	/// @brief Determine if this APInt Value is non-negative (>= 0)		bool isNonNegative() const { return !isNegative(); }
	bool isNonNegative() const {
	return !isNegative();
	}
			/// \brief Determine if this APInt Value is positive.
			///
	/// This tests if the value of this APInt is positive (> 0). Note		/// This tests if the value of this APInt is positive (> 0). Note
	/// that 0 is not a positive value.		/// that 0 is not a positive value.
	/// @returns true if this APInt is positive.		///
	/// @brief Determine if this APInt Value is positive.		/// \returns true if this APInt is positive.
	bool isStrictlyPositive() const {		bool isStrictlyPositive() const { return isNonNegative() && !!*this; }
	return isNonNegative() && !!*this;
	}
			/// \brief Determine if all bits are set
			///
	/// This checks to see if the value has all bits of the APInt are set or not.		/// This checks to see if the value has all bits of the APInt are set or not.
	/// @brief Determine if all bits are set
	bool isAllOnesValue() const {		bool isAllOnesValue() const {
	return countPopulation() == BitWidth;		if (isSingleWord())
			return VAL == ~integerPart(0) >> (APINT_BITS_PER_WORD - BitWidth);
			return countPopulationSlowCase() == BitWidth;
	}		}
			/// \brief Determine if this is the largest unsigned value.
			///
	/// This checks to see if the value of this APInt is the maximum unsigned		/// This checks to see if the value of this APInt is the maximum unsigned
	/// value for the APInt's bit width.		/// value for the APInt's bit width.
	/// @brief Determine if this is the largest unsigned value.		bool isMaxValue() const { return isAllOnesValue(); }
	bool isMaxValue() const {
	return countPopulation() == BitWidth;
	}
			/// \brief Determine if this is the largest signed value.
			///
	/// This checks to see if the value of this APInt is the maximum signed		/// This checks to see if the value of this APInt is the maximum signed
	/// value for the APInt's bit width.		/// value for the APInt's bit width.
	/// @brief Determine if this is the largest signed value.
	bool isMaxSignedValue() const {		bool isMaxSignedValue() const {
	return BitWidth == 1 ? VAL == 0 :		return BitWidth == 1 ? VAL == 0
	!isNegative() && countPopulation() == BitWidth -		: !isNegative() && countPopulation() == BitWidth -
	1;		1;
	}		}
			/// \brief Determine if this is the smallest unsigned value.
			///
	/// This checks to see if the value of this APInt is the minimum unsigned		/// This checks to see if the value of this APInt is the minimum unsigned
	/// value for the APInt's bit width.		/// value for the APInt's bit width.
	/// @brief Determine if this is the smallest unsigned value.		bool isMinValue() const { return !*this; }
	bool isMinValue() const {
	return !*this;
	}
			/// \brief Determine if this is the smallest signed value.
			///
	/// This checks to see if the value of this APInt is the minimum signed		/// This checks to see if the value of this APInt is the minimum signed
	/// value for the APInt's bit width.		/// value for the APInt's bit width.
	/// @brief Determine if this is the smallest signed value.
	bool isMinSignedValue() const {		bool isMinSignedValue() const {
	return BitWidth == 1 ? VAL == 1 : isNegative() && isPowerOf2();		return BitWidth == 1 ? VAL == 1 : isNegative() && isPowerOf2();
	}		}
	/// @brief Check if this APInt has an N-bits unsigned integer value.		/// \brief Check if this APInt has an N-bits unsigned integer value.
	bool isIntN(unsigned N) const {		bool isIntN(unsigned N) const {
	assert(N && "N == 0 ???");		assert(N && "N == 0 ???");
	return getActiveBits() <= N;		return getActiveBits() <= N;
	}		}
	/// @brief Check if this APInt has an N-bits signed integer value.		/// \brief Check if this APInt has an N-bits signed integer value.
	bool isSignedIntN(unsigned N) const {		bool isSignedIntN(unsigned N) const {
	assert(N && "N == 0 ???");		assert(N && "N == 0 ???");
	return getMinSignedBits() <= N;		return getMinSignedBits() <= N;
	}		}
	/// @returns true if the argument APInt value is a power of two > 0.		/// \brief Check if this APInt's value is a power of two greater than zer
			o.
			///
			/// \returns true if the argument APInt value is a power of two > 0.
	bool isPowerOf2() const {		bool isPowerOf2() const {
	if (isSingleWord())		if (isSingleWord())
	return isPowerOf2_64(VAL);		return isPowerOf2_64(VAL);
	return countPopulationSlowCase() == 1;		return countPopulationSlowCase() == 1;
	}		}
	/// isSignBit - Return true if this is the value returned by getSignBit.		/// \brief Check if the APInt's value is returned by getSignBit.
			///
			/// \returns true if this is the value returned by getSignBit.
	bool isSignBit() const { return isMinSignedValue(); }		bool isSignBit() const { return isMinSignedValue(); }
			/// \brief Convert APInt to a boolean value.
			///
	/// This converts the APInt to a boolean value as a test against zero.		/// This converts the APInt to a boolean value as a test against zero.
	/// @brief Boolean conversion function.		bool getBoolValue() const { return !!*this; }
	bool getBoolValue() const {
	return !!*this;
	}
	/// getLimitedValue - If this value is smaller than the specified limit,		/// If this value is smaller than the specified limit, return it, otherwi
	/// return it, otherwise return the limit value. This causes the value		se
	/// to saturate to the limit.		/// return the limit value. This causes the value to saturate to the lim
			it.
	uint64_t getLimitedValue(uint64_t Limit = ~0ULL) const {		uint64_t getLimitedValue(uint64_t Limit = ~0ULL) const {
	return (getActiveBits() > 64 || getZExtValue() > Limit) ?		return (getActiveBits() > 64 || getZExtValue() > Limit) ? Limit
	Limit : getZExtValue();		: getZExtValue(
			);
	}		}
	/// @}		/// @}
	/// @name Value Generators		/// \name Value Generators
	/// @{		/// @{
	/// @brief Gets maximum unsigned value of APInt for specific bit width.
			/// \brief Gets maximum unsigned value of APInt for specific bit width.
	static APInt getMaxValue(unsigned numBits) {		static APInt getMaxValue(unsigned numBits) {
	return getAllOnesValue(numBits);		return getAllOnesValue(numBits);
	}		}
	/// @brief Gets maximum signed value of APInt for a specific bit width.		/// \brief Gets maximum signed value of APInt for a specific bit width.
	static APInt getSignedMaxValue(unsigned numBits) {		static APInt getSignedMaxValue(unsigned numBits) {
	APInt API = getAllOnesValue(numBits);		APInt API = getAllOnesValue(numBits);
	API.clearBit(numBits - 1);		API.clearBit(numBits - 1);
	return API;		return API;
	}		}
	/// @brief Gets minimum unsigned value of APInt for a specific bit width.		/// \brief Gets minimum unsigned value of APInt for a specific bit width.
	static APInt getMinValue(unsigned numBits) {		static APInt getMinValue(unsigned numBits) { return APInt(numBits, 0); }
	return APInt(numBits, 0);
	}
	/// @brief Gets minimum signed value of APInt for a specific bit width.		/// \brief Gets minimum signed value of APInt for a specific bit width.
	static APInt getSignedMinValue(unsigned numBits) {		static APInt getSignedMinValue(unsigned numBits) {
	APInt API(numBits, 0);		APInt API(numBits, 0);
	API.setBit(numBits - 1);		API.setBit(numBits - 1);
	return API;		return API;
	}		}
	/// getSignBit - This is just a wrapper function of getSignedMinValue(),		/// \brief Get the SignBit for a specific bit width.
	and		///
	/// it helps code readability when we want to get a SignBit.		/// This is just a wrapper function of getSignedMinValue(), and it helps
	/// @brief Get the SignBit for a specific bit width.		code
			/// readability when we want to get a SignBit.
	static APInt getSignBit(unsigned BitWidth) {		static APInt getSignBit(unsigned BitWidth) {
	return getSignedMinValue(BitWidth);		return getSignedMinValue(BitWidth);
	}		}
	/// @returns the all-ones value for an APInt of the specified bit-width.		/// \brief Get the all-ones value.
	/// @brief Get the all-ones value.		///
			/// \returns the all-ones value for an APInt of the specified bit-width.
	static APInt getAllOnesValue(unsigned numBits) {		static APInt getAllOnesValue(unsigned numBits) {
	return APInt(numBits, UINT64_MAX, true);		return APInt(numBits, UINT64_MAX, true);
	}		}
	/// @returns the '0' value for an APInt of the specified bit-width.		/// \brief Get the '0' value.
	/// @brief Get the '0' value.		///
	static APInt getNullValue(unsigned numBits) {		/// \returns the '0' value for an APInt of the specified bit-width.
	return APInt(numBits, 0);		static APInt getNullValue(unsigned numBits) { return APInt(numBits, 0); }
	}
			/// \brief Compute an APInt containing numBits highbits from this APInt.
			///
	/// Get an APInt with the same BitWidth as this APInt, just zero mask		/// Get an APInt with the same BitWidth as this APInt, just zero mask
	/// the low bits and right shift to the least significant bit.		/// the low bits and right shift to the least significant bit.
	/// @returns the high "numBits" bits of this APInt.		///
			/// \returns the high "numBits" bits of this APInt.
	APInt getHiBits(unsigned numBits) const;		APInt getHiBits(unsigned numBits) const;
			/// \brief Compute an APInt containing numBits lowbits from this APInt.
			///
	/// Get an APInt with the same BitWidth as this APInt, just zero mask		/// Get an APInt with the same BitWidth as this APInt, just zero mask
	/// the high bits.		/// the high bits.
	/// @returns the low "numBits" bits of this APInt.		///
			/// \returns the low "numBits" bits of this APInt.
	APInt getLoBits(unsigned numBits) const;		APInt getLoBits(unsigned numBits) const;
	/// getOneBitSet - Return an APInt with exactly one bit set in the result .		/// \brief Return an APInt with exactly one bit set in the result.
	static APInt getOneBitSet(unsigned numBits, unsigned BitNo) {		static APInt getOneBitSet(unsigned numBits, unsigned BitNo) {
	APInt Res(numBits, 0);		APInt Res(numBits, 0);
	Res.setBit(BitNo);		Res.setBit(BitNo);
	return Res;		return Res;
	}		}
			/// \brief Get a value with a block of bits set.
			///
	/// Constructs an APInt value that has a contiguous range of bits set. Th e		/// Constructs an APInt value that has a contiguous range of bits set. Th e
	/// bits from loBit (inclusive) to hiBit (exclusive) will be set. All oth er		/// bits from loBit (inclusive) to hiBit (exclusive) will be set. All oth er
	/// bits will be zero. For example, with parameters(32, 0, 16) you would get		/// bits will be zero. For example, with parameters(32, 0, 16) you would get
	/// 0x0000FFFF. If hiBit is less than loBit then the set bits "wrap". For		/// 0x0000FFFF. If hiBit is less than loBit then the set bits "wrap". For
	/// example, with parameters (32, 28, 4), you would get 0xF000000F.		/// example, with parameters (32, 28, 4), you would get 0xF000000F.
	/// @param numBits the intended bit width of the result		///
	/// @param loBit the index of the lowest bit set.		/// \param numBits the intended bit width of the result
	/// @param hiBit the index of the highest bit set.		/// \param loBit the index of the lowest bit set.
	/// @returns An APInt value with the requested bits set.		/// \param hiBit the index of the highest bit set.
	/// @brief Get a value with a block of bits set.		///
			/// \returns An APInt value with the requested bits set.
	static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit) {		static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit) {
	assert(hiBit <= numBits && "hiBit out of range");		assert(hiBit <= numBits && "hiBit out of range");
	assert(loBit < numBits && "loBit out of range");		assert(loBit < numBits && "loBit out of range");
	if (hiBit < loBit)		if (hiBit < loBit)
	return getLowBitsSet(numBits, hiBit) |		return getLowBitsSet(numBits, hiBit) |
	getHighBitsSet(numBits, numBits-loBit);		getHighBitsSet(numBits, numBits - loBit);
	return getLowBitsSet(numBits, hiBit-loBit).shl(loBit);		return getLowBitsSet(numBits, hiBit - loBit).shl(loBit);
	}		}
			/// \brief Get a value with high bits set
			///
	/// Constructs an APInt value that has the top hiBitsSet bits set.		/// Constructs an APInt value that has the top hiBitsSet bits set.
	/// @param numBits the bitwidth of the result		///
	/// @param hiBitsSet the number of high-order bits set in the result.		/// \param numBits the bitwidth of the result
	/// @brief Get a value with high bits set		/// \param hiBitsSet the number of high-order bits set in the result.
	static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet) {		static APInt getHighBitsSet(unsigned numBits, unsigned hiBitsSet) {
	assert(hiBitsSet <= numBits && "Too many bits to set!");		assert(hiBitsSet <= numBits && "Too many bits to set!");
	// Handle a degenerate case, to avoid shifting by word size		// Handle a degenerate case, to avoid shifting by word size
	if (hiBitsSet == 0)		if (hiBitsSet == 0)
	return APInt(numBits, 0);		return APInt(numBits, 0);
	unsigned shiftAmt = numBits - hiBitsSet;		unsigned shiftAmt = numBits - hiBitsSet;
	// For small values, return quickly		// For small values, return quickly
	if (numBits <= APINT_BITS_PER_WORD)		if (numBits <= APINT_BITS_PER_WORD)
	return APInt(numBits, ~0ULL << shiftAmt);		return APInt(numBits, ~0ULL << shiftAmt);
	return getAllOnesValue(numBits).shl(shiftAmt);		return getAllOnesValue(numBits).shl(shiftAmt);
	}		}
			/// \brief Get a value with low bits set
			///
	/// Constructs an APInt value that has the bottom loBitsSet bits set.		/// Constructs an APInt value that has the bottom loBitsSet bits set.
	/// @param numBits the bitwidth of the result		///
	/// @param loBitsSet the number of low-order bits set in the result.		/// \param numBits the bitwidth of the result
	/// @brief Get a value with low bits set		/// \param loBitsSet the number of low-order bits set in the result.
	static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet) {		static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet) {
	assert(loBitsSet <= numBits && "Too many bits to set!");		assert(loBitsSet <= numBits && "Too many bits to set!");
	// Handle a degenerate case, to avoid shifting by word size		// Handle a degenerate case, to avoid shifting by word size
	if (loBitsSet == 0)		if (loBitsSet == 0)
	return APInt(numBits, 0);		return APInt(numBits, 0);
	if (loBitsSet == APINT_BITS_PER_WORD)		if (loBitsSet == APINT_BITS_PER_WORD)
	return APInt(numBits, UINT64_MAX);		return APInt(numBits, UINT64_MAX);
	// For small values, return quickly.		// For small values, return quickly.
	if (loBitsSet <= APINT_BITS_PER_WORD)		if (loBitsSet <= APINT_BITS_PER_WORD)
	return APInt(numBits, UINT64_MAX >> (APINT_BITS_PER_WORD - loBitsSet) );		return APInt(numBits, UINT64_MAX >> (APINT_BITS_PER_WORD - loBitsSet) );
	skipping to change at line 537		skipping to change at line 570
	return I1.zext(I2.getBitWidth()) == I2;		return I1.zext(I2.getBitWidth()) == I2;
	}		}
	/// \brief Overload to compute a hash_code for an APInt value.		/// \brief Overload to compute a hash_code for an APInt value.
	friend hash_code hash_value(const APInt &Arg);		friend hash_code hash_value(const APInt &Arg);
	/// This function returns a pointer to the internal storage of the APInt.		/// This function returns a pointer to the internal storage of the APInt.
	/// This is useful for writing out the APInt in binary form without any		/// This is useful for writing out the APInt in binary form without any
	/// conversions.		/// conversions.
	const uint64_t* getRawData() const {		const uint64_t *getRawData() const {
	if (isSingleWord())		if (isSingleWord())
	return &VAL;		return &VAL;
	return &pVal[0];		return &pVal[0];
	}		}
	/// @}		/// @}
	/// @name Unary Operators		/// \name Unary Operators
	/// @{		/// @{
	/// @returns a new APInt value representing *this incremented by one
	/// @brief Postfix increment operator.		/// \brief Postfix increment operator.
			///
			/// \returns a new APInt value representing *this incremented by one
	const APInt operator++(int) {		const APInt operator++(int) {
	APInt API(*this);		APInt API(*this);
	++(*this);		++(*this);
	return API;		return API;
	}		}
	/// @returns *this incremented by one		/// \brief Prefix increment operator.
	/// @brief Prefix increment operator.		///
	APInt& operator++();		/// \returns *this incremented by one
			APInt &operator++();
	/// @returns a new APInt representing *this decremented by one.		/// \brief Postfix decrement operator.
	/// @brief Postfix decrement operator.		///
			/// \returns a new APInt representing *this decremented by one.
	const APInt operator--(int) {		const APInt operator--(int) {
	APInt API(*this);		APInt API(*this);
	--(*this);		--(*this);
	return API;		return API;
	}		}
	/// @returns *this decremented by one.		/// \brief Prefix decrement operator.
	/// @brief Prefix decrement operator.		///
	APInt& operator--();		/// \returns *this decremented by one.
			APInt &operator--();
			/// \brief Unary bitwise complement operator.
			///
	/// Performs a bitwise complement operation on this APInt.		/// Performs a bitwise complement operation on this APInt.
	/// @returns an APInt that is the bitwise complement of *this		///
	/// @brief Unary bitwise complement operator.		/// \returns an APInt that is the bitwise complement of *this
	APInt operator~() const {		APInt operator~() const {
	APInt Result(*this);		APInt Result(*this);
	Result.flipAllBits();		Result.flipAllBits();
	return Result;		return Result;
	}		}
			/// \brief Unary negation operator
			///
	/// Negates *this using two's complement logic.		/// Negates *this using two's complement logic.
	/// @returns An APInt value representing the negation of *this.		///
	/// @brief Unary negation operator		/// \returns An APInt value representing the negation of *this.
	APInt operator-() const {		APInt operator-() const { return APInt(BitWidth, 0) - (*this); }
	return APInt(BitWidth, 0) - (*this);
	}
			/// \brief Logical negation operator.
			///
	/// Performs logical negation operation on this APInt.		/// Performs logical negation operation on this APInt.
	/// @returns true if *this is zero, false otherwise.		///
	/// @brief Logical negation operator.		/// \returns true if *this is zero, false otherwise.
	bool operator!() const {		bool operator!() const {
	if (isSingleWord())		if (isSingleWord())
	return !VAL;		return !VAL;
	for (unsigned i = 0; i != getNumWords(); ++i)		for (unsigned i = 0; i != getNumWords(); ++i)
	if (pVal[i])		if (pVal[i])
	return false;		return false;
	return true;		return true;
	}		}
	/// @}		/// @}
	/// @name Assignment Operators		/// \name Assignment Operators
	/// @{		/// @{
	/// @returns *this after assignment of RHS.
	/// @brief Copy assignment operator.		/// \brief Copy assignment operator.
	APInt& operator=(const APInt& RHS) {		///
			/// \returns *this after assignment of RHS.
			APInt &operator=(const APInt &RHS) {
	// If the bitwidths are the same, we can avoid mucking with memory		// If the bitwidths are the same, we can avoid mucking with memory
	if (isSingleWord() && RHS.isSingleWord()) {		if (isSingleWord() && RHS.isSingleWord()) {
	VAL = RHS.VAL;		VAL = RHS.VAL;
	BitWidth = RHS.BitWidth;		BitWidth = RHS.BitWidth;
	return clearUnusedBits();		return clearUnusedBits();
	}		}
	return AssignSlowCase(RHS);		return AssignSlowCase(RHS);
	}		}
	#if LLVM_HAS_RVALUE_REFERENCES		#if LLVM_HAS_RVALUE_REFERENCES
	/// @brief Move assignment operator.		/// @brief Move assignment operator.
	APInt& operator=(APInt&& that) {		APInt &operator=(APInt &&that) {
	if (!isSingleWord())		if (!isSingleWord())
	delete [] pVal;		delete[] pVal;
	BitWidth = that.BitWidth;		BitWidth = that.BitWidth;
	VAL = that.VAL;		VAL = that.VAL;
	that.BitWidth = 0;		that.BitWidth = 0;
	return *this;		return *this;
	}		}
	#endif		#endif
			/// \brief Assignment operator.
			///
	/// The RHS value is assigned to *this. If the significant bits in RHS ex ceed		/// The RHS value is assigned to *this. If the significant bits in RHS ex ceed
	/// the bit width, the excess bits are truncated. If the bit width is lar ger		/// the bit width, the excess bits are truncated. If the bit width is lar ger
	/// than 64, the value is zero filled in the unspecified high order bits.		/// than 64, the value is zero filled in the unspecified high order bits.
	/// @returns *this after assignment of RHS value.		///
	/// @brief Assignment operator.		/// \returns *this after assignment of RHS value.
	APInt& operator=(uint64_t RHS);		APInt &operator=(uint64_t RHS);
			/// \brief Bitwise AND assignment operator.
			///
	/// Performs a bitwise AND operation on this APInt and RHS. The result is		/// Performs a bitwise AND operation on this APInt and RHS. The result is
	/// assigned to *this.		/// assigned to *this.
	/// @returns *this after ANDing with RHS.		///
	/// @brief Bitwise AND assignment operator.		/// \returns *this after ANDing with RHS.
	APInt& operator&=(const APInt& RHS);		APInt &operator&=(const APInt &RHS);
			/// \brief Bitwise OR assignment operator.
			///
	/// Performs a bitwise OR operation on this APInt and RHS. The result is		/// Performs a bitwise OR operation on this APInt and RHS. The result is
	/// assigned *this;		/// assigned *this;
	/// @returns *this after ORing with RHS.		///
	/// @brief Bitwise OR assignment operator.		/// \returns *this after ORing with RHS.
	APInt& operator|=(const APInt& RHS);		APInt &operator|=(const APInt &RHS);
			/// \brief Bitwise OR assignment operator.
			///
	/// Performs a bitwise OR operation on this APInt and RHS. RHS is		/// Performs a bitwise OR operation on this APInt and RHS. RHS is
	/// logically zero-extended or truncated to match the bit-width of		/// logically zero-extended or truncated to match the bit-width of
	/// the LHS.		/// the LHS.
	///		APInt &operator|=(uint64_t RHS) {
	/// @brief Bitwise OR assignment operator.
	APInt& operator|=(uint64_t RHS) {
	if (isSingleWord()) {		if (isSingleWord()) {
	VAL |= RHS;		VAL |= RHS;
	clearUnusedBits();		clearUnusedBits();
	} else {		} else {
	pVal[0] |= RHS;		pVal[0] |= RHS;
	}		}
	return *this;		return *this;
	}		}
			/// \brief Bitwise XOR assignment operator.
			///
	/// Performs a bitwise XOR operation on this APInt and RHS. The result is		/// Performs a bitwise XOR operation on this APInt and RHS. The result is
	/// assigned to *this.		/// assigned to *this.
	/// @returns *this after XORing with RHS.		///
	/// @brief Bitwise XOR assignment operator.		/// \returns *this after XORing with RHS.
	APInt& operator^=(const APInt& RHS);		APInt &operator^=(const APInt &RHS);
			/// \brief Multiplication assignment operator.
			///
	/// Multiplies this APInt by RHS and assigns the result to *this.		/// Multiplies this APInt by RHS and assigns the result to *this.
	/// @returns *this		///
	/// @brief Multiplication assignment operator.		/// \returns *this
	APInt& operator*=(const APInt& RHS);		APInt &operator*=(const APInt &RHS);
			/// \brief Addition assignment operator.
			///
	/// Adds RHS to *this and assigns the result to *this.		/// Adds RHS to *this and assigns the result to *this.
	/// @returns *this		///
	/// @brief Addition assignment operator.		/// \returns *this
	APInt& operator+=(const APInt& RHS);		APInt &operator+=(const APInt &RHS);
			/// \brief Subtraction assignment operator.
			///
	/// Subtracts RHS from *this and assigns the result to *this.		/// Subtracts RHS from *this and assigns the result to *this.
	/// @returns *this		///
	/// @brief Subtraction assignment operator.		/// \returns *this
	APInt& operator-=(const APInt& RHS);		APInt &operator-=(const APInt &RHS);
			/// \brief Left-shift assignment function.
			///
	/// Shifts *this left by shiftAmt and assigns the result to *this.		/// Shifts *this left by shiftAmt and assigns the result to *this.
	/// @returns *this after shifting left by shiftAmt		///
	/// @brief Left-shift assignment function.		/// \returns *this after shifting left by shiftAmt
	APInt& operator<<=(unsigned shiftAmt) {		APInt &operator<<=(unsigned shiftAmt) {
	*this = shl(shiftAmt);		*this = shl(shiftAmt);
	return *this;		return *this;
	}		}
	/// @}		/// @}
	/// @name Binary Operators		/// \name Binary Operators
	/// @{		/// @{
			/// \brief Bitwise AND operator.
			///
	/// Performs a bitwise AND operation on *this and RHS.		/// Performs a bitwise AND operation on *this and RHS.
	/// @returns An APInt value representing the bitwise AND of *this and RHS		///
	.		/// \returns An APInt value representing the bitwise AND of *this and RHS
	/// @brief Bitwise AND operator.		.
	APInt operator&(const APInt& RHS) const {		APInt operator&(const APInt &RHS) const {
	assert(BitWidth == RHS.BitWidth && "Bit widths must be the same");		assert(BitWidth == RHS.BitWidth && "Bit widths must be the same");
	if (isSingleWord())		if (isSingleWord())
	return APInt(getBitWidth(), VAL & RHS.VAL);		return APInt(getBitWidth(), VAL & RHS.VAL);
	return AndSlowCase(RHS);		return AndSlowCase(RHS);
	}		}
	APInt And(const APInt& RHS) const {		APInt LLVM_ATTRIBUTE_UNUSED_RESULT And(const APInt &RHS) const {
	return this->operator&(RHS);		return this->operator&(RHS);
	}		}
			/// \brief Bitwise OR operator.
			///
	/// Performs a bitwise OR operation on *this and RHS.		/// Performs a bitwise OR operation on *this and RHS.
	/// @returns An APInt value representing the bitwise OR of *this and RHS.		///
	/// @brief Bitwise OR operator.		/// \returns An APInt value representing the bitwise OR of *this and RHS.
	APInt operator|(const APInt& RHS) const {		APInt operator|(const APInt &RHS) const {
	assert(BitWidth == RHS.BitWidth && "Bit widths must be the same");		assert(BitWidth == RHS.BitWidth && "Bit widths must be the same");
	if (isSingleWord())		if (isSingleWord())
	return APInt(getBitWidth(), VAL | RHS.VAL);		return APInt(getBitWidth(), VAL | RHS.VAL);
	return OrSlowCase(RHS);		return OrSlowCase(RHS);
	}		}
	APInt Or(const APInt& RHS) const {
			/// \brief Bitwise OR function.
			///
			/// Performs a bitwise or on *this and RHS. This is implemented bny simpl
			y
			/// calling operator|.
			///
			/// \returns An APInt value representing the bitwise OR of *this and RHS.
			APInt LLVM_ATTRIBUTE_UNUSED_RESULT Or(const APInt &RHS) const {
	return this->operator|(RHS);		return this->operator|(RHS);
	}		}
			/// \brief Bitwise XOR operator.
			///
	/// Performs a bitwise XOR operation on *this and RHS.		/// Performs a bitwise XOR operation on *this and RHS.
	/// @returns An APInt value representing the bitwise XOR of *this and RHS		///
	.		/// \returns An APInt value representing the bitwise XOR of *this and RHS
	/// @brief Bitwise XOR operator.		.
	APInt operator^(const APInt& RHS) const {		APInt operator^(const APInt &RHS) const {
	assert(BitWidth == RHS.BitWidth && "Bit widths must be the same");		assert(BitWidth == RHS.BitWidth && "Bit widths must be the same");
	if (isSingleWord())		if (isSingleWord())
	return APInt(BitWidth, VAL ^ RHS.VAL);		return APInt(BitWidth, VAL ^ RHS.VAL);
	return XorSlowCase(RHS);		return XorSlowCase(RHS);
	}		}
	APInt Xor(const APInt& RHS) const {
			/// \brief Bitwise XOR function.
			///
			/// Performs a bitwise XOR operation on *this and RHS. This is implemente
			d
			/// through the usage of operator^.
			///
			/// \returns An APInt value representing the bitwise XOR of *this and RHS
			.
			APInt LLVM_ATTRIBUTE_UNUSED_RESULT Xor(const APInt &RHS) const {
	return this->operator^(RHS);		return this->operator^(RHS);
	}		}
			/// \brief Multiplication operator.
			///
	/// Multiplies this APInt by RHS and returns the result.		/// Multiplies this APInt by RHS and returns the result.
	/// @brief Multiplication operator.		APInt operator*(const APInt &RHS) const;
	APInt operator*(const APInt& RHS) const;
			/// \brief Addition operator.
			///
	/// Adds RHS to this APInt and returns the result.		/// Adds RHS to this APInt and returns the result.
	/// @brief Addition operator.		APInt operator+(const APInt &RHS) const;
	APInt operator+(const APInt& RHS) const;		APInt operator+(uint64_t RHS) const { return (*this) + APInt(BitWidth, RH
	APInt operator+(uint64_t RHS) const {		S); }
	return (*this) + APInt(BitWidth, RHS);
	}
			/// \brief Subtraction operator.
			///
	/// Subtracts RHS from this APInt and returns the result.		/// Subtracts RHS from this APInt and returns the result.
	/// @brief Subtraction operator.		APInt operator-(const APInt &RHS) const;
	APInt operator-(const APInt& RHS) const;		APInt operator-(uint64_t RHS) const { return (*this) - APInt(BitWidth, RH
	APInt operator-(uint64_t RHS) const {		S); }
	return (*this) - APInt(BitWidth, RHS);
	}
	APInt operator<<(unsigned Bits) const {		/// \brief Left logical shift operator.
	return shl(Bits);		///
	}		/// Shifts this APInt left by \p Bits and returns the result.
			APInt operator<<(unsigned Bits) const { return shl(Bits); }
	APInt operator<<(const APInt &Bits) const {		/// \brief Left logical shift operator.
	return shl(Bits);		///
	}		/// Shifts this APInt left by \p Bits and returns the result.
			APInt operator<<(const APInt &Bits) const { return shl(Bits); }
			/// \brief Arithmetic right-shift function.
			///
	/// Arithmetic right-shift this APInt by shiftAmt.		/// Arithmetic right-shift this APInt by shiftAmt.
	/// @brief Arithmetic right-shift function.		APInt LLVM_ATTRIBUTE_UNUSED_RESULT ashr(unsigned shiftAmt) const;
	APInt ashr(unsigned shiftAmt) const;
			/// \brief Logical right-shift function.
			///
	/// Logical right-shift this APInt by shiftAmt.		/// Logical right-shift this APInt by shiftAmt.
	/// @brief Logical right-shift function.		APInt LLVM_ATTRIBUTE_UNUSED_RESULT lshr(unsigned shiftAmt) const;
	APInt lshr(unsigned shiftAmt) const;
			/// \brief Left-shift function.
			///
	/// Left-shift this APInt by shiftAmt.		/// Left-shift this APInt by shiftAmt.
	/// @brief Left-shift function.		APInt LLVM_ATTRIBUTE_UNUSED_RESULT shl(unsigned shiftAmt) const {
	APInt shl(unsigned shiftAmt) const {
	assert(shiftAmt <= BitWidth && "Invalid shift amount");		assert(shiftAmt <= BitWidth && "Invalid shift amount");
	if (isSingleWord()) {		if (isSingleWord()) {
	if (shiftAmt >= BitWidth)		if (shiftAmt >= BitWidth)
	return APInt(BitWidth, 0); // avoid undefined shift results		return APInt(BitWidth, 0); // avoid undefined shift results
	return APInt(BitWidth, VAL << shiftAmt);		return APInt(BitWidth, VAL << shiftAmt);
	}		}
	return shlSlowCase(shiftAmt);		return shlSlowCase(shiftAmt);
	}		}
	/// @brief Rotate left by rotateAmt.		/// \brief Rotate left by rotateAmt.
	APInt rotl(unsigned rotateAmt) const;		APInt LLVM_ATTRIBUTE_UNUSED_RESULT rotl(unsigned rotateAmt) const;
	/// @brief Rotate right by rotateAmt.		/// \brief Rotate right by rotateAmt.
	APInt rotr(unsigned rotateAmt) const;		APInt LLVM_ATTRIBUTE_UNUSED_RESULT rotr(unsigned rotateAmt) const;
			/// \brief Arithmetic right-shift function.
			///
	/// Arithmetic right-shift this APInt by shiftAmt.		/// Arithmetic right-shift this APInt by shiftAmt.
	/// @brief Arithmetic right-shift function.		APInt LLVM_ATTRIBUTE_UNUSED_RESULT ashr(const APInt &shiftAmt) const;
	APInt ashr(const APInt &shiftAmt) const;
			/// \brief Logical right-shift function.
			///
	/// Logical right-shift this APInt by shiftAmt.		/// Logical right-shift this APInt by shiftAmt.
	/// @brief Logical right-shift function.		APInt LLVM_ATTRIBUTE_UNUSED_RESULT lshr(const APInt &shiftAmt) const;
	APInt lshr(const APInt &shiftAmt) const;
			/// \brief Left-shift function.
			///
	/// Left-shift this APInt by shiftAmt.		/// Left-shift this APInt by shiftAmt.
	/// @brief Left-shift function.		APInt LLVM_ATTRIBUTE_UNUSED_RESULT shl(const APInt &shiftAmt) const;
	APInt shl(const APInt &shiftAmt) const;
	/// @brief Rotate left by rotateAmt.		/// \brief Rotate left by rotateAmt.
	APInt rotl(const APInt &rotateAmt) const;		APInt LLVM_ATTRIBUTE_UNUSED_RESULT rotl(const APInt &rotateAmt) const;
	/// @brief Rotate right by rotateAmt.		/// \brief Rotate right by rotateAmt.
	APInt rotr(const APInt &rotateAmt) const;		APInt LLVM_ATTRIBUTE_UNUSED_RESULT rotr(const APInt &rotateAmt) const;
			/// \brief Unsigned division operation.
			///
	/// Perform an unsigned divide operation on this APInt by RHS. Both this and		/// Perform an unsigned divide operation on this APInt by RHS. Both this and
	/// RHS are treated as unsigned quantities for purposes of this division.		/// RHS are treated as unsigned quantities for purposes of this division.
	/// @returns a new APInt value containing the division result		///
	/// @brief Unsigned division operation.		/// \returns a new APInt value containing the division result
	APInt udiv(const APInt &RHS) const;		APInt LLVM_ATTRIBUTE_UNUSED_RESULT udiv(const APInt &RHS) const;
			/// \brief Signed division function for APInt.
			///
	/// Signed divide this APInt by APInt RHS.		/// Signed divide this APInt by APInt RHS.
	/// @brief Signed division function for APInt.		APInt LLVM_ATTRIBUTE_UNUSED_RESULT sdiv(const APInt &RHS) const;
	APInt sdiv(const APInt &RHS) const;
			/// \brief Unsigned remainder operation.
			///
	/// Perform an unsigned remainder operation on this APInt with RHS being the		/// Perform an unsigned remainder operation on this APInt with RHS being the
	/// divisor. Both this and RHS are treated as unsigned quantities for pur poses		/// divisor. Both this and RHS are treated as unsigned quantities for pur poses
	/// of this operation. Note that this is a true remainder operation and n		/// of this operation. Note that this is a true remainder operation and n
	ot		ot a
	/// a modulo operation because the sign follows the sign of the dividend		/// modulo operation because the sign follows the sign of the dividend wh
	/// which is *this.		ich
	/// @returns a new APInt value containing the remainder result		/// is *this.
	/// @brief Unsigned remainder operation.		///
	APInt urem(const APInt &RHS) const;		/// \returns a new APInt value containing the remainder result
			APInt LLVM_ATTRIBUTE_UNUSED_RESULT urem(const APInt &RHS) const;
			/// \brief Function for signed remainder operation.
			///
	/// Signed remainder operation on APInt.		/// Signed remainder operation on APInt.
	/// @brief Function for signed remainder operation.		APInt LLVM_ATTRIBUTE_UNUSED_RESULT srem(const APInt &RHS) const;
	APInt srem(const APInt &RHS) const;
			/// \brief Dual division/remainder interface.
			///
	/// Sometimes it is convenient to divide two APInt values and obtain both the		/// Sometimes it is convenient to divide two APInt values and obtain both the
	/// quotient and remainder. This function does both operations in the sam e		/// quotient and remainder. This function does both operations in the sam e
	/// computation making it a little more efficient. The pair of input argu ments		/// computation making it a little more efficient. The pair of input argu ments
	/// may overlap with the pair of output arguments. It is safe to call		/// may overlap with the pair of output arguments. It is safe to call
	/// udivrem(X, Y, X, Y), for example.		/// udivrem(X, Y, X, Y), for example.
	/// @brief Dual division/remainder interface.		static void udivrem(const APInt &LHS, const APInt &RHS, APInt &Quotient,
	static void udivrem(const APInt &LHS, const APInt &RHS,		APInt &Remainder);
	APInt &Quotient, APInt &Remainder);
	static void sdivrem(const APInt &LHS, const APInt &RHS,		static void sdivrem(const APInt &LHS, const APInt &RHS, APInt &Quotient,
	APInt &Quotient, APInt &Remainder);		APInt &Remainder);
	// Operations that return overflow indicators.		// Operations that return overflow indicators.
	APInt sadd_ov(const APInt &RHS, bool &Overflow) const;		APInt sadd_ov(const APInt &RHS, bool &Overflow) const;
	APInt uadd_ov(const APInt &RHS, bool &Overflow) const;		APInt uadd_ov(const APInt &RHS, bool &Overflow) const;
	APInt ssub_ov(const APInt &RHS, bool &Overflow) const;		APInt ssub_ov(const APInt &RHS, bool &Overflow) const;
	APInt usub_ov(const APInt &RHS, bool &Overflow) const;		APInt usub_ov(const APInt &RHS, bool &Overflow) const;
	APInt sdiv_ov(const APInt &RHS, bool &Overflow) const;		APInt sdiv_ov(const APInt &RHS, bool &Overflow) const;
	APInt smul_ov(const APInt &RHS, bool &Overflow) const;		APInt smul_ov(const APInt &RHS, bool &Overflow) const;
	APInt umul_ov(const APInt &RHS, bool &Overflow) const;		APInt umul_ov(const APInt &RHS, bool &Overflow) const;
	APInt sshl_ov(unsigned Amt, bool &Overflow) const;		APInt sshl_ov(unsigned Amt, bool &Overflow) const;
	/// @returns the bit value at bitPosition		/// \brief Array-indexing support.
	/// @brief Array-indexing support.		///
			/// \returns the bit value at bitPosition
	bool operator[](unsigned bitPosition) const {		bool operator[](unsigned bitPosition) const {
	assert(bitPosition < getBitWidth() && "Bit position out of bounds!");		assert(bitPosition < getBitWidth() && "Bit position out of bounds!");
	return (maskBit(bitPosition) &		return (maskBit(bitPosition) &
	(isSingleWord() ? VAL : pVal[whichWord(bitPosition)])) != 0;		(isSingleWord() ? VAL : pVal[whichWord(bitPosition)])) !=
			0;
	}		}
	/// @}		/// @}
	/// @name Comparison Operators		/// \name Comparison Operators
	/// @{		/// @{
			/// \brief Equality operator.
			///
	/// Compares this APInt with RHS for the validity of the equality		/// Compares this APInt with RHS for the validity of the equality
	/// relationship.		/// relationship.
	/// @brief Equality operator.		bool operator==(const APInt &RHS) const {
	bool operator==(const APInt& RHS) const {
	assert(BitWidth == RHS.BitWidth && "Comparison requires equal bit width s");		assert(BitWidth == RHS.BitWidth && "Comparison requires equal bit width s");
	if (isSingleWord())		if (isSingleWord())
	return VAL == RHS.VAL;		return VAL == RHS.VAL;
	return EqualSlowCase(RHS);		return EqualSlowCase(RHS);
	}		}
			/// \brief Equality operator.
			///
	/// Compares this APInt with a uint64_t for the validity of the equality		/// Compares this APInt with a uint64_t for the validity of the equality
	/// relationship.		/// relationship.
	/// @returns true if *this == Val		///
	/// @brief Equality operator.		/// \returns true if *this == Val
	bool operator==(uint64_t Val) const {		bool operator==(uint64_t Val) const {
	if (isSingleWord())		if (isSingleWord())
	return VAL == Val;		return VAL == Val;
	return EqualSlowCase(Val);		return EqualSlowCase(Val);
	}		}
			/// \brief Equality comparison.
			///
	/// Compares this APInt with RHS for the validity of the equality		/// Compares this APInt with RHS for the validity of the equality
	/// relationship.		/// relationship.
	/// @returns true if *this == Val		///
	/// @brief Equality comparison.		/// \returns true if *this == Val
	bool eq(const APInt &RHS) const {		bool eq(const APInt &RHS) const { return (*this) == RHS; }
	return (*this) == RHS;
	}
			/// \brief Inequality operator.
			///
	/// Compares this APInt with RHS for the validity of the inequality		/// Compares this APInt with RHS for the validity of the inequality
	/// relationship.		/// relationship.
	/// @returns true if *this != Val		///
	/// @brief Inequality operator.		/// \returns true if *this != Val
	bool operator!=(const APInt& RHS) const {		bool operator!=(const APInt &RHS) const { return !((*this) == RHS); }
	return !((*this) == RHS);
	}
			/// \brief Inequality operator.
			///
	/// Compares this APInt with a uint64_t for the validity of the inequalit y		/// Compares this APInt with a uint64_t for the validity of the inequalit y
	/// relationship.		/// relationship.
	/// @returns true if *this != Val		///
	/// @brief Inequality operator.		/// \returns true if *this != Val
	bool operator!=(uint64_t Val) const {		bool operator!=(uint64_t Val) const { return !((*this) == Val); }
	return !((*this) == Val);
	}
			/// \brief Inequality comparison
			///
	/// Compares this APInt with RHS for the validity of the inequality		/// Compares this APInt with RHS for the validity of the inequality
	/// relationship.		/// relationship.
	/// @returns true if *this != Val		///
	/// @brief Inequality comparison		/// \returns true if *this != Val
	bool ne(const APInt &RHS) const {		bool ne(const APInt &RHS) const { return !((*this) == RHS); }
	return !((*this) == RHS);
	}
			/// \brief Unsigned less than comparison
			///
	/// Regards both *this and RHS as unsigned quantities and compares them f or		/// Regards both *this and RHS as unsigned quantities and compares them f or
	/// the validity of the less-than relationship.		/// the validity of the less-than relationship.
	/// @returns true if *this < RHS when both are considered unsigned.		///
	/// @brief Unsigned less than comparison		/// \returns true if *this < RHS when both are considered unsigned.
	bool ult(const APInt &RHS) const;		bool ult(const APInt &RHS) const;
			/// \brief Unsigned less than comparison
			///
	/// Regards both *this as an unsigned quantity and compares it with RHS f or		/// Regards both *this as an unsigned quantity and compares it with RHS f or
	/// the validity of the less-than relationship.		/// the validity of the less-than relationship.
	/// @returns true if *this < RHS when considered unsigned.		///
	/// @brief Unsigned less than comparison		/// \returns true if *this < RHS when considered unsigned.
	bool ult(uint64_t RHS) const {		bool ult(uint64_t RHS) const { return ult(APInt(getBitWidth(), RHS)); }
	return ult(APInt(getBitWidth(), RHS));
	}
			/// \brief Signed less than comparison
			///
	/// Regards both *this and RHS as signed quantities and compares them for		/// Regards both *this and RHS as signed quantities and compares them for
	/// validity of the less-than relationship.		/// validity of the less-than relationship.
	/// @returns true if *this < RHS when both are considered signed.		///
	/// @brief Signed less than comparison		/// \returns true if *this < RHS when both are considered signed.
	bool slt(const APInt& RHS) const;		bool slt(const APInt &RHS) const;
			/// \brief Signed less than comparison
			///
	/// Regards both *this as a signed quantity and compares it with RHS for		/// Regards both *this as a signed quantity and compares it with RHS for
	/// the validity of the less-than relationship.		/// the validity of the less-than relationship.
	/// @returns true if *this < RHS when considered signed.		///
	/// @brief Signed less than comparison		/// \returns true if *this < RHS when considered signed.
	bool slt(uint64_t RHS) const {		bool slt(uint64_t RHS) const { return slt(APInt(getBitWidth(), RHS)); }
	return slt(APInt(getBitWidth(), RHS));
	}
			/// \brief Unsigned less or equal comparison
			///
	/// Regards both *this and RHS as unsigned quantities and compares them f or		/// Regards both *this and RHS as unsigned quantities and compares them f or
	/// validity of the less-or-equal relationship.		/// validity of the less-or-equal relationship.
	/// @returns true if *this <= RHS when both are considered unsigned.		///
	/// @brief Unsigned less or equal comparison		/// \returns true if *this <= RHS when both are considered unsigned.
	bool ule(const APInt& RHS) const {		bool ule(const APInt &RHS) const { return ult(RHS) || eq(RHS); }
	return ult(RHS) || eq(RHS);
	}
			/// \brief Unsigned less or equal comparison
			///
	/// Regards both *this as an unsigned quantity and compares it with RHS f or		/// Regards both *this as an unsigned quantity and compares it with RHS f or
	/// the validity of the less-or-equal relationship.		/// the validity of the less-or-equal relationship.
	/// @returns true if *this <= RHS when considered unsigned.		///
	/// @brief Unsigned less or equal comparison		/// \returns true if *this <= RHS when considered unsigned.
	bool ule(uint64_t RHS) const {		bool ule(uint64_t RHS) const { return ule(APInt(getBitWidth(), RHS)); }
	return ule(APInt(getBitWidth(), RHS));
	}
			/// \brief Signed less or equal comparison
			///
	/// Regards both *this and RHS as signed quantities and compares them for		/// Regards both *this and RHS as signed quantities and compares them for
	/// validity of the less-or-equal relationship.		/// validity of the less-or-equal relationship.
	/// @returns true if *this <= RHS when both are considered signed.		///
	/// @brief Signed less or equal comparison		/// \returns true if *this <= RHS when both are considered signed.
	bool sle(const APInt& RHS) const {		bool sle(const APInt &RHS) const { return slt(RHS) || eq(RHS); }
	return slt(RHS) || eq(RHS);
	}
	/// Regards both *this as a signed quantity and compares it with RHS for		/// \brief Signed less or equal comparison
	/// the validity of the less-or-equal relationship.		///
	/// @returns true if *this <= RHS when considered signed.		/// Regards both *this as a signed quantity and compares it with RHS for
	/// @brief Signed less or equal comparison		the
	bool sle(uint64_t RHS) const {		/// validity of the less-or-equal relationship.
	return sle(APInt(getBitWidth(), RHS));		///
	}		/// \returns true if *this <= RHS when considered signed.
			bool sle(uint64_t RHS) const { return sle(APInt(getBitWidth(), RHS)); }
			/// \brief Unsigned greather than comparison
			///
	/// Regards both *this and RHS as unsigned quantities and compares them f or		/// Regards both *this and RHS as unsigned quantities and compares them f or
	/// the validity of the greater-than relationship.		/// the validity of the greater-than relationship.
	/// @returns true if *this > RHS when both are considered unsigned.		///
	/// @brief Unsigned greather than comparison		/// \returns true if *this > RHS when both are considered unsigned.
	bool ugt(const APInt& RHS) const {		bool ugt(const APInt &RHS) const { return !ult(RHS) && !eq(RHS); }
	return !ult(RHS) && !eq(RHS);
	}
			/// \brief Unsigned greater than comparison
			///
	/// Regards both *this as an unsigned quantity and compares it with RHS f or		/// Regards both *this as an unsigned quantity and compares it with RHS f or
	/// the validity of the greater-than relationship.		/// the validity of the greater-than relationship.
	/// @returns true if *this > RHS when considered unsigned.		///
	/// @brief Unsigned greater than comparison		/// \returns true if *this > RHS when considered unsigned.
	bool ugt(uint64_t RHS) const {		bool ugt(uint64_t RHS) const { return ugt(APInt(getBitWidth(), RHS)); }
	return ugt(APInt(getBitWidth(), RHS));
	}
	/// Regards both *this and RHS as signed quantities and compares them for		/// \brief Signed greather than comparison
	/// the validity of the greater-than relationship.		///
	/// @returns true if *this > RHS when both are considered signed.		/// Regards both *this and RHS as signed quantities and compares them for
	/// @brief Signed greather than comparison		the
	bool sgt(const APInt& RHS) const {		/// validity of the greater-than relationship.
	return !slt(RHS) && !eq(RHS);		///
	}		/// \returns true if *this > RHS when both are considered signed.
			bool sgt(const APInt &RHS) const { return !slt(RHS) && !eq(RHS); }
			/// \brief Signed greater than comparison
			///
	/// Regards both *this as a signed quantity and compares it with RHS for		/// Regards both *this as a signed quantity and compares it with RHS for
	/// the validity of the greater-than relationship.		/// the validity of the greater-than relationship.
	/// @returns true if *this > RHS when considered signed.		///
	/// @brief Signed greater than comparison		/// \returns true if *this > RHS when considered signed.
	bool sgt(uint64_t RHS) const {		bool sgt(uint64_t RHS) const { return sgt(APInt(getBitWidth(), RHS)); }
	return sgt(APInt(getBitWidth(), RHS));
	}
			/// \brief Unsigned greater or equal comparison
			///
	/// Regards both *this and RHS as unsigned quantities and compares them f or		/// Regards both *this and RHS as unsigned quantities and compares them f or
	/// validity of the greater-or-equal relationship.		/// validity of the greater-or-equal relationship.
	/// @returns true if *this >= RHS when both are considered unsigned.		///
	/// @brief Unsigned greater or equal comparison		/// \returns true if *this >= RHS when both are considered unsigned.
	bool uge(const APInt& RHS) const {		bool uge(const APInt &RHS) const { return !ult(RHS); }
	return !ult(RHS);
	}
			/// \brief Unsigned greater or equal comparison
			///
	/// Regards both *this as an unsigned quantity and compares it with RHS f or		/// Regards both *this as an unsigned quantity and compares it with RHS f or
	/// the validity of the greater-or-equal relationship.		/// the validity of the greater-or-equal relationship.
	/// @returns true if *this >= RHS when considered unsigned.		///
	/// @brief Unsigned greater or equal comparison		/// \returns true if *this >= RHS when considered unsigned.
	bool uge(uint64_t RHS) const {		bool uge(uint64_t RHS) const { return uge(APInt(getBitWidth(), RHS)); }
	return uge(APInt(getBitWidth(), RHS));
	}
			/// \brief Signed greather or equal comparison
			///
	/// Regards both *this and RHS as signed quantities and compares them for		/// Regards both *this and RHS as signed quantities and compares them for
	/// validity of the greater-or-equal relationship.		/// validity of the greater-or-equal relationship.
	/// @returns true if *this >= RHS when both are considered signed.		///
	/// @brief Signed greather or equal comparison		/// \returns true if *this >= RHS when both are considered signed.
	bool sge(const APInt& RHS) const {		bool sge(const APInt &RHS) const { return !slt(RHS); }
	return !slt(RHS);
	}
			/// \brief Signed greater or equal comparison
			///
	/// Regards both *this as a signed quantity and compares it with RHS for		/// Regards both *this as a signed quantity and compares it with RHS for
	/// the validity of the greater-or-equal relationship.		/// the validity of the greater-or-equal relationship.
	/// @returns true if *this >= RHS when considered signed.		///
	/// @brief Signed greater or equal comparison		/// \returns true if *this >= RHS when considered signed.
	bool sge(uint64_t RHS) const {		bool sge(uint64_t RHS) const { return sge(APInt(getBitWidth(), RHS)); }
	return sge(APInt(getBitWidth(), RHS));
	}
	/// This operation tests if there are any pairs of corresponding bits		/// This operation tests if there are any pairs of corresponding bits
	/// between this APInt and RHS that are both set.		/// between this APInt and RHS that are both set.
	bool intersects(const APInt &RHS) const {		bool intersects(const APInt &RHS) const { return (*this & RHS) != 0; }
	return (*this & RHS) != 0;
	}
	/// @}		/// @}
	/// @name Resizing Operators		/// \name Resizing Operators
	/// @{		/// @{
			/// \brief Truncate to new width.
			///
	/// Truncate the APInt to a specified width. It is an error to specify a width		/// Truncate the APInt to a specified width. It is an error to specify a width
	/// that is greater than or equal to the current width.		/// that is greater than or equal to the current width.
	/// @brief Truncate to new width.		APInt LLVM_ATTRIBUTE_UNUSED_RESULT trunc(unsigned width) const;
	APInt trunc(unsigned width) const;
			/// \brief Sign extend to a new width.
			///
	/// This operation sign extends the APInt to a new width. If the high ord er		/// This operation sign extends the APInt to a new width. If the high ord er
	/// bit is set, the fill on the left will be done with 1 bits, otherwise zero.		/// bit is set, the fill on the left will be done with 1 bits, otherwise zero.
	/// It is an error to specify a width that is less than or equal to the		/// It is an error to specify a width that is less than or equal to the
	/// current width.		/// current width.
	/// @brief Sign extend to a new width.		APInt LLVM_ATTRIBUTE_UNUSED_RESULT sext(unsigned width) const;
	APInt sext(unsigned width) const;
			/// \brief Zero extend to a new width.
			///
	/// This operation zero extends the APInt to a new width. The high order bits		/// This operation zero extends the APInt to a new width. The high order bits
	/// are filled with 0 bits. It is an error to specify a width that is le ss		/// are filled with 0 bits. It is an error to specify a width that is le ss
	/// than or equal to the current width.		/// than or equal to the current width.
	/// @brief Zero extend to a new width.		APInt LLVM_ATTRIBUTE_UNUSED_RESULT zext(unsigned width) const;
	APInt zext(unsigned width) const;
			/// \brief Sign extend or truncate to width
			///
	/// Make this APInt have the bit width given by \p width. The value is si gn		/// Make this APInt have the bit width given by \p width. The value is si gn
	/// extended, truncated, or left alone to make it that width.		/// extended, truncated, or left alone to make it that width.
	/// @brief Sign extend or truncate to width		APInt LLVM_ATTRIBUTE_UNUSED_RESULT sextOrTrunc(unsigned width) const;
	APInt sextOrTrunc(unsigned width) const;
			/// \brief Zero extend or truncate to width
			///
	/// Make this APInt have the bit width given by \p width. The value is ze ro		/// Make this APInt have the bit width given by \p width. The value is ze ro
	/// extended, truncated, or left alone to make it that width.		/// extended, truncated, or left alone to make it that width.
	/// @brief Zero extend or truncate to width		APInt LLVM_ATTRIBUTE_UNUSED_RESULT zextOrTrunc(unsigned width) const;
	APInt zextOrTrunc(unsigned width) const;
			/// \brief Sign extend or truncate to width
			///
	/// Make this APInt have the bit width given by \p width. The value is si gn		/// Make this APInt have the bit width given by \p width. The value is si gn
	/// extended, or left alone to make it that width.		/// extended, or left alone to make it that width.
	/// @brief Sign extend or truncate to width		APInt LLVM_ATTRIBUTE_UNUSED_RESULT sextOrSelf(unsigned width) const;
	APInt sextOrSelf(unsigned width) const;
			/// \brief Zero extend or truncate to width
			///
	/// Make this APInt have the bit width given by \p width. The value is ze ro		/// Make this APInt have the bit width given by \p width. The value is ze ro
	/// extended, or left alone to make it that width.		/// extended, or left alone to make it that width.
	/// @brief Zero extend or truncate to width		APInt LLVM_ATTRIBUTE_UNUSED_RESULT zextOrSelf(unsigned width) const;
	APInt zextOrSelf(unsigned width) const;
	/// @}		/// @}
	/// @name Bit Manipulation Operators		/// \name Bit Manipulation Operators
	/// @{		/// @{
	/// @brief Set every bit to 1.
			/// \brief Set every bit to 1.
	void setAllBits() {		void setAllBits() {
	if (isSingleWord())		if (isSingleWord())
	VAL = UINT64_MAX;		VAL = UINT64_MAX;
	else {		else {
	// Set all the bits in all the words.		// Set all the bits in all the words.
	for (unsigned i = 0; i < getNumWords(); ++i)		for (unsigned i = 0; i < getNumWords(); ++i)
	pVal[i] = UINT64_MAX;		pVal[i] = UINT64_MAX;
	}		}
	// Clear the unused ones		// Clear the unused ones
	clearUnusedBits();		clearUnusedBits();
	}		}
			/// \brief Set a given bit to 1.
			///
	/// Set the given bit to 1 whose position is given as "bitPosition".		/// Set the given bit to 1 whose position is given as "bitPosition".
	/// @brief Set a given bit to 1.
	void setBit(unsigned bitPosition);		void setBit(unsigned bitPosition);
	/// @brief Set every bit to 0.		/// \brief Set every bit to 0.
	void clearAllBits() {		void clearAllBits() {
	if (isSingleWord())		if (isSingleWord())
	VAL = 0;		VAL = 0;
	else		else
	memset(pVal, 0, getNumWords() * APINT_WORD_SIZE);		memset(pVal, 0, getNumWords() * APINT_WORD_SIZE);
	}		}
			/// \brief Set a given bit to 0.
			///
	/// Set the given bit to 0 whose position is given as "bitPosition".		/// Set the given bit to 0 whose position is given as "bitPosition".
	/// @brief Set a given bit to 0.
	void clearBit(unsigned bitPosition);		void clearBit(unsigned bitPosition);
	/// @brief Toggle every bit to its opposite value.		/// \brief Toggle every bit to its opposite value.
	void flipAllBits() {		void flipAllBits() {
	if (isSingleWord())		if (isSingleWord())
	VAL ^= UINT64_MAX;		VAL ^= UINT64_MAX;
	else {		else {
	for (unsigned i = 0; i < getNumWords(); ++i)		for (unsigned i = 0; i < getNumWords(); ++i)
	pVal[i] ^= UINT64_MAX;		pVal[i] ^= UINT64_MAX;
	}		}
	clearUnusedBits();		clearUnusedBits();
	}		}
			/// \brief Toggles a given bit to its opposite value.
			///
	/// Toggle a given bit to its opposite value whose position is given		/// Toggle a given bit to its opposite value whose position is given
	/// as "bitPosition".		/// as "bitPosition".
	/// @brief Toggles a given bit to its opposite value.
	void flipBit(unsigned bitPosition);		void flipBit(unsigned bitPosition);
	/// @}		/// @}
	/// @name Value Characterization Functions		/// \name Value Characterization Functions
	/// @{		/// @{
	/// @returns the total number of bits.		/// \brief Return the number of bits in the APInt.
	unsigned getBitWidth() const {		unsigned getBitWidth() const { return BitWidth; }
	return BitWidth;
	}
			/// \brief Get the number of words.
			///
	/// Here one word's bitwidth equals to that of uint64_t.		/// Here one word's bitwidth equals to that of uint64_t.
	/// @returns the number of words to hold the integer value of this APInt.		///
	/// @brief Get the number of words.		/// \returns the number of words to hold the integer value of this APInt.
	unsigned getNumWords() const {		unsigned getNumWords() const { return getNumWords(BitWidth); }
	return getNumWords(BitWidth);
	}
	/// Here one word's bitwidth equals to that of uint64_t.		/// \brief Get the number of words.
	/// @returns the number of words to hold the integer value with a		///
	/// given bit width.		/// *NOTE* Here one word's bitwidth equals to that of uint64_t.
	/// @brief Get the number of words.		///
			/// \returns the number of words to hold the integer value with a given b
			it
			/// width.
	static unsigned getNumWords(unsigned BitWidth) {		static unsigned getNumWords(unsigned BitWidth) {
	return (BitWidth + APINT_BITS_PER_WORD - 1) / APINT_BITS_PER_WORD;		return (BitWidth + APINT_BITS_PER_WORD - 1) / APINT_BITS_PER_WORD;
	}		}
			/// \brief Compute the number of active bits in the value
			///
	/// This function returns the number of active bits which is defined as t he		/// This function returns the number of active bits which is defined as t he
	/// bit width minus the number of leading zeros. This is used in several		/// bit width minus the number of leading zeros. This is used in several
	/// computations to see how "wide" the value is.		/// computations to see how "wide" the value is.
	/// @brief Compute the number of active bits in the value		unsigned getActiveBits() const { return BitWidth - countLeadingZeros(); }
	unsigned getActiveBits() const {
	return BitWidth - countLeadingZeros();
	}
	/// This function returns the number of active words in the value of this		/// \brief Compute the number of active words in the value of this APInt.
	/// APInt. This is used in conjunction with getActiveData to extract the		///
	raw		/// This is used in conjunction with getActiveData to extract the raw val
	/// value of the APInt.		ue of
			/// the APInt.
	unsigned getActiveWords() const {		unsigned getActiveWords() const {
	unsigned numActiveBits = getActiveBits();		unsigned numActiveBits = getActiveBits();
	return numActiveBits ? whichWord(numActiveBits - 1) + 1 : 1;		return numActiveBits ? whichWord(numActiveBits - 1) + 1 : 1;
	}		}
	/// Computes the minimum bit width for this APInt while considering it to		/// \brief Get the minimum bit size for this signed APInt
	be		///
	/// a signed (and probably negative) value. If the value is not negative,		/// Computes the minimum bit width for this APInt while considering it to
	/// this function returns the same value as getActiveBits()+1. Otherwise,		be a
	it		/// signed (and probably negative) value. If the value is not negative, t
			his
			/// function returns the same value as getActiveBits()+1. Otherwise, it
	/// returns the smallest bit width that will retain the negative value. F or		/// returns the smallest bit width that will retain the negative value. F or
	/// example, -1 can be written as 0b1 or 0xFFFFFFFFFF. 0b1 is shorter and so		/// example, -1 can be written as 0b1 or 0xFFFFFFFFFF. 0b1 is shorter and so
	/// for -1, this function will always return 1.		/// for -1, this function will always return 1.
	/// @brief Get the minimum bit size for this signed APInt
	unsigned getMinSignedBits() const {		unsigned getMinSignedBits() const {
	if (isNegative())		if (isNegative())
	return BitWidth - countLeadingOnes() + 1;		return BitWidth - countLeadingOnes() + 1;
	return getActiveBits()+1;		return getActiveBits() + 1;
	}		}
			/// \brief Get zero extended value
			///
	/// This method attempts to return the value of this APInt as a zero exte nded		/// This method attempts to return the value of this APInt as a zero exte nded
	/// uint64_t. The bitwidth must be <= 64 or the value must fit within a		/// uint64_t. The bitwidth must be <= 64 or the value must fit within a
	/// uint64_t. Otherwise an assertion will result.		/// uint64_t. Otherwise an assertion will result.
	/// @brief Get zero extended value
	uint64_t getZExtValue() const {		uint64_t getZExtValue() const {
	if (isSingleWord())		if (isSingleWord())
	return VAL;		return VAL;
	assert(getActiveBits() <= 64 && "Too many bits for uint64_t");		assert(getActiveBits() <= 64 && "Too many bits for uint64_t");
	return pVal[0];		return pVal[0];
	}		}
			/// \brief Get sign extended value
			///
	/// This method attempts to return the value of this APInt as a sign exte nded		/// This method attempts to return the value of this APInt as a sign exte nded
	/// int64_t. The bit width must be <= 64 or the value must fit within an		/// int64_t. The bit width must be <= 64 or the value must fit within an
	/// int64_t. Otherwise an assertion will result.		/// int64_t. Otherwise an assertion will result.
	/// @brief Get sign extended value
	int64_t getSExtValue() const {		int64_t getSExtValue() const {
	if (isSingleWord())		if (isSingleWord())
	return int64_t(VAL << (APINT_BITS_PER_WORD - BitWidth)) >>		return int64_t(VAL << (APINT_BITS_PER_WORD - BitWidth)) >>
	(APINT_BITS_PER_WORD - BitWidth);		(APINT_BITS_PER_WORD - BitWidth);
	assert(getMinSignedBits() <= 64 && "Too many bits for int64_t");		assert(getMinSignedBits() <= 64 && "Too many bits for int64_t");
	return int64_t(pVal[0]);		return int64_t(pVal[0]);
	}		}
			/// \brief Get bits required for string value.
			///
	/// This method determines how many bits are required to hold the APInt		/// This method determines how many bits are required to hold the APInt
	/// equivalent of the string given by \p str.		/// equivalent of the string given by \p str.
	/// @brief Get bits required for string value.
	static unsigned getBitsNeeded(StringRef str, uint8_t radix);		static unsigned getBitsNeeded(StringRef str, uint8_t radix);
	/// countLeadingZeros - This function is an APInt version of the		/// \brief The APInt version of the countLeadingZeros functions in
	/// countLeadingZeros_{32,64} functions in MathExtras.h. It counts the nu		/// MathExtras.h.
	mber		///
	/// of zeros from the most significant bit to the first one bit.		/// It counts the number of zeros from the most significant bit to the fi
	/// @returns BitWidth if the value is zero, otherwise		rst
	/// returns the number of zeros from the most significant bit to the firs		/// one bit.
	t		///
	/// one bits.		/// \returns BitWidth if the value is zero, otherwise returns the number
			of
			/// zeros from the most significant bit to the first one bits.
	unsigned countLeadingZeros() const {		unsigned countLeadingZeros() const {
	if (isSingleWord()) {		if (isSingleWord()) {
	unsigned unusedBits = APINT_BITS_PER_WORD - BitWidth;		unsigned unusedBits = APINT_BITS_PER_WORD - BitWidth;
	return CountLeadingZeros_64(VAL) - unusedBits;		return llvm::countLeadingZeros(VAL) - unusedBits;
	}		}
	return countLeadingZerosSlowCase();		return countLeadingZerosSlowCase();
	}		}
	/// countLeadingOnes - This function is an APInt version of the		/// \brief Count the number of leading one bits.
	/// countLeadingOnes_{32,64} functions in MathExtras.h. It counts the num		///
	ber		/// This function is an APInt version of the countLeadingOnes_{32,64}
	/// of ones from the most significant bit to the first zero bit.		/// functions in MathExtras.h. It counts the number of ones from the most
	/// @returns 0 if the high order bit is not set, otherwise		/// significant bit to the first zero bit.
	/// returns the number of 1 bits from the most significant to the least		///
	/// @brief Count the number of leading one bits.		/// \returns 0 if the high order bit is not set, otherwise returns the nu
			mber
			/// of 1 bits from the most significant to the least
	unsigned countLeadingOnes() const;		unsigned countLeadingOnes() const;
	/// Computes the number of leading bits of this APInt that are equal to i ts		/// Computes the number of leading bits of this APInt that are equal to i ts
	/// sign bit.		/// sign bit.
	unsigned getNumSignBits() const {		unsigned getNumSignBits() const {
	return isNegative() ? countLeadingOnes() : countLeadingZeros();		return isNegative() ? countLeadingOnes() : countLeadingZeros();
	}		}
	/// countTrailingZeros - This function is an APInt version of the		/// \brief Count the number of trailing zero bits.
	/// countTrailingZeros_{32,64} functions in MathExtras.h. It counts		///
	/// the number of zeros from the least significant bit to the first set b		/// This function is an APInt version of the countTrailingZeros_{32,64}
	it.		/// functions in MathExtras.h. It counts the number of zeros from the lea
	/// @returns BitWidth if the value is zero, otherwise		st
	/// returns the number of zeros from the least significant bit to the fir		/// significant bit to the first set bit.
	st		///
	/// one bit.		/// \returns BitWidth if the value is zero, otherwise returns the number
	/// @brief Count the number of trailing zero bits.		of
			/// zeros from the least significant bit to the first one bit.
	unsigned countTrailingZeros() const;		unsigned countTrailingZeros() const;
	/// countTrailingOnes - This function is an APInt version of the		/// \brief Count the number of trailing one bits.
	/// countTrailingOnes_{32,64} functions in MathExtras.h. It counts		///
	/// the number of ones from the least significant bit to the first zero b		/// This function is an APInt version of the countTrailingOnes_{32,64}
	it.		/// functions in MathExtras.h. It counts the number of ones from the leas
	/// @returns BitWidth if the value is all ones, otherwise		t
	/// returns the number of ones from the least significant bit to the firs		/// significant bit to the first zero bit.
	t		///
	/// zero bit.		/// \returns BitWidth if the value is all ones, otherwise returns the num
	/// @brief Count the number of trailing one bits.		ber
			/// of ones from the least significant bit to the first zero bit.
	unsigned countTrailingOnes() const {		unsigned countTrailingOnes() const {
	if (isSingleWord())		if (isSingleWord())
	return CountTrailingOnes_64(VAL);		return CountTrailingOnes_64(VAL);
	return countTrailingOnesSlowCase();		return countTrailingOnesSlowCase();
	}		}
	/// countPopulation - This function is an APInt version of the		/// \brief Count the number of bits set.
	/// countPopulation_{32,64} functions in MathExtras.h. It counts the numb		///
	er		/// This function is an APInt version of the countPopulation_{32,64} func
	/// of 1 bits in the APInt value.		tions
	/// @returns 0 if the value is zero, otherwise returns the number of set		/// in MathExtras.h. It counts the number of 1 bits in the APInt value.
	/// bits.		///
	/// @brief Count the number of bits set.		/// \returns 0 if the value is zero, otherwise returns the number of set
			bits.
	unsigned countPopulation() const {		unsigned countPopulation() const {
	if (isSingleWord())		if (isSingleWord())
	return CountPopulation_64(VAL);		return CountPopulation_64(VAL);
	return countPopulationSlowCase();		return countPopulationSlowCase();
	}		}
	/// @}		/// @}
	/// @name Conversion Functions		/// \name Conversion Functions
	/// @{		/// @{
	void print(raw_ostream &OS, bool isSigned) const;		void print(raw_ostream &OS, bool isSigned) const;
	/// toString - Converts an APInt to a string and append it to Str. Str i		/// Converts an APInt to a string and append it to Str. Str is commonly
	s		a
	/// commonly a SmallString.		/// SmallString.
	void toString(SmallVectorImpl<char> &Str, unsigned Radix, bool Signed,		void toString(SmallVectorImpl<char> &Str, unsigned Radix, bool Signed,
	bool formatAsCLiteral = false) const;		bool formatAsCLiteral = false) const;
	/// Considers the APInt to be unsigned and converts it into a string in t he		/// Considers the APInt to be unsigned and converts it into a string in t he
	/// radix given. The radix can be 2, 8, 10 16, or 36.		/// radix given. The radix can be 2, 8, 10 16, or 36.
	void toStringUnsigned(SmallVectorImpl<char> &Str, unsigned Radix = 10) co nst {		void toStringUnsigned(SmallVectorImpl<char> &Str, unsigned Radix = 10) co nst {
	toString(Str, Radix, false, false);		toString(Str, Radix, false, false);
	}		}
	/// Considers the APInt to be signed and converts it into a string in the		/// Considers the APInt to be signed and converts it into a string in the
	/// radix given. The radix can be 2, 8, 10, 16, or 36.		/// radix given. The radix can be 2, 8, 10, 16, or 36.
	void toStringSigned(SmallVectorImpl<char> &Str, unsigned Radix = 10) cons t {		void toStringSigned(SmallVectorImpl<char> &Str, unsigned Radix = 10) cons t {
	toString(Str, Radix, true, false);		toString(Str, Radix, true, false);
	}		}
	/// toString - This returns the APInt as a std::string. Note that this i		/// \brief Return the APInt as a std::string.
	s an		///
	/// inefficient method. It is better to pass in a SmallVector/SmallStrin		/// Note that this is an inefficient method. It is better to pass in a
	g		/// SmallVector/SmallString to the methods above to avoid thrashing the h
	/// to the methods above to avoid thrashing the heap for the string.		eap
			/// for the string.
	std::string toString(unsigned Radix, bool Signed) const;		std::string toString(unsigned Radix, bool Signed) const;
	/// @returns a byte-swapped representation of this APInt Value.		/// \returns a byte-swapped representation of this APInt Value.
	APInt byteSwap() const;		APInt LLVM_ATTRIBUTE_UNUSED_RESULT byteSwap() const;
	/// @brief Converts this APInt to a double value.		/// \brief Converts this APInt to a double value.
	double roundToDouble(bool isSigned) const;		double roundToDouble(bool isSigned) const;
	/// @brief Converts this unsigned APInt to a double value.		/// \brief Converts this unsigned APInt to a double value.
	double roundToDouble() const {		double roundToDouble() const { return roundToDouble(false); }
	return roundToDouble(false);
	}
	/// @brief Converts this signed APInt to a double value.		/// \brief Converts this signed APInt to a double value.
	double signedRoundToDouble() const {		double signedRoundToDouble() const { return roundToDouble(true); }
	return roundToDouble(true);
	}
			/// \brief Converts APInt bits to a double
			///
	/// The conversion does not do a translation from integer to double, it j ust		/// The conversion does not do a translation from integer to double, it j ust
	/// re-interprets the bits as a double. Note that it is valid to do this on		/// re-interprets the bits as a double. Note that it is valid to do this on
	/// any bit width. Exactly 64 bits will be translated.		/// any bit width. Exactly 64 bits will be translated.
	/// @brief Converts APInt bits to a double
	double bitsToDouble() const {		double bitsToDouble() const {
	union {		union {
	uint64_t I;		uint64_t I;
	double D;		double D;
	} T;		} T;
	T.I = (isSingleWord() ? VAL : pVal[0]);		T.I = (isSingleWord() ? VAL : pVal[0]);
	return T.D;		return T.D;
	}		}
			/// \brief Converts APInt bits to a double
			///
	/// The conversion does not do a translation from integer to float, it ju st		/// The conversion does not do a translation from integer to float, it ju st
	/// re-interprets the bits as a float. Note that it is valid to do this o n		/// re-interprets the bits as a float. Note that it is valid to do this o n
	/// any bit width. Exactly 32 bits will be translated.		/// any bit width. Exactly 32 bits will be translated.
	/// @brief Converts APInt bits to a double
	float bitsToFloat() const {		float bitsToFloat() const {
	union {		union {
	unsigned I;		unsigned I;
	float F;		float F;
	} T;		} T;
	T.I = unsigned((isSingleWord() ? VAL : pVal[0]));		T.I = unsigned((isSingleWord() ? VAL : pVal[0]));
	return T.F;		return T.F;
	}		}
			/// \brief Converts a double to APInt bits.
			///
	/// The conversion does not do a translation from double to integer, it j ust		/// The conversion does not do a translation from double to integer, it j ust
	/// re-interprets the bits of the double.		/// re-interprets the bits of the double.
	/// @brief Converts a double to APInt bits.		static APInt LLVM_ATTRIBUTE_UNUSED_RESULT doubleToBits(double V) {
	static APInt doubleToBits(double V) {
	union {		union {
	uint64_t I;		uint64_t I;
	double D;		double D;
	} T;		} T;
	T.D = V;		T.D = V;
	return APInt(sizeof T * CHAR_BIT, T.I);		return APInt(sizeof T * CHAR_BIT, T.I);
	}		}
			/// \brief Converts a float to APInt bits.
			///
	/// The conversion does not do a translation from float to integer, it ju st		/// The conversion does not do a translation from float to integer, it ju st
	/// re-interprets the bits of the float.		/// re-interprets the bits of the float.
	/// @brief Converts a float to APInt bits.		static APInt LLVM_ATTRIBUTE_UNUSED_RESULT floatToBits(float V) {
	static APInt floatToBits(float V) {
	union {		union {
	unsigned I;		unsigned I;
	float F;		float F;
	} T;		} T;
	T.F = V;		T.F = V;
	return APInt(sizeof T * CHAR_BIT, T.I);		return APInt(sizeof T * CHAR_BIT, T.I);
	}		}
	/// @}		/// @}
	/// @name Mathematics Operations		/// \name Mathematics Operations
	/// @{		/// @{
	/// @returns the floor log base 2 of this APInt.		/// \returns the floor log base 2 of this APInt.
	unsigned logBase2() const {		unsigned logBase2() const { return BitWidth - 1 - countLeadingZeros(); }
	return BitWidth - 1 - countLeadingZeros();
	}
	/// @returns the ceil log base 2 of this APInt.		/// \returns the ceil log base 2 of this APInt.
	unsigned ceilLogBase2() const {		unsigned ceilLogBase2() const {
	return BitWidth - (*this - 1).countLeadingZeros();		return BitWidth - (*this - 1).countLeadingZeros();
	}		}
	/// @returns the log base 2 of this APInt if its an exact power of two, - 1		/// \returns the log base 2 of this APInt if its an exact power of two, - 1
	/// otherwise		/// otherwise
	int32_t exactLogBase2() const {		int32_t exactLogBase2() const {
	if (!isPowerOf2())		if (!isPowerOf2())
	return -1;		return -1;
	return logBase2();		return logBase2();
	}		}
	/// @brief Compute the square root		/// \brief Compute the square root
	APInt sqrt() const;		APInt LLVM_ATTRIBUTE_UNUSED_RESULT sqrt() const;
			/// \brief Get the absolute value;
			///
	/// If *this is < 0 then return -(*this), otherwise *this;		/// If *this is < 0 then return -(*this), otherwise *this;
	/// @brief Get the absolute value;		APInt LLVM_ATTRIBUTE_UNUSED_RESULT abs() const {
	APInt abs() const {
	if (isNegative())		if (isNegative())
	return -(*this);		return -(*this);
	return *this;		return *this;
	}		}
	/// @returns the multiplicative inverse for a given modulo.		/// \returns the multiplicative inverse for a given modulo.
	APInt multiplicativeInverse(const APInt& modulo) const;		APInt multiplicativeInverse(const APInt &modulo) const;
	/// @}		/// @}
	/// @name Support for division by constant		/// \name Support for division by constant
	/// @{		/// @{
	/// Calculate the magic number for signed division by a constant.		/// Calculate the magic number for signed division by a constant.
	struct ms;		struct ms;
	ms magic() const;		ms magic() const;
	/// Calculate the magic number for unsigned division by a constant.		/// Calculate the magic number for unsigned division by a constant.
	struct mu;		struct mu;
	mu magicu(unsigned LeadingZeros = 0) const;		mu magicu(unsigned LeadingZeros = 0) const;
	/// @}		/// @}
	/// @name Building-block Operations for APInt and APFloat		/// \name Building-block Operations for APInt and APFloat
	/// @{		/// @{
	// These building block operations operate on a representation of		// These building block operations operate on a representation of arbitra
	// arbitrary precision, two's-complement, bignum integer values.		ry
	// They should be sufficient to implement APInt and APFloat bignum		// precision, two's-complement, bignum integer values. They should be
	// requirements. Inputs are generally a pointer to the base of an		// sufficient to implement APInt and APFloat bignum requirements. Inputs
	// array of integer parts, representing an unsigned bignum, and a		are
	// count of how many parts there are.		// generally a pointer to the base of an array of integer parts, represen
			ting
			// an unsigned bignum, and a count of how many parts there are.
	/// Sets the least significant part of a bignum to the input value,		/// Sets the least significant part of a bignum to the input value, and z
	/// and zeroes out higher parts. */		eroes
			/// out higher parts.
	static void tcSet(integerPart *, integerPart, unsigned int);		static void tcSet(integerPart *, integerPart, unsigned int);
	/// Assign one bignum to another.		/// Assign one bignum to another.
	static void tcAssign(integerPart *, const integerPart *, unsigned int);		static void tcAssign(integerPart *, const integerPart *, unsigned int);
	/// Returns true if a bignum is zero, false otherwise.		/// Returns true if a bignum is zero, false otherwise.
	static bool tcIsZero(const integerPart *, unsigned int);		static bool tcIsZero(const integerPart *, unsigned int);
	/// Extract the given bit of a bignum; returns 0 or 1. Zero-based.		/// Extract the given bit of a bignum; returns 0 or 1. Zero-based.
	static int tcExtractBit(const integerPart *, unsigned int bit);		static int tcExtractBit(const integerPart *, unsigned int bit);
	/// Copy the bit vector of width srcBITS from SRC, starting at bit		/// Copy the bit vector of width srcBITS from SRC, starting at bit srcLSB
	/// srcLSB, to DST, of dstCOUNT parts, such that the bit srcLSB		, to
	/// becomes the least significant bit of DST. All high bits above		/// DST, of dstCOUNT parts, such that the bit srcLSB becomes the least
	/// srcBITS in DST are zero-filled.		/// significant bit of DST. All high bits above srcBITS in DST are
			/// zero-filled.
	static void tcExtract(integerPart *, unsigned int dstCount,		static void tcExtract(integerPart *, unsigned int dstCount,
	const integerPart *,		const integerPart *, unsigned int srcBits,
	unsigned int srcBits, unsigned int srcLSB);		unsigned int srcLSB);
	/// Set the given bit of a bignum. Zero-based.		/// Set the given bit of a bignum. Zero-based.
	static void tcSetBit(integerPart *, unsigned int bit);		static void tcSetBit(integerPart *, unsigned int bit);
	/// Clear the given bit of a bignum. Zero-based.		/// Clear the given bit of a bignum. Zero-based.
	static void tcClearBit(integerPart *, unsigned int bit);		static void tcClearBit(integerPart *, unsigned int bit);
	/// Returns the bit number of the least or most significant set bit		/// Returns the bit number of the least or most significant set bit of a
	/// of a number. If the input number has no bits set -1U is		/// number. If the input number has no bits set -1U is returned.
	/// returned.
	static unsigned int tcLSB(const integerPart *, unsigned int);		static unsigned int tcLSB(const integerPart *, unsigned int);
	static unsigned int tcMSB(const integerPart *parts, unsigned int n);		static unsigned int tcMSB(const integerPart *parts, unsigned int n);
	/// Negate a bignum in-place.		/// Negate a bignum in-place.
	static void tcNegate(integerPart *, unsigned int);		static void tcNegate(integerPart *, unsigned int);
	/// DST += RHS + CARRY where CARRY is zero or one. Returns the		/// DST += RHS + CARRY where CARRY is zero or one. Returns the carry fla
	/// carry flag.		g.
	static integerPart tcAdd(integerPart *, const integerPart *,		static integerPart tcAdd(integerPart *, const integerPart *,
	integerPart carry, unsigned);		integerPart carry, unsigned);
	/// DST -= RHS + CARRY where CARRY is zero or one. Returns the		/// DST -= RHS + CARRY where CARRY is zero or one. Returns the carry flag
	/// carry flag.		.
	static integerPart tcSubtract(integerPart *, const integerPart *,		static integerPart tcSubtract(integerPart *, const integerPart *,
	integerPart carry, unsigned);		integerPart carry, unsigned);
	/// DST += SRC * MULTIPLIER + PART if add is true		/// DST += SRC * MULTIPLIER + PART if add is true
	/// DST = SRC * MULTIPLIER + PART if add is false		/// DST = SRC * MULTIPLIER + PART if add is false
	///		///
	/// Requires 0 <= DSTPARTS <= SRCPARTS + 1. If DST overlaps SRC		/// Requires 0 <= DSTPARTS <= SRCPARTS + 1. If DST overlaps SRC they mus
	/// they must start at the same point, i.e. DST == SRC.		t
			/// start at the same point, i.e. DST == SRC.
	///		///
	/// If DSTPARTS == SRC_PARTS + 1 no overflow occurs and zero is		/// If DSTPARTS == SRC_PARTS + 1 no overflow occurs and zero is returned.
	/// returned. Otherwise DST is filled with the least significant		/// Otherwise DST is filled with the least significant DSTPARTS parts of
	/// DSTPARTS parts of the result, and if all of the omitted higher		the
	/// parts were zero return zero, otherwise overflow occurred and		/// result, and if all of the omitted higher parts were zero return zero,
	/// return one.		/// otherwise overflow occurred and return one.
	static int tcMultiplyPart(integerPart *dst, const integerPart *src,		static int tcMultiplyPart(integerPart *dst, const integerPart *src,
	integerPart multiplier, integerPart carry,		integerPart multiplier, integerPart carry,
	unsigned int srcParts, unsigned int dstParts,		unsigned int srcParts, unsigned int dstParts,
	bool add);		bool add);
	/// DST = LHS * RHS, where DST has the same width as the operands		/// DST = LHS * RHS, where DST has the same width as the operands and is
	/// and is filled with the least significant parts of the result.		/// filled with the least significant parts of the result. Returns one i
	/// Returns one if overflow occurred, otherwise zero. DST must be		f
	/// disjoint from both operands.		/// overflow occurred, otherwise zero. DST must be disjoint from both
	static int tcMultiply(integerPart *, const integerPart *,		/// operands.
	const integerPart *, unsigned);		static int tcMultiply(integerPart *, const integerPart *, const integerPa
			rt *,
	/// DST = LHS * RHS, where DST has width the sum of the widths of		unsigned);
	/// the operands. No overflow occurs. DST must be disjoint from
	/// both operands. Returns the number of parts required to hold the		/// DST = LHS * RHS, where DST has width the sum of the widths of the
	/// result.		/// operands. No overflow occurs. DST must be disjoint from both
			/// operands. Returns the number of parts required to hold the result.
	static unsigned int tcFullMultiply(integerPart *, const integerPart *,		static unsigned int tcFullMultiply(integerPart *, const integerPart *,
	const integerPart *, unsigned, unsigne d);		const integerPart *, unsigned, unsigne d);
	/// If RHS is zero LHS and REMAINDER are left unchanged, return one.		/// If RHS is zero LHS and REMAINDER are left unchanged, return one.
	/// Otherwise set LHS to LHS / RHS with the fractional part		/// Otherwise set LHS to LHS / RHS with the fractional part discarded, se
	/// discarded, set REMAINDER to the remainder, return zero. i.e.		t
			/// REMAINDER to the remainder, return zero. i.e.
	///		///
	/// OLD_LHS = RHS * LHS + REMAINDER		/// OLD_LHS = RHS * LHS + REMAINDER
	///		///
	/// SCRATCH is a bignum of the same size as the operands and result		/// SCRATCH is a bignum of the same size as the operands and result for u
	/// for use by the routine; its contents need not be initialized		se by
	/// and are destroyed. LHS, REMAINDER and SCRATCH must be		/// the routine; its contents need not be initialized and are destroyed.
	/// distinct.		LHS,
			/// REMAINDER and SCRATCH must be distinct.
	static int tcDivide(integerPart *lhs, const integerPart *rhs,		static int tcDivide(integerPart *lhs, const integerPart *rhs,
	integerPart *remainder, integerPart *scratch,		integerPart *remainder, integerPart *scratch,
	unsigned int parts);		unsigned int parts);
	/// Shift a bignum left COUNT bits. Shifted in bits are zero.		/// Shift a bignum left COUNT bits. Shifted in bits are zero. There are
	/// There are no restrictions on COUNT.		no
			/// restrictions on COUNT.
	static void tcShiftLeft(integerPart *, unsigned int parts,		static void tcShiftLeft(integerPart *, unsigned int parts,
	unsigned int count);		unsigned int count);
	/// Shift a bignum right COUNT bits. Shifted in bits are zero.		/// Shift a bignum right COUNT bits. Shifted in bits are zero. There ar
	/// There are no restrictions on COUNT.		e no
			/// restrictions on COUNT.
	static void tcShiftRight(integerPart *, unsigned int parts,		static void tcShiftRight(integerPart *, unsigned int parts,
	unsigned int count);		unsigned int count);
	/// The obvious AND, OR and XOR and complement operations.		/// The obvious AND, OR and XOR and complement operations.
	static void tcAnd(integerPart *, const integerPart *, unsigned int);		static void tcAnd(integerPart *, const integerPart *, unsigned int);
	static void tcOr(integerPart *, const integerPart *, unsigned int);		static void tcOr(integerPart *, const integerPart *, unsigned int);
	static void tcXor(integerPart *, const integerPart *, unsigned int);		static void tcXor(integerPart *, const integerPart *, unsigned int);
	static void tcComplement(integerPart *, unsigned int);		static void tcComplement(integerPart *, unsigned int);
	/// Comparison (unsigned) of two bignums.		/// Comparison (unsigned) of two bignums.
	static int tcCompare(const integerPart *, const integerPart *,		static int tcCompare(const integerPart *, const integerPart *, unsigned i
	unsigned int);		nt);
	/// Increment a bignum in-place. Return the carry flag.		/// Increment a bignum in-place. Return the carry flag.
	static integerPart tcIncrement(integerPart *, unsigned int);		static integerPart tcIncrement(integerPart *, unsigned int);
			/// Decrement a bignum in-place. Return the borrow flag.
			static integerPart tcDecrement(integerPart *, unsigned int);
	/// Set the least significant BITS and clear the rest.		/// Set the least significant BITS and clear the rest.
	static void tcSetLeastSignificantBits(integerPart *, unsigned int,		static void tcSetLeastSignificantBits(integerPart *, unsigned int,
	unsigned int bits);		unsigned int bits);
	/// @brief debug method		/// \brief debug method
	void dump() const;		void dump() const;
	/// @}		/// @}
	};		};
	/// Magic data for optimising signed division by a constant.		/// Magic data for optimising signed division by a constant.
	struct APInt::ms {		struct APInt::ms {
	APInt m; ///< magic number		APInt m; ///< magic number
	unsigned s; ///< shift amount		unsigned s; ///< shift amount
	};		};
	/// Magic data for optimising unsigned division by a constant.		/// Magic data for optimising unsigned division by a constant.
	struct APInt::mu {		struct APInt::mu {
	APInt m; ///< magic number		APInt m; ///< magic number
	bool a; ///< add indicator		bool a; ///< add indicator
	unsigned s; ///< shift amount		unsigned s; ///< shift amount
	};		};
	inline bool operator==(uint64_t V1, const APInt& V2) {		inline bool operator==(uint64_t V1, const APInt &V2) { return V2 == V1; }
	return V2 == V1;
	}
	inline bool operator!=(uint64_t V1, const APInt& V2) {		inline bool operator!=(uint64_t V1, const APInt &V2) { return V2 != V1; }
	return V2 != V1;
	}
	inline raw_ostream &operator<<(raw_ostream &OS, const APInt &I) {		inline raw_ostream &operator<<(raw_ostream &OS, const APInt &I) {
	I.print(OS, true);		I.print(OS, true);
	return OS;		return OS;
	}		}
	namespace APIntOps {		namespace APIntOps {
	/// @brief Determine the smaller of two APInts considered to be signed.		/// \brief Determine the smaller of two APInts considered to be signed.
	inline APInt smin(const APInt &A, const APInt &B) {		inline APInt smin(const APInt &A, const APInt &B) { return A.slt(B) ? A : B
	return A.slt(B) ? A : B;		; }
	}
	/// @brief Determine the larger of two APInts considered to be signed.		/// \brief Determine the larger of two APInts considered to be signed.
	inline APInt smax(const APInt &A, const APInt &B) {		inline APInt smax(const APInt &A, const APInt &B) { return A.sgt(B) ? A : B
	return A.sgt(B) ? A : B;		; }
	}
	/// @brief Determine the smaller of two APInts considered to be signed.		/// \brief Determine the smaller of two APInts considered to be signed.
	inline APInt umin(const APInt &A, const APInt &B) {		inline APInt umin(const APInt &A, const APInt &B) { return A.ult(B) ? A : B
	return A.ult(B) ? A : B;		; }
	}
	/// @brief Determine the larger of two APInts considered to be unsigned.		/// \brief Determine the larger of two APInts considered to be unsigned.
	inline APInt umax(const APInt &A, const APInt &B) {		inline APInt umax(const APInt &A, const APInt &B) { return A.ugt(B) ? A : B
	return A.ugt(B) ? A : B;		; }
	}
	/// @brief Check if the specified APInt has a N-bits unsigned integer value		/// \brief Check if the specified APInt has a N-bits unsigned integer value
	.		.
	inline bool isIntN(unsigned N, const APInt& APIVal) {		inline bool isIntN(unsigned N, const APInt &APIVal) { return APIVal.isIntN(
	return APIVal.isIntN(N);		N); }
	}
	/// @brief Check if the specified APInt has a N-bits signed integer value.		/// \brief Check if the specified APInt has a N-bits signed integer value.
	inline bool isSignedIntN(unsigned N, const APInt& APIVal) {		inline bool isSignedIntN(unsigned N, const APInt &APIVal) {
	return APIVal.isSignedIntN(N);		return APIVal.isSignedIntN(N);
	}		}
	/// @returns true if the argument APInt value is a sequence of ones		/// \returns true if the argument APInt value is a sequence of ones startin
	/// starting at the least significant bit with the remainder zero.		g at
	inline bool isMask(unsigned numBits, const APInt& APIVal) {		/// the least significant bit with the remainder zero.
			inline bool isMask(unsigned numBits, const APInt &APIVal) {
	return numBits <= APIVal.getBitWidth() &&		return numBits <= APIVal.getBitWidth() &&
	APIVal == APInt::getLowBitsSet(APIVal.getBitWidth(), numBits);		APIVal == APInt::getLowBitsSet(APIVal.getBitWidth(), numBits);
	}		}
	/// @returns true if the argument APInt value contains a sequence of ones		/// \brief Return true if the argument APInt value contains a sequence of o nes
	/// with the remainder zero.		/// with the remainder zero.
	inline bool isShiftedMask(unsigned numBits, const APInt& APIVal) {		inline bool isShiftedMask(unsigned numBits, const APInt &APIVal) {
	return isMask(numBits, (APIVal - APInt(numBits,1)) | APIVal);		return isMask(numBits, (APIVal - APInt(numBits, 1)) | APIVal);
	}		}
	/// @returns a byte-swapped representation of the specified APInt Value.		/// \brief Returns a byte-swapped representation of the specified APInt Val
	inline APInt byteSwap(const APInt& APIVal) {		ue.
	return APIVal.byteSwap();		inline APInt byteSwap(const APInt &APIVal) { return APIVal.byteSwap(); }
	}
	/// @returns the floor log base 2 of the specified APInt value.		/// \brief Returns the floor log base 2 of the specified APInt value.
	inline unsigned logBase2(const APInt& APIVal) {		inline unsigned logBase2(const APInt &APIVal) { return APIVal.logBase2(); }
	return APIVal.logBase2();
	}
	/// GreatestCommonDivisor - This function returns the greatest common		/// \brief Compute GCD of two APInt values.
	/// divisor of the two APInt values using Euclid's algorithm.		///
	/// @returns the greatest common divisor of Val1 and Val2		/// This function returns the greatest common divisor of the two APInt valu
	/// @brief Compute GCD of two APInt values.		es
	APInt GreatestCommonDivisor(const APInt& Val1, const APInt& Val2);		/// using Euclid's algorithm.
			///
			/// \returns the greatest common divisor of Val1 and Val2
			APInt GreatestCommonDivisor(const APInt &Val1, const APInt &Val2);
			/// \brief Converts the given APInt to a double value.
			///
	/// Treats the APInt as an unsigned value for conversion purposes.		/// Treats the APInt as an unsigned value for conversion purposes.
	/// @brief Converts the given APInt to a double value.		inline double RoundAPIntToDouble(const APInt &APIVal) {
	inline double RoundAPIntToDouble(const APInt& APIVal) {
	return APIVal.roundToDouble();		return APIVal.roundToDouble();
	}		}
			/// \brief Converts the given APInt to a double value.
			///
	/// Treats the APInt as a signed value for conversion purposes.		/// Treats the APInt as a signed value for conversion purposes.
	/// @brief Converts the given APInt to a double value.		inline double RoundSignedAPIntToDouble(const APInt &APIVal) {
	inline double RoundSignedAPIntToDouble(const APInt& APIVal) {
	return APIVal.signedRoundToDouble();		return APIVal.signedRoundToDouble();
	}		}
	/// @brief Converts the given APInt to a float vlalue.		/// \brief Converts the given APInt to a float vlalue.
	inline float RoundAPIntToFloat(const APInt& APIVal) {		inline float RoundAPIntToFloat(const APInt &APIVal) {
	return float(RoundAPIntToDouble(APIVal));		return float(RoundAPIntToDouble(APIVal));
	}		}
			/// \brief Converts the given APInt to a float value.
			///
	/// Treast the APInt as a signed value for conversion purposes.		/// Treast the APInt as a signed value for conversion purposes.
	/// @brief Converts the given APInt to a float value.		inline float RoundSignedAPIntToFloat(const APInt &APIVal) {
	inline float RoundSignedAPIntToFloat(const APInt& APIVal) {
	return float(APIVal.signedRoundToDouble());		return float(APIVal.signedRoundToDouble());
	}		}
	/// RoundDoubleToAPInt - This function convert a double value to an APInt v		/// \brief Converts the given double value into a APInt.
	alue.		///
	/// @brief Converts the given double value into a APInt.		/// This function convert a double value to an APInt value.
	APInt RoundDoubleToAPInt(double Double, unsigned width);		APInt RoundDoubleToAPInt(double Double, unsigned width);
	/// RoundFloatToAPInt - Converts a float value into an APInt value.		/// \brief Converts a float value into a APInt.
	/// @brief Converts a float value into a APInt.		///
			/// Converts a float value into an APInt value.
	inline APInt RoundFloatToAPInt(float Float, unsigned width) {		inline APInt RoundFloatToAPInt(float Float, unsigned width) {
	return RoundDoubleToAPInt(double(Float), width);		return RoundDoubleToAPInt(double(Float), width);
	}		}
			/// \brief Arithmetic right-shift function.
			///
	/// Arithmetic right-shift the APInt by shiftAmt.		/// Arithmetic right-shift the APInt by shiftAmt.
	/// @brief Arithmetic right-shift function.		inline APInt ashr(const APInt &LHS, unsigned shiftAmt) {
	inline APInt ashr(const APInt& LHS, unsigned shiftAmt) {
	return LHS.ashr(shiftAmt);		return LHS.ashr(shiftAmt);
	}		}
			/// \brief Logical right-shift function.
			///
	/// Logical right-shift the APInt by shiftAmt.		/// Logical right-shift the APInt by shiftAmt.
	/// @brief Logical right-shift function.		inline APInt lshr(const APInt &LHS, unsigned shiftAmt) {
	inline APInt lshr(const APInt& LHS, unsigned shiftAmt) {
	return LHS.lshr(shiftAmt);		return LHS.lshr(shiftAmt);
	}		}
			/// \brief Left-shift function.
			///
	/// Left-shift the APInt by shiftAmt.		/// Left-shift the APInt by shiftAmt.
	/// @brief Left-shift function.		inline APInt shl(const APInt &LHS, unsigned shiftAmt) {
	inline APInt shl(const APInt& LHS, unsigned shiftAmt) {
	return LHS.shl(shiftAmt);		return LHS.shl(shiftAmt);
	}		}
			/// \brief Signed division function for APInt.
			///
	/// Signed divide APInt LHS by APInt RHS.		/// Signed divide APInt LHS by APInt RHS.
	/// @brief Signed division function for APInt.		inline APInt sdiv(const APInt &LHS, const APInt &RHS) { return LHS.sdiv(RHS
	inline APInt sdiv(const APInt& LHS, const APInt& RHS) {		); }
	return LHS.sdiv(RHS);
	}
			/// \brief Unsigned division function for APInt.
			///
	/// Unsigned divide APInt LHS by APInt RHS.		/// Unsigned divide APInt LHS by APInt RHS.
	/// @brief Unsigned division function for APInt.		inline APInt udiv(const APInt &LHS, const APInt &RHS) { return LHS.udiv(RHS
	inline APInt udiv(const APInt& LHS, const APInt& RHS) {		); }
	return LHS.udiv(RHS);
	}
			/// \brief Function for signed remainder operation.
			///
	/// Signed remainder operation on APInt.		/// Signed remainder operation on APInt.
	/// @brief Function for signed remainder operation.		inline APInt srem(const APInt &LHS, const APInt &RHS) { return LHS.srem(RHS
	inline APInt srem(const APInt& LHS, const APInt& RHS) {		); }
	return LHS.srem(RHS);
	}
			/// \brief Function for unsigned remainder operation.
			///
	/// Unsigned remainder operation on APInt.		/// Unsigned remainder operation on APInt.
	/// @brief Function for unsigned remainder operation.		inline APInt urem(const APInt &LHS, const APInt &RHS) { return LHS.urem(RHS
	inline APInt urem(const APInt& LHS, const APInt& RHS) {		); }
	return LHS.urem(RHS);
	}
			/// \brief Function for multiplication operation.
			///
	/// Performs multiplication on APInt values.		/// Performs multiplication on APInt values.
	/// @brief Function for multiplication operation.		inline APInt mul(const APInt &LHS, const APInt &RHS) { return LHS * RHS; }
	inline APInt mul(const APInt& LHS, const APInt& RHS) {
	return LHS * RHS;
	}
			/// \brief Function for addition operation.
			///
	/// Performs addition on APInt values.		/// Performs addition on APInt values.
	/// @brief Function for addition operation.		inline APInt add(const APInt &LHS, const APInt &RHS) { return LHS + RHS; }
	inline APInt add(const APInt& LHS, const APInt& RHS) {
	return LHS + RHS;
	}
			/// \brief Function for subtraction operation.
			///
	/// Performs subtraction on APInt values.		/// Performs subtraction on APInt values.
	/// @brief Function for subtraction operation.		inline APInt sub(const APInt &LHS, const APInt &RHS) { return LHS - RHS; }
	inline APInt sub(const APInt& LHS, const APInt& RHS) {
	return LHS - RHS;
	}
			/// \brief Bitwise AND function for APInt.
			///
	/// Performs bitwise AND operation on APInt LHS and		/// Performs bitwise AND operation on APInt LHS and
	/// APInt RHS.		/// APInt RHS.
	/// @brief Bitwise AND function for APInt.		inline APInt And(const APInt &LHS, const APInt &RHS) { return LHS & RHS; }
	inline APInt And(const APInt& LHS, const APInt& RHS) {
	return LHS & RHS;
	}
			/// \brief Bitwise OR function for APInt.
			///
	/// Performs bitwise OR operation on APInt LHS and APInt RHS.		/// Performs bitwise OR operation on APInt LHS and APInt RHS.
	/// @brief Bitwise OR function for APInt.		inline APInt Or(const APInt &LHS, const APInt &RHS) { return LHS | RHS; }
	inline APInt Or(const APInt& LHS, const APInt& RHS) {
	return LHS | RHS;
	}
			/// \brief Bitwise XOR function for APInt.
			///
	/// Performs bitwise XOR operation on APInt.		/// Performs bitwise XOR operation on APInt.
	/// @brief Bitwise XOR function for APInt.		inline APInt Xor(const APInt &LHS, const APInt &RHS) { return LHS ^ RHS; }
	inline APInt Xor(const APInt& LHS, const APInt& RHS) {
	return LHS ^ RHS;
	}
			/// \brief Bitwise complement function.
			///
	/// Performs a bitwise complement operation on APInt.		/// Performs a bitwise complement operation on APInt.
	/// @brief Bitwise complement function.		inline APInt Not(const APInt &APIVal) { return ~APIVal; }
	inline APInt Not(const APInt& APIVal) {
	return ~APIVal;
	}
	} // End of APIntOps namespace		} // End of APIntOps namespace
	// See friend declaration above. This additional declaration is required		// See friend declaration above. This additional declaration is required in
	in		// order to compile LLVM with IBM xlC compiler.
	// order to compile LLVM with IBM xlC compiler.		hash_code hash_value(const APInt &Arg);
	hash_code hash_value(const APInt &Arg);
	} // End of llvm namespace		} // End of llvm namespace
	#endif		#endif
End of changes. 362 change blocks.
	714 lines changed or deleted		855 lines changed or added

	APSInt.h		APSInt.h
	skipping to change at line 71		skipping to change at line 71
	void toString(SmallVectorImpl<char> &Str, unsigned Radix = 10) const {		void toString(SmallVectorImpl<char> &Str, unsigned Radix = 10) const {
	APInt::toString(Str, Radix, isSigned());		APInt::toString(Str, Radix, isSigned());
	}		}
	/// toString - Converts an APInt to a std::string. This is an inefficien t		/// toString - Converts an APInt to a std::string. This is an inefficien t
	/// method, your should prefer passing in a SmallString instead.		/// method, your should prefer passing in a SmallString instead.
	std::string toString(unsigned Radix) const {		std::string toString(unsigned Radix) const {
	return APInt::toString(Radix, isSigned());		return APInt::toString(Radix, isSigned());
	}		}
	using APInt::toString;		using APInt::toString;
	APSInt trunc(uint32_t width) const {		APSInt LLVM_ATTRIBUTE_UNUSED_RESULT trunc(uint32_t width) const {
	return APSInt(APInt::trunc(width), IsUnsigned);		return APSInt(APInt::trunc(width), IsUnsigned);
	}		}
	APSInt extend(uint32_t width) const {		APSInt LLVM_ATTRIBUTE_UNUSED_RESULT extend(uint32_t width) const {
	if (IsUnsigned)		if (IsUnsigned)
	return APSInt(zext(width), IsUnsigned);		return APSInt(zext(width), IsUnsigned);
	else		else
	return APSInt(sext(width), IsUnsigned);		return APSInt(sext(width), IsUnsigned);
	}		}
	APSInt extOrTrunc(uint32_t width) const {		APSInt LLVM_ATTRIBUTE_UNUSED_RESULT extOrTrunc(uint32_t width) const {
	if (IsUnsigned)		if (IsUnsigned)
	return APSInt(zextOrTrunc(width), IsUnsigned);		return APSInt(zextOrTrunc(width), IsUnsigned);
	else		else
	return APSInt(sextOrTrunc(width), IsUnsigned);		return APSInt(sextOrTrunc(width), IsUnsigned);
	}		}
	const APSInt &operator%=(const APSInt &RHS) {		const APSInt &operator%=(const APSInt &RHS) {
	assert(IsUnsigned == RHS.IsUnsigned && "Signedness mismatch!");		assert(IsUnsigned == RHS.IsUnsigned && "Signedness mismatch!");
	if (IsUnsigned)		if (IsUnsigned)
	*this = urem(RHS);		*this = urem(RHS);
	skipping to change at line 215		skipping to change at line 215
	APSInt& operator^=(const APSInt& RHS) {		APSInt& operator^=(const APSInt& RHS) {
	assert(IsUnsigned == RHS.IsUnsigned && "Signedness mismatch!");		assert(IsUnsigned == RHS.IsUnsigned && "Signedness mismatch!");
	static_cast<APInt&>(*this) ^= RHS;		static_cast<APInt&>(*this) ^= RHS;
	return *this;		return *this;
	}		}
	APSInt operator&(const APSInt& RHS) const {		APSInt operator&(const APSInt& RHS) const {
	assert(IsUnsigned == RHS.IsUnsigned && "Signedness mismatch!");		assert(IsUnsigned == RHS.IsUnsigned && "Signedness mismatch!");
	return APSInt(static_cast<const APInt&>(*this) & RHS, IsUnsigned);		return APSInt(static_cast<const APInt&>(*this) & RHS, IsUnsigned);
	}		}
	APSInt And(const APSInt& RHS) const {		APSInt LLVM_ATTRIBUTE_UNUSED_RESULT And(const APSInt& RHS) const {
	return this->operator&(RHS);		return this->operator&(RHS);
	}		}
	APSInt operator|(const APSInt& RHS) const {		APSInt operator|(const APSInt& RHS) const {
	assert(IsUnsigned == RHS.IsUnsigned && "Signedness mismatch!");		assert(IsUnsigned == RHS.IsUnsigned && "Signedness mismatch!");
	return APSInt(static_cast<const APInt&>(*this) | RHS, IsUnsigned);		return APSInt(static_cast<const APInt&>(*this) | RHS, IsUnsigned);
	}		}
	APSInt Or(const APSInt& RHS) const {		APSInt LLVM_ATTRIBUTE_UNUSED_RESULT Or(const APSInt& RHS) const {
	return this->operator|(RHS);		return this->operator|(RHS);
	}		}
	APSInt operator^(const APSInt& RHS) const {		APSInt operator^(const APSInt& RHS) const {
	assert(IsUnsigned == RHS.IsUnsigned && "Signedness mismatch!");		assert(IsUnsigned == RHS.IsUnsigned && "Signedness mismatch!");
	return APSInt(static_cast<const APInt&>(*this) ^ RHS, IsUnsigned);		return APSInt(static_cast<const APInt&>(*this) ^ RHS, IsUnsigned);
	}		}
	APSInt Xor(const APSInt& RHS) const {		APSInt LLVM_ATTRIBUTE_UNUSED_RESULT Xor(const APSInt& RHS) const {
	return this->operator^(RHS);		return this->operator^(RHS);
	}		}
	APSInt operator*(const APSInt& RHS) const {		APSInt operator*(const APSInt& RHS) const {
	assert(IsUnsigned == RHS.IsUnsigned && "Signedness mismatch!");		assert(IsUnsigned == RHS.IsUnsigned && "Signedness mismatch!");
	return APSInt(static_cast<const APInt&>(*this) * RHS, IsUnsigned);		return APSInt(static_cast<const APInt&>(*this) * RHS, IsUnsigned);
	}		}
	APSInt operator+(const APSInt& RHS) const {		APSInt operator+(const APSInt& RHS) const {
	assert(IsUnsigned == RHS.IsUnsigned && "Signedness mismatch!");		assert(IsUnsigned == RHS.IsUnsigned && "Signedness mismatch!");
	return APSInt(static_cast<const APInt&>(*this) + RHS, IsUnsigned);		return APSInt(static_cast<const APInt&>(*this) + RHS, IsUnsigned);
End of changes. 6 change blocks.
	6 lines changed or deleted		6 lines changed or added

	AliasAnalysis.h		AliasAnalysis.h
	skipping to change at line 587		skipping to change at line 587
	return LHS.Ptr == RHS.Ptr &&		return LHS.Ptr == RHS.Ptr &&
	LHS.Size == RHS.Size &&		LHS.Size == RHS.Size &&
	LHS.TBAATag == RHS.TBAATag;		LHS.TBAATag == RHS.TBAATag;
	}		}
	};		};
	/// isNoAliasCall - Return true if this pointer is returned by a noalias		/// isNoAliasCall - Return true if this pointer is returned by a noalias
	/// function.		/// function.
	bool isNoAliasCall(const Value *V);		bool isNoAliasCall(const Value *V);
			/// isNoAliasArgument - Return true if this is an argument with the noalias
			/// attribute.
			bool isNoAliasArgument(const Value *V);
	/// isIdentifiedObject - Return true if this pointer refers to a distinct a nd		/// isIdentifiedObject - Return true if this pointer refers to a distinct a nd
	/// identifiable object. This returns true for:		/// identifiable object. This returns true for:
	/// Global Variables and Functions (but not Global Aliases)		/// Global Variables and Functions (but not Global Aliases)
	/// Allocas		/// Allocas
	/// ByVal and NoAlias Arguments		/// ByVal and NoAlias Arguments
	/// NoAlias returns (e.g. calls to malloc)		/// NoAlias returns (e.g. calls to malloc)
	///		///
	bool isIdentifiedObject(const Value *V);		bool isIdentifiedObject(const Value *V);
	} // End llvm namespace		} // End llvm namespace
End of changes. 1 change blocks.
	0 lines changed or deleted		4 lines changed or added

	Allocator.h		Allocator.h
	skipping to change at line 102		skipping to change at line 102
	void operator=(const BumpPtrAllocator &) LLVM_DELETED_FUNCTION;		void operator=(const BumpPtrAllocator &) LLVM_DELETED_FUNCTION;
	/// SlabSize - Allocate data into slabs of this size unless we get an		/// SlabSize - Allocate data into slabs of this size unless we get an
	/// allocation above SizeThreshold.		/// allocation above SizeThreshold.
	size_t SlabSize;		size_t SlabSize;
	/// SizeThreshold - For any allocation larger than this threshold, we sho uld		/// SizeThreshold - For any allocation larger than this threshold, we sho uld
	/// allocate a separate slab.		/// allocate a separate slab.
	size_t SizeThreshold;		size_t SizeThreshold;
			/// \brief the default allocator used if one is not provided
			MallocSlabAllocator DefaultSlabAllocator;
	/// Allocator - The underlying allocator we use to get slabs of memory. This		/// Allocator - The underlying allocator we use to get slabs of memory. This
	/// defaults to MallocSlabAllocator, which wraps malloc, but it could be		/// defaults to MallocSlabAllocator, which wraps malloc, but it could be
	/// changed to use a custom allocator.		/// changed to use a custom allocator.
	SlabAllocator &Allocator;		SlabAllocator &Allocator;
	/// CurSlab - The slab that we are currently allocating into.		/// CurSlab - The slab that we are currently allocating into.
	///		///
	MemSlab *CurSlab;		MemSlab *CurSlab;
	/// CurPtr - The current pointer into the current slab. This points to t he		/// CurPtr - The current pointer into the current slab. This points to t he
	skipping to change at line 136		skipping to change at line 139
	static char *AlignPtr(char *Ptr, size_t Alignment);		static char *AlignPtr(char *Ptr, size_t Alignment);
	/// StartNewSlab - Allocate a new slab and move the bump pointers over in to		/// StartNewSlab - Allocate a new slab and move the bump pointers over in to
	/// the new slab. Modifies CurPtr and End.		/// the new slab. Modifies CurPtr and End.
	void StartNewSlab();		void StartNewSlab();
	/// DeallocateSlabs - Deallocate all memory slabs after and including thi s		/// DeallocateSlabs - Deallocate all memory slabs after and including thi s
	/// one.		/// one.
	void DeallocateSlabs(MemSlab *Slab);		void DeallocateSlabs(MemSlab *Slab);
	static MallocSlabAllocator DefaultSlabAllocator;
	template<typename T> friend class SpecificBumpPtrAllocator;		template<typename T> friend class SpecificBumpPtrAllocator;
	public:		public:
	BumpPtrAllocator(size_t size = 4096, size_t threshold = 4096,		BumpPtrAllocator(size_t size = 4096, size_t threshold = 4096);
	SlabAllocator &allocator = DefaultSlabAllocator);		BumpPtrAllocator(size_t size, size_t threshold, SlabAllocator &allocator)
			;
	~BumpPtrAllocator();		~BumpPtrAllocator();
	/// Reset - Deallocate all but the current slab and reset the current poi nter		/// Reset - Deallocate all but the current slab and reset the current poi nter
	/// to the beginning of it, freeing all memory allocated so far.		/// to the beginning of it, freeing all memory allocated so far.
	void Reset();		void Reset();
	/// Allocate - Allocate space at the specified alignment.		/// Allocate - Allocate space at the specified alignment.
	///		///
	void *Allocate(size_t Size, size_t Alignment);		void *Allocate(size_t Size, size_t Alignment);
	skipping to change at line 192		skipping to change at line 193
	size_t getTotalMemory() const;		size_t getTotalMemory() const;
	};		};
	/// SpecificBumpPtrAllocator - Same as BumpPtrAllocator but allows only		/// SpecificBumpPtrAllocator - Same as BumpPtrAllocator but allows only
	/// elements of one type to be allocated. This allows calling the destructo r		/// elements of one type to be allocated. This allows calling the destructo r
	/// in DestroyAll() and when the allocator is destroyed.		/// in DestroyAll() and when the allocator is destroyed.
	template <typename T>		template <typename T>
	class SpecificBumpPtrAllocator {		class SpecificBumpPtrAllocator {
	BumpPtrAllocator Allocator;		BumpPtrAllocator Allocator;
	public:		public:
	SpecificBumpPtrAllocator(size_t size = 4096, size_t threshold = 4096,		SpecificBumpPtrAllocator(size_t size = 4096, size_t threshold = 4096)
	SlabAllocator &allocator = BumpPtrAllocator::DefaultSlabAlloc		: Allocator(size, threshold) {}
	ator)		SpecificBumpPtrAllocator(size_t size, size_t threshold,
			SlabAllocator &allocator)
	: Allocator(size, threshold, allocator) {}		: Allocator(size, threshold, allocator) {}
	~SpecificBumpPtrAllocator() {		~SpecificBumpPtrAllocator() {
	DestroyAll();		DestroyAll();
	}		}
	/// Call the destructor of each allocated object and deallocate all but t he		/// Call the destructor of each allocated object and deallocate all but t he
	/// current slab and reset the current pointer to the beginning of it, fr eeing		/// current slab and reset the current pointer to the beginning of it, fr eeing
	/// all memory allocated so far.		/// all memory allocated so far.
	void DestroyAll() {		void DestroyAll() {
End of changes. 4 change blocks.
	7 lines changed or deleted		10 lines changed or added

	Archive.h		Archive.h
	skipping to change at line 17		skipping to change at line 17
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This file declares the ar archive file format class.		// This file declares the ar archive file format class.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_OBJECT_ARCHIVE_H		#ifndef LLVM_OBJECT_ARCHIVE_H
	#define LLVM_OBJECT_ARCHIVE_H		#define LLVM_OBJECT_ARCHIVE_H
	#include "llvm/ADT/SmallString.h"
	#include "llvm/ADT/StringRef.h"		#include "llvm/ADT/StringRef.h"
	#include "llvm/ADT/Twine.h"
	#include "llvm/Object/Binary.h"		#include "llvm/Object/Binary.h"
	#include "llvm/Support/DataTypes.h"
	#include "llvm/Support/ErrorHandling.h"		#include "llvm/Support/ErrorHandling.h"
			#include "llvm/Support/FileSystem.h"
	#include "llvm/Support/MemoryBuffer.h"		#include "llvm/Support/MemoryBuffer.h"
	namespace llvm {		namespace llvm {
	namespace object {		namespace object {
	struct ArchiveMemberHeader {		struct ArchiveMemberHeader {
	char Name[16];		char Name[16];
	char LastModified[12];		char LastModified[12];
	char UID[6];		char UID[6];
	char GID[6];		char GID[6];
	char AccessMode[8];		char AccessMode[8];
	char Size[10]; ///< Size of data, not including header or padding.		char Size[10]; ///< Size of data, not including header or padding.
	char Terminator[2];		char Terminator[2];
	///! Get the name without looking up long names.		/// Get the name without looking up long names.
	llvm::StringRef getName() const {		llvm::StringRef getName() const;
	char EndCond;
	if (Name[0] == '/' || Name[0] == '#')
	EndCond = ' ';
	else
	EndCond = '/';
	llvm::StringRef::size_type end =
	llvm::StringRef(Name, sizeof(Name)).find(EndCond);
	if (end == llvm::StringRef::npos)
	end = sizeof(Name);
	assert(end <= sizeof(Name) && end > 0);
	// Don't include the EndCond if there is one.
	return llvm::StringRef(Name, end);
	}
	uint64_t getSize() const {		/// Members are not larger than 4GB.
	uint64_t ret;		uint32_t getSize() const;
	if (llvm::StringRef(Size, sizeof(Size)).rtrim(" ").getAsInteger(10, ret
	))
	llvm_unreachable("Size is not an integer.");
	return ret;
	}
	};
	static const ArchiveMemberHeader *ToHeader(const char *base) {		sys::fs::perms getAccessMode() const;
	return reinterpret_cast<const ArchiveMemberHeader *>(base);		sys::TimeValue getLastModified() const;
	}		unsigned getUID() const;
			unsigned getGID() const;
			};
	class Archive : public Binary {		class Archive : public Binary {
	virtual void anchor();		virtual void anchor();
	public:		public:
	class Child {		class Child {
	const Archive *Parent;		const Archive *Parent;
	/// \brief Includes header but not padding byte.		/// \brief Includes header but not padding byte.
	StringRef Data;		StringRef Data;
	/// \brief Offset from Data to the start of the file.		/// \brief Offset from Data to the start of the file.
	uint16_t StartOfFile;		uint16_t StartOfFile;
	public:		const ArchiveMemberHeader *getHeader() const {
	Child(const Archive *p, StringRef d) : Parent(p), Data(d) {		return reinterpret_cast<const ArchiveMemberHeader *>(Data.data());
	if (!p || d.empty())
	return;
	// Setup StartOfFile and PaddingBytes.
	StartOfFile = sizeof(ArchiveMemberHeader);
	// Don't include attached name.
	StringRef Name = ToHeader(Data.data())->getName();
	if (Name.startswith("#1/")) {
	uint64_t NameSize;
	if (Name.substr(3).rtrim(" ").getAsInteger(10, NameSize))
	llvm_unreachable("Long name length is not an integer");
	StartOfFile += NameSize;
	}
	}		}
			public:
			Child(const Archive *Parent, const char *Start);
	bool operator ==(const Child &other) const {		bool operator ==(const Child &other) const {
	return (Parent == other.Parent) && (Data.begin() == other.Data.begin(		assert(Parent == other.Parent);
	));		return Data.begin() == other.Data.begin();
	}		}
	bool operator <(const Child &other) const {		bool operator <(const Child &other) const {
	return Data.begin() < other.Data.begin();		return Data.begin() < other.Data.begin();
	}		}
	Child getNext() const {		Child getNext() const;
	size_t SpaceToSkip = Data.size();
	// If it's odd, add 1 to make it even.
	if (SpaceToSkip & 1)
	++SpaceToSkip;
	const char *NextLoc = Data.data() + SpaceToSkip;
	// Check to see if this is past the end of the archive.
	if (NextLoc >= Parent->Data->getBufferEnd())
	return Child(Parent, StringRef(0, 0));
	size_t NextSize =
	sizeof(ArchiveMemberHeader) + ToHeader(NextLoc)->getSize();
	return Child(Parent, StringRef(NextLoc, NextSize));
	}
	error_code getName(StringRef &Result) const;		error_code getName(StringRef &Result) const;
	int getLastModified() const;		StringRef getRawName() const { return getHeader()->getName(); }
	int getUID() const;		sys::TimeValue getLastModified() const {
	int getGID() const;		return getHeader()->getLastModified();
	int getAccessMode() const;		}
			unsigned getUID() const { return getHeader()->getUID(); }
			unsigned getGID() const { return getHeader()->getGID(); }
			sys::fs::perms getAccessMode() const {
			return getHeader()->getAccessMode();
			}
	/// \return the size of the archive member without the header or paddin g.		/// \return the size of the archive member without the header or paddin g.
	uint64_t getSize() const { return Data.size() - StartOfFile; }		uint64_t getSize() const { return Data.size() - StartOfFile; }
	StringRef getBuffer() const {		StringRef getBuffer() const {
	return StringRef(Data.data() + StartOfFile, getSize());		return StringRef(Data.data() + StartOfFile, getSize());
	}		}
	error_code getMemoryBuffer(OwningPtr<MemoryBuffer> &Result,		error_code getMemoryBuffer(OwningPtr<MemoryBuffer> &Result,
	bool FullPath = false) const {		bool FullPath = false) const;
	StringRef Name;
	if (error_code ec = getName(Name))
	return ec;
	SmallString<128> Path;
	Result.reset(MemoryBuffer::getMemBuffer(
	getBuffer(), FullPath ? (Twine(Parent->getFileName()) + "(" + Nam
	e +
	")").toStringRef(Path) : Name, false));
	return error_code::success();
	}
	error_code getAsBinary(OwningPtr<Binary> &Result) const;		error_code getAsBinary(OwningPtr<Binary> &Result) const;
	};		};
	class child_iterator {		class child_iterator {
	Child child;		Child child;
	public:		public:
	child_iterator() : child(Child(0, StringRef())) {}		child_iterator() : child(Child(0, 0)) {}
	child_iterator(const Child &c) : child(c) {}		child_iterator(const Child &c) : child(c) {}
	const Child* operator->() const {		const Child* operator->() const {
	return &child;		return &child;
	}		}
	bool operator==(const child_iterator &other) const {		bool operator==(const child_iterator &other) const {
	return child == other.child;		return child == other.child;
	}		}
	bool operator!=(const child_iterator &other) const {		bool operator!=(const child_iterator &other) const {
	skipping to change at line 223		skipping to change at line 177
	enum Kind {		enum Kind {
	K_GNU,		K_GNU,
	K_BSD,		K_BSD,
	K_COFF		K_COFF
	};		};
	Kind kind() const {		Kind kind() const {
	return Format;		return Format;
	}		}
	child_iterator begin_children(bool skip_internal = true) const;		child_iterator begin_children(bool SkipInternal = true) const;
	child_iterator end_children() const;		child_iterator end_children() const;
	symbol_iterator begin_symbols() const;		symbol_iterator begin_symbols() const;
	symbol_iterator end_symbols() const;		symbol_iterator end_symbols() const;
	// Cast methods.		// Cast methods.
	static inline bool classof(Binary const *v) {		static inline bool classof(Binary const *v) {
	return v->isArchive();		return v->isArchive();
	}		}
	// check if a symbol is in the archive		// check if a symbol is in the archive
	child_iterator findSym(StringRef name) const;		child_iterator findSym(StringRef name) const;
			bool hasSymbolTable() const;
	private:		private:
	child_iterator SymbolTable;		child_iterator SymbolTable;
	child_iterator StringTable;		child_iterator StringTable;
			child_iterator FirstRegular;
	Kind Format;		Kind Format;
	};		};
	}		}
	}		}
	#endif		#endif
End of changes. 17 change blocks.
	79 lines changed or deleted		33 lines changed or added

	ArgList.h		ArgList.h
	skipping to change at line 225		skipping to change at line 225
	/// @}		/// @}
	/// @name Translation Utilities		/// @name Translation Utilities
	/// @{		/// @{
	/// hasFlag - Given an option \p Pos and its negative form \p Neg, return		/// hasFlag - Given an option \p Pos and its negative form \p Neg, return
	/// true if the option is present, false if the negation is present, and		/// true if the option is present, false if the negation is present, and
	/// \p Default if neither option is given. If both the option and its		/// \p Default if neither option is given. If both the option and its
	/// negation are present, the last one wins.		/// negation are present, the last one wins.
	bool hasFlag(OptSpecifier Pos, OptSpecifier Neg, bool Default=true) const ;		bool hasFlag(OptSpecifier Pos, OptSpecifier Neg, bool Default=true) const ;
			/// hasFlag - Given an option \p Pos, an alias \p PosAlias and its negati
			ve
			/// form \p Neg, return true if the option or its alias is present, false
			if
			/// the negation is present, and \p Default if none of the options are
			/// given. If multiple options are present, the last one wins.
			bool hasFlag(OptSpecifier Pos, OptSpecifier PosAlias, OptSpecifier Neg,
			bool Default = true) const;
	/// AddLastArg - Render only the last argument match \p Id0, if present.		/// AddLastArg - Render only the last argument match \p Id0, if present.
	void AddLastArg(ArgStringList &Output, OptSpecifier Id0) const;		void AddLastArg(ArgStringList &Output, OptSpecifier Id0) const;
			void AddLastArg(ArgStringList &Output, OptSpecifier Id0,
			OptSpecifier Id1) const;
	/// AddAllArgs - Render all arguments matching the given ids.		/// AddAllArgs - Render all arguments matching the given ids.
	void AddAllArgs(ArgStringList &Output, OptSpecifier Id0,		void AddAllArgs(ArgStringList &Output, OptSpecifier Id0,
	OptSpecifier Id1 = 0U, OptSpecifier Id2 = 0U) const;		OptSpecifier Id1 = 0U, OptSpecifier Id2 = 0U) const;
	/// AddAllArgValues - Render the argument values of all arguments		/// AddAllArgValues - Render the argument values of all arguments
	/// matching the given ids.		/// matching the given ids.
	void AddAllArgValues(ArgStringList &Output, OptSpecifier Id0,		void AddAllArgValues(ArgStringList &Output, OptSpecifier Id0,
	OptSpecifier Id1 = 0U, OptSpecifier Id2 = 0U) const ;		OptSpecifier Id1 = 0U, OptSpecifier Id2 = 0U) const ;
End of changes. 2 change blocks.
	0 lines changed or deleted		11 lines changed or added

	Argument.h		Argument.h
	skipping to change at line 85		skipping to change at line 85
	bool hasNoCaptureAttr() const;		bool hasNoCaptureAttr() const;
	/// \brief Return true if this argument has the sret attribute on it in i ts		/// \brief Return true if this argument has the sret attribute on it in i ts
	/// containing function.		/// containing function.
	bool hasStructRetAttr() const;		bool hasStructRetAttr() const;
	/// \brief Return true if this argument has the returned attribute on it in		/// \brief Return true if this argument has the returned attribute on it in
	/// its containing function.		/// its containing function.
	bool hasReturnedAttr() const;		bool hasReturnedAttr() const;
			/// \brief Return true if this argument has the readonly or readnone attr
			ibute
			/// on it in its containing function.
			bool onlyReadsMemory() const;
	/// \brief Add a Attribute to an argument.		/// \brief Add a Attribute to an argument.
	void addAttr(AttributeSet AS);		void addAttr(AttributeSet AS);
	/// \brief Remove a Attribute from an argument.		/// \brief Remove a Attribute from an argument.
	void removeAttr(AttributeSet AS);		void removeAttr(AttributeSet AS);
	/// \brief Method for support type inquiry through isa, cast, and		/// \brief Method for support type inquiry through isa, cast, and
	/// dyn_cast.		/// dyn_cast.
	static inline bool classof(const Value *V) {		static inline bool classof(const Value *V) {
	return V->getValueID() == ArgumentVal;		return V->getValueID() == ArgumentVal;
End of changes. 1 change blocks.
	0 lines changed or deleted		5 lines changed or added

	ArrayRef.h		ArrayRef.h
	skipping to change at line 83		skipping to change at line 83
	: Data(Vec.data()), Length(Vec.size()) {		: Data(Vec.data()), Length(Vec.size()) {
	}		}
	/// Construct an ArrayRef from a std::vector.		/// Construct an ArrayRef from a std::vector.
	template<typename A>		template<typename A>
	/*implicit*/ ArrayRef(const std::vector<T, A> &Vec)		/*implicit*/ ArrayRef(const std::vector<T, A> &Vec)
	: Data(Vec.empty() ? (T*)0 : &Vec[0]), Length(Vec.size()) {}		: Data(Vec.empty() ? (T*)0 : &Vec[0]), Length(Vec.size()) {}
	/// Construct an ArrayRef from a C array.		/// Construct an ArrayRef from a C array.
	template <size_t N>		template <size_t N>
	/*implicit*/ ArrayRef(const T (&Arr)[N])		/*implicit*/ LLVM_CONSTEXPR ArrayRef(const T (&Arr)[N])
	: Data(Arr), Length(N) {}		: Data(Arr), Length(N) {}
			#if LLVM_HAS_INITIALIZER_LISTS
			/// Construct an ArrayRef from a std::initializer_list.
			/*implicit*/ ArrayRef(const std::initializer_list<T> &Vec)
			: Data(Vec.begin() == Vec.end() ? (T*)0 : Vec.begin()),
			Length(Vec.size()) {}
			#endif
	/// @}		/// @}
	/// @name Simple Operations		/// @name Simple Operations
	/// @{		/// @{
	iterator begin() const { return Data; }		iterator begin() const { return Data; }
	iterator end() const { return Data + Length; }		iterator end() const { return Data + Length; }
	reverse_iterator rbegin() const { return reverse_iterator(end()); }		reverse_iterator rbegin() const { return reverse_iterator(end()); }
	reverse_iterator rend() const { return reverse_iterator(begin()); }		reverse_iterator rend() const { return reverse_iterator(begin()); }
	skipping to change at line 181		skipping to change at line 188
	/// extends past that of the MutableArrayRef. For this reason, it is not in		/// extends past that of the MutableArrayRef. For this reason, it is not in
	/// general safe to store a MutableArrayRef.		/// general safe to store a MutableArrayRef.
	///		///
	/// This is intended to be trivially copyable, so it should be passed by		/// This is intended to be trivially copyable, so it should be passed by
	/// value.		/// value.
	template<typename T>		template<typename T>
	class MutableArrayRef : public ArrayRef<T> {		class MutableArrayRef : public ArrayRef<T> {
	public:		public:
	typedef T *iterator;		typedef T *iterator;
			typedef std::reverse_iterator<iterator> reverse_iterator;
	/// Construct an empty MutableArrayRef.		/// Construct an empty MutableArrayRef.
	/*implicit*/ MutableArrayRef() : ArrayRef<T>() {}		/*implicit*/ MutableArrayRef() : ArrayRef<T>() {}
	/// Construct an empty MutableArrayRef from None.		/// Construct an empty MutableArrayRef from None.
	/*implicit*/ MutableArrayRef(NoneType) : ArrayRef<T>() {}		/*implicit*/ MutableArrayRef(NoneType) : ArrayRef<T>() {}
	/// Construct an MutableArrayRef from a single element.		/// Construct an MutableArrayRef from a single element.
	/*implicit*/ MutableArrayRef(T &OneElt) : ArrayRef<T>(OneElt) {}		/*implicit*/ MutableArrayRef(T &OneElt) : ArrayRef<T>(OneElt) {}
	/// Construct an MutableArrayRef from a pointer and length.		/// Construct an MutableArrayRef from a pointer and length.
	skipping to change at line 215		skipping to change at line 224
	/// Construct an MutableArrayRef from a C array.		/// Construct an MutableArrayRef from a C array.
	template <size_t N>		template <size_t N>
	/*implicit*/ MutableArrayRef(T (&Arr)[N])		/*implicit*/ MutableArrayRef(T (&Arr)[N])
	: ArrayRef<T>(Arr) {}		: ArrayRef<T>(Arr) {}
	T *data() const { return const_cast<T*>(ArrayRef<T>::data()); }		T *data() const { return const_cast<T*>(ArrayRef<T>::data()); }
	iterator begin() const { return data(); }		iterator begin() const { return data(); }
	iterator end() const { return data() + this->size(); }		iterator end() const { return data() + this->size(); }
			reverse_iterator rbegin() const { return reverse_iterator(end()); }
			reverse_iterator rend() const { return reverse_iterator(begin()); }
	/// front - Get the first element.		/// front - Get the first element.
	T &front() const {		T &front() const {
	assert(!this->empty());		assert(!this->empty());
	return data()[0];		return data()[0];
	}		}
	/// back - Get the last element.		/// back - Get the last element.
	T &back() const {		T &back() const {
	assert(!this->empty());		assert(!this->empty());
	return data()[this->size()-1];		return data()[this->size()-1];
End of changes. 4 change blocks.
	1 lines changed or deleted		13 lines changed or added

	AsmLexer.h		AsmLexer.h
	skipping to change at line 66		skipping to change at line 66
	int getNextChar();		int getNextChar();
	AsmToken ReturnError(const char *Loc, const std::string &Msg);		AsmToken ReturnError(const char *Loc, const std::string &Msg);
	AsmToken LexIdentifier();		AsmToken LexIdentifier();
	AsmToken LexSlash();		AsmToken LexSlash();
	AsmToken LexLineComment();		AsmToken LexLineComment();
	AsmToken LexDigit();		AsmToken LexDigit();
	AsmToken LexSingleQuote();		AsmToken LexSingleQuote();
	AsmToken LexQuote();		AsmToken LexQuote();
	AsmToken LexFloatLiteral();		AsmToken LexFloatLiteral();
			AsmToken LexHexFloatLiteral(bool NoIntDigits);
	};		};
	} // end namespace llvm		} // end namespace llvm
	#endif		#endif
End of changes. 1 change blocks.
	0 lines changed or deleted		1 lines changed or added

	AsmParsers.def		AsmParsers.def
	skipping to change at line 27		skipping to change at line 27
	|* The set of targets supported by LLVM is generated at configuration *|		|* The set of targets supported by LLVM is generated at configuration *|
	|* time, at which point this header is generated. Do not modify this *|		|* time, at which point this header is generated. Do not modify this *|
	|* header directly. *|		|* header directly. *|
	|* *|		|* *|
	\*===---------------------------------------------------------------------- ===*/		\*===---------------------------------------------------------------------- ===*/
	#ifndef LLVM_ASM_PARSER		#ifndef LLVM_ASM_PARSER
	# error Please define the macro LLVM_ASM_PARSER(TargetName)		# error Please define the macro LLVM_ASM_PARSER(TargetName)
	#endif		#endif
	LLVM_ASM_PARSER(SystemZ) LLVM_ASM_PARSER(MBlaze) LLVM_ASM_PARSER(Mips) LLVM _ASM_PARSER(ARM) LLVM_ASM_PARSER(AArch64) LLVM_ASM_PARSER(PowerPC) LLVM_ASM _PARSER(X86)		LLVM_ASM_PARSER(SystemZ) LLVM_ASM_PARSER(Mips) LLVM_ASM_PARSER(ARM) LLVM_AS M_PARSER(AArch64) LLVM_ASM_PARSER(PowerPC) LLVM_ASM_PARSER(X86)
	#undef LLVM_ASM_PARSER		#undef LLVM_ASM_PARSER
End of changes. 1 change blocks.
	1 lines changed or deleted		1 lines changed or added

	AsmPrinter.h		AsmPrinter.h
	skipping to change at line 41		skipping to change at line 41
	class GlobalVariable;		class GlobalVariable;
	class MachineBasicBlock;		class MachineBasicBlock;
	class MachineFunction;		class MachineFunction;
	class MachineInstr;		class MachineInstr;
	class MachineLocation;		class MachineLocation;
	class MachineLoopInfo;		class MachineLoopInfo;
	class MachineLoop;		class MachineLoop;
	class MachineConstantPoolValue;		class MachineConstantPoolValue;
	class MachineJumpTableInfo;		class MachineJumpTableInfo;
	class MachineModuleInfo;		class MachineModuleInfo;
	class MachineMove;
	class MCAsmInfo;		class MCAsmInfo;
			class MCCFIInstruction;
	class MCContext;		class MCContext;
			class MCInstrInfo;
	class MCSection;		class MCSection;
	class MCStreamer;		class MCStreamer;
	class MCSymbol;		class MCSymbol;
	class MDNode;		class MDNode;
	class DwarfDebug;		class DwarfDebug;
	class DwarfException;		class DwarfException;
	class Mangler;		class Mangler;
	class TargetLoweringObjectFile;		class TargetLoweringObjectFile;
	class DataLayout;		class DataLayout;
	class TargetMachine;		class TargetMachine;
	skipping to change at line 67		skipping to change at line 68
	class AsmPrinter : public MachineFunctionPass {		class AsmPrinter : public MachineFunctionPass {
	public:		public:
	/// Target machine description.		/// Target machine description.
	///		///
	TargetMachine &TM;		TargetMachine &TM;
	/// Target Asm Printer information.		/// Target Asm Printer information.
	///		///
	const MCAsmInfo *MAI;		const MCAsmInfo *MAI;
			const MCInstrInfo *MII;
	/// OutContext - This is the context for the output file that we are		/// OutContext - This is the context for the output file that we are
	/// streaming. This owns all of the global MC-related objects for the		/// streaming. This owns all of the global MC-related objects for the
	/// generated translation unit.		/// generated translation unit.
	MCContext &OutContext;		MCContext &OutContext;
	/// OutStreamer - This is the MCStreamer object for the file we are		/// OutStreamer - This is the MCStreamer object for the file we are
	/// generating. This contains the transient state for the current		/// generating. This contains the transient state for the current
	/// translation unit that we are generating (such as the current sectio n		/// translation unit that we are generating (such as the current sectio n
	/// etc).		/// etc).
	MCStreamer &OutStreamer;		MCStreamer &OutStreamer;
	skipping to change at line 124		skipping to change at line 126
	/// DE - If the target supports dwarf exception info, this pointer is		/// DE - If the target supports dwarf exception info, this pointer is
	/// non-null.		/// non-null.
	DwarfException *DE;		DwarfException *DE;
	protected:		protected:
	explicit AsmPrinter(TargetMachine &TM, MCStreamer &Streamer);		explicit AsmPrinter(TargetMachine &TM, MCStreamer &Streamer);
	public:		public:
	virtual ~AsmPrinter();		virtual ~AsmPrinter();
			const DwarfDebug *getDwarfDebug() const { return DD; }
	/// isVerbose - Return true if assembly output should contain comments.		/// isVerbose - Return true if assembly output should contain comments.
	///		///
	bool isVerbose() const { return VerboseAsm; }		bool isVerbose() const { return VerboseAsm; }
	/// getFunctionNumber - Return a unique ID for the current function.		/// getFunctionNumber - Return a unique ID for the current function.
	///		///
	unsigned getFunctionNumber() const;		unsigned getFunctionNumber() const;
	/// getObjFileLowering - Return information about object file lowering.		/// getObjFileLowering - Return information about object file lowering.
	const TargetLoweringObjectFile &getObjFileLowering() const;		const TargetLoweringObjectFile &getObjFileLowering() const;
	/// getDataLayout - Return information about data layout.		/// getDataLayout - Return information about data layout.
	const DataLayout &getDataLayout() const;		const DataLayout &getDataLayout() const;
	/// getTargetTriple - Return the target triple string.		/// getTargetTriple - Return the target triple string.
	StringRef getTargetTriple() const;		StringRef getTargetTriple() const;
	/// getCurrentSection() - Return the current section we are emitting to .		/// getCurrentSection() - Return the current section we are emitting to .
	const MCSection *getCurrentSection() const;		const MCSection *getCurrentSection() const;
			MCSymbol *getSymbol(const GlobalValue *GV) const;
	//===------------------------------------------------------------------ ===//		//===------------------------------------------------------------------ ===//
	// MachineFunctionPass Implementation.		// MachineFunctionPass Implementation.
	//===------------------------------------------------------------------ ===//		//===------------------------------------------------------------------ ===//
	/// getAnalysisUsage - Record analysis usage.		/// getAnalysisUsage - Record analysis usage.
	///		///
	void getAnalysisUsage(AnalysisUsage &AU) const;		void getAnalysisUsage(AnalysisUsage &AU) const;
	/// doInitialization - Set up the AsmPrinter when we are working on a n ew		/// doInitialization - Set up the AsmPrinter when we are working on a n ew
	/// module. If your pass overrides this, it must make sure to explicit ly		/// module. If your pass overrides this, it must make sure to explicit ly
	skipping to change at line 235		skipping to change at line 241
	/// an explicit alignment requested, it will override the alignment req uest		/// an explicit alignment requested, it will override the alignment req uest
	/// if required for correctness.		/// if required for correctness.
	///		///
	void EmitAlignment(unsigned NumBits, const GlobalValue *GV = 0) const;		void EmitAlignment(unsigned NumBits, const GlobalValue *GV = 0) const;
	/// EmitBasicBlockStart - This method prints the label for the specifie d		/// EmitBasicBlockStart - This method prints the label for the specifie d
	/// MachineBasicBlock, an alignment (if present) and a comment describi ng		/// MachineBasicBlock, an alignment (if present) and a comment describi ng
	/// it if appropriate.		/// it if appropriate.
	void EmitBasicBlockStart(const MachineBasicBlock *MBB) const;		void EmitBasicBlockStart(const MachineBasicBlock *MBB) const;
	/// EmitGlobalConstant - Print a general LLVM constant to the .s file.		/// \brief Print a general LLVM constant to the .s file.
	void EmitGlobalConstant(const Constant *CV, unsigned AddrSpace = 0);		void EmitGlobalConstant(const Constant *CV);
	//===------------------------------------------------------------------ ===//		//===------------------------------------------------------------------ ===//
	// Overridable Hooks		// Overridable Hooks
	//===------------------------------------------------------------------ ===//		//===------------------------------------------------------------------ ===//
	// Targets can, or in the case of EmitInstruction, must implement these to		// Targets can, or in the case of EmitInstruction, must implement these to
	// customize output.		// customize output.
	/// EmitStartOfAsmFile - This virtual method can be overridden by targe ts		/// EmitStartOfAsmFile - This virtual method can be overridden by targe ts
	/// that want to emit something at the start of their file.		/// that want to emit something at the start of their file.
	skipping to change at line 283		skipping to change at line 289
	virtual void EmitXXStructor(const Constant *CV) {		virtual void EmitXXStructor(const Constant *CV) {
	EmitGlobalConstant(CV);		EmitGlobalConstant(CV);
	}		}
	/// isBlockOnlyReachableByFallthough - Return true if the basic block h as		/// isBlockOnlyReachableByFallthough - Return true if the basic block h as
	/// exactly one predecessor and the control transfer mechanism between		/// exactly one predecessor and the control transfer mechanism between
	/// the predecessor and this block is a fall-through.		/// the predecessor and this block is a fall-through.
	virtual bool		virtual bool
	isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const;		isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const;
			/// emitImplicitDef - Targets can override this to customize the output
			of
			/// IMPLICIT_DEF instructions in verbose mode.
			virtual void emitImplicitDef(const MachineInstr *MI) const;
	//===------------------------------------------------------------------ ===//		//===------------------------------------------------------------------ ===//
	// Symbol Lowering Routines.		// Symbol Lowering Routines.
	//===------------------------------------------------------------------ ===//		//===------------------------------------------------------------------ ===//
	public:		public:
	/// GetTempSymbol - Return the MCSymbol corresponding to the assembler		/// GetTempSymbol - Return the MCSymbol corresponding to the assembler
	/// temporary label with the specified stem and unique ID.		/// temporary label with the specified stem and unique ID.
	MCSymbol *GetTempSymbol(StringRef Name, unsigned ID) const;		MCSymbol *GetTempSymbol(StringRef Name, unsigned ID) const;
	/// GetTempSymbol - Return an assembler temporary label with the specif ied		/// GetTempSymbol - Return an assembler temporary label with the specif ied
	skipping to change at line 357		skipping to change at line 367
	/// EmitLabelOffsetDifference - Emit something like ".long Hi+Offset-Lo "		/// EmitLabelOffsetDifference - Emit something like ".long Hi+Offset-Lo "
	/// where the size in bytes of the directive is specified by Size and H i/Lo		/// where the size in bytes of the directive is specified by Size and H i/Lo
	/// specify the labels. This implicitly uses .set if it is available.		/// specify the labels. This implicitly uses .set if it is available.
	void EmitLabelOffsetDifference(const MCSymbol *Hi, uint64_t Offset,		void EmitLabelOffsetDifference(const MCSymbol *Hi, uint64_t Offset,
	const MCSymbol *Lo, unsigned Size) const ;		const MCSymbol *Lo, unsigned Size) const ;
	/// EmitLabelPlusOffset - Emit something like ".long Label+Offset"		/// EmitLabelPlusOffset - Emit something like ".long Label+Offset"
	/// where the size in bytes of the directive is specified by Size and L abel		/// where the size in bytes of the directive is specified by Size and L abel
	/// specifies the label. This implicitly uses .set if it is available.		/// specifies the label. This implicitly uses .set if it is available.
	void EmitLabelPlusOffset(const MCSymbol *Label, uint64_t Offset,		void EmitLabelPlusOffset(const MCSymbol *Label, uint64_t Offset,
	unsigned Size) const;		unsigned Size,
			bool IsSectionRelative = false) const;
	/// EmitLabelReference - Emit something like ".long Label"		/// EmitLabelReference - Emit something like ".long Label"
	/// where the size in bytes of the directive is specified by Size and L abel		/// where the size in bytes of the directive is specified by Size and L abel
	/// specifies the label.		/// specifies the label.
	void EmitLabelReference(const MCSymbol *Label, unsigned Size) const {		void EmitLabelReference(const MCSymbol *Label, unsigned Size,
	EmitLabelPlusOffset(Label, 0, Size);		bool IsSectionRelative = false) const {
			EmitLabelPlusOffset(Label, 0, Size, IsSectionRelative);
	}		}
	//===------------------------------------------------------------------ ===//		//===------------------------------------------------------------------ ===//
	// Dwarf Emission Helper Routines		// Dwarf Emission Helper Routines
	//===------------------------------------------------------------------ ===//		//===------------------------------------------------------------------ ===//
	/// EmitSLEB128 - emit the specified signed leb128 value.		/// EmitSLEB128 - emit the specified signed leb128 value.
	void EmitSLEB128(int Value, const char *Desc = 0) const;		void EmitSLEB128(int64_t Value, const char *Desc = 0) const;
	/// EmitULEB128 - emit the specified unsigned leb128 value.		/// EmitULEB128 - emit the specified unsigned leb128 value.
	void EmitULEB128(unsigned Value, const char *Desc = 0,		void EmitULEB128(uint64_t Value, const char *Desc = 0,
	unsigned PadTo = 0) const;		unsigned PadTo = 0) const;
	/// EmitCFAByte - Emit a .byte 42 directive for a DW_CFA_xxx value.		/// EmitCFAByte - Emit a .byte 42 directive for a DW_CFA_xxx value.
	void EmitCFAByte(unsigned Val) const;		void EmitCFAByte(unsigned Val) const;
	/// EmitEncodingByte - Emit a .byte 42 directive that corresponds to an		/// EmitEncodingByte - Emit a .byte 42 directive that corresponds to an
	/// encoding. If verbose assembly output is enabled, we output comment s		/// encoding. If verbose assembly output is enabled, we output comment s
	/// describing the encoding. Desc is a string saying what the encoding is		/// describing the encoding. Desc is a string saying what the encoding is
	/// specifying (e.g. "LSDA").		/// specifying (e.g. "LSDA").
	void EmitEncodingByte(unsigned Val, const char *Desc = 0) const;		void EmitEncodingByte(unsigned Val, const char *Desc = 0) const;
	skipping to change at line 402		skipping to change at line 414
	/// EmitSectionOffset - Emit the 4-byte offset of Label from the start of		/// EmitSectionOffset - Emit the 4-byte offset of Label from the start of
	/// its section. This can be done with a special directive if the targ et		/// its section. This can be done with a special directive if the targ et
	/// supports it (e.g. cygwin) or by emitting it as an offset from a lab el at		/// supports it (e.g. cygwin) or by emitting it as an offset from a lab el at
	/// the start of the section.		/// the start of the section.
	///		///
	/// SectionLabel is a temporary label emitted at the start of the secti on		/// SectionLabel is a temporary label emitted at the start of the secti on
	/// that Label lives in.		/// that Label lives in.
	void EmitSectionOffset(const MCSymbol *Label,		void EmitSectionOffset(const MCSymbol *Label,
	const MCSymbol *SectionLabel) const;		const MCSymbol *SectionLabel) const;
	/// getDebugValueLocation - Get location information encoded by DBG_VAL
	UE
	/// operands.
	virtual MachineLocation getDebugValueLocation(const MachineInstr *MI) c
	onst;
	/// getISAEncoding - Get the value for DW_AT_APPLE_isa. Zero if no isa		/// getISAEncoding - Get the value for DW_AT_APPLE_isa. Zero if no isa
	/// encoding specified.		/// encoding specified.
	virtual unsigned getISAEncoding() { return 0; }		virtual unsigned getISAEncoding() { return 0; }
	/// EmitDwarfRegOp - Emit dwarf register operation.		/// EmitDwarfRegOp - Emit dwarf register operation.
	virtual void EmitDwarfRegOp(const MachineLocation &MLoc) const;		virtual void EmitDwarfRegOp(const MachineLocation &MLoc,
			bool Indirect) const;
	//===------------------------------------------------------------------ ===//		//===------------------------------------------------------------------ ===//
	// Dwarf Lowering Routines		// Dwarf Lowering Routines
	//===------------------------------------------------------------------ ===//		//===------------------------------------------------------------------ ===//
	/// EmitCFIFrameMove - Emit frame instruction to describe the layout of		/// \brief Emit frame instruction to describe the layout of the frame.
	the		void emitCFIInstruction(const MCCFIInstruction &Inst) const;
	/// frame.
	void EmitCFIFrameMove(const MachineMove &Move) const;
	//===------------------------------------------------------------------ ===//		//===------------------------------------------------------------------ ===//
	// Inline Asm Support		// Inline Asm Support
	//===------------------------------------------------------------------ ===//		//===------------------------------------------------------------------ ===//
	public:		public:
	// These are hooks that targets can override to implement inline asm		// These are hooks that targets can override to implement inline asm
	// support. These should probably be moved out of AsmPrinter someday.		// support. These should probably be moved out of AsmPrinter someday.
	/// PrintSpecial - Print information related to the specified machine i nstr		/// PrintSpecial - Print information related to the specified machine i nstr
	/// that is independent of the operand, and may be independent of the i nstr		/// that is independent of the operand, and may be independent of the i nstr
	skipping to change at line 451		skipping to change at line 459
	virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,		virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
	unsigned AsmVariant, const char *ExtraCode ,		unsigned AsmVariant, const char *ExtraCode ,
	raw_ostream &OS);		raw_ostream &OS);
	/// PrintAsmMemoryOperand - Print the specified operand of MI, an INLIN EASM		/// PrintAsmMemoryOperand - Print the specified operand of MI, an INLIN EASM
	/// instruction, using the specified assembler variant as an address.		/// instruction, using the specified assembler variant as an address.
	/// Targets should override this to format as appropriate. This method can		/// Targets should override this to format as appropriate. This method can
	/// return true if the operand is erroneous.		/// return true if the operand is erroneous.
	virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpN o,		virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpN o,
	unsigned AsmVariant,		unsigned AsmVariant,
	const char *ExtraCode,		const char *ExtraCode, raw_ostream &
	raw_ostream &OS);		OS);
	private:		private:
	/// Private state for PrintSpecial()		/// Private state for PrintSpecial()
	// Assign a unique ID to this machine instruction.		// Assign a unique ID to this machine instruction.
	mutable const MachineInstr *LastMI;		mutable const MachineInstr *LastMI;
	mutable unsigned LastFn;		mutable unsigned LastFn;
	mutable unsigned Counter;		mutable unsigned Counter;
	mutable unsigned SetCounter;		mutable unsigned SetCounter;
	/// EmitInlineAsm - Emit a blob of inline asm to the output streamer.		/// EmitInlineAsm - Emit a blob of inline asm to the output streamer.
	void EmitInlineAsm(StringRef Str, const MDNode *LocMDNode = 0,		void EmitInlineAsm(StringRef Str, const MDNode *LocMDNode = 0,
	InlineAsm::AsmDialect AsmDialect = InlineAsm::AD_ATT) c		InlineAsm::AsmDialect AsmDialect =
	onst;		InlineAsm::AD_ATT) const;
	/// EmitInlineAsm - This method formats and emits the specified machine		/// EmitInlineAsm - This method formats and emits the specified machine
	/// instruction that is an inline asm.		/// instruction that is an inline asm.
	void EmitInlineAsm(const MachineInstr *MI) const;		void EmitInlineAsm(const MachineInstr *MI) const;
	//===------------------------------------------------------------------ ===//		//===------------------------------------------------------------------ ===//
	// Internal Implementation Details		// Internal Implementation Details
	//===------------------------------------------------------------------ ===//		//===------------------------------------------------------------------ ===//
	/// EmitVisibility - This emits visibility information about symbol, if		/// EmitVisibility - This emits visibility information about symbol, if
	/// this is suported by the target.		/// this is suported by the target.
	void EmitVisibility(MCSymbol *Sym, unsigned Visibility,		void EmitVisibility(MCSymbol *Sym, unsigned Visibility,
	bool IsDefinition = true) const;		bool IsDefinition = true) const;
	void EmitLinkage(unsigned Linkage, MCSymbol *GVSym) const;		void EmitLinkage(const GlobalValue *GV, MCSymbol *GVSym) const;
	void EmitJumpTableEntry(const MachineJumpTableInfo *MJTI,		void EmitJumpTableEntry(const MachineJumpTableInfo *MJTI,
	const MachineBasicBlock *MBB,		const MachineBasicBlock *MBB, unsigned uid) con
	unsigned uid) const;		st;
	void EmitLLVMUsedList(const ConstantArray *InitList);		void EmitLLVMUsedList(const ConstantArray *InitList);
			/// Emit llvm.ident metadata in an '.ident' directive.
			void EmitModuleIdents(Module &M);
	void EmitXXStructorList(const Constant *List, bool isCtor);		void EmitXXStructorList(const Constant *List, bool isCtor);
	GCMetadataPrinter *GetOrCreateGCPrinter(GCStrategy *C);		GCMetadataPrinter *GetOrCreateGCPrinter(GCStrategy *C);
	};		};
	}		}
	#endif		#endif
End of changes. 20 change blocks.
	26 lines changed or deleted		34 lines changed or added

	AsmPrinters.def		AsmPrinters.def
	skipping to change at line 27		skipping to change at line 27
	|* The set of targets supported by LLVM is generated at configuration *|		|* The set of targets supported by LLVM is generated at configuration *|
	|* time, at which point this header is generated. Do not modify this *|		|* time, at which point this header is generated. Do not modify this *|
	|* header directly. *|		|* header directly. *|
	|* *|		|* *|
	\*===---------------------------------------------------------------------- ===*/		\*===---------------------------------------------------------------------- ===*/
	#ifndef LLVM_ASM_PRINTER		#ifndef LLVM_ASM_PRINTER
	# error Please define the macro LLVM_ASM_PRINTER(TargetName)		# error Please define the macro LLVM_ASM_PRINTER(TargetName)
	#endif		#endif
	LLVM_ASM_PRINTER(SystemZ) LLVM_ASM_PRINTER(Hexagon) LLVM_ASM_PRINTER(NVPTX) LLVM_ASM_PRINTER(MBlaze) LLVM_ASM_PRINTER(MSP430) LLVM_ASM_PRINTER(XCore) LLVM_ASM_PRINTER(Mips) LLVM_ASM_PRINTER(ARM) LLVM_ASM_PRINTER(AArch64) LLVM _ASM_PRINTER(PowerPC) LLVM_ASM_PRINTER(Sparc) LLVM_ASM_PRINTER(X86)		LLVM_ASM_PRINTER(R600) LLVM_ASM_PRINTER(SystemZ) LLVM_ASM_PRINTER(Hexagon) LLVM_ASM_PRINTER(NVPTX) LLVM_ASM_PRINTER(MSP430) LLVM_ASM_PRINTER(XCore) LL VM_ASM_PRINTER(Mips) LLVM_ASM_PRINTER(ARM) LLVM_ASM_PRINTER(AArch64) LLVM_A SM_PRINTER(PowerPC) LLVM_ASM_PRINTER(Sparc) LLVM_ASM_PRINTER(X86)
	#undef LLVM_ASM_PRINTER		#undef LLVM_ASM_PRINTER
End of changes. 1 change blocks.
	1 lines changed or deleted		1 lines changed or added

	Attributes.h		Attributes.h
	skipping to change at line 21		skipping to change at line 21
	/// \brief This file contains the simple types necessary to represent the		/// \brief This file contains the simple types necessary to represent the
	/// attributes associated with functions and their calls.		/// attributes associated with functions and their calls.
	///		///
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_IR_ATTRIBUTES_H		#ifndef LLVM_IR_ATTRIBUTES_H
	#define LLVM_IR_ATTRIBUTES_H		#define LLVM_IR_ATTRIBUTES_H
	#include "llvm/ADT/ArrayRef.h"		#include "llvm/ADT/ArrayRef.h"
	#include "llvm/ADT/FoldingSet.h"		#include "llvm/ADT/FoldingSet.h"
			#include "llvm/Support/Compiler.h"
	#include "llvm/Support/PointerLikeTypeTraits.h"		#include "llvm/Support/PointerLikeTypeTraits.h"
	#include <bitset>		#include <bitset>
	#include <cassert>		#include <cassert>
	#include <map>		#include <map>
	#include <string>		#include <string>
	namespace llvm {		namespace llvm {
	class AttrBuilder;		class AttrBuilder;
	class AttributeImpl;		class AttributeImpl;
	skipping to change at line 70		skipping to change at line 71
	/// an exception might pass by.		/// an exception might pass by.
	/// uwtable + nounwind = Needs an entry because the ABI says so.		/// uwtable + nounwind = Needs an entry because the ABI says so.
	enum AttrKind {		enum AttrKind {
	// IR-Level Attributes		// IR-Level Attributes
	None, ///< No attributes have been set		None, ///< No attributes have been set
	Alignment, ///< Alignment of parameter (5 bits)		Alignment, ///< Alignment of parameter (5 bits)
	///< stored as log2 of alignment with +1 bias		///< stored as log2 of alignment with +1 bias
	///< 0 means unaligned (different from align(1))		///< 0 means unaligned (different from align(1))
	AlwaysInline, ///< inline=always		AlwaysInline, ///< inline=always
			Builtin, ///< Callee is recognized as a builtin, despite
			///< nobuiltin attribute on its declaration.
	ByVal, ///< Pass structure by value		ByVal, ///< Pass structure by value
			Cold, ///< Marks function as being in a cold path.
	InlineHint, ///< Source said inlining was desirable		InlineHint, ///< Source said inlining was desirable
	InReg, ///< Force argument to be passed in register		InReg, ///< Force argument to be passed in register
	MinSize, ///< Function must be optimized for size first		MinSize, ///< Function must be optimized for size first
	Naked, ///< Naked function		Naked, ///< Naked function
	Nest, ///< Nested function static chain		Nest, ///< Nested function static chain
	NoAlias, ///< Considered to not alias after call		NoAlias, ///< Considered to not alias after call
	NoBuiltin, ///< Callee isn't recognized as a builtin		NoBuiltin, ///< Callee isn't recognized as a builtin
	NoCapture, ///< Function creates no aliases of pointer		NoCapture, ///< Function creates no aliases of pointer
	NoDuplicate, ///< Call cannot be duplicated		NoDuplicate, ///< Call cannot be duplicated
	NoImplicitFloat, ///< Disable implicit floating point insts		NoImplicitFloat, ///< Disable implicit floating point insts
	NoInline, ///< inline=never		NoInline, ///< inline=never
	NonLazyBind, ///< Function is called early and/or		NonLazyBind, ///< Function is called early and/or
	///< often, so lazy binding isn't worthwhile		///< often, so lazy binding isn't worthwhile
	NoRedZone, ///< Disable redzone		NoRedZone, ///< Disable redzone
	NoReturn, ///< Mark the function as not returning		NoReturn, ///< Mark the function as not returning
	NoUnwind, ///< Function doesn't unwind stack		NoUnwind, ///< Function doesn't unwind stack
	OptimizeForSize, ///< opt_size		OptimizeForSize, ///< opt_size
			OptimizeNone, ///< Function must not be optimized.
	ReadNone, ///< Function does not access memory		ReadNone, ///< Function does not access memory
	ReadOnly, ///< Function only reads from memory		ReadOnly, ///< Function only reads from memory
	Returned, ///< Return value is always equal to this argume nt		Returned, ///< Return value is always equal to this argume nt
	ReturnsTwice, ///< Function can return twice		ReturnsTwice, ///< Function can return twice
	SExt, ///< Sign extended before/after call		SExt, ///< Sign extended before/after call
	StackAlignment, ///< Alignment of stack for function (3 bits)		StackAlignment, ///< Alignment of stack for function (3 bits)
	///< stored as log2 of alignment with +1 bias 0		///< stored as log2 of alignment with +1 bias 0
	///< means unaligned (different from		///< means unaligned (different from
	///< alignstack=(1))		///< alignstack=(1))
	StackProtect, ///< Stack protection.		StackProtect, ///< Stack protection.
	skipping to change at line 199		skipping to change at line 204
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	/// \class		/// \class
	/// \brief This class holds the attributes for a function, its return value , and		/// \brief This class holds the attributes for a function, its return value , and
	/// its parameters. You access the attributes for each of them via an index into		/// its parameters. You access the attributes for each of them via an index into
	/// the AttributeSet object. The function attributes are at index		/// the AttributeSet object. The function attributes are at index
	/// `AttributeSet::FunctionIndex', the return value is at index		/// `AttributeSet::FunctionIndex', the return value is at index
	/// `AttributeSet::ReturnIndex', and the attributes for the parameters star t at		/// `AttributeSet::ReturnIndex', and the attributes for the parameters star t at
	/// index `1'.		/// index `1'.
	class AttributeSet {		class AttributeSet {
	public:		public:
	enum AttrIndex {		enum AttrIndex LLVM_ENUM_INT_TYPE(unsigned) {
	ReturnIndex = 0U,		ReturnIndex = 0U,
	FunctionIndex = ~0U		FunctionIndex = ~0U
	};		};
	private:		private:
	friend class AttrBuilder;		friend class AttrBuilder;
	friend class AttributeSetImpl;		friend class AttributeSetImpl;
	template <typename Ty> friend struct DenseMapInfo;		template <typename Ty> friend struct DenseMapInfo;
	/// \brief The attributes that we are managing. This can be null to repre sent		/// \brief The attributes that we are managing. This can be null to repre sent
	/// the empty attributes list.		/// the empty attributes list.
	skipping to change at line 249		skipping to change at line 254
	/// \brief Add an attribute to the attribute set at the given index. Sinc e		/// \brief Add an attribute to the attribute set at the given index. Sinc e
	/// attribute sets are immutable, this returns a new set.		/// attribute sets are immutable, this returns a new set.
	AttributeSet addAttribute(LLVMContext &C, unsigned Index,		AttributeSet addAttribute(LLVMContext &C, unsigned Index,
	Attribute::AttrKind Attr) const;		Attribute::AttrKind Attr) const;
	/// \brief Add an attribute to the attribute set at the given index. Sinc e		/// \brief Add an attribute to the attribute set at the given index. Sinc e
	/// attribute sets are immutable, this returns a new set.		/// attribute sets are immutable, this returns a new set.
	AttributeSet addAttribute(LLVMContext &C, unsigned Index,		AttributeSet addAttribute(LLVMContext &C, unsigned Index,
	StringRef Kind) const;		StringRef Kind) const;
			AttributeSet addAttribute(LLVMContext &C, unsigned Index,
			StringRef Kind, StringRef Value) const;
	/// \brief Add attributes to the attribute set at the given index. Since		/// \brief Add attributes to the attribute set at the given index. Since
	/// attribute sets are immutable, this returns a new set.		/// attribute sets are immutable, this returns a new set.
	AttributeSet addAttributes(LLVMContext &C, unsigned Index,		AttributeSet addAttributes(LLVMContext &C, unsigned Index,
	AttributeSet Attrs) const;		AttributeSet Attrs) const;
	/// \brief Remove the specified attribute at the specified index from thi s		/// \brief Remove the specified attribute at the specified index from thi s
	/// attribute list. Since attribute lists are immutable, this returns the new		/// attribute list. Since attribute lists are immutable, this returns the new
	/// list.		/// list.
	AttributeSet removeAttribute(LLVMContext &C, unsigned Index,		AttributeSet removeAttribute(LLVMContext &C, unsigned Index,
End of changes. 6 change blocks.
	1 lines changed or deleted		8 lines changed or added

	AutoUpgrade.h		AutoUpgrade.h
	//===-- llvm/AutoUpgrade.h - AutoUpgrade Helpers ----------------*- C++ -*- ===//		//===-- llvm/AutoUpgrade.h - AutoUpgrade Helpers ----------------*- C++ -*- ===//
	//		//
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// These functions are implemented by lib/VMCore/AutoUpgrade.cpp.		// These functions are implemented by lib/IR/AutoUpgrade.cpp.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_AUTOUPGRADE_H		#ifndef LLVM_AUTOUPGRADE_H
	#define LLVM_AUTOUPGRADE_H		#define LLVM_AUTOUPGRADE_H
	namespace llvm {		namespace llvm {
			class CallInst;
			class Constant;
			class Function;
			class Instruction;
	class Module;		class Module;
	class GlobalVariable;		class GlobalVariable;
	class Function;		class Type;
	class CallInst;		class Value;
	/// This is a more granular function that simply checks an intrinsic func tion		/// This is a more granular function that simply checks an intrinsic func tion
	/// for upgrading, and returns true if it requires upgrading. It may retu rn		/// for upgrading, and returns true if it requires upgrading. It may retu rn
	/// null in NewFn if the all calls to the original intrinsic function		/// null in NewFn if the all calls to the original intrinsic function
	/// should be transformed to non-function-call instructions.		/// should be transformed to non-function-call instructions.
	bool UpgradeIntrinsicFunction(Function *F, Function *&NewFn);		bool UpgradeIntrinsicFunction(Function *F, Function *&NewFn);
	/// This is the complement to the above, replacing a specific call to an		/// This is the complement to the above, replacing a specific call to an
	/// intrinsic function with a call to the specified new function.		/// intrinsic function with a call to the specified new function.
	void UpgradeIntrinsicCall(CallInst *CI, Function *NewFn);		void UpgradeIntrinsicCall(CallInst *CI, Function *NewFn);
	/// This is an auto-upgrade hook for any old intrinsic function syntaxes		/// This is an auto-upgrade hook for any old intrinsic function syntaxes
	/// which need to have both the function updated as well as all calls upd ated		/// which need to have both the function updated as well as all calls upd ated
	/// to the new function. This should only be run in a post-processing fas hion		/// to the new function. This should only be run in a post-processing fas hion
	/// so that it can update all calls to the old function.		/// so that it can update all calls to the old function.
	void UpgradeCallsToIntrinsic(Function* F);		void UpgradeCallsToIntrinsic(Function* F);
	/// This checks for global variables which should be upgraded. It returns true		/// This checks for global variables which should be upgraded. It returns true
	/// if it requires upgrading.		/// if it requires upgrading.
	bool UpgradeGlobalVariable(GlobalVariable *GV);		bool UpgradeGlobalVariable(GlobalVariable *GV);
			/// If the TBAA tag for the given instruction uses the scalar TBAA format
			,
			/// we upgrade it to the struct-path aware TBAA format.
			void UpgradeInstWithTBAATag(Instruction *I);
			/// This is an auto-upgrade for bitcast between pointers with different
			/// address spaces: the instruction is replaced by a pair ptrtoint+inttop
			tr.
			Instruction *UpgradeBitCastInst(unsigned Opc, Value *V, Type *DestTy,
			Instruction *&Temp);
			/// This is an auto-upgrade for bitcast constant expression between point
			ers
			/// with different address spaces: the instruction is replaced by a pair
			/// ptrtoint+inttoptr.
			Value *UpgradeBitCastExpr(unsigned Opc, Constant *C, Type *DestTy);
			/// Check the debug info version number, if it is out-dated, drop the deb
			ug
			/// info. Return true if module is modified.
			bool UpgradeDebugInfo(Module &M);
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 4 change blocks.
	3 lines changed or deleted		29 lines changed or added

	BasicBlockUtils.h		BasicBlockUtils.h
	skipping to change at line 72		skipping to change at line 72
	// updated to point to the new instruction.		// updated to point to the new instruction.
	//		//
	void ReplaceInstWithInst(BasicBlock::InstListType &BIL,		void ReplaceInstWithInst(BasicBlock::InstListType &BIL,
	BasicBlock::iterator &BI, Instruction *I);		BasicBlock::iterator &BI, Instruction *I);
	// ReplaceInstWithInst - Replace the instruction specified by From with the		// ReplaceInstWithInst - Replace the instruction specified by From with the
	// instruction specified by To.		// instruction specified by To.
	//		//
	void ReplaceInstWithInst(Instruction *From, Instruction *To);		void ReplaceInstWithInst(Instruction *From, Instruction *To);
	/// FindFunctionBackedges - Analyze the specified function to find all of t
	he
	/// loop backedges in the function and return them. This is a relatively c
	heap
	/// (compared to computing dominators and loop info) analysis.
	///
	/// The output is added to Result, as pairs of <from,to> edge info.
	void FindFunctionBackedges(const Function &F,
	SmallVectorImpl<std::pair<const BasicBlock*,const BasicBlock*> > &Res
	ult);
	/// GetSuccessorNumber - Search for the specified successor of basic block
	BB
	/// and return its position in the terminator instruction's list of
	/// successors. It is an error to call this with a block that is not a
	/// successor.
	unsigned GetSuccessorNumber(BasicBlock *BB, BasicBlock *Succ);
	/// isCriticalEdge - Return true if the specified edge is a critical edge.
	/// Critical edges are edges from a block with multiple successors to a blo
	ck
	/// with multiple predecessors.
	///
	bool isCriticalEdge(const TerminatorInst *TI, unsigned SuccNum,
	bool AllowIdenticalEdges = false);
	/// SplitCriticalEdge - If this edge is a critical edge, insert a new node to		/// SplitCriticalEdge - If this edge is a critical edge, insert a new node to
	/// split the critical edge. This will update DominatorTree and		/// split the critical edge. This will update DominatorTree and
	/// DominatorFrontier information if it is available, thus calling this pas s		/// DominatorFrontier information if it is available, thus calling this pas s
	/// will not invalidate either of them. This returns the new block if the e dge		/// will not invalidate either of them. This returns the new block if the e dge
	/// was split, null otherwise.		/// was split, null otherwise.
	///		///
	/// If MergeIdenticalEdges is true (not the default), *all* edges from TI t o the		/// If MergeIdenticalEdges is true (not the default), *all* edges from TI t o the
	/// specified successor will be merged into the same critical edge block.		/// specified successor will be merged into the same critical edge block.
	/// This is most commonly interesting with switch instructions, which may		/// This is most commonly interesting with switch instructions, which may
	/// have many edges to any one destination. This ensures that all edges to that		/// have many edges to any one destination. This ensures that all edges to that
	skipping to change at line 228		skipping to change at line 207
	/// ThenBlock		/// ThenBlock
	/// Tail		/// Tail
	///		///
	/// If Unreachable is true, then ThenBlock ends with		/// If Unreachable is true, then ThenBlock ends with
	/// UnreachableInst, otherwise it branches to Tail.		/// UnreachableInst, otherwise it branches to Tail.
	/// Returns the NewBasicBlock's terminator.		/// Returns the NewBasicBlock's terminator.
	TerminatorInst *SplitBlockAndInsertIfThen(Instruction *Cmp,		TerminatorInst *SplitBlockAndInsertIfThen(Instruction *Cmp,
	bool Unreachable, MDNode *BranchWeights = 0);		bool Unreachable, MDNode *BranchWeights = 0);
			///
			/// GetIfCondition - Check whether BB is the merge point of a if-region.
			/// If so, return the boolean condition that determines which entry into
			/// BB will be taken. Also, return by references the block that will be
			/// entered from if the condition is true, and the block that will be
			/// entered if the condition is false.
			Value *GetIfCondition(BasicBlock *BB, BasicBlock *&IfTrue,
			BasicBlock *&IfFalse);
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 2 change blocks.
	26 lines changed or deleted		9 lines changed or added

	Binary.h		Binary.h
	skipping to change at line 41		skipping to change at line 41
	unsigned int TypeID;		unsigned int TypeID;
	protected:		protected:
	MemoryBuffer *Data;		MemoryBuffer *Data;
	Binary(unsigned int Type, MemoryBuffer *Source);		Binary(unsigned int Type, MemoryBuffer *Source);
	enum {		enum {
	ID_Archive,		ID_Archive,
			ID_MachOUniversalBinary,
	// Object and children.		// Object and children.
	ID_StartObjects,		ID_StartObjects,
	ID_COFF,		ID_COFF,
	ID_ELF32L, // ELF 32-bit, little endian		ID_ELF32L, // ELF 32-bit, little endian
	ID_ELF32B, // ELF 32-bit, big endian		ID_ELF32B, // ELF 32-bit, big endian
	ID_ELF64L, // ELF 64-bit, little endian		ID_ELF64L, // ELF 64-bit, little endian
	ID_ELF64B, // ELF 64-bit, big endian		ID_ELF64B, // ELF 64-bit, big endian
	ID_MachO32L, // MachO 32-bit, little endian		ID_MachO32L, // MachO 32-bit, little endian
	skipping to change at line 90		skipping to change at line 91
	// Convenience methods		// Convenience methods
	bool isObject() const {		bool isObject() const {
	return TypeID > ID_StartObjects && TypeID < ID_EndObjects;		return TypeID > ID_StartObjects && TypeID < ID_EndObjects;
	}		}
	bool isArchive() const {		bool isArchive() const {
	return TypeID == ID_Archive;		return TypeID == ID_Archive;
	}		}
			bool isMachOUniversalBinary() const {
			return TypeID == ID_MachOUniversalBinary;
			}
	bool isELF() const {		bool isELF() const {
	return TypeID >= ID_ELF32L && TypeID <= ID_ELF64B;		return TypeID >= ID_ELF32L && TypeID <= ID_ELF64B;
	}		}
	bool isMachO() const {		bool isMachO() const {
	return TypeID >= ID_MachO32L && TypeID <= ID_MachO64B;		return TypeID >= ID_MachO32L && TypeID <= ID_MachO64B;
	}		}
	bool isCOFF() const {		bool isCOFF() const {
	return TypeID == ID_COFF;		return TypeID == ID_COFF;
End of changes. 2 change blocks.
	0 lines changed or deleted		5 lines changed or added

	BitVector.h		BitVector.h
	skipping to change at line 140		skipping to change at line 140
	/// any - Returns true if any bit is set.		/// any - Returns true if any bit is set.
	bool any() const {		bool any() const {
	for (unsigned i = 0; i < NumBitWords(size()); ++i)		for (unsigned i = 0; i < NumBitWords(size()); ++i)
	if (Bits[i] != 0)		if (Bits[i] != 0)
	return true;		return true;
	return false;		return false;
	}		}
	/// all - Returns true if all bits are set.		/// all - Returns true if all bits are set.
	bool all() const {		bool all() const {
	// TODO: Optimize this.		for (unsigned i = 0; i < Size / BITWORD_SIZE; ++i)
	return count() == size();		if (Bits[i] != ~0UL)
			return false;
			// If bits remain check that they are ones. The unused bits are always
			zero.
			if (unsigned Remainder = Size % BITWORD_SIZE)
			return Bits[Size / BITWORD_SIZE] == (1UL << Remainder) - 1;
			return true;
	}		}
	/// none - Returns true if none of the bits are set.		/// none - Returns true if none of the bits are set.
	bool none() const {		bool none() const {
	return !any();		return !any();
	}		}
	/// find_first - Returns the index of the first set bit, -1 if none		/// find_first - Returns the index of the first set bit, -1 if none
	/// of the bits are set.		/// of the bits are set.
	int find_first() const {		int find_first() const {
	for (unsigned i = 0; i < NumBitWords(size()); ++i)		for (unsigned i = 0; i < NumBitWords(size()); ++i)
	if (Bits[i] != 0) {		if (Bits[i] != 0) {
	if (sizeof(BitWord) == 4)		if (sizeof(BitWord) == 4)
	return i * BITWORD_SIZE + CountTrailingZeros_32((uint32_t)Bits[i] );		return i * BITWORD_SIZE + countTrailingZeros((uint32_t)Bits[i]);
	if (sizeof(BitWord) == 8)		if (sizeof(BitWord) == 8)
	return i * BITWORD_SIZE + CountTrailingZeros_64(Bits[i]);		return i * BITWORD_SIZE + countTrailingZeros(Bits[i]);
	llvm_unreachable("Unsupported!");		llvm_unreachable("Unsupported!");
	}		}
	return -1;		return -1;
	}		}
	/// find_next - Returns the index of the next set bit following the		/// find_next - Returns the index of the next set bit following the
	/// "Prev" bit. Returns -1 if the next set bit is not found.		/// "Prev" bit. Returns -1 if the next set bit is not found.
	int find_next(unsigned Prev) const {		int find_next(unsigned Prev) const {
	++Prev;		++Prev;
	if (Prev >= Size)		if (Prev >= Size)
	return -1;		return -1;
	unsigned WordPos = Prev / BITWORD_SIZE;		unsigned WordPos = Prev / BITWORD_SIZE;
	unsigned BitPos = Prev % BITWORD_SIZE;		unsigned BitPos = Prev % BITWORD_SIZE;
	BitWord Copy = Bits[WordPos];		BitWord Copy = Bits[WordPos];
	// Mask off previous bits.		// Mask off previous bits.
	Copy &= ~0UL << BitPos;		Copy &= ~0UL << BitPos;
	if (Copy != 0) {		if (Copy != 0) {
	if (sizeof(BitWord) == 4)		if (sizeof(BitWord) == 4)
	return WordPos * BITWORD_SIZE + CountTrailingZeros_32((uint32_t)Cop y);		return WordPos * BITWORD_SIZE + countTrailingZeros((uint32_t)Copy);
	if (sizeof(BitWord) == 8)		if (sizeof(BitWord) == 8)
	return WordPos * BITWORD_SIZE + CountTrailingZeros_64(Copy);		return WordPos * BITWORD_SIZE + countTrailingZeros(Copy);
	llvm_unreachable("Unsupported!");		llvm_unreachable("Unsupported!");
	}		}
	// Check subsequent words.		// Check subsequent words.
	for (unsigned i = WordPos+1; i < NumBitWords(size()); ++i)		for (unsigned i = WordPos+1; i < NumBitWords(size()); ++i)
	if (Bits[i] != 0) {		if (Bits[i] != 0) {
	if (sizeof(BitWord) == 4)		if (sizeof(BitWord) == 4)
	return i * BITWORD_SIZE + CountTrailingZeros_32((uint32_t)Bits[i] );		return i * BITWORD_SIZE + countTrailingZeros((uint32_t)Bits[i]);
	if (sizeof(BitWord) == 8)		if (sizeof(BitWord) == 8)
	return i * BITWORD_SIZE + CountTrailingZeros_64(Bits[i]);		return i * BITWORD_SIZE + countTrailingZeros(Bits[i]);
	llvm_unreachable("Unsupported!");		llvm_unreachable("Unsupported!");
	}		}
	return -1;		return -1;
	}		}
	/// clear - Clear all bits.		/// clear - Clear all bits.
	void clear() {		void clear() {
	Size = 0;		Size = 0;
	}		}
End of changes. 7 change blocks.
	8 lines changed or deleted		16 lines changed or added

	BitstreamReader.h		BitstreamReader.h
	skipping to change at line 244		skipping to change at line 244
	}		}
	bool canSkipToPos(size_t pos) const {		bool canSkipToPos(size_t pos) const {
	// pos can be skipped to if it is a valid address or one byte past the end.		// pos can be skipped to if it is a valid address or one byte past the end.
	return pos == 0 || BitStream->getBitcodeBytes().isValidAddress(		return pos == 0 || BitStream->getBitcodeBytes().isValidAddress(
	static_cast<uint64_t>(pos - 1));		static_cast<uint64_t>(pos - 1));
	}		}
	uint32_t getWord(size_t pos) {		uint32_t getWord(size_t pos) {
	uint8_t buf[4] = { 0xFF, 0xFF, 0xFF, 0xFF };		uint8_t buf[4] = { 0xFF, 0xFF, 0xFF, 0xFF };
	BitStream->getBitcodeBytes().readBytes(pos, sizeof(buf), buf, NULL);		BitStream->getBitcodeBytes().readBytes(pos, sizeof(buf), buf);
	return *reinterpret_cast<support::ulittle32_t *>(buf);		return *reinterpret_cast<support::ulittle32_t *>(buf);
	}		}
	bool AtEndOfStream() {		bool AtEndOfStream() {
	return BitsInCurWord == 0 && isEndPos(NextChar);		return BitsInCurWord == 0 && isEndPos(NextChar);
	}		}
	/// getAbbrevIDWidth - Return the number of bits used to encode an abbrev #.		/// getAbbrevIDWidth - Return the number of bits used to encode an abbrev #.
	unsigned getAbbrevIDWidth() const { return CurCodeSize; }		unsigned getAbbrevIDWidth() const { return CurCodeSize; }
	skipping to change at line 365		skipping to change at line 365
	CurWord = 0;		CurWord = 0;
	BitsInCurWord = 0;		BitsInCurWord = 0;
	return 0;		return 0;
	}		}
	uint32_t R = uint32_t(CurWord);		uint32_t R = uint32_t(CurWord);
	// Read the next word from the stream.		// Read the next word from the stream.
	uint8_t Array[sizeof(word_t)] = {0};		uint8_t Array[sizeof(word_t)] = {0};
	BitStream->getBitcodeBytes().readBytes(NextChar, sizeof(Array),		BitStream->getBitcodeBytes().readBytes(NextChar, sizeof(Array), Array);
	Array, NULL);
	// Handle big-endian byte-swapping if necessary.		// Handle big-endian byte-swapping if necessary.
	support::detail::packed_endian_specific_integral		support::detail::packed_endian_specific_integral
	<word_t, support::little, support::unaligned> EndianValue;		<word_t, support::little, support::unaligned> EndianValue;
	memcpy(&EndianValue, Array, sizeof(Array));		memcpy(&EndianValue, Array, sizeof(Array));
	CurWord = EndianValue;		CurWord = EndianValue;
	NextChar += sizeof(word_t);		NextChar += sizeof(word_t);
End of changes. 2 change blocks.
	3 lines changed or deleted		2 lines changed or added

	BitstreamWriter.h		BitstreamWriter.h
	skipping to change at line 384		skipping to change at line 384
	// Emit each field as a literal byte.		// Emit each field as a literal byte.
	if (BlobData) {		if (BlobData) {
	for (unsigned i = 0; i != BlobLen; ++i)		for (unsigned i = 0; i != BlobLen; ++i)
	WriteByte((unsigned char)BlobData[i]);		WriteByte((unsigned char)BlobData[i]);
	// Know that blob data is consumed for assertion below.		// Know that blob data is consumed for assertion below.
	BlobData = 0;		BlobData = 0;
	} else {		} else {
	for (unsigned e = Vals.size(); RecordIdx != e; ++RecordIdx) {		for (unsigned e = Vals.size(); RecordIdx != e; ++RecordIdx) {
	assert(Vals[RecordIdx] < 256 && "Value too large to emit as blo		assert(isUInt<8>(Vals[RecordIdx]) &&
	b");		"Value too large to emit as blob");
	WriteByte((unsigned char)Vals[RecordIdx]);		WriteByte((unsigned char)Vals[RecordIdx]);
	}		}
	}		}
	// Align end to 32-bits.		// Align end to 32-bits.
	while (GetBufferOffset() & 3)		while (GetBufferOffset() & 3)
	WriteByte(0);		WriteByte(0);
	} else { // Single scalar field.		} else { // Single scalar field.
	assert(RecordIdx < Vals.size() && "Invalid abbrev/record");		assert(RecordIdx < Vals.size() && "Invalid abbrev/record");
	EmitAbbreviatedField(Op, Vals[RecordIdx]);		EmitAbbreviatedField(Op, Vals[RecordIdx]);
End of changes. 1 change blocks.
	2 lines changed or deleted		2 lines changed or added

	BlockFrequency.h		BlockFrequency.h
	skipping to change at line 28		skipping to change at line 28
	namespace llvm {		namespace llvm {
	class raw_ostream;		class raw_ostream;
	class BranchProbability;		class BranchProbability;
	// This class represents Block Frequency as a 64-bit value.		// This class represents Block Frequency as a 64-bit value.
	class BlockFrequency {		class BlockFrequency {
	uint64_t Frequency;		uint64_t Frequency;
	static const int64_t ENTRY_FREQ = 1024;		static const int64_t ENTRY_FREQ = 1 << 14;
			/// \brief Scale the given BlockFrequency by N/D. Return the remainder fr
			om
			/// the division by D. Upon overflow, the routine will saturate and
			/// additionally will return the remainder set to D.
			uint32_t scale(uint32_t N, uint32_t D);
	public:		public:
	BlockFrequency(uint64_t Freq = 0) : Frequency(Freq) { }		BlockFrequency(uint64_t Freq = 0) : Frequency(Freq) { }
			/// \brief Returns the frequency of the entry block of the function.
	static uint64_t getEntryFrequency() { return ENTRY_FREQ; }		static uint64_t getEntryFrequency() { return ENTRY_FREQ; }
			/// \brief Returns the maximum possible frequency, the saturation value.
			static uint64_t getMaxFrequency() { return -1ULL; }
			/// \brief Returns the frequency as a fixpoint number scaled by the entry
			/// frequency.
	uint64_t getFrequency() const { return Frequency; }		uint64_t getFrequency() const { return Frequency; }
			/// \brief Multiplies with a branch probability. The computation will nev
			er
			/// overflow.
	BlockFrequency &operator*=(const BranchProbability &Prob);		BlockFrequency &operator*=(const BranchProbability &Prob);
	const BlockFrequency operator*(const BranchProbability &Prob) const;		const BlockFrequency operator*(const BranchProbability &Prob) const;
			/// \brief Divide by a non-zero branch probability using saturating
			/// arithmetic.
			BlockFrequency &operator/=(const BranchProbability &Prob);
			BlockFrequency operator/(const BranchProbability &Prob) const;
			/// \brief Adds another block frequency using saturating arithmetic.
	BlockFrequency &operator+=(const BlockFrequency &Freq);		BlockFrequency &operator+=(const BlockFrequency &Freq);
	const BlockFrequency operator+(const BlockFrequency &Freq) const;		const BlockFrequency operator+(const BlockFrequency &Freq) const;
			/// \brief Scale the given BlockFrequency by N/D. Return the remainder fr
			om
			/// the division by D. Upon overflow, the routine will saturate.
			uint32_t scale(const BranchProbability &Prob);
	bool operator<(const BlockFrequency &RHS) const {		bool operator<(const BlockFrequency &RHS) const {
	return Frequency < RHS.Frequency;		return Frequency < RHS.Frequency;
	}		}
	bool operator<=(const BlockFrequency &RHS) const {		bool operator<=(const BlockFrequency &RHS) const {
	return Frequency <= RHS.Frequency;		return Frequency <= RHS.Frequency;
	}		}
	bool operator>(const BlockFrequency &RHS) const {		bool operator>(const BlockFrequency &RHS) const {
	return Frequency > RHS.Frequency;		return Frequency > RHS.Frequency;
End of changes. 6 change blocks.
	1 lines changed or deleted		28 lines changed or added

	BlockFrequencyImpl.h		BlockFrequencyImpl.h
	//===---- BlockFrequencyImpl.h - Machine Block Frequency Implementation --- ===//		//===-- BlockFrequencyImpl.h - Block Frequency Implementation --*- C++ -*-- ===//
	//		//
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// Shared implementation of BlockFrequency for IR and Machine Instructions.		// Shared implementation of BlockFrequency for IR and Machine Instructions.
	//		//
	skipping to change at line 35		skipping to change at line 35
	#include "llvm/Support/raw_ostream.h"		#include "llvm/Support/raw_ostream.h"
	#include <string>		#include <string>
	#include <vector>		#include <vector>
	namespace llvm {		namespace llvm {
	class BlockFrequencyInfo;		class BlockFrequencyInfo;
	class MachineBlockFrequencyInfo;		class MachineBlockFrequencyInfo;
	/// BlockFrequencyImpl implements block frequency algorithm for IR and		/// BlockFrequencyImpl implements block frequency algorithm for IR and
	/// Machine Instructions. Algorithm starts with value 1024 (START_FREQ)		/// Machine Instructions. Algorithm starts with value ENTRY_FREQ
	/// for the entry block and then propagates frequencies using branch weight s		/// for the entry block and then propagates frequencies using branch weight s
	/// from (Machine)BranchProbabilityInfo. LoopInfo is not required because		/// from (Machine)BranchProbabilityInfo. LoopInfo is not required because
	/// algorithm can find "backedges" by itself.		/// algorithm can find "backedges" by itself.
	template<class BlockT, class FunctionT, class BlockProbInfoT>		template<class BlockT, class FunctionT, class BlockProbInfoT>
	class BlockFrequencyImpl {		class BlockFrequencyImpl {
	DenseMap<const BlockT *, BlockFrequency> Freqs;		DenseMap<const BlockT *, BlockFrequency> Freqs;
	BlockProbInfoT *BPI;		BlockProbInfoT *BPI;
	skipping to change at line 87		skipping to change at line 87
	}		}
	/// incBlockFreq - Increase BB block frequency by FREQ.		/// incBlockFreq - Increase BB block frequency by FREQ.
	///		///
	void incBlockFreq(BlockT *BB, BlockFrequency Freq) {		void incBlockFreq(BlockT *BB, BlockFrequency Freq) {
	Freqs[BB] += Freq;		Freqs[BB] += Freq;
	DEBUG(dbgs() << "Frequency(" << getBlockName(BB) << ") += " << Freq		DEBUG(dbgs() << "Frequency(" << getBlockName(BB) << ") += " << Freq
	<< " --> " << Freqs[BB] << "\n");		<< " --> " << Freqs[BB] << "\n");
	}		}
	/// divBlockFreq - Divide BB block frequency by PROB. If Prob = 0 do noth
	ing.
	///
	void divBlockFreq(BlockT *BB, BranchProbability Prob) {
	uint64_t N = Prob.getNumerator();
	assert(N && "Illegal division by zero!");
	uint64_t D = Prob.getDenominator();
	uint64_t Freq = (Freqs[BB].getFrequency() * D) / N;
	// Should we assert it?
	if (Freq > UINT32_MAX)
	Freq = UINT32_MAX;
	Freqs[BB] = BlockFrequency(Freq);
	DEBUG(dbgs() << "Frequency(" << getBlockName(BB) << ") /= (" << Prob
	<< ") --> " << Freqs[BB] << "\n");
	}
	// All blocks in postorder.		// All blocks in postorder.
	std::vector<BlockT *> POT;		std::vector<BlockT *> POT;
	// Map Block -> Position in reverse-postorder list.		// Map Block -> Position in reverse-postorder list.
	DenseMap<BlockT *, unsigned> RPO;		DenseMap<BlockT *, unsigned> RPO;
	// Cycle Probability for each bloch.		// For each loop header, record the per-iteration probability of exiting
	DenseMap<BlockT *, uint32_t> CycleProb;		the
			// loop. This is the reciprocal of the expected number of loop iterations
			.
			typedef DenseMap<BlockT*, BranchProbability> LoopExitProbMap;
			LoopExitProbMap LoopExitProb;
	// (reverse-)postorder traversal iterators.		// (reverse-)postorder traversal iterators.
	typedef typename std::vector<BlockT *>::iterator pot_iterator;		typedef typename std::vector<BlockT *>::iterator pot_iterator;
	typedef typename std::vector<BlockT *>::reverse_iterator rpot_iterator;		typedef typename std::vector<BlockT *>::reverse_iterator rpot_iterator;
	pot_iterator pot_begin() { return POT.begin(); }		pot_iterator pot_begin() { return POT.begin(); }
	pot_iterator pot_end() { return POT.end(); }		pot_iterator pot_end() { return POT.end(); }
	rpot_iterator rpot_begin() { return POT.rbegin(); }		rpot_iterator rpot_begin() { return POT.rbegin(); }
	rpot_iterator rpot_end() { return POT.rend(); }		rpot_iterator rpot_end() { return POT.rend(); }
	rpot_iterator rpot_at(BlockT *BB) {		rpot_iterator rpot_at(BlockT *BB) {
	rpot_iterator I = rpot_begin();		rpot_iterator I = rpot_begin();
	unsigned idx = RPO[BB];		unsigned idx = RPO.lookup(BB);
	assert(idx);		assert(idx);
	std::advance(I, idx - 1);		std::advance(I, idx - 1);
	assert(*I == BB);		assert(*I == BB);
	return I;		return I;
	}		}
	/// isReachable - Returns if BB block is reachable from the entry.		/// isBackedge - Return if edge Src -> Dst is a reachable backedge.
	///
	bool isReachable(BlockT *BB) {
	return RPO.count(BB);
	}
	/// isBackedge - Return if edge Src -> Dst is a backedge.
	///		///
	bool isBackedge(BlockT *Src, BlockT *Dst) {		bool isBackedge(BlockT *Src, BlockT *Dst) const {
	assert(isReachable(Src));		unsigned a = RPO.lookup(Src);
	assert(isReachable(Dst));		if (!a)
			return false;
	unsigned a = RPO[Src];		unsigned b = RPO.lookup(Dst);
	unsigned b = RPO[Dst];		assert(b && "Destination block should be reachable");
	return a >= b;		return a >= b;
	}		}
	/// getSingleBlockPred - return single BB block predecessor or NULL if		/// getSingleBlockPred - return single BB block predecessor or NULL if
	/// BB has none or more predecessors.		/// BB has none or more predecessors.
	BlockT *getSingleBlockPred(BlockT *BB) {		BlockT *getSingleBlockPred(BlockT *BB) {
	typename GT::ChildIteratorType		typename GT::ChildIteratorType
	PI = GraphTraits< Inverse<BlockT *> >::child_begin(BB),		PI = GraphTraits< Inverse<BlockT *> >::child_begin(BB),
	PE = GraphTraits< Inverse<BlockT *> >::child_end(BB);		PE = GraphTraits< Inverse<BlockT *> >::child_end(BB);
	skipping to change at line 197		skipping to change at line 175
	bool isInLoop = false;		bool isInLoop = false;
	bool isLoopHead = false;		bool isLoopHead = false;
	for (typename GT::ChildIteratorType		for (typename GT::ChildIteratorType
	PI = GraphTraits< Inverse<BlockT *> >::child_begin(BB),		PI = GraphTraits< Inverse<BlockT *> >::child_begin(BB),
	PE = GraphTraits< Inverse<BlockT *> >::child_end(BB);		PE = GraphTraits< Inverse<BlockT *> >::child_end(BB);
	PI != PE; ++PI) {		PI != PE; ++PI) {
	BlockT *Pred = *PI;		BlockT *Pred = *PI;
	if (isReachable(Pred) && isBackedge(Pred, BB)) {		if (isBackedge(Pred, BB)) {
	isLoopHead = true;		isLoopHead = true;
	} else if (BlocksInLoop.count(Pred)) {		} else if (BlocksInLoop.count(Pred)) {
	incBlockFreq(BB, getEdgeFreq(Pred, BB));		incBlockFreq(BB, getEdgeFreq(Pred, BB));
	isInLoop = true;		isInLoop = true;
	}		}
	// TODO: else? irreducible.		// TODO: else? irreducible.
	}		}
	if (!isInLoop)		if (!isInLoop)
	return;		return;
	if (!isLoopHead)		if (!isLoopHead)
	return;		return;
	assert(EntryFreq >= CycleProb[BB]);		// This block is a loop header, so boost its frequency by the expected
	uint32_t CProb = CycleProb[BB];		// number of loop iterations. The loop blocks will be revisited so they
	uint32_t Numerator = EntryFreq - CProb ? EntryFreq - CProb : 1;		all
	divBlockFreq(BB, BranchProbability(Numerator, EntryFreq));		// get this boost.
			typename LoopExitProbMap::const_iterator I = LoopExitProb.find(BB);
			assert(I != LoopExitProb.end() && "Loop header missing from table");
			Freqs[BB] /= I->second;
			DEBUG(dbgs() << "Loop header scaled to " << Freqs[BB] << ".\n");
	}		}
	/// doLoop - Propagate block frequency down through the loop.		/// doLoop - Propagate block frequency down through the loop.
	void doLoop(BlockT *Head, BlockT *Tail) {		void doLoop(BlockT *Head, BlockT *Tail) {
	DEBUG(dbgs() << "doLoop(" << getBlockName(Head) << ", "		DEBUG(dbgs() << "doLoop(" << getBlockName(Head) << ", "
	<< getBlockName(Tail) << ")\n");		<< getBlockName(Tail) << ")\n");
	SmallPtrSet<BlockT *, 8> BlocksInLoop;		SmallPtrSet<BlockT *, 8> BlocksInLoop;
	for (rpot_iterator I = rpot_at(Head), E = rpot_at(Tail); ; ++I) {		for (rpot_iterator I = rpot_at(Head), E = rpot_at(Tail); ; ++I) {
	BlockT *BB = *I;		BlockT *BB = *I;
	doBlock(BB, Head, BlocksInLoop);		doBlock(BB, Head, BlocksInLoop);
	BlocksInLoop.insert(BB);		BlocksInLoop.insert(BB);
	if (I == E)		if (I == E)
	break;		break;
	}		}
	// Compute loop's cyclic probability using backedges probabilities.		// Compute loop's cyclic probability using backedges probabilities.
			BlockFrequency BackFreq;
	for (typename GT::ChildIteratorType		for (typename GT::ChildIteratorType
	PI = GraphTraits< Inverse<BlockT *> >::child_begin(Head),		PI = GraphTraits< Inverse<BlockT *> >::child_begin(Head),
	PE = GraphTraits< Inverse<BlockT *> >::child_end(Head);		PE = GraphTraits< Inverse<BlockT *> >::child_end(Head);
	PI != PE; ++PI) {		PI != PE; ++PI) {
	BlockT *Pred = *PI;		BlockT *Pred = *PI;
	assert(Pred);		assert(Pred);
	if (isReachable(Pred) && isBackedge(Pred, Head)) {		if (isBackedge(Pred, Head))
	uint64_t N = getEdgeFreq(Pred, Head).getFrequency();		BackFreq += getEdgeFreq(Pred, Head);
	uint64_t D = getBlockFreq(Head).getFrequency();		}
	assert(N <= EntryFreq && "Backedge frequency must be <= EntryFreq!"
	);		// The cyclic probability is freq(BackEdges) / freq(Head), where freq(H
	uint64_t Res = (N * EntryFreq) / D;		ead)
			// only counts edges entering the loop, not the loop backedges.
	assert(Res <= UINT32_MAX);		// The probability of leaving the loop on each iteration is:
	CycleProb[Head] += (uint32_t) Res;		//
	DEBUG(dbgs() << " CycleProb[" << getBlockName(Head) << "] += " <<		// ExitProb = 1 - CyclicProb
	Res		//
	<< " --> " << CycleProb[Head] << "\n");		// The Expected number of loop iterations is:
	}		//
			// Iterations = 1 / ExitProb
			//
			uint64_t D = std::max(getBlockFreq(Head).getFrequency(), UINT64_C(1));
			uint64_t N = std::max(BackFreq.getFrequency(), UINT64_C(1));
			if (N < D)
			N = D - N;
			else
			// We'd expect N < D, but rounding and saturation means that can't be
			// guaranteed.
			N = 1;
			// Now ExitProb = N / D, make sure it fits in an i32/i32 fraction.
			assert(N <= D);
			if (D > UINT32_MAX) {
			unsigned Shift = 32 - countLeadingZeros(D);
			D >>= Shift;
			N >>= Shift;
			if (N == 0)
			N = 1;
	}		}
			BranchProbability LEP = BranchProbability(N, D);
			LoopExitProb.insert(std::make_pair(Head, LEP));
			DEBUG(dbgs() << "LoopExitProb[" << getBlockName(Head) << "] = " << LEP
			<< " from 1 - " << BackFreq << " / " << getBlockFreq(Head)
			<< ".\n");
	}		}
	friend class BlockFrequencyInfo;		friend class BlockFrequencyInfo;
	friend class MachineBlockFrequencyInfo;		friend class MachineBlockFrequencyInfo;
	BlockFrequencyImpl() : EntryFreq(BlockFrequency::getEntryFrequency()) { }		BlockFrequencyImpl() : EntryFreq(BlockFrequency::getEntryFrequency()) { }
	void doFunction(FunctionT *fn, BlockProbInfoT *bpi) {		void doFunction(FunctionT *fn, BlockProbInfoT *bpi) {
	Fn = fn;		Fn = fn;
	BPI = bpi;		BPI = bpi;
	// Clear everything.		// Clear everything.
	RPO.clear();		RPO.clear();
	POT.clear();		POT.clear();
	CycleProb.clear();		LoopExitProb.clear();
	Freqs.clear();		Freqs.clear();
	BlockT *EntryBlock = fn->begin();		BlockT *EntryBlock = fn->begin();
	std::copy(po_begin(EntryBlock), po_end(EntryBlock), std::back_inserter( POT));		std::copy(po_begin(EntryBlock), po_end(EntryBlock), std::back_inserter( POT));
	unsigned RPOidx = 0;		unsigned RPOidx = 0;
	for (rpot_iterator I = rpot_begin(), E = rpot_end(); I != E; ++I) {		for (rpot_iterator I = rpot_begin(), E = rpot_end(); I != E; ++I) {
	BlockT *BB = *I;		BlockT *BB = *I;
	RPO[BB] = ++RPOidx;		RPO[BB] = ++RPOidx;
	skipping to change at line 293		skipping to change at line 300
	BlockT *BB = *I;		BlockT *BB = *I;
	BlockT *LastTail = 0;		BlockT *LastTail = 0;
	DEBUG(dbgs() << "POT: " << getBlockName(BB) << "\n");		DEBUG(dbgs() << "POT: " << getBlockName(BB) << "\n");
	for (typename GT::ChildIteratorType		for (typename GT::ChildIteratorType
	PI = GraphTraits< Inverse<BlockT *> >::child_begin(BB),		PI = GraphTraits< Inverse<BlockT *> >::child_begin(BB),
	PE = GraphTraits< Inverse<BlockT *> >::child_end(BB);		PE = GraphTraits< Inverse<BlockT *> >::child_end(BB);
	PI != PE; ++PI) {		PI != PE; ++PI) {
	BlockT *Pred = *PI;		BlockT *Pred = *PI;
	if (isReachable(Pred) && isBackedge(Pred, BB)		if (isBackedge(Pred, BB) && (!LastTail || RPO[Pred] > RPO[LastTail]
	&& (!LastTail || RPO[Pred] > RPO[LastTail]))		))
	LastTail = Pred;		LastTail = Pred;
	}		}
	if (LastTail)		if (LastTail)
	doLoop(BB, LastTail);		doLoop(BB, LastTail);
	}		}
	// At the end assume the whole function as a loop, and travel over it o nce		// At the end assume the whole function as a loop, and travel over it o nce
	// again.		// again.
	doLoop(*(rpot_begin()), *(pot_begin()));		doLoop(*(rpot_begin()), *(pot_begin()));
End of changes. 14 change blocks.
	58 lines changed or deleted		66 lines changed or added

	BlockFrequencyInfo.h		BlockFrequencyInfo.h
	//========-------- BlockFrequencyInfo.h - Block Frequency Analysis -------= =======//		//===------- BlockFrequencyInfo.h - Block Frequency Analysis --*- C++ -*--- ===//
	//		//
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// Loops should be simplified before this analysis.		// Loops should be simplified before this analysis.
	//		//
	skipping to change at line 44		skipping to change at line 44
	static char ID;		static char ID;
	BlockFrequencyInfo();		BlockFrequencyInfo();
	~BlockFrequencyInfo();		~BlockFrequencyInfo();
	void getAnalysisUsage(AnalysisUsage &AU) const;		void getAnalysisUsage(AnalysisUsage &AU) const;
	bool runOnFunction(Function &F);		bool runOnFunction(Function &F);
	void print(raw_ostream &O, const Module *M) const;		void print(raw_ostream &O, const Module *M) const;
			const Function *getFunction() const;
			void view() const;
	/// getblockFreq - Return block frequency. Return 0 if we don't have the		/// getblockFreq - Return block frequency. Return 0 if we don't have the
	/// information. Please note that initial frequency is equal to 1024. It		/// information. Please note that initial frequency is equal to ENTRY_FRE
	means		Q. It
	/// that we should not rely on the value itself, but only on the comparis		/// means that we should not rely on the value itself, but only on the
	on to		/// comparison to the other block frequencies. We do this to avoid using
	/// the other block frequencies. We do this to avoid using of floating po		of
	ints.		/// floating points.
	///
	BlockFrequency getBlockFreq(const BasicBlock *BB) const;		BlockFrequency getBlockFreq(const BasicBlock *BB) const;
	};		};
	}		}
	#endif		#endif
End of changes. 3 change blocks.
	8 lines changed or deleted		9 lines changed or added

	BranchProbabilityInfo.h		BranchProbabilityInfo.h
	skipping to change at line 134		skipping to change at line 134
	/// \brief Handle to the LoopInfo analysis.		/// \brief Handle to the LoopInfo analysis.
	LoopInfo *LI;		LoopInfo *LI;
	/// \brief Track the last function we run over for printing.		/// \brief Track the last function we run over for printing.
	Function *LastF;		Function *LastF;
	/// \brief Track the set of blocks directly succeeded by a returning bloc k.		/// \brief Track the set of blocks directly succeeded by a returning bloc k.
	SmallPtrSet<BasicBlock *, 16> PostDominatedByUnreachable;		SmallPtrSet<BasicBlock *, 16> PostDominatedByUnreachable;
			/// \brief Track the set of blocks that always lead to a cold call.
			SmallPtrSet<BasicBlock *, 16> PostDominatedByColdCall;
	/// \brief Get sum of the block successors' weights.		/// \brief Get sum of the block successors' weights.
	uint32_t getSumForBlock(const BasicBlock *BB) const;		uint32_t getSumForBlock(const BasicBlock *BB) const;
	bool calcUnreachableHeuristics(BasicBlock *BB);		bool calcUnreachableHeuristics(BasicBlock *BB);
	bool calcMetadataWeights(BasicBlock *BB);		bool calcMetadataWeights(BasicBlock *BB);
			bool calcColdCallHeuristics(BasicBlock *BB);
	bool calcPointerHeuristics(BasicBlock *BB);		bool calcPointerHeuristics(BasicBlock *BB);
	bool calcLoopBranchHeuristics(BasicBlock *BB);		bool calcLoopBranchHeuristics(BasicBlock *BB);
	bool calcZeroHeuristics(BasicBlock *BB);		bool calcZeroHeuristics(BasicBlock *BB);
	bool calcFloatingPointHeuristics(BasicBlock *BB);		bool calcFloatingPointHeuristics(BasicBlock *BB);
	bool calcInvokeHeuristics(BasicBlock *BB);		bool calcInvokeHeuristics(BasicBlock *BB);
	};		};
	}		}
	#endif		#endif
End of changes. 2 change blocks.
	0 lines changed or deleted		4 lines changed or added

	Briggs.h		Briggs.h
	skipping to change at line 50		skipping to change at line 50
	/// the lowest estimated spill cost is selected and push to the solver stack		/// the lowest estimated spill cost is selected and push to the solver stack
	/// instead.		/// instead.
	///		///
	/// This implementation is built on top of HeuristicBase.		/// This implementation is built on top of HeuristicBase.
	class Briggs : public HeuristicBase<Briggs> {		class Briggs : public HeuristicBase<Briggs> {
	private:		private:
	class LinkDegreeComparator {		class LinkDegreeComparator {
	public:		public:
	LinkDegreeComparator(HeuristicSolverImpl<Briggs> &s) : s(&s) {}		LinkDegreeComparator(HeuristicSolverImpl<Briggs> &s) : s(&s) {}
	bool operator()(Graph::NodeItr n1Itr, Graph::NodeItr n2Itr) const {		bool operator()(Graph::NodeId n1Id, Graph::NodeId n2Id) const {
	if (s->getSolverDegree(n1Itr) > s->getSolverDegree(n2Itr))		if (s->getSolverDegree(n1Id) > s->getSolverDegree(n2Id))
	return true;		return true;
	return false;		return false;
	}		}
	private:		private:
	HeuristicSolverImpl<Briggs> *s;		HeuristicSolverImpl<Briggs> *s;
	};		};
	class SpillCostComparator {		class SpillCostComparator {
	public:		public:
	SpillCostComparator(HeuristicSolverImpl<Briggs> &s)		SpillCostComparator(HeuristicSolverImpl<Briggs> &s)
	: s(&s), g(&s.getGraph()) {}		: s(&s), g(&s.getGraph()) {}
	bool operator()(Graph::NodeItr n1Itr, Graph::NodeItr n2Itr) const {		bool operator()(Graph::NodeId n1Id, Graph::NodeId n2Id) const {
	const PBQP::Vector &cv1 = g->getNodeCosts(n1Itr);		const PBQP::Vector &cv1 = g->getNodeCosts(n1Id);
	const PBQP::Vector &cv2 = g->getNodeCosts(n2Itr);		const PBQP::Vector &cv2 = g->getNodeCosts(n2Id);
	PBQPNum cost1 = cv1[0] / s->getSolverDegree(n1Itr);		PBQPNum cost1 = cv1[0] / s->getSolverDegree(n1Id);
	PBQPNum cost2 = cv2[0] / s->getSolverDegree(n2Itr);		PBQPNum cost2 = cv2[0] / s->getSolverDegree(n2Id);
	if (cost1 < cost2)		if (cost1 < cost2)
	return true;		return true;
	return false;		return false;
	}		}
	private:		private:
	HeuristicSolverImpl<Briggs> *s;		HeuristicSolverImpl<Briggs> *s;
	Graph *g;		Graph *g;
	};		};
	typedef std::list<Graph::NodeItr> RNAllocableList;		typedef std::list<Graph::NodeId> RNAllocableList;
	typedef RNAllocableList::iterator RNAllocableListItr;		typedef RNAllocableList::iterator RNAllocableListItr;
	typedef std::list<Graph::NodeItr> RNUnallocableList;		typedef std::list<Graph::NodeId> RNUnallocableList;
	typedef RNUnallocableList::iterator RNUnallocableListItr;		typedef RNUnallocableList::iterator RNUnallocableListItr;
	public:		public:
	struct NodeData {		struct NodeData {
	typedef std::vector<unsigned> UnsafeDegreesArray;		typedef std::vector<unsigned> UnsafeDegreesArray;
	bool isHeuristic, isAllocable, isInitialized;		bool isHeuristic, isAllocable, isInitialized;
	unsigned numDenied, numSafe;		unsigned numDenied, numSafe;
	UnsafeDegreesArray unsafeDegrees;		UnsafeDegreesArray unsafeDegrees;
	RNAllocableListItr rnaItr;		RNAllocableListItr rnaItr;
	skipping to change at line 117		skipping to change at line 117
	EdgeData() : worst(0), reverseWorst(0), isUpToDate(false) {}		EdgeData() : worst(0), reverseWorst(0), isUpToDate(false) {}
	};		};
	/// \brief Construct an instance of the Briggs heuristic.		/// \brief Construct an instance of the Briggs heuristic.
	/// @param solver A reference to the solver which is using this heuri stic.		/// @param solver A reference to the solver which is using this heuri stic.
	Briggs(HeuristicSolverImpl<Briggs> &solver) :		Briggs(HeuristicSolverImpl<Briggs> &solver) :
	HeuristicBase<Briggs>(solver) {}		HeuristicBase<Briggs>(solver) {}
	/// \brief Determine whether a node should be reduced using optimal		/// \brief Determine whether a node should be reduced using optimal
	/// reduction.		/// reduction.
	/// @param nItr Node iterator to be considered.		/// @param nId Node id to be considered.
	/// @return True if the given node should be optimally reduced, false		/// @return True if the given node should be optimally reduced, false
	/// otherwise.		/// otherwise.
	///		///
	/// Selects nodes of degree 0, 1 or 2 for optimal reduction, with one		/// Selects nodes of degree 0, 1 or 2 for optimal reduction, with one
	/// exception. Nodes whose spill cost (element 0 of their cost vector ) is		/// exception. Nodes whose spill cost (element 0 of their cost vector ) is
	/// infinite are checked for allocability first. Allocable nodes may be		/// infinite are checked for allocability first. Allocable nodes may be
	/// optimally reduced, but nodes whose allocability cannot be proven are		/// optimally reduced, but nodes whose allocability cannot be proven are
	/// selected for heuristic reduction instead.		/// selected for heuristic reduction instead.
	bool shouldOptimallyReduce(Graph::NodeItr nItr) {		bool shouldOptimallyReduce(Graph::NodeId nId) {
	if (getSolver().getSolverDegree(nItr) < 3) {		if (getSolver().getSolverDegree(nId) < 3) {
	return true;		return true;
	}		}
	// else		// else
	return false;		return false;
	}		}
	/// \brief Add a node to the heuristic reduce list.		/// \brief Add a node to the heuristic reduce list.
	/// @param nItr Node iterator to add to the heuristic reduce list.		/// @param nId Node id to add to the heuristic reduce list.
	void addToHeuristicReduceList(Graph::NodeItr nItr) {		void addToHeuristicReduceList(Graph::NodeId nId) {
	NodeData &nd = getHeuristicNodeData(nItr);		NodeData &nd = getHeuristicNodeData(nId);
	initializeNode(nItr);		initializeNode(nId);
	nd.isHeuristic = true;		nd.isHeuristic = true;
	if (nd.isAllocable) {		if (nd.isAllocable) {
	nd.rnaItr = rnAllocableList.insert(rnAllocableList.end(), nItr);		nd.rnaItr = rnAllocableList.insert(rnAllocableList.end(), nId);
	} else {		} else {
	nd.rnuItr = rnUnallocableList.insert(rnUnallocableList.end(), nIt r);		nd.rnuItr = rnUnallocableList.insert(rnUnallocableList.end(), nId );
	}		}
	}		}
	/// \brief Heuristically reduce one of the nodes in the heuristic		/// \brief Heuristically reduce one of the nodes in the heuristic
	/// reduce list.		/// reduce list.
	/// @return True if a reduction takes place, false if the heuristic r educe		/// @return True if a reduction takes place, false if the heuristic r educe
	/// list is empty.		/// list is empty.
	///		///
	/// If the list of allocable nodes is non-empty a node is selected		/// If the list of allocable nodes is non-empty a node is selected
	/// from it and pushed to the stack. Otherwise if the non-allocable l ist		/// from it and pushed to the stack. Otherwise if the non-allocable l ist
	/// is non-empty a node is selected from it and pushed to the stack.		/// is non-empty a node is selected from it and pushed to the stack.
	/// If both lists are empty the method simply returns false with no a ction		/// If both lists are empty the method simply returns false with no a ction
	/// taken.		/// taken.
	bool heuristicReduce() {		bool heuristicReduce() {
	if (!rnAllocableList.empty()) {		if (!rnAllocableList.empty()) {
	RNAllocableListItr rnaItr =		RNAllocableListItr rnaItr =
	min_element(rnAllocableList.begin(), rnAllocableList.end(),		min_element(rnAllocableList.begin(), rnAllocableList.end(),
	LinkDegreeComparator(getSolver()));		LinkDegreeComparator(getSolver()));
	Graph::NodeItr nItr = *rnaItr;		Graph::NodeId nId = *rnaItr;
	rnAllocableList.erase(rnaItr);		rnAllocableList.erase(rnaItr);
	handleRemoveNode(nItr);		handleRemoveNode(nId);
	getSolver().pushToStack(nItr);		getSolver().pushToStack(nId);
	return true;		return true;
	} else if (!rnUnallocableList.empty()) {		} else if (!rnUnallocableList.empty()) {
	RNUnallocableListItr rnuItr =		RNUnallocableListItr rnuItr =
	min_element(rnUnallocableList.begin(), rnUnallocableList.end(),		min_element(rnUnallocableList.begin(), rnUnallocableList.end(),
	SpillCostComparator(getSolver()));		SpillCostComparator(getSolver()));
	Graph::NodeItr nItr = *rnuItr;		Graph::NodeId nId = *rnuItr;
	rnUnallocableList.erase(rnuItr);		rnUnallocableList.erase(rnuItr);
	handleRemoveNode(nItr);		handleRemoveNode(nId);
	getSolver().pushToStack(nItr);		getSolver().pushToStack(nId);
	return true;		return true;
	}		}
	// else		// else
	return false;		return false;
	}		}
	/// \brief Prepare a change in the costs on the given edge.		/// \brief Prepare a change in the costs on the given edge.
	/// @param eItr Edge iterator.		/// @param eId Edge id.
	void preUpdateEdgeCosts(Graph::EdgeItr eItr) {		void preUpdateEdgeCosts(Graph::EdgeId eId) {
	Graph &g = getGraph();		Graph &g = getGraph();
	Graph::NodeItr n1Itr = g.getEdgeNode1(eItr),		Graph::NodeId n1Id = g.getEdgeNode1(eId),
	n2Itr = g.getEdgeNode2(eItr);		n2Id = g.getEdgeNode2(eId);
	NodeData &n1 = getHeuristicNodeData(n1Itr),		NodeData &n1 = getHeuristicNodeData(n1Id),
	&n2 = getHeuristicNodeData(n2Itr);		&n2 = getHeuristicNodeData(n2Id);
	if (n1.isHeuristic)		if (n1.isHeuristic)
	subtractEdgeContributions(eItr, getGraph().getEdgeNode1(eItr));		subtractEdgeContributions(eId, getGraph().getEdgeNode1(eId));
	if (n2.isHeuristic)		if (n2.isHeuristic)
	subtractEdgeContributions(eItr, getGraph().getEdgeNode2(eItr));		subtractEdgeContributions(eId, getGraph().getEdgeNode2(eId));
	EdgeData &ed = getHeuristicEdgeData(eItr);		EdgeData &ed = getHeuristicEdgeData(eId);
	ed.isUpToDate = false;		ed.isUpToDate = false;
	}		}
	/// \brief Handle the change in the costs on the given edge.		/// \brief Handle the change in the costs on the given edge.
	/// @param eItr Edge iterator.		/// @param eId Edge id.
	void postUpdateEdgeCosts(Graph::EdgeItr eItr) {		void postUpdateEdgeCosts(Graph::EdgeId eId) {
	// This is effectively the same as adding a new edge now, since		// This is effectively the same as adding a new edge now, since
	// we've factored out the costs of the old one.		// we've factored out the costs of the old one.
	handleAddEdge(eItr);		handleAddEdge(eId);
	}		}
	/// \brief Handle the addition of a new edge into the PBQP graph.		/// \brief Handle the addition of a new edge into the PBQP graph.
	/// @param eItr Edge iterator for the added edge.		/// @param eId Edge id for the added edge.
	///		///
	/// Updates allocability of any nodes connected by this edge which ar e		/// Updates allocability of any nodes connected by this edge which ar e
	/// being managed by the heuristic. If allocability changes they are		/// being managed by the heuristic. If allocability changes they are
	/// moved to the appropriate list.		/// moved to the appropriate list.
	void handleAddEdge(Graph::EdgeItr eItr) {		void handleAddEdge(Graph::EdgeId eId) {
	Graph &g = getGraph();		Graph &g = getGraph();
	Graph::NodeItr n1Itr = g.getEdgeNode1(eItr),		Graph::NodeId n1Id = g.getEdgeNode1(eId),
	n2Itr = g.getEdgeNode2(eItr);		n2Id = g.getEdgeNode2(eId);
	NodeData &n1 = getHeuristicNodeData(n1Itr),		NodeData &n1 = getHeuristicNodeData(n1Id),
	&n2 = getHeuristicNodeData(n2Itr);		&n2 = getHeuristicNodeData(n2Id);
	// If neither node is managed by the heuristic there's nothing to b e		// If neither node is managed by the heuristic there's nothing to b e
	// done.		// done.
	if (!n1.isHeuristic && !n2.isHeuristic)		if (!n1.isHeuristic && !n2.isHeuristic)
	return;		return;
	// Ok - we need to update at least one node.		// Ok - we need to update at least one node.
	computeEdgeContributions(eItr);		computeEdgeContributions(eId);
	// Update node 1 if it's managed by the heuristic.		// Update node 1 if it's managed by the heuristic.
	if (n1.isHeuristic) {		if (n1.isHeuristic) {
	bool n1WasAllocable = n1.isAllocable;		bool n1WasAllocable = n1.isAllocable;
	addEdgeContributions(eItr, n1Itr);		addEdgeContributions(eId, n1Id);
	updateAllocability(n1Itr);		updateAllocability(n1Id);
	if (n1WasAllocable && !n1.isAllocable) {		if (n1WasAllocable && !n1.isAllocable) {
	rnAllocableList.erase(n1.rnaItr);		rnAllocableList.erase(n1.rnaItr);
	n1.rnuItr =		n1.rnuItr =
	rnUnallocableList.insert(rnUnallocableList.end(), n1Itr);		rnUnallocableList.insert(rnUnallocableList.end(), n1Id);
	}		}
	}		}
	// Likewise for node 2.		// Likewise for node 2.
	if (n2.isHeuristic) {		if (n2.isHeuristic) {
	bool n2WasAllocable = n2.isAllocable;		bool n2WasAllocable = n2.isAllocable;
	addEdgeContributions(eItr, n2Itr);		addEdgeContributions(eId, n2Id);
	updateAllocability(n2Itr);		updateAllocability(n2Id);
	if (n2WasAllocable && !n2.isAllocable) {		if (n2WasAllocable && !n2.isAllocable) {
	rnAllocableList.erase(n2.rnaItr);		rnAllocableList.erase(n2.rnaItr);
	n2.rnuItr =		n2.rnuItr =
	rnUnallocableList.insert(rnUnallocableList.end(), n2Itr);		rnUnallocableList.insert(rnUnallocableList.end(), n2Id);
	}		}
	}		}
	}		}
	/// \brief Handle disconnection of an edge from a node.		/// \brief Handle disconnection of an edge from a node.
	/// @param eItr Edge iterator for edge being disconnected.		/// @param eId Edge id for edge being disconnected.
	/// @param nItr Node iterator for the node being disconnected from.		/// @param nId Node id for the node being disconnected from.
	///		///
	/// Updates allocability of the given node and, if appropriate, moves the		/// Updates allocability of the given node and, if appropriate, moves the
	/// node to a new list.		/// node to a new list.
	void handleRemoveEdge(Graph::EdgeItr eItr, Graph::NodeItr nItr) {		void handleRemoveEdge(Graph::EdgeId eId, Graph::NodeId nId) {
	NodeData &nd = getHeuristicNodeData(nItr);		NodeData &nd =getHeuristicNodeData(nId);
	// If the node is not managed by the heuristic there's nothing to b e		// If the node is not managed by the heuristic there's nothing to b e
	// done.		// done.
	if (!nd.isHeuristic)		if (!nd.isHeuristic)
	return;		return;
	EdgeData &ed = getHeuristicEdgeData(eItr);		EdgeData &ed = getHeuristicEdgeData(eId);
	(void)ed;		(void)ed;
	assert(ed.isUpToDate && "Edge data is not up to date.");		assert(ed.isUpToDate && "Edge data is not up to date.");
	// Update node.		// Update node.
	bool ndWasAllocable = nd.isAllocable;		bool ndWasAllocable = nd.isAllocable;
	subtractEdgeContributions(eItr, nItr);		subtractEdgeContributions(eId, nId);
	updateAllocability(nItr);		updateAllocability(nId);
	// If the node has gone optimal...		// If the node has gone optimal...
	if (shouldOptimallyReduce(nItr)) {		if (shouldOptimallyReduce(nId)) {
	nd.isHeuristic = false;		nd.isHeuristic = false;
	addToOptimalReduceList(nItr);		addToOptimalReduceList(nId);
	if (ndWasAllocable) {		if (ndWasAllocable) {
	rnAllocableList.erase(nd.rnaItr);		rnAllocableList.erase(nd.rnaItr);
	} else {		} else {
	rnUnallocableList.erase(nd.rnuItr);		rnUnallocableList.erase(nd.rnuItr);
	}		}
	} else {		} else {
	// Node didn't go optimal, but we might have to move it		// Node didn't go optimal, but we might have to move it
	// from "unallocable" to "allocable".		// from "unallocable" to "allocable".
	if (!ndWasAllocable && nd.isAllocable) {		if (!ndWasAllocable && nd.isAllocable) {
	rnUnallocableList.erase(nd.rnuItr);		rnUnallocableList.erase(nd.rnuItr);
	nd.rnaItr = rnAllocableList.insert(rnAllocableList.end(), nItr) ;		nd.rnaItr = rnAllocableList.insert(rnAllocableList.end(), nId);
	}		}
	}		}
	}		}
	private:		private:
	NodeData& getHeuristicNodeData(Graph::NodeItr nItr) {		NodeData& getHeuristicNodeData(Graph::NodeId nId) {
	return getSolver().getHeuristicNodeData(nItr);		return getSolver().getHeuristicNodeData(nId);
	}		}
	EdgeData& getHeuristicEdgeData(Graph::EdgeItr eItr) {		EdgeData& getHeuristicEdgeData(Graph::EdgeId eId) {
	return getSolver().getHeuristicEdgeData(eItr);		return getSolver().getHeuristicEdgeData(eId);
	}		}
	// Work out what this edge will contribute to the allocability of the		// Work out what this edge will contribute to the allocability of the
	// nodes connected to it.		// nodes connected to it.
	void computeEdgeContributions(Graph::EdgeItr eItr) {		void computeEdgeContributions(Graph::EdgeId eId) {
	EdgeData &ed = getHeuristicEdgeData(eItr);		EdgeData &ed = getHeuristicEdgeData(eId);
	if (ed.isUpToDate)		if (ed.isUpToDate)
	return; // Edge data is already up to date.		return; // Edge data is already up to date.
	Matrix &eCosts = getGraph().getEdgeCosts(eItr);		Matrix &eCosts = getGraph().getEdgeCosts(eId);
	unsigned numRegs = eCosts.getRows() - 1,		unsigned numRegs = eCosts.getRows() - 1,
	numReverseRegs = eCosts.getCols() - 1;		numReverseRegs = eCosts.getCols() - 1;
	std::vector<unsigned> rowInfCounts(numRegs, 0),		std::vector<unsigned> rowInfCounts(numRegs, 0),
	colInfCounts(numReverseRegs, 0);		colInfCounts(numReverseRegs, 0);
	ed.worst = 0;		ed.worst = 0;
	ed.reverseWorst = 0;		ed.reverseWorst = 0;
	ed.unsafe.clear();		ed.unsafe.clear();
	skipping to change at line 355		skipping to change at line 355
	}		}
	}		}
	ed.isUpToDate = true;		ed.isUpToDate = true;
	}		}
	// Add the contributions of the given edge to the given node's		// Add the contributions of the given edge to the given node's
	// numDenied and safe members. No action is taken other than to updat e		// numDenied and safe members. No action is taken other than to updat e
	// these member values. Once updated these numbers can be used by cli ents		// these member values. Once updated these numbers can be used by cli ents
	// to update the node's allocability.		// to update the node's allocability.
	void addEdgeContributions(Graph::EdgeItr eItr, Graph::NodeItr nItr) {		void addEdgeContributions(Graph::EdgeId eId, Graph::NodeId nId) {
	EdgeData &ed = getHeuristicEdgeData(eItr);		EdgeData &ed = getHeuristicEdgeData(eId);
	assert(ed.isUpToDate && "Using out-of-date edge numbers.");		assert(ed.isUpToDate && "Using out-of-date edge numbers.");
	NodeData &nd = getHeuristicNodeData(nItr);		NodeData &nd = getHeuristicNodeData(nId);
	unsigned numRegs = getGraph().getNodeCosts(nItr).getLength() - 1;		unsigned numRegs = getGraph().getNodeCosts(nId).getLength() - 1;
	bool nIsNode1 = nItr == getGraph().getEdgeNode1(eItr);		bool nIsNode1 = nId == getGraph().getEdgeNode1(eId);
	EdgeData::UnsafeArray &unsafe =		EdgeData::UnsafeArray &unsafe =
	nIsNode1 ? ed.unsafe : ed.reverseUnsafe;		nIsNode1 ? ed.unsafe : ed.reverseUnsafe;
	nd.numDenied += nIsNode1 ? ed.worst : ed.reverseWorst;		nd.numDenied += nIsNode1 ? ed.worst : ed.reverseWorst;
	for (unsigned r = 0; r < numRegs; ++r) {		for (unsigned r = 0; r < numRegs; ++r) {
	if (unsafe[r]) {		if (unsafe[r]) {
	if (nd.unsafeDegrees[r]==0) {		if (nd.unsafeDegrees[r]==0) {
	--nd.numSafe;		--nd.numSafe;
	}		}
	++nd.unsafeDegrees[r];		++nd.unsafeDegrees[r];
	}		}
	}		}
	}		}
	// Subtract the contributions of the given edge to the given node's		// Subtract the contributions of the given edge to the given node's
	// numDenied and safe members. No action is taken other than to updat e		// numDenied and safe members. No action is taken other than to updat e
	// these member values. Once updated these numbers can be used by cli ents		// these member values. Once updated these numbers can be used by cli ents
	// to update the node's allocability.		// to update the node's allocability.
	void subtractEdgeContributions(Graph::EdgeItr eItr, Graph::NodeItr nI		void subtractEdgeContributions(Graph::EdgeId eId, Graph::NodeId nId)
	tr) {		{
	EdgeData &ed = getHeuristicEdgeData(eItr);		EdgeData &ed = getHeuristicEdgeData(eId);
	assert(ed.isUpToDate && "Using out-of-date edge numbers.");		assert(ed.isUpToDate && "Using out-of-date edge numbers.");
	NodeData &nd = getHeuristicNodeData(nItr);		NodeData &nd = getHeuristicNodeData(nId);
	unsigned numRegs = getGraph().getNodeCosts(nItr).getLength() - 1;		unsigned numRegs = getGraph().getNodeCosts(nId).getLength() - 1;
	bool nIsNode1 = nItr == getGraph().getEdgeNode1(eItr);		bool nIsNode1 = nId == getGraph().getEdgeNode1(eId);
	EdgeData::UnsafeArray &unsafe =		EdgeData::UnsafeArray &unsafe =
	nIsNode1 ? ed.unsafe : ed.reverseUnsafe;		nIsNode1 ? ed.unsafe : ed.reverseUnsafe;
	nd.numDenied -= nIsNode1 ? ed.worst : ed.reverseWorst;		nd.numDenied -= nIsNode1 ? ed.worst : ed.reverseWorst;
	for (unsigned r = 0; r < numRegs; ++r) {		for (unsigned r = 0; r < numRegs; ++r) {
	if (unsafe[r]) {		if (unsafe[r]) {
	if (nd.unsafeDegrees[r] == 1) {		if (nd.unsafeDegrees[r] == 1) {
	++nd.numSafe;		++nd.numSafe;
	}		}
	--nd.unsafeDegrees[r];		--nd.unsafeDegrees[r];
	}		}
	}		}
	}		}
	void updateAllocability(Graph::NodeItr nItr) {		void updateAllocability(Graph::NodeId nId) {
	NodeData &nd = getHeuristicNodeData(nItr);		NodeData &nd = getHeuristicNodeData(nId);
	unsigned numRegs = getGraph().getNodeCosts(nItr).getLength() - 1;		unsigned numRegs = getGraph().getNodeCosts(nId).getLength() - 1;
	nd.isAllocable = nd.numDenied < numRegs || nd.numSafe > 0;		nd.isAllocable = nd.numDenied < numRegs || nd.numSafe > 0;
	}		}
	void initializeNode(Graph::NodeItr nItr) {		void initializeNode(Graph::NodeId nId) {
	NodeData &nd = getHeuristicNodeData(nItr);		NodeData &nd = getHeuristicNodeData(nId);
	if (nd.isInitialized)		if (nd.isInitialized)
	return; // Node data is already up to date.		return; // Node data is already up to date.
	unsigned numRegs = getGraph().getNodeCosts(nItr).getLength() - 1;		unsigned numRegs = getGraph().getNodeCosts(nId).getLength() - 1;
	nd.numDenied = 0;		nd.numDenied = 0;
	const Vector& nCosts = getGraph().getNodeCosts(nItr);		const Vector& nCosts = getGraph().getNodeCosts(nId);
	for (unsigned i = 1; i < nCosts.getLength(); ++i) {		for (unsigned i = 1; i < nCosts.getLength(); ++i) {
	if (nCosts[i] == std::numeric_limits<PBQPNum>::infinity())		if (nCosts[i] == std::numeric_limits<PBQPNum>::infinity())
	++nd.numDenied;		++nd.numDenied;
	}		}
	nd.numSafe = numRegs;		nd.numSafe = numRegs;
	nd.unsafeDegrees.resize(numRegs, 0);		nd.unsafeDegrees.resize(numRegs, 0);
	typedef HeuristicSolverImpl<Briggs>::SolverEdgeItr SolverEdgeItr;		typedef HeuristicSolverImpl<Briggs>::SolverEdgeItr SolverEdgeItr;
	for (SolverEdgeItr aeItr = getSolver().solverEdgesBegin(nItr),		for (SolverEdgeItr aeItr = getSolver().solverEdgesBegin(nId),
	aeEnd = getSolver().solverEdgesEnd(nItr);		aeEnd = getSolver().solverEdgesEnd(nId);
	aeItr != aeEnd; ++aeItr) {		aeItr != aeEnd; ++aeItr) {
	Graph::EdgeItr eItr = *aeItr;		Graph::EdgeId eId = *aeItr;
	computeEdgeContributions(eItr);		computeEdgeContributions(eId);
	addEdgeContributions(eItr, nItr);		addEdgeContributions(eId, nId);
	}		}
	updateAllocability(nItr);		updateAllocability(nId);
	nd.isInitialized = true;		nd.isInitialized = true;
	}		}
	void handleRemoveNode(Graph::NodeItr xnItr) {		void handleRemoveNode(Graph::NodeId xnId) {
	typedef HeuristicSolverImpl<Briggs>::SolverEdgeItr SolverEdgeItr;		typedef HeuristicSolverImpl<Briggs>::SolverEdgeItr SolverEdgeItr;
	std::vector<Graph::EdgeItr> edgesToRemove;		std::vector<Graph::EdgeId> edgesToRemove;
	for (SolverEdgeItr aeItr = getSolver().solverEdgesBegin(xnItr),		for (SolverEdgeItr aeItr = getSolver().solverEdgesBegin(xnId),
	aeEnd = getSolver().solverEdgesEnd(xnItr);		aeEnd = getSolver().solverEdgesEnd(xnId);
	aeItr != aeEnd; ++aeItr) {		aeItr != aeEnd; ++aeItr) {
	Graph::NodeItr ynItr = getGraph().getEdgeOtherNode(*aeItr, xnItr)		Graph::NodeId ynId = getGraph().getEdgeOtherNode(*aeItr, xnId);
	;		handleRemoveEdge(*aeItr, ynId);
	handleRemoveEdge(*aeItr, ynItr);
	edgesToRemove.push_back(*aeItr);		edgesToRemove.push_back(*aeItr);
	}		}
	while (!edgesToRemove.empty()) {		while (!edgesToRemove.empty()) {
	getSolver().removeSolverEdge(edgesToRemove.back());		getSolver().removeSolverEdge(edgesToRemove.back());
	edgesToRemove.pop_back();		edgesToRemove.pop_back();
	}		}
	}		}
	RNAllocableList rnAllocableList;		RNAllocableList rnAllocableList;
	RNUnallocableList rnUnallocableList;		RNUnallocableList rnUnallocableList;
End of changes. 56 change blocks.
	97 lines changed or deleted		96 lines changed or added

	CFG.h		CFG.h
	skipping to change at line 241		skipping to change at line 241
	inline succ_const_iterator succ_begin(const BasicBlock *BB) {		inline succ_const_iterator succ_begin(const BasicBlock *BB) {
	return succ_const_iterator(BB->getTerminator());		return succ_const_iterator(BB->getTerminator());
	}		}
	inline succ_iterator succ_end(BasicBlock *BB) {		inline succ_iterator succ_end(BasicBlock *BB) {
	return succ_iterator(BB->getTerminator(), true);		return succ_iterator(BB->getTerminator(), true);
	}		}
	inline succ_const_iterator succ_end(const BasicBlock *BB) {		inline succ_const_iterator succ_end(const BasicBlock *BB) {
	return succ_const_iterator(BB->getTerminator(), true);		return succ_const_iterator(BB->getTerminator(), true);
	}		}
			template <typename T, typename U> struct isPodLike<SuccIterator<T, U> > {
			static const bool value = isPodLike<T>::value;
			};
	//===--------------------------------------------------------------------== =//		//===--------------------------------------------------------------------== =//
	// GraphTraits specializations for basic block graphs (CFGs)		// GraphTraits specializations for basic block graphs (CFGs)
	//===--------------------------------------------------------------------== =//		//===--------------------------------------------------------------------== =//
	// Provide specializations of GraphTraits to be able to treat a function as a		// Provide specializations of GraphTraits to be able to treat a function as a
	// graph of basic blocks...		// graph of basic blocks...
	template <> struct GraphTraits<BasicBlock*> {		template <> struct GraphTraits<BasicBlock*> {
	typedef BasicBlock NodeType;		typedef BasicBlock NodeType;
	typedef succ_iterator ChildIteratorType;		typedef succ_iterator ChildIteratorType;
	skipping to change at line 321		skipping to change at line 325
	// graph of basic blocks... these are the same as the basic block iterators ,		// graph of basic blocks... these are the same as the basic block iterators ,
	// except that the root node is implicitly the first node of the function.		// except that the root node is implicitly the first node of the function.
	//		//
	template <> struct GraphTraits<Function*> : public GraphTraits<BasicBlock*> {		template <> struct GraphTraits<Function*> : public GraphTraits<BasicBlock*> {
	static NodeType *getEntryNode(Function *F) { return &F->getEntryBlock(); }		static NodeType *getEntryNode(Function *F) { return &F->getEntryBlock(); }
	// nodes_iterator/begin/end - Allow iteration over all nodes in the graph		// nodes_iterator/begin/end - Allow iteration over all nodes in the graph
	typedef Function::iterator nodes_iterator;		typedef Function::iterator nodes_iterator;
	static nodes_iterator nodes_begin(Function *F) { return F->begin(); }		static nodes_iterator nodes_begin(Function *F) { return F->begin(); }
	static nodes_iterator nodes_end (Function *F) { return F->end(); }		static nodes_iterator nodes_end (Function *F) { return F->end(); }
	static unsigned size (Function *F) { return F->size(); }		static size_t size (Function *F) { return F->size(); }
	};		};
	template <> struct GraphTraits<const Function*> :		template <> struct GraphTraits<const Function*> :
	public GraphTraits<const BasicBlock*> {		public GraphTraits<const BasicBlock*> {
	static NodeType *getEntryNode(const Function *F) {return &F->getEntryBloc k();}		static NodeType *getEntryNode(const Function *F) {return &F->getEntryBloc k();}
	// nodes_iterator/begin/end - Allow iteration over all nodes in the graph		// nodes_iterator/begin/end - Allow iteration over all nodes in the graph
	typedef Function::const_iterator nodes_iterator;		typedef Function::const_iterator nodes_iterator;
	static nodes_iterator nodes_begin(const Function *F) { return F->begin(); }		static nodes_iterator nodes_begin(const Function *F) { return F->begin(); }
	static nodes_iterator nodes_end (const Function *F) { return F->end(); }		static nodes_iterator nodes_end (const Function *F) { return F->end(); }
	static unsigned size (const Function *F) { return F->size(); }		static size_t size (const Function *F) { return F->size(); }
	};		};
	// Provide specializations of GraphTraits to be able to treat a function as a		// Provide specializations of GraphTraits to be able to treat a function as a
	// graph of basic blocks... and to walk it in inverse order. Inverse order for		// graph of basic blocks... and to walk it in inverse order. Inverse order for
	// a function is considered to be when traversing the predecessor edges of a BB		// a function is considered to be when traversing the predecessor edges of a BB
	// instead of the successor edges.		// instead of the successor edges.
	//		//
	template <> struct GraphTraits<Inverse<Function*> > :		template <> struct GraphTraits<Inverse<Function*> > :
	public GraphTraits<Inverse<BasicBlock*> > {		public GraphTraits<Inverse<BasicBlock*> > {
	static NodeType *getEntryNode(Inverse<Function*> G) {		static NodeType *getEntryNode(Inverse<Function*> G) {
End of changes. 3 change blocks.
	2 lines changed or deleted		6 lines changed or added

	CFGPrinter.h		CFGPrinter.h
	skipping to change at line 49		skipping to change at line 49
	std::string Str;		std::string Str;
	raw_string_ostream OS(Str);		raw_string_ostream OS(Str);
	WriteAsOperand(OS, Node, false);		WriteAsOperand(OS, Node, false);
	return OS.str();		return OS.str();
	}		}
	static std::string getCompleteNodeLabel(const BasicBlock *Node,		static std::string getCompleteNodeLabel(const BasicBlock *Node,
	const Function *) {		const Function *) {
			enum { MaxColumns = 80 };
	std::string Str;		std::string Str;
	raw_string_ostream OS(Str);		raw_string_ostream OS(Str);
	if (Node->getName().empty()) {		if (Node->getName().empty()) {
	WriteAsOperand(OS, Node, false);		WriteAsOperand(OS, Node, false);
	OS << ":";		OS << ":";
	}		}
	OS << *Node;		OS << *Node;
	std::string OutStr = OS.str();		std::string OutStr = OS.str();
	if (OutStr[0] == '\n') OutStr.erase(OutStr.begin());		if (OutStr[0] == '\n') OutStr.erase(OutStr.begin());
	// Process string output to make it nicer...		// Process string output to make it nicer...
	for (unsigned i = 0; i != OutStr.length(); ++i)		unsigned ColNum = 0;
			unsigned LastSpace = 0;
			for (unsigned i = 0; i != OutStr.length(); ++i) {
	if (OutStr[i] == '\n') { // Left justify		if (OutStr[i] == '\n') { // Left justify
	OutStr[i] = '\\';		OutStr[i] = '\\';
	OutStr.insert(OutStr.begin()+i+1, 'l');		OutStr.insert(OutStr.begin()+i+1, 'l');
			ColNum = 0;
			LastSpace = 0;
	} else if (OutStr[i] == ';') { // Delete comment s!		} else if (OutStr[i] == ';') { // Delete comment s!
	unsigned Idx = OutStr.find('\n', i+1); // Find end of li ne		unsigned Idx = OutStr.find('\n', i+1); // Find end of li ne
	OutStr.erase(OutStr.begin()+i, OutStr.begin()+Idx);		OutStr.erase(OutStr.begin()+i, OutStr.begin()+Idx);
	--i;		--i;
			} else if (ColNum == MaxColumns) { // Wrap lines.
			if (LastSpace) {
			OutStr.insert(LastSpace, "\\l...");
			ColNum = i - LastSpace;
			LastSpace = 0;
			i += 3; // The loop will advance 'i' again.
			}
			// Else keep trying to find a space.
	}		}
			else
			++ColNum;
			if (OutStr[i] == ' ')
			LastSpace = i;
			}
	return OutStr;		return OutStr;
	}		}
	std::string getNodeLabel(const BasicBlock *Node,		std::string getNodeLabel(const BasicBlock *Node,
	const Function *Graph) {		const Function *Graph) {
	if (isSimple())		if (isSimple())
	return getSimpleNodeLabel(Node, Graph);		return getSimpleNodeLabel(Node, Graph);
	else		else
	return getCompleteNodeLabel(Node, Graph);		return getCompleteNodeLabel(Node, Graph);
	}		}
End of changes. 5 change blocks.
	2 lines changed or deleted		19 lines changed or added

	COFF.h		COFF.h
	skipping to change at line 26		skipping to change at line 26
	#include "llvm/Object/ObjectFile.h"		#include "llvm/Object/ObjectFile.h"
	#include "llvm/Support/COFF.h"		#include "llvm/Support/COFF.h"
	#include "llvm/Support/Endian.h"		#include "llvm/Support/Endian.h"
	namespace llvm {		namespace llvm {
	template <typename T>		template <typename T>
	class ArrayRef;		class ArrayRef;
	namespace object {		namespace object {
			class ImportDirectoryEntryRef;
			typedef content_iterator<ImportDirectoryEntryRef> import_directory_iterator
			;
			/// The DOS compatible header at the front of all PE/COFF executables.
			struct dos_header {
			support::ulittle16_t Magic;
			support::ulittle16_t UsedBytesInTheLastPage;
			support::ulittle16_t FileSizeInPages;
			support::ulittle16_t NumberOfRelocationItems;
			support::ulittle16_t HeaderSizeInParagraphs;
			support::ulittle16_t MinimumExtraParagraphs;
			support::ulittle16_t MaximumExtraParagraphs;
			support::ulittle16_t InitialRelativeSS;
			support::ulittle16_t InitialSP;
			support::ulittle16_t Checksum;
			support::ulittle16_t InitialIP;
			support::ulittle16_t InitialRelativeCS;
			support::ulittle16_t AddressOfRelocationTable;
			support::ulittle16_t OverlayNumber;
			support::ulittle16_t Reserved[4];
			support::ulittle16_t OEMid;
			support::ulittle16_t OEMinfo;
			support::ulittle16_t Reserved2[10];
			support::ulittle32_t AddressOfNewExeHeader;
			};
	struct coff_file_header {		struct coff_file_header {
	support::ulittle16_t Machine;		support::ulittle16_t Machine;
	support::ulittle16_t NumberOfSections;		support::ulittle16_t NumberOfSections;
	support::ulittle32_t TimeDateStamp;		support::ulittle32_t TimeDateStamp;
	support::ulittle32_t PointerToSymbolTable;		support::ulittle32_t PointerToSymbolTable;
	support::ulittle32_t NumberOfSymbols;		support::ulittle32_t NumberOfSymbols;
	support::ulittle16_t SizeOfOptionalHeader;		support::ulittle16_t SizeOfOptionalHeader;
	support::ulittle16_t Characteristics;		support::ulittle16_t Characteristics;
			bool isImportLibrary() const { return NumberOfSections == 0xffff; }
			};
			/// The 32-bit PE header that follows the COFF header.
			struct pe32_header {
			support::ulittle16_t Magic;
			uint8_t MajorLinkerVersion;
			uint8_t MinorLinkerVersion;
			support::ulittle32_t SizeOfCode;
			support::ulittle32_t SizeOfInitializedData;
			support::ulittle32_t SizeOfUninitializedData;
			support::ulittle32_t AddressOfEntryPoint;
			support::ulittle32_t BaseOfCode;
			support::ulittle32_t BaseOfData;
			support::ulittle32_t ImageBase;
			support::ulittle32_t SectionAlignment;
			support::ulittle32_t FileAlignment;
			support::ulittle16_t MajorOperatingSystemVersion;
			support::ulittle16_t MinorOperatingSystemVersion;
			support::ulittle16_t MajorImageVersion;
			support::ulittle16_t MinorImageVersion;
			support::ulittle16_t MajorSubsystemVersion;
			support::ulittle16_t MinorSubsystemVersion;
			support::ulittle32_t Win32VersionValue;
			support::ulittle32_t SizeOfImage;
			support::ulittle32_t SizeOfHeaders;
			support::ulittle32_t CheckSum;
			support::ulittle16_t Subsystem;
			support::ulittle16_t DLLCharacteristics;
			support::ulittle32_t SizeOfStackReserve;
			support::ulittle32_t SizeOfStackCommit;
			support::ulittle32_t SizeOfHeapReserve;
			support::ulittle32_t SizeOfHeapCommit;
			support::ulittle32_t LoaderFlags;
			support::ulittle32_t NumberOfRvaAndSize;
			};
			/// The 64-bit PE header that follows the COFF header.
			struct pe32plus_header {
			support::ulittle16_t Magic;
			uint8_t MajorLinkerVersion;
			uint8_t MinorLinkerVersion;
			support::ulittle32_t SizeOfCode;
			support::ulittle32_t SizeOfInitializedData;
			support::ulittle32_t SizeOfUninitializedData;
			support::ulittle32_t AddressOfEntryPoint;
			support::ulittle32_t BaseOfCode;
			support::ulittle64_t ImageBase;
			support::ulittle32_t SectionAlignment;
			support::ulittle32_t FileAlignment;
			support::ulittle16_t MajorOperatingSystemVersion;
			support::ulittle16_t MinorOperatingSystemVersion;
			support::ulittle16_t MajorImageVersion;
			support::ulittle16_t MinorImageVersion;
			support::ulittle16_t MajorSubsystemVersion;
			support::ulittle16_t MinorSubsystemVersion;
			support::ulittle32_t Win32VersionValue;
			support::ulittle32_t SizeOfImage;
			support::ulittle32_t SizeOfHeaders;
			support::ulittle32_t CheckSum;
			support::ulittle16_t Subsystem;
			support::ulittle16_t DLLCharacteristics;
			support::ulittle64_t SizeOfStackReserve;
			support::ulittle64_t SizeOfStackCommit;
			support::ulittle64_t SizeOfHeapReserve;
			support::ulittle64_t SizeOfHeapCommit;
			support::ulittle32_t LoaderFlags;
			support::ulittle32_t NumberOfRvaAndSize;
			};
			struct data_directory {
			support::ulittle32_t RelativeVirtualAddress;
			support::ulittle32_t Size;
			};
			struct import_directory_table_entry {
			support::ulittle32_t ImportLookupTableRVA;
			support::ulittle32_t TimeDateStamp;
			support::ulittle32_t ForwarderChain;
			support::ulittle32_t NameRVA;
			support::ulittle32_t ImportAddressTableRVA;
			};
			struct import_lookup_table_entry32 {
			support::ulittle32_t data;
			bool isOrdinal() const { return data & 0x80000000; }
			uint16_t getOrdinal() const {
			assert(isOrdinal() && "ILT entry is not an ordinal!");
			return data & 0xFFFF;
			}
			uint32_t getHintNameRVA() const {
			assert(!isOrdinal() && "ILT entry is not a Hint/Name RVA!");
			return data;
			}
	};		};
	struct coff_symbol {		struct coff_symbol {
	struct StringTableOffset {		struct StringTableOffset {
	support::ulittle32_t Zeroes;		support::ulittle32_t Zeroes;
	support::ulittle32_t Offset;		support::ulittle32_t Offset;
	};		};
	union {		union {
	char ShortName[8];		char ShortName[8];
	skipping to change at line 84		skipping to change at line 207
	support::ulittle16_t NumberOfLinenumbers;		support::ulittle16_t NumberOfLinenumbers;
	support::ulittle32_t Characteristics;		support::ulittle32_t Characteristics;
	};		};
	struct coff_relocation {		struct coff_relocation {
	support::ulittle32_t VirtualAddress;		support::ulittle32_t VirtualAddress;
	support::ulittle32_t SymbolTableIndex;		support::ulittle32_t SymbolTableIndex;
	support::ulittle16_t Type;		support::ulittle16_t Type;
	};		};
			struct coff_aux_weak_external {
			support::ulittle32_t TagIndex;
			support::ulittle32_t Characteristics;
			char Unused[10];
			};
	struct coff_aux_section_definition {		struct coff_aux_section_definition {
	support::ulittle32_t Length;		support::ulittle32_t Length;
	support::ulittle16_t NumberOfRelocations;		support::ulittle16_t NumberOfRelocations;
	support::ulittle16_t NumberOfLinenumbers;		support::ulittle16_t NumberOfLinenumbers;
	support::ulittle32_t CheckSum;		support::ulittle32_t CheckSum;
	support::ulittle16_t Number;		support::ulittle16_t Number;
	support::ulittle8_t Selection;		support::ulittle8_t Selection;
	char Unused[3];		char Unused[3];
	};		};
	class COFFObjectFile : public ObjectFile {		class COFFObjectFile : public ObjectFile {
	private:		private:
	const coff_file_header *Header;		friend class ImportDirectoryEntryRef;
			const coff_file_header *COFFHeader;
			const pe32_header *PE32Header;
			const data_directory *DataDirectory;
	const coff_section *SectionTable;		const coff_section *SectionTable;
	const coff_symbol *SymbolTable;		const coff_symbol *SymbolTable;
	const char *StringTable;		const char *StringTable;
	uint32_t StringTableSize;		uint32_t StringTableSize;
			const import_directory_table_entry *ImportDirectory;
			uint32_t NumberOfImportDirectory;
	error_code getString(uint32_t offset, StringRef &Res) const;		error_code getString(uint32_t offset, StringRef &Res) const;
	const coff_symbol *toSymb(DataRefImpl Symb) const;		const coff_symbol *toSymb(DataRefImpl Symb) const;
	const coff_section *toSec(DataRefImpl Sec) const;		const coff_section *toSec(DataRefImpl Sec) const;
	const coff_relocation *toRel(DataRefImpl Rel) const;		const coff_relocation *toRel(DataRefImpl Rel) const;
			error_code initSymbolTablePtr();
			error_code initImportTablePtr();
	protected:		protected:
	virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const;		virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const;
	virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const;		virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const;
	virtual error_code getSymbolFileOffset(DataRefImpl Symb, uint64_t &Res) c onst;		virtual error_code getSymbolFileOffset(DataRefImpl Symb, uint64_t &Res) c onst;
	virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) cons t;		virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) cons t;
	virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const;		virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const;
	virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const ;
	virtual error_code getSymbolFlags(DataRefImpl Symb, uint32_t &Res) const;		virtual error_code getSymbolFlags(DataRefImpl Symb, uint32_t &Res) const;
	virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::Type &Res) const;		virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::Type &Res) const;
	virtual error_code getSymbolSection(DataRefImpl Symb,		virtual error_code getSymbolSection(DataRefImpl Symb,
	section_iterator &Res) const;		section_iterator &Res) const;
	virtual error_code getSymbolValue(DataRefImpl Symb, uint64_t &Val) const;		virtual error_code getSymbolValue(DataRefImpl Symb, uint64_t &Val) const;
	virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const ;		virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const ;
	virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const;		virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const;
	virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) cons t;		virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) cons t;
	virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const;		virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const;
	skipping to change at line 137		skipping to change at line 273
	virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const;		virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const;
	virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const;		virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const;
	virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const;		virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const;
	virtual error_code isSectionVirtual(DataRefImpl Sec, bool &Res) const;		virtual error_code isSectionVirtual(DataRefImpl Sec, bool &Res) const;
	virtual error_code isSectionZeroInit(DataRefImpl Sec, bool &Res) const;		virtual error_code isSectionZeroInit(DataRefImpl Sec, bool &Res) const;
	virtual error_code isSectionReadOnlyData(DataRefImpl Sec, bool &Res) cons t;		virtual error_code isSectionReadOnlyData(DataRefImpl Sec, bool &Res) cons t;
	virtual error_code isSectionRequiredForExecution(DataRefImpl Sec,		virtual error_code isSectionRequiredForExecution(DataRefImpl Sec,
	bool &Res) const;		bool &Res) const;
	virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Sym b,		virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Sym b,
	bool &Result) const;		bool &Result) const;
	virtual relocation_iterator getSectionRelBegin(DataRefImpl Sec) const;		virtual relocation_iterator section_rel_begin(DataRefImpl Sec) const;
	virtual relocation_iterator getSectionRelEnd(DataRefImpl Sec) const;		virtual relocation_iterator section_rel_end(DataRefImpl Sec) const;
	virtual error_code getRelocationNext(DataRefImpl Rel,		virtual error_code getRelocationNext(DataRefImpl Rel,
	RelocationRef &Res) const;		RelocationRef &Res) const;
	virtual error_code getRelocationAddress(DataRefImpl Rel,		virtual error_code getRelocationAddress(DataRefImpl Rel,
	uint64_t &Res) const;		uint64_t &Res) const;
	virtual error_code getRelocationOffset(DataRefImpl Rel,		virtual error_code getRelocationOffset(DataRefImpl Rel,
	uint64_t &Res) const;		uint64_t &Res) const;
	virtual error_code getRelocationSymbol(DataRefImpl Rel,		virtual symbol_iterator getRelocationSymbol(DataRefImpl Rel) const;
	SymbolRef &Res) const;
	virtual error_code getRelocationType(DataRefImpl Rel,		virtual error_code getRelocationType(DataRefImpl Rel,
	uint64_t &Res) const;		uint64_t &Res) const;
	virtual error_code getRelocationTypeName(DataRefImpl Rel,		virtual error_code getRelocationTypeName(DataRefImpl Rel,
	SmallVectorImpl<char> &Result) c onst;		SmallVectorImpl<char> &Result) c onst;
	virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,
	int64_t &Res) const;
	virtual error_code getRelocationValueString(DataRefImpl Rel,		virtual error_code getRelocationValueString(DataRefImpl Rel,
	SmallVectorImpl<char> &Result) c onst;		SmallVectorImpl<char> &Result) c onst;
	virtual error_code getLibraryNext(DataRefImpl LibData,		virtual error_code getLibraryNext(DataRefImpl LibData,
	LibraryRef &Result) const;		LibraryRef &Result) const;
	virtual error_code getLibraryPath(DataRefImpl LibData,		virtual error_code getLibraryPath(DataRefImpl LibData,
	StringRef &Result) const;		StringRef &Result) const;
	public:		public:
	COFFObjectFile(MemoryBuffer *Object, error_code &ec);		COFFObjectFile(MemoryBuffer *Object, error_code &ec);
	skipping to change at line 182		skipping to change at line 315
	const coff_section *getCOFFSection(section_iterator &It) const;		const coff_section *getCOFFSection(section_iterator &It) const;
	const coff_symbol *getCOFFSymbol(symbol_iterator &It) const;		const coff_symbol *getCOFFSymbol(symbol_iterator &It) const;
	const coff_relocation *getCOFFRelocation(relocation_iterator &It) const;		const coff_relocation *getCOFFRelocation(relocation_iterator &It) const;
	virtual uint8_t getBytesInAddress() const;		virtual uint8_t getBytesInAddress() const;
	virtual StringRef getFileFormatName() const;		virtual StringRef getFileFormatName() const;
	virtual unsigned getArch() const;		virtual unsigned getArch() const;
	virtual StringRef getLoadName() const;		virtual StringRef getLoadName() const;
			import_directory_iterator import_directory_begin() const;
			import_directory_iterator import_directory_end() const;
	error_code getHeader(const coff_file_header *&Res) const;		error_code getHeader(const coff_file_header *&Res) const;
			error_code getCOFFHeader(const coff_file_header *&Res) const;
			error_code getPE32Header(const pe32_header *&Res) const;
			error_code getDataDirectory(uint32_t index, const data_directory *&Res) c
			onst;
	error_code getSection(int32_t index, const coff_section *&Res) const;		error_code getSection(int32_t index, const coff_section *&Res) const;
	error_code getSymbol(uint32_t index, const coff_symbol *&Res) const;		error_code getSymbol(uint32_t index, const coff_symbol *&Res) const;
	template <typename T>		template <typename T>
	error_code getAuxSymbol(uint32_t index, const T *&Res) const {		error_code getAuxSymbol(uint32_t index, const T *&Res) const {
	const coff_symbol *s;		const coff_symbol *s;
	error_code ec = getSymbol(index, s);		error_code ec = getSymbol(index, s);
	Res = reinterpret_cast<const T*>(s);		Res = reinterpret_cast<const T*>(s);
	return ec;		return ec;
	}		}
	error_code getSymbolName(const coff_symbol *symbol, StringRef &Res) const ;		error_code getSymbolName(const coff_symbol *symbol, StringRef &Res) const ;
	ArrayRef<uint8_t> getSymbolAuxData(const coff_symbol *symbol) const;		ArrayRef<uint8_t> getSymbolAuxData(const coff_symbol *symbol) const;
	error_code getSectionName(const coff_section *Sec, StringRef &Res) const;		error_code getSectionName(const coff_section *Sec, StringRef &Res) const;
	error_code getSectionContents(const coff_section *Sec,		error_code getSectionContents(const coff_section *Sec,
	ArrayRef<uint8_t> &Res) const;		ArrayRef<uint8_t> &Res) const;
			error_code getRvaPtr(uint32_t Rva, uintptr_t &Res) const;
			error_code getHintName(uint32_t Rva, uint16_t &Hint, StringRef &Name) con
			st;
	static inline bool classof(const Binary *v) {		static inline bool classof(const Binary *v) {
	return v->isCOFF();		return v->isCOFF();
	}		}
	};		};
	}		// The iterator for the import directory table.
	}		class ImportDirectoryEntryRef {
			public:
			ImportDirectoryEntryRef() : OwningObject(0) {}
			ImportDirectoryEntryRef(DataRefImpl ImportDirectory,
			const COFFObjectFile *Owner)
			: ImportDirectoryPimpl(ImportDirectory), OwningObject(Owner) {}
			bool operator==(const ImportDirectoryEntryRef &Other) const;
			error_code getNext(ImportDirectoryEntryRef &Result) const;
			error_code getName(StringRef &Result) const;
			error_code
			getImportTableEntry(const import_directory_table_entry *&Result) const;
			error_code
			getImportLookupEntry(const import_lookup_table_entry32 *&Result) const;
			private:
			DataRefImpl ImportDirectoryPimpl;
			const COFFObjectFile *OwningObject;
			};
			} // end namespace object
			} // end namespace llvm
	#endif		#endif
End of changes. 14 change blocks.
	10 lines changed or deleted		177 lines changed or added

	CalcSpillWeights.h		CalcSpillWeights.h
	skipping to change at line 20		skipping to change at line 20
	#ifndef LLVM_CODEGEN_CALCSPILLWEIGHTS_H		#ifndef LLVM_CODEGEN_CALCSPILLWEIGHTS_H
	#define LLVM_CODEGEN_CALCSPILLWEIGHTS_H		#define LLVM_CODEGEN_CALCSPILLWEIGHTS_H
	#include "llvm/ADT/DenseMap.h"		#include "llvm/ADT/DenseMap.h"
	#include "llvm/CodeGen/SlotIndexes.h"		#include "llvm/CodeGen/SlotIndexes.h"
	namespace llvm {		namespace llvm {
	class LiveInterval;		class LiveInterval;
	class LiveIntervals;		class LiveIntervals;
			class MachineBlockFrequencyInfo;
	class MachineLoopInfo;		class MachineLoopInfo;
	/// normalizeSpillWeight - The spill weight of a live interval is compute		/// \brief Normalize the spill weight of a live interval
	d as:		///
			/// The spill weight of a live interval is computed as:
	///		///
	/// (sum(use freq) + sum(def freq)) / (K + size)		/// (sum(use freq) + sum(def freq)) / (K + size)
	///		///
	/// @param UseDefFreq Expected number of executed use and def instruction s		/// @param UseDefFreq Expected number of executed use and def instruction s
	/// per function call. Derived from block frequencies.		/// per function call. Derived from block frequencies.
	/// @param Size Size of live interval as returnexd by getSize()		/// @param Size Size of live interval as returnexd by getSize()
	///		///
	static inline float normalizeSpillWeight(float UseDefFreq, unsigned Size) {		static inline float normalizeSpillWeight(float UseDefFreq, unsigned Size) {
	// The constant 25 instructions is added to avoid depending too much on		// The constant 25 instructions is added to avoid depending too much on
	// accidental SlotIndex gaps for small intervals. The effect is that sm all		// accidental SlotIndex gaps for small intervals. The effect is that sm all
	// intervals have a spill weight that is mostly proportional to the num ber		// intervals have a spill weight that is mostly proportional to the num ber
	// of uses, while large intervals get a spill weight that is closer to a use		// of uses, while large intervals get a spill weight that is closer to a use
	// density.		// density.
	return UseDefFreq / (Size + 25*SlotIndex::InstrDist);		return UseDefFreq / (Size + 25*SlotIndex::InstrDist);
	}		}
	/// VirtRegAuxInfo - Calculate auxiliary information for a virtual		/// \brief Calculate auxiliary information for a virtual register such as
	/// register such as its spill weight and allocation hint.		its
			/// spill weight and allocation hint.
	class VirtRegAuxInfo {		class VirtRegAuxInfo {
			public:
			typedef float (*NormalizingFn)(float, unsigned);
			private:
	MachineFunction &MF;		MachineFunction &MF;
	LiveIntervals &LIS;		LiveIntervals &LIS;
	const MachineLoopInfo &Loops;		const MachineLoopInfo &Loops;
			const MachineBlockFrequencyInfo &MBFI;
	DenseMap<unsigned, float> Hint;		DenseMap<unsigned, float> Hint;
			NormalizingFn normalize;
	public:		public:
	VirtRegAuxInfo(MachineFunction &mf, LiveIntervals &lis,		VirtRegAuxInfo(MachineFunction &mf, LiveIntervals &lis,
	const MachineLoopInfo &loops) :		const MachineLoopInfo &loops,
	MF(mf), LIS(lis), Loops(loops) {}		const MachineBlockFrequencyInfo &mbfi,
			NormalizingFn norm = normalizeSpillWeight)
			: MF(mf), LIS(lis), Loops(loops), MBFI(mbfi), normalize(norm) {}
	/// CalculateWeightAndHint - (re)compute li's spill weight and allocati		/// \brief (re)compute li's spill weight and allocation hint.
	on		void calculateSpillWeightAndHint(LiveInterval &li);
	/// hint.
	void CalculateWeightAndHint(LiveInterval &li);
	};		};
	/// CalculateSpillWeights - Compute spill weights for all virtual registe r		/// \brief Compute spill weights and allocation hints for all virtual reg ister
	/// live intervals.		/// live intervals.
	class CalculateSpillWeights : public MachineFunctionPass {		void calculateSpillWeightsAndHints(LiveIntervals &LIS, MachineFunction &M
	public:		F,
	static char ID;		const MachineLoopInfo &MLI,
			const MachineBlockFrequencyInfo &MBFI,
	CalculateSpillWeights() : MachineFunctionPass(ID) {		VirtRegAuxInfo::NormalizingFn norm =
	initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry())		normalizeSpillWeight);
	;
	}
	virtual void getAnalysisUsage(AnalysisUsage &au) const;
	virtual bool runOnMachineFunction(MachineFunction &fn);
	private:
	/// Returns true if the given live interval is zero length.
	bool isZeroLengthInterval(LiveInterval *li) const;
	};
	}		}
	#endif // LLVM_CODEGEN_CALCSPILLWEIGHTS_H		#endif // LLVM_CODEGEN_CALCSPILLWEIGHTS_H
End of changes. 10 change blocks.
	29 lines changed or deleted		27 lines changed or added

	CallGraph.h		CallGraph.h
	skipping to change at line 72		skipping to change at line 72
	namespace llvm {		namespace llvm {
	class Function;		class Function;
	class Module;		class Module;
	class CallGraphNode;		class CallGraphNode;
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// CallGraph class definition		// CallGraph class definition
	//		//
	class CallGraph {		class CallGraph : public ModulePass {
	protected:
	Module *Mod; // The module this call graph represents		Module *Mod; // The module this call graph represents
	typedef std::map<const Function *, CallGraphNode *> FunctionMapTy;		typedef std::map<const Function *, CallGraphNode *> FunctionMapTy;
	FunctionMapTy FunctionMap; // Map from a function to its node		FunctionMapTy FunctionMap; // Map from a function to its node
			// Root is root of the call graph, or the external node if a 'main' funct
			ion
			// couldn't be found.
			//
			CallGraphNode *Root;
			// ExternalCallingNode - This node has edges to all external functions an
			d
			// those internal functions that have their address taken.
			CallGraphNode *ExternalCallingNode;
			// CallsExternalNode - This node has edges to it from all functions makin
			g
			// indirect calls or calling an external function.
			CallGraphNode *CallsExternalNode;
			/// Replace the function represented by this node by another.
			/// This does not rescan the body of the function, so it is suitable when
			/// splicing the body of one function to another while also updating all
			/// callers from the old function to the new.
			///
			void spliceFunction(const Function *From, const Function *To);
			// Add a function to the call graph, and link the node to all of the func
			tions
			// that it calls.
			void addToCallGraph(Function *F);
	public:		public:
	static char ID; // Class identification, replacement for typeinfo		static char ID; // Class identification, replacement for typeinfo
	//===-------------------------------------------------------------------- -		//===-------------------------------------------------------------------- -
	// Accessors.		// Accessors.
	//		//
	typedef FunctionMapTy::iterator iterator;		typedef FunctionMapTy::iterator iterator;
	typedef FunctionMapTy::const_iterator const_iterator;		typedef FunctionMapTy::const_iterator const_iterator;
	/// getModule - Return the module the call graph corresponds to.		/// getModule - Return the module the call graph corresponds to.
	///		///
	skipping to change at line 110		skipping to change at line 133
	assert(I != FunctionMap.end() && "Function not in callgraph!");		assert(I != FunctionMap.end() && "Function not in callgraph!");
	return I->second;		return I->second;
	}		}
	inline CallGraphNode *operator[](const Function *F) {		inline CallGraphNode *operator[](const Function *F) {
	const_iterator I = FunctionMap.find(F);		const_iterator I = FunctionMap.find(F);
	assert(I != FunctionMap.end() && "Function not in callgraph!");		assert(I != FunctionMap.end() && "Function not in callgraph!");
	return I->second;		return I->second;
	}		}
	/// Returns the CallGraphNode which is used to represent undetermined cal ls		/// Returns the CallGraphNode which is used to represent undetermined cal ls
	/// into the callgraph. Override this if you want behavioral inheritance		/// into the callgraph.
	.		CallGraphNode *getExternalCallingNode() const { return ExternalCallingNod
	virtual CallGraphNode* getExternalCallingNode() const { return 0; }		e; }
	virtual CallGraphNode* getCallsExternalNode() const { return 0; }		CallGraphNode *getCallsExternalNode() const { return CallsExternalNode; }
	/// Return the root/main method in the module, or some other root node, s uch		/// Return the root/main method in the module, or some other root node, s uch
	/// as the externalcallingnode. Overload these if you behavioral		/// as the externalcallingnode.
	/// inheritance.		CallGraphNode *getRoot() { return Root; }
	virtual CallGraphNode* getRoot() { return 0; }		const CallGraphNode *getRoot() const { return Root; }
	virtual const CallGraphNode* getRoot() const { return 0; }
	//===-------------------------------------------------------------------- -		//===-------------------------------------------------------------------- -
	// Functions to keep a call graph up to date with a function that has bee n		// Functions to keep a call graph up to date with a function that has bee n
	// modified.		// modified.
	//		//
	/// removeFunctionFromModule - Unlink the function from this module, retu rning		/// removeFunctionFromModule - Unlink the function from this module, retu rning
	/// it. Because this removes the function from the module, the call grap h		/// it. Because this removes the function from the module, the call grap h
	/// node is destroyed. This is only valid if the function does not call any		/// node is destroyed. This is only valid if the function does not call any
	/// other functions (ie, there are no edges in it's CGN). The easiest wa y to		/// other functions (ie, there are no edges in it's CGN). The easiest wa y to
	/// do this is to dropAllReferences before calling this.		/// do this is to dropAllReferences before calling this.
	///		///
	Function *removeFunctionFromModule(CallGraphNode *CGN);		Function *removeFunctionFromModule(CallGraphNode *CGN);
	Function *removeFunctionFromModule(Function *F) {
	return removeFunctionFromModule((*this)[F]);
	}
	/// getOrInsertFunction - This method is identical to calling operator[], but		/// getOrInsertFunction - This method is identical to calling operator[], but
	/// it will insert a new CallGraphNode for the specified function if one does		/// it will insert a new CallGraphNode for the specified function if one does
	/// not already exist.		/// not already exist.
	CallGraphNode *getOrInsertFunction(const Function *F);		CallGraphNode *getOrInsertFunction(const Function *F);
	/// spliceFunction - Replace the function represented by this node by ano		CallGraph();
	ther.		virtual ~CallGraph() { releaseMemory(); }
	/// This does not rescan the body of the function, so it is suitable when		virtual void getAnalysisUsage(AnalysisUsage &AU) const;
	/// splicing the body of one function to another while also updating all		virtual bool runOnModule(Module &M);
	/// callers from the old function to the new.		virtual void releaseMemory();
	///
	void spliceFunction(const Function *From, const Function *To);
	//===--------------------------------------------------------------------
	-
	// Pass infrastructure interface glue code.
	//
	protected:
	CallGraph() {}
	public:
	virtual ~CallGraph() { destroy(); }
	/// initialize - Call this method before calling other methods,
	/// re/initializes the state of the CallGraph.
	///
	void initialize(Module &M);
	void print(raw_ostream &o, Module *) const;		void print(raw_ostream &o, const Module *) const;
	void dump() const;		void dump() const;
	protected:
	// destroy - Release memory for the call graph
	virtual void destroy();
	};		};
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// CallGraphNode class definition.		// CallGraphNode class definition.
	//		//
	class CallGraphNode {		class CallGraphNode {
	friend class CallGraph;		friend class CallGraph;
	AssertingVH<Function> F;		AssertingVH<Function> F;
End of changes. 8 change blocks.
	39 lines changed or deleted		42 lines changed or added

	CallSite.h		CallSite.h
	skipping to change at line 81		skipping to change at line 81
	/// Note that !isCall() does not mean it is an InvokeInst enclosed,		/// Note that !isCall() does not mean it is an InvokeInst enclosed,
	/// it also could signify a NULL Instruction pointer.		/// it also could signify a NULL Instruction pointer.
	bool isCall() const { return I.getInt(); }		bool isCall() const { return I.getInt(); }
	/// isInvoke - true if a InvokeInst is enclosed.		/// isInvoke - true if a InvokeInst is enclosed.
	///		///
	bool isInvoke() const { return getInstruction() && !I.getInt(); }		bool isInvoke() const { return getInstruction() && !I.getInt(); }
	InstrTy *getInstruction() const { return I.getPointer(); }		InstrTy *getInstruction() const { return I.getPointer(); }
	InstrTy *operator->() const { return I.getPointer(); }		InstrTy *operator->() const { return I.getPointer(); }
	operator bool() const { return I.getPointer(); }		LLVM_EXPLICIT operator bool() const { return I.getPointer(); }
	/// getCalledValue - Return the pointer to function that is being called.		/// getCalledValue - Return the pointer to function that is being called.
	///		///
	ValTy *getCalledValue() const {		ValTy *getCalledValue() const {
	assert(getInstruction() && "Not a call or invoke instruction!");		assert(getInstruction() && "Not a call or invoke instruction!");
	return *getCallee();		return *getCallee();
	}		}
	/// getCalledFunction - Return the function being called if this is a dir ect		/// getCalledFunction - Return the function being called if this is a dir ect
	/// call, otherwise return null (if it's an indirect call).		/// call, otherwise return null (if it's an indirect call).
	skipping to change at line 201		skipping to change at line 201
	/// \brief Return true if the call or the callee has the given attribute.		/// \brief Return true if the call or the callee has the given attribute.
	bool paramHasAttr(unsigned i, Attribute::AttrKind A) const {		bool paramHasAttr(unsigned i, Attribute::AttrKind A) const {
	CALLSITE_DELEGATE_GETTER(paramHasAttr(i, A));		CALLSITE_DELEGATE_GETTER(paramHasAttr(i, A));
	}		}
	/// @brief Extract the alignment for a call or parameter (0=unknown).		/// @brief Extract the alignment for a call or parameter (0=unknown).
	uint16_t getParamAlignment(uint16_t i) const {		uint16_t getParamAlignment(uint16_t i) const {
	CALLSITE_DELEGATE_GETTER(getParamAlignment(i));		CALLSITE_DELEGATE_GETTER(getParamAlignment(i));
	}		}
			/// \brief Return true if the call should not be treated as a call to a
			/// builtin.
			bool isNoBuiltin() const {
			CALLSITE_DELEGATE_GETTER(isNoBuiltin());
			}
	/// @brief Return true if the call should not be inlined.		/// @brief Return true if the call should not be inlined.
	bool isNoInline() const {		bool isNoInline() const {
	CALLSITE_DELEGATE_GETTER(isNoInline());		CALLSITE_DELEGATE_GETTER(isNoInline());
	}		}
	void setIsNoInline(bool Value = true) {		void setIsNoInline(bool Value = true) {
	CALLSITE_DELEGATE_SETTER(setIsNoInline(Value));		CALLSITE_DELEGATE_SETTER(setIsNoInline(Value));
	}		}
	/// @brief Determine if the call does not access memory.		/// @brief Determine if the call does not access memory.
	bool doesNotAccessMemory() const {		bool doesNotAccessMemory() const {
	skipping to change at line 254		skipping to change at line 260
	/// @brief Determine whether this argument is not captured.		/// @brief Determine whether this argument is not captured.
	bool doesNotCapture(unsigned ArgNo) const {		bool doesNotCapture(unsigned ArgNo) const {
	return paramHasAttr(ArgNo + 1, Attribute::NoCapture);		return paramHasAttr(ArgNo + 1, Attribute::NoCapture);
	}		}
	/// @brief Determine whether this argument is passed by value.		/// @brief Determine whether this argument is passed by value.
	bool isByValArgument(unsigned ArgNo) const {		bool isByValArgument(unsigned ArgNo) const {
	return paramHasAttr(ArgNo + 1, Attribute::ByVal);		return paramHasAttr(ArgNo + 1, Attribute::ByVal);
	}		}
			bool doesNotAccessMemory(unsigned ArgNo) const {
			return paramHasAttr(ArgNo + 1, Attribute::ReadNone);
			}
			bool onlyReadsMemory(unsigned ArgNo) const {
			return paramHasAttr(ArgNo + 1, Attribute::ReadOnly) ||
			paramHasAttr(ArgNo + 1, Attribute::ReadNone);
			}
	/// hasArgument - Returns true if this CallSite passes the given Value* a s an		/// hasArgument - Returns true if this CallSite passes the given Value* a s an
	/// argument to the called function.		/// argument to the called function.
	bool hasArgument(const Value *Arg) const {		bool hasArgument(const Value *Arg) const {
	for (arg_iterator AI = this->arg_begin(), E = this->arg_end(); AI != E;		for (arg_iterator AI = this->arg_begin(), E = this->arg_end(); AI != E;
	++AI)		++AI)
	if (AI->get() == Arg)		if (AI->get() == Arg)
	return true;		return true;
	return false;		return false;
	}		}
End of changes. 3 change blocks.
	1 lines changed or deleted		16 lines changed or added

	CallingConv.h		CallingConv.h
	skipping to change at line 54		skipping to change at line 54
	// call does not break any live ranges in the caller side.		// call does not break any live ranges in the caller side.
	Cold = 9,		Cold = 9,
	// GHC - Calling convention used by the Glasgow Haskell Compiler (GHC).		// GHC - Calling convention used by the Glasgow Haskell Compiler (GHC).
	GHC = 10,		GHC = 10,
	// HiPE - Calling convention used by the High-Performance Erlang Compil er		// HiPE - Calling convention used by the High-Performance Erlang Compil er
	// (HiPE).		// (HiPE).
	HiPE = 11,		HiPE = 11,
			// WebKit JS - Calling convention for stack based JavaScript calls
			WebKit_JS = 12,
			// AnyReg - Calling convention for dynamic register based calls (e.g.
			// stackmap and patchpoint intrinsics).
			AnyReg = 13,
	// Target - This is the start of the target-specific calling convention s,		// Target - This is the start of the target-specific calling convention s,
	// e.g. fastcall and thiscall on X86.		// e.g. fastcall and thiscall on X86.
	FirstTargetCC = 64,		FirstTargetCC = 64,
	/// X86_StdCall - stdcall is the calling conventions mostly used by the		/// X86_StdCall - stdcall is the calling conventions mostly used by the
	/// Win32 API. It is basically the same as the C convention with the		/// Win32 API. It is basically the same as the C convention with the
	/// difference in that the callee is responsible for popping the argume nts		/// difference in that the callee is responsible for popping the argume nts
	/// from the stack.		/// from the stack.
	X86_StdCall = 64,		X86_StdCall = 64,
	skipping to change at line 96		skipping to change at line 103
	X86_ThisCall = 70,		X86_ThisCall = 70,
	/// PTX_Kernel - Call to a PTX kernel.		/// PTX_Kernel - Call to a PTX kernel.
	/// Passes all arguments in parameter space.		/// Passes all arguments in parameter space.
	PTX_Kernel = 71,		PTX_Kernel = 71,
	/// PTX_Device - Call to a PTX device function.		/// PTX_Device - Call to a PTX device function.
	/// Passes all arguments in register or parameter space.		/// Passes all arguments in register or parameter space.
	PTX_Device = 72,		PTX_Device = 72,
	/// MBLAZE_INTR - Calling convention used for MBlaze interrupt routines
	.
	MBLAZE_INTR = 73,
	/// MBLAZE_INTR - Calling convention used for MBlaze interrupt support
	/// routines (i.e. GCC's save_volatiles attribute).
	MBLAZE_SVOL = 74,
	/// SPIR_FUNC - Calling convention for SPIR non-kernel device functions .		/// SPIR_FUNC - Calling convention for SPIR non-kernel device functions .
	/// No lowering or expansion of arguments.		/// No lowering or expansion of arguments.
	/// Structures are passed as a pointer to a struct with the byval attri bute.		/// Structures are passed as a pointer to a struct with the byval attri bute.
	/// Functions can only call SPIR_FUNC and SPIR_KERNEL functions.		/// Functions can only call SPIR_FUNC and SPIR_KERNEL functions.
	/// Functions can only have zero or one return values.		/// Functions can only have zero or one return values.
	/// Variable arguments are not allowed, except for printf.		/// Variable arguments are not allowed, except for printf.
	/// How arguments/return values are lowered are not specified.		/// How arguments/return values are lowered are not specified.
	/// Functions are only visible to the devices.		/// Functions are only visible to the devices.
	SPIR_FUNC = 75,		SPIR_FUNC = 75,
	/// SPIR_KERNEL - Calling convention for SPIR kernel functions.		/// SPIR_KERNEL - Calling convention for SPIR kernel functions.
	/// Inherits the restrictions of SPIR_FUNC, except		/// Inherits the restrictions of SPIR_FUNC, except
	/// Cannot have non-void return values.		/// Cannot have non-void return values.
	/// Cannot have variable arguments.		/// Cannot have variable arguments.
	/// Can also be called by the host.		/// Can also be called by the host.
	/// Is externally visible.		/// Is externally visible.
	SPIR_KERNEL = 76,		SPIR_KERNEL = 76,
	/// Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins		/// Intel_OCL_BI - Calling conventions for Intel OpenCL built-ins
	Intel_OCL_BI = 77		Intel_OCL_BI = 77,
			/// \brief The C convention as specified in the x86-64 supplement to th
			e
			/// System V ABI, used on most non-Windows systems.
			X86_64_SysV = 78,
			/// \brief The C convention as implemented on Windows/x86-64. This
			/// convention differs from the more common \c X86_64_SysV convention
			/// in a number of ways, most notably in that XMM registers used to pas
			s
			/// arguments are shadowed by GPRs, and vice versa.
			X86_64_Win64 = 79
	};		};
	} // End CallingConv namespace		} // End CallingConv namespace
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 4 change blocks.
	9 lines changed or deleted		19 lines changed or added

	CallingConvLower.h		CallingConvLower.h
	skipping to change at line 161		skipping to change at line 161
	/// CCState - This class holds information needed while lowering arguments and		/// CCState - This class holds information needed while lowering arguments and
	/// return values. It captures which registers are already assigned and wh ich		/// return values. It captures which registers are already assigned and wh ich
	/// stack slots are used. It provides accessors to allocate these values.		/// stack slots are used. It provides accessors to allocate these values.
	class CCState {		class CCState {
	private:		private:
	CallingConv::ID CallingConv;		CallingConv::ID CallingConv;
	bool IsVarArg;		bool IsVarArg;
	MachineFunction &MF;		MachineFunction &MF;
	const TargetMachine &TM;		const TargetMachine &TM;
	const TargetRegisterInfo &TRI;		const TargetRegisterInfo &TRI;
	SmallVector<CCValAssign, 16> &Locs;		SmallVectorImpl<CCValAssign> &Locs;
	LLVMContext &Context;		LLVMContext &Context;
	unsigned StackOffset;		unsigned StackOffset;
	SmallVector<uint32_t, 16> UsedRegs;		SmallVector<uint32_t, 16> UsedRegs;
	// ByValInfo and SmallVector<ByValInfo, 4> ByValRegs:		// ByValInfo and SmallVector<ByValInfo, 4> ByValRegs:
	//		//
	// Vector of ByValInfo instances (ByValRegs) is introduced for byval regi sters		// Vector of ByValInfo instances (ByValRegs) is introduced for byval regi sters
	// tracking.		// tracking.
	// Or, in another words it tracks byval parameters that are stored in		// Or, in another words it tracks byval parameters that are stored in
	skipping to change at line 222		skipping to change at line 222
	// InRegsParamsProceed - shows how many instances of ByValRegs was procee d		// InRegsParamsProceed - shows how many instances of ByValRegs was procee d
	// during argument analysis.		// during argument analysis.
	unsigned InRegsParamsProceed;		unsigned InRegsParamsProceed;
	protected:		protected:
	ParmContext CallOrPrologue;		ParmContext CallOrPrologue;
	public:		public:
	CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,		CCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
	const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs,		const TargetMachine &TM, SmallVectorImpl<CCValAssign> &locs,
	LLVMContext &C);		LLVMContext &C);
	void addLoc(const CCValAssign &V) {		void addLoc(const CCValAssign &V) {
	Locs.push_back(V);		Locs.push_back(V);
	}		}
	LLVMContext &getContext() const { return Context; }		LLVMContext &getContext() const { return Context; }
	const TargetMachine &getTarget() const { return TM; }		const TargetMachine &getTarget() const { return TM; }
	MachineFunction &getMachineFunction() const { return MF; }		MachineFunction &getMachineFunction() const { return MF; }
	CallingConv::ID getCallingConv() const { return CallingConv; }		CallingConv::ID getCallingConv() const { return CallingConv; }
End of changes. 2 change blocks.
	2 lines changed or deleted		2 lines changed or added

	Casting.h		Casting.h
	skipping to change at line 207		skipping to change at line 207
	template<class To, class FromTy> struct cast_convert_val<To,FromTy,FromTy> {		template<class To, class FromTy> struct cast_convert_val<To,FromTy,FromTy> {
	// This _is_ a simple type, just cast it.		// This _is_ a simple type, just cast it.
	static typename cast_retty<To, FromTy>::ret_type doit(const FromTy &Val) {		static typename cast_retty<To, FromTy>::ret_type doit(const FromTy &Val) {
	typename cast_retty<To, FromTy>::ret_type Res2		typename cast_retty<To, FromTy>::ret_type Res2
	= (typename cast_retty<To, FromTy>::ret_type)const_cast<FromTy&>(Val);		= (typename cast_retty<To, FromTy>::ret_type)const_cast<FromTy&>(Val);
	return Res2;		return Res2;
	}		}
	};		};
			template <class X> struct is_simple_type {
			static const bool value =
			is_same<X, typename simplify_type<X>::SimpleType>::value;
			};
	// cast<X> - Return the argument parameter cast to the specified type. Thi s		// cast<X> - Return the argument parameter cast to the specified type. Thi s
	// casting operator asserts that the type is correct, so it does not return null		// casting operator asserts that the type is correct, so it does not return null
	// on failure. It does not allow a null argument (use cast_or_null for tha t).		// on failure. It does not allow a null argument (use cast_or_null for tha t).
	// It is typically used like this:		// It is typically used like this:
	//		//
	// cast<Instruction>(myVal)->getParent()		// cast<Instruction>(myVal)->getParent()
	//		//
	template <class X, class Y>		template <class X, class Y>
	inline typename cast_retty<X, const Y>::ret_type cast(const Y &Val) {		inline typename enable_if_c<!is_simple_type<Y>::value,
			typename cast_retty<X, const Y>::ret_type>::typ
			e
			cast(const Y &Val) {
	assert(isa<X>(Val) && "cast<Ty>() argument of incompatible type!");		assert(isa<X>(Val) && "cast<Ty>() argument of incompatible type!");
	return cast_convert_val<X, const Y,		return cast_convert_val<
	typename simplify_type<const Y>::SimpleType>::doit(		X, const Y, typename simplify_type<const Y>::SimpleType>::doit(Val);
	Val);
	}		}
	template <class X, class Y>		template <class X, class Y>
	inline typename cast_retty<X, Y>::ret_type cast(Y &Val) {		inline typename cast_retty<X, Y>::ret_type cast(Y &Val) {
	assert(isa<X>(Val) && "cast<Ty>() argument of incompatible type!");		assert(isa<X>(Val) && "cast<Ty>() argument of incompatible type!");
	return cast_convert_val<X, Y,		return cast_convert_val<X, Y,
	typename simplify_type<Y>::SimpleType>::doit(Val) ;		typename simplify_type<Y>::SimpleType>::doit(Val) ;
	}		}
	template <class X, class Y>		template <class X, class Y>
	inline typename enable_if<		inline typename cast_retty<X, Y *>::ret_type cast(Y *Val) {
	is_same<Y, typename simplify_type<Y>::SimpleType>,
	typename cast_retty<X, Y*>::ret_type
	>::type cast(Y *Val) {
	assert(isa<X>(Val) && "cast<Ty>() argument of incompatible type!");		assert(isa<X>(Val) && "cast<Ty>() argument of incompatible type!");
	return cast_convert_val<X, Y*,		return cast_convert_val<X, Y*,
	typename simplify_type<Y*>::SimpleType>::doit(Val );		typename simplify_type<Y*>::SimpleType>::doit(Val );
	}		}
	// cast_or_null<X> - Functionally identical to cast, except that a null val ue is		// cast_or_null<X> - Functionally identical to cast, except that a null val ue is
	// accepted.		// accepted.
	//		//
	template <class X, class Y>		template <class X, class Y>
	inline typename cast_retty<X, Y*>::ret_type cast_or_null(Y *Val) {		inline typename cast_retty<X, Y*>::ret_type cast_or_null(Y *Val) {
	skipping to change at line 257		skipping to change at line 261
	// dyn_cast<X> - Return the argument parameter cast to the specified type. This		// dyn_cast<X> - Return the argument parameter cast to the specified type. This
	// casting operator returns null if the argument is of the wrong type, so i t can		// casting operator returns null if the argument is of the wrong type, so i t can
	// be used to test for a type as well as cast if successful. This should b e		// be used to test for a type as well as cast if successful. This should b e
	// used in the context of an if statement like this:		// used in the context of an if statement like this:
	//		//
	// if (const Instruction *I = dyn_cast<Instruction>(myVal)) { ... }		// if (const Instruction *I = dyn_cast<Instruction>(myVal)) { ... }
	//		//
	template <class X, class Y>		template <class X, class Y>
	inline typename cast_retty<X, const Y>::ret_type dyn_cast(const Y &Val) {		inline typename enable_if_c<!is_simple_type<Y>::value,
			typename cast_retty<X, const Y>::ret_type>::typ
			e
			dyn_cast(const Y &Val) {
	return isa<X>(Val) ? cast<X>(Val) : 0;		return isa<X>(Val) ? cast<X>(Val) : 0;
	}		}
	template <class X, class Y>		template <class X, class Y>
	inline typename cast_retty<X, Y>::ret_type dyn_cast(Y &Val) {		inline typename cast_retty<X, Y>::ret_type dyn_cast(Y &Val) {
	return isa<X>(Val) ? cast<X>(Val) : 0;		return isa<X>(Val) ? cast<X>(Val) : 0;
	}		}
	template <class X, class Y>		template <class X, class Y>
	inline typename enable_if<		inline typename cast_retty<X, Y *>::ret_type dyn_cast(Y *Val) {
	is_same<Y, typename simplify_type<Y>::SimpleType>,
	typename cast_retty<X, Y*>::ret_type
	>::type dyn_cast(Y *Val) {
	return isa<X>(Val) ? cast<X>(Val) : 0;		return isa<X>(Val) ? cast<X>(Val) : 0;
	}		}
	// dyn_cast_or_null<X> - Functionally identical to dyn_cast, except that a null		// dyn_cast_or_null<X> - Functionally identical to dyn_cast, except that a null
	// value is accepted.		// value is accepted.
	//		//
	template <class X, class Y>		template <class X, class Y>
	inline typename cast_retty<X, Y*>::ret_type dyn_cast_or_null(Y *Val) {		inline typename cast_retty<X, Y*>::ret_type dyn_cast_or_null(Y *Val) {
	return (Val && isa<X>(Val)) ? cast<X>(Val) : 0;		return (Val && isa<X>(Val)) ? cast<X>(Val) : 0;
	}		}
End of changes. 6 change blocks.
	13 lines changed or deleted		17 lines changed or added

	Cloning.h		Cloning.h
	skipping to change at line 133		skipping to change at line 133
	///		///
	/// If ModuleLevelChanges is false, VMap contains no non-identity GlobalVal ue		/// If ModuleLevelChanges is false, VMap contains no non-identity GlobalVal ue
	/// mappings.		/// mappings.
	///		///
	void CloneFunctionInto(Function *NewFunc, const Function *OldFunc,		void CloneFunctionInto(Function *NewFunc, const Function *OldFunc,
	ValueToValueMapTy &VMap,		ValueToValueMapTy &VMap,
	bool ModuleLevelChanges,		bool ModuleLevelChanges,
	SmallVectorImpl<ReturnInst*> &Returns,		SmallVectorImpl<ReturnInst*> &Returns,
	const char *NameSuffix = "",		const char *NameSuffix = "",
	ClonedCodeInfo *CodeInfo = 0,		ClonedCodeInfo *CodeInfo = 0,
	ValueMapTypeRemapper *TypeMapper = 0);		ValueMapTypeRemapper *TypeMapper = 0,
			ValueMaterializer *Materializer = 0);
	/// CloneAndPruneFunctionInto - This works exactly like CloneFunctionInto,		/// CloneAndPruneFunctionInto - This works exactly like CloneFunctionInto,
	/// except that it does some simple constant prop and DCE on the fly. The		/// except that it does some simple constant prop and DCE on the fly. The
	/// effect of this is to copy significantly less code in cases where (for		/// effect of this is to copy significantly less code in cases where (for
	/// example) a function call with constant arguments is inlined, and those		/// example) a function call with constant arguments is inlined, and those
	/// constant arguments cause a significant amount of code in the callee to be		/// constant arguments cause a significant amount of code in the callee to be
	/// dead. Since this doesn't produce an exactly copy of the input, it can' t be		/// dead. Since this doesn't produce an exactly copy of the input, it can' t be
	/// used for things like CloneFunction or CloneModule.		/// used for things like CloneFunction or CloneModule.
	///		///
	/// If ModuleLevelChanges is false, VMap contains no non-identity GlobalVal ue		/// If ModuleLevelChanges is false, VMap contains no non-identity GlobalVal ue
End of changes. 1 change blocks.
	1 lines changed or deleted		2 lines changed or added

	CommandFlags.h		CommandFlags.h
	skipping to change at line 113		skipping to change at line 113
	EnableFPMAD("enable-fp-mad",		EnableFPMAD("enable-fp-mad",
	cl::desc("Enable less precise MAD instructions to be generated" ),		cl::desc("Enable less precise MAD instructions to be generated" ),
	cl::init(false));		cl::init(false));
	cl::opt<bool>		cl::opt<bool>
	DisableFPElim("disable-fp-elim",		DisableFPElim("disable-fp-elim",
	cl::desc("Disable frame pointer elimination optimization"),		cl::desc("Disable frame pointer elimination optimization"),
	cl::init(false));		cl::init(false));
	cl::opt<bool>		cl::opt<bool>
	DisableFPElimNonLeaf("disable-non-leaf-fp-elim",
	cl::desc("Disable frame pointer elimination optimization for non-leaf fun
	cs"),
	cl::init(false));
	cl::opt<bool>
	EnableUnsafeFPMath("enable-unsafe-fp-math",		EnableUnsafeFPMath("enable-unsafe-fp-math",
	cl::desc("Enable optimizations that may decrease FP precisi on"),		cl::desc("Enable optimizations that may decrease FP precisi on"),
	cl::init(false));		cl::init(false));
	cl::opt<bool>		cl::opt<bool>
	EnableNoInfsFPMath("enable-no-infs-fp-math",		EnableNoInfsFPMath("enable-no-infs-fp-math",
	cl::desc("Enable FP math optimizations that assume no +-Inf s"),		cl::desc("Enable FP math optimizations that assume no +-Inf s"),
	cl::init(false));		cl::init(false));
	cl::opt<bool>		cl::opt<bool>
	skipping to change at line 158		skipping to change at line 153
	clEnumValN(FloatABI::Default, "default",		clEnumValN(FloatABI::Default, "default",
	"Target default float ABI type"),		"Target default float ABI type"),
	clEnumValN(FloatABI::Soft, "soft",		clEnumValN(FloatABI::Soft, "soft",
	"Soft float ABI (implied by -soft-float)"),		"Soft float ABI (implied by -soft-float)"),
	clEnumValN(FloatABI::Hard, "hard",		clEnumValN(FloatABI::Hard, "hard",
	"Hard float ABI (uses FP registers)"),		"Hard float ABI (uses FP registers)"),
	clEnumValEnd));		clEnumValEnd));
	cl::opt<llvm::FPOpFusion::FPOpFusionMode>		cl::opt<llvm::FPOpFusion::FPOpFusionMode>
	FuseFPOps("fp-contract",		FuseFPOps("fp-contract",
	cl::desc("Enable aggresive formation of fused FP ops"),		cl::desc("Enable aggressive formation of fused FP ops"),
	cl::init(FPOpFusion::Standard),		cl::init(FPOpFusion::Standard),
	cl::values(		cl::values(
	clEnumValN(FPOpFusion::Fast, "fast",		clEnumValN(FPOpFusion::Fast, "fast",
	"Fuse FP ops whenever profitable"),		"Fuse FP ops whenever profitable"),
	clEnumValN(FPOpFusion::Standard, "on",		clEnumValN(FPOpFusion::Standard, "on",
	"Only fuse 'blessed' FP ops."),		"Only fuse 'blessed' FP ops."),
	clEnumValN(FPOpFusion::Strict, "off",		clEnumValN(FPOpFusion::Strict, "off",
	"Only fuse FP ops when the result won't be effecte d."),		"Only fuse FP ops when the result won't be effecte d."),
	clEnumValEnd));		clEnumValEnd));
	skipping to change at line 189		skipping to change at line 184
	cl::opt<bool>		cl::opt<bool>
	DisableTailCalls("disable-tail-calls",		DisableTailCalls("disable-tail-calls",
	cl::desc("Never emit tail calls"),		cl::desc("Never emit tail calls"),
	cl::init(false));		cl::init(false));
	cl::opt<unsigned>		cl::opt<unsigned>
	OverrideStackAlignment("stack-alignment",		OverrideStackAlignment("stack-alignment",
	cl::desc("Override default stack alignment"),		cl::desc("Override default stack alignment"),
	cl::init(0));		cl::init(0));
	cl::opt<bool>
	EnableRealignStack("realign-stack",
	cl::desc("Realign stack if needed"),
	cl::init(true));
	cl::opt<std::string>		cl::opt<std::string>
	TrapFuncName("trap-func", cl::Hidden,		TrapFuncName("trap-func", cl::Hidden,
	cl::desc("Emit a call to trap function rather than a trap instructi on"),		cl::desc("Emit a call to trap function rather than a trap instructi on"),
	cl::init(""));		cl::init(""));
	cl::opt<bool>		cl::opt<bool>
	EnablePIE("enable-pie",		EnablePIE("enable-pie",
	cl::desc("Assume the creation of a position independent executabl e."),		cl::desc("Assume the creation of a position independent executabl e."),
	cl::init(false));		cl::init(false));
	skipping to change at line 223		skipping to change at line 213
	cl::opt<std::string> StopAfter("stop-after",		cl::opt<std::string> StopAfter("stop-after",
	cl::desc("Stop compilation after a specific pas s"),		cl::desc("Stop compilation after a specific pas s"),
	cl::value_desc("pass-name"),		cl::value_desc("pass-name"),
	cl::init(""));		cl::init(""));
	cl::opt<std::string> StartAfter("start-after",		cl::opt<std::string> StartAfter("start-after",
	cl::desc("Resume compilation after a specific pas s"),		cl::desc("Resume compilation after a specific pas s"),
	cl::value_desc("pass-name"),		cl::value_desc("pass-name"),
	cl::init(""));		cl::init(""));
	cl::opt<unsigned>
	SSPBufferSize("stack-protector-buffer-size", cl::init(8),
	cl::desc("Lower bound for a buffer to be considered for "
	"stack protection"));
	#endif		#endif
End of changes. 4 change blocks.
	16 lines changed or deleted		1 lines changed or added

	CommandLine.h		CommandLine.h
	skipping to change at line 349		skipping to change at line 349
	void apply(Opt &O) const { O.setCategory(Category); }		void apply(Opt &O) const { O.setCategory(Category); }
	};		};
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// OptionValue class		// OptionValue class
	// Support value comparison outside the template.		// Support value comparison outside the template.
	struct GenericOptionValue {		struct GenericOptionValue {
	virtual ~GenericOptionValue() {}		virtual ~GenericOptionValue() {}
	virtual bool compare(const GenericOptionValue &V) const = 0;		virtual bool compare(const GenericOptionValue &V) const = 0;
	private:		private:
	virtual void anchor();		virtual void anchor();
	};		};
	template<class DataType> struct OptionValue;		template<class DataType> struct OptionValue;
	// The default value safely does nothing. Option value printing is only		// The default value safely does nothing. Option value printing is only
	// best-effort.		// best-effort.
	template<class DataType, bool isClass>		template<class DataType, bool isClass>
	struct OptionValueBase : public GenericOptionValue {		struct OptionValueBase : public GenericOptionValue {
	skipping to change at line 1701		skipping to change at line 1702
	explicit extrahelp(const char* help);		explicit extrahelp(const char* help);
	};		};
	void PrintVersionMessage();		void PrintVersionMessage();
	/// This function just prints the help message, exactly the same way as if the		/// This function just prints the help message, exactly the same way as if the
	/// -help or -help-hidden option had been given on the command line.		/// -help or -help-hidden option had been given on the command line.
	///		///
	/// NOTE: THIS FUNCTION TERMINATES THE PROGRAM!		/// NOTE: THIS FUNCTION TERMINATES THE PROGRAM!
	///		///
	/// \param hidden if true will print hidden options		/// \param Hidden if true will print hidden options
	/// \param categorized if true print options in categories		/// \param Categorized if true print options in categories
	void PrintHelpMessage(bool Hidden=false, bool Categorized=false);		void PrintHelpMessage(bool Hidden=false, bool Categorized=false);
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// Public interface for accessing registered options.		// Public interface for accessing registered options.
	//		//
	/// \brief Use this to get a StringMap to all registered named options		/// \brief Use this to get a StringMap to all registered named options
	/// (e.g. -help). Note \p Map Should be an empty StringMap.		/// (e.g. -help). Note \p Map Should be an empty StringMap.
	///		///
	/// \param [out] map will be filled with mappings where the key is the		/// \param [out] Map will be filled with mappings where the key is the
	/// Option argument string (e.g. "help") and value is the corresponding		/// Option argument string (e.g. "help") and value is the corresponding
	/// Option*.		/// Option*.
	///		///
	/// Access to unnamed arguments (i.e. positional) are not provided because		/// Access to unnamed arguments (i.e. positional) are not provided because
	/// it is expected that the client already has access to these.		/// it is expected that the client already has access to these.
	///		///
	/// Typical usage:		/// Typical usage:
	/// \code		/// \code
	/// main(int argc,char* argv[]) {		/// main(int argc,char* argv[]) {
	/// StringMap<llvm::cl::Option*> opts;		/// StringMap<llvm::cl::Option*> opts;
	skipping to change at line 1737		skipping to change at line 1738
	/// llvm::cl::ParseCommandLineOptions(argc,argv);		/// llvm::cl::ParseCommandLineOptions(argc,argv);
	/// //More code		/// //More code
	/// }		/// }
	/// \endcode		/// \endcode
	///		///
	/// This interface is useful for modifying options in libraries that are ou t of		/// This interface is useful for modifying options in libraries that are ou t of
	/// the control of the client. The options should be modified before callin g		/// the control of the client. The options should be modified before callin g
	/// llvm::cl::ParseCommandLineOptions().		/// llvm::cl::ParseCommandLineOptions().
	void getRegisteredOptions(StringMap<Option*> &Map);		void getRegisteredOptions(StringMap<Option*> &Map);
			//===----------------------------------------------------------------------
			===//
			// Standalone command line processing utilities.
			//
			/// \brief Saves strings in the inheritor's stable storage and returns a st
			able
			/// raw character pointer.
			class StringSaver {
			virtual void anchor();
			public:
			virtual const char *SaveString(const char *Str) = 0;
			virtual ~StringSaver() {}; // Pacify -Wnon-virtual-dtor.
			};
			/// \brief Tokenizes a command line that can contain escapes and quotes.
			//
			/// The quoting rules match those used by GCC and other tools that use
			/// libiberty's buildargv() or expandargv() utilities, and do not match bas
			h.
			/// They differ from buildargv() on treatment of backslashes that do not es
			cape
			/// a special character to make it possible to accept most Windows file pat
			hs.
			///
			/// \param [in] Source The string to be split on whitespace with quotes.
			/// \param [in] Saver Delegates back to the caller for saving parsed string
			s.
			/// \param [out] NewArgv All parsed strings are appended to NewArgv.
			void TokenizeGNUCommandLine(StringRef Source, StringSaver &Saver,
			SmallVectorImpl<const char *> &NewArgv);
			/// \brief Tokenizes a Windows command line which may contain quotes and es
			caped
			/// quotes.
			///
			/// See MSDN docs for CommandLineToArgvW for information on the quoting rul
			es.
			/// http://msdn.microsoft.com/en-us/library/windows/desktop/17w5ykft(v=vs.8
			5).aspx
			///
			/// \param [in] Source The string to be split on whitespace with quotes.
			/// \param [in] Saver Delegates back to the caller for saving parsed string
			s.
			/// \param [out] NewArgv All parsed strings are appended to NewArgv.
			void TokenizeWindowsCommandLine(StringRef Source, StringSaver &Saver,
			SmallVectorImpl<const char *> &NewArgv);
			/// \brief String tokenization function type. Should be compatible with ei
			ther
			/// Windows or Unix command line tokenizers.
			typedef void (*TokenizerCallback)(StringRef Source, StringSaver &Saver,
			SmallVectorImpl<const char *> &NewArgv);
			/// \brief Expand response files on a command line recursively using the gi
			ven
			/// StringSaver and tokenization strategy. Argv should contain the command
			line
			/// before expansion and will be modified in place.
			///
			/// \param [in] Saver Delegates back to the caller for saving parsed string
			s.
			/// \param [in] Tokenizer Tokenization strategy. Typically Unix or Windows.
			/// \param [in,out] Argv Command line into which to expand response files.
			/// \return true if all @files were expanded successfully or there were non
			e.
			bool ExpandResponseFiles(StringSaver &Saver, TokenizerCallback Tokenizer,
			SmallVectorImpl<const char *> &Argv);
	} // End namespace cl		} // End namespace cl
	} // End namespace llvm		} // End namespace llvm
	#endif		#endif
End of changes. 4 change blocks.
	3 lines changed or deleted		73 lines changed or added

	Compiler.h		Compiler.h
	skipping to change at line 24		skipping to change at line 24
	#ifndef LLVM_SUPPORT_COMPILER_H		#ifndef LLVM_SUPPORT_COMPILER_H
	#define LLVM_SUPPORT_COMPILER_H		#define LLVM_SUPPORT_COMPILER_H
	#include "llvm/Config/llvm-config.h"		#include "llvm/Config/llvm-config.h"
	#ifndef __has_feature		#ifndef __has_feature
	# define __has_feature(x) 0		# define __has_feature(x) 0
	#endif		#endif
			#ifndef __has_attribute
			# define __has_attribute(x) 0
			#endif
			#ifndef __has_builtin
			# define __has_builtin(x) 0
			#endif
			/// \macro __GNUC_PREREQ
			/// \brief Defines __GNUC_PREREQ if glibc's features.h isn't available.
			#ifndef __GNUC_PREREQ
			# if defined(__GNUC__) && defined(__GNUC_MINOR__)
			# define __GNUC_PREREQ(maj, min) \
			((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min))
			# else
			# define __GNUC_PREREQ(maj, min) 0
			# endif
			#endif
	/// \brief Does the compiler support r-value references?		/// \brief Does the compiler support r-value references?
	/// This implies that <utility> provides the one-argument std::move; it		/// This implies that <utility> provides the one-argument std::move; it
	/// does not imply the existence of any other C++ library features.		/// does not imply the existence of any other C++ library features.
	#if (__has_feature(cxx_rvalue_references) \		#if (__has_feature(cxx_rvalue_references) \
	|| defined(__GXX_EXPERIMENTAL_CXX0X__) \		|| defined(__GXX_EXPERIMENTAL_CXX0X__) \
	|| (defined(_MSC_VER) && _MSC_VER >= 1600))		|| (defined(_MSC_VER) && _MSC_VER >= 1600))
	#define LLVM_HAS_RVALUE_REFERENCES 1		#define LLVM_HAS_RVALUE_REFERENCES 1
	#else		#else
	#define LLVM_HAS_RVALUE_REFERENCES 0		#define LLVM_HAS_RVALUE_REFERENCES 0
	#endif		#endif
	skipping to change at line 149		skipping to change at line 168
	#if __has_feature(cxx_constexpr) || defined(__GXX_EXPERIMENTAL_CXX0X__)		#if __has_feature(cxx_constexpr) || defined(__GXX_EXPERIMENTAL_CXX0X__)
	# define LLVM_CONSTEXPR constexpr		# define LLVM_CONSTEXPR constexpr
	#else		#else
	# define LLVM_CONSTEXPR		# define LLVM_CONSTEXPR
	#endif		#endif
	/// LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is link ed		/// LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is link ed
	/// into a shared library, then the class should be private to the library and		/// into a shared library, then the class should be private to the library and
	/// not accessible from outside it. Can also be used to mark variables and		/// not accessible from outside it. Can also be used to mark variables and
	/// functions, making them private to any shared library they are linked in to.		/// functions, making them private to any shared library they are linked in to.
	#if (__GNUC__ >= 4) && !defined(__MINGW32__) && !defined(__CYGWIN__)		/// On PE/COFF targets, library visibility is the default, so this isn't ne
			eded.
			#if (__has_attribute(visibility) || __GNUC_PREREQ(4, 0)) &&
			\
			!defined(__MINGW32__) && !defined(__CYGWIN__) && !defined(LLVM_ON_WIN32
			)
	#define LLVM_LIBRARY_VISIBILITY __attribute__ ((visibility("hidden")))		#define LLVM_LIBRARY_VISIBILITY __attribute__ ((visibility("hidden")))
	#else		#else
	#define LLVM_LIBRARY_VISIBILITY		#define LLVM_LIBRARY_VISIBILITY
	#endif		#endif
	#if (__GNUC__ >= 4 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 1))		#if __has_attribute(used) || __GNUC_PREREQ(3, 1)
	#define LLVM_ATTRIBUTE_USED __attribute__((__used__))		#define LLVM_ATTRIBUTE_USED __attribute__((__used__))
	#else		#else
	#define LLVM_ATTRIBUTE_USED		#define LLVM_ATTRIBUTE_USED
	#endif		#endif
			#if __has_attribute(warn_unused_result) || __GNUC_PREREQ(3, 4)
			#define LLVM_ATTRIBUTE_UNUSED_RESULT __attribute__((__warn_unused_result__)
			)
			#else
			#define LLVM_ATTRIBUTE_UNUSED_RESULT
			#endif
	// Some compilers warn about unused functions. When a function is sometimes		// Some compilers warn about unused functions. When a function is sometimes
	// used or not depending on build settings (e.g. a function only called fro m		// used or not depending on build settings (e.g. a function only called fro m
	// within "assert"), this attribute can be used to suppress such warnings.		// within "assert"), this attribute can be used to suppress such warnings.
	//		//
	// However, it shouldn't be used for unused *variables*, as those have a mu ch		// However, it shouldn't be used for unused *variables*, as those have a mu ch
	// more portable solution:		// more portable solution:
	// (void)unused_var_name;		// (void)unused_var_name;
	// Prefer cast-to-void wherever it is sufficient.		// Prefer cast-to-void wherever it is sufficient.
	#if (__GNUC__ >= 4 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 1))		#if __has_attribute(unused) || __GNUC_PREREQ(3, 1)
	#define LLVM_ATTRIBUTE_UNUSED __attribute__((__unused__))		#define LLVM_ATTRIBUTE_UNUSED __attribute__((__unused__))
	#else		#else
	#define LLVM_ATTRIBUTE_UNUSED		#define LLVM_ATTRIBUTE_UNUSED
	#endif		#endif
	#if (__GNUC__ >= 4) && !defined(__MINGW32__) && !defined(__CYGWIN__)		// FIXME: Provide this for PE/COFF targets.
			#if (__has_attribute(weak) || __GNUC_PREREQ(4, 0)) &&
			\
			(!defined(__MINGW32__) && !defined(__CYGWIN__) && !defined(LLVM_ON_WIN3
			2))
	#define LLVM_ATTRIBUTE_WEAK __attribute__((__weak__))		#define LLVM_ATTRIBUTE_WEAK __attribute__((__weak__))
	#else		#else
	#define LLVM_ATTRIBUTE_WEAK		#define LLVM_ATTRIBUTE_WEAK
	#endif		#endif
	#ifdef __GNUC__ // aka 'CONST' but following LLVM Conventions.		// Prior to clang 3.2, clang did not accept any spelling of
			// __has_attribute(const), so assume it is supported.
			#if defined(__clang__) || defined(__GNUC__)
			// aka 'CONST' but following LLVM Conventions.
	#define LLVM_READNONE __attribute__((__const__))		#define LLVM_READNONE __attribute__((__const__))
	#else		#else
	#define LLVM_READNONE		#define LLVM_READNONE
	#endif		#endif
	#ifdef __GNUC__ // aka 'PURE' but following LLVM Conventions.		#if __has_attribute(pure) || defined(__GNUC__)
			// aka 'PURE' but following LLVM Conventions.
	#define LLVM_READONLY __attribute__((__pure__))		#define LLVM_READONLY __attribute__((__pure__))
	#else		#else
	#define LLVM_READONLY		#define LLVM_READONLY
	#endif		#endif
	#if (__GNUC__ >= 4)		#if __has_builtin(__builtin_expect) || __GNUC_PREREQ(4, 0)
	#define LLVM_LIKELY(EXPR) __builtin_expect((bool)(EXPR), true)		#define LLVM_LIKELY(EXPR) __builtin_expect((bool)(EXPR), true)
	#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false)		#define LLVM_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false)
	#else		#else
	#define LLVM_LIKELY(EXPR) (EXPR)		#define LLVM_LIKELY(EXPR) (EXPR)
	#define LLVM_UNLIKELY(EXPR) (EXPR)		#define LLVM_UNLIKELY(EXPR) (EXPR)
	#endif		#endif
	// C++ doesn't support 'extern template' of template specializations. GCC does,		// C++ doesn't support 'extern template' of template specializations. GCC does,
	// but requires __extension__ before it. In the header, use this:		// but requires __extension__ before it. In the header, use this:
	// EXTERN_TEMPLATE_INSTANTIATION(class foo<bar>);		// EXTERN_TEMPLATE_INSTANTIATION(class foo<bar>);
	skipping to change at line 216		skipping to change at line 249
	#ifdef __GNUC__		#ifdef __GNUC__
	#define EXTERN_TEMPLATE_INSTANTIATION(X) __extension__ extern template X		#define EXTERN_TEMPLATE_INSTANTIATION(X) __extension__ extern template X
	#define TEMPLATE_INSTANTIATION(X) template X		#define TEMPLATE_INSTANTIATION(X) template X
	#else		#else
	#define EXTERN_TEMPLATE_INSTANTIATION(X)		#define EXTERN_TEMPLATE_INSTANTIATION(X)
	#define TEMPLATE_INSTANTIATION(X)		#define TEMPLATE_INSTANTIATION(X)
	#endif		#endif
	/// LLVM_ATTRIBUTE_NOINLINE - On compilers where we have a directive to do so,		/// LLVM_ATTRIBUTE_NOINLINE - On compilers where we have a directive to do so,
	/// mark a method "not for inlining".		/// mark a method "not for inlining".
	#if (__GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4))		#if __has_attribute(noinline) || __GNUC_PREREQ(3, 4)
	#define LLVM_ATTRIBUTE_NOINLINE __attribute__((noinline))		#define LLVM_ATTRIBUTE_NOINLINE __attribute__((noinline))
	#elif defined(_MSC_VER)		#elif defined(_MSC_VER)
	#define LLVM_ATTRIBUTE_NOINLINE __declspec(noinline)		#define LLVM_ATTRIBUTE_NOINLINE __declspec(noinline)
	#else		#else
	#define LLVM_ATTRIBUTE_NOINLINE		#define LLVM_ATTRIBUTE_NOINLINE
	#endif		#endif
	/// LLVM_ATTRIBUTE_ALWAYS_INLINE - On compilers where we have a directive t o do		/// LLVM_ATTRIBUTE_ALWAYS_INLINE - On compilers where we have a directive t o do
	/// so, mark a method "always inline" because it is performance sensitive. GCC		/// so, mark a method "always inline" because it is performance sensitive. GCC
	/// 3.4 supported this but is buggy in various cases and produces unimpleme nted		/// 3.4 supported this but is buggy in various cases and produces unimpleme nted
	/// errors, just use it in GCC 4.0 and later.		/// errors, just use it in GCC 4.0 and later.
	#if __GNUC__ > 3		#if __has_attribute(always_inline) || __GNUC_PREREQ(4, 0)
	#define LLVM_ATTRIBUTE_ALWAYS_INLINE inline __attribute__((always_inline))		#define LLVM_ATTRIBUTE_ALWAYS_INLINE inline __attribute__((always_inline))
	#elif defined(_MSC_VER)		#elif defined(_MSC_VER)
	#define LLVM_ATTRIBUTE_ALWAYS_INLINE __forceinline		#define LLVM_ATTRIBUTE_ALWAYS_INLINE __forceinline
	#else		#else
	#define LLVM_ATTRIBUTE_ALWAYS_INLINE		#define LLVM_ATTRIBUTE_ALWAYS_INLINE
	#endif		#endif
	#ifdef __GNUC__		#ifdef __GNUC__
	#define LLVM_ATTRIBUTE_NORETURN __attribute__((noreturn))		#define LLVM_ATTRIBUTE_NORETURN __attribute__((noreturn))
	#elif defined(_MSC_VER)		#elif defined(_MSC_VER)
	skipping to change at line 270		skipping to change at line 303
	# define LLVM_ATTRIBUTE_DEPRECATED(decl, message) \		# define LLVM_ATTRIBUTE_DEPRECATED(decl, message) \
	__declspec(deprecated(message)) decl		__declspec(deprecated(message)) decl
	#else		#else
	# define LLVM_ATTRIBUTE_DEPRECATED(decl, message) \		# define LLVM_ATTRIBUTE_DEPRECATED(decl, message) \
	decl		decl
	#endif		#endif
	/// LLVM_BUILTIN_UNREACHABLE - On compilers which support it, expands		/// LLVM_BUILTIN_UNREACHABLE - On compilers which support it, expands
	/// to an expression which states that it is undefined behavior for the		/// to an expression which states that it is undefined behavior for the
	/// compiler to reach this point. Otherwise is not defined.		/// compiler to reach this point. Otherwise is not defined.
	#if defined(__clang__) || (__GNUC__ > 4) \		#if __has_builtin(__builtin_unreachable) || __GNUC_PREREQ(4, 5)
	|| (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
	# define LLVM_BUILTIN_UNREACHABLE __builtin_unreachable()		# define LLVM_BUILTIN_UNREACHABLE __builtin_unreachable()
	#elif defined(_MSC_VER)		#elif defined(_MSC_VER)
	# define LLVM_BUILTIN_UNREACHABLE __assume(false)		# define LLVM_BUILTIN_UNREACHABLE __assume(false)
	#endif		#endif
	/// LLVM_BUILTIN_TRAP - On compilers which support it, expands to an expres sion		/// LLVM_BUILTIN_TRAP - On compilers which support it, expands to an expres sion
	/// which causes the program to exit abnormally.		/// which causes the program to exit abnormally.
	#if defined(__clang__) || (__GNUC__ > 4) \		#if __has_builtin(__builtin_trap) || __GNUC_PREREQ(4, 3)
	|| (__GNUC__ == 4 && __GNUC_MINOR__ >= 3)
	# define LLVM_BUILTIN_TRAP __builtin_trap()		# define LLVM_BUILTIN_TRAP __builtin_trap()
	#else		#else
	# define LLVM_BUILTIN_TRAP *(volatile int*)0x11 = 0		# define LLVM_BUILTIN_TRAP *(volatile int*)0x11 = 0
	#endif		#endif
	/// \macro LLVM_ASSUME_ALIGNED		/// \macro LLVM_ASSUME_ALIGNED
	/// \brief Returns a pointer with an assumed alignment.		/// \brief Returns a pointer with an assumed alignment.
	#if !defined(__clang__) && ((__GNUC__ > 4) \		#if __has_builtin(__builtin_assume_aligned) && __GNUC_PREREQ(4, 7)
	|| (__GNUC__ == 4 && __GNUC_MINOR__ >= 7))
	// FIXME: Enable on clang when it supports it.
	# define LLVM_ASSUME_ALIGNED(p, a) __builtin_assume_aligned(p, a)		# define LLVM_ASSUME_ALIGNED(p, a) __builtin_assume_aligned(p, a)
	#elif defined(LLVM_BUILTIN_UNREACHABLE)		#elif defined(LLVM_BUILTIN_UNREACHABLE)
			// As of today, clang does not support __builtin_assume_aligned.
	# define LLVM_ASSUME_ALIGNED(p, a) \		# define LLVM_ASSUME_ALIGNED(p, a) \
	(((uintptr_t(p) % (a)) == 0) ? (p) : (LLVM_BUILTIN_UNREACHABLE, (p)))		(((uintptr_t(p) % (a)) == 0) ? (p) : (LLVM_BUILTIN_UNREACHABLE, (p)))
	#else		#else
	# define LLVM_ASSUME_ALIGNED(p, a) (p)		# define LLVM_ASSUME_ALIGNED(p, a) (p)
	#endif		#endif
	/// \macro LLVM_FUNCTION_NAME		/// \macro LLVM_FUNCTION_NAME
	/// \brief Expands to __func__ on compilers which support it. Otherwise,		/// \brief Expands to __func__ on compilers which support it. Otherwise,
	/// expands to a compiler-dependent replacement.		/// expands to a compiler-dependent replacement.
	#if defined(_MSC_VER)		#if defined(_MSC_VER)
	skipping to change at line 364		skipping to change at line 394
	/// \macro LLVM_STATIC_ASSERT		/// \macro LLVM_STATIC_ASSERT
	/// \brief Expands to C/C++'s static_assert on compilers which support it.		/// \brief Expands to C/C++'s static_assert on compilers which support it.
	#if __has_feature(cxx_static_assert)		#if __has_feature(cxx_static_assert)
	# define LLVM_STATIC_ASSERT(expr, msg) static_assert(expr, msg)		# define LLVM_STATIC_ASSERT(expr, msg) static_assert(expr, msg)
	#elif __has_feature(c_static_assert)		#elif __has_feature(c_static_assert)
	# define LLVM_STATIC_ASSERT(expr, msg) _Static_assert(expr, msg)		# define LLVM_STATIC_ASSERT(expr, msg) _Static_assert(expr, msg)
	#else		#else
	# define LLVM_STATIC_ASSERT(expr, msg)		# define LLVM_STATIC_ASSERT(expr, msg)
	#endif		#endif
			/// \macro LLVM_ENUM_INT_TYPE
			/// \brief Expands to colon followed by the given integral type on compiler
			s
			/// which support C++11 strong enums. This can be used to make enums unsig
			ned
			/// with MSVC.
			#if __has_feature(cxx_strong_enums)
			# define LLVM_ENUM_INT_TYPE(intty) : intty
			#elif defined(_MSC_VER) && _MSC_VER >= 1600 // Added in MSVC 2010.
			# define LLVM_ENUM_INT_TYPE(intty) : intty
			#else
			# define LLVM_ENUM_INT_TYPE(intty)
			#endif
			/// \brief Does the compiler support generalized initializers (using braced
			/// lists and std::initializer_list).
			#if __has_feature(cxx_generalized_initializers)
			#define LLVM_HAS_INITIALIZER_LISTS 1
			#else
			#define LLVM_HAS_INITIALIZER_LISTS 0
			#endif
	#endif		#endif
End of changes. 16 change blocks.
	16 lines changed or deleted		74 lines changed or added

	Compression.h		Compression.h
	skipping to change at line 53		skipping to change at line 53
	bool isAvailable();		bool isAvailable();
	Status compress(StringRef InputBuffer,		Status compress(StringRef InputBuffer,
	OwningPtr<MemoryBuffer> &CompressedBuffer,		OwningPtr<MemoryBuffer> &CompressedBuffer,
	CompressionLevel Level = DefaultCompression);		CompressionLevel Level = DefaultCompression);
	Status uncompress(StringRef InputBuffer,		Status uncompress(StringRef InputBuffer,
	OwningPtr<MemoryBuffer> &UncompressedBuffer,		OwningPtr<MemoryBuffer> &UncompressedBuffer,
	size_t UncompressedSize);		size_t UncompressedSize);
			uint32_t crc32(StringRef Buffer);
	} // End of namespace zlib		} // End of namespace zlib
	} // End of namespace llvm		} // End of namespace llvm
	#endif		#endif
End of changes. 1 change blocks.
	0 lines changed or deleted		2 lines changed or added

	ConstantFolding.h		ConstantFolding.h
	//===-- ConstantFolding.h - Fold instructions into constants -------------- ===//		//===-- ConstantFolding.h - Fold instructions into constants ----*- C++ -*- ===//
	//		//
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This file declares routines for folding instructions into constants when all		// This file declares routines for folding instructions into constants when all
	// operands are constants, for example "sub i32 1, 0" -> "1".		// operands are constants, for example "sub i32 1, 0" -> "1".
End of changes. 1 change blocks.
	1 lines changed or deleted		1 lines changed or added

	ConstantRange.h		ConstantRange.h
	skipping to change at line 45		skipping to change at line 45
	#include "llvm/ADT/APInt.h"		#include "llvm/ADT/APInt.h"
	#include "llvm/Support/DataTypes.h"		#include "llvm/Support/DataTypes.h"
	namespace llvm {		namespace llvm {
	/// ConstantRange - This class represents an range of values.		/// ConstantRange - This class represents an range of values.
	///		///
	class ConstantRange {		class ConstantRange {
	APInt Lower, Upper;		APInt Lower, Upper;
			#if LLVM_HAS_RVALUE_REFERENCES
			// If we have move semantics, pass APInts by value and move them into pla
			ce.
			typedef APInt APIntMoveTy;
			#else
			// Otherwise pass by const ref to save one copy.
			typedef const APInt &APIntMoveTy;
			#endif
	public:		public:
	/// Initialize a full (the default) or empty set for the specified bit wi dth.		/// Initialize a full (the default) or empty set for the specified bit wi dth.
	///		///
	explicit ConstantRange(uint32_t BitWidth, bool isFullSet = true);		explicit ConstantRange(uint32_t BitWidth, bool isFullSet = true);
	/// Initialize a range to hold the single specified value.		/// Initialize a range to hold the single specified value.
	///		///
	ConstantRange(const APInt &Value);		ConstantRange(APIntMoveTy Value);
	/// @brief Initialize a range of values explicitly. This will assert out if		/// @brief Initialize a range of values explicitly. This will assert out if
	/// Lower==Upper and Lower != Min or Max value for its type. It will also		/// Lower==Upper and Lower != Min or Max value for its type. It will also
	/// assert out if the two APInt's are not the same bit width.		/// assert out if the two APInt's are not the same bit width.
	ConstantRange(const APInt &Lower, const APInt &Upper);		ConstantRange(APIntMoveTy Lower, APIntMoveTy Upper);
	/// makeICmpRegion - Produce the smallest range that contains all values that		/// makeICmpRegion - Produce the smallest range that contains all values that
	/// might satisfy the comparison specified by Pred when compared to any v alue		/// might satisfy the comparison specified by Pred when compared to any v alue
	/// contained within Other.		/// contained within Other.
	///		///
	/// Solves for range X in 'for all x in X, there exists a y in Y such tha t		/// Solves for range X in 'for all x in X, there exists a y in Y such tha t
	/// icmp op x, y is true'. Every value that might make the comparison tru e		/// icmp op x, y is true'. Every value that might make the comparison tru e
	/// is included in the resulting range.		/// is included in the resulting range.
	static ConstantRange makeICmpRegion(unsigned Pred,		static ConstantRange makeICmpRegion(unsigned Pred,
	const ConstantRange &Other);		const ConstantRange &Other);
End of changes. 3 change blocks.
	2 lines changed or deleted		11 lines changed or added

	Constants.h		Constants.h
	skipping to change at line 115		skipping to change at line 115
	inline const APInt &getValue() const {		inline const APInt &getValue() const {
	return Val;		return Val;
	}		}
	/// getBitWidth - Return the bitwidth of this constant.		/// getBitWidth - Return the bitwidth of this constant.
	unsigned getBitWidth() const { return Val.getBitWidth(); }		unsigned getBitWidth() const { return Val.getBitWidth(); }
	/// Return the constant as a 64-bit unsigned integer value after it		/// Return the constant as a 64-bit unsigned integer value after it
	/// has been zero extended as appropriate for the type of this constant. Note		/// has been zero extended as appropriate for the type of this constant. Note
	/// that this method can assert if the value does not fit in 64 bits.		/// that this method can assert if the value does not fit in 64 bits.
	/// @deprecated
	/// @brief Return the zero extended value.		/// @brief Return the zero extended value.
	inline uint64_t getZExtValue() const {		inline uint64_t getZExtValue() const {
	return Val.getZExtValue();		return Val.getZExtValue();
	}		}
	/// Return the constant as a 64-bit integer value after it has been sign		/// Return the constant as a 64-bit integer value after it has been sign
	/// extended as appropriate for the type of this constant. Note that		/// extended as appropriate for the type of this constant. Note that
	/// this method can assert if the value does not fit in 64 bits.		/// this method can assert if the value does not fit in 64 bits.
	/// @deprecated
	/// @brief Return the sign extended value.		/// @brief Return the sign extended value.
	inline int64_t getSExtValue() const {		inline int64_t getSExtValue() const {
	return Val.getSExtValue();		return Val.getSExtValue();
	}		}
	/// A helper method that can be used to determine if the constant contain ed		/// A helper method that can be used to determine if the constant contain ed
	/// within is equal to a constant. This only works for very small values ,		/// within is equal to a constant. This only works for very small values ,
	/// because this is all that can be represented with all types.		/// because this is all that can be represented with all types.
	/// @brief Determine if this constant's value is same as an unsigned char .		/// @brief Determine if this constant's value is same as an unsigned char .
	bool equalsInt(uint64_t V) const {		bool equalsInt(uint64_t V) const {
	skipping to change at line 860		skipping to change at line 858
	static Constant *getZExt (Constant *C, Type *Ty);		static Constant *getZExt (Constant *C, Type *Ty);
	static Constant *getFPTrunc (Constant *C, Type *Ty);		static Constant *getFPTrunc (Constant *C, Type *Ty);
	static Constant *getFPExtend(Constant *C, Type *Ty);		static Constant *getFPExtend(Constant *C, Type *Ty);
	static Constant *getUIToFP (Constant *C, Type *Ty);		static Constant *getUIToFP (Constant *C, Type *Ty);
	static Constant *getSIToFP (Constant *C, Type *Ty);		static Constant *getSIToFP (Constant *C, Type *Ty);
	static Constant *getFPToUI (Constant *C, Type *Ty);		static Constant *getFPToUI (Constant *C, Type *Ty);
	static Constant *getFPToSI (Constant *C, Type *Ty);		static Constant *getFPToSI (Constant *C, Type *Ty);
	static Constant *getPtrToInt(Constant *C, Type *Ty);		static Constant *getPtrToInt(Constant *C, Type *Ty);
	static Constant *getIntToPtr(Constant *C, Type *Ty);		static Constant *getIntToPtr(Constant *C, Type *Ty);
	static Constant *getBitCast (Constant *C, Type *Ty);		static Constant *getBitCast (Constant *C, Type *Ty);
			static Constant *getAddrSpaceCast(Constant *C, Type *Ty);
	static Constant *getNSWNeg(Constant *C) { return getNeg(C, false, true); }		static Constant *getNSWNeg(Constant *C) { return getNeg(C, false, true); }
	static Constant *getNUWNeg(Constant *C) { return getNeg(C, true, false); }		static Constant *getNUWNeg(Constant *C) { return getNeg(C, true, false); }
	static Constant *getNSWAdd(Constant *C1, Constant *C2) {		static Constant *getNSWAdd(Constant *C1, Constant *C2) {
	return getAdd(C1, C2, false, true);		return getAdd(C1, C2, false, true);
	}		}
	static Constant *getNUWAdd(Constant *C1, Constant *C2) {		static Constant *getNUWAdd(Constant *C1, Constant *C2) {
	return getAdd(C1, C2, true, false);		return getAdd(C1, C2, true, false);
	}		}
	static Constant *getNSWSub(Constant *C1, Constant *C2) {		static Constant *getNSWSub(Constant *C1, Constant *C2) {
	skipping to change at line 940		skipping to change at line 939
	Constant *C, ///< The constant to sext or bitcast		Constant *C, ///< The constant to sext or bitcast
	Type *Ty ///< The type to sext or bitcast C to		Type *Ty ///< The type to sext or bitcast C to
	);		);
	// @brief Create a Trunc or BitCast cast constant expression		// @brief Create a Trunc or BitCast cast constant expression
	static Constant *getTruncOrBitCast(		static Constant *getTruncOrBitCast(
	Constant *C, ///< The constant to trunc or bitcast		Constant *C, ///< The constant to trunc or bitcast
	Type *Ty ///< The type to trunc or bitcast C to		Type *Ty ///< The type to trunc or bitcast C to
	);		);
	/// @brief Create a BitCast or a PtrToInt cast constant expression		/// @brief Create a BitCast, AddrSpaceCast, or a PtrToInt cast constant
			/// expression.
	static Constant *getPointerCast(		static Constant *getPointerCast(
	Constant *C, ///< The pointer value to be casted (operand 0)		Constant *C, ///< The pointer value to be casted (operand 0)
	Type *Ty ///< The type to which cast should be made		Type *Ty ///< The type to which cast should be made
	);		);
			/// @brief Create a BitCast or AddrSpaceCast for a pointer type depending
			on
			/// the address space.
			static Constant *getPointerBitCastOrAddrSpaceCast(
			Constant *C, ///< The constant to addrspacecast or bitcast
			Type *Ty ///< The type to bitcast or addrspacecast C to
			);
	/// @brief Create a ZExt, Bitcast or Trunc for integer -> integer casts		/// @brief Create a ZExt, Bitcast or Trunc for integer -> integer casts
	static Constant *getIntegerCast(		static Constant *getIntegerCast(
	Constant *C, ///< The integer constant to be casted		Constant *C, ///< The integer constant to be casted
	Type *Ty, ///< The integer type to cast to		Type *Ty, ///< The integer type to cast to
	bool isSigned ///< Whether C should be treated as signed or not		bool isSigned ///< Whether C should be treated as signed or not
	);		);
	/// @brief Create a FPExt, Bitcast or FPTrunc for fp -> fp casts		/// @brief Create a FPExt, Bitcast or FPTrunc for fp -> fp casts
	static Constant *getFPCast(		static Constant *getFPCast(
	Constant *C, ///< The integer constant to be casted		Constant *C, ///< The integer constant to be casted
End of changes. 5 change blocks.
	3 lines changed or deleted		11 lines changed or added

	ConvertUTF.h		ConvertUTF.h
	skipping to change at line 90		skipping to change at line 90
	value will point to the illegal value that caused the problem. E.g. ,		value will point to the illegal value that caused the problem. E.g. ,
	in UTF-8 when a sequence is malformed, it points to the start of th e		in UTF-8 when a sequence is malformed, it points to the start of th e
	malformed sequence.		malformed sequence.
	Author: Mark E. Davis, 1994.		Author: Mark E. Davis, 1994.
	Rev History: Rick McGowan, fixes & updates May 2001.		Rev History: Rick McGowan, fixes & updates May 2001.
	Fixes & updates, Sept 2001.		Fixes & updates, Sept 2001.
	------------------------------------------------------------------------ */		------------------------------------------------------------------------ */
	#ifndef CLANG_BASIC_CONVERTUTF_H		#ifndef LLVM_SUPPORT_CONVERTUTF_H
	#define CLANG_BASIC_CONVERTUTF_H		#define LLVM_SUPPORT_CONVERTUTF_H
	/* ---------------------------------------------------------------------		/* ---------------------------------------------------------------------
	The following 4 definitions are compiler-specific.		The following 4 definitions are compiler-specific.
	The C standard does not guarantee that wchar_t has at least		The C standard does not guarantee that wchar_t has at least
	16 bits, so wchar_t is no less portable than unsigned short!		16 bits, so wchar_t is no less portable than unsigned short!
	All should be unsigned values to avoid sign extension during		All should be unsigned values to avoid sign extension during
	bit mask & shift operations.		bit mask & shift operations.
	------------------------------------------------------------------------ */		------------------------------------------------------------------------ */
	typedef unsigned int UTF32; /* at least 32 bits */		typedef unsigned int UTF32; /* at least 32 bits */
	skipping to change at line 115		skipping to change at line 115
	/* Some fundamental constants */		/* Some fundamental constants */
	#define UNI_REPLACEMENT_CHAR (UTF32)0x0000FFFD		#define UNI_REPLACEMENT_CHAR (UTF32)0x0000FFFD
	#define UNI_MAX_BMP (UTF32)0x0000FFFF		#define UNI_MAX_BMP (UTF32)0x0000FFFF
	#define UNI_MAX_UTF16 (UTF32)0x0010FFFF		#define UNI_MAX_UTF16 (UTF32)0x0010FFFF
	#define UNI_MAX_UTF32 (UTF32)0x7FFFFFFF		#define UNI_MAX_UTF32 (UTF32)0x7FFFFFFF
	#define UNI_MAX_LEGAL_UTF32 (UTF32)0x0010FFFF		#define UNI_MAX_LEGAL_UTF32 (UTF32)0x0010FFFF
	#define UNI_MAX_UTF8_BYTES_PER_CODE_POINT 4		#define UNI_MAX_UTF8_BYTES_PER_CODE_POINT 4
			#define UNI_UTF16_BYTE_ORDER_MARK_NATIVE 0xFEFF
			#define UNI_UTF16_BYTE_ORDER_MARK_SWAPPED 0xFFFE
	typedef enum {		typedef enum {
	conversionOK, /* conversion successful */		conversionOK, /* conversion successful */
	sourceExhausted, /* partial character in source, but hit end */		sourceExhausted, /* partial character in source, but hit end */
	targetExhausted, /* insuff. room in target for conversion */		targetExhausted, /* insuff. room in target for conversion */
	sourceIllegal /* source sequence is illegal/malformed */		sourceIllegal /* source sequence is illegal/malformed */
	} ConversionResult;		} ConversionResult;
	typedef enum {		typedef enum {
	strictConversion = 0,		strictConversion = 0,
	lenientConversion		lenientConversion
	skipping to change at line 168		skipping to change at line 171
	Boolean isLegalUTF8String(const UTF8 **source, const UTF8 *sourceEnd);		Boolean isLegalUTF8String(const UTF8 **source, const UTF8 *sourceEnd);
	unsigned getNumBytesForUTF8(UTF8 firstByte);		unsigned getNumBytesForUTF8(UTF8 firstByte);
	#ifdef __cplusplus		#ifdef __cplusplus
	}		}
	/*************************************************************************/		/*************************************************************************/
	/* Below are LLVM-specific wrappers of the functions above. */		/* Below are LLVM-specific wrappers of the functions above. */
			#include "llvm/ADT/ArrayRef.h"
	#include "llvm/ADT/StringRef.h"		#include "llvm/ADT/StringRef.h"
	namespace llvm {		namespace llvm {
	/**		/**
	* Convert an UTF8 StringRef to UTF8, UTF16, or UTF32 depending on		* Convert an UTF8 StringRef to UTF8, UTF16, or UTF32 depending on
	* WideCharWidth. The converted data is written to ResultPtr, which needs t o		* WideCharWidth. The converted data is written to ResultPtr, which needs t o
	* point to at least WideCharWidth * (Source.Size() + 1) bytes. On success,		* point to at least WideCharWidth * (Source.Size() + 1) bytes. On success,
	* ResultPtr will point one after the end of the copied string. On failure,		* ResultPtr will point one after the end of the copied string. On failure,
	* ResultPtr will not be changed, and ErrorPtr will be set to the location of		* ResultPtr will not be changed, and ErrorPtr will be set to the location of
	skipping to change at line 222		skipping to change at line 226
	const UTF8 *sourceEnd,		const UTF8 *sourceEnd,
	UTF32 *target,		UTF32 *target,
	ConversionFlags flags) {		ConversionFlags flags) {
	if (*source == sourceEnd)		if (*source == sourceEnd)
	return sourceExhausted;		return sourceExhausted;
	unsigned size = getNumBytesForUTF8(**source);		unsigned size = getNumBytesForUTF8(**source);
	if ((ptrdiff_t)size > sourceEnd - *source)		if ((ptrdiff_t)size > sourceEnd - *source)
	return sourceExhausted;		return sourceExhausted;
	return ConvertUTF8toUTF32(source, *source + size, &target, target + 1, fl ags);		return ConvertUTF8toUTF32(source, *source + size, &target, target + 1, fl ags);
	}		}
			/**
			* Returns true if a blob of text starts with a UTF-16 big or little endian
			byte
			* order mark.
			*/
			bool hasUTF16ByteOrderMark(ArrayRef<char> SrcBytes);
			/**
			* Converts a stream of raw bytes assumed to be UTF16 into a UTF8 std::stri
			ng.
			*
			* \param [in] SrcBytes A buffer of what is assumed to be UTF-16 encoded te
			xt.
			* \param [out] Out Converted UTF-8 is stored here on success.
			* \returns true on success
			*/
			bool convertUTF16ToUTF8String(ArrayRef<char> SrcBytes, std::string &Out);
	} /* end namespace llvm */		} /* end namespace llvm */
	#endif		#endif
	/* --------------------------------------------------------------------- */		/* --------------------------------------------------------------------- */
	#endif		#endif
End of changes. 4 change blocks.
	2 lines changed or deleted		25 lines changed or added

	Core.h		Core.h
	skipping to change at line 168		skipping to change at line 168
	LLVMInlineHintAttribute = 1<<25,		LLVMInlineHintAttribute = 1<<25,
	LLVMStackAlignment = 7<<26,		LLVMStackAlignment = 7<<26,
	LLVMReturnsTwice = 1 << 29,		LLVMReturnsTwice = 1 << 29,
	LLVMUWTable = 1 << 30,		LLVMUWTable = 1 << 30,
	LLVMNonLazyBind = 1 << 31		LLVMNonLazyBind = 1 << 31
	/* FIXME: These attributes are currently not included in the C API as		/* FIXME: These attributes are currently not included in the C API as
	a temporary measure until the API/ABI impact to the C API is underst ood		a temporary measure until the API/ABI impact to the C API is underst ood
	and the path forward agreed upon.		and the path forward agreed upon.
	LLVMAddressSafety = 1ULL << 32,		LLVMAddressSafety = 1ULL << 32,
	LLVMStackProtectStrongAttribute = 1ULL<<33		LLVMStackProtectStrongAttribute = 1ULL<<33,
			LLVMCold = 1ULL << 34,
			LLVMOptimizeNone = 1ULL << 35
	*/		*/
	} LLVMAttribute;		} LLVMAttribute;
	typedef enum {		typedef enum {
	/* Terminator Instructions */		/* Terminator Instructions */
	LLVMRet = 1,		LLVMRet = 1,
	LLVMBr = 2,		LLVMBr = 2,
	LLVMSwitch = 3,		LLVMSwitch = 3,
	LLVMIndirectBr = 4,		LLVMIndirectBr = 4,
	LLVMInvoke = 5,		LLVMInvoke = 5,
	skipping to change at line 223		skipping to change at line 225
	LLVMSExt = 32,		LLVMSExt = 32,
	LLVMFPToUI = 33,		LLVMFPToUI = 33,
	LLVMFPToSI = 34,		LLVMFPToSI = 34,
	LLVMUIToFP = 35,		LLVMUIToFP = 35,
	LLVMSIToFP = 36,		LLVMSIToFP = 36,
	LLVMFPTrunc = 37,		LLVMFPTrunc = 37,
	LLVMFPExt = 38,		LLVMFPExt = 38,
	LLVMPtrToInt = 39,		LLVMPtrToInt = 39,
	LLVMIntToPtr = 40,		LLVMIntToPtr = 40,
	LLVMBitCast = 41,		LLVMBitCast = 41,
			LLVMAddrSpaceCast = 60,
	/* Other Operators */		/* Other Operators */
	LLVMICmp = 42,		LLVMICmp = 42,
	LLVMFCmp = 43,		LLVMFCmp = 43,
	LLVMPHI = 44,		LLVMPHI = 44,
	LLVMCall = 45,		LLVMCall = 45,
	LLVMSelect = 46,		LLVMSelect = 46,
	LLVMUserOp1 = 47,		LLVMUserOp1 = 47,
	LLVMUserOp2 = 48,		LLVMUserOp2 = 48,
	LLVMVAArg = 49,		LLVMVAArg = 49,
	skipping to change at line 275		skipping to change at line 278
	LLVMMetadataTypeKind, /**< Metadata */		LLVMMetadataTypeKind, /**< Metadata */
	LLVMX86_MMXTypeKind /**< X86 MMX */		LLVMX86_MMXTypeKind /**< X86 MMX */
	} LLVMTypeKind;		} LLVMTypeKind;
	typedef enum {		typedef enum {
	LLVMExternalLinkage, /**< Externally visible function */		LLVMExternalLinkage, /**< Externally visible function */
	LLVMAvailableExternallyLinkage,		LLVMAvailableExternallyLinkage,
	LLVMLinkOnceAnyLinkage, /**< Keep one copy of function when linking (inli ne)*/		LLVMLinkOnceAnyLinkage, /**< Keep one copy of function when linking (inli ne)*/
	LLVMLinkOnceODRLinkage, /**< Same, but only replaced by something		LLVMLinkOnceODRLinkage, /**< Same, but only replaced by something
	equivalent. */		equivalent. */
	LLVMLinkOnceODRAutoHideLinkage, /**< Like LinkOnceODR, but possibly hidde n. */		LLVMLinkOnceODRAutoHideLinkage, /**< Obsolete */
	LLVMWeakAnyLinkage, /**< Keep one copy of function when linking (weak ) */		LLVMWeakAnyLinkage, /**< Keep one copy of function when linking (weak ) */
	LLVMWeakODRLinkage, /**< Same, but only replaced by something		LLVMWeakODRLinkage, /**< Same, but only replaced by something
	equivalent. */		equivalent. */
	LLVMAppendingLinkage, /**< Special purpose, only applies to global arra ys */		LLVMAppendingLinkage, /**< Special purpose, only applies to global arra ys */
	LLVMInternalLinkage, /**< Rename collisions when linking (static		LLVMInternalLinkage, /**< Rename collisions when linking (static
	functions) */		functions) */
	LLVMPrivateLinkage, /**< Like Internal, but omit from symbol table */		LLVMPrivateLinkage, /**< Like Internal, but omit from symbol table */
	LLVMDLLImportLinkage, /**< Function to be imported from DLL */		LLVMDLLImportLinkage, /**< Function to be imported from DLL */
	LLVMDLLExportLinkage, /**< Function to be accessible from DLL */		LLVMDLLExportLinkage, /**< Function to be accessible from DLL */
	LLVMExternalWeakLinkage,/**< ExternalWeak linkage description */		LLVMExternalWeakLinkage,/**< ExternalWeak linkage description */
	skipping to change at line 302		skipping to change at line 305
	typedef enum {		typedef enum {
	LLVMDefaultVisibility, /**< The GV is visible */		LLVMDefaultVisibility, /**< The GV is visible */
	LLVMHiddenVisibility, /**< The GV is hidden */		LLVMHiddenVisibility, /**< The GV is hidden */
	LLVMProtectedVisibility /**< The GV is protected */		LLVMProtectedVisibility /**< The GV is protected */
	} LLVMVisibility;		} LLVMVisibility;
	typedef enum {		typedef enum {
	LLVMCCallConv = 0,		LLVMCCallConv = 0,
	LLVMFastCallConv = 8,		LLVMFastCallConv = 8,
	LLVMColdCallConv = 9,		LLVMColdCallConv = 9,
			LLVMWebKitJSCallConv = 12,
			LLVMAnyRegCallConv = 13,
	LLVMX86StdcallCallConv = 64,		LLVMX86StdcallCallConv = 64,
	LLVMX86FastcallCallConv = 65		LLVMX86FastcallCallConv = 65
	} LLVMCallConv;		} LLVMCallConv;
	typedef enum {		typedef enum {
	LLVMIntEQ = 32, /**< equal */		LLVMIntEQ = 32, /**< equal */
	LLVMIntNE, /**< not equal */		LLVMIntNE, /**< not equal */
	LLVMIntUGT, /**< unsigned greater than */		LLVMIntUGT, /**< unsigned greater than */
	LLVMIntUGE, /**< unsigned greater or equal */		LLVMIntUGE, /**< unsigned greater or equal */
	LLVMIntULT, /**< unsigned less than */		LLVMIntULT, /**< unsigned less than */
	skipping to change at line 409		skipping to change at line 414
	/**		/**
	* @}		* @}
	*/		*/
	void LLVMInitializeCore(LLVMPassRegistryRef R);		void LLVMInitializeCore(LLVMPassRegistryRef R);
	/** Deallocate and destroy all ManagedStatic variables.		/** Deallocate and destroy all ManagedStatic variables.
	@see llvm::llvm_shutdown		@see llvm::llvm_shutdown
	@see ManagedStatic */		@see ManagedStatic */
	void LLVMShutdown();		void LLVMShutdown(void);
	/*===-- Error handling ---------------------------------------------------- ===*/		/*===-- Error handling ---------------------------------------------------- ===*/
			char *LLVMCreateMessage(const char *Message);
	void LLVMDisposeMessage(char *Message);		void LLVMDisposeMessage(char *Message);
			typedef void (*LLVMFatalErrorHandler)(const char *Reason);
			/**
			* Install a fatal error handler. By default, if LLVM detects a fatal error
			, it
			* will call exit(1). This may not be appropriate in many contexts. For exa
			mple,
			* doing exit(1) will bypass many crash reporting/tracing system tools. Thi
			s
			* function allows you to install a callback that will be invoked prior to
			the
			* call to exit(1).
			*/
			void LLVMInstallFatalErrorHandler(LLVMFatalErrorHandler Handler);
			/**
			* Reset the fatal error handler. This resets LLVM's fatal error handling
			* behavior to the default.
			*/
			void LLVMResetFatalErrorHandler(void);
			/**
			* Enable LLVM's built-in stack trace code. This intercepts the OS's crash
			* signals and prints which component of LLVM you were in at the time if th
			e
			* crash.
			*/
			void LLVMEnablePrettyStackTrace(void);
	/**		/**
	* @defgroup LLVMCCoreContext Contexts		* @defgroup LLVMCCoreContext Contexts
	*		*
	* Contexts are execution states for the core LLVM IR system.		* Contexts are execution states for the core LLVM IR system.
	*		*
	* Most types are tied to a context instance. Multiple contexts can		* Most types are tied to a context instance. Multiple contexts can
	* exist simultaneously. A single context is not thread safe. However,		* exist simultaneously. A single context is not thread safe. However,
	* different contexts can execute on different threads simultaneously.		* different contexts can execute on different threads simultaneously.
	*		*
	* @{		* @{
	skipping to change at line 459		skipping to change at line 489
	unsigned SLen);		unsigned SLen);
	unsigned LLVMGetMDKindID(const char* Name, unsigned SLen);		unsigned LLVMGetMDKindID(const char* Name, unsigned SLen);
	/**		/**
	* @}		* @}
	*/		*/
	/**		/**
	* @defgroup LLVMCCoreModule Modules		* @defgroup LLVMCCoreModule Modules
	*		*
	* Modules represent the top-level structure in a LLVM program. An LLVM		* Modules represent the top-level structure in an LLVM program. An LLVM
	* module is effectively a translation unit or a collection of		* module is effectively a translation unit or a collection of
	* translation units merged together.		* translation units merged together.
	*		*
	* @{		* @{
	*/		*/
	/**		/**
	* Create a new, empty module in the global context.		* Create a new, empty module in the global context.
	*		*
	* This is equivalent to calling LLVMModuleCreateWithNameInContext with		* This is equivalent to calling LLVMModuleCreateWithNameInContext with
	skipping to change at line 539		skipping to change at line 569
	/**		/**
	* Print a representation of a module to a file. The ErrorMessage needs to be		* Print a representation of a module to a file. The ErrorMessage needs to be
	* disposed with LLVMDisposeMessage. Returns 0 on success, 1 otherwise.		* disposed with LLVMDisposeMessage. Returns 0 on success, 1 otherwise.
	*		*
	* @see Module::print()		* @see Module::print()
	*/		*/
	LLVMBool LLVMPrintModuleToFile(LLVMModuleRef M, const char *Filename,		LLVMBool LLVMPrintModuleToFile(LLVMModuleRef M, const char *Filename,
	char **ErrorMessage);		char **ErrorMessage);
	/**		/**
			* Return a string representation of the module. Use
			* LLVMDisposeMessage to free the string.
			*
			* @see Module::print()
			*/
			char *LLVMPrintModuleToString(LLVMModuleRef M);
			/**
	* Set inline assembly for a module.		* Set inline assembly for a module.
	*		*
	* @see Module::setModuleInlineAsm()		* @see Module::setModuleInlineAsm()
	*/		*/
	void LLVMSetModuleInlineAsm(LLVMModuleRef M, const char *Asm);		void LLVMSetModuleInlineAsm(LLVMModuleRef M, const char *Asm);
	/**		/**
	* Obtain the context to which this module is associated.		* Obtain the context to which this module is associated.
	*		*
	* @see Module::getContext()		* @see Module::getContext()
	skipping to change at line 690		skipping to change at line 728
	LLVMBool LLVMTypeIsSized(LLVMTypeRef Ty);		LLVMBool LLVMTypeIsSized(LLVMTypeRef Ty);
	/**		/**
	* Obtain the context to which this type instance is associated.		* Obtain the context to which this type instance is associated.
	*		*
	* @see llvm::Type::getContext()		* @see llvm::Type::getContext()
	*/		*/
	LLVMContextRef LLVMGetTypeContext(LLVMTypeRef Ty);		LLVMContextRef LLVMGetTypeContext(LLVMTypeRef Ty);
	/**		/**
			* Dump a representation of a type to stderr.
			*
			* @see llvm::Type::dump()
			*/
			void LLVMDumpType(LLVMTypeRef Val);
			/**
			* Return a string representation of the type. Use
			* LLVMDisposeMessage to free the string.
			*
			* @see llvm::Type::print()
			*/
			char *LLVMPrintTypeToString(LLVMTypeRef Val);
			/**
	* @defgroup LLVMCCoreTypeInt Integer Types		* @defgroup LLVMCCoreTypeInt Integer Types
	*		*
	* Functions in this section operate on integer types.		* Functions in this section operate on integer types.
	*		*
	* @{		* @{
	*/		*/
	/**		/**
	* Obtain an integer type from a context with specified bit width.		* Obtain an integer type from a context with specified bit width.
	*/		*/
	skipping to change at line 1039		skipping to change at line 1092
	/**		/**
	* @defgroup LLVMCCoreValues Values		* @defgroup LLVMCCoreValues Values
	*		*
	* The bulk of LLVM's object model consists of values, which comprise a ver y		* The bulk of LLVM's object model consists of values, which comprise a ver y
	* rich type hierarchy.		* rich type hierarchy.
	*		*
	* LLVMValueRef essentially represents llvm::Value. There is a rich		* LLVMValueRef essentially represents llvm::Value. There is a rich
	* hierarchy of classes within this type. Depending on the instance		* hierarchy of classes within this type. Depending on the instance
	* obtained, not all APIs are available.		* obtained, not all APIs are available.
	*		*
	* Callers can determine the type of a LLVMValueRef by calling the		* Callers can determine the type of an LLVMValueRef by calling the
	* LLVMIsA* family of functions (e.g. LLVMIsAArgument()). These		* LLVMIsA* family of functions (e.g. LLVMIsAArgument()). These
	* functions are defined by a macro, so it isn't obvious which are		* functions are defined by a macro, so it isn't obvious which are
	* available by looking at the Doxygen source code. Instead, look at the		* available by looking at the Doxygen source code. Instead, look at the
	* source definition of LLVM_FOR_EACH_VALUE_SUBCLASS and note the list		* source definition of LLVM_FOR_EACH_VALUE_SUBCLASS and note the list
	* of value names given. These value names also correspond to classes in		* of value names given. These value names also correspond to classes in
	* the llvm::Value hierarchy.		* the llvm::Value hierarchy.
	*		*
	* @{		* @{
	*/		*/
	skipping to change at line 1061		skipping to change at line 1114
	macro(Argument) \		macro(Argument) \
	macro(BasicBlock) \		macro(BasicBlock) \
	macro(InlineAsm) \		macro(InlineAsm) \
	macro(MDNode) \		macro(MDNode) \
	macro(MDString) \		macro(MDString) \
	macro(User) \		macro(User) \
	macro(Constant) \		macro(Constant) \
	macro(BlockAddress) \		macro(BlockAddress) \
	macro(ConstantAggregateZero) \		macro(ConstantAggregateZero) \
	macro(ConstantArray) \		macro(ConstantArray) \
			macro(ConstantDataSequential) \
			macro(ConstantDataArray) \
			macro(ConstantDataVector) \
	macro(ConstantExpr) \		macro(ConstantExpr) \
	macro(ConstantFP) \		macro(ConstantFP) \
	macro(ConstantInt) \		macro(ConstantInt) \
	macro(ConstantPointerNull) \		macro(ConstantPointerNull) \
	macro(ConstantStruct) \		macro(ConstantStruct) \
	macro(ConstantVector) \		macro(ConstantVector) \
	macro(GlobalValue) \		macro(GlobalValue) \
	macro(Function) \		macro(Function) \
	macro(GlobalAlias) \		macro(GlobalAlias) \
	macro(GlobalVariable) \		macro(GlobalVariable) \
	skipping to change at line 1105		skipping to change at line 1161
	macro(BranchInst) \		macro(BranchInst) \
	macro(IndirectBrInst) \		macro(IndirectBrInst) \
	macro(InvokeInst) \		macro(InvokeInst) \
	macro(ReturnInst) \		macro(ReturnInst) \
	macro(SwitchInst) \		macro(SwitchInst) \
	macro(UnreachableInst) \		macro(UnreachableInst) \
	macro(ResumeInst) \		macro(ResumeInst) \
	macro(UnaryInstruction) \		macro(UnaryInstruction) \
	macro(AllocaInst) \		macro(AllocaInst) \
	macro(CastInst) \		macro(CastInst) \
			macro(AddrSpaceCastInst) \
	macro(BitCastInst) \		macro(BitCastInst) \
	macro(FPExtInst) \		macro(FPExtInst) \
	macro(FPToSIInst) \		macro(FPToSIInst) \
	macro(FPToUIInst) \		macro(FPToUIInst) \
	macro(FPTruncInst) \		macro(FPTruncInst) \
	macro(IntToPtrInst) \		macro(IntToPtrInst) \
	macro(PtrToIntInst) \		macro(PtrToIntInst) \
	macro(SExtInst) \		macro(SExtInst) \
	macro(SIToFPInst) \		macro(SIToFPInst) \
	macro(TruncInst) \		macro(TruncInst) \
	skipping to change at line 1160		skipping to change at line 1217
	void LLVMSetValueName(LLVMValueRef Val, const char *Name);		void LLVMSetValueName(LLVMValueRef Val, const char *Name);
	/**		/**
	* Dump a representation of a value to stderr.		* Dump a representation of a value to stderr.
	*		*
	* @see llvm::Value::dump()		* @see llvm::Value::dump()
	*/		*/
	void LLVMDumpValue(LLVMValueRef Val);		void LLVMDumpValue(LLVMValueRef Val);
	/**		/**
			* Return a string representation of the value. Use
			* LLVMDisposeMessage to free the string.
			*
			* @see llvm::Value::print()
			*/
			char *LLVMPrintValueToString(LLVMValueRef Val);
			/**
	* Replace all uses of a value with another one.		* Replace all uses of a value with another one.
	*		*
	* @see llvm::Value::replaceAllUsesWith()		* @see llvm::Value::replaceAllUsesWith()
	*/		*/
	void LLVMReplaceAllUsesWith(LLVMValueRef OldVal, LLVMValueRef NewVal);		void LLVMReplaceAllUsesWith(LLVMValueRef OldVal, LLVMValueRef NewVal);
	/**		/**
	* Determine whether the specified constant instance is constant.		* Determine whether the specified constant instance is constant.
	*/		*/
	LLVMBool LLVMIsConstant(LLVMValueRef Val);		LLVMBool LLVMIsConstant(LLVMValueRef Val);
	/**		/**
	* Determine whether a value instance is undefined.		* Determine whether a value instance is undefined.
	*/		*/
	LLVMBool LLVMIsUndef(LLVMValueRef Val);		LLVMBool LLVMIsUndef(LLVMValueRef Val);
	/**		/**
	* Convert value instances between types.		* Convert value instances between types.
	*		*
	* Internally, a LLVMValueRef is "pinned" to a specific type. This		* Internally, an LLVMValueRef is "pinned" to a specific type. This
	* series of functions allows you to cast an instance to a specific		* series of functions allows you to cast an instance to a specific
	* type.		* type.
	*		*
	* If the cast is not valid for the specified type, NULL is returned.		* If the cast is not valid for the specified type, NULL is returned.
	*		*
	* @see llvm::dyn_cast_or_null<>		* @see llvm::dyn_cast_or_null<>
	*/		*/
	#define LLVM_DECLARE_VALUE_CAST(name) \		#define LLVM_DECLARE_VALUE_CAST(name) \
	LLVMValueRef LLVMIsA##name(LLVMValueRef Val);		LLVMValueRef LLVMIsA##name(LLVMValueRef Val);
	LLVM_FOR_EACH_VALUE_SUBCLASS(LLVM_DECLARE_VALUE_CAST)		LLVM_FOR_EACH_VALUE_SUBCLASS(LLVM_DECLARE_VALUE_CAST)
	skipping to change at line 1201		skipping to change at line 1266
	/**		/**
	* @}		* @}
	*/		*/
	/**		/**
	* @defgroup LLVMCCoreValueUses Usage		* @defgroup LLVMCCoreValueUses Usage
	*		*
	* This module defines functions that allow you to inspect the uses of a		* This module defines functions that allow you to inspect the uses of a
	* LLVMValueRef.		* LLVMValueRef.
	*		*
	* It is possible to obtain a LLVMUseRef for any LLVMValueRef instance.		* It is possible to obtain an LLVMUseRef for any LLVMValueRef instance.
	* Each LLVMUseRef (which corresponds to a llvm::Use instance) holds a		* Each LLVMUseRef (which corresponds to a llvm::Use instance) holds a
	* llvm::User and llvm::Value.		* llvm::User and llvm::Value.
	*		*
	* @{		* @{
	*/		*/
	/**		/**
	* Obtain the first use of a value.		* Obtain the first use of a value.
	*		*
	* Uses are obtained in an iterator fashion. First, call this function		* Uses are obtained in an iterator fashion. First, call this function
	skipping to change at line 1568		skipping to change at line 1633
	LLVMValueRef LLVMConstZExt(LLVMValueRef ConstantVal, LLVMTypeRef ToType);		LLVMValueRef LLVMConstZExt(LLVMValueRef ConstantVal, LLVMTypeRef ToType);
	LLVMValueRef LLVMConstFPTrunc(LLVMValueRef ConstantVal, LLVMTypeRef ToType) ;		LLVMValueRef LLVMConstFPTrunc(LLVMValueRef ConstantVal, LLVMTypeRef ToType) ;
	LLVMValueRef LLVMConstFPExt(LLVMValueRef ConstantVal, LLVMTypeRef ToType);		LLVMValueRef LLVMConstFPExt(LLVMValueRef ConstantVal, LLVMTypeRef ToType);
	LLVMValueRef LLVMConstUIToFP(LLVMValueRef ConstantVal, LLVMTypeRef ToType);		LLVMValueRef LLVMConstUIToFP(LLVMValueRef ConstantVal, LLVMTypeRef ToType);
	LLVMValueRef LLVMConstSIToFP(LLVMValueRef ConstantVal, LLVMTypeRef ToType);		LLVMValueRef LLVMConstSIToFP(LLVMValueRef ConstantVal, LLVMTypeRef ToType);
	LLVMValueRef LLVMConstFPToUI(LLVMValueRef ConstantVal, LLVMTypeRef ToType);		LLVMValueRef LLVMConstFPToUI(LLVMValueRef ConstantVal, LLVMTypeRef ToType);
	LLVMValueRef LLVMConstFPToSI(LLVMValueRef ConstantVal, LLVMTypeRef ToType);		LLVMValueRef LLVMConstFPToSI(LLVMValueRef ConstantVal, LLVMTypeRef ToType);
	LLVMValueRef LLVMConstPtrToInt(LLVMValueRef ConstantVal, LLVMTypeRef ToType );		LLVMValueRef LLVMConstPtrToInt(LLVMValueRef ConstantVal, LLVMTypeRef ToType );
	LLVMValueRef LLVMConstIntToPtr(LLVMValueRef ConstantVal, LLVMTypeRef ToType );		LLVMValueRef LLVMConstIntToPtr(LLVMValueRef ConstantVal, LLVMTypeRef ToType );
	LLVMValueRef LLVMConstBitCast(LLVMValueRef ConstantVal, LLVMTypeRef ToType) ;		LLVMValueRef LLVMConstBitCast(LLVMValueRef ConstantVal, LLVMTypeRef ToType) ;
			LLVMValueRef LLVMConstAddrSpaceCast(LLVMValueRef ConstantVal, LLVMTypeRef T oType);
	LLVMValueRef LLVMConstZExtOrBitCast(LLVMValueRef ConstantVal,		LLVMValueRef LLVMConstZExtOrBitCast(LLVMValueRef ConstantVal,
	LLVMTypeRef ToType);		LLVMTypeRef ToType);
	LLVMValueRef LLVMConstSExtOrBitCast(LLVMValueRef ConstantVal,		LLVMValueRef LLVMConstSExtOrBitCast(LLVMValueRef ConstantVal,
	LLVMTypeRef ToType);		LLVMTypeRef ToType);
	LLVMValueRef LLVMConstTruncOrBitCast(LLVMValueRef ConstantVal,		LLVMValueRef LLVMConstTruncOrBitCast(LLVMValueRef ConstantVal,
	LLVMTypeRef ToType);		LLVMTypeRef ToType);
	LLVMValueRef LLVMConstPointerCast(LLVMValueRef ConstantVal,		LLVMValueRef LLVMConstPointerCast(LLVMValueRef ConstantVal,
	LLVMTypeRef ToType);		LLVMTypeRef ToType);
	LLVMValueRef LLVMConstIntCast(LLVMValueRef ConstantVal, LLVMTypeRef ToType,		LLVMValueRef LLVMConstIntCast(LLVMValueRef ConstantVal, LLVMTypeRef ToType,
	LLVMBool isSigned);		LLVMBool isSigned);
	skipping to change at line 1623		skipping to change at line 1689
	*/		*/
	LLVMModuleRef LLVMGetGlobalParent(LLVMValueRef Global);		LLVMModuleRef LLVMGetGlobalParent(LLVMValueRef Global);
	LLVMBool LLVMIsDeclaration(LLVMValueRef Global);		LLVMBool LLVMIsDeclaration(LLVMValueRef Global);
	LLVMLinkage LLVMGetLinkage(LLVMValueRef Global);		LLVMLinkage LLVMGetLinkage(LLVMValueRef Global);
	void LLVMSetLinkage(LLVMValueRef Global, LLVMLinkage Linkage);		void LLVMSetLinkage(LLVMValueRef Global, LLVMLinkage Linkage);
	const char *LLVMGetSection(LLVMValueRef Global);		const char *LLVMGetSection(LLVMValueRef Global);
	void LLVMSetSection(LLVMValueRef Global, const char *Section);		void LLVMSetSection(LLVMValueRef Global, const char *Section);
	LLVMVisibility LLVMGetVisibility(LLVMValueRef Global);		LLVMVisibility LLVMGetVisibility(LLVMValueRef Global);
	void LLVMSetVisibility(LLVMValueRef Global, LLVMVisibility Viz);		void LLVMSetVisibility(LLVMValueRef Global, LLVMVisibility Viz);
	unsigned LLVMGetAlignment(LLVMValueRef Global);
	void LLVMSetAlignment(LLVMValueRef Global, unsigned Bytes);		/**
			* @defgroup LLVMCCoreValueWithAlignment Values with alignment
			*
			* Functions in this group only apply to values with alignment, i.e.
			* global variables, load and store instructions.
			*/
			/**
			* Obtain the preferred alignment of the value.
			* @see llvm::LoadInst::getAlignment()
			* @see llvm::StoreInst::getAlignment()
			* @see llvm::GlobalValue::getAlignment()
			*/
			unsigned LLVMGetAlignment(LLVMValueRef V);
			/**
			* Set the preferred alignment of the value.
			* @see llvm::LoadInst::setAlignment()
			* @see llvm::StoreInst::setAlignment()
			* @see llvm::GlobalValue::setAlignment()
			*/
			void LLVMSetAlignment(LLVMValueRef V, unsigned Bytes);
			/**
			* @}
			*/
	/**		/**
	* @defgroup LLVMCoreValueConstantGlobalVariable Global Variables		* @defgroup LLVMCoreValueConstantGlobalVariable Global Variables
	*		*
	* This group contains functions that operate on global variable values.		* This group contains functions that operate on global variable values.
	*		*
	* @see llvm::GlobalVariable		* @see llvm::GlobalVariable
	*		*
	* @{		* @{
	*/		*/
	skipping to change at line 1804		skipping to change at line 1895
	*		*
	* Parameters are indexed from 0.		* Parameters are indexed from 0.
	*		*
	* @see llvm::Function::arg_begin()		* @see llvm::Function::arg_begin()
	*/		*/
	LLVMValueRef LLVMGetParam(LLVMValueRef Fn, unsigned Index);		LLVMValueRef LLVMGetParam(LLVMValueRef Fn, unsigned Index);
	/**		/**
	* Obtain the function to which this argument belongs.		* Obtain the function to which this argument belongs.
	*		*
	* Unlike other functions in this group, this one takes a LLVMValueRef		* Unlike other functions in this group, this one takes an LLVMValueRef
	* that corresponds to a llvm::Attribute.		* that corresponds to a llvm::Attribute.
	*		*
	* The returned LLVMValueRef is the llvm::Function to which this		* The returned LLVMValueRef is the llvm::Function to which this
	* argument belongs.		* argument belongs.
	*/		*/
	LLVMValueRef LLVMGetParamParent(LLVMValueRef Inst);		LLVMValueRef LLVMGetParamParent(LLVMValueRef Inst);
	/**		/**
	* Obtain the first parameter to a function.		* Obtain the first parameter to a function.
	*		*
	skipping to change at line 1829		skipping to change at line 1920
	/**		/**
	* Obtain the last parameter to a function.		* Obtain the last parameter to a function.
	*		*
	* @see llvm::Function::arg_end()		* @see llvm::Function::arg_end()
	*/		*/
	LLVMValueRef LLVMGetLastParam(LLVMValueRef Fn);		LLVMValueRef LLVMGetLastParam(LLVMValueRef Fn);
	/**		/**
	* Obtain the next parameter to a function.		* Obtain the next parameter to a function.
	*		*
	* This takes a LLVMValueRef obtained from LLVMGetFirstParam() (which is		* This takes an LLVMValueRef obtained from LLVMGetFirstParam() (which is
	* actually a wrapped iterator) and obtains the next parameter from the		* actually a wrapped iterator) and obtains the next parameter from the
	* underlying iterator.		* underlying iterator.
	*/		*/
	LLVMValueRef LLVMGetNextParam(LLVMValueRef Arg);		LLVMValueRef LLVMGetNextParam(LLVMValueRef Arg);
	/**		/**
	* Obtain the previous parameter to a function.		* Obtain the previous parameter to a function.
	*		*
	* This is the opposite of LLVMGetNextParam().		* This is the opposite of LLVMGetNextParam().
	*/		*/
	skipping to change at line 1978		skipping to change at line 2069
	*		*
	* @{		* @{
	*/		*/
	/**		/**
	* Convert a basic block instance to a value type.		* Convert a basic block instance to a value type.
	*/		*/
	LLVMValueRef LLVMBasicBlockAsValue(LLVMBasicBlockRef BB);		LLVMValueRef LLVMBasicBlockAsValue(LLVMBasicBlockRef BB);
	/**		/**
	* Determine whether a LLVMValueRef is itself a basic block.		* Determine whether an LLVMValueRef is itself a basic block.
	*/		*/
	LLVMBool LLVMValueIsBasicBlock(LLVMValueRef Val);		LLVMBool LLVMValueIsBasicBlock(LLVMValueRef Val);
	/**		/**
	* Convert a LLVMValueRef to a LLVMBasicBlockRef instance.		* Convert an LLVMValueRef to an LLVMBasicBlockRef instance.
	*/		*/
	LLVMBasicBlockRef LLVMValueAsBasicBlock(LLVMValueRef Val);		LLVMBasicBlockRef LLVMValueAsBasicBlock(LLVMValueRef Val);
	/**		/**
	* Obtain the function to which a basic block belongs.		* Obtain the function to which a basic block belongs.
	*		*
	* @see llvm::BasicBlock::getParent()		* @see llvm::BasicBlock::getParent()
	*/		*/
	LLVMValueRef LLVMGetBasicBlockParent(LLVMBasicBlockRef BB);		LLVMValueRef LLVMGetBasicBlockParent(LLVMBasicBlockRef BB);
	skipping to change at line 2140		skipping to change at line 2231
	* Obtain the first instruction in a basic block.		* Obtain the first instruction in a basic block.
	*		*
	* The returned LLVMValueRef corresponds to a llvm::Instruction		* The returned LLVMValueRef corresponds to a llvm::Instruction
	* instance.		* instance.
	*/		*/
	LLVMValueRef LLVMGetFirstInstruction(LLVMBasicBlockRef BB);		LLVMValueRef LLVMGetFirstInstruction(LLVMBasicBlockRef BB);
	/**		/**
	* Obtain the last instruction in a basic block.		* Obtain the last instruction in a basic block.
	*		*
	* The returned LLVMValueRef corresponds to a LLVM:Instruction.		* The returned LLVMValueRef corresponds to an LLVM:Instruction.
	*/		*/
	LLVMValueRef LLVMGetLastInstruction(LLVMBasicBlockRef BB);		LLVMValueRef LLVMGetLastInstruction(LLVMBasicBlockRef BB);
	/**		/**
	* @}		* @}
	*/		*/
	/**		/**
	* @defgroup LLVMCCoreValueInstruction Instructions		* @defgroup LLVMCCoreValueInstruction Instructions
	*		*
	skipping to change at line 2321		skipping to change at line 2412
	*/		*/
	void LLVMAddIncoming(LLVMValueRef PhiNode, LLVMValueRef *IncomingValues,		void LLVMAddIncoming(LLVMValueRef PhiNode, LLVMValueRef *IncomingValues,
	LLVMBasicBlockRef *IncomingBlocks, unsigned Count);		LLVMBasicBlockRef *IncomingBlocks, unsigned Count);
	/**		/**
	* Obtain the number of incoming basic blocks to a PHI node.		* Obtain the number of incoming basic blocks to a PHI node.
	*/		*/
	unsigned LLVMCountIncoming(LLVMValueRef PhiNode);		unsigned LLVMCountIncoming(LLVMValueRef PhiNode);
	/**		/**
	* Obtain an incoming value to a PHI node as a LLVMValueRef.		* Obtain an incoming value to a PHI node as an LLVMValueRef.
	*/		*/
	LLVMValueRef LLVMGetIncomingValue(LLVMValueRef PhiNode, unsigned Index);		LLVMValueRef LLVMGetIncomingValue(LLVMValueRef PhiNode, unsigned Index);
	/**		/**
	* Obtain an incoming value to a PHI node as a LLVMBasicBlockRef.		* Obtain an incoming value to a PHI node as an LLVMBasicBlockRef.
	*/		*/
	LLVMBasicBlockRef LLVMGetIncomingBlock(LLVMValueRef PhiNode, unsigned Index );		LLVMBasicBlockRef LLVMGetIncomingBlock(LLVMValueRef PhiNode, unsigned Index );
	/**		/**
	* @}		* @}
	*/		*/
	/**		/**
	* @}		* @}
	*/		*/
	skipping to change at line 2517		skipping to change at line 2608
	LLVMValueRef LLVMBuildFPTrunc(LLVMBuilderRef, LLVMValueRef Val,		LLVMValueRef LLVMBuildFPTrunc(LLVMBuilderRef, LLVMValueRef Val,
	LLVMTypeRef DestTy, const char *Name);		LLVMTypeRef DestTy, const char *Name);
	LLVMValueRef LLVMBuildFPExt(LLVMBuilderRef, LLVMValueRef Val,		LLVMValueRef LLVMBuildFPExt(LLVMBuilderRef, LLVMValueRef Val,
	LLVMTypeRef DestTy, const char *Name);		LLVMTypeRef DestTy, const char *Name);
	LLVMValueRef LLVMBuildPtrToInt(LLVMBuilderRef, LLVMValueRef Val,		LLVMValueRef LLVMBuildPtrToInt(LLVMBuilderRef, LLVMValueRef Val,
	LLVMTypeRef DestTy, const char *Name);		LLVMTypeRef DestTy, const char *Name);
	LLVMValueRef LLVMBuildIntToPtr(LLVMBuilderRef, LLVMValueRef Val,		LLVMValueRef LLVMBuildIntToPtr(LLVMBuilderRef, LLVMValueRef Val,
	LLVMTypeRef DestTy, const char *Name);		LLVMTypeRef DestTy, const char *Name);
	LLVMValueRef LLVMBuildBitCast(LLVMBuilderRef, LLVMValueRef Val,		LLVMValueRef LLVMBuildBitCast(LLVMBuilderRef, LLVMValueRef Val,
	LLVMTypeRef DestTy, const char *Name);		LLVMTypeRef DestTy, const char *Name);
			LLVMValueRef LLVMBuildAddrSpaceCast(LLVMBuilderRef, LLVMValueRef Val,
			LLVMTypeRef DestTy, const char *Name);
	LLVMValueRef LLVMBuildZExtOrBitCast(LLVMBuilderRef, LLVMValueRef Val,		LLVMValueRef LLVMBuildZExtOrBitCast(LLVMBuilderRef, LLVMValueRef Val,
	LLVMTypeRef DestTy, const char *Name);		LLVMTypeRef DestTy, const char *Name);
	LLVMValueRef LLVMBuildSExtOrBitCast(LLVMBuilderRef, LLVMValueRef Val,		LLVMValueRef LLVMBuildSExtOrBitCast(LLVMBuilderRef, LLVMValueRef Val,
	LLVMTypeRef DestTy, const char *Name);		LLVMTypeRef DestTy, const char *Name);
	LLVMValueRef LLVMBuildTruncOrBitCast(LLVMBuilderRef, LLVMValueRef Val,		LLVMValueRef LLVMBuildTruncOrBitCast(LLVMBuilderRef, LLVMValueRef Val,
	LLVMTypeRef DestTy, const char *Name);		LLVMTypeRef DestTy, const char *Name);
	LLVMValueRef LLVMBuildCast(LLVMBuilderRef B, LLVMOpcode Op, LLVMValueRef Va l,		LLVMValueRef LLVMBuildCast(LLVMBuilderRef B, LLVMOpcode Op, LLVMValueRef Va l,
	LLVMTypeRef DestTy, const char *Name);		LLVMTypeRef DestTy, const char *Name);
	LLVMValueRef LLVMBuildPointerCast(LLVMBuilderRef, LLVMValueRef Val,		LLVMValueRef LLVMBuildPointerCast(LLVMBuilderRef, LLVMValueRef Val,
	LLVMTypeRef DestTy, const char *Name);		LLVMTypeRef DestTy, const char *Name);
	skipping to change at line 2705		skipping to change at line 2798
	* Handle the structures needed to make LLVM safe for multithreading.		* Handle the structures needed to make LLVM safe for multithreading.
	*		*
	* @{		* @{
	*/		*/
	/** Allocate and initialize structures needed to make LLVM safe for		/** Allocate and initialize structures needed to make LLVM safe for
	multithreading. The return value indicates whether multithreaded		multithreading. The return value indicates whether multithreaded
	initialization succeeded. Must be executed in isolation from all		initialization succeeded. Must be executed in isolation from all
	other LLVM api calls.		other LLVM api calls.
	@see llvm::llvm_start_multithreaded */		@see llvm::llvm_start_multithreaded */
	LLVMBool LLVMStartMultithreaded();		LLVMBool LLVMStartMultithreaded(void);
	/** Deallocate structures necessary to make LLVM safe for multithreading.		/** Deallocate structures necessary to make LLVM safe for multithreading.
	Must be executed in isolation from all other LLVM api calls.		Must be executed in isolation from all other LLVM api calls.
	@see llvm::llvm_stop_multithreaded */		@see llvm::llvm_stop_multithreaded */
	void LLVMStopMultithreaded();		void LLVMStopMultithreaded(void);
	/** Check whether LLVM is executing in thread-safe mode or not.		/** Check whether LLVM is executing in thread-safe mode or not.
	@see llvm::llvm_is_multithreaded */		@see llvm::llvm_is_multithreaded */
	LLVMBool LLVMIsMultithreaded();		LLVMBool LLVMIsMultithreaded(void);
	/**		/**
	* @}		* @}
	*/		*/
	/**		/**
	* @}		* @}
	*/		*/
	/**		/**
End of changes. 29 change blocks.
	19 lines changed or deleted		117 lines changed or added

	CostTable.h		CostTable.h
	skipping to change at line 28		skipping to change at line 28
	namespace llvm {		namespace llvm {
	/// Cost Table Entry		/// Cost Table Entry
	template <class TypeTy>		template <class TypeTy>
	struct CostTblEntry {		struct CostTblEntry {
	int ISD;		int ISD;
	TypeTy Type;		TypeTy Type;
	unsigned Cost;		unsigned Cost;
	};		};
	/// Find in cost table, TypeTy must be comparable by ==		/// Find in cost table, TypeTy must be comparable to CompareTy by ==
	template <class TypeTy>		template <class TypeTy, class CompareTy>
	int CostTableLookup(const CostTblEntry<TypeTy> *Tbl,		int CostTableLookup(const CostTblEntry<TypeTy> *Tbl, unsigned len, int ISD,
	unsigned len, int ISD, TypeTy Ty) {		CompareTy Ty) {
	for (unsigned int i = 0; i < len; ++i)		for (unsigned int i = 0; i < len; ++i)
	if (Tbl[i].ISD == ISD && Tbl[i].Type == Ty)		if (ISD == Tbl[i].ISD && Ty == Tbl[i].Type)
	return i;		return i;
	// Could not find an entry.		// Could not find an entry.
	return -1;		return -1;
	}		}
			/// Find in cost table, TypeTy must be comparable to CompareTy by ==
			template <class TypeTy, class CompareTy, unsigned N>
			int CostTableLookup(const CostTblEntry<TypeTy>(&Tbl)[N], int ISD,
			CompareTy Ty) {
			return CostTableLookup(Tbl, N, ISD, Ty);
			}
	/// Type Conversion Cost Table		/// Type Conversion Cost Table
	template <class TypeTy>		template <class TypeTy>
	struct TypeConversionCostTblEntry {		struct TypeConversionCostTblEntry {
	int ISD;		int ISD;
	TypeTy Dst;		TypeTy Dst;
	TypeTy Src;		TypeTy Src;
	unsigned Cost;		unsigned Cost;
	};		};
	/// Find in type conversion cost table, TypeTy must be comparable by ==		/// Find in type conversion cost table, TypeTy must be comparable to Compar
	template <class TypeTy>		eTy
			/// by ==
			template <class TypeTy, class CompareTy>
	int ConvertCostTableLookup(const TypeConversionCostTblEntry<TypeTy> *Tbl,		int ConvertCostTableLookup(const TypeConversionCostTblEntry<TypeTy> *Tbl,
	unsigned len, int ISD, TypeTy Dst, TypeTy Src) {		unsigned len, int ISD, CompareTy Dst,
			CompareTy Src) {
	for (unsigned int i = 0; i < len; ++i)		for (unsigned int i = 0; i < len; ++i)
	if (Tbl[i].ISD == ISD && Tbl[i].Src == Src && Tbl[i].Dst == Dst)		if (ISD == Tbl[i].ISD && Src == Tbl[i].Src && Dst == Tbl[i].Dst)
	return i;		return i;
	// Could not find an entry.		// Could not find an entry.
	return -1;		return -1;
	}		}
			/// Find in type conversion cost table, TypeTy must be comparable to Compar
			eTy
			/// by ==
			template <class TypeTy, class CompareTy, unsigned N>
			int ConvertCostTableLookup(const TypeConversionCostTblEntry<TypeTy>(&Tbl)[N
			],
			int ISD, CompareTy Dst, CompareTy Src) {
			return ConvertCostTableLookup(Tbl, N, ISD, Dst, Src);
			}
	} // namespace llvm		} // namespace llvm
	#endif /* LLVM_TARGET_COSTTABLE_H_ */		#endif /* LLVM_TARGET_COSTTABLE_H_ */
End of changes. 7 change blocks.
	9 lines changed or deleted		29 lines changed or added

	DIBuilder.h		DIBuilder.h
	skipping to change at line 20		skipping to change at line 20
	// This file defines a DIBuilder that is useful for creating debugging		// This file defines a DIBuilder that is useful for creating debugging
	// information entries in LLVM IR form.		// information entries in LLVM IR form.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_DIBUILDER_H		#ifndef LLVM_DIBUILDER_H
	#define LLVM_DIBUILDER_H		#define LLVM_DIBUILDER_H
	#include "llvm/ADT/ArrayRef.h"		#include "llvm/ADT/ArrayRef.h"
	#include "llvm/ADT/StringRef.h"		#include "llvm/ADT/StringRef.h"
			#include "llvm/DebugInfo.h"
	#include "llvm/Support/DataTypes.h"		#include "llvm/Support/DataTypes.h"
			#include "llvm/Support/ValueHandle.h"
	namespace llvm {		namespace llvm {
	class BasicBlock;		class BasicBlock;
	class Instruction;		class Instruction;
	class Function;		class Function;
	class Module;		class Module;
	class Value;		class Value;
	class LLVMContext;		class LLVMContext;
	class MDNode;		class MDNode;
	class StringRef;		class StringRef;
	class DIBasicType;		class DIBasicType;
			class DICompileUnit;
	class DICompositeType;		class DICompositeType;
	class DIDerivedType;		class DIDerivedType;
	class DIDescriptor;		class DIDescriptor;
	class DIFile;		class DIFile;
	class DIEnumerator;		class DIEnumerator;
	class DIType;		class DIType;
	class DIArray;		class DIArray;
	class DIGlobalVariable;		class DIGlobalVariable;
	class DIImportedModule;		class DIImportedEntity;
	class DINameSpace;		class DINameSpace;
	class DIVariable;		class DIVariable;
	class DISubrange;		class DISubrange;
	class DILexicalBlockFile;		class DILexicalBlockFile;
	class DILexicalBlock;		class DILexicalBlock;
	class DIScope;		class DIScope;
	class DISubprogram;		class DISubprogram;
	class DITemplateTypeParameter;		class DITemplateTypeParameter;
	class DITemplateValueParameter;		class DITemplateValueParameter;
	class DIObjCProperty;		class DIObjCProperty;
	class DIBuilder {		class DIBuilder {
	private:		private:
	Module &M;		Module &M;
	LLVMContext & VMContext;		LLVMContext & VMContext;
	MDNode *TheCU;
	MDNode *TempEnumTypes;		MDNode *TempEnumTypes;
	MDNode *TempRetainTypes;		MDNode *TempRetainTypes;
	MDNode *TempSubprograms;		MDNode *TempSubprograms;
	MDNode *TempGVs;		MDNode *TempGVs;
	MDNode *TempImportedModules;		MDNode *TempImportedModules;
	Function *DeclareFn; // llvm.dbg.declare		Function *DeclareFn; // llvm.dbg.declare
	Function *ValueFn; // llvm.dbg.value		Function *ValueFn; // llvm.dbg.value
	SmallVector<Value *, 4> AllEnumTypes;		SmallVector<Value *, 4> AllEnumTypes;
	SmallVector<Value *, 4> AllRetainTypes;		/// Use TrackingVH to collect RetainTypes, since they can be updated
			/// later on.
			SmallVector<TrackingVH<MDNode>, 4> AllRetainTypes;
	SmallVector<Value *, 4> AllSubprograms;		SmallVector<Value *, 4> AllSubprograms;
	SmallVector<Value *, 4> AllGVs;		SmallVector<Value *, 4> AllGVs;
	SmallVector<Value *, 4> AllImportedModules;		SmallVector<Value *, 4> AllImportedModules;
			DITemplateValueParameter
			createTemplateValueParameter(unsigned Tag, DIDescriptor Scope,
			StringRef Name, DIType Ty, Value *Val,
			MDNode *File = 0, unsigned LineNo = 0,
			unsigned ColumnNo = 0);
	DIBuilder(const DIBuilder &) LLVM_DELETED_FUNCTION;		DIBuilder(const DIBuilder &) LLVM_DELETED_FUNCTION;
	void operator=(const DIBuilder &) LLVM_DELETED_FUNCTION;		void operator=(const DIBuilder &) LLVM_DELETED_FUNCTION;
	public:		public:
	explicit DIBuilder(Module &M);		explicit DIBuilder(Module &M);
	const MDNode *getCU() { return TheCU; }
	enum ComplexAddrKind { OpPlus=1, OpDeref };		enum ComplexAddrKind { OpPlus=1, OpDeref };
	/// finalize - Construct any deferred debug info descriptors.		/// finalize - Construct any deferred debug info descriptors.
	void finalize();		void finalize();
	/// createCompileUnit - A CompileUnit provides an anchor for all debugg ing		/// createCompileUnit - A CompileUnit provides an anchor for all debugg ing
	/// information generated during this instance of compilation.		/// information generated during this instance of compilation.
	/// @param Lang Source programming language, eg. dwarf::DW_LANG_C99		/// @param Lang Source programming language, eg. dwarf::DW_LANG_C99
	/// @param File File name		/// @param File File name
	/// @param Dir Directory		/// @param Dir Directory
	skipping to change at line 100		skipping to change at line 109
	/// Usuall this is a compiler version string.		/// Usuall this is a compiler version string.
	/// @param isOptimized A boolean flag which indicates whether optimizat ion		/// @param isOptimized A boolean flag which indicates whether optimizat ion
	/// is ON or not.		/// is ON or not.
	/// @param Flags This string lists command line options. This string is		/// @param Flags This string lists command line options. This string is
	/// directly embedded in debug info output which may be used		/// directly embedded in debug info output which may be used
	/// by a tool analyzing generated debugging information .		/// by a tool analyzing generated debugging information .
	/// @param RV This indicates runtime version for languages like		/// @param RV This indicates runtime version for languages like
	/// Objective-C.		/// Objective-C.
	/// @param SplitName The name of the file that we'll split debug info o ut		/// @param SplitName The name of the file that we'll split debug info o ut
	/// into.		/// into.
	void createCompileUnit(unsigned Lang, StringRef File, StringRef Dir,		DICompileUnit createCompileUnit(unsigned Lang, StringRef File,
	StringRef Producer, bool isOptimized,		StringRef Dir, StringRef Producer,
	StringRef Flags, unsigned RV,		bool isOptimized, StringRef Flags,
	StringRef SplitName = StringRef());		unsigned RV,
			StringRef SplitName = StringRef());
	/// createFile - Create a file descriptor to hold debugging information		/// createFile - Create a file descriptor to hold debugging information
	/// for a file.		/// for a file.
	DIFile createFile(StringRef Filename, StringRef Directory);		DIFile createFile(StringRef Filename, StringRef Directory);
	/// createEnumerator - Create a single enumerator value.		/// createEnumerator - Create a single enumerator value.
	DIEnumerator createEnumerator(StringRef Name, uint64_t Val);		DIEnumerator createEnumerator(StringRef Name, int64_t Val);
			/// \brief Create a DWARF unspecified type.
			DIBasicType createUnspecifiedType(StringRef Name);
	/// createNullPtrType - Create C++0x nullptr type.		/// \brief Create C++11 nullptr type.
	DIType createNullPtrType(StringRef Name);		DIBasicType createNullPtrType();
	/// createBasicType - Create debugging information entry for a basic		/// createBasicType - Create debugging information entry for a basic
	/// type.		/// type.
	/// @param Name Type name.		/// @param Name Type name.
	/// @param SizeInBits Size of the type.		/// @param SizeInBits Size of the type.
	/// @param AlignInBits Type alignment.		/// @param AlignInBits Type alignment.
	/// @param Encoding DWARF encoding code, e.g. dwarf::DW_ATE_float.		/// @param Encoding DWARF encoding code, e.g. dwarf::DW_ATE_float.
	DIBasicType createBasicType(StringRef Name, uint64_t SizeInBits,		DIBasicType createBasicType(StringRef Name, uint64_t SizeInBits,
	uint64_t AlignInBits, unsigned Encoding);		uint64_t AlignInBits, unsigned Encoding);
	skipping to change at line 158		skipping to change at line 171
	/// createTypedef - Create debugging information entry for a typedef.		/// createTypedef - Create debugging information entry for a typedef.
	/// @param Ty Original type.		/// @param Ty Original type.
	/// @param Name Typedef name.		/// @param Name Typedef name.
	/// @param File File where this type is defined.		/// @param File File where this type is defined.
	/// @param LineNo Line number.		/// @param LineNo Line number.
	/// @param Context The surrounding context for the typedef.		/// @param Context The surrounding context for the typedef.
	DIDerivedType createTypedef(DIType Ty, StringRef Name, DIFile File,		DIDerivedType createTypedef(DIType Ty, StringRef Name, DIFile File,
	unsigned LineNo, DIDescriptor Context);		unsigned LineNo, DIDescriptor Context);
	/// createFriend - Create debugging information entry for a 'friend'.		/// createFriend - Create debugging information entry for a 'friend'.
	DIType createFriend(DIType Ty, DIType FriendTy);		DIDerivedType createFriend(DIType Ty, DIType FriendTy);
	/// createInheritance - Create debugging information entry to establish		/// createInheritance - Create debugging information entry to establish
	/// inheritance relationship between two types.		/// inheritance relationship between two types.
	/// @param Ty Original type.		/// @param Ty Original type.
	/// @param BaseTy Base type. Ty is inherits from base.		/// @param BaseTy Base type. Ty is inherits from base.
	/// @param BaseOffset Base offset.		/// @param BaseOffset Base offset.
	/// @param Flags Flags to describe inheritance attribute,		/// @param Flags Flags to describe inheritance attribute,
	/// e.g. private		/// e.g. private
	DIDerivedType createInheritance(DIType Ty, DIType BaseTy,		DIDerivedType createInheritance(DIType Ty, DIType BaseTy,
	uint64_t BaseOffset, unsigned Flags);		uint64_t BaseOffset, unsigned Flags);
	skipping to change at line 194		skipping to change at line 207
	/// createStaticMemberType - Create debugging information entry for a		/// createStaticMemberType - Create debugging information entry for a
	/// C++ static data member.		/// C++ static data member.
	/// @param Scope Member scope.		/// @param Scope Member scope.
	/// @param Name Member name.		/// @param Name Member name.
	/// @param File File where this member is declared.		/// @param File File where this member is declared.
	/// @param LineNo Line number.		/// @param LineNo Line number.
	/// @param Ty Type of the static member.		/// @param Ty Type of the static member.
	/// @param Flags Flags to encode member attribute, e.g. private.		/// @param Flags Flags to encode member attribute, e.g. private.
	/// @param Val Const initializer of the member.		/// @param Val Const initializer of the member.
	DIType createStaticMemberType(DIDescriptor Scope, StringRef Name,		DIDerivedType
	DIFile File, unsigned LineNo, DIType Ty,		createStaticMemberType(DIDescriptor Scope, StringRef Name,
	unsigned Flags, llvm::Value *Val);		DIFile File, unsigned LineNo, DIType Ty,
			unsigned Flags, llvm::Value *Val);
	/// createObjCIVar - Create debugging information entry for Objective-C		/// createObjCIVar - Create debugging information entry for Objective-C
	/// instance variable.		/// instance variable.
	/// @param Name Member name.		/// @param Name Member name.
	/// @param File File where this member is defined.		/// @param File File where this member is defined.
	/// @param LineNo Line number.		/// @param LineNo Line number.
	/// @param SizeInBits Member size.		/// @param SizeInBits Member size.
	/// @param AlignInBits Member alignment.		/// @param AlignInBits Member alignment.
	/// @param OffsetInBits Member offset.		/// @param OffsetInBits Member offset.
	/// @param Flags Flags to encode member attribute, e.g. private		/// @param Flags Flags to encode member attribute, e.g. private
	/// @param Ty Parent type.		/// @param Ty Parent type.
	/// @param PropertyName Name of the Objective C property associated wit h		/// @param PropertyName Name of the Objective C property associated wit h
	/// this ivar.		/// this ivar.
	/// @param PropertyGetterName Name of the Objective C property getter		/// @param PropertyGetterName Name of the Objective C property getter
	/// selector.		/// selector.
	/// @param PropertySetterName Name of the Objective C property setter		/// @param PropertySetterName Name of the Objective C property setter
	/// selector.		/// selector.
	/// @param PropertyAttributes Objective C property attributes.		/// @param PropertyAttributes Objective C property attributes.
	DIType createObjCIVar(StringRef Name, DIFile File,		DIDerivedType createObjCIVar(StringRef Name, DIFile File,
	unsigned LineNo, uint64_t SizeInBits,		unsigned LineNo, uint64_t SizeInBits,
	uint64_t AlignInBits, uint64_t OffsetInBits,		uint64_t AlignInBits, uint64_t OffsetInBit
	unsigned Flags, DIType Ty,		s,
	StringRef PropertyName = StringRef(),		unsigned Flags, DIType Ty,
	StringRef PropertyGetterName = StringRef(),		StringRef PropertyName = StringRef(),
	StringRef PropertySetterName = StringRef(),		StringRef PropertyGetterName = StringRef()
	unsigned PropertyAttributes = 0);		,
			StringRef PropertySetterName = StringRef()
			,
			unsigned PropertyAttributes = 0);
	/// createObjCIVar - Create debugging information entry for Objective-C		/// createObjCIVar - Create debugging information entry for Objective-C
	/// instance variable.		/// instance variable.
	/// @param Name Member name.		/// @param Name Member name.
	/// @param File File where this member is defined.		/// @param File File where this member is defined.
	/// @param LineNo Line number.		/// @param LineNo Line number.
	/// @param SizeInBits Member size.		/// @param SizeInBits Member size.
	/// @param AlignInBits Member alignment.		/// @param AlignInBits Member alignment.
	/// @param OffsetInBits Member offset.		/// @param OffsetInBits Member offset.
	/// @param Flags Flags to encode member attribute, e.g. private		/// @param Flags Flags to encode member attribute, e.g. private
	/// @param Ty Parent type.		/// @param Ty Parent type.
	/// @param PropertyNode Property associated with this ivar.		/// @param PropertyNode Property associated with this ivar.
	DIType createObjCIVar(StringRef Name, DIFile File,		DIDerivedType createObjCIVar(StringRef Name, DIFile File,
	unsigned LineNo, uint64_t SizeInBits,		unsigned LineNo, uint64_t SizeInBits,
	uint64_t AlignInBits, uint64_t OffsetInBits,		uint64_t AlignInBits, uint64_t OffsetInBit
	unsigned Flags, DIType Ty,		s,
	MDNode *PropertyNode);		unsigned Flags, DIType Ty,
			MDNode *PropertyNode);
	/// createObjCProperty - Create debugging information entry for Objecti ve-C		/// createObjCProperty - Create debugging information entry for Objecti ve-C
	/// property.		/// property.
	/// @param Name Property name.		/// @param Name Property name.
	/// @param File File where this property is defined.		/// @param File File where this property is defined.
	/// @param LineNumber Line number.		/// @param LineNumber Line number.
	/// @param GetterName Name of the Objective C property getter selecto r.		/// @param GetterName Name of the Objective C property getter selecto r.
	/// @param SetterName Name of the Objective C property setter selecto r.		/// @param SetterName Name of the Objective C property setter selecto r.
	/// @param PropertyAttributes Objective C property attributes.		/// @param PropertyAttributes Objective C property attributes.
	/// @param Ty Type.		/// @param Ty Type.
	skipping to change at line 272		skipping to change at line 286
	/// @param SizeInBits Member size.		/// @param SizeInBits Member size.
	/// @param AlignInBits Member alignment.		/// @param AlignInBits Member alignment.
	/// @param OffsetInBits Member offset.		/// @param OffsetInBits Member offset.
	/// @param Flags Flags to encode member attribute, e.g. private		/// @param Flags Flags to encode member attribute, e.g. private
	/// @param Elements class members.		/// @param Elements class members.
	/// @param VTableHolder Debug info of the base class that contains vtab le		/// @param VTableHolder Debug info of the base class that contains vtab le
	/// for this type. This is used in		/// for this type. This is used in
	/// DW_AT_containing_type. See DWARF documentation		/// DW_AT_containing_type. See DWARF documentation
	/// for more info.		/// for more info.
	/// @param TemplateParms Template type parameters.		/// @param TemplateParms Template type parameters.
			/// @param UniqueIdentifier A unique identifier for the class.
	DICompositeType createClassType(DIDescriptor Scope, StringRef Name,		DICompositeType createClassType(DIDescriptor Scope, StringRef Name,
	DIFile File, unsigned LineNumber,		DIFile File, unsigned LineNumber,
	uint64_t SizeInBits, uint64_t AlignInBi ts,		uint64_t SizeInBits, uint64_t AlignInBi ts,
	uint64_t OffsetInBits, unsigned Flags,		uint64_t OffsetInBits, unsigned Flags,
	DIType DerivedFrom, DIArray Elements,		DIType DerivedFrom, DIArray Elements,
	MDNode *VTableHolder = 0,		DIType VTableHolder = DIType(),
	MDNode *TemplateParms = 0);		MDNode *TemplateParms = 0,
			StringRef UniqueIdentifier = StringRef(
			));
	/// createStructType - Create debugging information entry for a struct.		/// createStructType - Create debugging information entry for a struct.
	/// @param Scope Scope in which this struct is defined.		/// @param Scope Scope in which this struct is defined.
	/// @param Name Struct name.		/// @param Name Struct name.
	/// @param File File where this member is defined.		/// @param File File where this member is defined.
	/// @param LineNumber Line number.		/// @param LineNumber Line number.
	/// @param SizeInBits Member size.		/// @param SizeInBits Member size.
	/// @param AlignInBits Member alignment.		/// @param AlignInBits Member alignment.
	/// @param Flags Flags to encode member attribute, e.g. private		/// @param Flags Flags to encode member attribute, e.g. private
	/// @param Elements Struct elements.		/// @param Elements Struct elements.
	/// @param RunTimeLang Optional parameter, Objective-C runtime version .		/// @param RunTimeLang Optional parameter, Objective-C runtime version .
			/// @param UniqueIdentifier A unique identifier for the struct.
	DICompositeType createStructType(DIDescriptor Scope, StringRef Name,		DICompositeType createStructType(DIDescriptor Scope, StringRef Name,
	DIFile File, unsigned LineNumber,		DIFile File, unsigned LineNumber,
	uint64_t SizeInBits, uint64_t AlignInB its,		uint64_t SizeInBits, uint64_t AlignInB its,
	unsigned Flags, DIType DerivedFrom,		unsigned Flags, DIType DerivedFrom,
	DIArray Elements, unsigned RunTimeLang = 0,		DIArray Elements, unsigned RunTimeLang = 0,
	MDNode *VTableHolder = 0);		DIType VTableHolder = DIType(),
			StringRef UniqueIdentifier = StringRef
			());
	/// createUnionType - Create debugging information entry for an union.		/// createUnionType - Create debugging information entry for an union.
	/// @param Scope Scope in which this union is defined.		/// @param Scope Scope in which this union is defined.
	/// @param Name Union name.		/// @param Name Union name.
	/// @param File File where this member is defined.		/// @param File File where this member is defined.
	/// @param LineNumber Line number.		/// @param LineNumber Line number.
	/// @param SizeInBits Member size.		/// @param SizeInBits Member size.
	/// @param AlignInBits Member alignment.		/// @param AlignInBits Member alignment.
	/// @param Flags Flags to encode member attribute, e.g. private		/// @param Flags Flags to encode member attribute, e.g. private
	/// @param Elements Union elements.		/// @param Elements Union elements.
	/// @param RunTimeLang Optional parameter, Objective-C runtime version .		/// @param RunTimeLang Optional parameter, Objective-C runtime version .
			/// @param UniqueIdentifier A unique identifier for the union.
	DICompositeType createUnionType(		DICompositeType createUnionType(
	DIDescriptor Scope, StringRef Name, DIFile File, unsigned LineNumbe r,		DIDescriptor Scope, StringRef Name, DIFile File, unsigned LineNumbe r,
	uint64_t SizeInBits, uint64_t AlignInBits, unsigned Flags,		uint64_t SizeInBits, uint64_t AlignInBits, unsigned Flags,
	DIArray Elements, unsigned RunTimeLang = 0);		DIArray Elements, unsigned RunTimeLang = 0,
			StringRef UniqueIdentifier = StringRef());
	/// createTemplateTypeParameter - Create debugging information for temp late		/// createTemplateTypeParameter - Create debugging information for temp late
	/// type parameter.		/// type parameter.
	/// @param Scope Scope in which this type is defined.		/// @param Scope Scope in which this type is defined.
	/// @param Name Type parameter name.		/// @param Name Type parameter name.
	/// @param Ty Parameter type.		/// @param Ty Parameter type.
	/// @param File File where this type parameter is defined.		/// @param File File where this type parameter is defined.
	/// @param LineNo Line number.		/// @param LineNo Line number.
	/// @param ColumnNo Column Number.		/// @param ColumnNo Column Number.
	DITemplateTypeParameter		DITemplateTypeParameter
	createTemplateTypeParameter(DIDescriptor Scope, StringRef Name, DIType Ty,		createTemplateTypeParameter(DIDescriptor Scope, StringRef Name, DIType Ty,
	MDNode *File = 0, unsigned LineNo = 0,		MDNode *File = 0, unsigned LineNo = 0,
	unsigned ColumnNo = 0);		unsigned ColumnNo = 0);
	/// createTemplateValueParameter - Create debugging information for tem plate		/// createTemplateValueParameter - Create debugging information for tem plate
	/// value parameter.		/// value parameter.
	/// @param Scope Scope in which this type is defined.		/// @param Scope Scope in which this type is defined.
	/// @param Name Value parameter name.		/// @param Name Value parameter name.
	/// @param Ty Parameter type.		/// @param Ty Parameter type.
	/// @param Value Constant parameter value.		/// @param Val Constant parameter value.
	/// @param File File where this type parameter is defined.		/// @param File File where this type parameter is defined.
	/// @param LineNo Line number.		/// @param LineNo Line number.
	/// @param ColumnNo Column Number.		/// @param ColumnNo Column Number.
	DITemplateValueParameter		DITemplateValueParameter
	createTemplateValueParameter(DIDescriptor Scope, StringRef Name, DIType		createTemplateValueParameter(DIDescriptor Scope, StringRef Name,
	Ty,		DIType Ty, Value *Val, MDNode *File = 0,
	uint64_t Value,		unsigned LineNo = 0, unsigned ColumnNo = 0
	MDNode *File = 0, unsigned LineNo = 0,		);
	unsigned ColumnNo = 0);
			/// \brief Create debugging information for a template template paramet
			er.
			/// @param Scope Scope in which this type is defined.
			/// @param Name Value parameter name.
			/// @param Ty Parameter type.
			/// @param Val The fully qualified name of the template.
			/// @param File File where this type parameter is defined.
			/// @param LineNo Line number.
			/// @param ColumnNo Column Number.
			DITemplateValueParameter
			createTemplateTemplateParameter(DIDescriptor Scope, StringRef Name,
			DIType Ty, StringRef Val, MDNode *File
			= 0,
			unsigned LineNo = 0, unsigned ColumnNo
			= 0);
			/// \brief Create debugging information for a template parameter pack.
			/// @param Scope Scope in which this type is defined.
			/// @param Name Value parameter name.
			/// @param Ty Parameter type.
			/// @param Val An array of types in the pack.
			/// @param File File where this type parameter is defined.
			/// @param LineNo Line number.
			/// @param ColumnNo Column Number.
			DITemplateValueParameter
			createTemplateParameterPack(DIDescriptor Scope, StringRef Name,
			DIType Ty, DIArray Val, MDNode *File = 0,
			unsigned LineNo = 0, unsigned ColumnNo = 0)
			;
	/// createArrayType - Create debugging information entry for an array.		/// createArrayType - Create debugging information entry for an array.
	/// @param Size Array size.		/// @param Size Array size.
	/// @param AlignInBits Alignment.		/// @param AlignInBits Alignment.
	/// @param Ty Element type.		/// @param Ty Element type.
	/// @param Subscripts Subscripts.		/// @param Subscripts Subscripts.
	DICompositeType createArrayType(uint64_t Size, uint64_t AlignInBits,		DICompositeType createArrayType(uint64_t Size, uint64_t AlignInBits,
	DIType Ty, DIArray Subscripts);		DIType Ty, DIArray Subscripts);
	/// createVectorType - Create debugging information entry for a vector type.		/// createVectorType - Create debugging information entry for a vector type.
	/// @param Size Array size.		/// @param Size Array size.
	/// @param AlignInBits Alignment.		/// @param AlignInBits Alignment.
	/// @param Ty Element type.		/// @param Ty Element type.
	/// @param Subscripts Subscripts.		/// @param Subscripts Subscripts.
	DIType createVectorType(uint64_t Size, uint64_t AlignInBits,		DICompositeType createVectorType(uint64_t Size, uint64_t AlignInBits,
	DIType Ty, DIArray Subscripts);		DIType Ty, DIArray Subscripts);
	/// createEnumerationType - Create debugging information entry for an		/// createEnumerationType - Create debugging information entry for an
	/// enumeration.		/// enumeration.
	/// @param Scope Scope in which this enumeration is defined.		/// @param Scope Scope in which this enumeration is defined.
	/// @param Name Union name.		/// @param Name Union name.
	/// @param File File where this member is defined.		/// @param File File where this member is defined.
	/// @param LineNumber Line number.		/// @param LineNumber Line number.
	/// @param SizeInBits Member size.		/// @param SizeInBits Member size.
	/// @param AlignInBits Member alignment.		/// @param AlignInBits Member alignment.
	/// @param Elements Enumeration elements.		/// @param Elements Enumeration elements.
	/// @param UnderlyingType Underlying type of a C++11/ObjC fixed enum.		/// @param UnderlyingType Underlying type of a C++11/ObjC fixed enum.
			/// @param UniqueIdentifier A unique identifier for the enum.
	DICompositeType createEnumerationType(DIDescriptor Scope, StringRef Nam e,		DICompositeType createEnumerationType(DIDescriptor Scope, StringRef Nam e,
	DIFile File, unsigned LineNumber,		DIFile File, unsigned LineNumber, uint64_t SizeInBits,
	uint64_t SizeInBits,		uint64_t AlignInBits, DIArray Elements, DIType UnderlyingType,
	uint64_t AlignInBits,		StringRef UniqueIdentifier = StringRef());
	DIArray Elements,
	DIType UnderlyingType);
	/// createSubroutineType - Create subroutine type.		/// createSubroutineType - Create subroutine type.
	/// @param File File in which this subroutine is defined.		/// @param File File in which this subroutine is defined.
	/// @param ParameterTypes An array of subroutine parameter types. This		/// @param ParameterTypes An array of subroutine parameter types. This
	/// includes return type at 0th index.		/// includes return type at 0th index.
	DICompositeType createSubroutineType(DIFile File, DIArray ParameterType s);		DICompositeType createSubroutineType(DIFile File, DIArray ParameterType s);
	/// createArtificialType - Create a new DIType with "artificial" flag s et.		/// createArtificialType - Create a new DIType with "artificial" flag s et.
	DIType createArtificialType(DIType Ty);		DIType createArtificialType(DIType Ty);
	/// createObjectPointerType - Create a new DIType with the "object poin ter"		/// createObjectPointerType - Create a new DIType with the "object poin ter"
	/// flag set.		/// flag set.
	DIType createObjectPointerType(DIType Ty);		DIType createObjectPointerType(DIType Ty);
	/// createForwardDecl - Create a temporary forward-declared type.		/// createForwardDecl - Create a temporary forward-declared type.
	DIType createForwardDecl(unsigned Tag, StringRef Name, DIDescriptor Sco		DICompositeType createForwardDecl(unsigned Tag, StringRef Name,
	pe,		DIDescriptor Scope, DIFile F,
	DIFile F, unsigned Line, unsigned RuntimeLang		unsigned Line, unsigned RuntimeLang =
	= 0,		0,
	uint64_t SizeInBits = 0, uint64_t AlignInBits		uint64_t SizeInBits = 0,
	= 0);		uint64_t AlignInBits = 0,
			StringRef UniqueIdentifier = StringRe
			f());
	/// retainType - Retain DIType in a module even if it is not referenced		/// retainType - Retain DIType in a module even if it is not referenced
	/// through debug info anchors.		/// through debug info anchors.
	void retainType(DIType T);		void retainType(DIType T);
	/// createUnspecifiedParameter - Create unspeicified type descriptor		/// createUnspecifiedParameter - Create unspeicified type descriptor
	/// for a subroutine type.		/// for a subroutine type.
	DIDescriptor createUnspecifiedParameter();		DIDescriptor createUnspecifiedParameter();
	/// getOrCreateArray - Get a DIArray, create one if required.		/// getOrCreateArray - Get a DIArray, create one if required.
	skipping to change at line 462		skipping to change at line 509
	/// @param Tag Dwarf TAG. Usually DW_TAG_auto_variable or		/// @param Tag Dwarf TAG. Usually DW_TAG_auto_variable or
	/// DW_TAG_arg_variable.		/// DW_TAG_arg_variable.
	/// @param Scope Variable scope.		/// @param Scope Variable scope.
	/// @param Name Variable name.		/// @param Name Variable name.
	/// @param File File where this variable is defined.		/// @param File File where this variable is defined.
	/// @param LineNo Line number.		/// @param LineNo Line number.
	/// @param Ty Variable Type		/// @param Ty Variable Type
	/// @param AlwaysPreserve Boolean. Set to true if debug info for this		/// @param AlwaysPreserve Boolean. Set to true if debug info for this
	/// variable should be preserved in optimized bui ld.		/// variable should be preserved in optimized bui ld.
	/// @param Flags Flags, e.g. artificial variable.		/// @param Flags Flags, e.g. artificial variable.
	/// @param ArgNo If this variable is an arugment then this argume nt's		/// @param ArgNo If this variable is an argument then this argume nt's
	/// number. 1 indicates 1st argument.		/// number. 1 indicates 1st argument.
	DIVariable createLocalVariable(unsigned Tag, DIDescriptor Scope,		DIVariable createLocalVariable(unsigned Tag, DIDescriptor Scope,
	StringRef Name,		StringRef Name,
	DIFile File, unsigned LineNo,		DIFile File, unsigned LineNo,
	DIType Ty, bool AlwaysPreserve = false,		DIType Ty, bool AlwaysPreserve = false,
	unsigned Flags = 0,		unsigned Flags = 0,
	unsigned ArgNo = 0);		unsigned ArgNo = 0);
	/// createComplexVariable - Create a new descriptor for the specified		/// createComplexVariable - Create a new descriptor for the specified
	/// variable which has a complex address expression for its address.		/// variable which has a complex address expression for its address.
	/// @param Tag Dwarf TAG. Usually DW_TAG_auto_variable or		/// @param Tag Dwarf TAG. Usually DW_TAG_auto_variable or
	/// DW_TAG_arg_variable.		/// DW_TAG_arg_variable.
	/// @param Scope Variable scope.		/// @param Scope Variable scope.
	/// @param Name Variable name.		/// @param Name Variable name.
	/// @param F File where this variable is defined.		/// @param F File where this variable is defined.
	/// @param LineNo Line number.		/// @param LineNo Line number.
	/// @param Ty Variable Type		/// @param Ty Variable Type
	/// @param Addr An array of complex address operations.		/// @param Addr An array of complex address operations.
	/// @param ArgNo If this variable is an arugment then this argume nt's		/// @param ArgNo If this variable is an argument then this argume nt's
	/// number. 1 indicates 1st argument.		/// number. 1 indicates 1st argument.
	DIVariable createComplexVariable(unsigned Tag, DIDescriptor Scope,		DIVariable createComplexVariable(unsigned Tag, DIDescriptor Scope,
	StringRef Name, DIFile F, unsigned Lin eNo,		StringRef Name, DIFile F, unsigned Lin eNo,
	DIType Ty, ArrayRef<Value *> Addr,		DIType Ty, ArrayRef<Value *> Addr,
	unsigned ArgNo = 0);		unsigned ArgNo = 0);
	/// createFunction - Create a new descriptor for the specified subprogr am.		/// createFunction - Create a new descriptor for the specified subprogr am.
	/// See comments in DISubprogram for descriptions of these fields.		/// See comments in DISubprogram for descriptions of these fields.
	/// @param Scope Function scope.		/// @param Scope Function scope.
	/// @param Name Function name.		/// @param Name Function name.
	skipping to change at line 507		skipping to change at line 554
	/// @param isDefinition True if this is a function definition.		/// @param isDefinition True if this is a function definition.
	/// @param ScopeLine Set to the beginning of the scope this starts		/// @param ScopeLine Set to the beginning of the scope this starts
	/// @param Flags e.g. is this function prototyped or not.		/// @param Flags e.g. is this function prototyped or not.
	/// This flags are used to emit dwarf attributes.		/// This flags are used to emit dwarf attributes.
	/// @param isOptimized True if optimization is ON.		/// @param isOptimized True if optimization is ON.
	/// @param Fn llvm::Function pointer.		/// @param Fn llvm::Function pointer.
	/// @param TParam Function template parameters.		/// @param TParam Function template parameters.
	DISubprogram createFunction(DIDescriptor Scope, StringRef Name,		DISubprogram createFunction(DIDescriptor Scope, StringRef Name,
	StringRef LinkageName,		StringRef LinkageName,
	DIFile File, unsigned LineNo,		DIFile File, unsigned LineNo,
	DIType Ty, bool isLocalToUnit,		DICompositeType Ty, bool isLocalToUnit,
			bool isDefinition,
			unsigned ScopeLine,
			unsigned Flags = 0,
			bool isOptimized = false,
			Function *Fn = 0,
			MDNode *TParam = 0,
			MDNode *Decl = 0);
			/// FIXME: this is added for dragonegg. Once we update dragonegg
			/// to call resolve function, this will be removed.
			DISubprogram createFunction(DIScopeRef Scope, StringRef Name,
			StringRef LinkageName,
			DIFile File, unsigned LineNo,
			DICompositeType Ty, bool isLocalToUnit,
	bool isDefinition,		bool isDefinition,
	unsigned ScopeLine,		unsigned ScopeLine,
	unsigned Flags = 0,		unsigned Flags = 0,
	bool isOptimized = false,		bool isOptimized = false,
	Function *Fn = 0,		Function *Fn = 0,
	MDNode *TParam = 0,		MDNode *TParam = 0,
	MDNode *Decl = 0);		MDNode *Decl = 0);
	/// createMethod - Create a new descriptor for the specified C++ method .		/// createMethod - Create a new descriptor for the specified C++ method .
	/// See comments in DISubprogram for descriptions of these fields.		/// See comments in DISubprogram for descriptions of these fields.
	skipping to change at line 538		skipping to change at line 599
	/// @param VTableIndex Index no of this method in virtual table.		/// @param VTableIndex Index no of this method in virtual table.
	/// @param VTableHolder Type that holds vtable.		/// @param VTableHolder Type that holds vtable.
	/// @param Flags e.g. is this function prototyped or not.		/// @param Flags e.g. is this function prototyped or not.
	/// This flags are used to emit dwarf attributes.		/// This flags are used to emit dwarf attributes.
	/// @param isOptimized True if optimization is ON.		/// @param isOptimized True if optimization is ON.
	/// @param Fn llvm::Function pointer.		/// @param Fn llvm::Function pointer.
	/// @param TParam Function template parameters.		/// @param TParam Function template parameters.
	DISubprogram createMethod(DIDescriptor Scope, StringRef Name,		DISubprogram createMethod(DIDescriptor Scope, StringRef Name,
	StringRef LinkageName,		StringRef LinkageName,
	DIFile File, unsigned LineNo,		DIFile File, unsigned LineNo,
	DIType Ty, bool isLocalToUnit,		DICompositeType Ty, bool isLocalToUnit,
	bool isDefinition,		bool isDefinition,
	unsigned Virtuality = 0, unsigned VTableIndex = 0,		unsigned Virtuality = 0, unsigned VTableIndex = 0,
	MDNode *VTableHolder = 0,		DIType VTableHolder = DIType(),
	unsigned Flags = 0,		unsigned Flags = 0,
	bool isOptimized = false,		bool isOptimized = false,
	Function *Fn = 0,		Function *Fn = 0,
	MDNode *TParam = 0);		MDNode *TParam = 0);
	/// createNameSpace - This creates new descriptor for a namespace		/// createNameSpace - This creates new descriptor for a namespace
	/// with the specified parent scope.		/// with the specified parent scope.
	/// @param Scope Namespace scope		/// @param Scope Namespace scope
	/// @param Name Name of this namespace		/// @param Name Name of this namespace
	/// @param File Source file		/// @param File Source file
	skipping to change at line 577		skipping to change at line 638
	/// @param File Source file		/// @param File Source file
	/// @param Line Line number		/// @param Line Line number
	/// @param Col Column number		/// @param Col Column number
	DILexicalBlock createLexicalBlock(DIDescriptor Scope, DIFile File,		DILexicalBlock createLexicalBlock(DIDescriptor Scope, DIFile File,
	unsigned Line, unsigned Col);		unsigned Line, unsigned Col);
	/// \brief Create a descriptor for an imported module.		/// \brief Create a descriptor for an imported module.
	/// @param Context The scope this module is imported into		/// @param Context The scope this module is imported into
	/// @param NS The namespace being imported here		/// @param NS The namespace being imported here
	/// @param Line Line number		/// @param Line Line number
	DIImportedModule createImportedModule(DIScope Context, DINameSpace NS,		DIImportedEntity createImportedModule(DIScope Context, DINameSpace NS,
	unsigned Line);		unsigned Line,
			StringRef Name = StringRef());
			/// \brief Create a descriptor for an imported module.
			/// @param Context The scope this module is imported into
			/// @param NS An aliased namespace
			/// @param Line Line number
			DIImportedEntity createImportedModule(DIScope Context, DIImportedEntity
			NS,
			unsigned Line, StringRef Name);
			/// \brief Create a descriptor for an imported function.
			/// @param Context The scope this module is imported into
			/// @param Decl The declaration (or definition) of a function, type, or
			/// variable
			/// @param Line Line number
			DIImportedEntity createImportedDeclaration(DIScope Context,
			DIDescriptor Decl,
			unsigned Line);
	/// insertDeclare - Insert a new llvm.dbg.declare intrinsic call.		/// insertDeclare - Insert a new llvm.dbg.declare intrinsic call.
	/// @param Storage llvm::Value of the variable		/// @param Storage llvm::Value of the variable
	/// @param VarInfo Variable's debug info descriptor.		/// @param VarInfo Variable's debug info descriptor.
	/// @param InsertAtEnd Location for the new intrinsic.		/// @param InsertAtEnd Location for the new intrinsic.
	Instruction *insertDeclare(llvm::Value *Storage, DIVariable VarInfo,		Instruction *insertDeclare(llvm::Value *Storage, DIVariable VarInfo,
	BasicBlock *InsertAtEnd);		BasicBlock *InsertAtEnd);
	/// insertDeclare - Insert a new llvm.dbg.declare intrinsic call.		/// insertDeclare - Insert a new llvm.dbg.declare intrinsic call.
	/// @param Storage llvm::Value of the variable		/// @param Storage llvm::Value of the variable
End of changes. 33 change blocks.
	58 lines changed or deleted		146 lines changed or added

	DIContext.h		DIContext.h
	skipping to change at line 24		skipping to change at line 24
	#ifndef LLVM_DEBUGINFO_DICONTEXT_H		#ifndef LLVM_DEBUGINFO_DICONTEXT_H
	#define LLVM_DEBUGINFO_DICONTEXT_H		#define LLVM_DEBUGINFO_DICONTEXT_H
	#include "llvm/ADT/DenseMap.h"		#include "llvm/ADT/DenseMap.h"
	#include "llvm/ADT/SmallString.h"		#include "llvm/ADT/SmallString.h"
	#include "llvm/ADT/SmallVector.h"		#include "llvm/ADT/SmallVector.h"
	#include "llvm/ADT/StringRef.h"		#include "llvm/ADT/StringRef.h"
	#include "llvm/Object/ObjectFile.h"		#include "llvm/Object/ObjectFile.h"
	#include "llvm/Object/RelocVisitor.h"		#include "llvm/Object/RelocVisitor.h"
			#include "llvm/Support/Casting.h"
	#include "llvm/Support/DataTypes.h"		#include "llvm/Support/DataTypes.h"
	namespace llvm {		namespace llvm {
	class raw_ostream;		class raw_ostream;
	/// DILineInfo - a format-neutral container for source line information.		/// DILineInfo - a format-neutral container for source line information.
	class DILineInfo {		class DILineInfo {
	SmallString<16> FileName;		SmallString<16> FileName;
	SmallString<16> FunctionName;		SmallString<16> FunctionName;
	uint32_t Line;		uint32_t Line;
	uint32_t Column;		uint32_t Column;
	public:		public:
	DILineInfo()		DILineInfo()
	: FileName("<invalid>"), FunctionName("<invalid>"),		: FileName("<invalid>"), FunctionName("<invalid>"),
	Line(0), Column(0) {}		Line(0), Column(0) {}
	DILineInfo(const SmallString<16> &fileName,		DILineInfo(StringRef fileName, StringRef functionName, uint32_t line,
	const SmallString<16> &functionName,		uint32_t column)
	uint32_t line, uint32_t column)		: FileName(fileName), FunctionName(functionName), Line(line),
	: FileName(fileName), FunctionName(functionName),		Column(column) {}
	Line(line), Column(column) {}
	const char *getFileName() { return FileName.c_str(); }		const char *getFileName() { return FileName.c_str(); }
	const char *getFunctionName() { return FunctionName.c_str(); }		const char *getFunctionName() { return FunctionName.c_str(); }
	uint32_t getLine() const { return Line; }		uint32_t getLine() const { return Line; }
	uint32_t getColumn() const { return Column; }		uint32_t getColumn() const { return Column; }
	bool operator==(const DILineInfo &RHS) const {		bool operator==(const DILineInfo &RHS) const {
	return Line == RHS.Line && Column == RHS.Column &&		return Line == RHS.Line && Column == RHS.Column &&
	FileName.equals(RHS.FileName) &&		FileName.equals(RHS.FileName) &&
	FunctionName.equals(RHS.FunctionName);		FunctionName.equals(RHS.FunctionName);
	skipping to change at line 107		skipping to change at line 107
	/// Selects which debug sections get dumped.		/// Selects which debug sections get dumped.
	enum DIDumpType {		enum DIDumpType {
	DIDT_Null,		DIDT_Null,
	DIDT_All,		DIDT_All,
	DIDT_Abbrev,		DIDT_Abbrev,
	DIDT_AbbrevDwo,		DIDT_AbbrevDwo,
	DIDT_Aranges,		DIDT_Aranges,
	DIDT_Frames,		DIDT_Frames,
	DIDT_Info,		DIDT_Info,
	DIDT_InfoDwo,		DIDT_InfoDwo,
			DIDT_Types,
	DIDT_Line,		DIDT_Line,
			DIDT_Loc,
	DIDT_Ranges,		DIDT_Ranges,
	DIDT_Pubnames,		DIDT_Pubnames,
			DIDT_Pubtypes,
			DIDT_GnuPubnames,
			DIDT_GnuPubtypes,
	DIDT_Str,		DIDT_Str,
	DIDT_StrDwo,		DIDT_StrDwo,
	DIDT_StrOffsetsDwo		DIDT_StrOffsetsDwo
	};		};
	// In place of applying the relocations to the data we've read from disk we use		// In place of applying the relocations to the data we've read from disk we use
	// a separate mapping table to the side and checking that at locations in t he		// a separate mapping table to the side and checking that at locations in t he
	// dwarf where we expect relocated values. This adds a bit of complexity to the		// dwarf where we expect relocated values. This adds a bit of complexity to the
	// dwarf parsing/extraction at the benefit of not allocating memory for the		// dwarf parsing/extraction at the benefit of not allocating memory for the
	// entire size of the debug info sections.		// entire size of the debug info sections.
	typedef DenseMap<uint64_t, std::pair<uint8_t, int64_t> > RelocAddrMap;		typedef DenseMap<uint64_t, std::pair<uint8_t, int64_t> > RelocAddrMap;
	class DIContext {		class DIContext {
	public:		public:
			enum DIContextKind {
			CK_DWARF
			};
			DIContextKind getKind() const { return Kind; }
			DIContext(DIContextKind K) : Kind(K) {}
	virtual ~DIContext();		virtual ~DIContext();
	/// getDWARFContext - get a context for binary DWARF data.		/// getDWARFContext - get a context for binary DWARF data.
	static DIContext *getDWARFContext(object::ObjectFile *);		static DIContext *getDWARFContext(object::ObjectFile *);
	virtual void dump(raw_ostream &OS, DIDumpType DumpType = DIDT_All) = 0;		virtual void dump(raw_ostream &OS, DIDumpType DumpType = DIDT_All) = 0;
	virtual DILineInfo getLineInfoForAddress(uint64_t Address,		virtual DILineInfo getLineInfoForAddress(uint64_t Address,
	DILineInfoSpecifier Specifier = DILineInfoSpecifier()) = 0;		DILineInfoSpecifier Specifier = DILineInfoSpecifier()) = 0;
	virtual DILineInfoTable getLineInfoForAddressRange(uint64_t Address,		virtual DILineInfoTable getLineInfoForAddressRange(uint64_t Address,
	uint64_t Size, DILineInfoSpecifier Specifier = DILineInfoSpecifier()) = 0;		uint64_t Size, DILineInfoSpecifier Specifier = DILineInfoSpecifier()) = 0;
	virtual DIInliningInfo getInliningInfoForAddress(uint64_t Address,		virtual DIInliningInfo getInliningInfoForAddress(uint64_t Address,
	DILineInfoSpecifier Specifier = DILineInfoSpecifier()) = 0;		DILineInfoSpecifier Specifier = DILineInfoSpecifier()) = 0;
			private:
			const DIContextKind Kind;
	};		};
	}		}
	#endif		#endif
End of changes. 7 change blocks.
	5 lines changed or deleted		18 lines changed or added

	DWARFFormValue.h		DWARFFormValue.h
	skipping to change at line 13		skipping to change at line 13
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_DEBUGINFO_DWARFFORMVALUE_H		#ifndef LLVM_DEBUGINFO_DWARFFORMVALUE_H
	#define LLVM_DEBUGINFO_DWARFFORMVALUE_H		#define LLVM_DEBUGINFO_DWARFFORMVALUE_H
			#include "llvm/ADT/ArrayRef.h"
			#include "llvm/ADT/Optional.h"
	#include "llvm/Support/DataExtractor.h"		#include "llvm/Support/DataExtractor.h"
	namespace llvm {		namespace llvm {
	class DWARFCompileUnit;		class DWARFUnit;
	class raw_ostream;		class raw_ostream;
	class DWARFFormValue {		class DWARFFormValue {
	public:		public:
			enum FormClass {
			FC_Unknown,
			FC_Address,
			FC_Block,
			FC_Constant,
			FC_String,
			FC_Flag,
			FC_Reference,
			FC_Indirect,
			FC_SectionOffset,
			FC_Exprloc
			};
			private:
	struct ValueType {		struct ValueType {
	ValueType() : data(NULL) {		ValueType() : data(NULL) {
	uval = 0;		uval = 0;
	}		}
	union {		union {
	uint64_t uval;		uint64_t uval;
	int64_t sval;		int64_t sval;
	const char* cstr;		const char* cstr;
	};		};
	const uint8_t* data;		const uint8_t* data;
	};		};
	enum {
	eValueTypeInvalid = 0,
	eValueTypeUnsigned,
	eValueTypeSigned,
	eValueTypeCStr,
	eValueTypeBlock
	};
	private:
	uint16_t Form; // Form for this value.		uint16_t Form; // Form for this value.
	ValueType Value; // Contains all data for the form.		ValueType Value; // Contains all data for the form.
	public:		public:
	DWARFFormValue(uint16_t form = 0) : Form(form) {}		DWARFFormValue(uint16_t Form = 0) : Form(Form) {}
	uint16_t getForm() const { return Form; }		uint16_t getForm() const { return Form; }
	const ValueType& value() const { return Value; }		bool isFormClass(FormClass FC) const;
	void dump(raw_ostream &OS, const DWARFCompileUnit* cu) const;
			void dump(raw_ostream &OS, const DWARFUnit *U) const;
	bool extractValue(DataExtractor data, uint32_t *offset_ptr,		bool extractValue(DataExtractor data, uint32_t *offset_ptr,
	const DWARFCompileUnit *cu);		const DWARFUnit *u);
	bool isInlinedCStr() const {		bool isInlinedCStr() const {
	return Value.data != NULL && Value.data == (const uint8_t*)Value.cstr;		return Value.data != NULL && Value.data == (const uint8_t*)Value.cstr;
	}		}
	const uint8_t *BlockData() const;
	uint64_t getReference(const DWARFCompileUnit* cu) const;
	/// Resolve any compile unit specific references so that we don't need		/// getAsFoo functions below return the extracted value as Foo if only
	/// the compile unit at a later time in order to work with the form		/// DWARFFormValue has form class is suitable for representing Foo.
	/// value.		Optional<uint64_t> getAsReference(const DWARFUnit *U) const;
	bool resolveCompileUnitReferences(const DWARFCompileUnit* cu);		Optional<uint64_t> getAsUnsignedConstant() const;
	uint64_t getUnsigned() const { return Value.uval; }		Optional<const char *> getAsCString(const DWARFUnit *U) const;
	int64_t getSigned() const { return Value.sval; }		Optional<uint64_t> getAsAddress(const DWARFUnit *U) const;
	const char *getAsCString(const DataExtractor *debug_str_data_ptr) const;		Optional<uint64_t> getAsSectionOffset() const;
	const char *getIndirectCString(const DataExtractor *,
	const DataExtractor *) const;
	uint64_t getIndirectAddress(const DataExtractor *,
	const DWARFCompileUnit *) const;
	bool skipValue(DataExtractor debug_info_data, uint32_t *offset_ptr,		bool skipValue(DataExtractor debug_info_data, uint32_t *offset_ptr,
	const DWARFCompileUnit *cu) const;		const DWARFUnit *u) const;
	static bool skipValue(uint16_t form, DataExtractor debug_info_data,		static bool skipValue(uint16_t form, DataExtractor debug_info_data,
	uint32_t *offset_ptr, const DWARFCompileUnit *cu);		uint32_t *offset_ptr, const DWARFUnit *u);
	static bool isBlockForm(uint16_t form);
	static bool isDataForm(uint16_t form);		static ArrayRef<uint8_t> getFixedFormSizes(uint8_t AddrSize,
	static const uint8_t *getFixedFormSizes(uint8_t AddrSize, uint16_t Versio		uint16_t Version);
	n);
	};		};
	}		}
	#endif		#endif
End of changes. 11 change blocks.
	33 lines changed or deleted		35 lines changed or added

	DataLayout.h		DataLayout.h
	skipping to change at line 239		skipping to change at line 239
	bool fitsInLegalInteger(unsigned Width) const {		bool fitsInLegalInteger(unsigned Width) const {
	for (unsigned i = 0, e = (unsigned)LegalIntWidths.size(); i != e; ++i)		for (unsigned i = 0, e = (unsigned)LegalIntWidths.size(); i != e; ++i)
	if (Width <= LegalIntWidths[i])		if (Width <= LegalIntWidths[i])
	return true;		return true;
	return false;		return false;
	}		}
	/// Layout pointer alignment		/// Layout pointer alignment
	/// FIXME: The defaults need to be removed once all of		/// FIXME: The defaults need to be removed once all of
	/// the backends/clients are updated.		/// the backends/clients are updated.
	unsigned getPointerABIAlignment(unsigned AS = 0) const {		unsigned getPointerABIAlignment(unsigned AS = 0) const {
	DenseMap<unsigned, PointerAlignElem>::const_iterator val = Pointers.fin d(AS);		DenseMap<unsigned, PointerAlignElem>::const_iterator val = Pointers.fin d(AS);
	if (val == Pointers.end()) {		if (val == Pointers.end()) {
	val = Pointers.find(0);		val = Pointers.find(0);
	}		}
	return val->second.ABIAlign;		return val->second.ABIAlign;
	}		}
	/// Return target's alignment for stack-based pointers		/// Return target's alignment for stack-based pointers
	/// FIXME: The defaults need to be removed once all of		/// FIXME: The defaults need to be removed once all of
	/// the backends/clients are updated.		/// the backends/clients are updated.
	unsigned getPointerPrefAlignment(unsigned AS = 0) const {		unsigned getPointerPrefAlignment(unsigned AS = 0) const {
	DenseMap<unsigned, PointerAlignElem>::const_iterator val = Pointers.fin d(AS);		DenseMap<unsigned, PointerAlignElem>::const_iterator val = Pointers.fin d(AS);
	if (val == Pointers.end()) {		if (val == Pointers.end()) {
	val = Pointers.find(0);		val = Pointers.find(0);
	}		}
	return val->second.PrefAlign;		return val->second.PrefAlign;
	}		}
	/// Layout pointer size		/// Layout pointer size
	/// FIXME: The defaults need to be removed once all of		/// FIXME: The defaults need to be removed once all of
	/// the backends/clients are updated.		/// the backends/clients are updated.
	unsigned getPointerSize(unsigned AS = 0) const {		unsigned getPointerSize(unsigned AS = 0) const {
	DenseMap<unsigned, PointerAlignElem>::const_iterator val = Pointers.fin d(AS);		DenseMap<unsigned, PointerAlignElem>::const_iterator val = Pointers.fin d(AS);
	if (val == Pointers.end()) {		if (val == Pointers.end()) {
	val = Pointers.find(0);		val = Pointers.find(0);
	}		}
	return val->second.TypeBitWidth;		return val->second.TypeBitWidth;
	}		}
	/// Layout pointer size, in bits		/// Layout pointer size, in bits
	/// FIXME: The defaults need to be removed once all of		/// FIXME: The defaults need to be removed once all of
	/// the backends/clients are updated.		/// the backends/clients are updated.
	unsigned getPointerSizeInBits(unsigned AS = 0) const {		unsigned getPointerSizeInBits(unsigned AS = 0) const {
	return getPointerSize(AS) * 8;		return getPointerSize(AS) * 8;
	}		}
			/// Layout pointer size, in bits, based on the type. If this function is
			/// called with a pointer type, then the type size of the pointer is retu
			rned.
			/// If this function is called with a vector of pointers, then the type s
			ize
			/// of the pointer is returned. This should only be called with a pointe
			r or
			/// vector of pointers.
			unsigned getPointerTypeSizeInBits(Type *) const;
			unsigned getPointerTypeSize(Type *Ty) const {
			return getPointerTypeSizeInBits(Ty) / 8;
			}
	/// Size examples:		/// Size examples:
	///		///
	/// Type SizeInBits StoreSizeInBits AllocSizeInBits[*]		/// Type SizeInBits StoreSizeInBits AllocSizeInBits[*]
	/// ---- ---------- --------------- ---------------		/// ---- ---------- --------------- ---------------
	/// i1 1 8 8		/// i1 1 8 8
	/// i8 8 8 8		/// i8 8 8 8
	/// i19 19 24 32		/// i19 19 24 32
	/// i32 32 32 32		/// i32 32 32 32
	/// i100 100 104 128		/// i100 100 104 128
	/// i128 128 128 128		/// i128 128 128 128
	skipping to change at line 358		skipping to change at line 371
	/// getIntPtrType - Return an integer (vector of integer) type with size at		/// getIntPtrType - Return an integer (vector of integer) type with size at
	/// least as big as that of a pointer of the given pointer (vector of poi nter)		/// least as big as that of a pointer of the given pointer (vector of poi nter)
	/// type.		/// type.
	Type *getIntPtrType(Type *) const;		Type *getIntPtrType(Type *) const;
	/// getSmallestLegalIntType - Return the smallest integer type with size at		/// getSmallestLegalIntType - Return the smallest integer type with size at
	/// least as big as Width bits.		/// least as big as Width bits.
	Type *getSmallestLegalIntType(LLVMContext &C, unsigned Width = 0) const;		Type *getSmallestLegalIntType(LLVMContext &C, unsigned Width = 0) const;
			/// getLargestLegalIntType - Return the largest legal integer type, or nu
			ll if
			/// none are set.
			Type *getLargestLegalIntType(LLVMContext &C) const {
			unsigned LargestSize = getLargestLegalIntTypeSize();
			return (LargestSize == 0) ? 0 : Type::getIntNTy(C, LargestSize);
			}
			/// getLargestLegalIntType - Return the size of largest legal integer typ
			e
			/// size, or 0 if none are set.
			unsigned getLargestLegalIntTypeSize() const;
	/// getIndexedOffset - return the offset from the beginning of the type f or		/// getIndexedOffset - return the offset from the beginning of the type f or
	/// the specified indices. This is used to implement getelementptr.		/// the specified indices. This is used to implement getelementptr.
	uint64_t getIndexedOffset(Type *Ty, ArrayRef<Value *> Indices) const;		uint64_t getIndexedOffset(Type *Ty, ArrayRef<Value *> Indices) const;
	/// getStructLayout - Return a StructLayout object, indicating the alignm ent		/// getStructLayout - Return a StructLayout object, indicating the alignm ent
	/// of the struct, its size, and the offsets of its fields. Note that th is		/// of the struct, its size, and the offsets of its fields. Note that th is
	/// information is lazily cached.		/// information is lazily cached.
	const StructLayout *getStructLayout(StructType *Ty) const;		const StructLayout *getStructLayout(StructType *Ty) const;
	/// getPreferredAlignment - Return the preferred alignment of the specifi ed		/// getPreferredAlignment - Return the preferred alignment of the specifi ed
	skipping to change at line 439		skipping to change at line 463
	};		};
	// The implementation of this method is provided inline as it is particular ly		// The implementation of this method is provided inline as it is particular ly
	// well suited to constant folding when called on a specific Type subclass.		// well suited to constant folding when called on a specific Type subclass.
	inline uint64_t DataLayout::getTypeSizeInBits(Type *Ty) const {		inline uint64_t DataLayout::getTypeSizeInBits(Type *Ty) const {
	assert(Ty->isSized() && "Cannot getTypeInfo() on a type that is unsized!" );		assert(Ty->isSized() && "Cannot getTypeInfo() on a type that is unsized!" );
	switch (Ty->getTypeID()) {		switch (Ty->getTypeID()) {
	case Type::LabelTyID:		case Type::LabelTyID:
	return getPointerSizeInBits(0);		return getPointerSizeInBits(0);
	case Type::PointerTyID:		case Type::PointerTyID:
	return getPointerSizeInBits(cast<PointerType>(Ty)->getAddressSpace());		return getPointerSizeInBits(Ty->getPointerAddressSpace());
	case Type::ArrayTyID: {		case Type::ArrayTyID: {
	ArrayType *ATy = cast<ArrayType>(Ty);		ArrayType *ATy = cast<ArrayType>(Ty);
	return ATy->getNumElements() *		return ATy->getNumElements() *
	getTypeAllocSizeInBits(ATy->getElementType());		getTypeAllocSizeInBits(ATy->getElementType());
	}		}
	case Type::StructTyID:		case Type::StructTyID:
	// Get the layout annotation... which is lazily created on demand.		// Get the layout annotation... which is lazily created on demand.
	return getStructLayout(cast<StructType>(Ty))->getSizeInBits();		return getStructLayout(cast<StructType>(Ty))->getSizeInBits();
	case Type::IntegerTyID:		case Type::IntegerTyID:
	return cast<IntegerType>(Ty)->getBitWidth();		return Ty->getIntegerBitWidth();
	case Type::HalfTyID:		case Type::HalfTyID:
	return 16;		return 16;
	case Type::FloatTyID:		case Type::FloatTyID:
	return 32;		return 32;
	case Type::DoubleTyID:		case Type::DoubleTyID:
	case Type::X86_MMXTyID:		case Type::X86_MMXTyID:
	return 64;		return 64;
	case Type::PPC_FP128TyID:		case Type::PPC_FP128TyID:
	case Type::FP128TyID:		case Type::FP128TyID:
	return 128;		return 128;
End of changes. 8 change blocks.
	5 lines changed or deleted		34 lines changed or added

	DataTypes.h		DataTypes.h
	skipping to change at line 30		skipping to change at line 30
	|* *|		|* *|
	|*===---------------------------------------------------------------------- ===*/		|*===---------------------------------------------------------------------- ===*/
	/* Please leave this file C-compatible. */		/* Please leave this file C-compatible. */
	/* Please keep this file in sync with DataTypes.h.cmake */		/* Please keep this file in sync with DataTypes.h.cmake */
	#ifndef SUPPORT_DATATYPES_H		#ifndef SUPPORT_DATATYPES_H
	#define SUPPORT_DATATYPES_H		#define SUPPORT_DATATYPES_H
	#define HAVE_SYS_TYPES_H 1
	#define HAVE_INTTYPES_H 1		#define HAVE_INTTYPES_H 1
	#define HAVE_STDINT_H 1		#define HAVE_STDINT_H 1
	#define HAVE_UINT64_T 1		#define HAVE_UINT64_T 1
	/* #undef HAVE_U_INT64_T */		/* #undef HAVE_U_INT64_T */
	#ifdef __cplusplus		#ifdef __cplusplus
	#include <cmath>		#include <cmath>
	#else		#else
	#include <math.h>		#include <math.h>
	#endif		#endif
	skipping to change at line 58		skipping to change at line 57
	#if !defined(__STDC_LIMIT_MACROS)		#if !defined(__STDC_LIMIT_MACROS)
	# error "Must #define __STDC_LIMIT_MACROS before #including Support/DataTyp es.h"		# error "Must #define __STDC_LIMIT_MACROS before #including Support/DataTyp es.h"
	#endif		#endif
	#if !defined(__STDC_CONSTANT_MACROS)		#if !defined(__STDC_CONSTANT_MACROS)
	# error "Must #define __STDC_CONSTANT_MACROS before " \		# error "Must #define __STDC_CONSTANT_MACROS before " \
	"#including Support/DataTypes.h"		"#including Support/DataTypes.h"
	#endif		#endif
	/* Note that <inttypes.h> includes <stdint.h>, if this is a C99 system. */		/* Note that <inttypes.h> includes <stdint.h>, if this is a C99 system. */
	#ifdef HAVE_SYS_TYPES_H
	#include <sys/types.h>		#include <sys/types.h>
	#endif
	#ifdef HAVE_INTTYPES_H		#ifdef HAVE_INTTYPES_H
	#include <inttypes.h>		#include <inttypes.h>
	#endif		#endif
	#ifdef HAVE_STDINT_H		#ifdef HAVE_STDINT_H
	#include <stdint.h>		#include <stdint.h>
	#endif		#endif
	#ifdef _AIX		#ifdef _AIX
	skipping to change at line 102		skipping to change at line 99
	#include <math.h>		#include <math.h>
	#endif		#endif
	typedef __int64 int64_t;		typedef __int64 int64_t;
	typedef unsigned __int64 uint64_t;		typedef unsigned __int64 uint64_t;
	typedef signed int int32_t;		typedef signed int int32_t;
	typedef unsigned int uint32_t;		typedef unsigned int uint32_t;
	typedef short int16_t;		typedef short int16_t;
	typedef unsigned short uint16_t;		typedef unsigned short uint16_t;
	typedef signed char int8_t;		typedef signed char int8_t;
	typedef unsigned char uint8_t;		typedef unsigned char uint8_t;
	typedef signed int ssize_t;		#if defined(_WIN64)
			typedef signed __int64 ssize_t;
			#else
			typedef signed int ssize_t;
			#endif
	#ifndef INT8_MAX		#ifndef INT8_MAX
	# define INT8_MAX 127		# define INT8_MAX 127
	#endif		#endif
	#ifndef INT8_MIN		#ifndef INT8_MIN
	# define INT8_MIN -128		# define INT8_MIN -128
	#endif		#endif
	#ifndef UINT8_MAX		#ifndef UINT8_MAX
	# define UINT8_MAX 255		# define UINT8_MAX 255
	#endif		#endif
	#ifndef INT16_MAX		#ifndef INT16_MAX
End of changes. 4 change blocks.
	4 lines changed or deleted		6 lines changed or added

	Debug.h		Debug.h
	skipping to change at line 29		skipping to change at line 29
	// foo class.		// foo class.
	//		//
	// When compiling without assertions, the -debug-* options and all code in		// When compiling without assertions, the -debug-* options and all code in
	// DEBUG() statements disappears, so it does not affect the runtime of the code.		// DEBUG() statements disappears, so it does not affect the runtime of the code.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_SUPPORT_DEBUG_H		#ifndef LLVM_SUPPORT_DEBUG_H
	#define LLVM_SUPPORT_DEBUG_H		#define LLVM_SUPPORT_DEBUG_H
	namespace llvm {		#include "llvm/Support/raw_ostream.h"
	class raw_ostream;		namespace llvm {
	/// DEBUG_TYPE macro - Files can specify a DEBUG_TYPE as a string, which ca uses		/// DEBUG_TYPE macro - Files can specify a DEBUG_TYPE as a string, which ca uses
	/// all of their DEBUG statements to be activatable with -debug-only=thatst ring.		/// all of their DEBUG statements to be activatable with -debug-only=thatst ring.
	#ifndef DEBUG_TYPE		#ifndef DEBUG_TYPE
	#define DEBUG_TYPE ""		#define DEBUG_TYPE ""
	#endif		#endif
	#ifndef NDEBUG		#ifndef NDEBUG
	/// DebugFlag - This boolean is set to true if the '-debug' command line op tion		/// DebugFlag - This boolean is set to true if the '-debug' command line op tion
	/// is specified. This should probably not be referenced directly, instead , use		/// is specified. This should probably not be referenced directly, instead , use
End of changes. 2 change blocks.
	2 lines changed or deleted		2 lines changed or added

	DebugInfo.h		DebugInfo.h
	skipping to change at line 20		skipping to change at line 20
	// This file defines a bunch of datatypes that are useful for creating and		// This file defines a bunch of datatypes that are useful for creating and
	// walking debug info in LLVM IR form. They essentially provide wrappers ar ound		// walking debug info in LLVM IR form. They essentially provide wrappers ar ound
	// the information in the global variables that's needed when constructing the		// the information in the global variables that's needed when constructing the
	// DWARF information.		// DWARF information.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_DEBUGINFO_H		#ifndef LLVM_DEBUGINFO_H
	#define LLVM_DEBUGINFO_H		#define LLVM_DEBUGINFO_H
			#include "llvm/Support/Casting.h"
			#include "llvm/ADT/DenseMap.h"
	#include "llvm/ADT/SmallPtrSet.h"		#include "llvm/ADT/SmallPtrSet.h"
	#include "llvm/ADT/SmallVector.h"		#include "llvm/ADT/SmallVector.h"
	#include "llvm/ADT/StringRef.h"		#include "llvm/ADT/StringRef.h"
			#include "llvm/IR/Metadata.h"
	#include "llvm/Support/Dwarf.h"		#include "llvm/Support/Dwarf.h"
	namespace llvm {		namespace llvm {
	class BasicBlock;		class BasicBlock;
	class Constant;		class Constant;
	class Function;		class Function;
	class GlobalVariable;		class GlobalVariable;
	class Module;		class Module;
	class Type;		class Type;
	class Value;		class Value;
	class DbgDeclareInst;		class DbgDeclareInst;
	class Instruction;		class DbgValueInst;
	class MDNode;		class Instruction;
	class NamedMDNode;		class MDNode;
	class LLVMContext;		class MDString;
	class raw_ostream;		class NamedMDNode;
			class LLVMContext;
	class DIFile;		class raw_ostream;
	class DISubprogram;
	class DILexicalBlock;		class DIFile;
	class DILexicalBlockFile;		class DISubprogram;
	class DIVariable;		class DILexicalBlock;
	class DIType;		class DILexicalBlockFile;
	class DIObjCProperty;		class DIVariable;
			class DIType;
	/// DIDescriptor - A thin wraper around MDNode to access encoded debug in		class DIScope;
	fo.		class DIObjCProperty;
	/// This should not be stored in a container, because the underlying MDNo
	de		/// Maps from type identifier to the actual MDNode.
	/// may change in certain situations.		typedef DenseMap<const MDString *, MDNode *> DITypeIdentifierMap;
	class DIDescriptor {
	public:		/// DIDescriptor - A thin wraper around MDNode to access encoded debug info
	enum {		.
	FlagPrivate = 1 << 0,		/// This should not be stored in a container, because the underlying MDNode
	FlagProtected = 1 << 1,		/// may change in certain situations.
	FlagFwdDecl = 1 << 2,		class DIDescriptor {
	FlagAppleBlock = 1 << 3,		// Befriends DIRef so DIRef can befriend the protected member
	FlagBlockByrefStruct = 1 << 4,		// function: getFieldAs<DIRef>.
	FlagVirtual = 1 << 5,		template <typename T> friend class DIRef;
	FlagArtificial = 1 << 6,
	FlagExplicit = 1 << 7,		public:
	FlagPrototyped = 1 << 8,		enum {
	FlagObjcClassComplete = 1 << 9,		FlagPrivate = 1 << 0,
	FlagObjectPointer = 1 << 10,		FlagProtected = 1 << 1,
	FlagVector = 1 << 11,		FlagFwdDecl = 1 << 2,
	FlagStaticMember = 1 << 12		FlagAppleBlock = 1 << 3,
	};		FlagBlockByrefStruct = 1 << 4,
	protected:		FlagVirtual = 1 << 5,
	const MDNode *DbgNode;		FlagArtificial = 1 << 6,
			FlagExplicit = 1 << 7,
	StringRef getStringField(unsigned Elt) const;		FlagPrototyped = 1 << 8,
	unsigned getUnsignedField(unsigned Elt) const {		FlagObjcClassComplete = 1 << 9,
	return (unsigned)getUInt64Field(Elt);		FlagObjectPointer = 1 << 10,
	}		FlagVector = 1 << 11,
	uint64_t getUInt64Field(unsigned Elt) const;		FlagStaticMember = 1 << 12,
	int64_t getInt64Field(unsigned Elt) const;		FlagIndirectVariable = 1 << 13
	DIDescriptor getDescriptorField(unsigned Elt) const;		};
	template <typename DescTy>		protected:
	DescTy getFieldAs(unsigned Elt) const {		const MDNode *DbgNode;
	return DescTy(getDescriptorField(Elt));
	}		StringRef getStringField(unsigned Elt) const;
			unsigned getUnsignedField(unsigned Elt) const {
	GlobalVariable *getGlobalVariableField(unsigned Elt) const;		return (unsigned)getUInt64Field(Elt);
	Constant *getConstantField(unsigned Elt) const;		}
	Function *getFunctionField(unsigned Elt) const;		uint64_t getUInt64Field(unsigned Elt) const;
	void replaceFunctionField(unsigned Elt, Function *F);		int64_t getInt64Field(unsigned Elt) const;
			DIDescriptor getDescriptorField(unsigned Elt) const;
	public:
	explicit DIDescriptor() : DbgNode(0) {}		template <typename DescTy> DescTy getFieldAs(unsigned Elt) const {
	explicit DIDescriptor(const MDNode *N) : DbgNode(N) {}		return DescTy(getDescriptorField(Elt));
	explicit DIDescriptor(const DIFile F);		}
	explicit DIDescriptor(const DISubprogram F);
	explicit DIDescriptor(const DILexicalBlockFile F);		GlobalVariable *getGlobalVariableField(unsigned Elt) const;
	explicit DIDescriptor(const DILexicalBlock F);		Constant *getConstantField(unsigned Elt) const;
	explicit DIDescriptor(const DIVariable F);		Function *getFunctionField(unsigned Elt) const;
	explicit DIDescriptor(const DIType F);		void replaceFunctionField(unsigned Elt, Function *F);
	bool Verify() const;		public:
			explicit DIDescriptor(const MDNode *N = 0) : DbgNode(N) {}
	operator MDNode *() const { return const_cast<MDNode*>(DbgNode); }
	MDNode *operator ->() const { return const_cast<MDNode*>(DbgNode); }		bool Verify() const;
	unsigned getTag() const {		operator MDNode *() const { return const_cast<MDNode *>(DbgNode); }
	return getUnsignedField(0) & ~LLVMDebugVersionMask;		MDNode *operator->() const { return const_cast<MDNode *>(DbgNode); }
	}
			// An explicit operator bool so that we can do testing of DI values
	bool isDerivedType() const;		// easily.
	bool isCompositeType() const;		// FIXME: This operator bool isn't actually protecting anything at the
	bool isBasicType() const;		// moment due to the conversion operator above making DIDescriptor nodes
	bool isVariable() const;		// implicitly convertable to bool.
	bool isSubprogram() const;		LLVM_EXPLICIT operator bool() const { return DbgNode != 0; }
	bool isGlobalVariable() const;
	bool isScope() const;		bool operator==(DIDescriptor Other) const { return DbgNode == Other.DbgNo
	bool isFile() const;		de; }
	bool isCompileUnit() const;		bool operator!=(DIDescriptor Other) const { return !operator==(Other); }
	bool isNameSpace() const;
	bool isLexicalBlockFile() const;		uint16_t getTag() const {
	bool isLexicalBlock() const;		return getUnsignedField(0) & ~LLVMDebugVersionMask;
	bool isSubrange() const;		}
	bool isEnumerator() const;
	bool isType() const;		bool isDerivedType() const;
	bool isGlobal() const;		bool isCompositeType() const;
	bool isUnspecifiedParameter() const;		bool isBasicType() const;
	bool isTemplateTypeParameter() const;		bool isVariable() const;
	bool isTemplateValueParameter() const;		bool isSubprogram() const;
	bool isObjCProperty() const;		bool isGlobalVariable() const;
	bool isImportedModule() const;		bool isScope() const;
			bool isFile() const;
	/// print - print descriptor.		bool isCompileUnit() const;
	void print(raw_ostream &OS) const;		bool isNameSpace() const;
			bool isLexicalBlockFile() const;
	/// dump - print descriptor to dbgs() with a newline.		bool isLexicalBlock() const;
	void dump() const;		bool isSubrange() const;
	};		bool isEnumerator() const;
			bool isType() const;
	/// DISubrange - This is used to represent ranges, for array bounds.		bool isUnspecifiedParameter() const;
	class DISubrange : public DIDescriptor {		bool isTemplateTypeParameter() const;
	friend class DIDescriptor;		bool isTemplateValueParameter() const;
	void printInternal(raw_ostream &OS) const;		bool isObjCProperty() const;
	public:		bool isImportedEntity() const;
	explicit DISubrange(const MDNode *N = 0) : DIDescriptor(N) {}
			/// print - print descriptor.
	int64_t getLo() const { return getInt64Field(1); }		void print(raw_ostream &OS) const;
	int64_t getCount() const { return getInt64Field(2); }
	bool Verify() const;		/// dump - print descriptor to dbgs() with a newline.
	};		void dump() const;
			};
	/// DIArray - This descriptor holds an array of descriptors.
	class DIArray : public DIDescriptor {		/// DISubrange - This is used to represent ranges, for array bounds.
	public:		class DISubrange : public DIDescriptor {
	explicit DIArray(const MDNode *N = 0)		friend class DIDescriptor;
	: DIDescriptor(N) {}		void printInternal(raw_ostream &OS) const;
	unsigned getNumElements() const;		public:
	DIDescriptor getElement(unsigned Idx) const {		explicit DISubrange(const MDNode *N = 0) : DIDescriptor(N) {}
	return getDescriptorField(Idx);
	}		int64_t getLo() const { return getInt64Field(1); }
	};		int64_t getCount() const { return getInt64Field(2); }
			bool Verify() const;
	/// DIScope - A base class for various scopes.		};
	class DIScope : public DIDescriptor {
	protected:		/// DIArray - This descriptor holds an array of descriptors.
	friend class DIDescriptor;		class DIArray : public DIDescriptor {
	void printInternal(raw_ostream &OS) const;		public:
	public:		explicit DIArray(const MDNode *N = 0) : DIDescriptor(N) {}
	explicit DIScope(const MDNode *N = 0) : DIDescriptor (N) {}
			unsigned getNumElements() const;
	StringRef getFilename() const;		DIDescriptor getElement(unsigned Idx) const {
	StringRef getDirectory() const;		return getDescriptorField(Idx);
	};		}
			};
	/// DIFile - This is a wrapper for a file.
	class DIFile : public DIScope {		/// DIEnumerator - A wrapper for an enumerator (e.g. X and Y in 'enum {X,Y}
	friend class DIDescriptor;		').
	public:		/// FIXME: it seems strange that this doesn't have either a reference to th
	explicit DIFile(const MDNode *N = 0) : DIScope(N) {		e
	if (DbgNode && !isFile())		/// type/precision or a file/line pair for location info.
	DbgNode = 0;		class DIEnumerator : public DIDescriptor {
	}		friend class DIDescriptor;
	MDNode *getFileNode() const;		void printInternal(raw_ostream &OS) const;
	bool Verify() const;
	};		public:
			explicit DIEnumerator(const MDNode *N = 0) : DIDescriptor(N) {}
	/// DICompileUnit - A wrapper for a compile unit.
	class DICompileUnit : public DIScope {		StringRef getName() const { return getStringField(1); }
	friend class DIDescriptor;		int64_t getEnumValue() const { return getInt64Field(2); }
	void printInternal(raw_ostream &OS) const;		bool Verify() const;
	public:		};
	explicit DICompileUnit(const MDNode *N = 0) : DIScope(N) {}
			template <typename T> class DIRef;
	unsigned getLanguage() const { return getUnsignedField(2); }		typedef DIRef<DIScope> DIScopeRef;
	StringRef getProducer() const { return getStringField(3); }		typedef DIRef<DIType> DITypeRef;
	bool isOptimized() const { return getUnsignedField(4) != 0; }		/// DIScope - A base class for various scopes.
	StringRef getFlags() const { return getStringField(5); }		class DIScope : public DIDescriptor {
	unsigned getRunTimeVersion() const { return getUnsignedField(6); }		protected:
			friend class DIDescriptor;
	DIArray getEnumTypes() const;		void printInternal(raw_ostream &OS) const;
	DIArray getRetainedTypes() const;
	DIArray getSubprograms() const;		public:
	DIArray getGlobalVariables() const;		explicit DIScope(const MDNode *N = 0) : DIDescriptor(N) {}
	DIArray getImportedModules() const;
			/// Gets the parent scope for this scope node or returns a
	StringRef getSplitDebugFilename() const { return getStringField(12); }		/// default constructed scope.
			DIScopeRef getContext() const;
	/// Verify - Verify that a compile unit is well formed.		/// If the scope node has a name, return that, else return an empty strin
	bool Verify() const;		g.
	};		StringRef getName() const;
			StringRef getFilename() const;
	/// DIEnumerator - A wrapper for an enumerator (e.g. X and Y in 'enum {X,		StringRef getDirectory() const;
	Y}').
	/// FIXME: it seems strange that this doesn't have either a reference to		/// Generate a reference to this DIScope. Uses the type identifier instea
	the		d
	/// type/precision or a file/line pair for location info.		/// of the actual MDNode if possible, to help type uniquing.
	class DIEnumerator : public DIDescriptor {		DIScopeRef getRef() const;
	friend class DIDescriptor;		};
	void printInternal(raw_ostream &OS) const;
	public:		/// Represents reference to a DIDescriptor, abstracts over direct and
	explicit DIEnumerator(const MDNode *N = 0) : DIDescriptor(N) {}		/// identifier-based metadata references.
			template <typename T> class DIRef {
	StringRef getName() const { return getStringField(1); }		template <typename DescTy>
	uint64_t getEnumValue() const { return getUInt64Field(2); }		friend DescTy DIDescriptor::getFieldAs(unsigned Elt) const;
	bool Verify() const;		friend DIScopeRef DIScope::getContext() const;
	};		friend DIScopeRef DIScope::getRef() const;
	/// DIType - This is a wrapper for a type.		/// Val can be either a MDNode or a MDString, in the latter,
	/// FIXME: Types should be factored much better so that CV qualifiers and		/// MDString specifies the type identifier.
	/// others do not require a huge and empty descriptor full of zeros.		const Value *Val;
	class DIType : public DIScope {		explicit DIRef(const Value *V);
	protected:
	friend class DIDescriptor;		public:
	void printInternal(raw_ostream &OS) const;		T resolve(const DITypeIdentifierMap &Map) const;
	// This ctor is used when the Tag has already been validated by a deriv		StringRef getName() const;
	ed		operator Value *() const { return const_cast<Value *>(Val); }
	// ctor.		};
	DIType(const MDNode *N, bool, bool) : DIScope(N) {}
	public:		template <typename T>
	/// Verify - Verify that a type descriptor is well formed.		T DIRef<T>::resolve(const DITypeIdentifierMap &Map) const {
	bool Verify() const;		if (!Val)
	explicit DIType(const MDNode *N);		return T();
	explicit DIType() {}
			if (const MDNode *MD = dyn_cast<MDNode>(Val))
	DIScope getContext() const { return getFieldAs<DIScope>(2); }		return T(MD);
	StringRef getName() const { return getStringField(3); }
	unsigned getLineNumber() const { return getUnsignedField(4); }		const MDString *MS = cast<MDString>(Val);
	uint64_t getSizeInBits() const { return getUInt64Field(5); }		// Find the corresponding MDNode.
	uint64_t getAlignInBits() const { return getUInt64Field(6); }		DITypeIdentifierMap::const_iterator Iter = Map.find(MS);
	// FIXME: Offset is only used for DW_TAG_member nodes. Making every ty		assert(Iter != Map.end() && "Identifier not in the type map?");
	pe		assert(DIDescriptor(Iter->second).isType() &&
	// carry this is just plain insane.		"MDNode in DITypeIdentifierMap should be a DIType.");
	uint64_t getOffsetInBits() const { return getUInt64Field(7); }		return T(Iter->second);
	unsigned getFlags() const { return getUnsignedField(8); }		}
	bool isPrivate() const {
	return (getFlags() & FlagPrivate) != 0;		template <typename T> StringRef DIRef<T>::getName() const {
	}		if (!Val)
	bool isProtected() const {		return StringRef();
	return (getFlags() & FlagProtected) != 0;
	}		if (const MDNode *MD = dyn_cast<MDNode>(Val))
	bool isForwardDecl() const {		return T(MD).getName();
	return (getFlags() & FlagFwdDecl) != 0;
	}		const MDString *MS = cast<MDString>(Val);
	// isAppleBlock - Return true if this is the Apple Blocks extension.		return MS->getString();
	bool isAppleBlockExtension() const {		}
	return (getFlags() & FlagAppleBlock) != 0;
	}		/// Specialize getFieldAs to handle fields that are references to DIScopes.
	bool isBlockByrefStruct() const {		template <> DIScopeRef DIDescriptor::getFieldAs<DIScopeRef>(unsigned Elt) c
	return (getFlags() & FlagBlockByrefStruct) != 0;		onst;
	}		/// Specialize DIRef constructor for DIScopeRef.
	bool isVirtual() const {		template <> DIRef<DIScope>::DIRef(const Value *V);
	return (getFlags() & FlagVirtual) != 0;
	}		/// Specialize getFieldAs to handle fields that are references to DITypes.
	bool isArtificial() const {		template <> DITypeRef DIDescriptor::getFieldAs<DITypeRef>(unsigned Elt) con
	return (getFlags() & FlagArtificial) != 0;		st;
	}		/// Specialize DIRef constructor for DITypeRef.
	bool isObjectPointer() const {		template <> DIRef<DIType>::DIRef(const Value *V);
	return (getFlags() & FlagObjectPointer) != 0;
	}		/// DIType - This is a wrapper for a type.
	bool isObjcClassComplete() const {		/// FIXME: Types should be factored much better so that CV qualifiers and
	return (getFlags() & FlagObjcClassComplete) != 0;		/// others do not require a huge and empty descriptor full of zeros.
	}		class DIType : public DIScope {
	bool isVector() const {		protected:
	return (getFlags() & FlagVector) != 0;		friend class DIDescriptor;
	}		void printInternal(raw_ostream &OS) const;
	bool isStaticMember() const {
	return (getFlags() & FlagStaticMember) != 0;		public:
	}		explicit DIType(const MDNode *N = 0) : DIScope(N) {}
	bool isValid() const {
	return DbgNode && (isBasicType() || isDerivedType() || isCompositeTyp		/// Verify - Verify that a type descriptor is well formed.
	e());		bool Verify() const;
	}
			DIScopeRef getContext() const { return getFieldAs<DIScopeRef>(2); }
	/// isUnsignedDIType - Return true if type encoding is unsigned.		StringRef getName() const { return getStringField(3); }
	bool isUnsignedDIType();		unsigned getLineNumber() const { return getUnsignedField(4); }
			uint64_t getSizeInBits() const { return getUInt64Field(5); }
	/// replaceAllUsesWith - Replace all uses of debug info referenced by		uint64_t getAlignInBits() const { return getUInt64Field(6); }
	/// this descriptor.		// FIXME: Offset is only used for DW_TAG_member nodes. Making every type
	void replaceAllUsesWith(DIDescriptor &D);		// carry this is just plain insane.
	void replaceAllUsesWith(MDNode *D);		uint64_t getOffsetInBits() const { return getUInt64Field(7); }
	};		unsigned getFlags() const { return getUnsignedField(8); }
			bool isPrivate() const { return (getFlags() & FlagPrivate) != 0; }
	/// DIBasicType - A basic type, like 'int' or 'float'.		bool isProtected() const { return (getFlags() & FlagProtected) != 0; }
	class DIBasicType : public DIType {		bool isForwardDecl() const { return (getFlags() & FlagFwdDecl) != 0; }
	public:		// isAppleBlock - Return true if this is the Apple Blocks extension.
	explicit DIBasicType(const MDNode *N = 0) : DIType(N) {}		bool isAppleBlockExtension() const {
			return (getFlags() & FlagAppleBlock) != 0;
	unsigned getEncoding() const { return getUnsignedField(9); }		}
			bool isBlockByrefStruct() const {
	/// Verify - Verify that a basic type descriptor is well formed.		return (getFlags() & FlagBlockByrefStruct) != 0;
	bool Verify() const;		}
	};		bool isVirtual() const { return (getFlags() & FlagVirtual) != 0; }
			bool isArtificial() const { return (getFlags() & FlagArtificial) != 0; }
	/// DIDerivedType - A simple derived type, like a const qualified type,		bool isObjectPointer() const { return (getFlags() & FlagObjectPointer) !=
	/// a typedef, a pointer or reference, et cetera. Or, a data member of		0; }
	/// a class/struct/union.		bool isObjcClassComplete() const {
	class DIDerivedType : public DIType {		return (getFlags() & FlagObjcClassComplete) != 0;
	friend class DIDescriptor;		}
	void printInternal(raw_ostream &OS) const;		bool isVector() const { return (getFlags() & FlagVector) != 0; }
	protected:		bool isStaticMember() const { return (getFlags() & FlagStaticMember) != 0
	explicit DIDerivedType(const MDNode *N, bool, bool)		; }
	: DIType(N, true, true) {}		bool isValid() const { return DbgNode && isType(); }
	public:
	explicit DIDerivedType(const MDNode *N = 0)		/// replaceAllUsesWith - Replace all uses of debug info referenced by
	: DIType(N, true, true) {}		/// this descriptor.
			void replaceAllUsesWith(DIDescriptor &D);
	DIType getTypeDerivedFrom() const { return getFieldAs<DIType>(9); }		void replaceAllUsesWith(MDNode *D);
			};
	/// getOriginalTypeSize - If this type is derived from a base type then
	/// return base type size.		/// DIBasicType - A basic type, like 'int' or 'float'.
	uint64_t getOriginalTypeSize() const;		class DIBasicType : public DIType {
			public:
	/// getObjCProperty - Return property node, if this ivar is		explicit DIBasicType(const MDNode *N = 0) : DIType(N) {}
	/// associated with one.
	MDNode *getObjCProperty() const;		unsigned getEncoding() const { return getUnsignedField(9); }
	DIType getClassType() const {		/// Verify - Verify that a basic type descriptor is well formed.
	assert(getTag() == dwarf::DW_TAG_ptr_to_member_type);		bool Verify() const;
	return getFieldAs<DIType>(10);		};
	}
			/// DIDerivedType - A simple derived type, like a const qualified type,
	Constant *getConstant() const {		/// a typedef, a pointer or reference, et cetera. Or, a data member of
	assert((getTag() == dwarf::DW_TAG_member) && isStaticMember());		/// a class/struct/union.
	return getConstantField(10);		class DIDerivedType : public DIType {
	}		friend class DIDescriptor;
			void printInternal(raw_ostream &OS) const;
	/// Verify - Verify that a derived type descriptor is well formed.
	bool Verify() const;		public:
	};		explicit DIDerivedType(const MDNode *N = 0) : DIType(N) {}
	/// DICompositeType - This descriptor holds a type that can refer to mult		DITypeRef getTypeDerivedFrom() const { return getFieldAs<DITypeRef>(9); }
	iple
	/// other types, like a function or struct.		/// getObjCProperty - Return property node, if this ivar is
	/// DICompositeType is derived from DIDerivedType because some		/// associated with one.
	/// composite types (such as enums) can be derived from basic types		MDNode *getObjCProperty() const;
	// FIXME: Make this derive from DIType directly & just store the
	// base type in a single DIType field.		DITypeRef getClassType() const {
	class DICompositeType : public DIDerivedType {		assert(getTag() == dwarf::DW_TAG_ptr_to_member_type);
	friend class DIDescriptor;		return getFieldAs<DITypeRef>(10);
	void printInternal(raw_ostream &OS) const;		}
	public:
	explicit DICompositeType(const MDNode *N = 0)		Constant *getConstant() const {
	: DIDerivedType(N, true, true) {		assert((getTag() == dwarf::DW_TAG_member) && isStaticMember());
	if (N && !isCompositeType())		return getConstantField(10);
	DbgNode = 0;		}
	}
			/// Verify - Verify that a derived type descriptor is well formed.
	DIArray getTypeArray() const { return getFieldAs<DIArray>(10); }		bool Verify() const;
	void setTypeArray(DIArray Elements, DIArray TParams = DIArray());		};
	unsigned getRunTimeLang() const { return getUnsignedField(11); }
	DICompositeType getContainingType() const {		/// DICompositeType - This descriptor holds a type that can refer to multip
	return getFieldAs<DICompositeType>(12);		le
	}		/// other types, like a function or struct.
	void setContainingType(DICompositeType ContainingType);		/// DICompositeType is derived from DIDerivedType because some
	DIArray getTemplateParams() const { return getFieldAs<DIArray>(13); }		/// composite types (such as enums) can be derived from basic types
			// FIXME: Make this derive from DIType directly & just store the
	/// Verify - Verify that a composite type descriptor is well formed.		// base type in a single DIType field.
	bool Verify() const;		class DICompositeType : public DIDerivedType {
	};		friend class DIDescriptor;
			void printInternal(raw_ostream &OS) const;
	/// DITemplateTypeParameter - This is a wrapper for template type paramet
	er.		public:
	class DITemplateTypeParameter : public DIDescriptor {		explicit DICompositeType(const MDNode *N = 0) : DIDerivedType(N) {}
	public:
	explicit DITemplateTypeParameter(const MDNode *N = 0) : DIDescriptor(N)		DIArray getTypeArray() const { return getFieldAs<DIArray>(10); }
	{}		void setTypeArray(DIArray Elements, DIArray TParams = DIArray());
			void addMember(DIDescriptor D);
	DIScope getContext() const { return getFieldAs<DIScope>(1); }		unsigned getRunTimeLang() const { return getUnsignedField(11); }
	StringRef getName() const { return getStringField(2); }		DITypeRef getContainingType() const { return getFieldAs<DITypeRef>(12); }
	DIType getType() const { return getFieldAs<DIType>(3); }		void setContainingType(DICompositeType ContainingType);
	StringRef getFilename() const {		DIArray getTemplateParams() const { return getFieldAs<DIArray>(13); }
	return getFieldAs<DIFile>(4).getFilename();		MDString *getIdentifier() const;
	}
	StringRef getDirectory() const {		/// Verify - Verify that a composite type descriptor is well formed.
	return getFieldAs<DIFile>(4).getDirectory();		bool Verify() const;
	}		};
	unsigned getLineNumber() const { return getUnsignedField(5); }
	unsigned getColumnNumber() const { return getUnsignedField(6); }		/// DIFile - This is a wrapper for a file.
	bool Verify() const;		class DIFile : public DIScope {
	};		friend class DIDescriptor;
	/// DITemplateValueParameter - This is a wrapper for template value param		public:
	eter.		explicit DIFile(const MDNode *N = 0) : DIScope(N) {}
	class DITemplateValueParameter : public DIDescriptor {		MDNode *getFileNode() const;
	public:		bool Verify() const;
	explicit DITemplateValueParameter(const MDNode *N = 0) : DIDescriptor(N		};
	) {}
			/// DICompileUnit - A wrapper for a compile unit.
	DIScope getContext() const { return getFieldAs<DIScope>(1); }		class DICompileUnit : public DIScope {
	StringRef getName() const { return getStringField(2); }		friend class DIDescriptor;
	DIType getType() const { return getFieldAs<DIType>(3); }		void printInternal(raw_ostream &OS) const;
	uint64_t getValue() const { return getUInt64Field(4); }
	StringRef getFilename() const {		public:
	return getFieldAs<DIFile>(5).getFilename();		explicit DICompileUnit(const MDNode *N = 0) : DIScope(N) {}
	}
	StringRef getDirectory() const {		unsigned getLanguage() const { return getUnsignedField(2); }
	return getFieldAs<DIFile>(5).getDirectory();		StringRef getProducer() const { return getStringField(3); }
	}
	unsigned getLineNumber() const { return getUnsignedField(6); }		bool isOptimized() const { return getUnsignedField(4) != 0; }
	unsigned getColumnNumber() const { return getUnsignedField(7); }		StringRef getFlags() const { return getStringField(5); }
	bool Verify() const;		unsigned getRunTimeVersion() const { return getUnsignedField(6); }
	};
			DIArray getEnumTypes() const;
	/// DISubprogram - This is a wrapper for a subprogram (e.g. a function).		DIArray getRetainedTypes() const;
	class DISubprogram : public DIScope {		DIArray getSubprograms() const;
	friend class DIDescriptor;		DIArray getGlobalVariables() const;
	void printInternal(raw_ostream &OS) const;		DIArray getImportedEntities() const;
	public:
	explicit DISubprogram(const MDNode *N = 0) : DIScope(N) {}		StringRef getSplitDebugFilename() const { return getStringField(12); }
	DIScope getContext() const { return getFieldAs<DIScope>(2); }		/// Verify - Verify that a compile unit is well formed.
	StringRef getName() const { return getStringField(3); }		bool Verify() const;
	StringRef getDisplayName() const { return getStringField(4); }		};
	StringRef getLinkageName() const { return getStringField(5); }
	unsigned getLineNumber() const { return getUnsignedField(6); }		/// DISubprogram - This is a wrapper for a subprogram (e.g. a function).
	DICompositeType getType() const { return getFieldAs<DICompositeType>(7)		class DISubprogram : public DIScope {
	; }		friend class DIDescriptor;
			void printInternal(raw_ostream &OS) const;
	/// getReturnTypeName - Subprogram return types are encoded either as
	/// DIType or as DICompositeType.		public:
	StringRef getReturnTypeName() const {		explicit DISubprogram(const MDNode *N = 0) : DIScope(N) {}
	DICompositeType DCT(getFieldAs<DICompositeType>(7));
	if (DCT.Verify()) {		DIScopeRef getContext() const { return getFieldAs<DIScopeRef>(2); }
	DIArray A = DCT.getTypeArray();		StringRef getName() const { return getStringField(3); }
	DIType T(A.getElement(0));		StringRef getDisplayName() const { return getStringField(4); }
	return T.getName();		StringRef getLinkageName() const { return getStringField(5); }
	}		unsigned getLineNumber() const { return getUnsignedField(6); }
	DIType T(getFieldAs<DIType>(7));		DICompositeType getType() const { return getFieldAs<DICompositeType>(7);
	return T.getName();		}
	}
			/// isLocalToUnit - Return true if this subprogram is local to the curren
	/// isLocalToUnit - Return true if this subprogram is local to the curr		t
	ent		/// compile unit, like 'static' in C.
	/// compile unit, like 'static' in C.		unsigned isLocalToUnit() const { return getUnsignedField(8); }
	unsigned isLocalToUnit() const { return getUnsignedField(8); }		unsigned isDefinition() const { return getUnsignedField(9); }
	unsigned isDefinition() const { return getUnsignedField(9); }
			unsigned getVirtuality() const { return getUnsignedField(10); }
	unsigned getVirtuality() const { return getUnsignedField(10); }		unsigned getVirtualIndex() const { return getUnsignedField(11); }
	unsigned getVirtualIndex() const { return getUnsignedField(11); }
			DITypeRef getContainingType() const { return getFieldAs<DITypeRef>(12); }
	DICompositeType getContainingType() const {
	return getFieldAs<DICompositeType>(12);		unsigned getFlags() const { return getUnsignedField(13); }
	}
			unsigned isArtificial() const {
	unsigned getFlags() const {		return (getUnsignedField(13) & FlagArtificial) != 0;
	return getUnsignedField(13);		}
	}		/// isPrivate - Return true if this subprogram has "private"
			/// access specifier.
	unsigned isArtificial() const {		bool isPrivate() const { return (getUnsignedField(13) & FlagPrivate) != 0
	return (getUnsignedField(13) & FlagArtificial) != 0;		; }
	}		/// isProtected - Return true if this subprogram has "protected"
	/// isPrivate - Return true if this subprogram has "private"		/// access specifier.
	/// access specifier.		bool isProtected() const {
	bool isPrivate() const {		return (getUnsignedField(13) & FlagProtected) != 0;
	return (getUnsignedField(13) & FlagPrivate) != 0;		}
	}		/// isExplicit - Return true if this subprogram is marked as explicit.
	/// isProtected - Return true if this subprogram has "protected"		bool isExplicit() const { return (getUnsignedField(13) & FlagExplicit) !=
	/// access specifier.		0; }
	bool isProtected() const {		/// isPrototyped - Return true if this subprogram is prototyped.
	return (getUnsignedField(13) & FlagProtected) != 0;		bool isPrototyped() const {
	}		return (getUnsignedField(13) & FlagPrototyped) != 0;
	/// isExplicit - Return true if this subprogram is marked as explicit.		}
	bool isExplicit() const {
	return (getUnsignedField(13) & FlagExplicit) != 0;		unsigned isOptimized() const;
	}
	/// isPrototyped - Return true if this subprogram is prototyped.		/// Verify - Verify that a subprogram descriptor is well formed.
	bool isPrototyped() const {		bool Verify() const;
	return (getUnsignedField(13) & FlagPrototyped) != 0;
	}		/// describes - Return true if this subprogram provides debugging
			/// information for the function F.
	unsigned isOptimized() const;		bool describes(const Function *F);
	/// getScopeLineNumber - Get the beginning of the scope of the		Function *getFunction() const { return getFunctionField(15); }
	/// function, not necessarily where the name of the program		void replaceFunction(Function *F) { replaceFunctionField(15, F); }
	/// starts.		DIArray getTemplateParams() const { return getFieldAs<DIArray>(16); }
	unsigned getScopeLineNumber() const { return getUnsignedField(19); }		DISubprogram getFunctionDeclaration() const {
			return getFieldAs<DISubprogram>(17);
	/// Verify - Verify that a subprogram descriptor is well formed.		}
	bool Verify() const;		MDNode *getVariablesNodes() const;
			DIArray getVariables() const;
	/// describes - Return true if this subprogram provides debugging
	/// information for the function F.		/// getScopeLineNumber - Get the beginning of the scope of the
	bool describes(const Function *F);		/// function, not necessarily where the name of the program
			/// starts.
	Function *getFunction() const { return getFunctionField(15); }		unsigned getScopeLineNumber() const { return getUnsignedField(19); }
	void replaceFunction(Function *F) { replaceFunctionField(15, F); }		};
	DIArray getTemplateParams() const { return getFieldAs<DIArray>(16); }
	DISubprogram getFunctionDeclaration() const {		/// DILexicalBlock - This is a wrapper for a lexical block.
	return getFieldAs<DISubprogram>(17);		class DILexicalBlock : public DIScope {
	}		public:
	MDNode *getVariablesNodes() const;		explicit DILexicalBlock(const MDNode *N = 0) : DIScope(N) {}
	DIArray getVariables() const;		DIScope getContext() const { return getFieldAs<DIScope>(2); }
	};		unsigned getLineNumber() const { return getUnsignedField(3); }
			unsigned getColumnNumber() const { return getUnsignedField(4); }
	/// DIGlobalVariable - This is a wrapper for a global variable.		bool Verify() const;
	class DIGlobalVariable : public DIDescriptor {		};
	friend class DIDescriptor;
	void printInternal(raw_ostream &OS) const;		/// DILexicalBlockFile - This is a wrapper for a lexical block with
	public:		/// a filename change.
	explicit DIGlobalVariable(const MDNode *N = 0) : DIDescriptor(N) {}		class DILexicalBlockFile : public DIScope {
			public:
	DIScope getContext() const { return getFieldAs<DIScope>(2); }		explicit DILexicalBlockFile(const MDNode *N = 0) : DIScope(N) {}
	StringRef getName() const { return getStringField(3); }		DIScope getContext() const {
	StringRef getDisplayName() const { return getStringField(4); }		if (getScope().isSubprogram())
	StringRef getLinkageName() const { return getStringField(5); }		return getScope();
	StringRef getFilename() const {		return getScope().getContext();
	return getFieldAs<DIFile>(6).getFilename();		}
	}		unsigned getLineNumber() const { return getScope().getLineNumber(); }
	StringRef getDirectory() const {		unsigned getColumnNumber() const { return getScope().getColumnNumber(); }
	return getFieldAs<DIFile>(6).getDirectory();		DILexicalBlock getScope() const { return getFieldAs<DILexicalBlock>(2); }
			bool Verify() const;
	}		};
	unsigned getLineNumber() const { return getUnsignedField(7); }		/// DINameSpace - A wrapper for a C++ style name space.
	DIType getType() const { return getFieldAs<DIType>(8); }		class DINameSpace : public DIScope {
	unsigned isLocalToUnit() const { return getUnsignedField(9); }		friend class DIDescriptor;
	unsigned isDefinition() const { return getUnsignedField(10); }		void printInternal(raw_ostream &OS) const;
	GlobalVariable *getGlobal() const { return getGlobalVariableField(11);		public:
	}		explicit DINameSpace(const MDNode *N = 0) : DIScope(N) {}
	Constant *getConstant() const { return getConstantField(11); }		DIScope getContext() const { return getFieldAs<DIScope>(2); }
	DIDerivedType getStaticDataMemberDeclaration() const {		StringRef getName() const { return getStringField(3); }
	return getFieldAs<DIDerivedType>(12);		unsigned getLineNumber() const { return getUnsignedField(4); }
	}		bool Verify() const;
			};
	/// Verify - Verify that a global variable descriptor is well formed.
	bool Verify() const;		/// DITemplateTypeParameter - This is a wrapper for template type parameter
	};		.
			class DITemplateTypeParameter : public DIDescriptor {
	/// DIVariable - This is a wrapper for a variable (e.g. parameter, local,		public:
	/// global etc).		explicit DITemplateTypeParameter(const MDNode *N = 0) : DIDescriptor(N) {
	class DIVariable : public DIDescriptor {		}
	friend class DIDescriptor;
	void printInternal(raw_ostream &OS) const;		DIScopeRef getContext() const { return getFieldAs<DIScopeRef>(1); }
	public:		StringRef getName() const { return getStringField(2); }
	explicit DIVariable(const MDNode *N = 0)		DITypeRef getType() const { return getFieldAs<DITypeRef>(3); }
	: DIDescriptor(N) {}		StringRef getFilename() const { return getFieldAs<DIFile>(4).getFilename(
			); }
	DIScope getContext() const { return getFieldAs<DIScope>(1); }		StringRef getDirectory() const {
	StringRef getName() const { return getStringField(2); }		return getFieldAs<DIFile>(4).getDirectory();
	DIFile getFile() const { return getFieldAs<DIFile>(3); }		}
	unsigned getLineNumber() const {		unsigned getLineNumber() const { return getUnsignedField(5); }
	return (getUnsignedField(4) << 8) >> 8;		unsigned getColumnNumber() const { return getUnsignedField(6); }
	}		bool Verify() const;
	unsigned getArgNumber() const {		};
	unsigned L = getUnsignedField(4);
	return L >> 24;		/// DITemplateValueParameter - This is a wrapper for template value paramet
	}		er.
	DIType getType() const { return getFieldAs<DIType>(5); }		class DITemplateValueParameter : public DIDescriptor {
			public:
	/// isArtificial - Return true if this variable is marked as "artificia		explicit DITemplateValueParameter(const MDNode *N = 0) : DIDescriptor(N)
	l".		{}
	bool isArtificial() const {
	return (getUnsignedField(6) & FlagArtificial) != 0;		DIScopeRef getContext() const { return getFieldAs<DIScopeRef>(1); }
	}		StringRef getName() const { return getStringField(2); }
			DITypeRef getType() const { return getFieldAs<DITypeRef>(3); }
	bool isObjectPointer() const {		Value *getValue() const;
	return (getUnsignedField(6) & FlagObjectPointer) != 0;		StringRef getFilename() const { return getFieldAs<DIFile>(5).getFilename(
	}		); }
			StringRef getDirectory() const {
	/// getInlinedAt - If this variable is inlined then return inline locat		return getFieldAs<DIFile>(5).getDirectory();
	ion.		}
	MDNode *getInlinedAt() const;		unsigned getLineNumber() const { return getUnsignedField(6); }
			unsigned getColumnNumber() const { return getUnsignedField(7); }
	/// Verify - Verify that a variable descriptor is well formed.		bool Verify() const;
	bool Verify() const;		};
	/// HasComplexAddr - Return true if the variable has a complex address.		/// DIGlobalVariable - This is a wrapper for a global variable.
	bool hasComplexAddress() const {		class DIGlobalVariable : public DIDescriptor {
	return getNumAddrElements() > 0;		friend class DIDescriptor;
	}		void printInternal(raw_ostream &OS) const;
	unsigned getNumAddrElements() const;		public:
			explicit DIGlobalVariable(const MDNode *N = 0) : DIDescriptor(N) {}
	uint64_t getAddrElement(unsigned Idx) const {
	return getUInt64Field(Idx+8);		DIScope getContext() const { return getFieldAs<DIScope>(2); }
	}		StringRef getName() const { return getStringField(3); }
			StringRef getDisplayName() const { return getStringField(4); }
	/// isBlockByrefVariable - Return true if the variable was declared as		StringRef getLinkageName() const { return getStringField(5); }
	/// a "__block" variable (Apple Blocks).		StringRef getFilename() const { return getFieldAs<DIFile>(6).getFilename(
	bool isBlockByrefVariable() const {		); }
	return getType().isBlockByrefStruct();		StringRef getDirectory() const {
	}		return getFieldAs<DIFile>(6).getDirectory();
			}
	/// isInlinedFnArgument - Return true if this variable provides debuggi
	ng		unsigned getLineNumber() const { return getUnsignedField(7); }
	/// information for an inlined function arguments.		DIType getType() const { return getFieldAs<DIType>(8); }
	bool isInlinedFnArgument(const Function *CurFn);		unsigned isLocalToUnit() const { return getUnsignedField(9); }
			unsigned isDefinition() const { return getUnsignedField(10); }
	void printExtendedName(raw_ostream &OS) const;
	};		GlobalVariable *getGlobal() const { return getGlobalVariableField(11); }
			Constant *getConstant() const { return getConstantField(11); }
	/// DILexicalBlock - This is a wrapper for a lexical block.		DIDerivedType getStaticDataMemberDeclaration() const {
	class DILexicalBlock : public DIScope {		return getFieldAs<DIDerivedType>(12);
	public:		}
	explicit DILexicalBlock(const MDNode *N = 0) : DIScope(N) {}
	DIScope getContext() const { return getFieldAs<DIScope>(2);		/// Verify - Verify that a global variable descriptor is well formed.
	}		bool Verify() const;
	unsigned getLineNumber() const { return getUnsignedField(3);		};
	}
	unsigned getColumnNumber() const { return getUnsignedField(4);		/// DIVariable - This is a wrapper for a variable (e.g. parameter, local,
	}		/// global etc).
	bool Verify() const;		class DIVariable : public DIDescriptor {
	};		friend class DIDescriptor;
			void printInternal(raw_ostream &OS) const;
	/// DILexicalBlockFile - This is a wrapper for a lexical block with
	/// a filename change.		public:
	class DILexicalBlockFile : public DIScope {		explicit DIVariable(const MDNode *N = 0) : DIDescriptor(N) {}
	public:
	explicit DILexicalBlockFile(const MDNode *N = 0) : DIScope(N) {}		DIScope getContext() const { return getFieldAs<DIScope>(1); }
	DIScope getContext() const { if (getScope().isSubprogram()) return getS		StringRef getName() const { return getStringField(2); }
	cope(); return getScope().getContext(); }		DIFile getFile() const { return getFieldAs<DIFile>(3); }
	unsigned getLineNumber() const { return getScope().getLineNumber(); }		unsigned getLineNumber() const { return (getUnsignedField(4) << 8) >> 8;
	unsigned getColumnNumber() const { return getScope().getColumnNumber();		}
	}		unsigned getArgNumber() const {
	DILexicalBlock getScope() const { return getFieldAs<DILexicalBlock>(2);		unsigned L = getUnsignedField(4);
	}		return L >> 24;
	bool Verify() const;		}
	};		DIType getType() const { return getFieldAs<DIType>(5); }
	/// DINameSpace - A wrapper for a C++ style name space.		/// isArtificial - Return true if this variable is marked as "artificial"
	class DINameSpace : public DIScope {		.
	friend class DIDescriptor;		bool isArtificial() const {
	void printInternal(raw_ostream &OS) const;		return (getUnsignedField(6) & FlagArtificial) != 0;
	public:		}
	explicit DINameSpace(const MDNode *N = 0) : DIScope(N) {}
	DIScope getContext() const { return getFieldAs<DIScope>(2); }		bool isObjectPointer() const {
	StringRef getName() const { return getStringField(3); }		return (getUnsignedField(6) & FlagObjectPointer) != 0;
	unsigned getLineNumber() const { return getUnsignedField(4); }		}
	bool Verify() const;
	};		/// \brief Return true if this variable is represented as a pointer.
			bool isIndirect() const {
	/// DILocation - This object holds location information. This object		return (getUnsignedField(6) & FlagIndirectVariable) != 0;
	/// is not associated with any DWARF tag.		}
	class DILocation : public DIDescriptor {
	public:		/// getInlinedAt - If this variable is inlined then return inline locatio
	explicit DILocation(const MDNode *N) : DIDescriptor(N) { }		n.
			MDNode *getInlinedAt() const;
	unsigned getLineNumber() const { return getUnsignedField(0); }
	unsigned getColumnNumber() const { return getUnsignedField(1); }		/// Verify - Verify that a variable descriptor is well formed.
	DIScope getScope() const { return getFieldAs<DIScope>(2); }		bool Verify() const;
	DILocation getOrigLocation() const { return getFieldAs<DILocation>(3);
	}		/// HasComplexAddr - Return true if the variable has a complex address.
	StringRef getFilename() const { return getScope().getFilename(); }		bool hasComplexAddress() const { return getNumAddrElements() > 0; }
	StringRef getDirectory() const { return getScope().getDirectory(); }
	bool Verify() const;		unsigned getNumAddrElements() const;
	};
			uint64_t getAddrElement(unsigned Idx) const {
	class DIObjCProperty : public DIDescriptor {		return getUInt64Field(Idx + 8);
	friend class DIDescriptor;		}
	void printInternal(raw_ostream &OS) const;
	public:		/// isBlockByrefVariable - Return true if the variable was declared as
	explicit DIObjCProperty(const MDNode *N) : DIDescriptor(N) { }		/// a "__block" variable (Apple Blocks).
			bool isBlockByrefVariable() const { return getType().isBlockByrefStruct()
	StringRef getObjCPropertyName() const { return getStringField(1); }		; }
	DIFile getFile() const { return getFieldAs<DIFile>(2); }
	unsigned getLineNumber() const { return getUnsignedField(3); }		/// isInlinedFnArgument - Return true if this variable provides debugging
			/// information for an inlined function arguments.
	StringRef getObjCPropertyGetterName() const {		bool isInlinedFnArgument(const Function *CurFn);
	return getStringField(4);
	}		void printExtendedName(raw_ostream &OS) const;
	StringRef getObjCPropertySetterName() const {		};
	return getStringField(5);
	}		/// DILocation - This object holds location information. This object
	bool isReadOnlyObjCProperty() {		/// is not associated with any DWARF tag.
	return (getUnsignedField(6) & dwarf::DW_APPLE_PROPERTY_readonly) != 0		class DILocation : public DIDescriptor {
	;		public:
	}		explicit DILocation(const MDNode *N) : DIDescriptor(N) {}
	bool isReadWriteObjCProperty() {
	return (getUnsignedField(6) & dwarf::DW_APPLE_PROPERTY_readwrite) !=		unsigned getLineNumber() const { return getUnsignedField(0); }
	0;		unsigned getColumnNumber() const { return getUnsignedField(1); }
	}		DIScope getScope() const { return getFieldAs<DIScope>(2); }
	bool isAssignObjCProperty() {		DILocation getOrigLocation() const { return getFieldAs<DILocation>(3); }
	return (getUnsignedField(6) & dwarf::DW_APPLE_PROPERTY_assign) != 0;		StringRef getFilename() const { return getScope().getFilename(); }
	}		StringRef getDirectory() const { return getScope().getDirectory(); }
	bool isRetainObjCProperty() {		bool Verify() const;
	return (getUnsignedField(6) & dwarf::DW_APPLE_PROPERTY_retain) != 0;		};
	}
	bool isCopyObjCProperty() {		class DIObjCProperty : public DIDescriptor {
	return (getUnsignedField(6) & dwarf::DW_APPLE_PROPERTY_copy) != 0;		friend class DIDescriptor;
	}		void printInternal(raw_ostream &OS) const;
	bool isNonAtomicObjCProperty() {
	return (getUnsignedField(6) & dwarf::DW_APPLE_PROPERTY_nonatomic) !=		public:
	0;		explicit DIObjCProperty(const MDNode *N) : DIDescriptor(N) {}
	}
			StringRef getObjCPropertyName() const { return getStringField(1); }
	DIType getType() const { return getFieldAs<DIType>(7); }		DIFile getFile() const { return getFieldAs<DIFile>(2); }
			unsigned getLineNumber() const { return getUnsignedField(3); }
	/// Verify - Verify that a derived type descriptor is well formed.
	bool Verify() const;		StringRef getObjCPropertyGetterName() const { return getStringField(4); }
	};		StringRef getObjCPropertySetterName() const { return getStringField(5); }
			bool isReadOnlyObjCProperty() const {
	/// \brief An imported module (C++ using directive or similar).		return (getUnsignedField(6) & dwarf::DW_APPLE_PROPERTY_readonly) != 0;
	class DIImportedModule : public DIDescriptor {		}
	friend class DIDescriptor;		bool isReadWriteObjCProperty() const {
	void printInternal(raw_ostream &OS) const;		return (getUnsignedField(6) & dwarf::DW_APPLE_PROPERTY_readwrite) != 0;
	public:		}
	explicit DIImportedModule(const MDNode *N) : DIDescriptor(N) { }		bool isAssignObjCProperty() const {
	DIScope getContext() const { return getFieldAs<DIScope>(1); }		return (getUnsignedField(6) & dwarf::DW_APPLE_PROPERTY_assign) != 0;
	DINameSpace getNameSpace() const { return getFieldAs<DINameSpace>(2); }		}
	unsigned getLineNumber() const { return getUnsignedField(3); }		bool isRetainObjCProperty() const {
	bool Verify() const;		return (getUnsignedField(6) & dwarf::DW_APPLE_PROPERTY_retain) != 0;
	};		}
			bool isCopyObjCProperty() const {
	/// getDISubprogram - Find subprogram that is enclosing this scope.		return (getUnsignedField(6) & dwarf::DW_APPLE_PROPERTY_copy) != 0;
	DISubprogram getDISubprogram(const MDNode *Scope);		}
			bool isNonAtomicObjCProperty() const {
	/// getDICompositeType - Find underlying composite type.		return (getUnsignedField(6) & dwarf::DW_APPLE_PROPERTY_nonatomic) != 0;
	DICompositeType getDICompositeType(DIType T);		}
	/// isSubprogramContext - Return true if Context is either a subprogram		DIType getType() const { return getFieldAs<DIType>(7); }
	/// or another context nested inside a subprogram.
	bool isSubprogramContext(const MDNode *Context);		/// Verify - Verify that a derived type descriptor is well formed.
			bool Verify() const;
	/// getOrInsertFnSpecificMDNode - Return a NameMDNode that is suitable		};
	/// to hold function specific information.
	NamedMDNode *getOrInsertFnSpecificMDNode(Module &M, DISubprogram SP);		/// \brief An imported module (C++ using directive or similar).
			class DIImportedEntity : public DIDescriptor {
	/// getFnSpecificMDNode - Return a NameMDNode, if available, that is		friend class DIDescriptor;
	/// suitable to hold function specific information.		void printInternal(raw_ostream &OS) const;
	NamedMDNode *getFnSpecificMDNode(const Module &M, DISubprogram SP);
			public:
	/// createInlinedVariable - Create a new inlined variable based on curren		explicit DIImportedEntity(const MDNode *N) : DIDescriptor(N) {}
	t		DIScope getContext() const { return getFieldAs<DIScope>(1); }
	/// variable.		DIDescriptor getEntity() const { return getFieldAs<DIDescriptor>(2); }
	/// @param DV Current Variable.		unsigned getLineNumber() const { return getUnsignedField(3); }
	/// @param InlinedScope Location at current variable is inlined.		StringRef getName() const { return getStringField(4); }
	DIVariable createInlinedVariable(MDNode *DV, MDNode *InlinedScope,		bool Verify() const;
	LLVMContext &VMContext);		};
	/// cleanseInlinedVariable - Remove inlined scope from the variable.		/// getDISubprogram - Find subprogram that is enclosing this scope.
	DIVariable cleanseInlinedVariable(MDNode *DV, LLVMContext &VMContext);		DISubprogram getDISubprogram(const MDNode *Scope);
	class DebugInfoFinder {		/// getDICompositeType - Find underlying composite type.
	public:		DICompositeType getDICompositeType(DIType T);
	/// processModule - Process entire module and collect debug info
	/// anchors.		/// getOrInsertFnSpecificMDNode - Return a NameMDNode that is suitable
	void processModule(const Module &M);		/// to hold function specific information.
			NamedMDNode *getOrInsertFnSpecificMDNode(Module &M, DISubprogram SP);
	private:
	/// processType - Process DIType.		/// getFnSpecificMDNode - Return a NameMDNode, if available, that is
	void processType(DIType DT);		/// suitable to hold function specific information.
			NamedMDNode *getFnSpecificMDNode(const Module &M, DISubprogram SP);
	/// processLexicalBlock - Process DILexicalBlock.
	void processLexicalBlock(DILexicalBlock LB);		/// createInlinedVariable - Create a new inlined variable based on current
			/// variable.
	/// processSubprogram - Process DISubprogram.		/// @param DV Current Variable.
	void processSubprogram(DISubprogram SP);		/// @param InlinedScope Location at current variable is inlined.
			DIVariable createInlinedVariable(MDNode *DV, MDNode *InlinedScope,
	/// processDeclare - Process DbgDeclareInst.		LLVMContext &VMContext);
	void processDeclare(const DbgDeclareInst *DDI);
			/// cleanseInlinedVariable - Remove inlined scope from the variable.
	/// processLocation - Process DILocation.		DIVariable cleanseInlinedVariable(MDNode *DV, LLVMContext &VMContext);
	void processLocation(DILocation Loc);
			/// Construct DITypeIdentifierMap by going through retained types of each C
	/// addCompileUnit - Add compile unit into CUs.		U.
	bool addCompileUnit(DICompileUnit CU);		DITypeIdentifierMap generateDITypeIdentifierMap(const NamedMDNode *CU_Nodes
			);
	/// addGlobalVariable - Add global variable into GVs.
	bool addGlobalVariable(DIGlobalVariable DIG);		/// Strip debug info in the module if it exists.
			/// To do this, we remove all calls to the debugger intrinsics and any name
	// addSubprogram - Add subprogram into SPs.		d
	bool addSubprogram(DISubprogram SP);		/// metadata for debugging. We also remove debug locations for instructions
			.
	/// addType - Add type into Tys.		/// Return true if module is modified.
	bool addType(DIType DT);		bool StripDebugInfo(Module &M);
	public:		/// Return Debug Info Metadata Version by checking module flags.
	typedef SmallVector<MDNode *, 8>::const_iterator iterator;		unsigned getDebugMetadataVersionFromModule(const Module &M);
	iterator compile_unit_begin() const { return CUs.begin(); }
	iterator compile_unit_end() const { return CUs.end(); }		/// DebugInfoFinder tries to list all debug info MDNodes used in a module.
	iterator subprogram_begin() const { return SPs.begin(); }		To
	iterator subprogram_end() const { return SPs.end(); }		/// list debug info MDNodes used by an instruction, DebugInfoFinder uses
	iterator global_variable_begin() const { return GVs.begin(); }		/// processDeclare, processValue and processLocation to handle DbgDeclareIn
	iterator global_variable_end() const { return GVs.end(); }		st,
	iterator type_begin() const { return TYs.begin(); }		/// DbgValueInst and DbgLoc attached to instructions. processModule will go
	iterator type_end() const { return TYs.end(); }		/// through all DICompileUnits in llvm.dbg.cu and list debug info MDNodes
			/// used by the CUs.
	unsigned compile_unit_count() const { return CUs.size(); }		class DebugInfoFinder {
	unsigned global_variable_count() const { return GVs.size(); }		public:
	unsigned subprogram_count() const { return SPs.size(); }		DebugInfoFinder() : TypeMapInitialized(false) {}
	unsigned type_count() const { return TYs.size(); }
			/// processModule - Process entire module and collect debug info
	private:		/// anchors.
	SmallVector<MDNode *, 8> CUs; // Compile Units		void processModule(const Module &M);
	SmallVector<MDNode *, 8> SPs; // Subprograms
	SmallVector<MDNode *, 8> GVs; // Global Variables;		/// processDeclare - Process DbgDeclareInst.
	SmallVector<MDNode *, 8> TYs; // Types		void processDeclare(const Module &M, const DbgDeclareInst *DDI);
	SmallPtrSet<MDNode *, 64> NodesSeen;		/// Process DbgValueInst.
	};		void processValue(const Module &M, const DbgValueInst *DVI);
			/// processLocation - Process DILocation.
			void processLocation(const Module &M, DILocation Loc);
			/// Clear all lists.
			void reset();
			private:
			/// Initialize TypeIdentifierMap.
			void InitializeTypeMap(const Module &M);
			/// processType - Process DIType.
			void processType(DIType DT);
			/// processLexicalBlock - Process DILexicalBlock.
			void processLexicalBlock(DILexicalBlock LB);
			/// processSubprogram - Process DISubprogram.
			void processSubprogram(DISubprogram SP);
			void processScope(DIScope Scope);
			/// addCompileUnit - Add compile unit into CUs.
			bool addCompileUnit(DICompileUnit CU);
			/// addGlobalVariable - Add global variable into GVs.
			bool addGlobalVariable(DIGlobalVariable DIG);
			// addSubprogram - Add subprogram into SPs.
			bool addSubprogram(DISubprogram SP);
			/// addType - Add type into Tys.
			bool addType(DIType DT);
			bool addScope(DIScope Scope);
			public:
			typedef SmallVectorImpl<MDNode *>::const_iterator iterator;
			iterator compile_unit_begin() const { return CUs.begin(); }
			iterator compile_unit_end() const { return CUs.end(); }
			iterator subprogram_begin() const { return SPs.begin(); }
			iterator subprogram_end() const { return SPs.end(); }
			iterator global_variable_begin() const { return GVs.begin(); }
			iterator global_variable_end() const { return GVs.end(); }
			iterator type_begin() const { return TYs.begin(); }
			iterator type_end() const { return TYs.end(); }
			iterator scope_begin() const { return Scopes.begin(); }
			iterator scope_end() const { return Scopes.end(); }
			unsigned compile_unit_count() const { return CUs.size(); }
			unsigned global_variable_count() const { return GVs.size(); }
			unsigned subprogram_count() const { return SPs.size(); }
			unsigned type_count() const { return TYs.size(); }
			unsigned scope_count() const { return Scopes.size(); }
			private:
			SmallVector<MDNode *, 8> CUs; // Compile Units
			SmallVector<MDNode *, 8> SPs; // Subprograms
			SmallVector<MDNode *, 8> GVs; // Global Variables;
			SmallVector<MDNode *, 8> TYs; // Types
			SmallVector<MDNode *, 8> Scopes; // Scopes
			SmallPtrSet<MDNode *, 64> NodesSeen;
			DITypeIdentifierMap TypeIdentifierMap;
			/// Specify if TypeIdentifierMap is initialized.
			bool TypeMapInitialized;
			};
	} // end namespace llvm		} // end namespace llvm
	#endif		#endif
End of changes. 3 change blocks.
	786 lines changed or deleted		854 lines changed or added

	DebugLoc.h		DebugLoc.h
	skipping to change at line 18		skipping to change at line 18
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This file defines a number of light weight data structures used		// This file defines a number of light weight data structures used
	// to describe and track debug location information.		// to describe and track debug location information.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_SUPPORT_DEBUGLOC_H		#ifndef LLVM_SUPPORT_DEBUGLOC_H
	#define LLVM_SUPPORT_DEBUGLOC_H		#define LLVM_SUPPORT_DEBUGLOC_H
			#include "llvm/Support/DataTypes.h"
	namespace llvm {		namespace llvm {
	template <typename T> struct DenseMapInfo;		template <typename T> struct DenseMapInfo;
	class MDNode;		class MDNode;
	class LLVMContext;		class LLVMContext;
	/// DebugLoc - Debug location id. This is carried by Instruction, SDNode ,		/// DebugLoc - Debug location id. This is carried by Instruction, SDNode ,
	/// and MachineInstr to compactly encode file/line/scope information for an		/// and MachineInstr to compactly encode file/line/scope information for an
	/// operation.		/// operation.
	class DebugLoc {		class DebugLoc {
	friend struct DenseMapInfo<DebugLoc>;		friend struct DenseMapInfo<DebugLoc>;
	skipping to change at line 48		skipping to change at line 50
	/// is not equal to the empty key or DebugLoc().		/// is not equal to the empty key or DebugLoc().
	static DebugLoc getTombstoneKey() {		static DebugLoc getTombstoneKey() {
	DebugLoc DL;		DebugLoc DL;
	DL.LineCol = 2;		DL.LineCol = 2;
	return DL;		return DL;
	}		}
	/// LineCol - This 32-bit value encodes the line and column number for the		/// LineCol - This 32-bit value encodes the line and column number for the
	/// location, encoded as 24-bits for line and 8 bits for col. A value of 0		/// location, encoded as 24-bits for line and 8 bits for col. A value of 0
	/// for either means unknown.		/// for either means unknown.
	unsigned LineCol;		uint32_t LineCol;
	/// ScopeIdx - This is an opaque ID# for Scope/InlinedAt information,		/// ScopeIdx - This is an opaque ID# for Scope/InlinedAt information,
	/// decoded by LLVMContext. 0 is unknown.		/// decoded by LLVMContext. 0 is unknown.
	int ScopeIdx;		int ScopeIdx;
	public:		public:
	DebugLoc() : LineCol(0), ScopeIdx(0) {} // Defaults to unknown.		DebugLoc() : LineCol(0), ScopeIdx(0) {} // Defaults to unknown.
	/// get - Get a new DebugLoc that corresponds to the specified line/col		/// get - Get a new DebugLoc that corresponds to the specified line/col
	/// scope/inline location.		/// scope/inline location.
	static DebugLoc get(unsigned Line, unsigned Col,		static DebugLoc get(unsigned Line, unsigned Col,
End of changes. 2 change blocks.
	1 lines changed or deleted		3 lines changed or added

	DenseMap.h		DenseMap.h
	skipping to change at line 67		skipping to change at line 67
	inline iterator end() {		inline iterator end() {
	return iterator(getBucketsEnd(), getBucketsEnd(), true);		return iterator(getBucketsEnd(), getBucketsEnd(), true);
	}		}
	inline const_iterator begin() const {		inline const_iterator begin() const {
	return empty() ? end() : const_iterator(getBuckets(), getBucketsEnd());		return empty() ? end() : const_iterator(getBuckets(), getBucketsEnd());
	}		}
	inline const_iterator end() const {		inline const_iterator end() const {
	return const_iterator(getBucketsEnd(), getBucketsEnd(), true);		return const_iterator(getBucketsEnd(), getBucketsEnd(), true);
	}		}
	bool empty() const { return getNumEntries() == 0; }		bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const {
			return getNumEntries() == 0;
			}
	unsigned size() const { return getNumEntries(); }		unsigned size() const { return getNumEntries(); }
	/// Grow the densemap so that it has at least Size buckets. Does not shri nk		/// Grow the densemap so that it has at least Size buckets. Does not shri nk
	void resize(size_t Size) {		void resize(size_t Size) {
	if (Size > getNumBuckets())		if (Size > getNumBuckets())
	grow(Size);		grow(Size);
	}		}
	void clear() {		void clear() {
	if (getNumEntries() == 0 && getNumTombstones() == 0) return;		if (getNumEntries() == 0 && getNumTombstones() == 0) return;
	skipping to change at line 224		skipping to change at line 226
	ValueT &operator[](const KeyT &Key) {		ValueT &operator[](const KeyT &Key) {
	return FindAndConstruct(Key).second;		return FindAndConstruct(Key).second;
	}		}
	#if LLVM_HAS_RVALUE_REFERENCES		#if LLVM_HAS_RVALUE_REFERENCES
	value_type& FindAndConstruct(KeyT &&Key) {		value_type& FindAndConstruct(KeyT &&Key) {
	BucketT *TheBucket;		BucketT *TheBucket;
	if (LookupBucketFor(Key, TheBucket))		if (LookupBucketFor(Key, TheBucket))
	return *TheBucket;		return *TheBucket;
	return *InsertIntoBucket(Key, ValueT(), TheBucket);		return *InsertIntoBucket(std::move(Key), ValueT(), TheBucket);
	}		}
	ValueT &operator[](KeyT &&Key) {		ValueT &operator[](KeyT &&Key) {
	return FindAndConstruct(Key).second;		return FindAndConstruct(std::move(Key)).second;
	}		}
	#endif		#endif
	/// isPointerIntoBucketsArray - Return true if the specified pointer poin ts		/// isPointerIntoBucketsArray - Return true if the specified pointer poin ts
	/// somewhere into the DenseMap's array of buckets (i.e. either to a key or		/// somewhere into the DenseMap's array of buckets (i.e. either to a key or
	/// value in the DenseMap).		/// value in the DenseMap).
	bool isPointerIntoBucketsArray(const void *Ptr) const {		bool isPointerIntoBucketsArray(const void *Ptr) const {
	return Ptr >= getBuckets() && Ptr < getBucketsEnd();		return Ptr >= getBuckets() && Ptr < getBucketsEnd();
	}		}
	skipping to change at line 437		skipping to change at line 439
	// tons of tombstones, failing lookups (e.g. for insertion) would have to		// tons of tombstones, failing lookups (e.g. for insertion) would have to
	// probe almost the entire table until it found the empty bucket. If t he		// probe almost the entire table until it found the empty bucket. If t he
	// table completely filled with tombstones, no lookup would ever succee d,		// table completely filled with tombstones, no lookup would ever succee d,
	// causing infinite loops in lookup.		// causing infinite loops in lookup.
	unsigned NewNumEntries = getNumEntries() + 1;		unsigned NewNumEntries = getNumEntries() + 1;
	unsigned NumBuckets = getNumBuckets();		unsigned NumBuckets = getNumBuckets();
	if (NewNumEntries*4 >= NumBuckets*3) {		if (NewNumEntries*4 >= NumBuckets*3) {
	this->grow(NumBuckets * 2);		this->grow(NumBuckets * 2);
	LookupBucketFor(Key, TheBucket);		LookupBucketFor(Key, TheBucket);
	NumBuckets = getNumBuckets();		NumBuckets = getNumBuckets();
	}		} else if (NumBuckets-(NewNumEntries+getNumTombstones()) <= NumBuckets/
	if (NumBuckets-(NewNumEntries+getNumTombstones()) <= NumBuckets/8) {		8) {
	this->grow(NumBuckets * 2);		this->grow(NumBuckets);
	LookupBucketFor(Key, TheBucket);		LookupBucketFor(Key, TheBucket);
	}		}
	assert(TheBucket);		assert(TheBucket);
	// Only update the state after we've grown our bucket space appropriate ly		// Only update the state after we've grown our bucket space appropriate ly
	// so that when growing buckets we have self-consistent entry count.		// so that when growing buckets we have self-consistent entry count.
	incrementNumEntries();		incrementNumEntries();
	// If we are writing over a tombstone, remember this.		// If we are writing over a tombstone, remember this.
	const KeyT EmptyKey = getEmptyKey();		const KeyT EmptyKey = getEmptyKey();
	skipping to change at line 714		skipping to change at line 715
	/// A "union" of an inline bucket array and the struct representing		/// A "union" of an inline bucket array and the struct representing
	/// a large bucket. This union will be discriminated by the 'Small' bit.		/// a large bucket. This union will be discriminated by the 'Small' bit.
	AlignedCharArrayUnion<BucketT[InlineBuckets], LargeRep> storage;		AlignedCharArrayUnion<BucketT[InlineBuckets], LargeRep> storage;
	public:		public:
	explicit SmallDenseMap(unsigned NumInitBuckets = 0) {		explicit SmallDenseMap(unsigned NumInitBuckets = 0) {
	init(NumInitBuckets);		init(NumInitBuckets);
	}		}
	SmallDenseMap(const SmallDenseMap &other) {		SmallDenseMap(const SmallDenseMap &other) : BaseT() {
	init(0);		init(0);
	copyFrom(other);		copyFrom(other);
	}		}
	#if LLVM_HAS_RVALUE_REFERENCES		#if LLVM_HAS_RVALUE_REFERENCES
	SmallDenseMap(SmallDenseMap &&other) {		SmallDenseMap(SmallDenseMap &&other) : BaseT() {
	init(0);		init(0);
	swap(other);		swap(other);
	}		}
	#endif		#endif
	template<typename InputIt>		template<typename InputIt>
	SmallDenseMap(const InputIt &I, const InputIt &E) {		SmallDenseMap(const InputIt &I, const InputIt &E) {
	init(NextPowerOf2(std::distance(I, E)));		init(NextPowerOf2(std::distance(I, E)));
	this->insert(I, E);		this->insert(I, E);
	}		}
End of changes. 6 change blocks.
	8 lines changed or deleted		10 lines changed or added

	DependenceAnalysis.h		DependenceAnalysis.h
	skipping to change at line 64		skipping to change at line 64
	class raw_ostream;		class raw_ostream;
	/// Dependence - This class represents a dependence between two memory		/// Dependence - This class represents a dependence between two memory
	/// memory references in a function. It contains minimal information and		/// memory references in a function. It contains minimal information and
	/// is used in the very common situation where the compiler is unable to		/// is used in the very common situation where the compiler is unable to
	/// determine anything beyond the existence of a dependence; that is, it		/// determine anything beyond the existence of a dependence; that is, it
	/// represents a confused dependence (see also FullDependence). In most		/// represents a confused dependence (see also FullDependence). In most
	/// cases (for output, flow, and anti dependences), the dependence implie s		/// cases (for output, flow, and anti dependences), the dependence implie s
	/// an ordering, where the source must precede the destination; in contra st,		/// an ordering, where the source must precede the destination; in contra st,
	/// input dependences are unordered.		/// input dependences are unordered.
			///
			/// When a dependence graph is built, each Dependence will be a member of
			/// the set of predecessor edges for its destination instruction and a se
			t
			/// if successor edges for its source instruction. These sets are represe
			nted
			/// as singly-linked lists, with the "next" fields stored in the dependen
			ce
			/// itelf.
	class Dependence {		class Dependence {
	public:		public:
	Dependence(Instruction *Source,		Dependence(Instruction *Source,
	Instruction *Destination) :		Instruction *Destination) :
	Src(Source), Dst(Destination) {}		Src(Source),
			Dst(Destination),
			NextPredecessor(NULL),
			NextSuccessor(NULL) {}
	virtual ~Dependence() {}		virtual ~Dependence() {}
	/// Dependence::DVEntry - Each level in the distance/direction vector		/// Dependence::DVEntry - Each level in the distance/direction vector
	/// has a direction (or perhaps a union of several directions), and		/// has a direction (or perhaps a union of several directions), and
	/// perhaps a distance.		/// perhaps a distance.
	struct DVEntry {		struct DVEntry {
	enum { NONE = 0,		enum { NONE = 0,
	LT = 1,		LT = 1,
	EQ = 2,		EQ = 2,
	LE = 3,		LE = 3,
	skipping to change at line 167		skipping to change at line 176
	/// isSplitable - Returns true if splitting this loop will break		/// isSplitable - Returns true if splitting this loop will break
	/// the dependence.		/// the dependence.
	virtual bool isSplitable(unsigned Level) const { return false; }		virtual bool isSplitable(unsigned Level) const { return false; }
	/// isScalar - Returns true if a particular level is scalar; that is,		/// isScalar - Returns true if a particular level is scalar; that is,
	/// if no subscript in the source or destination mention the induction		/// if no subscript in the source or destination mention the induction
	/// variable associated with the loop at this level.		/// variable associated with the loop at this level.
	virtual bool isScalar(unsigned Level) const;		virtual bool isScalar(unsigned Level) const;
			/// getNextPredecessor - Returns the value of the NextPredecessor
			/// field.
			const Dependence *getNextPredecessor() const {
			return NextPredecessor;
			}
			/// getNextSuccessor - Returns the value of the NextSuccessor
			/// field.
			const Dependence *getNextSuccessor() const {
			return NextSuccessor;
			}
			/// setNextPredecessor - Sets the value of the NextPredecessor
			/// field.
			void setNextPredecessor(const Dependence *pred) {
			NextPredecessor = pred;
			}
			/// setNextSuccessor - Sets the value of the NextSuccessor
			/// field.
			void setNextSuccessor(const Dependence *succ) {
			NextSuccessor = succ;
			}
	/// dump - For debugging purposes, dumps a dependence to OS.		/// dump - For debugging purposes, dumps a dependence to OS.
	///		///
	void dump(raw_ostream &OS) const;		void dump(raw_ostream &OS) const;
	private:		private:
	Instruction *Src, *Dst;		Instruction *Src, *Dst;
			const Dependence *NextPredecessor, *NextSuccessor;
	friend class DependenceAnalysis;		friend class DependenceAnalysis;
	};		};
	/// FullDependence - This class represents a dependence between two memor y		/// FullDependence - This class represents a dependence between two memor y
	/// references in a function. It contains detailed information about the		/// references in a function. It contains detailed information about the
	/// dependence (direction vectors, etc.) and is used when the compiler is		/// dependence (direction vectors, etc.) and is used when the compiler is
	/// able to accurately analyze the interaction of the references; that is ,		/// able to accurately analyze the interaction of the references; that is ,
	/// it is not a confused dependence (see Dependence). In most cases		/// it is not a confused dependence (see Dependence). In most cases
	/// (for output, flow, and anti dependences), the dependence implies an		/// (for output, flow, and anti dependences), the dependence implies an
	/// ordering, where the source must precede the destination; in contrast,		/// ordering, where the source must precede the destination; in contrast,
	skipping to change at line 815		skipping to change at line 849
	const Constraint *Y);		const Constraint *Y);
	/// propagate - Review the constraints, looking for opportunities		/// propagate - Review the constraints, looking for opportunities
	/// to simplify a subscript pair (Src and Dst).		/// to simplify a subscript pair (Src and Dst).
	/// Return true if some simplification occurs.		/// Return true if some simplification occurs.
	/// If the simplification isn't exact (that is, if it is conservative		/// If the simplification isn't exact (that is, if it is conservative
	/// in terms of dependence), set consistent to false.		/// in terms of dependence), set consistent to false.
	bool propagate(const SCEV *&Src,		bool propagate(const SCEV *&Src,
	const SCEV *&Dst,		const SCEV *&Dst,
	SmallBitVector &Loops,		SmallBitVector &Loops,
	SmallVector<Constraint, 4> &Constraints,		SmallVectorImpl<Constraint> &Constraints,
	bool &Consistent);		bool &Consistent);
	/// propagateDistance - Attempt to propagate a distance		/// propagateDistance - Attempt to propagate a distance
	/// constraint into a subscript pair (Src and Dst).		/// constraint into a subscript pair (Src and Dst).
	/// Return true if some simplification occurs.		/// Return true if some simplification occurs.
	/// If the simplification isn't exact (that is, if it is conservative		/// If the simplification isn't exact (that is, if it is conservative
	/// in terms of dependence), set consistent to false.		/// in terms of dependence), set consistent to false.
	bool propagateDistance(const SCEV *&Src,		bool propagateDistance(const SCEV *&Src,
	const SCEV *&Dst,		const SCEV *&Dst,
	Constraint &CurConstraint,		Constraint &CurConstraint,
	skipping to change at line 874		skipping to change at line 908
	/// For example, given a*i + b*j + c*k, adding 1 to the coefficient		/// For example, given a*i + b*j + c*k, adding 1 to the coefficient
	/// corresponding to the j loop would yield a*i + (b+1)*j + c*k.		/// corresponding to the j loop would yield a*i + (b+1)*j + c*k.
	const SCEV *addToCoefficient(const SCEV *Expr,		const SCEV *addToCoefficient(const SCEV *Expr,
	const Loop *TargetLoop,		const Loop *TargetLoop,
	const SCEV *Value) const;		const SCEV *Value) const;
	/// updateDirection - Update direction vector entry		/// updateDirection - Update direction vector entry
	/// based on the current constraint.		/// based on the current constraint.
	void updateDirection(Dependence::DVEntry &Level,		void updateDirection(Dependence::DVEntry &Level,
	const Constraint &CurConstraint) const;		const Constraint &CurConstraint) const;
			bool tryDelinearize(const SCEV *SrcSCEV, const SCEV *DstSCEV,
			SmallVectorImpl<Subscript> &Pair) const;
	public:		public:
	static char ID; // Class identification, replacement for typeinfo		static char ID; // Class identification, replacement for typeinfo
	DependenceAnalysis() : FunctionPass(ID) {		DependenceAnalysis() : FunctionPass(ID) {
	initializeDependenceAnalysisPass(*PassRegistry::getPassRegistry());		initializeDependenceAnalysisPass(*PassRegistry::getPassRegistry());
	}		}
	bool runOnFunction(Function &F);		bool runOnFunction(Function &F);
	void releaseMemory();		void releaseMemory();
	void getAnalysisUsage(AnalysisUsage &) const;		void getAnalysisUsage(AnalysisUsage &) const;
	void print(raw_ostream &, const Module * = 0) const;		void print(raw_ostream &, const Module * = 0) const;
End of changes. 6 change blocks.
	2 lines changed or deleted		43 lines changed or added

	Disassembler.h		Disassembler.h
	skipping to change at line 133		skipping to change at line 133
	/* The input reference is from a PC relative load instruction. */		/* The input reference is from a PC relative load instruction. */
	#define LLVMDisassembler_ReferenceType_In_PCrel_Load 2		#define LLVMDisassembler_ReferenceType_In_PCrel_Load 2
	/* The output reference is to as symbol stub. */		/* The output reference is to as symbol stub. */
	#define LLVMDisassembler_ReferenceType_Out_SymbolStub 1		#define LLVMDisassembler_ReferenceType_Out_SymbolStub 1
	/* The output reference is to a symbol address in a literal pool. */		/* The output reference is to a symbol address in a literal pool. */
	#define LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr 2		#define LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr 2
	/* The output reference is to a cstring address in a literal pool. */		/* The output reference is to a cstring address in a literal pool. */
	#define LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr 3		#define LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr 3
			/* The output reference is to a Objective-C CoreFoundation string. */
			#define LLVMDisassembler_ReferenceType_Out_Objc_CFString_Ref 4
			/* The output reference is to a Objective-C message. */
			#define LLVMDisassembler_ReferenceType_Out_Objc_Message 5
			/* The output reference is to a Objective-C message ref. */
			#define LLVMDisassembler_ReferenceType_Out_Objc_Message_Ref 6
			/* The output reference is to a Objective-C selector ref. */
			#define LLVMDisassembler_ReferenceType_Out_Objc_Selector_Ref 7
			/* The output reference is to a Objective-C class ref. */
			#define LLVMDisassembler_ReferenceType_Out_Objc_Class_Ref 8
	#ifdef __cplusplus		#ifdef __cplusplus
	extern "C" {		extern "C" {
	#endif /* !defined(__cplusplus) */		#endif /* !defined(__cplusplus) */
	/**		/**
	* Create a disassembler for the TripleName. Symbolic disassembly is suppo rted		* Create a disassembler for the TripleName. Symbolic disassembly is suppo rted
	* by passing a block of information in the DisInfo parameter and specifyin g the		* by passing a block of information in the DisInfo parameter and specifyin g the
	* TagType and callback functions as described above. These can all be pas sed		* TagType and callback functions as described above. These can all be pas sed
	* as NULL. If successful, this returns a disassembler context. If not, i t		* as NULL. If successful, this returns a disassembler context. If not, i t
	* returns NULL. This function is equivalent to calling LLVMCreateDisasmCPU ()		* returns NULL. This function is equivalent to calling LLVMCreateDisasmCPU ()
	skipping to change at line 173		skipping to change at line 184
	* otherwise.		* otherwise.
	*/		*/
	int LLVMSetDisasmOptions(LLVMDisasmContextRef DC, uint64_t Options);		int LLVMSetDisasmOptions(LLVMDisasmContextRef DC, uint64_t Options);
	/* The option to produce marked up assembly. */		/* The option to produce marked up assembly. */
	#define LLVMDisassembler_Option_UseMarkup 1		#define LLVMDisassembler_Option_UseMarkup 1
	/* The option to print immediates as hex. */		/* The option to print immediates as hex. */
	#define LLVMDisassembler_Option_PrintImmHex 2		#define LLVMDisassembler_Option_PrintImmHex 2
	/* The option use the other assembler printer variant */		/* The option use the other assembler printer variant */
	#define LLVMDisassembler_Option_AsmPrinterVariant 4		#define LLVMDisassembler_Option_AsmPrinterVariant 4
			/* The option to set comment on instructions */
			#define LLVMDisassembler_Option_SetInstrComments 8
			/* The option to print latency information alongside instructions */
			#define LLVMDisassembler_Option_PrintLatency 16
	/**		/**
	* Dispose of a disassembler context.		* Dispose of a disassembler context.
	*/		*/
	void LLVMDisasmDispose(LLVMDisasmContextRef DC);		void LLVMDisasmDispose(LLVMDisasmContextRef DC);
	/**		/**
	* Disassemble a single instruction using the disassembler context specifie d in		* Disassemble a single instruction using the disassembler context specifie d in
	* the parameter DC. The bytes of the instruction are specified in the		* the parameter DC. The bytes of the instruction are specified in the
	* parameter Bytes, and contains at least BytesSize number of bytes. The		* parameter Bytes, and contains at least BytesSize number of bytes. The
End of changes. 2 change blocks.
	0 lines changed or deleted		15 lines changed or added

	Disassemblers.def		Disassemblers.def
	skipping to change at line 27		skipping to change at line 27
	|* The set of targets supported by LLVM is generated at configuration *|		|* The set of targets supported by LLVM is generated at configuration *|
	|* time, at which point this header is generated. Do not modify this *|		|* time, at which point this header is generated. Do not modify this *|
	|* header directly. *|		|* header directly. *|
	|* *|		|* *|
	\*===---------------------------------------------------------------------- ===*/		\*===---------------------------------------------------------------------- ===*/
	#ifndef LLVM_DISASSEMBLER		#ifndef LLVM_DISASSEMBLER
	# error Please define the macro LLVM_DISASSEMBLER(TargetName)		# error Please define the macro LLVM_DISASSEMBLER(TargetName)
	#endif		#endif
	LLVM_DISASSEMBLER(MBlaze) LLVM_DISASSEMBLER(XCore) LLVM_DISASSEMBLER(Mips) LLVM_DISASSEMBLER(ARM) LLVM_DISASSEMBLER(AArch64) LLVM_DISASSEMBLER(X86)		LLVM_DISASSEMBLER(SystemZ) LLVM_DISASSEMBLER(XCore) LLVM_DISASSEMBLER(Mips) LLVM_DISASSEMBLER(ARM) LLVM_DISASSEMBLER(AArch64) LLVM_DISASSEMBLER(X86)
	#undef LLVM_DISASSEMBLER		#undef LLVM_DISASSEMBLER
End of changes. 1 change blocks.
	1 lines changed or deleted		1 lines changed or added

	Dominators.h		Dominators.h
	skipping to change at line 348		skipping to change at line 348
	/// getRootNode - This returns the entry node for the CFG of the function . If		/// getRootNode - This returns the entry node for the CFG of the function . If
	/// this tree represents the post-dominance relations for a function, how ever,		/// this tree represents the post-dominance relations for a function, how ever,
	/// this root may be a node with the block == NULL. This is the case whe n		/// this root may be a node with the block == NULL. This is the case whe n
	/// there are multiple exit nodes from a particular function. Consumers of		/// there are multiple exit nodes from a particular function. Consumers of
	/// post-dominance information must be capable of dealing with this		/// post-dominance information must be capable of dealing with this
	/// possibility.		/// possibility.
	///		///
	DomTreeNodeBase<NodeT> *getRootNode() { return RootNode; }		DomTreeNodeBase<NodeT> *getRootNode() { return RootNode; }
	const DomTreeNodeBase<NodeT> *getRootNode() const { return RootNode; }		const DomTreeNodeBase<NodeT> *getRootNode() const { return RootNode; }
			/// Get all nodes dominated by R, including R itself. Return true on succ
			ess.
			void getDescendants(NodeT *R, SmallVectorImpl<NodeT *> &Result) const {
			const DomTreeNodeBase<NodeT> *RN = getNode(R);
			SmallVector<const DomTreeNodeBase<NodeT> *, 8> WL;
			WL.push_back(RN);
			Result.clear();
			while (!WL.empty()) {
			const DomTreeNodeBase<NodeT> *N = WL.pop_back_val();
			Result.push_back(N->getBlock());
			WL.append(N->begin(), N->end());
			}
			}
	/// properlyDominates - Returns true iff A dominates B and A != B.		/// properlyDominates - Returns true iff A dominates B and A != B.
	/// Note that this is not a constant time operation!		/// Note that this is not a constant time operation!
	///		///
	bool properlyDominates(const DomTreeNodeBase<NodeT> *A,		bool properlyDominates(const DomTreeNodeBase<NodeT> *A,
	const DomTreeNodeBase<NodeT> *B) {		const DomTreeNodeBase<NodeT> *B) {
	if (A == 0 || B == 0)		if (A == 0 || B == 0)
	return false;		return false;
	if (A == B)		if (A == B)
	return false;		return false;
	return dominates(A, B);		return dominates(A, B);
	skipping to change at line 757		skipping to change at line 771
	}		}
	inline BasicBlock *getRoot() const {		inline BasicBlock *getRoot() const {
	return DT->getRoot();		return DT->getRoot();
	}		}
	inline DomTreeNode *getRootNode() const {		inline DomTreeNode *getRootNode() const {
	return DT->getRootNode();		return DT->getRootNode();
	}		}
			/// Get all nodes dominated by R, including R itself. Return true on succ
			ess.
			void getDescendants(BasicBlock *R,
			SmallVectorImpl<BasicBlock *> &Result) const {
			DT->getDescendants(R, Result);
			}
	/// compare - Return false if the other dominator tree matches this		/// compare - Return false if the other dominator tree matches this
	/// dominator tree. Otherwise return true.		/// dominator tree. Otherwise return true.
	inline bool compare(DominatorTree &Other) const {		inline bool compare(DominatorTree &Other) const {
	DomTreeNode *R = getRootNode();		DomTreeNode *R = getRootNode();
	DomTreeNode *OtherR = Other.getRootNode();		DomTreeNode *OtherR = Other.getRootNode();
	if (!R || !OtherR || R->getBlock() != OtherR->getBlock())		if (!R || !OtherR || R->getBlock() != OtherR->getBlock())
	return true;		return true;
	if (DT->compare(Other.getBase()))		if (DT->compare(Other.getBase()))
End of changes. 2 change blocks.
	0 lines changed or deleted		22 lines changed or added

	Dwarf.h		Dwarf.h
	skipping to change at line 19		skipping to change at line 19
	//		//
	// This file contains constants used for implementing Dwarf debug support. For		// This file contains constants used for implementing Dwarf debug support. For
	// Details on the Dwarf 3 specfication see DWARF Debugging Information Form at		// Details on the Dwarf 3 specfication see DWARF Debugging Information Form at
	// V.3 reference manual http://dwarf.freestandards.org ,		// V.3 reference manual http://dwarf.freestandards.org ,
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_SUPPORT_DWARF_H		#ifndef LLVM_SUPPORT_DWARF_H
	#define LLVM_SUPPORT_DWARF_H		#define LLVM_SUPPORT_DWARF_H
			#include "llvm/Support/Compiler.h"
	#include "llvm/Support/DataTypes.h"		#include "llvm/Support/DataTypes.h"
	namespace llvm {		namespace llvm {
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// Debug info constants.		// Debug info constants.
	enum {		enum LLVM_ENUM_INT_TYPE(uint32_t) {
	LLVMDebugVersion = (12 << 16), // Current version of debug informa		LLVMDebugVersion = (12 << 16), // Current version of debug information
	tion.		.
	LLVMDebugVersion11 = (11 << 16), // Constant for version 11.		LLVMDebugVersion11 = (11 << 16), // Constant for version 11.
	LLVMDebugVersion10 = (10 << 16), // Constant for version 10.		LLVMDebugVersion10 = (10 << 16), // Constant for version 10.
	LLVMDebugVersion9 = (9 << 16), // Constant for version 9.		LLVMDebugVersion9 = (9 << 16), // Constant for version 9.
	LLVMDebugVersion8 = (8 << 16), // Constant for version 8.		LLVMDebugVersion8 = (8 << 16), // Constant for version 8.
	LLVMDebugVersion7 = (7 << 16), // Constant for version 7.		LLVMDebugVersion7 = (7 << 16), // Constant for version 7.
	LLVMDebugVersion6 = (6 << 16), // Constant for version 6.		LLVMDebugVersion6 = (6 << 16), // Constant for version 6.
	LLVMDebugVersion5 = (5 << 16), // Constant for version 5.		LLVMDebugVersion5 = (5 << 16), // Constant for version 5.
	LLVMDebugVersion4 = (4 << 16), // Constant for version 4.		LLVMDebugVersion4 = (4 << 16), // Constant for version 4.
	LLVMDebugVersionMask = 0xffff0000 // Mask for version number.		LLVMDebugVersionMask = 0xffff0000 // Mask for version number.
	};		};
	namespace dwarf {		namespace dwarf {
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// Dwarf constants as gleaned from the DWARF Debugging Information Format V .4		// Dwarf constants as gleaned from the DWARF Debugging Information Format V .4
	// reference manual http://dwarf.freestandards.org .		// reference manual http://dwarf.freestandards.org.
	//		//
	// Do not mix the following two enumerations sets. DW_TAG_invalid changes the		// Do not mix the following two enumerations sets. DW_TAG_invalid changes the
	// enumeration base type.		// enumeration base type.
	enum llvm_dwarf_constants {		enum LLVMConstants LLVM_ENUM_INT_TYPE(uint32_t) {
	// llvm mock tags		// llvm mock tags
	DW_TAG_invalid = ~0U, // Tag for invalid results.		DW_TAG_invalid = ~0U, // Tag for invalid results.
	DW_TAG_auto_variable = 0x100, // Tag for local (auto) variables.		DW_TAG_auto_variable = 0x100, // Tag for local (auto) variables.
	DW_TAG_arg_variable = 0x101, // Tag for argument variables.		DW_TAG_arg_variable = 0x101, // Tag for argument variables.
	DW_TAG_user_base = 0x1000, // Recommended base for user tags.		DW_TAG_user_base = 0x1000, // Recommended base for user tags.
	DW_CIE_VERSION = 1 // Common frame information version		DWARF_VERSION = 4, // Default dwarf version we output.
	.		DW_CIE_VERSION = 1, // Common frame information version.
			DW_PUBTYPES_VERSION = 2, // Section version number for .debug_pubtypes.
			DW_PUBNAMES_VERSION = 2, // Section version number for .debug_pubnames.
			DW_ARANGES_VERSION = 2 // Section version number for .debug_aranges.
	};		};
	// Special ID values that distinguish a CIE from a FDE in DWARF CFI.		// Special ID values that distinguish a CIE from a FDE in DWARF CFI.
	// Not inside an enum because a 64-bit value is needed.		// Not inside an enum because a 64-bit value is needed.
	const uint32_t DW_CIE_ID = UINT32_MAX;		const uint32_t DW_CIE_ID = UINT32_MAX;
	const uint64_t DW64_CIE_ID = UINT64_MAX;		const uint64_t DW64_CIE_ID = UINT64_MAX;
	enum dwarf_constants {		enum Tag LLVM_ENUM_INT_TYPE(uint16_t) {
	DWARF_VERSION = 2,
	// Tags
	DW_TAG_array_type = 0x01,		DW_TAG_array_type = 0x01,
	DW_TAG_class_type = 0x02,		DW_TAG_class_type = 0x02,
	DW_TAG_entry_point = 0x03,		DW_TAG_entry_point = 0x03,
	DW_TAG_enumeration_type = 0x04,		DW_TAG_enumeration_type = 0x04,
	DW_TAG_formal_parameter = 0x05,		DW_TAG_formal_parameter = 0x05,
	DW_TAG_imported_declaration = 0x08,		DW_TAG_imported_declaration = 0x08,
	DW_TAG_label = 0x0a,		DW_TAG_label = 0x0a,
	DW_TAG_lexical_block = 0x0b,		DW_TAG_lexical_block = 0x0b,
	DW_TAG_member = 0x0d,		DW_TAG_member = 0x0d,
	DW_TAG_pointer_type = 0x0f,		DW_TAG_pointer_type = 0x0f,
	skipping to change at line 139		skipping to change at line 141
	DW_TAG_template_alias = 0x43,		DW_TAG_template_alias = 0x43,
	DW_TAG_MIPS_loop = 0x4081,		DW_TAG_MIPS_loop = 0x4081,
	DW_TAG_format_label = 0x4101,		DW_TAG_format_label = 0x4101,
	DW_TAG_function_template = 0x4102,		DW_TAG_function_template = 0x4102,
	DW_TAG_class_template = 0x4103,		DW_TAG_class_template = 0x4103,
	DW_TAG_GNU_template_template_param = 0x4106,		DW_TAG_GNU_template_template_param = 0x4106,
	DW_TAG_GNU_template_parameter_pack = 0x4107,		DW_TAG_GNU_template_parameter_pack = 0x4107,
	DW_TAG_GNU_formal_parameter_pack = 0x4108,		DW_TAG_GNU_formal_parameter_pack = 0x4108,
	DW_TAG_lo_user = 0x4080,		DW_TAG_lo_user = 0x4080,
	DW_TAG_APPLE_property = 0x4200,		DW_TAG_APPLE_property = 0x4200,
	DW_TAG_hi_user = 0xffff,		DW_TAG_hi_user = 0xffff
			};
	// Children flag		inline bool isType(Tag T) {
	DW_CHILDREN_no = 0x00,		switch (T) {
	DW_CHILDREN_yes = 0x01,		case DW_TAG_array_type:
			case DW_TAG_class_type:
			case DW_TAG_interface_type:
			case DW_TAG_enumeration_type:
			case DW_TAG_pointer_type:
			case DW_TAG_reference_type:
			case DW_TAG_rvalue_reference_type:
			case DW_TAG_string_type:
			case DW_TAG_structure_type:
			case DW_TAG_subroutine_type:
			case DW_TAG_union_type:
			case DW_TAG_ptr_to_member_type:
			case DW_TAG_set_type:
			case DW_TAG_subrange_type:
			case DW_TAG_base_type:
			case DW_TAG_const_type:
			case DW_TAG_file_type:
			case DW_TAG_packed_type:
			case DW_TAG_volatile_type:
			case DW_TAG_typedef:
			return true;
			default:
			return false;
			}
			}
			enum Attribute LLVM_ENUM_INT_TYPE(uint16_t) {
	// Attributes		// Attributes
	DW_AT_sibling = 0x01,		DW_AT_sibling = 0x01,
	DW_AT_location = 0x02,		DW_AT_location = 0x02,
	DW_AT_name = 0x03,		DW_AT_name = 0x03,
	DW_AT_ordering = 0x09,		DW_AT_ordering = 0x09,
	DW_AT_byte_size = 0x0b,		DW_AT_byte_size = 0x0b,
	DW_AT_bit_offset = 0x0c,		DW_AT_bit_offset = 0x0c,
	DW_AT_bit_size = 0x0d,		DW_AT_bit_size = 0x0d,
	DW_AT_stmt_list = 0x10,		DW_AT_stmt_list = 0x10,
	DW_AT_low_pc = 0x11,		DW_AT_low_pc = 0x11,
	skipping to change at line 272		skipping to change at line 300
	// GNU extensions		// GNU extensions
	DW_AT_sf_names = 0x2101,		DW_AT_sf_names = 0x2101,
	DW_AT_src_info = 0x2102,		DW_AT_src_info = 0x2102,
	DW_AT_mac_info = 0x2103,		DW_AT_mac_info = 0x2103,
	DW_AT_src_coords = 0x2104,		DW_AT_src_coords = 0x2104,
	DW_AT_body_begin = 0x2105,		DW_AT_body_begin = 0x2105,
	DW_AT_body_end = 0x2106,		DW_AT_body_end = 0x2106,
	DW_AT_GNU_vector = 0x2107,		DW_AT_GNU_vector = 0x2107,
	DW_AT_GNU_template_name = 0x2110,		DW_AT_GNU_template_name = 0x2110,
			DW_AT_GNU_odr_signature = 0x210f,
	// Extensions for Fission proposal.		// Extensions for Fission proposal.
	DW_AT_GNU_dwo_name = 0x2130,		DW_AT_GNU_dwo_name = 0x2130,
	DW_AT_GNU_dwo_id = 0x2131,		DW_AT_GNU_dwo_id = 0x2131,
	DW_AT_GNU_ranges_base = 0x2132,		DW_AT_GNU_ranges_base = 0x2132,
	DW_AT_GNU_addr_base = 0x2133,		DW_AT_GNU_addr_base = 0x2133,
	DW_AT_GNU_pubnames = 0x2134,		DW_AT_GNU_pubnames = 0x2134,
	DW_AT_GNU_pubtypes = 0x2135,		DW_AT_GNU_pubtypes = 0x2135,
	// Apple extensions.		// Apple extensions.
	DW_AT_APPLE_optimized = 0x3fe1,		DW_AT_APPLE_optimized = 0x3fe1,
	skipping to change at line 293		skipping to change at line 323
	DW_AT_APPLE_isa = 0x3fe3,		DW_AT_APPLE_isa = 0x3fe3,
	DW_AT_APPLE_block = 0x3fe4,		DW_AT_APPLE_block = 0x3fe4,
	DW_AT_APPLE_major_runtime_vers = 0x3fe5,		DW_AT_APPLE_major_runtime_vers = 0x3fe5,
	DW_AT_APPLE_runtime_class = 0x3fe6,		DW_AT_APPLE_runtime_class = 0x3fe6,
	DW_AT_APPLE_omit_frame_ptr = 0x3fe7,		DW_AT_APPLE_omit_frame_ptr = 0x3fe7,
	DW_AT_APPLE_property_name = 0x3fe8,		DW_AT_APPLE_property_name = 0x3fe8,
	DW_AT_APPLE_property_getter = 0x3fe9,		DW_AT_APPLE_property_getter = 0x3fe9,
	DW_AT_APPLE_property_setter = 0x3fea,		DW_AT_APPLE_property_setter = 0x3fea,
	DW_AT_APPLE_property_attribute = 0x3feb,		DW_AT_APPLE_property_attribute = 0x3feb,
	DW_AT_APPLE_objc_complete_type = 0x3fec,		DW_AT_APPLE_objc_complete_type = 0x3fec,
	DW_AT_APPLE_property = 0x3fed,		DW_AT_APPLE_property = 0x3fed
			};
			enum Form LLVM_ENUM_INT_TYPE(uint16_t) {
	// Attribute form encodings		// Attribute form encodings
	DW_FORM_addr = 0x01,		DW_FORM_addr = 0x01,
	DW_FORM_block2 = 0x03,		DW_FORM_block2 = 0x03,
	DW_FORM_block4 = 0x04,		DW_FORM_block4 = 0x04,
	DW_FORM_data2 = 0x05,		DW_FORM_data2 = 0x05,
	DW_FORM_data4 = 0x06,		DW_FORM_data4 = 0x06,
	DW_FORM_data8 = 0x07,		DW_FORM_data8 = 0x07,
	DW_FORM_string = 0x08,		DW_FORM_string = 0x08,
	DW_FORM_block = 0x09,		DW_FORM_block = 0x09,
	DW_FORM_block1 = 0x0a,		DW_FORM_block1 = 0x0a,
	skipping to change at line 324		skipping to change at line 356
	DW_FORM_ref8 = 0x14,		DW_FORM_ref8 = 0x14,
	DW_FORM_ref_udata = 0x15,		DW_FORM_ref_udata = 0x15,
	DW_FORM_indirect = 0x16,		DW_FORM_indirect = 0x16,
	DW_FORM_sec_offset = 0x17,		DW_FORM_sec_offset = 0x17,
	DW_FORM_exprloc = 0x18,		DW_FORM_exprloc = 0x18,
	DW_FORM_flag_present = 0x19,		DW_FORM_flag_present = 0x19,
	DW_FORM_ref_sig8 = 0x20,		DW_FORM_ref_sig8 = 0x20,
	// Extensions for Fission proposal		// Extensions for Fission proposal
	DW_FORM_GNU_addr_index = 0x1f01,		DW_FORM_GNU_addr_index = 0x1f01,
	DW_FORM_GNU_str_index = 0x1f02,		DW_FORM_GNU_str_index = 0x1f02
			};
			enum LocationAtom {
	// Operation encodings		// Operation encodings
	DW_OP_addr = 0x03,		DW_OP_addr = 0x03,
	DW_OP_deref = 0x06,		DW_OP_deref = 0x06,
	DW_OP_const1u = 0x08,		DW_OP_const1u = 0x08,
	DW_OP_const1s = 0x09,		DW_OP_const1s = 0x09,
	DW_OP_const2u = 0x0a,		DW_OP_const2u = 0x0a,
	DW_OP_const2s = 0x0b,		DW_OP_const2s = 0x0b,
	DW_OP_const4u = 0x0c,		DW_OP_const4u = 0x0c,
	DW_OP_const4s = 0x0d,		DW_OP_const4s = 0x0d,
	DW_OP_const8u = 0x0e,		DW_OP_const8u = 0x0e,
	skipping to change at line 484		skipping to change at line 518
	DW_OP_call4 = 0x99,		DW_OP_call4 = 0x99,
	DW_OP_call_ref = 0x9a,		DW_OP_call_ref = 0x9a,
	DW_OP_form_tls_address = 0x9b,		DW_OP_form_tls_address = 0x9b,
	DW_OP_call_frame_cfa = 0x9c,		DW_OP_call_frame_cfa = 0x9c,
	DW_OP_bit_piece = 0x9d,		DW_OP_bit_piece = 0x9d,
	DW_OP_implicit_value = 0x9e,		DW_OP_implicit_value = 0x9e,
	DW_OP_stack_value = 0x9f,		DW_OP_stack_value = 0x9f,
	DW_OP_lo_user = 0xe0,		DW_OP_lo_user = 0xe0,
	DW_OP_hi_user = 0xff,		DW_OP_hi_user = 0xff,
			// Extensions for GNU-style thread-local storage.
			DW_OP_GNU_push_tls_address = 0xe0,
	// Extensions for Fission proposal.		// Extensions for Fission proposal.
	DW_OP_GNU_addr_index = 0xfb,		DW_OP_GNU_addr_index = 0xfb,
	DW_OP_GNU_const_index = 0xfc,		DW_OP_GNU_const_index = 0xfc
			};
			enum TypeKind {
	// Encoding attribute values		// Encoding attribute values
	DW_ATE_address = 0x01,		DW_ATE_address = 0x01,
	DW_ATE_boolean = 0x02,		DW_ATE_boolean = 0x02,
	DW_ATE_complex_float = 0x03,		DW_ATE_complex_float = 0x03,
	DW_ATE_float = 0x04,		DW_ATE_float = 0x04,
	DW_ATE_signed = 0x05,		DW_ATE_signed = 0x05,
	DW_ATE_signed_char = 0x06,		DW_ATE_signed_char = 0x06,
	DW_ATE_unsigned = 0x07,		DW_ATE_unsigned = 0x07,
	DW_ATE_unsigned_char = 0x08,		DW_ATE_unsigned_char = 0x08,
	DW_ATE_imaginary_float = 0x09,		DW_ATE_imaginary_float = 0x09,
	DW_ATE_packed_decimal = 0x0a,		DW_ATE_packed_decimal = 0x0a,
	DW_ATE_numeric_string = 0x0b,		DW_ATE_numeric_string = 0x0b,
	DW_ATE_edited = 0x0c,		DW_ATE_edited = 0x0c,
	DW_ATE_signed_fixed = 0x0d,		DW_ATE_signed_fixed = 0x0d,
	DW_ATE_unsigned_fixed = 0x0e,		DW_ATE_unsigned_fixed = 0x0e,
	DW_ATE_decimal_float = 0x0f,		DW_ATE_decimal_float = 0x0f,
	DW_ATE_UTF = 0x10,		DW_ATE_UTF = 0x10,
	DW_ATE_lo_user = 0x80,		DW_ATE_lo_user = 0x80,
	DW_ATE_hi_user = 0xff,		DW_ATE_hi_user = 0xff
			};
			enum DecimalSignEncoding {
	// Decimal sign attribute values		// Decimal sign attribute values
	DW_DS_unsigned = 0x01,		DW_DS_unsigned = 0x01,
	DW_DS_leading_overpunch = 0x02,		DW_DS_leading_overpunch = 0x02,
	DW_DS_trailing_overpunch = 0x03,		DW_DS_trailing_overpunch = 0x03,
	DW_DS_leading_separate = 0x04,		DW_DS_leading_separate = 0x04,
	DW_DS_trailing_separate = 0x05,		DW_DS_trailing_separate = 0x05
			};
			enum EndianityEncoding {
	// Endianity attribute values		// Endianity attribute values
	DW_END_default = 0x00,		DW_END_default = 0x00,
	DW_END_big = 0x01,		DW_END_big = 0x01,
	DW_END_little = 0x02,		DW_END_little = 0x02,
	DW_END_lo_user = 0x40,		DW_END_lo_user = 0x40,
	DW_END_hi_user = 0xff,		DW_END_hi_user = 0xff
			};
			enum AccessAttribute {
	// Accessibility codes		// Accessibility codes
	DW_ACCESS_public = 0x01,		DW_ACCESS_public = 0x01,
	DW_ACCESS_protected = 0x02,		DW_ACCESS_protected = 0x02,
	DW_ACCESS_private = 0x03,		DW_ACCESS_private = 0x03
			};
			enum VisibilityAttribute {
	// Visibility codes		// Visibility codes
	DW_VIS_local = 0x01,		DW_VIS_local = 0x01,
	DW_VIS_exported = 0x02,		DW_VIS_exported = 0x02,
	DW_VIS_qualified = 0x03,		DW_VIS_qualified = 0x03
			};
			enum VirtualityAttribute {
	// Virtuality codes		// Virtuality codes
	DW_VIRTUALITY_none = 0x00,		DW_VIRTUALITY_none = 0x00,
	DW_VIRTUALITY_virtual = 0x01,		DW_VIRTUALITY_virtual = 0x01,
	DW_VIRTUALITY_pure_virtual = 0x02,		DW_VIRTUALITY_pure_virtual = 0x02
			};
			enum SourceLanguage {
	// Language names		// Language names
	DW_LANG_C89 = 0x0001,		DW_LANG_C89 = 0x0001,
	DW_LANG_C = 0x0002,		DW_LANG_C = 0x0002,
	DW_LANG_Ada83 = 0x0003,		DW_LANG_Ada83 = 0x0003,
	DW_LANG_C_plus_plus = 0x0004,		DW_LANG_C_plus_plus = 0x0004,
	DW_LANG_Cobol74 = 0x0005,		DW_LANG_Cobol74 = 0x0005,
	DW_LANG_Cobol85 = 0x0006,		DW_LANG_Cobol85 = 0x0006,
	DW_LANG_Fortran77 = 0x0007,		DW_LANG_Fortran77 = 0x0007,
	DW_LANG_Fortran90 = 0x0008,		DW_LANG_Fortran90 = 0x0008,
	DW_LANG_Pascal83 = 0x0009,		DW_LANG_Pascal83 = 0x0009,
	skipping to change at line 560		skipping to change at line 611
	DW_LANG_Ada95 = 0x000d,		DW_LANG_Ada95 = 0x000d,
	DW_LANG_Fortran95 = 0x000e,		DW_LANG_Fortran95 = 0x000e,
	DW_LANG_PLI = 0x000f,		DW_LANG_PLI = 0x000f,
	DW_LANG_ObjC = 0x0010,		DW_LANG_ObjC = 0x0010,
	DW_LANG_ObjC_plus_plus = 0x0011,		DW_LANG_ObjC_plus_plus = 0x0011,
	DW_LANG_UPC = 0x0012,		DW_LANG_UPC = 0x0012,
	DW_LANG_D = 0x0013,		DW_LANG_D = 0x0013,
	DW_LANG_Python = 0x0014,		DW_LANG_Python = 0x0014,
	DW_LANG_lo_user = 0x8000,		DW_LANG_lo_user = 0x8000,
	DW_LANG_Mips_Assembler = 0x8001,		DW_LANG_Mips_Assembler = 0x8001,
	DW_LANG_hi_user = 0xffff,		DW_LANG_hi_user = 0xffff
			};
			enum CaseSensitivity {
	// Identifier case codes		// Identifier case codes
	DW_ID_case_sensitive = 0x00,		DW_ID_case_sensitive = 0x00,
	DW_ID_up_case = 0x01,		DW_ID_up_case = 0x01,
	DW_ID_down_case = 0x02,		DW_ID_down_case = 0x02,
	DW_ID_case_insensitive = 0x03,		DW_ID_case_insensitive = 0x03
			};
			enum CallingConvention {
	// Calling convention codes		// Calling convention codes
	DW_CC_normal = 0x01,		DW_CC_normal = 0x01,
	DW_CC_program = 0x02,		DW_CC_program = 0x02,
	DW_CC_nocall = 0x03,		DW_CC_nocall = 0x03,
	DW_CC_lo_user = 0x40,		DW_CC_lo_user = 0x40,
	DW_CC_hi_user = 0xff,		DW_CC_hi_user = 0xff
			};
			enum InlineAttribute {
	// Inline codes		// Inline codes
	DW_INL_not_inlined = 0x00,		DW_INL_not_inlined = 0x00,
	DW_INL_inlined = 0x01,		DW_INL_inlined = 0x01,
	DW_INL_declared_not_inlined = 0x02,		DW_INL_declared_not_inlined = 0x02,
	DW_INL_declared_inlined = 0x03,		DW_INL_declared_inlined = 0x03
			};
			enum ArrayDimensionOrdering {
	// Array ordering		// Array ordering
	DW_ORD_row_major = 0x00,		DW_ORD_row_major = 0x00,
	DW_ORD_col_major = 0x01,		DW_ORD_col_major = 0x01
			};
			enum DiscriminantList {
	// Discriminant descriptor values		// Discriminant descriptor values
	DW_DSC_label = 0x00,		DW_DSC_label = 0x00,
	DW_DSC_range = 0x01,		DW_DSC_range = 0x01
			};
			enum LineNumberOps {
	// Line Number Standard Opcode Encodings		// Line Number Standard Opcode Encodings
	DW_LNS_extended_op = 0x00,		DW_LNS_extended_op = 0x00,
	DW_LNS_copy = 0x01,		DW_LNS_copy = 0x01,
	DW_LNS_advance_pc = 0x02,		DW_LNS_advance_pc = 0x02,
	DW_LNS_advance_line = 0x03,		DW_LNS_advance_line = 0x03,
	DW_LNS_set_file = 0x04,		DW_LNS_set_file = 0x04,
	DW_LNS_set_column = 0x05,		DW_LNS_set_column = 0x05,
	DW_LNS_negate_stmt = 0x06,		DW_LNS_negate_stmt = 0x06,
	DW_LNS_set_basic_block = 0x07,		DW_LNS_set_basic_block = 0x07,
	DW_LNS_const_add_pc = 0x08,		DW_LNS_const_add_pc = 0x08,
	DW_LNS_fixed_advance_pc = 0x09,		DW_LNS_fixed_advance_pc = 0x09,
	DW_LNS_set_prologue_end = 0x0a,		DW_LNS_set_prologue_end = 0x0a,
	DW_LNS_set_epilogue_begin = 0x0b,		DW_LNS_set_epilogue_begin = 0x0b,
	DW_LNS_set_isa = 0x0c,		DW_LNS_set_isa = 0x0c
			};
			enum LineNumberExtendedOps {
	// Line Number Extended Opcode Encodings		// Line Number Extended Opcode Encodings
	DW_LNE_end_sequence = 0x01,		DW_LNE_end_sequence = 0x01,
	DW_LNE_set_address = 0x02,		DW_LNE_set_address = 0x02,
	DW_LNE_define_file = 0x03,		DW_LNE_define_file = 0x03,
	DW_LNE_set_discriminator = 0x04,		DW_LNE_set_discriminator = 0x04,
	DW_LNE_lo_user = 0x80,		DW_LNE_lo_user = 0x80,
	DW_LNE_hi_user = 0xff,		DW_LNE_hi_user = 0xff
			};
			enum MacinfoRecordType {
	// Macinfo Type Encodings		// Macinfo Type Encodings
	DW_MACINFO_define = 0x01,		DW_MACINFO_define = 0x01,
	DW_MACINFO_undef = 0x02,		DW_MACINFO_undef = 0x02,
	DW_MACINFO_start_file = 0x03,		DW_MACINFO_start_file = 0x03,
	DW_MACINFO_end_file = 0x04,		DW_MACINFO_end_file = 0x04,
	DW_MACINFO_vendor_ext = 0xff,		DW_MACINFO_vendor_ext = 0xff
			};
			enum CallFrameInfo {
	// Call frame instruction encodings		// Call frame instruction encodings
	DW_CFA_extended = 0x00,		DW_CFA_extended = 0x00,
	DW_CFA_nop = 0x00,		DW_CFA_nop = 0x00,
	DW_CFA_advance_loc = 0x40,		DW_CFA_advance_loc = 0x40,
	DW_CFA_offset = 0x80,		DW_CFA_offset = 0x80,
	DW_CFA_restore = 0xc0,		DW_CFA_restore = 0xc0,
	DW_CFA_set_loc = 0x01,		DW_CFA_set_loc = 0x01,
	DW_CFA_advance_loc1 = 0x02,		DW_CFA_advance_loc1 = 0x02,
	DW_CFA_advance_loc2 = 0x03,		DW_CFA_advance_loc2 = 0x03,
	DW_CFA_advance_loc4 = 0x04,		DW_CFA_advance_loc4 = 0x04,
	skipping to change at line 651		skipping to change at line 720
	DW_CFA_offset_extended_sf = 0x11,		DW_CFA_offset_extended_sf = 0x11,
	DW_CFA_def_cfa_sf = 0x12,		DW_CFA_def_cfa_sf = 0x12,
	DW_CFA_def_cfa_offset_sf = 0x13,		DW_CFA_def_cfa_offset_sf = 0x13,
	DW_CFA_val_offset = 0x14,		DW_CFA_val_offset = 0x14,
	DW_CFA_val_offset_sf = 0x15,		DW_CFA_val_offset_sf = 0x15,
	DW_CFA_val_expression = 0x16,		DW_CFA_val_expression = 0x16,
	DW_CFA_MIPS_advance_loc8 = 0x1d,		DW_CFA_MIPS_advance_loc8 = 0x1d,
	DW_CFA_GNU_window_save = 0x2d,		DW_CFA_GNU_window_save = 0x2d,
	DW_CFA_GNU_args_size = 0x2e,		DW_CFA_GNU_args_size = 0x2e,
	DW_CFA_lo_user = 0x1c,		DW_CFA_lo_user = 0x1c,
	DW_CFA_hi_user = 0x3f,		DW_CFA_hi_user = 0x3f
			};
			enum Constants {
			// Children flag
			DW_CHILDREN_no = 0x00,
			DW_CHILDREN_yes = 0x01,
	DW_EH_PE_absptr = 0x00,		DW_EH_PE_absptr = 0x00,
	DW_EH_PE_omit = 0xff,		DW_EH_PE_omit = 0xff,
	DW_EH_PE_uleb128 = 0x01,		DW_EH_PE_uleb128 = 0x01,
	DW_EH_PE_udata2 = 0x02,		DW_EH_PE_udata2 = 0x02,
	DW_EH_PE_udata4 = 0x03,		DW_EH_PE_udata4 = 0x03,
	DW_EH_PE_udata8 = 0x04,		DW_EH_PE_udata8 = 0x04,
	DW_EH_PE_sleb128 = 0x09,		DW_EH_PE_sleb128 = 0x09,
	DW_EH_PE_sdata2 = 0x0A,		DW_EH_PE_sdata2 = 0x0A,
	DW_EH_PE_sdata4 = 0x0B,		DW_EH_PE_sdata4 = 0x0B,
	DW_EH_PE_sdata8 = 0x0C,		DW_EH_PE_sdata8 = 0x0C,
	DW_EH_PE_signed = 0x08,		DW_EH_PE_signed = 0x08,
	DW_EH_PE_pcrel = 0x10,		DW_EH_PE_pcrel = 0x10,
	DW_EH_PE_textrel = 0x20,		DW_EH_PE_textrel = 0x20,
	DW_EH_PE_datarel = 0x30,		DW_EH_PE_datarel = 0x30,
	DW_EH_PE_funcrel = 0x40,		DW_EH_PE_funcrel = 0x40,
	DW_EH_PE_aligned = 0x50,		DW_EH_PE_aligned = 0x50,
	DW_EH_PE_indirect = 0x80,		DW_EH_PE_indirect = 0x80
			};
			enum ApplePropertyAttributes {
	// Apple Objective-C Property Attributes		// Apple Objective-C Property Attributes
	DW_APPLE_PROPERTY_readonly = 0x01,		DW_APPLE_PROPERTY_readonly = 0x01,
	DW_APPLE_PROPERTY_readwrite = 0x02,		DW_APPLE_PROPERTY_readwrite = 0x02,
	DW_APPLE_PROPERTY_assign = 0x04,		DW_APPLE_PROPERTY_assign = 0x04,
	DW_APPLE_PROPERTY_retain = 0x08,		DW_APPLE_PROPERTY_retain = 0x08,
	DW_APPLE_PROPERTY_copy = 0x10,		DW_APPLE_PROPERTY_copy = 0x10,
	DW_APPLE_PROPERTY_nonatomic = 0x20		DW_APPLE_PROPERTY_nonatomic = 0x20
	};		};
	/// TagString - Return the string for the specified tag.		/// TagString - Return the string for the specified tag.
	skipping to change at line 763		skipping to change at line 840
	/// opcode encodings.		/// opcode encodings.
	const char *LNExtendedString(unsigned Encoding);		const char *LNExtendedString(unsigned Encoding);
	/// MacinfoString - Return the string for the specified macinfo type encodi ngs.		/// MacinfoString - Return the string for the specified macinfo type encodi ngs.
	///		///
	const char *MacinfoString(unsigned Encoding);		const char *MacinfoString(unsigned Encoding);
	/// CallFrameString - Return the string for the specified call frame instru ction		/// CallFrameString - Return the string for the specified call frame instru ction
	/// encodings.		/// encodings.
	const char *CallFrameString(unsigned Encoding);		const char *CallFrameString(unsigned Encoding);
			// Constants for the DWARF5 Accelerator Table Proposal
			enum AcceleratorTable {
			// Data layout descriptors.
			DW_ATOM_null = 0u, // Marker as the end of a list of atoms.
			DW_ATOM_die_offset = 1u, // DIE offset in the debug_info section.
			DW_ATOM_cu_offset = 2u, // Offset of the compile unit header that contain
			s the
			// item in question.
			DW_ATOM_die_tag = 3u, // A tag entry.
			DW_ATOM_type_flags = 4u, // Set of flags for a type.
			// DW_ATOM_type_flags values.
			// Always set for C++, only set for ObjC if this is the @implementation f
			or a
			// class.
			DW_FLAG_type_implementation = 2u,
			// Hash functions.
			// Daniel J. Bernstein hash.
			DW_hash_function_djb = 0u
			};
			/// AtomTypeString - Return the string for the specified Atom type.
			const char *AtomTypeString(unsigned Atom);
			// Constants for the GNU pubnames/pubtypes extensions supporting gdb index.
			enum GDBIndexEntryKind {
			GIEK_NONE,
			GIEK_TYPE,
			GIEK_VARIABLE,
			GIEK_FUNCTION,
			GIEK_OTHER,
			GIEK_UNUSED5,
			GIEK_UNUSED6,
			GIEK_UNUSED7
			};
			const char *GDBIndexEntryKindString(GDBIndexEntryKind Kind);
			enum GDBIndexEntryLinkage {
			GIEL_EXTERNAL,
			GIEL_STATIC
			};
			const char *GDBIndexEntryLinkageString(GDBIndexEntryLinkage Linkage);
			/// The gnu_pub* kind looks like:
			///
			/// 0-3 reserved
			/// 4-6 symbol kind
			/// 7 0 == global, 1 == static
			///
			/// A gdb_index descriptor includes the above kind, shifted 24 bits up with
			the
			/// offset of the cu within the debug_info section stored in those 24 bits.
			struct PubIndexEntryDescriptor {
			GDBIndexEntryKind Kind;
			GDBIndexEntryLinkage Linkage;
			PubIndexEntryDescriptor(GDBIndexEntryKind Kind, GDBIndexEntryLinkage Link
			age)
			: Kind(Kind), Linkage(Linkage) {}
			/* implicit */ PubIndexEntryDescriptor(GDBIndexEntryKind Kind)
			: Kind(Kind), Linkage(GIEL_EXTERNAL) {}
			explicit PubIndexEntryDescriptor(uint8_t Value)
			: Kind(static_cast<GDBIndexEntryKind>((Value & KIND_MASK) >>
			KIND_OFFSET)),
			Linkage(static_cast<GDBIndexEntryLinkage>((Value & LINKAGE_MASK) >>
			LINKAGE_OFFSET)) {}
			uint8_t toBits() { return Kind << KIND_OFFSET | Linkage << LINKAGE_OFFSET
			; }
			private:
			enum {
			KIND_OFFSET = 4,
			KIND_MASK = 7 << KIND_OFFSET,
			LINKAGE_OFFSET = 7,
			LINKAGE_MASK = 1 << LINKAGE_OFFSET
			};
			};
	} // End of namespace dwarf		} // End of namespace dwarf
	} // End of namespace llvm		} // End of namespace llvm
	#endif		#endif
End of changes. 54 change blocks.
	48 lines changed or deleted		207 lines changed or added

	ELF.h		ELF.h
	//===- ELF.h - ELF object file implementation -------------------*- C++ -*- ===//		//===- ELF.h - ELF object file implementation -------------------*- C++ -*- ===//
	//		//
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This file declares the ELFObjectFile template class.		// This file declares the ELFFile template class.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_OBJECT_ELF_H		#ifndef LLVM_OBJECT_ELF_H
	#define LLVM_OBJECT_ELF_H		#define LLVM_OBJECT_ELF_H
			#include "llvm/ADT/ArrayRef.h"
	#include "llvm/ADT/DenseMap.h"		#include "llvm/ADT/DenseMap.h"
	#include "llvm/ADT/PointerIntPair.h"		#include "llvm/ADT/PointerIntPair.h"
	#include "llvm/ADT/SmallVector.h"		#include "llvm/ADT/SmallVector.h"
	#include "llvm/ADT/StringSwitch.h"		#include "llvm/ADT/StringSwitch.h"
	#include "llvm/ADT/Triple.h"		#include "llvm/ADT/Triple.h"
	#include "llvm/Object/ObjectFile.h"		#include "llvm/Object/ELFTypes.h"
			#include "llvm/Object/Error.h"
	#include "llvm/Support/Casting.h"		#include "llvm/Support/Casting.h"
	#include "llvm/Support/ELF.h"		#include "llvm/Support/ELF.h"
	#include "llvm/Support/Endian.h"		#include "llvm/Support/Endian.h"
	#include "llvm/Support/ErrorHandling.h"		#include "llvm/Support/ErrorHandling.h"
			#include "llvm/Support/ErrorOr.h"
	#include "llvm/Support/MemoryBuffer.h"		#include "llvm/Support/MemoryBuffer.h"
	#include "llvm/Support/raw_ostream.h"		#include "llvm/Support/raw_ostream.h"
	#include <algorithm>		#include <algorithm>
	#include <limits>		#include <limits>
	#include <utility>		#include <utility>
	namespace llvm {		namespace llvm {
	namespace object {		namespace object {
	using support::endianness;		StringRef getELFRelocationTypeName(uint32_t Machine, uint32_t Type);
	template<endianness target_endianness, std::size_t max_alignment, bool is64		// Subclasses of ELFFile may need this for template instantiation
	Bits>
	struct ELFType {
	static const endianness TargetEndianness = target_endianness;
	static const std::size_t MaxAlignment = max_alignment;
	static const bool Is64Bits = is64Bits;
	};
	template<typename T, int max_align>
	struct MaximumAlignment {
	enum {value = AlignOf<T>::Alignment > max_align ? max_align
	: AlignOf<T>::Alignment};
	};
	// Subclasses of ELFObjectFile may need this for template instantiation
	inline std::pair<unsigned char, unsigned char>		inline std::pair<unsigned char, unsigned char>
	getElfArchType(MemoryBuffer *Object) {		getElfArchType(MemoryBuffer *Object) {
	if (Object->getBufferSize() < ELF::EI_NIDENT)		if (Object->getBufferSize() < ELF::EI_NIDENT)
	return std::make_pair((uint8_t)ELF::ELFCLASSNONE,(uint8_t)ELF::ELFDATAN ONE);		return std::make_pair((uint8_t)ELF::ELFCLASSNONE,(uint8_t)ELF::ELFDATAN ONE);
	return std::make_pair( (uint8_t)Object->getBufferStart()[ELF::EI_CLASS]		return std::make_pair((uint8_t) Object->getBufferStart()[ELF::EI_CLASS],
	, (uint8_t)Object->getBufferStart()[ELF::EI_DATA]);		(uint8_t) Object->getBufferStart()[ELF::EI_DATA]);
	}		}
	// Templates to choose Elf_Addr and Elf_Off depending on is64Bits.		template <class ELFT>
	template<endianness target_endianness, std::size_t max_alignment>		class ELFFile {
	struct ELFDataTypeTypedefHelperCommon {		public:
	typedef support::detail::packed_endian_specific_integral
	<uint16_t, target_endianness,
	MaximumAlignment<uint16_t, max_alignment>::value> Elf_Half;
	typedef support::detail::packed_endian_specific_integral
	<uint32_t, target_endianness,
	MaximumAlignment<uint32_t, max_alignment>::value> Elf_Word;
	typedef support::detail::packed_endian_specific_integral
	<int32_t, target_endianness,
	MaximumAlignment<int32_t, max_alignment>::value> Elf_Sword;
	typedef support::detail::packed_endian_specific_integral
	<uint64_t, target_endianness,
	MaximumAlignment<uint64_t, max_alignment>::value> Elf_Xword;
	typedef support::detail::packed_endian_specific_integral
	<int64_t, target_endianness,
	MaximumAlignment<int64_t, max_alignment>::value> Elf_Sxword;
	};
	template<class ELFT>
	struct ELFDataTypeTypedefHelper;
	/// ELF 32bit types.
	template<endianness TargetEndianness, std::size_t MaxAlign>
	struct ELFDataTypeTypedefHelper<ELFType<TargetEndianness, MaxAlign, false>
	>
	: ELFDataTypeTypedefHelperCommon<TargetEndianness, MaxAlign> {
	typedef uint32_t value_type;
	typedef support::detail::packed_endian_specific_integral
	<value_type, TargetEndianness,
	MaximumAlignment<value_type, MaxAlign>::value> Elf_Addr;
	typedef support::detail::packed_endian_specific_integral
	<value_type, TargetEndianness,
	MaximumAlignment<value_type, MaxAlign>::value> Elf_Off;
	};
	/// ELF 64bit types.
	template<endianness TargetEndianness, std::size_t MaxAlign>
	struct ELFDataTypeTypedefHelper<ELFType<TargetEndianness, MaxAlign, true> >
	: ELFDataTypeTypedefHelperCommon<TargetEndianness, MaxAlign> {
	typedef uint64_t value_type;
	typedef support::detail::packed_endian_specific_integral
	<value_type, TargetEndianness,
	MaximumAlignment<value_type, MaxAlign>::value> Elf_Addr;
	typedef support::detail::packed_endian_specific_integral
	<value_type, TargetEndianness,
	MaximumAlignment<value_type, MaxAlign>::value> Elf_Off;
	};
	// I really don't like doing this, but the alternative is copypasta.
	#define LLVM_ELF_IMPORT_TYPES(E, M, W)
	\
	typedef typename ELFDataTypeTypedefHelper<ELFType<E,M,W> >::Elf_Addr Elf_Ad
	dr; \
	typedef typename ELFDataTypeTypedefHelper<ELFType<E,M,W> >::Elf_Off Elf_Off
	; \
	typedef typename ELFDataTypeTypedefHelper<ELFType<E,M,W> >::Elf_Half Elf_Ha
	lf; \
	typedef typename ELFDataTypeTypedefHelper<ELFType<E,M,W> >::Elf_Word Elf_Wo
	rd; \
	typedef typename
	\
	ELFDataTypeTypedefHelper<ELFType<E,M,W> >::Elf_Sword Elf_Sword;
	\
	typedef typename
	\
	ELFDataTypeTypedefHelper<ELFType<E,M,W> >::Elf_Xword Elf_Xword;
	\
	typedef typename
	\
	ELFDataTypeTypedefHelper<ELFType<E,M,W> >::Elf_Sxword Elf_Sxword;
	#define LLVM_ELF_IMPORT_TYPES_ELFT(ELFT)
	\
	LLVM_ELF_IMPORT_TYPES(ELFT::TargetEndianness, ELFT::MaxAlignment,
	\
	ELFT::Is64Bits)
	// Section header.
	template<class ELFT>
	struct Elf_Shdr_Base;
	template<endianness TargetEndianness, std::size_t MaxAlign>
	struct Elf_Shdr_Base<ELFType<TargetEndianness, MaxAlign, false> > {
	LLVM_ELF_IMPORT_TYPES(TargetEndianness, MaxAlign, false)
	Elf_Word sh_name; // Section name (index into string table)
	Elf_Word sh_type; // Section type (SHT_*)
	Elf_Word sh_flags; // Section flags (SHF_*)
	Elf_Addr sh_addr; // Address where section is to be loaded
	Elf_Off sh_offset; // File offset of section data, in bytes
	Elf_Word sh_size; // Size of section, in bytes
	Elf_Word sh_link; // Section type-specific header table index link
	Elf_Word sh_info; // Section type-specific extra information
	Elf_Word sh_addralign;// Section address alignment
	Elf_Word sh_entsize; // Size of records contained within the section
	};
	template<endianness TargetEndianness, std::size_t MaxAlign>
	struct Elf_Shdr_Base<ELFType<TargetEndianness, MaxAlign, true> > {
	LLVM_ELF_IMPORT_TYPES(TargetEndianness, MaxAlign, true)
	Elf_Word sh_name; // Section name (index into string table)
	Elf_Word sh_type; // Section type (SHT_*)
	Elf_Xword sh_flags; // Section flags (SHF_*)
	Elf_Addr sh_addr; // Address where section is to be loaded
	Elf_Off sh_offset; // File offset of section data, in bytes
	Elf_Xword sh_size; // Size of section, in bytes
	Elf_Word sh_link; // Section type-specific header table index link
	Elf_Word sh_info; // Section type-specific extra information
	Elf_Xword sh_addralign;// Section address alignment
	Elf_Xword sh_entsize; // Size of records contained within the section
	};
	template<class ELFT>
	struct Elf_Shdr_Impl : Elf_Shdr_Base<ELFT> {
	using Elf_Shdr_Base<ELFT>::sh_entsize;
	using Elf_Shdr_Base<ELFT>::sh_size;
	/// @brief Get the number of entities this section contains if it has any
	.
	unsigned getEntityCount() const {
	if (sh_entsize == 0)
	return 0;
	return sh_size / sh_entsize;
	}
	};
	template<class ELFT>
	struct Elf_Sym_Base;
	template<endianness TargetEndianness, std::size_t MaxAlign>
	struct Elf_Sym_Base<ELFType<TargetEndianness, MaxAlign, false> > {
	LLVM_ELF_IMPORT_TYPES(TargetEndianness, MaxAlign, false)
	Elf_Word st_name; // Symbol name (index into string table)
	Elf_Addr st_value; // Value or address associated with the symbol
	Elf_Word st_size; // Size of the symbol
	unsigned char st_info; // Symbol's type and binding attributes
	unsigned char st_other; // Must be zero; reserved
	Elf_Half st_shndx; // Which section (header table index) it's define
	d in
	};
	template<endianness TargetEndianness, std::size_t MaxAlign>
	struct Elf_Sym_Base<ELFType<TargetEndianness, MaxAlign, true> > {
	LLVM_ELF_IMPORT_TYPES(TargetEndianness, MaxAlign, true)
	Elf_Word st_name; // Symbol name (index into string table)
	unsigned char st_info; // Symbol's type and binding attributes
	unsigned char st_other; // Must be zero; reserved
	Elf_Half st_shndx; // Which section (header table index) it's define
	d in
	Elf_Addr st_value; // Value or address associated with the symbol
	Elf_Xword st_size; // Size of the symbol
	};
	template<class ELFT>
	struct Elf_Sym_Impl : Elf_Sym_Base<ELFT> {
	using Elf_Sym_Base<ELFT>::st_info;
	// These accessors and mutators correspond to the ELF32_ST_BIND,
	// ELF32_ST_TYPE, and ELF32_ST_INFO macros defined in the ELF specificati
	on:
	unsigned char getBinding() const { return st_info >> 4; }
	unsigned char getType() const { return st_info & 0x0f; }
	void setBinding(unsigned char b) { setBindingAndType(b, getType()); }
	void setType(unsigned char t) { setBindingAndType(getBinding(), t); }
	void setBindingAndType(unsigned char b, unsigned char t) {
	st_info = (b << 4) + (t & 0x0f);
	}
	};
	/// Elf_Versym: This is the structure of entries in the SHT_GNU_versym sect
	ion
	/// (.gnu.version). This structure is identical for ELF32 and ELF64.
	template<class ELFT>
	struct Elf_Versym_Impl {
	LLVM_ELF_IMPORT_TYPES_ELFT(ELFT)
	Elf_Half vs_index; // Version index with flags (e.g. VERSYM_HIDDEN)
	};
	template<class ELFT>
	struct Elf_Verdaux_Impl;
	/// Elf_Verdef: This is the structure of entries in the SHT_GNU_verdef sect
	ion
	/// (.gnu.version_d). This structure is identical for ELF32 and ELF64.
	template<class ELFT>
	struct Elf_Verdef_Impl {
	LLVM_ELF_IMPORT_TYPES_ELFT(ELFT)
	typedef Elf_Verdaux_Impl<ELFT> Elf_Verdaux;
	Elf_Half vd_version; // Version of this structure (e.g. VER_DEF_CURRENT)
	Elf_Half vd_flags; // Bitwise flags (VER_DEF_*)
	Elf_Half vd_ndx; // Version index, used in .gnu.version entries
	Elf_Half vd_cnt; // Number of Verdaux entries
	Elf_Word vd_hash; // Hash of name
	Elf_Word vd_aux; // Offset to the first Verdaux entry (in bytes)
	Elf_Word vd_next; // Offset to the next Verdef entry (in bytes)
	/// Get the first Verdaux entry for this Verdef.
	const Elf_Verdaux *getAux() const {
	return reinterpret_cast<const Elf_Verdaux*>((const char*)this + vd_aux)
	;
	}
	};
	/// Elf_Verdaux: This is the structure of auxiliary data in the SHT_GNU_ver
	def
	/// section (.gnu.version_d). This structure is identical for ELF32 and ELF
	64.
	template<class ELFT>
	struct Elf_Verdaux_Impl {
	LLVM_ELF_IMPORT_TYPES_ELFT(ELFT)
	Elf_Word vda_name; // Version name (offset in string table)
	Elf_Word vda_next; // Offset to next Verdaux entry (in bytes)
	};
	/// Elf_Verneed: This is the structure of entries in the SHT_GNU_verneed
	/// section (.gnu.version_r). This structure is identical for ELF32 and ELF
	64.
	template<class ELFT>
	struct Elf_Verneed_Impl {
	LLVM_ELF_IMPORT_TYPES_ELFT(ELFT)
	Elf_Half vn_version; // Version of this structure (e.g. VER_NEED_CURRENT)
	Elf_Half vn_cnt; // Number of associated Vernaux entries
	Elf_Word vn_file; // Library name (string table offset)
	Elf_Word vn_aux; // Offset to first Vernaux entry (in bytes)
	Elf_Word vn_next; // Offset to next Verneed entry (in bytes)
	};
	/// Elf_Vernaux: This is the structure of auxiliary data in SHT_GNU_verneed
	/// section (.gnu.version_r). This structure is identical for ELF32 and ELF
	64.
	template<class ELFT>
	struct Elf_Vernaux_Impl {
	LLVM_ELF_IMPORT_TYPES_ELFT(ELFT)
	Elf_Word vna_hash; // Hash of dependency name
	Elf_Half vna_flags; // Bitwise Flags (VER_FLAG_*)
	Elf_Half vna_other; // Version index, used in .gnu.version entries
	Elf_Word vna_name; // Dependency name
	Elf_Word vna_next; // Offset to next Vernaux entry (in bytes)
	};
	/// Elf_Dyn_Base: This structure matches the form of entries in the dynamic
	/// table section (.dynamic) look like.
	template<class ELFT>
	struct Elf_Dyn_Base;
	template<endianness TargetEndianness, std::size_t MaxAlign>
	struct Elf_Dyn_Base<ELFType<TargetEndianness, MaxAlign, false> > {
	LLVM_ELF_IMPORT_TYPES(TargetEndianness, MaxAlign, false)
	Elf_Sword d_tag;
	union {
	Elf_Word d_val;
	Elf_Addr d_ptr;
	} d_un;
	};
	template<endianness TargetEndianness, std::size_t MaxAlign>
	struct Elf_Dyn_Base<ELFType<TargetEndianness, MaxAlign, true> > {
	LLVM_ELF_IMPORT_TYPES(TargetEndianness, MaxAlign, true)
	Elf_Sxword d_tag;
	union {
	Elf_Xword d_val;
	Elf_Addr d_ptr;
	} d_un;
	};
	/// Elf_Dyn_Impl: This inherits from Elf_Dyn_Base, adding getters and sette
	rs.
	template<class ELFT>
	struct Elf_Dyn_Impl : Elf_Dyn_Base<ELFT> {
	using Elf_Dyn_Base<ELFT>::d_tag;
	using Elf_Dyn_Base<ELFT>::d_un;
	int64_t getTag() const { return d_tag; }
	uint64_t getVal() const { return d_un.d_val; }
	uint64_t getPtr() const { return d_un.ptr; }
	};
	// Elf_Rel: Elf Relocation
	template<class ELFT, bool isRela>
	struct Elf_Rel_Base;
	template<endianness TargetEndianness, std::size_t MaxAlign>
	struct Elf_Rel_Base<ELFType<TargetEndianness, MaxAlign, false>, false> {
	LLVM_ELF_IMPORT_TYPES(TargetEndianness, MaxAlign, false)
	Elf_Addr r_offset; // Location (file byte offset, or program virtual
	addr)
	Elf_Word r_info; // Symbol table index and type of relocation to ap
	ply
	uint32_t getRInfo(bool isMips64EL) const {
	assert(!isMips64EL);
	return r_info;
	}
	void setRInfo(uint32_t R) {
	r_info = R;
	}
	};
	template<endianness TargetEndianness, std::size_t MaxAlign>
	struct Elf_Rel_Base<ELFType<TargetEndianness, MaxAlign, true>, false> {
	LLVM_ELF_IMPORT_TYPES(TargetEndianness, MaxAlign, true)
	Elf_Addr r_offset; // Location (file byte offset, or program virtual
	addr)
	Elf_Xword r_info; // Symbol table index and type of relocation to a
	pply
	uint64_t getRInfo(bool isMips64EL) const {
	uint64_t t = r_info;
	if (!isMips64EL)
	return t;
	// Mip64 little endian has a "special" encoding of r_info. Instead of o
	ne
	// 64 bit little endian number, it is a little ending 32 bit number fol
	lowed
	// by a 32 bit big endian number.
	return (t << 32) | ((t >> 8) & 0xff000000) | ((t >> 24) & 0x00ff0000) |
	((t >> 40) & 0x0000ff00) | ((t >> 56) & 0x000000ff);
	return r_info;
	}
	void setRInfo(uint64_t R) {
	// FIXME: Add mips64el support.
	r_info = R;
	}
	};
	template<endianness TargetEndianness, std::size_t MaxAlign>
	struct Elf_Rel_Base<ELFType<TargetEndianness, MaxAlign, false>, true> {
	LLVM_ELF_IMPORT_TYPES(TargetEndianness, MaxAlign, false)
	Elf_Addr r_offset; // Location (file byte offset, or program virtual
	addr)
	Elf_Word r_info; // Symbol table index and type of relocation to a
	pply
	Elf_Sword r_addend; // Compute value for relocatable field by adding
	this
	uint32_t getRInfo(bool isMips64EL) const {
	assert(!isMips64EL);
	return r_info;
	}
	void setRInfo(uint32_t R) {
	r_info = R;
	}
	};
	template<endianness TargetEndianness, std::size_t MaxAlign>
	struct Elf_Rel_Base<ELFType<TargetEndianness, MaxAlign, true>, true> {
	LLVM_ELF_IMPORT_TYPES(TargetEndianness, MaxAlign, true)
	Elf_Addr r_offset; // Location (file byte offset, or program virtual
	addr)
	Elf_Xword r_info; // Symbol table index and type of relocation to a
	pply
	Elf_Sxword r_addend; // Compute value for relocatable field by adding
	this.
	uint64_t getRInfo(bool isMips64EL) const {
	// Mip64 little endian has a "special" encoding of r_info. Instead of o
	ne
	// 64 bit little endian number, it is a little ending 32 bit number fol
	lowed
	// by a 32 bit big endian number.
	uint64_t t = r_info;
	if (!isMips64EL)
	return t;
	return (t << 32) | ((t >> 8) & 0xff000000) | ((t >> 24) & 0x00ff0000) |
	((t >> 40) & 0x0000ff00) | ((t >> 56) & 0x000000ff);
	}
	void setRInfo(uint64_t R) {
	// FIXME: Add mips64el support.
	r_info = R;
	}
	};
	template<class ELFT, bool isRela>
	struct Elf_Rel_Impl;
	template<endianness TargetEndianness, std::size_t MaxAlign, bool isRela>
	struct Elf_Rel_Impl<ELFType<TargetEndianness, MaxAlign, true>, isRela>
	: Elf_Rel_Base<ELFType<TargetEndianness, MaxAlign, true>, isRela> {
	LLVM_ELF_IMPORT_TYPES(TargetEndianness, MaxAlign, true)
	// These accessors and mutators correspond to the ELF64_R_SYM, ELF64_R_TY
	PE,
	// and ELF64_R_INFO macros defined in the ELF specification:
	uint32_t getSymbol(bool isMips64EL) const {
	return (uint32_t) (this->getRInfo(isMips64EL) >> 32);
	}
	uint32_t getType(bool isMips64EL) const {
	return (uint32_t) (this->getRInfo(isMips64EL) & 0xffffffffL);
	}
	void setSymbol(uint32_t s) { setSymbolAndType(s, getType()); }
	void setType(uint32_t t) { setSymbolAndType(getSymbol(), t); }
	void setSymbolAndType(uint32_t s, uint32_t t) {
	this->setRInfo(((uint64_t)s << 32) + (t&0xffffffffL));
	}
	};
	template<endianness TargetEndianness, std::size_t MaxAlign, bool isRela>
	struct Elf_Rel_Impl<ELFType<TargetEndianness, MaxAlign, false>, isRela>
	: Elf_Rel_Base<ELFType<TargetEndianness, MaxAlign, false>, isRela> {
	LLVM_ELF_IMPORT_TYPES(TargetEndianness, MaxAlign, false)
	// These accessors and mutators correspond to the ELF32_R_SYM, ELF32_R_TY
	PE,
	// and ELF32_R_INFO macros defined in the ELF specification:
	uint32_t getSymbol(bool isMips64EL) const {
	return this->getRInfo(isMips64EL) >> 8;
	}
	unsigned char getType(bool isMips64EL) const {
	return (unsigned char) (this->getRInfo(isMips64EL) & 0x0ff);
	}
	void setSymbol(uint32_t s) { setSymbolAndType(s, getType()); }
	void setType(unsigned char t) { setSymbolAndType(getSymbol(), t); }
	void setSymbolAndType(uint32_t s, unsigned char t) {
	this->setRInfo((s << 8) + t);
	}
	};
	template<class ELFT>
	struct Elf_Ehdr_Impl {
	LLVM_ELF_IMPORT_TYPES_ELFT(ELFT)
	unsigned char e_ident[ELF::EI_NIDENT]; // ELF Identification bytes
	Elf_Half e_type; // Type of file (see ET_*)
	Elf_Half e_machine; // Required architecture for this file (see EM_*)
	Elf_Word e_version; // Must be equal to 1
	Elf_Addr e_entry; // Address to jump to in order to start program
	Elf_Off e_phoff; // Program header table's file offset, in bytes
	Elf_Off e_shoff; // Section header table's file offset, in bytes
	Elf_Word e_flags; // Processor-specific flags
	Elf_Half e_ehsize; // Size of ELF header, in bytes
	Elf_Half e_phentsize;// Size of an entry in the program header table
	Elf_Half e_phnum; // Number of entries in the program header table
	Elf_Half e_shentsize;// Size of an entry in the section header table
	Elf_Half e_shnum; // Number of entries in the section header table
	Elf_Half e_shstrndx; // Section header table index of section name
	// string table
	bool checkMagic() const {
	return (memcmp(e_ident, ELF::ElfMagic, strlen(ELF::ElfMagic))) == 0;
	}
	unsigned char getFileClass() const { return e_ident[ELF::EI_CLASS]; }
	unsigned char getDataEncoding() const { return e_ident[ELF::EI_DATA]; }
	};
	template<class ELFT>
	struct Elf_Phdr_Impl;
	template<endianness TargetEndianness, std::size_t MaxAlign>
	struct Elf_Phdr_Impl<ELFType<TargetEndianness, MaxAlign, false> > {
	LLVM_ELF_IMPORT_TYPES(TargetEndianness, MaxAlign, false)
	Elf_Word p_type; // Type of segment
	Elf_Off p_offset; // FileOffset where segment is located, in bytes
	Elf_Addr p_vaddr; // Virtual Address of beginning of segment
	Elf_Addr p_paddr; // Physical address of beginning of segment (OS-specif
	ic)
	Elf_Word p_filesz; // Num. of bytes in file image of segment (may be zero
	)
	Elf_Word p_memsz; // Num. of bytes in mem image of segment (may be zero)
	Elf_Word p_flags; // Segment flags
	Elf_Word p_align; // Segment alignment constraint
	};
	template<endianness TargetEndianness, std::size_t MaxAlign>
	struct Elf_Phdr_Impl<ELFType<TargetEndianness, MaxAlign, true> > {
	LLVM_ELF_IMPORT_TYPES(TargetEndianness, MaxAlign, true)
	Elf_Word p_type; // Type of segment
	Elf_Word p_flags; // Segment flags
	Elf_Off p_offset; // FileOffset where segment is located, in bytes
	Elf_Addr p_vaddr; // Virtual Address of beginning of segment
	Elf_Addr p_paddr; // Physical address of beginning of segment (OS-specif
	ic)
	Elf_Xword p_filesz; // Num. of bytes in file image of segment (may be zer
	o)
	Elf_Xword p_memsz; // Num. of bytes in mem image of segment (may be zero
	)
	Elf_Xword p_align; // Segment alignment constraint
	};
	template<class ELFT>
	class ELFObjectFile : public ObjectFile {
	LLVM_ELF_IMPORT_TYPES_ELFT(ELFT)		LLVM_ELF_IMPORT_TYPES_ELFT(ELFT)
			typedef typename conditional<ELFT::Is64Bits,
			uint64_t, uint32_t>::type uintX_t;
	public:
	/// \brief Iterate over constant sized entities.		/// \brief Iterate over constant sized entities.
	template<class EntT>		template <class EntT>
	class ELFEntityIterator {		class ELFEntityIterator {
	public:		public:
	typedef ptrdiff_t difference_type;		typedef ptrdiff_t difference_type;
	typedef EntT value_type;		typedef EntT value_type;
	typedef std::random_access_iterator_tag iterator_category;		typedef std::random_access_iterator_tag iterator_category;
	typedef value_type &reference;		typedef value_type &reference;
	typedef value_type *pointer;		typedef value_type *pointer;
	/// \brief Default construct iterator.		/// \brief Default construct iterator.
	ELFEntityIterator() : EntitySize(0), Current(0) {}		ELFEntityIterator() : EntitySize(0), Current(0) {}
	ELFEntityIterator(uint64_t EntSize, const char *Start)		ELFEntityIterator(uintX_t EntSize, const char *Start)
	: EntitySize(EntSize)		: EntitySize(EntSize), Current(Start) {}
	, Current(Start) {}
	reference operator *() {		reference operator *() {
	assert(Current && "Attempted to dereference an invalid iterator!");		assert(Current && "Attempted to dereference an invalid iterator!");
	return *reinterpret_cast<pointer>(Current);		return *reinterpret_cast<pointer>(Current);
	}		}
	pointer operator ->() {		pointer operator ->() {
	assert(Current && "Attempted to dereference an invalid iterator!");		assert(Current && "Attempted to dereference an invalid iterator!");
	return reinterpret_cast<pointer>(Current);		return reinterpret_cast<pointer>(Current);
	}		}
	skipping to change at line 549		skipping to change at line 110
	}		}
	ELFEntityIterator &operator =(const ELFEntityIterator &Other) {		ELFEntityIterator &operator =(const ELFEntityIterator &Other) {
	EntitySize = Other.EntitySize;		EntitySize = Other.EntitySize;
	Current = Other.Current;		Current = Other.Current;
	return *this;		return *this;
	}		}
	difference_type operator -(const ELFEntityIterator &Other) const {		difference_type operator -(const ELFEntityIterator &Other) const {
	assert(EntitySize == Other.EntitySize &&		assert(EntitySize == Other.EntitySize &&
	"Subtracting iterators of different EntitiySize!");		"Subtracting iterators of different EntitySize!");
	return (Current - Other.Current) / EntitySize;		return (Current - Other.Current) / EntitySize;
	}		}
	const char *get() const { return Current; }		const char *get() const { return Current; }
			uintX_t getEntSize() const { return EntitySize; }
	private:		private:
	uint64_t EntitySize;		uintX_t EntitySize;
	const char *Current;		const char *Current;
	};		};
	typedef Elf_Ehdr_Impl<ELFT> Elf_Ehdr;		typedef Elf_Ehdr_Impl<ELFT> Elf_Ehdr;
	typedef Elf_Shdr_Impl<ELFT> Elf_Shdr;		typedef Elf_Shdr_Impl<ELFT> Elf_Shdr;
	typedef Elf_Sym_Impl<ELFT> Elf_Sym;		typedef Elf_Sym_Impl<ELFT> Elf_Sym;
	typedef Elf_Dyn_Impl<ELFT> Elf_Dyn;		typedef Elf_Dyn_Impl<ELFT> Elf_Dyn;
	typedef Elf_Phdr_Impl<ELFT> Elf_Phdr;		typedef Elf_Phdr_Impl<ELFT> Elf_Phdr;
	typedef Elf_Rel_Impl<ELFT, false> Elf_Rel;		typedef Elf_Rel_Impl<ELFT, false> Elf_Rel;
	typedef Elf_Rel_Impl<ELFT, true> Elf_Rela;		typedef Elf_Rel_Impl<ELFT, true> Elf_Rela;
	typedef Elf_Verdef_Impl<ELFT> Elf_Verdef;		typedef Elf_Verdef_Impl<ELFT> Elf_Verdef;
	typedef Elf_Verdaux_Impl<ELFT> Elf_Verdaux;		typedef Elf_Verdaux_Impl<ELFT> Elf_Verdaux;
	typedef Elf_Verneed_Impl<ELFT> Elf_Verneed;		typedef Elf_Verneed_Impl<ELFT> Elf_Verneed;
	typedef Elf_Vernaux_Impl<ELFT> Elf_Vernaux;		typedef Elf_Vernaux_Impl<ELFT> Elf_Vernaux;
	typedef Elf_Versym_Impl<ELFT> Elf_Versym;		typedef Elf_Versym_Impl<ELFT> Elf_Versym;
	typedef ELFEntityIterator<const Elf_Dyn> Elf_Dyn_iterator;		typedef ELFEntityIterator<const Elf_Dyn> Elf_Dyn_Iter;
	typedef ELFEntityIterator<const Elf_Sym> Elf_Sym_iterator;
	typedef ELFEntityIterator<const Elf_Rela> Elf_Rela_Iter;		typedef ELFEntityIterator<const Elf_Rela> Elf_Rela_Iter;
	typedef ELFEntityIterator<const Elf_Rel> Elf_Rel_Iter;		typedef ELFEntityIterator<const Elf_Rel> Elf_Rel_Iter;
			typedef ELFEntityIterator<const Elf_Shdr> Elf_Shdr_Iter;
			/// \brief Archive files are 2 byte aligned, so we need this for
			/// PointerIntPair to work.
			template <typename T>
			class ArchivePointerTypeTraits {
			public:
			static inline const void *getAsVoidPointer(T *P) { return P; }
			static inline T *getFromVoidPointer(const void *P) {
			return static_cast<T *>(P);
			}
			enum { NumLowBitsAvailable = 1 };
			};
	protected:		class Elf_Sym_Iter {
	// This flag is used for classof, to distinguish ELFObjectFile from		public:
	// its subclass. If more subclasses will be created, this flag will		typedef ptrdiff_t difference_type;
	// have to become an enum.		typedef const Elf_Sym value_type;
	bool isDyldELFObject;		typedef std::random_access_iterator_tag iterator_category;
			typedef value_type &reference;
			typedef value_type *pointer;
			/// \brief Default construct iterator.
			Elf_Sym_Iter() : EntitySize(0), Current(0, false) {}
			Elf_Sym_Iter(uintX_t EntSize, const char *Start, bool IsDynamic)
			: EntitySize(EntSize), Current(Start, IsDynamic) {}
			reference operator*() {
			assert(Current.getPointer() &&
			"Attempted to dereference an invalid iterator!");
			return *reinterpret_cast<pointer>(Current.getPointer());
			}
			pointer operator->() {
			assert(Current.getPointer() &&
			"Attempted to dereference an invalid iterator!");
			return reinterpret_cast<pointer>(Current.getPointer());
			}
			bool operator==(const Elf_Sym_Iter &Other) {
			return Current == Other.Current;
			}
			bool operator!=(const Elf_Sym_Iter &Other) { return !(*this == Other);
			}
			Elf_Sym_Iter &operator++() {
			assert(Current.getPointer() &&
			"Attempted to increment an invalid iterator!");
			Current.setPointer(Current.getPointer() + EntitySize);
			return *this;
			}
			Elf_Sym_Iter operator++(int) {
			Elf_Sym_Iter Tmp = *this;
			++*this;
			return Tmp;
			}
			Elf_Sym_Iter operator+(difference_type Dist) {
			assert(Current.getPointer() &&
			"Attempted to increment an invalid iterator!");
			Current.setPointer(Current.getPointer() + EntitySize * Dist);
			return *this;
			}
			Elf_Sym_Iter &operator=(const Elf_Sym_Iter &Other) {
			EntitySize = Other.EntitySize;
			Current = Other.Current;
			return *this;
			}
			difference_type operator-(const Elf_Sym_Iter &Other) const {
			assert(EntitySize == Other.EntitySize &&
			"Subtracting iterators of different EntitySize!");
			return (Current.getPointer() - Other.Current.getPointer()) / EntitySi
			ze;
			}
			const char *get() const { return Current.getPointer(); }
			bool isDynamic() const { return Current.getInt(); }
			uintX_t getEntSize() const { return EntitySize; }
			private:
			uintX_t EntitySize;
			PointerIntPair<const char *, 1, bool,
			ArchivePointerTypeTraits<const char> > Current;
			};
	private:		private:
	typedef SmallVector<const Elf_Shdr *, 2> Sections_t;		typedef SmallVector<const Elf_Shdr *, 2> Sections_t;
	typedef DenseMap<unsigned, unsigned> IndexMap_t;		typedef DenseMap<unsigned, unsigned> IndexMap_t;
	typedef DenseMap<const Elf_Shdr*, SmallVector<uint32_t, 1> > RelocMap_t;
			MemoryBuffer *Buf;
			const uint8_t *base() const {
			return reinterpret_cast<const uint8_t *>(Buf->getBufferStart());
			}
	const Elf_Ehdr *Header;		const Elf_Ehdr *Header;
	const Elf_Shdr *SectionHeaderTable;		const Elf_Shdr *SectionHeaderTable;
	const Elf_Shdr *dot_shstrtab_sec; // Section header string table.		const Elf_Shdr *dot_shstrtab_sec; // Section header string table.
	const Elf_Shdr *dot_strtab_sec; // Symbol header string table.		const Elf_Shdr *dot_strtab_sec; // Symbol header string table.
	const Elf_Shdr *dot_dynstr_sec; // Dynamic symbol string table.		const Elf_Shdr *dot_symtab_sec; // Symbol table section.
	// SymbolTableSections[0] always points to the dynamic string table secti		const Elf_Shdr *SymbolTableSectionHeaderIndex;
	on		DenseMap<const Elf_Sym *, ELF::Elf64_Word> ExtendedSymbolTable;
	// header, or NULL if there is no dynamic string table.
	Sections_t SymbolTableSections;
	IndexMap_t SymbolTableSectionsIndexMap;
	DenseMap<const Elf_Sym*, ELF::Elf64_Word> ExtendedSymbolTable;
	const Elf_Shdr *dot_dynamic_sec; // .dynamic
	const Elf_Shdr *dot_gnu_version_sec; // .gnu.version		const Elf_Shdr *dot_gnu_version_sec; // .gnu.version
	const Elf_Shdr *dot_gnu_version_r_sec; // .gnu.version_r		const Elf_Shdr *dot_gnu_version_r_sec; // .gnu.version_r
	const Elf_Shdr *dot_gnu_version_d_sec; // .gnu.version_d		const Elf_Shdr *dot_gnu_version_d_sec; // .gnu.version_d
			/// \brief Represents a region described by entries in the .dynamic table
			.
			struct DynRegionInfo {
			DynRegionInfo() : Addr(0), Size(0), EntSize(0) {}
			/// \brief Address in current address space.
			const void *Addr;
			/// \brief Size in bytes of the region.
			uintX_t Size;
			/// \brief Size of each entity in the region.
			uintX_t EntSize;
			};
			DynRegionInfo DynamicRegion;
			DynRegionInfo DynHashRegion;
			DynRegionInfo DynStrRegion;
			DynRegionInfo DynSymRegion;
	// Pointer to SONAME entry in dynamic string table		// Pointer to SONAME entry in dynamic string table
	// This is set the first time getLoadName is called.		// This is set the first time getLoadName is called.
	mutable const char *dt_soname;		mutable const char *dt_soname;
	private:
	uint64_t getROffset(DataRefImpl Rel) const;
	// Records for each version index the corresponding Verdef or Vernaux ent ry.		// Records for each version index the corresponding Verdef or Vernaux ent ry.
	// This is filled the first time LoadVersionMap() is called.		// This is filled the first time LoadVersionMap() is called.
	class VersionMapEntry : public PointerIntPair<const void*, 1> {		class VersionMapEntry : public PointerIntPair<const void*, 1> {
	public:		public:
	// If the integer is 0, this is an Elf_Verdef*.		// If the integer is 0, this is an Elf_Verdef*.
	// If the integer is 1, this is an Elf_Vernaux*.		// If the integer is 1, this is an Elf_Vernaux*.
	VersionMapEntry() : PointerIntPair<const void*, 1>(NULL, 0) { }		VersionMapEntry() : PointerIntPair<const void*, 1>(NULL, 0) { }
	VersionMapEntry(const Elf_Verdef *verdef)		VersionMapEntry(const Elf_Verdef *verdef)
	: PointerIntPair<const void*, 1>(verdef, 0) { }		: PointerIntPair<const void*, 1>(verdef, 0) { }
	VersionMapEntry(const Elf_Vernaux *vernaux)		VersionMapEntry(const Elf_Vernaux *vernaux)
	skipping to change at line 638		skipping to change at line 296
	}		}
	const Elf_Vernaux *getVernaux() const {		const Elf_Vernaux *getVernaux() const {
	return isVernaux() ? (const Elf_Vernaux*)getPointer() : NULL;		return isVernaux() ? (const Elf_Vernaux*)getPointer() : NULL;
	}		}
	};		};
	mutable SmallVector<VersionMapEntry, 16> VersionMap;		mutable SmallVector<VersionMapEntry, 16> VersionMap;
	void LoadVersionDefs(const Elf_Shdr *sec) const;		void LoadVersionDefs(const Elf_Shdr *sec) const;
	void LoadVersionNeeds(const Elf_Shdr *ec) const;		void LoadVersionNeeds(const Elf_Shdr *ec) const;
	void LoadVersionMap() const;		void LoadVersionMap() const;
	/// @brief Map sections to an array of relocation sections that reference
	/// them sorted by section index.
	RelocMap_t SectionRelocMap;
	/// @brief Get the relocation section that contains \a Rel.
	const Elf_Shdr *getRelSection(DataRefImpl Rel) const {
	return getSection(Rel.w.b);
	}
	public:		public:
	bool isRelocationHasAddend(DataRefImpl Rel) const;
	template<typename T>		template<typename T>
	const T *getEntry(uint16_t Section, uint32_t Entry) const;		const T *getEntry(uint32_t Section, uint32_t Entry) const;
	template<typename T>		template <typename T>
	const T *getEntry(const Elf_Shdr *Section, uint32_t Entry) const;		const T *getEntry(const Elf_Shdr *Section, uint32_t Entry) const;
	const Elf_Shdr *getSection(DataRefImpl index) const;
	const Elf_Shdr *getSection(uint32_t index) const;
	const Elf_Rel *getRel(DataRefImpl Rel) const;
	const Elf_Rela *getRela(DataRefImpl Rela) const;
	const char *getString(uint32_t section, uint32_t offset) const;		const char *getString(uint32_t section, uint32_t offset) const;
	const char *getString(const Elf_Shdr *section, uint32_t offset) const ;		const char *getString(const Elf_Shdr *section, uint32_t offset) const ;
	error_code getSymbolVersion(const Elf_Shdr *section,		const char *getDynamicString(uintX_t Offset) const;
	const Elf_Sym *Symb,		ErrorOr<StringRef> getSymbolVersion(const Elf_Shdr *section,
	StringRef &Version,		const Elf_Sym *Symb,
	bool &IsDefault) const;		bool &IsDefault) const;
	void VerifyStrTab(const Elf_Shdr *sh) const;		void VerifyStrTab(const Elf_Shdr *sh) const;
	protected:		StringRef getRelocationTypeName(uint32_t Type) const;
	const Elf_Sym *getSymbol(DataRefImpl Symb) const; // FIXME: Should be pr		void getRelocationTypeName(uint32_t Type,
	ivate?		SmallVectorImpl<char> &Result) const;
	void validateSymbol(DataRefImpl Symb) const;
	StringRef getRelocationTypeName(uint32_t Type) const;		/// \brief Get the symbol table section and symbol for a given relocation
			.
			template <class RelT>
			std::pair<const Elf_Shdr *, const Elf_Sym *>
			getRelocationSymbol(const Elf_Shdr *RelSec, const RelT *Rel) const;
	public:		ELFFile(MemoryBuffer *Object, error_code &ec);
	error_code getSymbolName(const Elf_Shdr *section,
	const Elf_Sym *Symb,
	StringRef &Res) const;
	error_code getSectionName(const Elf_Shdr *section,
	StringRef &Res) const;
	const Elf_Dyn *getDyn(DataRefImpl DynData) const;
	error_code getSymbolVersion(SymbolRef Symb, StringRef &Version,
	bool &IsDefault) const;
	uint64_t getSymbolIndex(const Elf_Sym *sym) const;
	protected:
	virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const;
	virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const;
	virtual error_code getSymbolFileOffset(DataRefImpl Symb, uint64_t &Res) c
	onst;
	virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) cons
	t;
	virtual error_code getSymbolAlignment(DataRefImpl Symb, uint32_t &Res) co
	nst;
	virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const;
	virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const
	;
	virtual error_code getSymbolFlags(DataRefImpl Symb, uint32_t &Res) const;
	virtual error_code getSymbolType(DataRefImpl Symb, SymbolRef::Type &Res)
	const;
	virtual error_code getSymbolSection(DataRefImpl Symb,
	section_iterator &Res) const;
	virtual error_code getSymbolValue(DataRefImpl Symb, uint64_t &Val) const;
	virtual error_code getLibraryNext(DataRefImpl Data, LibraryRef &Result) c
	onst;
	virtual error_code getLibraryPath(DataRefImpl Data, StringRef &Res) const
	;
	virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const
	;
	virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const;
	virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) cons
	t;
	virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const;
	virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res) co
	nst;
	virtual error_code getSectionAlignment(DataRefImpl Sec, uint64_t &Res) co
	nst;
	virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const;
	virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const;
	virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const;
	virtual error_code isSectionRequiredForExecution(DataRefImpl Sec,
	bool &Res) const;
	virtual error_code isSectionVirtual(DataRefImpl Sec, bool &Res) const;
	virtual error_code isSectionZeroInit(DataRefImpl Sec, bool &Res) const;
	virtual error_code isSectionReadOnlyData(DataRefImpl Sec, bool &Res) cons
	t;
	virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Sym
	b,
	bool &Result) const;
	virtual relocation_iterator getSectionRelBegin(DataRefImpl Sec) const;
	virtual relocation_iterator getSectionRelEnd(DataRefImpl Sec) const;
	virtual error_code getRelocationNext(DataRefImpl Rel,
	RelocationRef &Res) const;
	virtual error_code getRelocationAddress(DataRefImpl Rel,
	uint64_t &Res) const;
	virtual error_code getRelocationOffset(DataRefImpl Rel,
	uint64_t &Res) const;
	virtual error_code getRelocationSymbol(DataRefImpl Rel,
	SymbolRef &Res) const;
	virtual error_code getRelocationType(DataRefImpl Rel,
	uint64_t &Res) const;
	virtual error_code getRelocationTypeName(DataRefImpl Rel,
	SmallVectorImpl<char> &Result) c
	onst;
	virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,
	int64_t &Res) const;
	virtual error_code getRelocationValueString(DataRefImpl Rel,
	SmallVectorImpl<char> &Result) c
	onst;
	public:
	ELFObjectFile(MemoryBuffer *Object, error_code &ec);
	bool isMips64EL() const {		bool isMips64EL() const {
	return Header->e_machine == ELF::EM_MIPS &&		return Header->e_machine == ELF::EM_MIPS &&
	Header->getFileClass() == ELF::ELFCLASS64 &&		Header->getFileClass() == ELF::ELFCLASS64 &&
	Header->getDataEncoding() == ELF::ELFDATA2LSB;		Header->getDataEncoding() == ELF::ELFDATA2LSB;
	}		}
	virtual symbol_iterator begin_symbols() const;		Elf_Shdr_Iter begin_sections() const;
	virtual symbol_iterator end_symbols() const;		Elf_Shdr_Iter end_sections() const;
	virtual symbol_iterator begin_dynamic_symbols() const;		Elf_Sym_Iter begin_symbols() const;
	virtual symbol_iterator end_dynamic_symbols() const;		Elf_Sym_Iter end_symbols() const;
	virtual section_iterator begin_sections() const;
	virtual section_iterator end_sections() const;
	virtual library_iterator begin_libraries_needed() const;
	virtual library_iterator end_libraries_needed() const;
	const Elf_Shdr *getDynamicSymbolTableSectionHeader() const {
	return SymbolTableSections[0];
	}
	const Elf_Shdr *getDynamicStringTableSectionHeader() const {		Elf_Dyn_Iter begin_dynamic_table() const;
	return dot_dynstr_sec;
	}
	Elf_Dyn_iterator begin_dynamic_table() const;
	/// \param NULLEnd use one past the first DT_NULL entry as the end instea d of		/// \param NULLEnd use one past the first DT_NULL entry as the end instea d of
	/// the section size.		/// the section size.
	Elf_Dyn_iterator end_dynamic_table(bool NULLEnd = false) const;		Elf_Dyn_Iter end_dynamic_table(bool NULLEnd = false) const;
	Elf_Sym_iterator begin_elf_dynamic_symbols() const {		Elf_Sym_Iter begin_dynamic_symbols() const {
	const Elf_Shdr *DynSymtab = SymbolTableSections[0];		if (DynSymRegion.Addr)
	if (DynSymtab)		return Elf_Sym_Iter(DynSymRegion.EntSize, (const char *)DynSymRegion.
	return Elf_Sym_iterator(DynSymtab->sh_entsize,		Addr,
	(const char *)base() + DynSymtab->sh_offset);		true);
	return Elf_Sym_iterator(0, 0);		return Elf_Sym_Iter(0, 0, true);
	}		}
	Elf_Sym_iterator end_elf_dynamic_symbols() const {		Elf_Sym_Iter end_dynamic_symbols() const {
	const Elf_Shdr *DynSymtab = SymbolTableSections[0];		if (DynSymRegion.Addr)
	if (DynSymtab)		return Elf_Sym_Iter(DynSymRegion.EntSize,
	return Elf_Sym_iterator(DynSymtab->sh_entsize, (const char *)base() +		(const char *)DynSymRegion.Addr + DynSymRegion.Si
	DynSymtab->sh_offset + DynSymtab->sh_size);		ze,
	return Elf_Sym_iterator(0, 0);		true);
			return Elf_Sym_Iter(0, 0, true);
	}		}
	Elf_Rela_Iter beginELFRela(const Elf_Shdr *sec) const {		Elf_Rela_Iter begin_rela(const Elf_Shdr *sec) const {
	return Elf_Rela_Iter(sec->sh_entsize,		return Elf_Rela_Iter(sec->sh_entsize,
	(const char *)(base() + sec->sh_offset));		(const char *)(base() + sec->sh_offset));
	}		}
	Elf_Rela_Iter endELFRela(const Elf_Shdr *sec) const {		Elf_Rela_Iter end_rela(const Elf_Shdr *sec) const {
	return Elf_Rela_Iter(sec->sh_entsize, (const char *)		return Elf_Rela_Iter(
	(base() + sec->sh_offset + sec->sh_size));		sec->sh_entsize,
			(const char *)(base() + sec->sh_offset + sec->sh_size));
	}		}
	Elf_Rel_Iter beginELFRel(const Elf_Shdr *sec) const {		Elf_Rel_Iter begin_rel(const Elf_Shdr *sec) const {
	return Elf_Rel_Iter(sec->sh_entsize,		return Elf_Rel_Iter(sec->sh_entsize,
	(const char *)(base() + sec->sh_offset));		(const char *)(base() + sec->sh_offset));
	}		}
	Elf_Rel_Iter endELFRel(const Elf_Shdr *sec) const {		Elf_Rel_Iter end_rel(const Elf_Shdr *sec) const {
	return Elf_Rel_Iter(sec->sh_entsize, (const char *)		return Elf_Rel_Iter(sec->sh_entsize,
	(base() + sec->sh_offset + sec->sh_size));		(const char *)(base() + sec->sh_offset + sec->sh_si
			ze));
	}		}
	/// \brief Iterate over program header table.		/// \brief Iterate over program header table.
	typedef ELFEntityIterator<const Elf_Phdr> Elf_Phdr_Iter;		typedef ELFEntityIterator<const Elf_Phdr> Elf_Phdr_Iter;
	Elf_Phdr_Iter begin_program_headers() const {		Elf_Phdr_Iter begin_program_headers() const {
	return Elf_Phdr_Iter(Header->e_phentsize,		return Elf_Phdr_Iter(Header->e_phentsize,
	(const char*)base() + Header->e_phoff);		(const char*)base() + Header->e_phoff);
	}		}
	Elf_Phdr_Iter end_program_headers() const {		Elf_Phdr_Iter end_program_headers() const {
	return Elf_Phdr_Iter(Header->e_phentsize,		return Elf_Phdr_Iter(Header->e_phentsize,
	(const char*)base() +		(const char*)base() +
	Header->e_phoff +		Header->e_phoff +
	(Header->e_phnum * Header->e_phentsize));		(Header->e_phnum * Header->e_phentsize));
	}		}
	virtual uint8_t getBytesInAddress() const;
	virtual StringRef getFileFormatName() const;
	virtual StringRef getObjectType() const { return "ELF"; }
	virtual unsigned getArch() const;
	virtual StringRef getLoadName() const;
	virtual error_code getSectionContents(const Elf_Shdr *sec,
	StringRef &Res) const;
	uint64_t getNumSections() const;		uint64_t getNumSections() const;
	uint64_t getStringTableIndex() const;		uintX_t getStringTableIndex() const;
	ELF::Elf64_Word getSymbolTableIndex(const Elf_Sym *symb) const;		ELF::Elf64_Word getSymbolTableIndex(const Elf_Sym *symb) const;
	const Elf_Ehdr *getElfHeader() const;		const Elf_Ehdr *getHeader() const { return Header; }
	const Elf_Shdr *getSection(const Elf_Sym *symb) const;		const Elf_Shdr *getSection(const Elf_Sym *symb) const;
	const Elf_Shdr *getElfSection(section_iterator &It) const;		const Elf_Shdr *getSection(uint32_t Index) const;
	const Elf_Sym *getElfSymbol(symbol_iterator &It) const;		const Elf_Sym *getSymbol(uint32_t index) const;
	const Elf_Sym *getElfSymbol(uint32_t index) const;
			ErrorOr<StringRef> getSymbolName(Elf_Sym_Iter Sym) const;
	// Methods for type inquiry through isa, cast, and dyn_cast
	bool isDyldType() const { return isDyldELFObject; }		/// \brief Get the name of \p Symb.
	static inline bool classof(const Binary *v) {		/// \param SymTab The symbol table section \p Symb is contained in.
	return v->getType() == getELFType(ELFT::TargetEndianness == support::li		/// \param Symb The symbol to get the name of.
	ttle,		///
	ELFT::Is64Bits);		/// \p SymTab is used to lookup the string table to use to get the symbol
	}		's
			/// name.
			ErrorOr<StringRef> getSymbolName(const Elf_Shdr *SymTab,
			const Elf_Sym *Symb) const;
			ErrorOr<StringRef> getSectionName(const Elf_Shdr *Section) const;
			uint64_t getSymbolIndex(const Elf_Sym *sym) const;
			ErrorOr<ArrayRef<uint8_t> > getSectionContents(const Elf_Shdr *Sec) const
			;
			StringRef getLoadName() const;
	};		};
			// Use an alignment of 2 for the typedefs since that is the worst case for
			// ELF files in archives.
			typedef ELFFile<ELFType<support::little, 2, false> > ELF32LEFile;
			typedef ELFFile<ELFType<support::little, 2, true> > ELF64LEFile;
			typedef ELFFile<ELFType<support::big, 2, false> > ELF32BEFile;
			typedef ELFFile<ELFType<support::big, 2, true> > ELF64BEFile;
	// Iterate through the version definitions, and place each Elf_Verdef		// Iterate through the version definitions, and place each Elf_Verdef
	// in the VersionMap according to its index.		// in the VersionMap according to its index.
	template<class ELFT>		template <class ELFT>
	void ELFObjectFile<ELFT>::LoadVersionDefs(const Elf_Shdr *sec) const {		void ELFFile<ELFT>::LoadVersionDefs(const Elf_Shdr *sec) const {
	unsigned vd_size = sec->sh_size; // Size of section in bytes		unsigned vd_size = sec->sh_size; // Size of section in bytes
	unsigned vd_count = sec->sh_info; // Number of Verdef entries		unsigned vd_count = sec->sh_info; // Number of Verdef entries
	const char *sec_start = (const char*)base() + sec->sh_offset;		const char *sec_start = (const char*)base() + sec->sh_offset;
	const char *sec_end = sec_start + vd_size;		const char *sec_end = sec_start + vd_size;
	// The first Verdef entry is at the start of the section.		// The first Verdef entry is at the start of the section.
	const char *p = sec_start;		const char *p = sec_start;
	for (unsigned i = 0; i < vd_count; i++) {		for (unsigned i = 0; i < vd_count; i++) {
	if (p + sizeof(Elf_Verdef) > sec_end)		if (p + sizeof(Elf_Verdef) > sec_end)
	report_fatal_error("Section ended unexpectedly while scanning "		report_fatal_error("Section ended unexpectedly while scanning "
	"version definitions.");		"version definitions.");
	const Elf_Verdef *vd = reinterpret_cast<const Elf_Verdef *>(p);		const Elf_Verdef *vd = reinterpret_cast<const Elf_Verdef *>(p);
	if (vd->vd_version != ELF::VER_DEF_CURRENT)		if (vd->vd_version != ELF::VER_DEF_CURRENT)
	report_fatal_error("Unexpected verdef version");		report_fatal_error("Unexpected verdef version");
	size_t index = vd->vd_ndx & ELF::VERSYM_VERSION;		size_t index = vd->vd_ndx & ELF::VERSYM_VERSION;
	if (index >= VersionMap.size())		if (index >= VersionMap.size())
	VersionMap.resize(index+1);		VersionMap.resize(index + 1);
	VersionMap[index] = VersionMapEntry(vd);		VersionMap[index] = VersionMapEntry(vd);
	p += vd->vd_next;		p += vd->vd_next;
	}		}
	}		}
	// Iterate through the versions needed section, and place each Elf_Vernaux		// Iterate through the versions needed section, and place each Elf_Vernaux
	// in the VersionMap according to its index.		// in the VersionMap according to its index.
	template<class ELFT>		template <class ELFT>
	void ELFObjectFile<ELFT>::LoadVersionNeeds(const Elf_Shdr *sec) const {		void ELFFile<ELFT>::LoadVersionNeeds(const Elf_Shdr *sec) const {
	unsigned vn_size = sec->sh_size; // Size of section in bytes		unsigned vn_size = sec->sh_size; // Size of section in bytes
	unsigned vn_count = sec->sh_info; // Number of Verneed entries		unsigned vn_count = sec->sh_info; // Number of Verneed entries
	const char *sec_start = (const char*)base() + sec->sh_offset;		const char *sec_start = (const char *)base() + sec->sh_offset;
	const char *sec_end = sec_start + vn_size;		const char *sec_end = sec_start + vn_size;
	// The first Verneed entry is at the start of the section.		// The first Verneed entry is at the start of the section.
	const char *p = sec_start;		const char *p = sec_start;
	for (unsigned i = 0; i < vn_count; i++) {		for (unsigned i = 0; i < vn_count; i++) {
	if (p + sizeof(Elf_Verneed) > sec_end)		if (p + sizeof(Elf_Verneed) > sec_end)
	report_fatal_error("Section ended unexpectedly while scanning "		report_fatal_error("Section ended unexpectedly while scanning "
	"version needed records.");		"version needed records.");
	const Elf_Verneed *vn = reinterpret_cast<const Elf_Verneed *>(p);		const Elf_Verneed *vn = reinterpret_cast<const Elf_Verneed *>(p);
	if (vn->vn_version != ELF::VER_NEED_CURRENT)		if (vn->vn_version != ELF::VER_NEED_CURRENT)
	report_fatal_error("Unexpected verneed version");		report_fatal_error("Unexpected verneed version");
	// Iterate through the Vernaux entries		// Iterate through the Vernaux entries
	const char *paux = p + vn->vn_aux;		const char *paux = p + vn->vn_aux;
	for (unsigned j = 0; j < vn->vn_cnt; j++) {		for (unsigned j = 0; j < vn->vn_cnt; j++) {
	if (paux + sizeof(Elf_Vernaux) > sec_end)		if (paux + sizeof(Elf_Vernaux) > sec_end)
	report_fatal_error("Section ended unexpected while scanning auxilia ry "		report_fatal_error("Section ended unexpected while scanning auxilia ry "
	"version needed records.");		"version needed records.");
	const Elf_Vernaux *vna = reinterpret_cast<const Elf_Vernaux *>(paux);		const Elf_Vernaux *vna = reinterpret_cast<const Elf_Vernaux *>(paux);
	size_t index = vna->vna_other & ELF::VERSYM_VERSION;		size_t index = vna->vna_other & ELF::VERSYM_VERSION;
	if (index >= VersionMap.size())		if (index >= VersionMap.size())
	VersionMap.resize(index+1);		VersionMap.resize(index + 1);
	VersionMap[index] = VersionMapEntry(vna);		VersionMap[index] = VersionMapEntry(vna);
	paux += vna->vna_next;		paux += vna->vna_next;
	}		}
	p += vn->vn_next;		p += vn->vn_next;
	}		}
	}		}
	template<class ELFT>		template <class ELFT>
	void ELFObjectFile<ELFT>::LoadVersionMap() const {		void ELFFile<ELFT>::LoadVersionMap() const {
	// If there is no dynamic symtab or version table, there is nothing to do .		// If there is no dynamic symtab or version table, there is nothing to do .
	if (SymbolTableSections[0] == NULL || dot_gnu_version_sec == NULL)		if (DynSymRegion.Addr == NULL || dot_gnu_version_sec == NULL)
	return;		return;
	// Has the VersionMap already been loaded?		// Has the VersionMap already been loaded?
	if (VersionMap.size() > 0)		if (VersionMap.size() > 0)
	return;		return;
	// The first two version indexes are reserved.		// The first two version indexes are reserved.
	// Index 0 is LOCAL, index 1 is GLOBAL.		// Index 0 is LOCAL, index 1 is GLOBAL.
	VersionMap.push_back(VersionMapEntry());		VersionMap.push_back(VersionMapEntry());
	VersionMap.push_back(VersionMapEntry());		VersionMap.push_back(VersionMapEntry());
	if (dot_gnu_version_d_sec)		if (dot_gnu_version_d_sec)
	LoadVersionDefs(dot_gnu_version_d_sec);		LoadVersionDefs(dot_gnu_version_d_sec);
	if (dot_gnu_version_r_sec)		if (dot_gnu_version_r_sec)
	LoadVersionNeeds(dot_gnu_version_r_sec);		LoadVersionNeeds(dot_gnu_version_r_sec);
	}		}
	template<class ELFT>		template <class ELFT>
	void ELFObjectFile<ELFT>::validateSymbol(DataRefImpl Symb) const {		ELF::Elf64_Word ELFFile<ELFT>::getSymbolTableIndex(const Elf_Sym *symb) con
	#ifndef NDEBUG		st {
	const Elf_Sym *symb = getSymbol(Symb);
	const Elf_Shdr *SymbolTableSection = SymbolTableSections[Symb.d.b];
	// FIXME: We really need to do proper error handling in the case of an in
	valid
	// input file. Because we don't use exceptions, I think we'll just
	pass
	// an error object around.
	if (!( symb
	&& SymbolTableSection
	&& symb >= (const Elf_Sym*)(base()
	+ SymbolTableSection->sh_offset)
	&& symb < (const Elf_Sym*)(base()
	+ SymbolTableSection->sh_offset
	+ SymbolTableSection->sh_size)))
	// FIXME: Proper error handling.
	report_fatal_error("Symb must point to a valid symbol!");
	#endif
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getSymbolNext(DataRefImpl Symb,
	SymbolRef &Result) const {
	validateSymbol(Symb);
	const Elf_Shdr *SymbolTableSection = SymbolTableSections[Symb.d.b];
	++Symb.d.a;
	// Check to see if we are at the end of this symbol table.
	if (Symb.d.a >= SymbolTableSection->getEntityCount()) {
	// We are at the end. If there are other symbol tables, jump to them.
	// If the symbol table is .dynsym, we are iterating dynamic symbols,
	// and there is only one table of these.
	if (Symb.d.b != 0) {
	++Symb.d.b;
	Symb.d.a = 1; // The 0th symbol in ELF is fake.
	}
	// Otherwise return the terminator.
	if (Symb.d.b == 0 || Symb.d.b >= SymbolTableSections.size()) {
	Symb.d.a = std::numeric_limits<uint32_t>::max();
	Symb.d.b = std::numeric_limits<uint32_t>::max();
	}
	}
	Result = SymbolRef(Symb, this);
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getSymbolName(DataRefImpl Symb,
	StringRef &Result) const {
	validateSymbol(Symb);
	const Elf_Sym *symb = getSymbol(Symb);
	return getSymbolName(SymbolTableSections[Symb.d.b], symb, Result);
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getSymbolVersion(SymbolRef SymRef,
	StringRef &Version,
	bool &IsDefault) const {
	DataRefImpl Symb = SymRef.getRawDataRefImpl();
	validateSymbol(Symb);
	const Elf_Sym *symb = getSymbol(Symb);
	return getSymbolVersion(SymbolTableSections[Symb.d.b], symb,
	Version, IsDefault);
	}
	template<class ELFT>
	ELF::Elf64_Word ELFObjectFile<ELFT>
	::getSymbolTableIndex(const Elf_Sym *symb) con
	st {
	if (symb->st_shndx == ELF::SHN_XINDEX)		if (symb->st_shndx == ELF::SHN_XINDEX)
	return ExtendedSymbolTable.lookup(symb);		return ExtendedSymbolTable.lookup(symb);
	return symb->st_shndx;		return symb->st_shndx;
	}		}
	template<class ELFT>		template <class ELFT>
	const typename ELFObjectFile<ELFT>::Elf_Shdr *		const typename ELFFile<ELFT>::Elf_Shdr *
	ELFObjectFile<ELFT>::getSection(const Elf_Sym *symb) const {		ELFFile<ELFT>::getSection(const Elf_Sym *symb) const {
	if (symb->st_shndx == ELF::SHN_XINDEX)		if (symb->st_shndx == ELF::SHN_XINDEX)
	return getSection(ExtendedSymbolTable.lookup(symb));		return getSection(ExtendedSymbolTable.lookup(symb));
	if (symb->st_shndx >= ELF::SHN_LORESERVE)		if (symb->st_shndx >= ELF::SHN_LORESERVE)
	return 0;		return 0;
	return getSection(symb->st_shndx);		return getSection(symb->st_shndx);
	}		}
	template<class ELFT>		template <class ELFT>
	const typename ELFObjectFile<ELFT>::Elf_Ehdr *		const typename ELFFile<ELFT>::Elf_Sym *
	ELFObjectFile<ELFT>::getElfHeader() const {		ELFFile<ELFT>::getSymbol(uint32_t Index) const {
	return Header;		return &*(begin_symbols() + Index);
	}
	template<class ELFT>
	const typename ELFObjectFile<ELFT>::Elf_Shdr *
	ELFObjectFile<ELFT>::getElfSection(section_iterator &It) const {
	llvm::object::DataRefImpl ShdrRef = It->getRawDataRefImpl();
	return reinterpret_cast<const Elf_Shdr *>(ShdrRef.p);
	}
	template<class ELFT>
	const typename ELFObjectFile<ELFT>::Elf_Sym *
	ELFObjectFile<ELFT>::getElfSymbol(symbol_iterator &It) const {
	return getSymbol(It->getRawDataRefImpl());
	}
	template<class ELFT>
	const typename ELFObjectFile<ELFT>::Elf_Sym *
	ELFObjectFile<ELFT>::getElfSymbol(uint32_t index) const {
	DataRefImpl SymbolData;
	SymbolData.d.a = index;
	SymbolData.d.b = 1;
	return getSymbol(SymbolData);
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getSymbolFileOffset(DataRefImpl Symb,
	uint64_t &Result) const
	{
	validateSymbol(Symb);
	const Elf_Sym *symb = getSymbol(Symb);
	const Elf_Shdr *Section;
	switch (getSymbolTableIndex(symb)) {
	case ELF::SHN_COMMON:
	// Unintialized symbols have no offset in the object file
	case ELF::SHN_UNDEF:
	Result = UnknownAddressOrSize;
	return object_error::success;
	case ELF::SHN_ABS:
	Result = symb->st_value;
	return object_error::success;
	default: Section = getSection(symb);
	}
	switch (symb->getType()) {
	case ELF::STT_SECTION:
	Result = Section ? Section->sh_offset : UnknownAddressOrSize;
	return object_error::success;
	case ELF::STT_FUNC:
	case ELF::STT_OBJECT:
	case ELF::STT_NOTYPE:
	Result = symb->st_value +
	(Section ? Section->sh_offset : 0);
	return object_error::success;
	default:
	Result = UnknownAddressOrSize;
	return object_error::success;
	}
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getSymbolAddress(DataRefImpl Symb,
	uint64_t &Result) const {
	validateSymbol(Symb);
	const Elf_Sym *symb = getSymbol(Symb);
	const Elf_Shdr *Section;
	switch (getSymbolTableIndex(symb)) {
	case ELF::SHN_COMMON:
	case ELF::SHN_UNDEF:
	Result = UnknownAddressOrSize;
	return object_error::success;
	case ELF::SHN_ABS:
	Result = symb->st_value;
	return object_error::success;
	default: Section = getSection(symb);
	}
	switch (symb->getType()) {
	case ELF::STT_SECTION:
	Result = Section ? Section->sh_addr : UnknownAddressOrSize;
	return object_error::success;
	case ELF::STT_FUNC:
	case ELF::STT_OBJECT:
	case ELF::STT_NOTYPE:
	bool IsRelocatable;
	switch(Header->e_type) {
	case ELF::ET_EXEC:
	case ELF::ET_DYN:
	IsRelocatable = false;
	break;
	default:
	IsRelocatable = true;
	}
	Result = symb->st_value;
	// Clear the ARM/Thumb indicator flag.
	if (Header->e_machine == ELF::EM_ARM)
	Result &= ~1;
	if (IsRelocatable && Section != 0)
	Result += Section->sh_addr;
	return object_error::success;
	default:
	Result = UnknownAddressOrSize;
	return object_error::success;
	}
	}		}
	template<class ELFT>		template <class ELFT>
	error_code ELFObjectFile<ELFT>::getSymbolAlignment(DataRefImpl Symb,		ErrorOr<ArrayRef<uint8_t> >
	uint32_t &Res) const {		ELFFile<ELFT>::getSectionContents(const Elf_Shdr *Sec) const {
	uint32_t flags;		if (Sec->sh_offset + Sec->sh_size > Buf->getBufferSize())
	getSymbolFlags(Symb, flags);		return object_error::parse_failed;
	if (flags & SymbolRef::SF_Common) {		const uint8_t *Start = base() + Sec->sh_offset;
	uint64_t Value;		return ArrayRef<uint8_t>(Start, Sec->sh_size);
	getSymbolValue(Symb, Value);
	Res = Value;
	} else {
	Res = 0;
	}
	return object_error::success;
	}		}
	template<class ELFT>		template <class ELFT>
	error_code ELFObjectFile<ELFT>::getSymbolSize(DataRefImpl Symb,		StringRef ELFFile<ELFT>::getRelocationTypeName(uint32_t Type) const {
	uint64_t &Result) const {		return getELFRelocationTypeName(Header->e_machine, Type);
	validateSymbol(Symb);
	const Elf_Sym *symb = getSymbol(Symb);
	if (symb->st_size == 0)
	Result = UnknownAddressOrSize;
	Result = symb->st_size;
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getSymbolNMTypeChar(DataRefImpl Symb,
	char &Result) const {
	validateSymbol(Symb);
	const Elf_Sym *symb = getSymbol(Symb);
	const Elf_Shdr *Section = getSection(symb);
	char ret = '?';
	if (Section) {
	switch (Section->sh_type) {
	case ELF::SHT_PROGBITS:
	case ELF::SHT_DYNAMIC:
	switch (Section->sh_flags) {
	case (ELF::SHF_ALLOC | ELF::SHF_EXECINSTR):
	ret = 't'; break;
	case (ELF::SHF_ALLOC | ELF::SHF_WRITE):
	ret = 'd'; break;
	case ELF::SHF_ALLOC:
	case (ELF::SHF_ALLOC | ELF::SHF_MERGE):
	case (ELF::SHF_ALLOC | ELF::SHF_MERGE | ELF::SHF_STRINGS):
	ret = 'r'; break;
	}
	break;
	case ELF::SHT_NOBITS: ret = 'b';
	}
	}
	switch (getSymbolTableIndex(symb)) {
	case ELF::SHN_UNDEF:
	if (ret == '?')
	ret = 'U';
	break;
	case ELF::SHN_ABS: ret = 'a'; break;
	case ELF::SHN_COMMON: ret = 'c'; break;
	}
	switch (symb->getBinding()) {
	case ELF::STB_GLOBAL: ret = ::toupper(ret); break;
	case ELF::STB_WEAK:
	if (getSymbolTableIndex(symb) == ELF::SHN_UNDEF)
	ret = 'w';
	else
	if (symb->getType() == ELF::STT_OBJECT)
	ret = 'V';
	else
	ret = 'W';
	}
	if (ret == '?' && symb->getType() == ELF::STT_SECTION) {
	StringRef name;
	if (error_code ec = getSymbolName(Symb, name))
	return ec;
	Result = StringSwitch<char>(name)
	.StartsWith(".debug", 'N')
	.StartsWith(".note", 'n')
	.Default('?');
	return object_error::success;
	}
	Result = ret;
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getSymbolType(DataRefImpl Symb,
	SymbolRef::Type &Result) cons
	t {
	validateSymbol(Symb);
	const Elf_Sym *symb = getSymbol(Symb);
	switch (symb->getType()) {
	case ELF::STT_NOTYPE:
	Result = SymbolRef::ST_Unknown;
	break;
	case ELF::STT_SECTION:
	Result = SymbolRef::ST_Debug;
	break;
	case ELF::STT_FILE:
	Result = SymbolRef::ST_File;
	break;
	case ELF::STT_FUNC:
	Result = SymbolRef::ST_Function;
	break;
	case ELF::STT_OBJECT:
	case ELF::STT_COMMON:
	case ELF::STT_TLS:
	Result = SymbolRef::ST_Data;
	break;
	default:
	Result = SymbolRef::ST_Other;
	break;
	}
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getSymbolFlags(DataRefImpl Symb,
	uint32_t &Result) const {
	validateSymbol(Symb);
	const Elf_Sym *symb = getSymbol(Symb);
	Result = SymbolRef::SF_None;
	if (symb->getBinding() != ELF::STB_LOCAL)
	Result |= SymbolRef::SF_Global;
	if (symb->getBinding() == ELF::STB_WEAK)
	Result |= SymbolRef::SF_Weak;
	if (symb->st_shndx == ELF::SHN_ABS)
	Result |= SymbolRef::SF_Absolute;
	if (symb->getType() == ELF::STT_FILE ||
	symb->getType() == ELF::STT_SECTION)
	Result |= SymbolRef::SF_FormatSpecific;
	if (getSymbolTableIndex(symb) == ELF::SHN_UNDEF)
	Result |= SymbolRef::SF_Undefined;
	if (symb->getType() == ELF::STT_COMMON ||
	getSymbolTableIndex(symb) == ELF::SHN_COMMON)
	Result |= SymbolRef::SF_Common;
	if (symb->getType() == ELF::STT_TLS)
	Result |= SymbolRef::SF_ThreadLocal;
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getSymbolSection(DataRefImpl Symb,
	section_iterator &Res) con
	st {
	validateSymbol(Symb);
	const Elf_Sym *symb = getSymbol(Symb);
	const Elf_Shdr *sec = getSection(symb);
	if (!sec)
	Res = end_sections();
	else {
	DataRefImpl Sec;
	Sec.p = reinterpret_cast<intptr_t>(sec);
	Res = section_iterator(SectionRef(Sec, this));
	}
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getSymbolValue(DataRefImpl Symb,
	uint64_t &Val) const {
	validateSymbol(Symb);
	const Elf_Sym *symb = getSymbol(Symb);
	Val = symb->st_value;
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getSectionNext(DataRefImpl Sec,
	SectionRef &Result) const {
	const uint8_t *sec = reinterpret_cast<const uint8_t *>(Sec.p);
	sec += Header->e_shentsize;
	Sec.p = reinterpret_cast<intptr_t>(sec);
	Result = SectionRef(Sec, this);
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getSectionName(DataRefImpl Sec,
	StringRef &Result) const {
	const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
	Result = StringRef(getString(dot_shstrtab_sec, sec->sh_name));
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getSectionAddress(DataRefImpl Sec,
	uint64_t &Result) const {
	const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
	Result = sec->sh_addr;
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getSectionSize(DataRefImpl Sec,
	uint64_t &Result) const {
	const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
	Result = sec->sh_size;
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getSectionContents(DataRefImpl Sec,
	StringRef &Result) const
	{
	const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
	const char *start = (const char*)base() + sec->sh_offset;
	Result = StringRef(start, sec->sh_size);
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getSectionContents(const Elf_Shdr *Sec,
	StringRef &Result) const
	{
	const char *start = (const char*)base() + Sec->sh_offset;
	Result = StringRef(start, Sec->sh_size);
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getSectionAlignment(DataRefImpl Sec,
	uint64_t &Result) const
	{
	const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
	Result = sec->sh_addralign;
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::isSectionText(DataRefImpl Sec,
	bool &Result) const {
	const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
	if (sec->sh_flags & ELF::SHF_EXECINSTR)
	Result = true;
	else
	Result = false;
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::isSectionData(DataRefImpl Sec,
	bool &Result) const {
	const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
	if (sec->sh_flags & (ELF::SHF_ALLOC | ELF::SHF_WRITE)
	&& sec->sh_type == ELF::SHT_PROGBITS)
	Result = true;
	else
	Result = false;
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::isSectionBSS(DataRefImpl Sec,
	bool &Result) const {
	const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
	if (sec->sh_flags & (ELF::SHF_ALLOC | ELF::SHF_WRITE)
	&& sec->sh_type == ELF::SHT_NOBITS)
	Result = true;
	else
	Result = false;
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::isSectionRequiredForExecution(
	DataRefImpl Sec, bool &Result) const {
	const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
	if (sec->sh_flags & ELF::SHF_ALLOC)
	Result = true;
	else
	Result = false;
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::isSectionVirtual(DataRefImpl Sec,
	bool &Result) const {
	const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
	if (sec->sh_type == ELF::SHT_NOBITS)
	Result = true;
	else
	Result = false;
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::isSectionZeroInit(DataRefImpl Sec,
	bool &Result) const {
	const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
	// For ELF, all zero-init sections are virtual (that is, they occupy no s
	pace
	// in the object image) and vice versa.
	Result = sec->sh_type == ELF::SHT_NOBITS;
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::isSectionReadOnlyData(DataRefImpl Sec,
	bool &Result) const {
	const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
	if (sec->sh_flags & ELF::SHF_WRITE || sec->sh_flags & ELF::SHF_EXECINSTR)
	Result = false;
	else
	Result = true;
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::sectionContainsSymbol(DataRefImpl Sec,
	DataRefImpl Symb,
	bool &Result) const {
	validateSymbol(Symb);
	const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
	const Elf_Sym *symb = getSymbol(Symb);
	unsigned shndx = symb->st_shndx;
	bool Reserved = shndx >= ELF::SHN_LORESERVE
	&& shndx <= ELF::SHN_HIRESERVE;
	Result = !Reserved && (sec == getSection(symb->st_shndx));
	return object_error::success;
	}
	template<class ELFT>
	relocation_iterator
	ELFObjectFile<ELFT>::getSectionRelBegin(DataRefImpl Sec) const {
	DataRefImpl RelData;
	const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
	typename RelocMap_t::const_iterator ittr = SectionRelocMap.find(sec);
	if (sec != 0 && ittr != SectionRelocMap.end()) {
	RelData.w.a = getSection(ittr->second[0])->sh_info;
	RelData.w.b = ittr->second[0];
	RelData.w.c = 0;
	}
	return relocation_iterator(RelocationRef(RelData, this));
	}
	template<class ELFT>
	relocation_iterator
	ELFObjectFile<ELFT>::getSectionRelEnd(DataRefImpl Sec) const {
	DataRefImpl RelData;
	const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
	typename RelocMap_t::const_iterator ittr = SectionRelocMap.find(sec);
	if (sec != 0 && ittr != SectionRelocMap.end()) {
	// Get the index of the last relocation section for this section.
	std::size_t relocsecindex = ittr->second[ittr->second.size() - 1];
	const Elf_Shdr *relocsec = getSection(relocsecindex);
	RelData.w.a = relocsec->sh_info;
	RelData.w.b = relocsecindex;
	RelData.w.c = relocsec->sh_size / relocsec->sh_entsize;
	}
	return relocation_iterator(RelocationRef(RelData, this));
	}
	// Relocations
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getRelocationNext(DataRefImpl Rel,
	RelocationRef &Result) co
	nst {
	++Rel.w.c;
	const Elf_Shdr *relocsec = getSection(Rel.w.b);
	if (Rel.w.c >= (relocsec->sh_size / relocsec->sh_entsize)) {
	// We have reached the end of the relocations for this section. See if
	there
	// is another relocation section.
	typename RelocMap_t::mapped_type relocseclist =
	SectionRelocMap.lookup(getSection(Rel.w.a));
	// Do a binary search for the current reloc section index (which must b
	e
	// present). Then get the next one.
	typename RelocMap_t::mapped_type::const_iterator loc =
	std::lower_bound(relocseclist.begin(), relocseclist.end(), Rel.w.b);
	++loc;
	// If there is no next one, don't do anything. The ++Rel.w.c above sets
	Rel
	// to the end iterator.
	if (loc != relocseclist.end()) {
	Rel.w.b = *loc;
	Rel.w.a = 0;
	}
	}
	Result = RelocationRef(Rel, this);
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getRelocationSymbol(DataRefImpl Rel,
	SymbolRef &Result) cons
	t {
	uint32_t symbolIdx;
	const Elf_Shdr *sec = getSection(Rel.w.b);
	switch (sec->sh_type) {
	default :
	report_fatal_error("Invalid section type in Rel!");
	case ELF::SHT_REL : {
	symbolIdx = getRel(Rel)->getSymbol(isMips64EL());
	break;
	}
	case ELF::SHT_RELA : {
	symbolIdx = getRela(Rel)->getSymbol(isMips64EL());
	break;
	}
	}
	DataRefImpl SymbolData;
	IndexMap_t::const_iterator it = SymbolTableSectionsIndexMap.find(sec->sh_
	link);
	if (it == SymbolTableSectionsIndexMap.end())
	report_fatal_error("Relocation symbol table not found!");
	SymbolData.d.a = symbolIdx;
	SymbolData.d.b = it->second;
	Result = SymbolRef(SymbolData, this);
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getRelocationAddress(DataRefImpl Rel,
	uint64_t &Result) cons
	t {
	assert((Header->e_type == ELF::ET_EXEC || Header->e_type == ELF::ET_DYN)
	&&
	"Only executable and shared objects files have addresses");
	Result = getROffset(Rel);
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getRelocationOffset(DataRefImpl Rel,
	uint64_t &Result) const
	{
	assert(Header->e_type == ELF::ET_REL &&
	"Only relocatable object files have relocation offsets");
	Result = getROffset(Rel);
	return object_error::success;
	}
	template<class ELFT>
	uint64_t ELFObjectFile<ELFT>::getROffset(DataRefImpl Rel) const {
	const Elf_Shdr *sec = getSection(Rel.w.b);
	switch (sec->sh_type) {
	default:
	report_fatal_error("Invalid section type in Rel!");
	case ELF::SHT_REL:
	return getRel(Rel)->r_offset;
	case ELF::SHT_RELA:
	return getRela(Rel)->r_offset;
	}
	}		}
	template<class ELFT>		template <class ELFT>
	error_code ELFObjectFile<ELFT>::getRelocationType(DataRefImpl Rel,		void ELFFile<ELFT>::getRelocationTypeName(uint32_t Type,
	uint64_t &Result) const {		SmallVectorImpl<char> &Result) co
	const Elf_Shdr *sec = getSection(Rel.w.b);		nst {
	switch (sec->sh_type) {
	default :
	report_fatal_error("Invalid section type in Rel!");
	case ELF::SHT_REL : {
	Result = getRel(Rel)->getType(isMips64EL());
	break;
	}
	case ELF::SHT_RELA : {
	Result = getRela(Rel)->getType(isMips64EL());
	break;
	}
	}
	return object_error::success;
	}
	#define LLVM_ELF_SWITCH_RELOC_TYPE_NAME(enum) \
	case ELF::enum: Res = #enum; break;
	template<class ELFT>
	StringRef ELFObjectFile<ELFT>::getRelocationTypeName(uint32_t Type) const {
	StringRef Res = "Unknown";
	switch (Header->e_machine) {
	case ELF::EM_X86_64:
	switch (Type) {
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_NONE);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_PC32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_GOT32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_PLT32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_COPY);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_GLOB_DAT);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_JUMP_SLOT);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_RELATIVE);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_GOTPCREL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_32S);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_PC16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_8);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_PC8);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_DTPMOD64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_DTPOFF64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_TPOFF64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_TLSGD);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_TLSLD);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_DTPOFF32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_GOTTPOFF);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_TPOFF32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_PC64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_GOTOFF64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_GOTPC32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_GOT64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_GOTPCREL64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_GOTPC64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_GOTPLT64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_PLTOFF64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_SIZE32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_SIZE64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_GOTPC32_TLSDESC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_TLSDESC_CALL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_TLSDESC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_X86_64_IRELATIVE);
	default: break;
	}
	break;
	case ELF::EM_386:
	switch (Type) {
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_NONE);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_PC32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_GOT32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_PLT32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_COPY);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_GLOB_DAT);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_JUMP_SLOT);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_RELATIVE);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_GOTOFF);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_GOTPC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_32PLT);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_TPOFF);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_IE);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_GOTIE);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_LE);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_GD);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_LDM);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_PC16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_8);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_PC8);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_GD_32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_GD_PUSH);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_GD_CALL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_GD_POP);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_LDM_32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_LDM_PUSH);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_LDM_CALL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_LDM_POP);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_LDO_32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_IE_32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_LE_32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_DTPMOD32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_DTPOFF32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_TPOFF32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_GOTDESC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_DESC_CALL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_TLS_DESC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_386_IRELATIVE);
	default: break;
	}
	break;
	case ELF::EM_MIPS:
	switch (Type) {
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_NONE);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_REL32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_26);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_HI16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_LO16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_GPREL16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_LITERAL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_GOT16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_PC16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_CALL16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_GPREL32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_SHIFT5);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_SHIFT6);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_GOT_DISP);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_GOT_PAGE);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_GOT_OFST);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_GOT_HI16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_GOT_LO16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_SUB);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_INSERT_A);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_INSERT_B);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_DELETE);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_HIGHER);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_HIGHEST);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_CALL_HI16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_CALL_LO16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_SCN_DISP);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_REL16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_ADD_IMMEDIATE);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_PJUMP);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_RELGOT);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_JALR);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_TLS_DTPMOD32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_TLS_DTPREL32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_TLS_DTPMOD64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_TLS_DTPREL64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_TLS_GD);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_TLS_LDM);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_TLS_DTPREL_HI16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_TLS_DTPREL_LO16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_TLS_GOTTPREL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_TLS_TPREL32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_TLS_TPREL64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_TLS_TPREL_HI16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_TLS_TPREL_LO16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_GLOB_DAT);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_COPY);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_JUMP_SLOT);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_MIPS_NUM);
	default: break;
	}
	break;
	case ELF::EM_AARCH64:
	switch (Type) {
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_NONE);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_ABS64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_ABS32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_ABS16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_PREL64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_PREL32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_PREL16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_MOVW_UABS_G0);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_MOVW_UABS_G0_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_MOVW_UABS_G1);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_MOVW_UABS_G1_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_MOVW_UABS_G2);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_MOVW_UABS_G2_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_MOVW_UABS_G3);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_MOVW_SABS_G0);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_MOVW_SABS_G1);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_MOVW_SABS_G2);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_LD_PREL_LO19);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_ADR_PREL_LO21);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_ADR_PREL_PG_HI21);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_ADD_ABS_LO12_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_LDST8_ABS_LO12_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TSTBR14);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_CONDBR19);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_JUMP26);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_CALL26);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_LDST16_ABS_LO12_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_LDST32_ABS_LO12_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_LDST64_ABS_LO12_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_LDST128_ABS_LO12_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_ADR_GOT_PAGE);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_LD64_GOT_LO12_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_MOVW_DTPREL_G2);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_MOVW_DTPREL_G1);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_MOVW_DTPREL_G0);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_ADD_DTPREL_HI12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_ADD_DTPREL_LO12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_LDST8_DTPREL_LO12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC)
	;
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_LDST16_DTPREL_LO12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
	);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_LDST32_DTPREL_LO12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
	);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_LDST64_DTPREL_LO12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
	);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSIE_MOVW_GOTTPREL_G1);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
	);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSIE_LD_GOTTPREL_PREL19);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_MOVW_TPREL_G2);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_MOVW_TPREL_G1);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_MOVW_TPREL_G1_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_MOVW_TPREL_G0);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_MOVW_TPREL_G0_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_ADD_TPREL_HI12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_ADD_TPREL_LO12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_ADD_TPREL_LO12_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_LDST8_TPREL_LO12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_LDST16_TPREL_LO12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC)
	;
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_LDST32_TPREL_LO12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC)
	;
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_LDST64_TPREL_LO12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC)
	;
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSDESC_ADR_PAGE);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSDESC_LD64_LO12_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSDESC_ADD_LO12_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSDESC_CALL);
	default: break;
	}
	break;
	case ELF::EM_ARM:
	switch (Type) {
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_NONE);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PC24);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ABS32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_REL32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDR_PC_G0);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ABS16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ABS12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_ABS5);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ABS8);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_SBREL32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_CALL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_PC8);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_BREL_ADJ);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_DESC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_SWI8);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_XPC25);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_XPC22);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_DTPMOD32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_DTPOFF32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_TPOFF32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_COPY);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_GLOB_DAT);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_JUMP_SLOT);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_RELATIVE);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_GOTOFF32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_BASE_PREL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_GOT_BREL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PLT32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_CALL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_JUMP24);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_JUMP24);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_BASE_ABS);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_PCREL_7_0);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_PCREL_15_8);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_PCREL_23_15);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDR_SBREL_11_0_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_SBREL_19_12_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_SBREL_27_20_CK);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TARGET1);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_SBREL31);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_V4BX);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TARGET2);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PREL31);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_MOVW_ABS_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_MOVT_ABS);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_MOVW_PREL_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_MOVT_PREL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_MOVW_ABS_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_MOVT_ABS);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_MOVW_PREL_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_MOVT_PREL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_JUMP19);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_JUMP6);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_ALU_PREL_11_0);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_PC12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ABS32_NOI);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_REL32_NOI);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_PC_G0_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_PC_G0);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_PC_G1_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_PC_G1);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_PC_G2);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDR_PC_G1);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDR_PC_G2);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDRS_PC_G0);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDRS_PC_G1);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDRS_PC_G2);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDC_PC_G0);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDC_PC_G1);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDC_PC_G2);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_SB_G0_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_SB_G0);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_SB_G1_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_SB_G1);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ALU_SB_G2);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDR_SB_G0);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDR_SB_G1);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDR_SB_G2);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDRS_SB_G0);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDRS_SB_G1);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDRS_SB_G2);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDC_SB_G0);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDC_SB_G1);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_LDC_SB_G2);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_MOVW_BREL_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_MOVT_BREL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_MOVW_BREL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_MOVW_BREL_NC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_MOVT_BREL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_MOVW_BREL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_GOTDESC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_CALL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_DESCSEQ);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_TLS_CALL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PLT32_ABS);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_GOT_ABS);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_GOT_PREL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_GOT_BREL12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_GOTOFF12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_GOTRELAX);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_GNU_VTENTRY);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_GNU_VTINHERIT);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_JUMP11);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_JUMP8);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_GD32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_LDM32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_LDO32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_IE32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_LE32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_LDO12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_LE12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_TLS_IE12GP);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_0);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_1);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_2);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_3);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_4);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_5);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_6);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_7);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_8);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_9);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_10);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_11);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_13);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_14);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_PRIVATE_15);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_ME_TOO);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_TLS_DESCSEQ16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_ARM_THM_TLS_DESCSEQ32);
	default: break;
	}
	break;
	case ELF::EM_HEXAGON:
	switch (Type) {
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_NONE);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_B22_PCREL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_B15_PCREL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_B7_PCREL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_LO16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_HI16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_8);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GPREL16_0);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GPREL16_1);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GPREL16_2);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GPREL16_3);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_HL16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_B13_PCREL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_B9_PCREL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_B32_PCREL_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_32_6_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_B22_PCREL_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_B15_PCREL_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_B13_PCREL_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_B9_PCREL_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_B7_PCREL_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_16_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_12_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_11_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_10_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_9_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_8_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_7_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_6_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_32_PCREL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_COPY);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GLOB_DAT);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_JMP_SLOT);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_RELATIVE);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_PLT_B22_PCREL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOTREL_LO16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOTREL_HI16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOTREL_32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOT_LO16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOT_HI16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOT_32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOT_16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_DTPMOD_32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_DTPREL_LO16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_DTPREL_HI16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_DTPREL_32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_DTPREL_16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GD_PLT_B22_PCREL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GD_GOT_LO16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GD_GOT_HI16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GD_GOT_32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GD_GOT_16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_LO16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_HI16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_GOT_LO16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_GOT_HI16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_GOT_32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_GOT_16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_TPREL_LO16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_TPREL_HI16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_TPREL_32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_TPREL_16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_6_PCREL_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOTREL_32_6_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOTREL_16_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOTREL_11_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOT_32_6_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOT_16_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GOT_11_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_DTPREL_32_6_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_DTPREL_16_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_DTPREL_11_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GD_GOT_32_6_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GD_GOT_16_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_GD_GOT_11_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_32_6_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_16_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_GOT_32_6_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_GOT_16_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_IE_GOT_11_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_TPREL_32_6_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_TPREL_16_X);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_HEX_TPREL_11_X);
	default: break;
	}
	break;
	case ELF::EM_PPC:
	switch (Type) {
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_NONE);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_ADDR32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_ADDR24);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_ADDR16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_ADDR16_LO);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_ADDR16_HI);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_ADDR16_HA);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_ADDR14);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_ADDR14_BRTAKEN);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_ADDR14_BRNTAKEN);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_REL24);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_REL14);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_REL14_BRTAKEN);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_REL14_BRNTAKEN);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_REL32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_TPREL16_LO);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_TPREL16_HA);
	default: break;
	}
	break;
	case ELF::EM_PPC64:
	switch (Type) {
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_NONE);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_ADDR32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_ADDR16_LO);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_ADDR16_HI);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_ADDR14);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_REL24);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_REL32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_ADDR64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_ADDR16_HIGHER);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_ADDR16_HIGHEST);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_REL64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_TOC16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_TOC16_LO);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_TOC16_HA);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_TOC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_ADDR16_DS);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_ADDR16_LO_DS);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_TOC16_DS);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_TOC16_LO_DS);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_TLS);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_TPREL16_LO);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_TPREL16_HA);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_DTPREL16_LO);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_DTPREL16_HA);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_GOT_TLSGD16_LO);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_GOT_TLSGD16_HA);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_GOT_TLSLD16_LO);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_GOT_TLSLD16_HA);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_GOT_TPREL16_LO_DS);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_GOT_TPREL16_HA);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_TLSGD);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_TLSLD);
	default: break;
	}
	break;
	case ELF::EM_S390:
	switch (Type) {
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_NONE);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_8);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_PC32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_GOT12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_GOT32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_PLT32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_COPY);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_GLOB_DAT);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_JMP_SLOT);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_RELATIVE);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_GOTOFF);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_GOTPC);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_GOT16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_PC16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_PC16DBL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_PLT16DBL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_PC32DBL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_PLT32DBL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_GOTPCDBL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_PC64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_GOT64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_PLT64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_GOTENT);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_GOTOFF16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_GOTOFF64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_GOTPLT12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_GOTPLT16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_GOTPLT32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_GOTPLT64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_GOTPLTENT);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_PLTOFF16);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_PLTOFF32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_PLTOFF64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_TLS_LOAD);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_TLS_GDCALL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_TLS_LDCALL);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_TLS_GD32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_TLS_GD64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_TLS_GOTIE12);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_TLS_GOTIE32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_TLS_GOTIE64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_TLS_LDM32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_TLS_LDM64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_TLS_IE32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_TLS_IE64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_TLS_IEENT);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_TLS_LE32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_TLS_LE64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_TLS_LDO32);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_TLS_LDO64);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_TLS_DTPMOD);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_TLS_DTPOFF);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_TLS_TPOFF);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_20);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_GOT20);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_GOTPLT20);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_TLS_GOTIE20);
	LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_390_IRELATIVE);
	default: break;
	}
	break;
	default: break;
	}
	return Res;
	}
	#undef LLVM_ELF_SWITCH_RELOC_TYPE_NAME
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getRelocationTypeName(
	DataRefImpl Rel, SmallVectorImpl<char> &Result) const {
	const Elf_Shdr *sec = getSection(Rel.w.b);
	uint32_t type;
	switch (sec->sh_type) {
	default :
	return object_error::parse_failed;
	case ELF::SHT_REL : {
	type = getRel(Rel)->getType(isMips64EL());
	break;
	}
	case ELF::SHT_RELA : {
	type = getRela(Rel)->getType(isMips64EL());
	break;
	}
	}
	if (!isMips64EL()) {		if (!isMips64EL()) {
	StringRef Name = getRelocationTypeName(type);		StringRef Name = getRelocationTypeName(Type);
	Result.append(Name.begin(), Name.end());		Result.append(Name.begin(), Name.end());
	} else {		} else {
	uint8_t Type1 = (type >> 0) & 0xFF;		uint8_t Type1 = (Type >> 0) & 0xFF;
	uint8_t Type2 = (type >> 8) & 0xFF;		uint8_t Type2 = (Type >> 8) & 0xFF;
	uint8_t Type3 = (type >> 16) & 0xFF;		uint8_t Type3 = (Type >> 16) & 0xFF;
	// Concat all three relocation type names.		// Concat all three relocation type names.
	StringRef Name = getRelocationTypeName(Type1);		StringRef Name = getRelocationTypeName(Type1);
	Result.append(Name.begin(), Name.end());		Result.append(Name.begin(), Name.end());
	Name = getRelocationTypeName(Type2);		Name = getRelocationTypeName(Type2);
	Result.append(1, '/');		Result.append(1, '/');
	Result.append(Name.begin(), Name.end());		Result.append(Name.begin(), Name.end());
	Name = getRelocationTypeName(Type3);		Name = getRelocationTypeName(Type3);
	Result.append(1, '/');		Result.append(1, '/');
	Result.append(Name.begin(), Name.end());		Result.append(Name.begin(), Name.end());
	}		}
	return object_error::success;
	}		}
	template<class ELFT>		template <class ELFT>
	error_code ELFObjectFile<ELFT>::getRelocationAdditionalInfo(		template <class RelT>
	DataRefImpl Rel, int64_t &Result) const {		std::pair<const typename ELFFile<ELFT>::Elf_Shdr *,
	const Elf_Shdr *sec = getSection(Rel.w.b);		const typename ELFFile<ELFT>::Elf_Sym *>
	switch (sec->sh_type) {		ELFFile<ELFT>::getRelocationSymbol(const Elf_Shdr *Sec, const RelT *Rel) co
	default :		nst {
	report_fatal_error("Invalid section type in Rel!");		if (!Sec->sh_link)
	case ELF::SHT_REL : {		return std::make_pair((const Elf_Shdr *)0, (const Elf_Sym *)0);
	Result = 0;		const Elf_Shdr *SymTable = getSection(Sec->sh_link);
	return object_error::success;		return std::make_pair(
	}		SymTable, getEntry<Elf_Sym>(SymTable, Rel->getSymbol(isMips64EL())));
	case ELF::SHT_RELA : {
	Result = getRela(Rel)->r_addend;
	return object_error::success;
	}
	}
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getRelocationValueString(
	DataRefImpl Rel, SmallVectorImpl<char> &Result) const {
	const Elf_Shdr *sec = getSection(Rel.w.b);
	uint8_t type;
	StringRef res;
	int64_t addend = 0;
	uint16_t symbol_index = 0;
	switch (sec->sh_type) {
	default:
	return object_error::parse_failed;
	case ELF::SHT_REL: {
	type = getRel(Rel)->getType(isMips64EL());
	symbol_index = getRel(Rel)->getSymbol(isMips64EL());
	// TODO: Read implicit addend from section data.
	break;
	}
	case ELF::SHT_RELA: {
	type = getRela(Rel)->getType(isMips64EL());
	symbol_index = getRela(Rel)->getSymbol(isMips64EL());
	addend = getRela(Rel)->r_addend;
	break;
	}
	}
	const Elf_Sym *symb = getEntry<Elf_Sym>(sec->sh_link, symbol_index);
	StringRef symname;
	if (error_code ec = getSymbolName(getSection(sec->sh_link), symb, symname
	))
	return ec;
	switch (Header->e_machine) {
	case ELF::EM_X86_64:
	switch (type) {
	case ELF::R_X86_64_PC8:
	case ELF::R_X86_64_PC16:
	case ELF::R_X86_64_PC32: {
	std::string fmtbuf;
	raw_string_ostream fmt(fmtbuf);
	fmt << symname << (addend < 0 ? "" : "+") << addend << "-P";
	fmt.flush();
	Result.append(fmtbuf.begin(), fmtbuf.end());
	}
	break;
	case ELF::R_X86_64_8:
	case ELF::R_X86_64_16:
	case ELF::R_X86_64_32:
	case ELF::R_X86_64_32S:
	case ELF::R_X86_64_64: {
	std::string fmtbuf;
	raw_string_ostream fmt(fmtbuf);
	fmt << symname << (addend < 0 ? "" : "+") << addend;
	fmt.flush();
	Result.append(fmtbuf.begin(), fmtbuf.end());
	}
	break;
	default:
	res = "Unknown";
	}
	break;
	case ELF::EM_AARCH64:
	case ELF::EM_ARM:
	case ELF::EM_HEXAGON:
	res = symname;
	break;
	default:
	res = "Unknown";
	}
	if (Result.empty())
	Result.append(res.begin(), res.end());
	return object_error::success;
	}		}
	// Verify that the last byte in the string table in a null.		// Verify that the last byte in the string table in a null.
	template<class ELFT>		template <class ELFT>
	void ELFObjectFile<ELFT>::VerifyStrTab(const Elf_Shdr *sh) const {		void ELFFile<ELFT>::VerifyStrTab(const Elf_Shdr *sh) const {
	const char *strtab = (const char*)base() + sh->sh_offset;		const char *strtab = (const char *)base() + sh->sh_offset;
	if (strtab[sh->sh_size - 1] != 0)		if (strtab[sh->sh_size - 1] != 0)
	// FIXME: Proper error handling.		// FIXME: Proper error handling.
	report_fatal_error("String table must end with a null terminator!");		report_fatal_error("String table must end with a null terminator!");
	}		}
	template<class ELFT>		template <class ELFT>
	ELFObjectFile<ELFT>::ELFObjectFile(MemoryBuffer *Object, error_code &ec)		uint64_t ELFFile<ELFT>::getNumSections() const {
	: ObjectFile(getELFType(		assert(Header && "Header not initialized!");
	static_cast<endianness>(ELFT::TargetEndianness) == support::little,		if (Header->e_shnum == ELF::SHN_UNDEF) {
	ELFT::Is64Bits),		assert(SectionHeaderTable && "SectionHeaderTable not initialized!");
	Object)		return SectionHeaderTable->sh_size;
	, isDyldELFObject(false)		}
	, SectionHeaderTable(0)		return Header->e_shnum;
	, dot_shstrtab_sec(0)		}
	, dot_strtab_sec(0)
	, dot_dynstr_sec(0)
	, dot_dynamic_sec(0)
	, dot_gnu_version_sec(0)
	, dot_gnu_version_r_sec(0)
	, dot_gnu_version_d_sec(0)
	, dt_soname(0)
	{
	const uint64_t FileSize = Data->getBufferSize();		template <class ELFT>
			typename ELFFile<ELFT>::uintX_t ELFFile<ELFT>::getStringTableIndex() const
			{
			if (Header->e_shnum == ELF::SHN_UNDEF) {
			if (Header->e_shstrndx == ELF::SHN_HIRESERVE)
			return SectionHeaderTable->sh_link;
			if (Header->e_shstrndx >= getNumSections())
			return 0;
			}
			return Header->e_shstrndx;
			}
			template <class ELFT>
			ELFFile<ELFT>::ELFFile(MemoryBuffer *Object, error_code &ec)
			: Buf(Object),
			SectionHeaderTable(0),
			dot_shstrtab_sec(0),
			dot_strtab_sec(0),
			dot_symtab_sec(0),
			SymbolTableSectionHeaderIndex(0),
			dot_gnu_version_sec(0),
			dot_gnu_version_r_sec(0),
			dot_gnu_version_d_sec(0),
			dt_soname(0) {
			const uint64_t FileSize = Buf->getBufferSize();
	if (sizeof(Elf_Ehdr) > FileSize)		if (sizeof(Elf_Ehdr) > FileSize)
	// FIXME: Proper error handling.		// FIXME: Proper error handling.
	report_fatal_error("File too short!");		report_fatal_error("File too short!");
	Header = reinterpret_cast<const Elf_Ehdr *>(base());		Header = reinterpret_cast<const Elf_Ehdr *>(base());
	if (Header->e_shoff == 0)		if (Header->e_shoff == 0)
	return;		return;
	skipping to change at line 2362		skipping to change at line 642
	// The getNumSections() call below depends on SectionHeaderTable being se t.		// The getNumSections() call below depends on SectionHeaderTable being se t.
	SectionHeaderTable =		SectionHeaderTable =
	reinterpret_cast<const Elf_Shdr *>(base() + SectionTableOffset);		reinterpret_cast<const Elf_Shdr *>(base() + SectionTableOffset);
	const uint64_t SectionTableSize = getNumSections() * Header->e_shentsize;		const uint64_t SectionTableSize = getNumSections() * Header->e_shentsize;
	if (SectionTableOffset + SectionTableSize > FileSize)		if (SectionTableOffset + SectionTableSize > FileSize)
	// FIXME: Proper error handling.		// FIXME: Proper error handling.
	report_fatal_error("Section table goes past end of file!");		report_fatal_error("Section table goes past end of file!");
	// To find the symbol tables we walk the section table to find SHT_SYMTAB		// Scan sections for special sections.
	.
	const Elf_Shdr* SymbolTableSectionHeaderIndex = 0;		for (Elf_Shdr_Iter SecI = begin_sections(), SecE = end_sections();
	const Elf_Shdr* sh = SectionHeaderTable;		SecI != SecE; ++SecI) {
			switch (SecI->sh_type) {
	// Reserve SymbolTableSections[0] for .dynsym		case ELF::SHT_SYMTAB_SHNDX:
	SymbolTableSections.push_back(NULL);
	for (uint64_t i = 0, e = getNumSections(); i != e; ++i) {
	switch (sh->sh_type) {
	case ELF::SHT_SYMTAB_SHNDX: {
	if (SymbolTableSectionHeaderIndex)		if (SymbolTableSectionHeaderIndex)
	// FIXME: Proper error handling.		// FIXME: Proper error handling.
	report_fatal_error("More than one .symtab_shndx!");		report_fatal_error("More than one .symtab_shndx!");
	SymbolTableSectionHeaderIndex = sh;		SymbolTableSectionHeaderIndex = &*SecI;
	break;		break;
	}		case ELF::SHT_SYMTAB:
	case ELF::SHT_SYMTAB: {		if (dot_symtab_sec)
	SymbolTableSectionsIndexMap[i] = SymbolTableSections.size();		// FIXME: Proper error handling.
	SymbolTableSections.push_back(sh);		report_fatal_error("More than one .symtab!");
			dot_symtab_sec = &*SecI;
			dot_strtab_sec = getSection(SecI->sh_link);
	break;		break;
	}
	case ELF::SHT_DYNSYM: {		case ELF::SHT_DYNSYM: {
	if (SymbolTableSections[0] != NULL)		if (DynSymRegion.Addr)
	// FIXME: Proper error handling.		// FIXME: Proper error handling.
	report_fatal_error("More than one .dynsym!");		report_fatal_error("More than one .dynsym!");
	SymbolTableSectionsIndexMap[i] = 0;		DynSymRegion.Addr = base() + SecI->sh_offset;
	SymbolTableSections[0] = sh;		DynSymRegion.Size = SecI->sh_size;
	break;		DynSymRegion.EntSize = SecI->sh_entsize;
	}		const Elf_Shdr *DynStr = getSection(SecI->sh_link);
	case ELF::SHT_REL:		DynStrRegion.Addr = base() + DynStr->sh_offset;
	case ELF::SHT_RELA: {		DynStrRegion.Size = DynStr->sh_size;
	SectionRelocMap[getSection(sh->sh_info)].push_back(i);		DynStrRegion.EntSize = DynStr->sh_entsize;
	break;		break;
	}		}
	case ELF::SHT_DYNAMIC: {		case ELF::SHT_DYNAMIC:
	if (dot_dynamic_sec != NULL)		if (DynamicRegion.Addr)
	// FIXME: Proper error handling.		// FIXME: Proper error handling.
	report_fatal_error("More than one .dynamic!");		report_fatal_error("More than one .dynamic!");
	dot_dynamic_sec = sh;		DynamicRegion.Addr = base() + SecI->sh_offset;
			DynamicRegion.Size = SecI->sh_size;
			DynamicRegion.EntSize = SecI->sh_entsize;
	break;		break;
	}		case ELF::SHT_GNU_versym:
	case ELF::SHT_GNU_versym: {
	if (dot_gnu_version_sec != NULL)		if (dot_gnu_version_sec != NULL)
	// FIXME: Proper error handling.		// FIXME: Proper error handling.
	report_fatal_error("More than one .gnu.version section!");		report_fatal_error("More than one .gnu.version section!");
	dot_gnu_version_sec = sh;		dot_gnu_version_sec = &*SecI;
	break;		break;
	}		case ELF::SHT_GNU_verdef:
	case ELF::SHT_GNU_verdef: {
	if (dot_gnu_version_d_sec != NULL)		if (dot_gnu_version_d_sec != NULL)
	// FIXME: Proper error handling.		// FIXME: Proper error handling.
	report_fatal_error("More than one .gnu.version_d section!");		report_fatal_error("More than one .gnu.version_d section!");
	dot_gnu_version_d_sec = sh;		dot_gnu_version_d_sec = &*SecI;
	break;		break;
	}		case ELF::SHT_GNU_verneed:
	case ELF::SHT_GNU_verneed: {
	if (dot_gnu_version_r_sec != NULL)		if (dot_gnu_version_r_sec != NULL)
	// FIXME: Proper error handling.		// FIXME: Proper error handling.
	report_fatal_error("More than one .gnu.version_r section!");		report_fatal_error("More than one .gnu.version_r section!");
	dot_gnu_version_r_sec = sh;		dot_gnu_version_r_sec = &*SecI;
	break;		break;
	}		}
	}
	++sh;
	}
	// Sort section relocation lists by index.
	for (typename RelocMap_t::iterator i = SectionRelocMap.begin(),
	e = SectionRelocMap.end(); i != e; ++i
	) {
	std::sort(i->second.begin(), i->second.end());
	}		}
	// Get string table sections.		// Get string table sections.
	dot_shstrtab_sec = getSection(getStringTableIndex());		dot_shstrtab_sec = getSection(getStringTableIndex());
	if (dot_shstrtab_sec) {		if (dot_shstrtab_sec) {
	// Verify that the last byte in the string table in a null.		// Verify that the last byte in the string table in a null.
	VerifyStrTab(dot_shstrtab_sec);		VerifyStrTab(dot_shstrtab_sec);
	}		}
	// Merge this into the above loop.
	for (const char *i = reinterpret_cast<const char *>(SectionHeaderTable),
	*e = i + getNumSections() * Header->e_shentsize;
	i != e; i += Header->e_shentsize) {
	const Elf_Shdr *sh = reinterpret_cast<const Elf_Shdr*>(i);
	if (sh->sh_type == ELF::SHT_STRTAB) {
	StringRef SectionName(getString(dot_shstrtab_sec, sh->sh_name));
	if (SectionName == ".strtab") {
	if (dot_strtab_sec != 0)
	// FIXME: Proper error handling.
	report_fatal_error("Already found section named .strtab!");
	dot_strtab_sec = sh;
	VerifyStrTab(dot_strtab_sec);
	} else if (SectionName == ".dynstr") {
	if (dot_dynstr_sec != 0)
	// FIXME: Proper error handling.
	report_fatal_error("Already found section named .dynstr!");
	dot_dynstr_sec = sh;
	VerifyStrTab(dot_dynstr_sec);
	}
	}
	}
	// Build symbol name side-mapping if there is one.		// Build symbol name side-mapping if there is one.
	if (SymbolTableSectionHeaderIndex) {		if (SymbolTableSectionHeaderIndex) {
	const Elf_Word *ShndxTable = reinterpret_cast<const Elf_Word*>(base() +		const Elf_Word *ShndxTable = reinterpret_cast<const Elf_Word*>(base() +
	SymbolTableSectionHeaderIndex->sh_off set);		SymbolTableSectionHeaderIndex->sh_off set);
	error_code ec;		for (Elf_Sym_Iter SI = begin_symbols(), SE = end_symbols(); SI != SE;
	for (symbol_iterator si = begin_symbols(),		++SI) {
	se = end_symbols(); si != se; si.increment(ec)) {
	if (ec)
	report_fatal_error("Fewer extended symbol table entries than symbol
	s!");
	if (*ShndxTable != ELF::SHN_UNDEF)		if (*ShndxTable != ELF::SHN_UNDEF)
	ExtendedSymbolTable[getSymbol(si->getRawDataRefImpl())] = *ShndxTab le;		ExtendedSymbolTable[&*SI] = *ShndxTable;
	++ShndxTable;		++ShndxTable;
	}		}
	}		}
			// Scan program headers.
			for (Elf_Phdr_Iter PhdrI = begin_program_headers(),
			PhdrE = end_program_headers();
			PhdrI != PhdrE; ++PhdrI) {
			if (PhdrI->p_type == ELF::PT_DYNAMIC) {
			DynamicRegion.Addr = base() + PhdrI->p_offset;
			DynamicRegion.Size = PhdrI->p_filesz;
			DynamicRegion.EntSize = sizeof(Elf_Dyn);
			break;
			}
			}
			ec = error_code::success();
	}		}
	// Get the symbol table index in the symtab section given a symbol		// Get the symbol table index in the symtab section given a symbol
	template<class ELFT>		template <class ELFT>
	uint64_t ELFObjectFile<ELFT>::getSymbolIndex(const Elf_Sym *Sym) const {		uint64_t ELFFile<ELFT>::getSymbolIndex(const Elf_Sym *Sym) const {
	assert(SymbolTableSections.size() == 1 && "Only one symbol table supporte
	d!");
	const Elf_Shdr *SymTab = *SymbolTableSections.begin();
	uintptr_t SymLoc = uintptr_t(Sym);		uintptr_t SymLoc = uintptr_t(Sym);
	uintptr_t SymTabLoc = uintptr_t(base() + SymTab->sh_offset);		uintptr_t SymTabLoc = uintptr_t(base() + dot_symtab_sec->sh_offset);
	assert(SymLoc > SymTabLoc && "Symbol not in symbol table!");		assert(SymLoc > SymTabLoc && "Symbol not in symbol table!");
	uint64_t SymOffset = SymLoc - SymTabLoc;		uint64_t SymOffset = SymLoc - SymTabLoc;
	assert(SymOffset % SymTab->sh_entsize == 0 &&		assert(SymOffset % dot_symtab_sec->sh_entsize == 0 &&
	"Symbol not multiple of symbol size!");		"Symbol not multiple of symbol size!");
	return SymOffset / SymTab->sh_entsize;		return SymOffset / dot_symtab_sec->sh_entsize;
	}
	template<class ELFT>
	symbol_iterator ELFObjectFile<ELFT>::begin_symbols() const {
	DataRefImpl SymbolData;
	if (SymbolTableSections.size() <= 1) {
	SymbolData.d.a = std::numeric_limits<uint32_t>::max();
	SymbolData.d.b = std::numeric_limits<uint32_t>::max();
	} else {
	SymbolData.d.a = 1; // The 0th symbol in ELF is fake.
	SymbolData.d.b = 1; // The 0th table is .dynsym
	}
	return symbol_iterator(SymbolRef(SymbolData, this));
	}		}
	template<class ELFT>		template <class ELFT>
	symbol_iterator ELFObjectFile<ELFT>::end_symbols() const {		typename ELFFile<ELFT>::Elf_Shdr_Iter ELFFile<ELFT>::begin_sections() const
	DataRefImpl SymbolData;		{
	SymbolData.d.a = std::numeric_limits<uint32_t>::max();		return Elf_Shdr_Iter(Header->e_shentsize,
	SymbolData.d.b = std::numeric_limits<uint32_t>::max();		(const char *)base() + Header->e_shoff);
	return symbol_iterator(SymbolRef(SymbolData, this));
	}
	template<class ELFT>
	symbol_iterator ELFObjectFile<ELFT>::begin_dynamic_symbols() const {
	DataRefImpl SymbolData;
	if (SymbolTableSections[0] == NULL) {
	SymbolData.d.a = std::numeric_limits<uint32_t>::max();
	SymbolData.d.b = std::numeric_limits<uint32_t>::max();
	} else {
	SymbolData.d.a = 1; // The 0th symbol in ELF is fake.
	SymbolData.d.b = 0; // The 0th table is .dynsym
	}
	return symbol_iterator(SymbolRef(SymbolData, this));
	}		}
	template<class ELFT>		template <class ELFT>
	symbol_iterator ELFObjectFile<ELFT>::end_dynamic_symbols() const {		typename ELFFile<ELFT>::Elf_Shdr_Iter ELFFile<ELFT>::end_sections() const {
	DataRefImpl SymbolData;		return Elf_Shdr_Iter(Header->e_shentsize,
	SymbolData.d.a = std::numeric_limits<uint32_t>::max();		(const char *)base() + Header->e_shoff +
	SymbolData.d.b = std::numeric_limits<uint32_t>::max();		(getNumSections() * Header->e_shentsize));
	return symbol_iterator(SymbolRef(SymbolData, this));
	}		}
	template<class ELFT>		template <class ELFT>
	section_iterator ELFObjectFile<ELFT>::begin_sections() const {		typename ELFFile<ELFT>::Elf_Sym_Iter ELFFile<ELFT>::begin_symbols() const {
	DataRefImpl ret;		if (!dot_symtab_sec)
	ret.p = reinterpret_cast<intptr_t>(base() + Header->e_shoff);		return Elf_Sym_Iter(0, 0, false);
	return section_iterator(SectionRef(ret, this));		return Elf_Sym_Iter(dot_symtab_sec->sh_entsize,
			(const char *)base() + dot_symtab_sec->sh_offset, fal
			se);
	}		}
	template<class ELFT>		template <class ELFT>
	section_iterator ELFObjectFile<ELFT>::end_sections() const {		typename ELFFile<ELFT>::Elf_Sym_Iter ELFFile<ELFT>::end_symbols() const {
	DataRefImpl ret;		if (!dot_symtab_sec)
	ret.p = reinterpret_cast<intptr_t>(base()		return Elf_Sym_Iter(0, 0, false);
	+ Header->e_shoff		return Elf_Sym_Iter(dot_symtab_sec->sh_entsize,
	+ (Header->e_shentsize*getNumSections(		(const char *)base() + dot_symtab_sec->sh_offset +
	)));		dot_symtab_sec->sh_size,
	return section_iterator(SectionRef(ret, this));		false);
	}		}
	template<class ELFT>		template <class ELFT>
	typename ELFObjectFile<ELFT>::Elf_Dyn_iterator		typename ELFFile<ELFT>::Elf_Dyn_Iter
	ELFObjectFile<ELFT>::begin_dynamic_table() const {		ELFFile<ELFT>::begin_dynamic_table() const {
	if (dot_dynamic_sec)		if (DynamicRegion.Addr)
	return Elf_Dyn_iterator(dot_dynamic_sec->sh_entsize,		return Elf_Dyn_Iter(DynamicRegion.EntSize,
	(const char *)base() + dot_dynamic_sec->sh_offs		(const char *)DynamicRegion.Addr);
	et);		return Elf_Dyn_Iter(0, 0);
	return Elf_Dyn_iterator(0, 0);
	}		}
	template<class ELFT>		template <class ELFT>
	typename ELFObjectFile<ELFT>::Elf_Dyn_iterator		typename ELFFile<ELFT>::Elf_Dyn_Iter
	ELFObjectFile<ELFT>::end_dynamic_table(bool NULLEnd) const {		ELFFile<ELFT>::end_dynamic_table(bool NULLEnd) const {
	if (dot_dynamic_sec) {		if (!DynamicRegion.Addr)
	Elf_Dyn_iterator Ret(dot_dynamic_sec->sh_entsize,		return Elf_Dyn_Iter(0, 0);
	(const char *)base() + dot_dynamic_sec->sh_offset		Elf_Dyn_Iter Ret(DynamicRegion.EntSize,
	+		(const char *)DynamicRegion.Addr + DynamicRegion.Size);
	dot_dynamic_sec->sh_size);
	if (NULLEnd) {		if (NULLEnd) {
	Elf_Dyn_iterator Start = begin_dynamic_table();		Elf_Dyn_Iter Start = begin_dynamic_table();
	while (Start != Ret && Start->getTag() != ELF::DT_NULL)		while (Start != Ret && Start->getTag() != ELF::DT_NULL)
	++Start;		++Start;
	// Include the DT_NULL.		// Include the DT_NULL.
	if (Start != Ret)		if (Start != Ret)
	++Start;		++Start;
	Ret = Start;		Ret = Start;
	}
	return Ret;
	}		}
	return Elf_Dyn_iterator(0, 0);		return Ret;
	}		}
	template<class ELFT>		template <class ELFT>
	StringRef ELFObjectFile<ELFT>::getLoadName() const {		StringRef ELFFile<ELFT>::getLoadName() const {
	if (!dt_soname) {		if (!dt_soname) {
	// Find the DT_SONAME entry		// Find the DT_SONAME entry
	Elf_Dyn_iterator it = begin_dynamic_table();		Elf_Dyn_Iter it = begin_dynamic_table();
	Elf_Dyn_iterator ie = end_dynamic_table();		Elf_Dyn_Iter ie = end_dynamic_table();
	while (it != ie && it->getTag() != ELF::DT_SONAME)		while (it != ie && it->getTag() != ELF::DT_SONAME)
	++it;		++it;
	if (it != ie) {		if (it != ie) {
	if (dot_dynstr_sec == NULL)		dt_soname = getDynamicString(it->getVal());
	report_fatal_error("Dynamic string table is missing");
	dt_soname = getString(dot_dynstr_sec, it->getVal());
	} else {		} else {
	dt_soname = "";		dt_soname = "";
	}		}
	}		}
	return dt_soname;		return dt_soname;
	}		}
	template<class ELFT>		template <class ELFT>
	library_iterator ELFObjectFile<ELFT>::begin_libraries_needed() const {		template <typename T>
	// Find the first DT_NEEDED entry		const T *ELFFile<ELFT>::getEntry(uint32_t Section, uint32_t Entry) const {
	Elf_Dyn_iterator i = begin_dynamic_table();
	Elf_Dyn_iterator e = end_dynamic_table();
	while (i != e && i->getTag() != ELF::DT_NEEDED)
	++i;
	DataRefImpl DRI;
	DRI.p = reinterpret_cast<uintptr_t>(i.get());
	return library_iterator(LibraryRef(DRI, this));
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getLibraryNext(DataRefImpl Data,
	LibraryRef &Result) const {
	// Use the same DataRefImpl format as DynRef.
	Elf_Dyn_iterator i = Elf_Dyn_iterator(dot_dynamic_sec->sh_entsize,
	reinterpret_cast<const char *>(Data
	.p));
	Elf_Dyn_iterator e = end_dynamic_table();
	// Skip the current dynamic table entry and find the next DT_NEEDED entry
	.
	do
	++i;
	while (i != e && i->getTag() != ELF::DT_NEEDED);
	DataRefImpl DRI;
	DRI.p = reinterpret_cast<uintptr_t>(i.get());
	Result = LibraryRef(DRI, this);
	return object_error::success;
	}
	template<class ELFT>
	error_code ELFObjectFile<ELFT>::getLibraryPath(DataRefImpl Data,
	StringRef &Res) const {
	Elf_Dyn_iterator i = Elf_Dyn_iterator(dot_dynamic_sec->sh_entsize,
	reinterpret_cast<const char *>(Data
	.p));
	if (i == end_dynamic_table())
	report_fatal_error("getLibraryPath() called on iterator end");
	if (i->getTag() != ELF::DT_NEEDED)
	report_fatal_error("Invalid library_iterator");
	// This uses .dynstr to lookup the name of the DT_NEEDED entry.
	// THis works as long as DT_STRTAB == .dynstr. This is true most of
	// the time, but the specification allows exceptions.
	// TODO: This should really use DT_STRTAB instead. Doing this requires
	// reading the program headers.
	if (dot_dynstr_sec == NULL)
	report_fatal_error("Dynamic string table is missing");
	Res = getString(dot_dynstr_sec, i->getVal());
	return object_error::success;
	}
	template<class ELFT>
	library_iterator ELFObjectFile<ELFT>::end_libraries_needed() const {
	Elf_Dyn_iterator e = end_dynamic_table();
	DataRefImpl DRI;
	DRI.p = reinterpret_cast<uintptr_t>(e.get());
	return library_iterator(LibraryRef(DRI, this));
	}
	template<class ELFT>
	uint8_t ELFObjectFile<ELFT>::getBytesInAddress() const {
	return ELFT::Is64Bits ? 8 : 4;
	}
	template<class ELFT>
	StringRef ELFObjectFile<ELFT>::getFileFormatName() const {
	switch(Header->e_ident[ELF::EI_CLASS]) {
	case ELF::ELFCLASS32:
	switch(Header->e_machine) {
	case ELF::EM_386:
	return "ELF32-i386";
	case ELF::EM_X86_64:
	return "ELF32-x86-64";
	case ELF::EM_ARM:
	return "ELF32-arm";
	case ELF::EM_HEXAGON:
	return "ELF32-hexagon";
	case ELF::EM_MIPS:
	return "ELF32-mips";
	default:
	return "ELF32-unknown";
	}
	case ELF::ELFCLASS64:
	switch(Header->e_machine) {
	case ELF::EM_386:
	return "ELF64-i386";
	case ELF::EM_X86_64:
	return "ELF64-x86-64";
	case ELF::EM_AARCH64:
	return "ELF64-aarch64";
	case ELF::EM_PPC64:
	return "ELF64-ppc64";
	case ELF::EM_S390:
	return "ELF64-s390";
	default:
	return "ELF64-unknown";
	}
	default:
	// FIXME: Proper error handling.
	report_fatal_error("Invalid ELFCLASS!");
	}
	}
	template<class ELFT>
	unsigned ELFObjectFile<ELFT>::getArch() const {
	switch(Header->e_machine) {
	case ELF::EM_386:
	return Triple::x86;
	case ELF::EM_X86_64:
	return Triple::x86_64;
	case ELF::EM_AARCH64:
	return Triple::aarch64;
	case ELF::EM_ARM:
	return Triple::arm;
	case ELF::EM_HEXAGON:
	return Triple::hexagon;
	case ELF::EM_MIPS:
	return (ELFT::TargetEndianness == support::little) ?
	Triple::mipsel : Triple::mips;
	case ELF::EM_PPC64:
	return Triple::ppc64;
	case ELF::EM_S390:
	return Triple::systemz;
	default:
	return Triple::UnknownArch;
	}
	}
	template<class ELFT>
	uint64_t ELFObjectFile<ELFT>::getNumSections() const {
	assert(Header && "Header not initialized!");
	if (Header->e_shnum == ELF::SHN_UNDEF) {
	assert(SectionHeaderTable && "SectionHeaderTable not initialized!");
	return SectionHeaderTable->sh_size;
	}
	return Header->e_shnum;
	}
	template<class ELFT>
	uint64_t
	ELFObjectFile<ELFT>::getStringTableIndex() const {
	if (Header->e_shnum == ELF::SHN_UNDEF) {
	if (Header->e_shstrndx == ELF::SHN_HIRESERVE)
	return SectionHeaderTable->sh_link;
	if (Header->e_shstrndx >= getNumSections())
	return 0;
	}
	return Header->e_shstrndx;
	}
	template<class ELFT>
	template<typename T>
	inline const T *
	ELFObjectFile<ELFT>::getEntry(uint16_t Section, uint32_t Entry) const {
	return getEntry<T>(getSection(Section), Entry);		return getEntry<T>(getSection(Section), Entry);
	}		}
	template<class ELFT>		template <class ELFT>
	template<typename T>		template <typename T>
	inline const T *		const T *ELFFile<ELFT>::getEntry(const Elf_Shdr *Section,
	ELFObjectFile<ELFT>::getEntry(const Elf_Shdr * Section, uint32_t Entry) con		uint32_t Entry) const {
	st {		return reinterpret_cast<const T *>(base() + Section->sh_offset +
	return reinterpret_cast<const T *>(		(Entry * Section->sh_entsize));
	base()
	+ Section->sh_offset
	+ (Entry * Section->sh_entsize));
	}
	template<class ELFT>
	const typename ELFObjectFile<ELFT>::Elf_Sym *
	ELFObjectFile<ELFT>::getSymbol(DataRefImpl Symb) const {
	return getEntry<Elf_Sym>(SymbolTableSections[Symb.d.b], Symb.d.a);
	}
	template<class ELFT>
	const typename ELFObjectFile<ELFT>::Elf_Rel *
	ELFObjectFile<ELFT>::getRel(DataRefImpl Rel) const {
	return getEntry<Elf_Rel>(Rel.w.b, Rel.w.c);
	}
	template<class ELFT>
	const typename ELFObjectFile<ELFT>::Elf_Rela *
	ELFObjectFile<ELFT>::getRela(DataRefImpl Rela) const {
	return getEntry<Elf_Rela>(Rela.w.b, Rela.w.c);
	}
	template<class ELFT>
	const typename ELFObjectFile<ELFT>::Elf_Shdr *
	ELFObjectFile<ELFT>::getSection(DataRefImpl Symb) const {
	const Elf_Shdr *sec = getSection(Symb.d.b);
	if (sec->sh_type != ELF::SHT_SYMTAB || sec->sh_type != ELF::SHT_DYNSYM)
	// FIXME: Proper error handling.
	report_fatal_error("Invalid symbol table section!");
	return sec;
	}		}
	template<class ELFT>		template <class ELFT>
	const typename ELFObjectFile<ELFT>::Elf_Shdr *		const typename ELFFile<ELFT>::Elf_Shdr *
	ELFObjectFile<ELFT>::getSection(uint32_t index) const {		ELFFile<ELFT>::getSection(uint32_t index) const {
	if (index == 0)		if (index == 0)
	return 0;		return 0;
	if (!SectionHeaderTable || index >= getNumSections())		if (!SectionHeaderTable || index >= getNumSections())
	// FIXME: Proper error handling.		// FIXME: Proper error handling.
	report_fatal_error("Invalid section index!");		report_fatal_error("Invalid section index!");
	return reinterpret_cast<const Elf_Shdr *>(		return reinterpret_cast<const Elf_Shdr *>(
	reinterpret_cast<const char *>(SectionHeaderTable)		reinterpret_cast<const char *>(SectionHeaderTable)
	+ (index * Header->e_shentsize));		+ (index * Header->e_shentsize));
	}		}
	template<class ELFT>		template <class ELFT>
	const char *ELFObjectFile<ELFT>::getString(uint32_t section,		const char *ELFFile<ELFT>::getString(uint32_t section,
	ELF::Elf32_Word offset) const {		ELF::Elf32_Word offset) const {
	return getString(getSection(section), offset);		return getString(getSection(section), offset);
	}		}
	template<class ELFT>		template <class ELFT>
	const char *ELFObjectFile<ELFT>::getString(const Elf_Shdr *section,		const char *ELFFile<ELFT>::getString(const Elf_Shdr *section,
	ELF::Elf32_Word offset) const {		ELF::Elf32_Word offset) const {
	assert(section && section->sh_type == ELF::SHT_STRTAB && "Invalid section !");		assert(section && section->sh_type == ELF::SHT_STRTAB && "Invalid section !");
	if (offset >= section->sh_size)		if (offset >= section->sh_size)
	// FIXME: Proper error handling.		// FIXME: Proper error handling.
	report_fatal_error("Symbol name offset outside of string table!");		report_fatal_error("Symbol name offset outside of string table!");
	return (const char *)base() + section->sh_offset + offset;		return (const char *)base() + section->sh_offset + offset;
	}		}
	template<class ELFT>		template <class ELFT>
	error_code ELFObjectFile<ELFT>::getSymbolName(const Elf_Shdr *section,		const char *ELFFile<ELFT>::getDynamicString(uintX_t Offset) const {
	const Elf_Sym *symb,		if (!DynStrRegion.Addr || Offset >= DynStrRegion.Size)
	StringRef &Result) const {		return 0;
	if (symb->st_name == 0) {		return (const char *)DynStrRegion.Addr + Offset;
	const Elf_Shdr *section = getSection(symb);		}
	if (!section)
	Result = "";		template <class ELFT>
	else		ErrorOr<StringRef> ELFFile<ELFT>::getSymbolName(Elf_Sym_Iter Sym) const {
	Result = getString(dot_shstrtab_sec, section->sh_name);		if (!Sym.isDynamic())
	return object_error::success;		return getSymbolName(dot_symtab_sec, &*Sym);
	}
			if (!DynStrRegion.Addr || Sym->st_name >= DynStrRegion.Size)
	if (section == SymbolTableSections[0]) {		return object_error::parse_failed;
	// Symbol is in .dynsym, use .dynstr string table		return StringRef(getDynamicString(Sym->st_name));
	Result = getString(dot_dynstr_sec, symb->st_name);		}
	} else {
	// Use the default symbol table name section.		template <class ELFT>
	Result = getString(dot_strtab_sec, symb->st_name);		ErrorOr<StringRef> ELFFile<ELFT>::getSymbolName(const Elf_Shdr *Section,
			const Elf_Sym *Symb) const
			{
			if (Symb->st_name == 0) {
			const Elf_Shdr *ContainingSec = getSection(Symb);
			if (ContainingSec)
			return getSectionName(ContainingSec);
	}		}
	return object_error::success;
			const Elf_Shdr *StrTab = getSection(Section->sh_link);
			if (Symb->st_name >= StrTab->sh_size)
			return object_error::parse_failed;
			return StringRef(getString(StrTab, Symb->st_name));
	}		}
	template<class ELFT>		template <class ELFT>
	error_code ELFObjectFile<ELFT>::getSectionName(const Elf_Shdr *section,		ErrorOr<StringRef>
	StringRef &Result) const {		ELFFile<ELFT>::getSectionName(const Elf_Shdr *Section) const {
	Result = StringRef(getString(dot_shstrtab_sec, section->sh_name));		if (Section->sh_name >= dot_shstrtab_sec->sh_size)
	return object_error::success;		return object_error::parse_failed;
			return StringRef(getString(dot_shstrtab_sec, Section->sh_name));
	}		}
	template<class ELFT>		template <class ELFT>
	error_code ELFObjectFile<ELFT>::getSymbolVersion(const Elf_Shdr *section,		ErrorOr<StringRef> ELFFile<ELFT>::getSymbolVersion(const Elf_Shdr *section,
	const Elf_Sym *symb,		const Elf_Sym *symb,
	StringRef &Version,		bool &IsDefault) const {
	bool &IsDefault) const {
	// Handle non-dynamic symbols.		// Handle non-dynamic symbols.
	if (section != SymbolTableSections[0]) {		if (section != DynSymRegion.Addr && section != 0) {
	// Non-dynamic symbols can have versions in their names		// Non-dynamic symbols can have versions in their names
	// A name of the form 'foo@V1' indicates version 'V1', non-default.		// A name of the form 'foo@V1' indicates version 'V1', non-default.
	// A name of the form 'foo@@V2' indicates version 'V2', default version .		// A name of the form 'foo@@V2' indicates version 'V2', default version .
	StringRef Name;		ErrorOr<StringRef> SymName = getSymbolName(section, symb);
	error_code ec = getSymbolName(section, symb, Name);		if (!SymName)
	if (ec != object_error::success)		return SymName;
	return ec;		StringRef Name = *SymName;
	size_t atpos = Name.find('@');		size_t atpos = Name.find('@');
	if (atpos == StringRef::npos) {		if (atpos == StringRef::npos) {
	Version = "";
	IsDefault = false;		IsDefault = false;
	return object_error::success;		return StringRef("");
	}		}
	++atpos;		++atpos;
	if (atpos < Name.size() && Name[atpos] == '@') {		if (atpos < Name.size() && Name[atpos] == '@') {
	IsDefault = true;		IsDefault = true;
	++atpos;		++atpos;
	} else {		} else {
	IsDefault = false;		IsDefault = false;
	}		}
	Version = Name.substr(atpos);		return Name.substr(atpos);
	return object_error::success;
	}		}
	// This is a dynamic symbol. Look in the GNU symbol version table.		// This is a dynamic symbol. Look in the GNU symbol version table.
	if (dot_gnu_version_sec == NULL) {		if (dot_gnu_version_sec == NULL) {
	// No version table.		// No version table.
	Version = "";
	IsDefault = false;		IsDefault = false;
	return object_error::success;		return StringRef("");
	}		}
	// Determine the position in the symbol table of this entry.		// Determine the position in the symbol table of this entry.
	const char *sec_start = (const char*)base() + section->sh_offset;		size_t entry_index = ((const char *)symb - (const char *)DynSymRegion.Add
	size_t entry_index = ((const char*)symb - sec_start)/section->sh_entsize;		r) /
			DynSymRegion.EntSize;
	// Get the corresponding version index entry		// Get the corresponding version index entry
	const Elf_Versym *vs = getEntry<Elf_Versym>(dot_gnu_version_sec, entry_in dex);		const Elf_Versym *vs = getEntry<Elf_Versym>(dot_gnu_version_sec, entry_in dex);
	size_t version_index = vs->vs_index & ELF::VERSYM_VERSION;		size_t version_index = vs->vs_index & ELF::VERSYM_VERSION;
	// Special markers for unversioned symbols.		// Special markers for unversioned symbols.
	if (version_index == ELF::VER_NDX_LOCAL ||		if (version_index == ELF::VER_NDX_LOCAL ||
	version_index == ELF::VER_NDX_GLOBAL) {		version_index == ELF::VER_NDX_GLOBAL) {
	Version = "";
	IsDefault = false;		IsDefault = false;
	return object_error::success;		return StringRef("");
	}		}
	// Lookup this symbol in the version table		// Lookup this symbol in the version table
	LoadVersionMap();		LoadVersionMap();
	if (version_index >= VersionMap.size() || VersionMap[version_index].isNul l())		if (version_index >= VersionMap.size() || VersionMap[version_index].isNul l())
	report_fatal_error("Symbol has version index without corresponding "		return object_error::parse_failed;
	"define or reference entry");
	const VersionMapEntry &entry = VersionMap[version_index];		const VersionMapEntry &entry = VersionMap[version_index];
	// Get the version name string		// Get the version name string
	size_t name_offset;		size_t name_offset;
	if (entry.isVerdef()) {		if (entry.isVerdef()) {
	// The first Verdaux entry holds the name.		// The first Verdaux entry holds the name.
	name_offset = entry.getVerdef()->getAux()->vda_name;		name_offset = entry.getVerdef()->getAux()->vda_name;
	} else {		} else {
	name_offset = entry.getVernaux()->vna_name;		name_offset = entry.getVernaux()->vna_name;
	}		}
	Version = getString(dot_dynstr_sec, name_offset);
	// Set IsDefault		// Set IsDefault
	if (entry.isVerdef()) {		if (entry.isVerdef()) {
	IsDefault = !(vs->vs_index & ELF::VERSYM_HIDDEN);		IsDefault = !(vs->vs_index & ELF::VERSYM_HIDDEN);
	} else {		} else {
	IsDefault = false;		IsDefault = false;
	}		}
	return object_error::success;		if (name_offset >= DynStrRegion.Size)
	}		return object_error::parse_failed;
			return StringRef(getDynamicString(name_offset));
	/// This is a generic interface for retrieving GNU symbol version
	/// information from an ELFObjectFile.
	static inline error_code GetELFSymbolVersion(const ObjectFile *Obj,
	const SymbolRef &Sym,
	StringRef &Version,
	bool &IsDefault) {
	// Little-endian 32-bit
	if (const ELFObjectFile<ELFType<support::little, 4, false> > *ELFObj =
	dyn_cast<ELFObjectFile<ELFType<support::little, 4, false> > >(Obj
	))
	return ELFObj->getSymbolVersion(Sym, Version, IsDefault);
	// Big-endian 32-bit
	if (const ELFObjectFile<ELFType<support::big, 4, false> > *ELFObj =
	dyn_cast<ELFObjectFile<ELFType<support::big, 4, false> > >(Obj))
	return ELFObj->getSymbolVersion(Sym, Version, IsDefault);
	// Little-endian 64-bit
	if (const ELFObjectFile<ELFType<support::little, 8, true> > *ELFObj =
	dyn_cast<ELFObjectFile<ELFType<support::little, 8, true> > >(Obj)
	)
	return ELFObj->getSymbolVersion(Sym, Version, IsDefault);
	// Big-endian 64-bit
	if (const ELFObjectFile<ELFType<support::big, 8, true> > *ELFObj =
	dyn_cast<ELFObjectFile<ELFType<support::big, 8, true> > >(Obj))
	return ELFObj->getSymbolVersion(Sym, Version, IsDefault);
	llvm_unreachable("Object passed to GetELFSymbolVersion() is not ELF");
	}		}
	/// This function returns the hash value for a symbol in the .dynsym sectio n		/// This function returns the hash value for a symbol in the .dynsym sectio n
	/// Name of the API remains consistent as specified in the libelf		/// Name of the API remains consistent as specified in the libelf
	/// REF : http://www.sco.com/developers/gabi/latest/ch5.dynamic.html#hash		/// REF : http://www.sco.com/developers/gabi/latest/ch5.dynamic.html#hash
	static inline unsigned elf_hash(StringRef &symbolName) {		static inline unsigned elf_hash(StringRef &symbolName) {
	unsigned h = 0, g;		unsigned h = 0, g;
	for (unsigned i = 0, j = symbolName.size(); i < j; i++) {		for (unsigned i = 0, j = symbolName.size(); i < j; i++) {
	h = (h << 4) + symbolName[i];		h = (h << 4) + symbolName[i];
	g = h & 0xf0000000L;		g = h & 0xf0000000L;
	if (g != 0)		if (g != 0)
	h ^= g >> 24;		h ^= g >> 24;
	h &= ~g;		h &= ~g;
	}		}
	return h;		return h;
	}		}
			} // end namespace object
	}		} // end namespace llvm
	}
	#endif		#endif
End of changes. 123 change blocks.
	2557 lines changed or deleted		482 lines changed or added

	Error.h		Error.h
	skipping to change at line 25		skipping to change at line 25
	#define LLVM_OBJECT_ERROR_H		#define LLVM_OBJECT_ERROR_H
	#include "llvm/Support/system_error.h"		#include "llvm/Support/system_error.h"
	namespace llvm {		namespace llvm {
	namespace object {		namespace object {
	const error_category &object_category();		const error_category &object_category();
	struct object_error {		struct object_error {
	enum _ {		enum Impl {
	success = 0,		success = 0,
	invalid_file_type,		arch_not_found,
	parse_failed,		invalid_file_type,
	unexpected_eof		parse_failed,
	};		unexpected_eof
	_ v_;		};
			Impl V;
	object_error(_ v) : v_(v) {}		object_error(Impl V) : V(V) {}
	explicit object_error(int v) : v_(_(v)) {}		operator Impl() const { return V; }
	operator int() const {return v_;}
	};		};
	inline error_code make_error_code(object_error e) {		inline error_code make_error_code(object_error e) {
	return error_code(static_cast<int>(e), object_category());		return error_code(static_cast<int>(e), object_category());
	}		}
	} // end namespace object.		} // end namespace object.
	template <> struct is_error_code_enum<object::object_error> : true_type { } ;		template <> struct is_error_code_enum<object::object_error> : true_type { } ;
	template <> struct is_error_code_enum<object::object_error::_> : true_type		template <> struct is_error_code_enum<object::object_error::Impl> : true_ty
	{ };		pe {
			};
	} // end namespace llvm.		} // end namespace llvm.
	#endif		#endif
End of changes. 3 change blocks.
	12 lines changed or deleted		13 lines changed or added

	ErrorOr.h		ErrorOr.h
	skipping to change at line 30		skipping to change at line 30
	#include "llvm/Support/AlignOf.h"		#include "llvm/Support/AlignOf.h"
	#include "llvm/Support/system_error.h"		#include "llvm/Support/system_error.h"
	#include "llvm/Support/type_traits.h"		#include "llvm/Support/type_traits.h"
	#include <cassert>		#include <cassert>
	#if LLVM_HAS_CXX11_TYPETRAITS		#if LLVM_HAS_CXX11_TYPETRAITS
	#include <type_traits>		#include <type_traits>
	#endif		#endif
	namespace llvm {		namespace llvm {
	struct ErrorHolderBase {
	error_code Error;
	uint16_t RefCount;
	bool HasUserData;
	ErrorHolderBase() : RefCount(1) {}
	void aquire() {
	++RefCount;
	}
	void release() {
	if (--RefCount == 0)
	delete this;
	}
	protected:
	virtual ~ErrorHolderBase() {}
	};
	template<class T>
	struct ErrorHolder : ErrorHolderBase {
	#if LLVM_HAS_RVALUE_REFERENCES
	ErrorHolder(T &&UD) : UserData(llvm_move(UD)) {}
	#else
	ErrorHolder(T &UD) : UserData(UD) {}
	#endif
	T UserData;
	};
	template<class Tp> struct ErrorOrUserDataTraits : llvm::false_type {};
	#if LLVM_HAS_CXX11_TYPETRAITS && LLVM_HAS_RVALUE_REFERENCES		#if LLVM_HAS_CXX11_TYPETRAITS && LLVM_HAS_RVALUE_REFERENCES
	template<class T, class V>		template<class T, class V>
	typename std::enable_if< std::is_constructible<T, V>::value		typename std::enable_if< std::is_constructible<T, V>::value
	, typename std::remove_reference<V>::type>::type &&		, typename std::remove_reference<V>::type>::type &&
	moveIfMoveConstructible(V &Val) {		moveIfMoveConstructible(V &Val) {
	return std::move(Val);		return std::move(Val);
	}		}
	template<class T, class V>		template<class T, class V>
	typename std::enable_if< !std::is_constructible<T, V>::value		typename std::enable_if< !std::is_constructible<T, V>::value
	skipping to change at line 114		skipping to change at line 82
	/// \code		/// \code
	/// ErrorOr<Buffer> getBuffer();		/// ErrorOr<Buffer> getBuffer();
	/// void handleError(error_code ec);		/// void handleError(error_code ec);
	///		///
	/// auto buffer = getBuffer();		/// auto buffer = getBuffer();
	/// if (!buffer)		/// if (!buffer)
	/// handleError(buffer);		/// handleError(buffer);
	/// buffer->write("adena");		/// buffer->write("adena");
	/// \endcode		/// \endcode
	///		///
	/// ErrorOr<T> also supports user defined data for specific error_codes. To
	use
	/// this feature you must first add a template specialization of
	/// ErrorOrUserDataTraits derived from std::true_type for your type in the
	lld
	/// namespace. This specialization must have a static error_code error()
	/// function that returns the error_code this data is used with.
	///
	/// getError<UserData>() may be called to get either the stored user data,
	or
	/// a default constructed UserData if none was stored.
	///
	/// Example:
	/// \code
	/// struct InvalidArgError {
	/// InvalidArgError() {}
	/// InvalidArgError(std::string S) : ArgName(S) {}
	/// std::string ArgName;
	/// };
	///
	/// namespace llvm {
	/// template<>
	/// struct ErrorOrUserDataTraits<InvalidArgError> : std::true_type {
	/// static error_code error() {
	/// return make_error_code(errc::invalid_argument);
	/// }
	/// };
	/// } // end namespace llvm
	///
	/// using namespace llvm;
	///
	/// ErrorOr<int> foo() {
	/// return InvalidArgError("adena");
	/// }
	///
	/// int main() {
	/// auto a = foo();
	/// if (!a && error_code(a) == errc::invalid_argument)
	/// llvm::errs() << a.getError<InvalidArgError>().ArgName << "\n";
	/// }
	/// \endcode
	///		///
	/// An implicit conversion to bool provides a way to check if there was an		/// An implicit conversion to bool provides a way to check if there was an
	/// error. The unary * and -> operators provide pointer like access to the		/// error. The unary * and -> operators provide pointer like access to the
	/// value. Accessing the value when there is an error has undefined behavio r.		/// value. Accessing the value when there is an error has undefined behavio r.
	///		///
	/// When T is a reference type the behaivor is slightly different. The refe rence		/// When T is a reference type the behaivor is slightly different. The refe rence
	/// is held in a std::reference_wrapper<std::remove_reference<T>::type>, an d		/// is held in a std::reference_wrapper<std::remove_reference<T>::type>, an d
	/// there is special handling to make operator -> work as if T was not a		/// there is special handling to make operator -> work as if T was not a
	/// reference.		/// reference.
	///		///
	skipping to change at line 181		skipping to change at line 111
	conditional< isRef		conditional< isRef
	, wrap		, wrap
	, T		, T
	>::type storage_type;		>::type storage_type;
	private:		private:
	typedef typename remove_reference<T>::type &reference;		typedef typename remove_reference<T>::type &reference;
	typedef typename remove_reference<T>::type *pointer;		typedef typename remove_reference<T>::type *pointer;
	public:		public:
	ErrorOr() : IsValid(false) {}
	template <class E>		template <class E>
	ErrorOr(E ErrorCode, typename enable_if_c<is_error_code_enum<E>::value ||		ErrorOr(E ErrorCode, typename enable_if_c<is_error_code_enum<E>::value ||
	is_error_condition_enum<E>::val ue,		is_error_condition_enum<E>::val ue,
	void *>::type = 0)		void *>::type = 0)
	: HasError(true), IsValid(true) {		: HasError(true) {
	Error = new ErrorHolderBase;		new (getError()) error_code(make_error_code(ErrorCode));
	Error->Error = make_error_code(ErrorCode);
	Error->HasUserData = false;
	}
	ErrorOr(llvm::error_code EC) : HasError(true), IsValid(true) {
	Error = new ErrorHolderBase;
	Error->Error = EC;
	Error->HasUserData = false;
	}		}
	template<class UserDataT>		ErrorOr(llvm::error_code EC) : HasError(true) {
	ErrorOr(UserDataT UD, typename		new (getError()) error_code(EC);
	enable_if_c<ErrorOrUserDataTraits<UserDataT>::value>::type* = 0)
	: HasError(true), IsValid(true) {
	Error = new ErrorHolder<UserDataT>(llvm_move(UD));
	Error->Error = ErrorOrUserDataTraits<UserDataT>::error();
	Error->HasUserData = true;
	}		}
	ErrorOr(T Val) : HasError(false), IsValid(true) {		ErrorOr(T Val) : HasError(false) {
	new (get()) storage_type(moveIfMoveConstructible<storage_type>(Val));		new (get()) storage_type(moveIfMoveConstructible<storage_type>(Val));
	}		}
	ErrorOr(const ErrorOr &Other) : IsValid(false) {		ErrorOr(const ErrorOr &Other) {
	copyConstruct(Other);		copyConstruct(Other);
	}		}
	template <class OtherT>		template <class OtherT>
	ErrorOr(const ErrorOr<OtherT> &Other) : IsValid(false) {		ErrorOr(const ErrorOr<OtherT> &Other) {
	copyConstruct(Other);		copyConstruct(Other);
	}		}
	ErrorOr &operator =(const ErrorOr &Other) {		ErrorOr &operator =(const ErrorOr &Other) {
	copyAssign(Other);		copyAssign(Other);
	return *this;		return *this;
	}		}
	template <class OtherT>		template <class OtherT>
	ErrorOr &operator =(const ErrorOr<OtherT> &Other) {		ErrorOr &operator =(const ErrorOr<OtherT> &Other) {
	copyAssign(Other);		copyAssign(Other);
	return *this;		return *this;
	}		}
	#if LLVM_HAS_RVALUE_REFERENCES		#if LLVM_HAS_RVALUE_REFERENCES
	ErrorOr(ErrorOr &&Other) : IsValid(false) {		ErrorOr(ErrorOr &&Other) {
	moveConstruct(std::move(Other));		moveConstruct(std::move(Other));
	}		}
	template <class OtherT>		template <class OtherT>
	ErrorOr(ErrorOr<OtherT> &&Other) : IsValid(false) {		ErrorOr(ErrorOr<OtherT> &&Other) {
	moveConstruct(std::move(Other));		moveConstruct(std::move(Other));
	}		}
	ErrorOr &operator =(ErrorOr &&Other) {		ErrorOr &operator =(ErrorOr &&Other) {
	moveAssign(std::move(Other));		moveAssign(std::move(Other));
	return *this;		return *this;
	}		}
	template <class OtherT>		template <class OtherT>
	ErrorOr &operator =(ErrorOr<OtherT> &&Other) {		ErrorOr &operator =(ErrorOr<OtherT> &&Other) {
	moveAssign(std::move(Other));		moveAssign(std::move(Other));
	return *this;		return *this;
	}		}
	#endif		#endif
	~ErrorOr() {		~ErrorOr() {
	if (!IsValid)		if (!HasError)
	return;
	if (HasError)
	Error->release();
	else
	get()->~storage_type();		get()->~storage_type();
	}		}
	template<class ET>
	ET getError() const {
	assert(IsValid && "Cannot get the error of a default constructed ErrorO
	r!");
	assert(HasError && "Cannot get an error if none exists!");
	assert(ErrorOrUserDataTraits<ET>::error() == Error->Error &&
	"Incorrect user error data type for error!");
	if (!Error->HasUserData)
	return ET();
	return reinterpret_cast<const ErrorHolder<ET>*>(Error)->UserData;
	}
	typedef void (*unspecified_bool_type)();		typedef void (*unspecified_bool_type)();
	static void unspecified_bool_true() {}		static void unspecified_bool_true() {}
	/// \brief Return false if there is an error.		/// \brief Return false if there is an error.
	operator unspecified_bool_type() const {		operator unspecified_bool_type() const {
	assert(IsValid && "Can't do anything on a default constructed ErrorOr!" );
	return HasError ? 0 : unspecified_bool_true;		return HasError ? 0 : unspecified_bool_true;
	}		}
	operator llvm::error_code() const {		operator llvm::error_code() const {
	assert(IsValid && "Can't do anything on a default constructed ErrorOr!"		return HasError ? *getError() : llvm::error_code::success();
	);
	return HasError ? Error->Error : llvm::error_code::success();
	}		}
	pointer operator ->() {		pointer operator ->() {
	return toPointer(get());		return toPointer(get());
	}		}
	reference operator *() {		reference operator *() {
	return *get();		return *get();
	}		}
	private:		private:
	template <class OtherT>		template <class OtherT>
	void copyConstruct(const ErrorOr<OtherT> &Other) {		void copyConstruct(const ErrorOr<OtherT> &Other) {
	// Construct an invalid ErrorOr if other is invalid.
	if (!Other.IsValid)
	return;
	IsValid = true;
	if (!Other.HasError) {		if (!Other.HasError) {
	// Get the other value.		// Get the other value.
	HasError = false;		HasError = false;
	new (get()) storage_type(*Other.get());		new (get()) storage_type(*Other.get());
	} else {		} else {
	// Get other's error.		// Get other's error.
	Error = Other.Error;
	HasError = true;		HasError = true;
	Error->aquire();		new (getError()) error_code(Other);
	}		}
	}		}
	template <class T1>		template <class T1>
	static bool compareThisIfSameType(const T1 &a, const T1 &b) {		static bool compareThisIfSameType(const T1 &a, const T1 &b) {
	return &a == &b;		return &a == &b;
	}		}
	template <class T1, class T2>		template <class T1, class T2>
	static bool compareThisIfSameType(const T1 &a, const T2 &b) {		static bool compareThisIfSameType(const T1 &a, const T2 &b) {
	skipping to change at line 337		skipping to change at line 230
	if (compareThisIfSameType(*this, Other))		if (compareThisIfSameType(*this, Other))
	return;		return;
	this->~ErrorOr();		this->~ErrorOr();
	new (this) ErrorOr(Other);		new (this) ErrorOr(Other);
	}		}
	#if LLVM_HAS_RVALUE_REFERENCES		#if LLVM_HAS_RVALUE_REFERENCES
	template <class OtherT>		template <class OtherT>
	void moveConstruct(ErrorOr<OtherT> &&Other) {		void moveConstruct(ErrorOr<OtherT> &&Other) {
	// Construct an invalid ErrorOr if other is invalid.
	if (!Other.IsValid)
	return;
	IsValid = true;
	if (!Other.HasError) {		if (!Other.HasError) {
	// Get the other value.		// Get the other value.
	HasError = false;		HasError = false;
	new (get()) storage_type(std::move(*Other.get()));		new (get()) storage_type(std::move(*Other.get()));
	// Tell other not to do any destruction.
	Other.IsValid = false;
	} else {		} else {
	// Get other's error.		// Get other's error.
	Error = Other.Error;
	HasError = true;		HasError = true;
	// Tell other not to do any destruction.		new (getError()) error_code(Other);
	Other.IsValid = false;
	}		}
	}		}
	template <class OtherT>		template <class OtherT>
	void moveAssign(ErrorOr<OtherT> &&Other) {		void moveAssign(ErrorOr<OtherT> &&Other) {
	if (compareThisIfSameType(*this, Other))		if (compareThisIfSameType(*this, Other))
	return;		return;
	this->~ErrorOr();		this->~ErrorOr();
	new (this) ErrorOr(std::move(Other));		new (this) ErrorOr(std::move(Other));
	skipping to change at line 375		skipping to change at line 260
	pointer toPointer(pointer Val) {		pointer toPointer(pointer Val) {
	return Val;		return Val;
	}		}
	pointer toPointer(wrap *Val) {		pointer toPointer(wrap *Val) {
	return &Val->get();		return &Val->get();
	}		}
	storage_type *get() {		storage_type *get() {
	assert(IsValid && "Can't do anything on a default constructed ErrorOr!" );
	assert(!HasError && "Cannot get value when an error exists!");		assert(!HasError && "Cannot get value when an error exists!");
	return reinterpret_cast<storage_type*>(TStorage.buffer);		return reinterpret_cast<storage_type*>(TStorage.buffer);
	}		}
	const storage_type *get() const {		const storage_type *get() const {
	assert(IsValid && "Can't do anything on a default constructed ErrorOr!" );
	assert(!HasError && "Cannot get value when an error exists!");		assert(!HasError && "Cannot get value when an error exists!");
	return reinterpret_cast<const storage_type*>(TStorage.buffer);		return reinterpret_cast<const storage_type*>(TStorage.buffer);
	}		}
	union {		error_code *getError() {
	AlignedCharArrayUnion<storage_type> TStorage;		assert(HasError && "Cannot get error when a value exists!");
	ErrorHolderBase *Error;		return reinterpret_cast<error_code*>(ErrorStorage.buffer);
	};
	bool HasError : 1;
	bool IsValid : 1;
	};
	// ErrorOr specialization for void.
	template <>
	class ErrorOr<void> {
	public:
	ErrorOr() : Error(0, 0) {}
	template <class E>
	ErrorOr(E ErrorCode, typename enable_if_c<is_error_code_enum<E>::value ||
	is_error_condition_enum<E>::val
	ue,
	void *> ::type = 0)
	: Error(0, 0) {
	error_code EC = make_error_code(ErrorCode);
	if (EC == errc::success) {
	Error.setInt(1);
	return;
	}
	ErrorHolderBase *EHB = new ErrorHolderBase;
	EHB->Error = EC;
	EHB->HasUserData = false;
	Error.setPointer(EHB);
	}		}
	ErrorOr(llvm::error_code EC) : Error(0, 0) {		const error_code *getError() const {
	if (EC == errc::success) {		return const_cast<ErrorOr<T> *>(this)->getError();
	Error.setInt(1);
	return;
	}
	ErrorHolderBase *E = new ErrorHolderBase;
	E->Error = EC;
	E->HasUserData = false;
	Error.setPointer(E);
	}
	template<class UserDataT>
	ErrorOr(UserDataT UD, typename
	enable_if_c<ErrorOrUserDataTraits<UserDataT>::value>::type* = 0)
	: Error(0, 0) {
	ErrorHolderBase *E = new ErrorHolder<UserDataT>(llvm_move(UD));
	E->Error = ErrorOrUserDataTraits<UserDataT>::error();
	E->HasUserData = true;
	Error.setPointer(E);
	}
	ErrorOr(const ErrorOr &Other) : Error(0, 0) {
	Error = Other.Error;
	if (Other.Error.getPointer()->Error) {
	Error.getPointer()->aquire();
	}
	}
	ErrorOr &operator =(const ErrorOr &Other) {
	if (this == &Other)
	return *this;
	this->~ErrorOr();
	new (this) ErrorOr(Other);
	return *this;
	}		}
	#if LLVM_HAS_RVALUE_REFERENCES		union {
	ErrorOr(ErrorOr &&Other) : Error(0) {		AlignedCharArrayUnion<storage_type> TStorage;
	// Get other's error.		AlignedCharArrayUnion<error_code> ErrorStorage;
	Error = Other.Error;		};
	// Tell other not to do any destruction.		bool HasError : 1;
	Other.Error.setPointer(0);
	}
	ErrorOr &operator =(ErrorOr &&Other) {
	if (this == &Other)
	return *this;
	this->~ErrorOr();
	new (this) ErrorOr(std::move(Other));
	return *this;
	}
	#endif
	~ErrorOr() {
	if (Error.getPointer())
	Error.getPointer()->release();
	}
	template<class ET>
	ET getError() const {
	assert(ErrorOrUserDataTraits<ET>::error() == *this &&
	"Incorrect user error data type for error!");
	if (!Error.getPointer()->HasUserData)
	return ET();
	return reinterpret_cast<const ErrorHolder<ET> *>(
	Error.getPointer())->UserData;
	}
	typedef void (*unspecified_bool_type)();
	static void unspecified_bool_true() {}
	/// \brief Return false if there is an error.
	operator unspecified_bool_type() const {
	return Error.getInt() ? unspecified_bool_true : 0;
	}
	operator llvm::error_code() const {
	return Error.getInt() ? make_error_code(errc::success)
	: Error.getPointer()->Error;
	}
	private:
	// If the bit is 1, the error is success.
	llvm::PointerIntPair<ErrorHolderBase *, 1> Error;
	};		};
	template<class T, class E>		template<class T, class E>
	typename enable_if_c<is_error_code_enum<E>::value ||		typename enable_if_c<is_error_code_enum<E>::value ||
	is_error_condition_enum<E>::value, bool>::type		is_error_condition_enum<E>::value, bool>::type
	operator ==(ErrorOr<T> &Err, E Code) {		operator ==(ErrorOr<T> &Err, E Code) {
	return error_code(Err) == Code;		return error_code(Err) == Code;
	}		}
	} // end namespace llvm		} // end namespace llvm
End of changes. 26 change blocks.
	250 lines changed or deleted		23 lines changed or added

	ExecutionEngine.h		ExecutionEngine.h
	skipping to change at line 43		skipping to change at line 43
	*		*
	* @{		* @{
	*/		*/
	void LLVMLinkInJIT(void);		void LLVMLinkInJIT(void);
	void LLVMLinkInMCJIT(void);		void LLVMLinkInMCJIT(void);
	void LLVMLinkInInterpreter(void);		void LLVMLinkInInterpreter(void);
	typedef struct LLVMOpaqueGenericValue *LLVMGenericValueRef;		typedef struct LLVMOpaqueGenericValue *LLVMGenericValueRef;
	typedef struct LLVMOpaqueExecutionEngine *LLVMExecutionEngineRef;		typedef struct LLVMOpaqueExecutionEngine *LLVMExecutionEngineRef;
			typedef struct LLVMOpaqueMCJITMemoryManager *LLVMMCJITMemoryManagerRef;
	struct LLVMMCJITCompilerOptions {		struct LLVMMCJITCompilerOptions {
	unsigned OptLevel;		unsigned OptLevel;
	LLVMCodeModel CodeModel;		LLVMCodeModel CodeModel;
	LLVMBool NoFramePointerElim;		LLVMBool NoFramePointerElim;
	LLVMBool EnableFastISel;		LLVMBool EnableFastISel;
			LLVMMCJITMemoryManagerRef MCJMM;
	};		};
	/*===-- Operations on generic values -------------------------------------- ===*/		/*===-- Operations on generic values -------------------------------------- ===*/
	LLVMGenericValueRef LLVMCreateGenericValueOfInt(LLVMTypeRef Ty,		LLVMGenericValueRef LLVMCreateGenericValueOfInt(LLVMTypeRef Ty,
	unsigned long long N,		unsigned long long N,
	LLVMBool IsSigned);		LLVMBool IsSigned);
	LLVMGenericValueRef LLVMCreateGenericValueOfPointer(void *P);		LLVMGenericValueRef LLVMCreateGenericValueOfPointer(void *P);
	skipping to change at line 170		skipping to change at line 172
	void *LLVMRecompileAndRelinkFunction(LLVMExecutionEngineRef EE,		void *LLVMRecompileAndRelinkFunction(LLVMExecutionEngineRef EE,
	LLVMValueRef Fn);		LLVMValueRef Fn);
	LLVMTargetDataRef LLVMGetExecutionEngineTargetData(LLVMExecutionEngineRef E E);		LLVMTargetDataRef LLVMGetExecutionEngineTargetData(LLVMExecutionEngineRef E E);
	void LLVMAddGlobalMapping(LLVMExecutionEngineRef EE, LLVMValueRef Global,		void LLVMAddGlobalMapping(LLVMExecutionEngineRef EE, LLVMValueRef Global,
	void* Addr);		void* Addr);
	void *LLVMGetPointerToGlobal(LLVMExecutionEngineRef EE, LLVMValueRef Global );		void *LLVMGetPointerToGlobal(LLVMExecutionEngineRef EE, LLVMValueRef Global );
			/*===-- Operations on memory managers -------------------------------------
			===*/
			typedef uint8_t *(*LLVMMemoryManagerAllocateCodeSectionCallback)(
			void *Opaque, uintptr_t Size, unsigned Alignment, unsigned SectionID,
			const char *SectionName);
			typedef uint8_t *(*LLVMMemoryManagerAllocateDataSectionCallback)(
			void *Opaque, uintptr_t Size, unsigned Alignment, unsigned SectionID,
			const char *SectionName, LLVMBool IsReadOnly);
			typedef LLVMBool (*LLVMMemoryManagerFinalizeMemoryCallback)(
			void *Opaque, char **ErrMsg);
			typedef void (*LLVMMemoryManagerDestroyCallback)(void *Opaque);
			/**
			* Create a simple custom MCJIT memory manager. This memory manager can
			* intercept allocations in a module-oblivious way. This will return NULL
			* if any of the passed functions are NULL.
			*
			* @param Opaque An opaque client object to pass back to the callbacks.
			* @param AllocateCodeSection Allocate a block of memory for executable cod
			e.
			* @param AllocateDataSection Allocate a block of memory for data.
			* @param FinalizeMemory Set page permissions and flush cache. Return 0 on
			* success, 1 on error.
			*/
			LLVMMCJITMemoryManagerRef LLVMCreateSimpleMCJITMemoryManager(
			void *Opaque,
			LLVMMemoryManagerAllocateCodeSectionCallback AllocateCodeSection,
			LLVMMemoryManagerAllocateDataSectionCallback AllocateDataSection,
			LLVMMemoryManagerFinalizeMemoryCallback FinalizeMemory,
			LLVMMemoryManagerDestroyCallback Destroy);
			void LLVMDisposeMCJITMemoryManager(LLVMMCJITMemoryManagerRef MM);
	/**		/**
	* @}		* @}
	*/		*/
	#ifdef __cplusplus		#ifdef __cplusplus
	}		}
	#endif /* defined(__cplusplus) */		#endif /* defined(__cplusplus) */
	#endif		#endif
End of changes. 3 change blocks.
	0 lines changed or deleted		36 lines changed or added

	FastISel.h		FastISel.h
	//===-- FastISel.h - Definition of the FastISel class --------------------- ===//		//===-- FastISel.h - Definition of the FastISel class ---*- C++ -*--------- ===//
	//		//
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		///
	// This file defines the FastISel class.		/// \file
	//		/// This file defines the FastISel class.
			///
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_CODEGEN_FASTISEL_H		#ifndef LLVM_CODEGEN_FASTISEL_H
	#define LLVM_CODEGEN_FASTISEL_H		#define LLVM_CODEGEN_FASTISEL_H
	#include "llvm/ADT/DenseMap.h"		#include "llvm/ADT/DenseMap.h"
	#include "llvm/CodeGen/MachineBasicBlock.h"		#include "llvm/CodeGen/MachineBasicBlock.h"
	#include "llvm/CodeGen/ValueTypes.h"		#include "llvm/CodeGen/ValueTypes.h"
	namespace llvm {		namespace llvm {
	class AllocaInst;		class AllocaInst;
	class Constant;		class Constant;
	class ConstantFP;		class ConstantFP;
	class FunctionLoweringInfo;		class FunctionLoweringInfo;
	class Instruction;		class Instruction;
	class LoadInst;		class LoadInst;
	class MachineBasicBlock;
	class MachineConstantPool;		class MachineConstantPool;
	class MachineFunction;		class MachineFunction;
	class MachineInstr;		class MachineInstr;
	class MachineFrameInfo;		class MachineFrameInfo;
	class MachineRegisterInfo;		class MachineRegisterInfo;
	class DataLayout;		class DataLayout;
	class TargetInstrInfo;		class TargetInstrInfo;
	class TargetLibraryInfo;		class TargetLibraryInfo;
	class TargetLowering;		class TargetLowering;
	class TargetMachine;		class TargetMachine;
	class TargetRegisterClass;		class TargetRegisterClass;
	class TargetRegisterInfo;		class TargetRegisterInfo;
	class User;		class User;
	class Value;		class Value;
	/// FastISel - This is a fast-path instruction selection class that		/// This is a fast-path instruction selection class that generates poor cod
	/// generates poor code and doesn't support illegal types or non-trivial		e and
	/// lowering, but runs quickly.		/// doesn't support illegal types or non-trivial lowering, but runs quickly
			.
	class FastISel {		class FastISel {
	protected:		protected:
	DenseMap<const Value *, unsigned> LocalValueMap;		DenseMap<const Value *, unsigned> LocalValueMap;
	FunctionLoweringInfo &FuncInfo;		FunctionLoweringInfo &FuncInfo;
	MachineRegisterInfo &MRI;		MachineRegisterInfo &MRI;
	MachineFrameInfo &MFI;		MachineFrameInfo &MFI;
	MachineConstantPool &MCP;		MachineConstantPool &MCP;
	DebugLoc DL;		DebugLoc DL;
	const TargetMachine &TM;		const TargetMachine &TM;
	const DataLayout &TD;		const DataLayout &TD;
	const TargetInstrInfo &TII;		const TargetInstrInfo &TII;
	const TargetLowering &TLI;		const TargetLowering &TLI;
	const TargetRegisterInfo &TRI;		const TargetRegisterInfo &TRI;
	const TargetLibraryInfo *LibInfo;		const TargetLibraryInfo *LibInfo;
	/// The position of the last instruction for materializing constants		/// The position of the last instruction for materializing constants for
	/// for use in the current block. It resets to EmitStartPt when it		use
	/// makes sense (for example, it's usually profitable to avoid function		/// in the current block. It resets to EmitStartPt when it makes sense (f
	/// calls between the definition and the use)		or
			/// example, it's usually profitable to avoid function calls between the
			/// definition and the use)
	MachineInstr *LastLocalValue;		MachineInstr *LastLocalValue;
	/// The top most instruction in the current block that is allowed for		/// The top most instruction in the current block that is allowed for emi
	/// emitting local variables. LastLocalValue resets to EmitStartPt when		tting
	/// it makes sense (for example, on function calls)		/// local variables. LastLocalValue resets to EmitStartPt when it makes s
			ense
			/// (for example, on function calls)
	MachineInstr *EmitStartPt;		MachineInstr *EmitStartPt;
	public:		public:
	/// getLastLocalValue - Return the position of the last instruction		/// Return the position of the last instruction emitted for materializing
	/// emitted for materializing constants for use in the current block.		/// constants for use in the current block.
	MachineInstr *getLastLocalValue() { return LastLocalValue; }		MachineInstr *getLastLocalValue() { return LastLocalValue; }
	/// setLastLocalValue - Update the position of the last instruction		/// Update the position of the last instruction emitted for materializing
	/// emitted for materializing constants for use in the current block.		/// constants for use in the current block.
	void setLastLocalValue(MachineInstr *I) {		void setLastLocalValue(MachineInstr *I) {
	EmitStartPt = I;		EmitStartPt = I;
	LastLocalValue = I;		LastLocalValue = I;
	}		}
	/// startNewBlock - Set the current block to which generated machine		/// Set the current block to which generated machine instructions will be
	/// instructions will be appended, and clear the local CSE map.		/// appended, and clear the local CSE map.
	///
	void startNewBlock();		void startNewBlock();
	/// getCurDebugLoc() - Return current debug location information.		/// Return current debug location information.
	DebugLoc getCurDebugLoc() const { return DL; }		DebugLoc getCurDebugLoc() const { return DL; }
	/// LowerArguments - Do "fast" instruction selection for function argumen		/// Do "fast" instruction selection for function arguments and append mac
	ts		hine
	/// and append machine instructions to the current block. Return true if		/// instructions to the current block. Return true if it is successful.
	/// it is successful.
	bool LowerArguments();		bool LowerArguments();
	/// SelectInstruction - Do "fast" instruction selection for the given		/// Do "fast" instruction selection for the given LLVM IR instruction, an
	/// LLVM IR instruction, and append generated machine instructions to		d
	/// the current block. Return true if selection was successful.		/// append generated machine instructions to the current block. Return tr
	///		ue if
			/// selection was successful.
	bool SelectInstruction(const Instruction *I);		bool SelectInstruction(const Instruction *I);
	/// SelectOperator - Do "fast" instruction selection for the given		/// Do "fast" instruction selection for the given LLVM IR operator
	/// LLVM IR operator (Instruction or ConstantExpr), and append		/// (Instruction or ConstantExpr), and append generated machine instructi
	/// generated machine instructions to the current block. Return true		ons
	/// if selection was successful.		/// to the current block. Return true if selection was successful.
	///
	bool SelectOperator(const User *I, unsigned Opcode);		bool SelectOperator(const User *I, unsigned Opcode);
	/// getRegForValue - Create a virtual register and arrange for it to		/// Create a virtual register and arrange for it to be assigned the value
	/// be assigned the value for the given LLVM value.		for
			/// the given LLVM value.
	unsigned getRegForValue(const Value *V);		unsigned getRegForValue(const Value *V);
	/// lookUpRegForValue - Look up the value to see if its value is already		/// Look up the value to see if its value is already cached in a register
	/// cached in a register. It may be defined by instructions across blocks		. It
	or		/// may be defined by instructions across blocks or defined locally.
	/// defined locally.
	unsigned lookUpRegForValue(const Value *V);		unsigned lookUpRegForValue(const Value *V);
	/// getRegForGEPIndex - This is a wrapper around getRegForValue that also		/// This is a wrapper around getRegForValue that also takes care of trunc
	/// takes care of truncating or sign-extending the given getelementptr		ating
	/// index value.		/// or sign-extending the given getelementptr index value.
	std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);		std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);
	/// \brief We're checking to see if we can fold \p LI into \p FoldInst.		/// \brief We're checking to see if we can fold \p LI into \p FoldInst. N
	/// Note that we could have a sequence where multiple LLVM IR instruction		ote
	s		/// that we could have a sequence where multiple LLVM IR instructions are
	/// are folded into the same machineinstr. For example we could have:		/// folded into the same machineinstr. For example we could have:
			///
	/// A: x = load i32 *P		/// A: x = load i32 *P
	/// B: y = icmp A, 42		/// B: y = icmp A, 42
	/// C: br y, ...		/// C: br y, ...
	///		///
	/// In this scenario, \p LI is "A", and \p FoldInst is "C". We know		/// In this scenario, \p LI is "A", and \p FoldInst is "C". We know abou
	/// about "B" (and any other folded instructions) because it is between		t "B"
	/// A and C.		/// (and any other folded instructions) because it is between A and C.
	///		///
	/// If we succeed folding, return true.		/// If we succeed folding, return true.
	///
	bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst);		bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst);
	/// \brief The specified machine instr operand is a vreg, and that		/// \brief The specified machine instr operand is a vreg, and that vreg i
	/// vreg is being provided by the specified load instruction. If possibl		s
	e,		/// being provided by the specified load instruction. If possible, try t
	/// try to fold the load as an operand to the instruction, returning true		o
	if		/// fold the load as an operand to the instruction, returning true if
	/// possible.		/// possible.
			///
	/// This method should be implemented by targets.		/// This method should be implemented by targets.
	virtual bool tryToFoldLoadIntoMI(MachineInstr * /*MI*/, unsigned /*OpNo*/ ,		virtual bool tryToFoldLoadIntoMI(MachineInstr * /*MI*/, unsigned /*OpNo*/ ,
	const LoadInst * /*LI*/) {		const LoadInst * /*LI*/) {
	return false;		return false;
	}		}
	/// recomputeInsertPt - Reset InsertPt to prepare for inserting instructi		/// Reset InsertPt to prepare for inserting instructions into the current
	ons		/// block.
	/// into the current block.
	void recomputeInsertPt();		void recomputeInsertPt();
	/// removeDeadCode - Remove all dead instructions between the I and E.		/// Remove all dead instructions between the I and E.
	void removeDeadCode(MachineBasicBlock::iterator I,		void removeDeadCode(MachineBasicBlock::iterator I,
	MachineBasicBlock::iterator E);		MachineBasicBlock::iterator E);
	struct SavePoint {		struct SavePoint {
	MachineBasicBlock::iterator InsertPt;		MachineBasicBlock::iterator InsertPt;
	DebugLoc DL;		DebugLoc DL;
	};		};
	/// enterLocalValueArea - Prepare InsertPt to begin inserting instruction		/// Prepare InsertPt to begin inserting instructions into the local value
	s		area
	/// into the local value area and return the old insert position.		/// and return the old insert position.
	SavePoint enterLocalValueArea();		SavePoint enterLocalValueArea();
	/// leaveLocalValueArea - Reset InsertPt to the given old insert position .		/// Reset InsertPt to the given old insert position.
	void leaveLocalValueArea(SavePoint Old);		void leaveLocalValueArea(SavePoint Old);
	virtual ~FastISel();		virtual ~FastISel();
	protected:		protected:
	explicit FastISel(FunctionLoweringInfo &funcInfo,		explicit FastISel(FunctionLoweringInfo &funcInfo,
	const TargetLibraryInfo *libInfo);		const TargetLibraryInfo *libInfo);
	/// TargetSelectInstruction - This method is called by target-independent		/// This method is called by target-independent code when the normal Fast
	/// code when the normal FastISel process fails to select an instruction.		ISel
	/// This gives targets a chance to emit code for anything that doesn't		/// process fails to select an instruction. This gives targets a chance
	/// fit into FastISel's framework. It returns true if it was successful.		to
	///		/// emit code for anything that doesn't fit into FastISel's framework. It
			/// returns true if it was successful.
	virtual bool		virtual bool
	TargetSelectInstruction(const Instruction *I) = 0;		TargetSelectInstruction(const Instruction *I) = 0;
	/// FastLowerArguments - This method is called by target-independent code		/// This method is called by target-independent code to do target specifi
	to		c
	/// do target specific argument lowering. It returns true if it was		/// argument lowering. It returns true if it was successful.
	/// successful.
	virtual bool FastLowerArguments();		virtual bool FastLowerArguments();
	/// FastEmit_r - This method is called by target-independent code		/// This method is called by target-independent code to request that an
	/// to request that an instruction with the given type and opcode		/// instruction with the given type and opcode be emitted.
	/// be emitted.
	virtual unsigned FastEmit_(MVT VT,		virtual unsigned FastEmit_(MVT VT,
	MVT RetVT,		MVT RetVT,
	unsigned Opcode);		unsigned Opcode);
	/// FastEmit_r - This method is called by target-independent code		/// This method is called by target-independent code to request that an
	/// to request that an instruction with the given type, opcode, and		/// instruction with the given type, opcode, and register operand be emit
	/// register operand be emitted.		ted.
	///
	virtual unsigned FastEmit_r(MVT VT,		virtual unsigned FastEmit_r(MVT VT,
	MVT RetVT,		MVT RetVT,
	unsigned Opcode,		unsigned Opcode,
	unsigned Op0, bool Op0IsKill);		unsigned Op0, bool Op0IsKill);
	/// FastEmit_rr - This method is called by target-independent code		/// This method is called by target-independent code to request that an
	/// to request that an instruction with the given type, opcode, and		/// instruction with the given type, opcode, and register operands be emi
	/// register operands be emitted.		tted.
	///
	virtual unsigned FastEmit_rr(MVT VT,		virtual unsigned FastEmit_rr(MVT VT,
	MVT RetVT,		MVT RetVT,
	unsigned Opcode,		unsigned Opcode,
	unsigned Op0, bool Op0IsKill,		unsigned Op0, bool Op0IsKill,
	unsigned Op1, bool Op1IsKill);		unsigned Op1, bool Op1IsKill);
	/// FastEmit_ri - This method is called by target-independent code		/// This method is called by target-independent code to request that an
	/// to request that an instruction with the given type, opcode, and		/// instruction with the given type, opcode, and register and immediate
	/// register and immediate operands be emitted.		/// operands be emitted.
	///
	virtual unsigned FastEmit_ri(MVT VT,		virtual unsigned FastEmit_ri(MVT VT,
	MVT RetVT,		MVT RetVT,
	unsigned Opcode,		unsigned Opcode,
	unsigned Op0, bool Op0IsKill,		unsigned Op0, bool Op0IsKill,
	uint64_t Imm);		uint64_t Imm);
	/// FastEmit_rf - This method is called by target-independent code		/// This method is called by target-independent code to request that an
	/// to request that an instruction with the given type, opcode, and		/// instruction with the given type, opcode, and register and floating-po
	/// register and floating-point immediate operands be emitted.		int
	///		/// immediate operands be emitted.
	virtual unsigned FastEmit_rf(MVT VT,		virtual unsigned FastEmit_rf(MVT VT,
	MVT RetVT,		MVT RetVT,
	unsigned Opcode,		unsigned Opcode,
	unsigned Op0, bool Op0IsKill,		unsigned Op0, bool Op0IsKill,
	const ConstantFP *FPImm);		const ConstantFP *FPImm);
	/// FastEmit_rri - This method is called by target-independent code		/// This method is called by target-independent code to request that an
	/// to request that an instruction with the given type, opcode, and		/// instruction with the given type, opcode, and register and immediate
	/// register and immediate operands be emitted.		/// operands be emitted.
	///
	virtual unsigned FastEmit_rri(MVT VT,		virtual unsigned FastEmit_rri(MVT VT,
	MVT RetVT,		MVT RetVT,
	unsigned Opcode,		unsigned Opcode,
	unsigned Op0, bool Op0IsKill,		unsigned Op0, bool Op0IsKill,
	unsigned Op1, bool Op1IsKill,		unsigned Op1, bool Op1IsKill,
	uint64_t Imm);		uint64_t Imm);
	/// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first trie		/// \brief This method is a wrapper of FastEmit_ri.
	s		///
	/// to emit an instruction with an immediate operand using FastEmit_ri.		/// It first tries to emit an instruction with an immediate operand using
	/// If that fails, it materializes the immediate into a register and try		/// FastEmit_ri. If that fails, it materializes the immediate into a reg
	/// FastEmit_rr instead.		ister
			/// and try FastEmit_rr instead.
	unsigned FastEmit_ri_(MVT VT,		unsigned FastEmit_ri_(MVT VT,
	unsigned Opcode,		unsigned Opcode,
	unsigned Op0, bool Op0IsKill,		unsigned Op0, bool Op0IsKill,
	uint64_t Imm, MVT ImmType);		uint64_t Imm, MVT ImmType);
	/// FastEmit_i - This method is called by target-independent code		/// This method is called by target-independent code to request that an
	/// to request that an instruction with the given type, opcode, and		/// instruction with the given type, opcode, and immediate operand be emi
	/// immediate operand be emitted.		tted.
	virtual unsigned FastEmit_i(MVT VT,		virtual unsigned FastEmit_i(MVT VT,
	MVT RetVT,		MVT RetVT,
	unsigned Opcode,		unsigned Opcode,
	uint64_t Imm);		uint64_t Imm);
	/// FastEmit_f - This method is called by target-independent code		/// This method is called by target-independent code to request that an
	/// to request that an instruction with the given type, opcode, and		/// instruction with the given type, opcode, and floating-point immediate
	/// floating-point immediate operand be emitted.		/// operand be emitted.
	virtual unsigned FastEmit_f(MVT VT,		virtual unsigned FastEmit_f(MVT VT,
	MVT RetVT,		MVT RetVT,
	unsigned Opcode,		unsigned Opcode,
	const ConstantFP *FPImm);		const ConstantFP *FPImm);
	/// FastEmitInst_ - Emit a MachineInstr with no operands and a		/// Emit a MachineInstr with no operands and a result register in the giv
	/// result register in the given register class.		en
	///		/// register class.
	unsigned FastEmitInst_(unsigned MachineInstOpcode,		unsigned FastEmitInst_(unsigned MachineInstOpcode,
	const TargetRegisterClass *RC);		const TargetRegisterClass *RC);
	/// FastEmitInst_r - Emit a MachineInstr with one register operand		/// Emit a MachineInstr with one register operand and a result register i
	/// and a result register in the given register class.		n the
	///		/// given register class.
	unsigned FastEmitInst_r(unsigned MachineInstOpcode,		unsigned FastEmitInst_r(unsigned MachineInstOpcode,
	const TargetRegisterClass *RC,		const TargetRegisterClass *RC,
	unsigned Op0, bool Op0IsKill);		unsigned Op0, bool Op0IsKill);
	/// FastEmitInst_rr - Emit a MachineInstr with two register operands		/// Emit a MachineInstr with two register operands and a result register
	/// and a result register in the given register class.		in
	///		/// the given register class.
	unsigned FastEmitInst_rr(unsigned MachineInstOpcode,		unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
	const TargetRegisterClass *RC,		const TargetRegisterClass *RC,
	unsigned Op0, bool Op0IsKill,		unsigned Op0, bool Op0IsKill,
	unsigned Op1, bool Op1IsKill);		unsigned Op1, bool Op1IsKill);
	/// FastEmitInst_rrr - Emit a MachineInstr with three register operands		/// Emit a MachineInstr with three register operands and a result registe
	/// and a result register in the given register class.		r in
	///		/// the given register class.
	unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,		unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
	const TargetRegisterClass *RC,		const TargetRegisterClass *RC,
	unsigned Op0, bool Op0IsKill,		unsigned Op0, bool Op0IsKill,
	unsigned Op1, bool Op1IsKill,		unsigned Op1, bool Op1IsKill,
	unsigned Op2, bool Op2IsKill);		unsigned Op2, bool Op2IsKill);
	/// FastEmitInst_ri - Emit a MachineInstr with a register operand,		/// Emit a MachineInstr with a register operand, an immediate, and a resu
	/// an immediate, and a result register in the given register class.		lt
	///		/// register in the given register class.
	unsigned FastEmitInst_ri(unsigned MachineInstOpcode,		unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
	const TargetRegisterClass *RC,		const TargetRegisterClass *RC,
	unsigned Op0, bool Op0IsKill,		unsigned Op0, bool Op0IsKill,
	uint64_t Imm);		uint64_t Imm);
	/// FastEmitInst_rii - Emit a MachineInstr with one register operand		/// Emit a MachineInstr with one register operand and two immediate opera
	/// and two immediate operands.		nds.
	///
	unsigned FastEmitInst_rii(unsigned MachineInstOpcode,		unsigned FastEmitInst_rii(unsigned MachineInstOpcode,
	const TargetRegisterClass *RC,		const TargetRegisterClass *RC,
	unsigned Op0, bool Op0IsKill,		unsigned Op0, bool Op0IsKill,
	uint64_t Imm1, uint64_t Imm2);		uint64_t Imm1, uint64_t Imm2);
	/// FastEmitInst_rf - Emit a MachineInstr with two register operands		/// Emit a MachineInstr with two register operands and a result register
	/// and a result register in the given register class.		in
	///		/// the given register class.
	unsigned FastEmitInst_rf(unsigned MachineInstOpcode,		unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
	const TargetRegisterClass *RC,		const TargetRegisterClass *RC,
	unsigned Op0, bool Op0IsKill,		unsigned Op0, bool Op0IsKill,
	const ConstantFP *FPImm);		const ConstantFP *FPImm);
	/// FastEmitInst_rri - Emit a MachineInstr with two register operands,		/// Emit a MachineInstr with two register operands, an immediate, and a r
	/// an immediate, and a result register in the given register class.		esult
	///		/// register in the given register class.
	unsigned FastEmitInst_rri(unsigned MachineInstOpcode,		unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
	const TargetRegisterClass *RC,		const TargetRegisterClass *RC,
	unsigned Op0, bool Op0IsKill,		unsigned Op0, bool Op0IsKill,
	unsigned Op1, bool Op1IsKill,		unsigned Op1, bool Op1IsKill,
	uint64_t Imm);		uint64_t Imm);
	/// FastEmitInst_rrii - Emit a MachineInstr with two register operands,		/// Emit a MachineInstr with two register operands, two immediates operan
	/// two immediates operands, and a result register in the given register		ds,
	/// class.		/// and a result register in the given register class.
	unsigned FastEmitInst_rrii(unsigned MachineInstOpcode,		unsigned FastEmitInst_rrii(unsigned MachineInstOpcode,
	const TargetRegisterClass *RC,		const TargetRegisterClass *RC,
	unsigned Op0, bool Op0IsKill,		unsigned Op0, bool Op0IsKill,
	unsigned Op1, bool Op1IsKill,		unsigned Op1, bool Op1IsKill,
	uint64_t Imm1, uint64_t Imm2);		uint64_t Imm1, uint64_t Imm2);
	/// FastEmitInst_i - Emit a MachineInstr with a single immediate		/// Emit a MachineInstr with a single immediate operand, and a result reg
	/// operand, and a result register in the given register class.		ister
			/// in the given register class.
	unsigned FastEmitInst_i(unsigned MachineInstrOpcode,		unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
	const TargetRegisterClass *RC,		const TargetRegisterClass *RC,
	uint64_t Imm);		uint64_t Imm);
	/// FastEmitInst_ii - Emit a MachineInstr with a two immediate operands.		/// Emit a MachineInstr with a two immediate operands.
	unsigned FastEmitInst_ii(unsigned MachineInstrOpcode,		unsigned FastEmitInst_ii(unsigned MachineInstrOpcode,
	const TargetRegisterClass *RC,		const TargetRegisterClass *RC,
	uint64_t Imm1, uint64_t Imm2);		uint64_t Imm1, uint64_t Imm2);
	/// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subre		/// Emit a MachineInstr for an extract_subreg from a specified index of a
	g		/// superregister to a specified type.
	/// from a specified index of a superregister to a specified type.
	unsigned FastEmitInst_extractsubreg(MVT RetVT,		unsigned FastEmitInst_extractsubreg(MVT RetVT,
	unsigned Op0, bool Op0IsKill,		unsigned Op0, bool Op0IsKill,
	uint32_t Idx);		uint32_t Idx);
	/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op		/// Emit MachineInstrs to compute the value of Op with all but the least
	/// with all but the least significant bit set to zero.		/// significant bit set to zero.
	unsigned FastEmitZExtFromI1(MVT VT,		unsigned FastEmitZExtFromI1(MVT VT,
	unsigned Op0, bool Op0IsKill);		unsigned Op0, bool Op0IsKill);
	/// FastEmitBranch - Emit an unconditional branch to the given block,		/// Emit an unconditional branch to the given block, unless it is the
	/// unless it is the immediate (fall-through) successor, and update		/// immediate (fall-through) successor, and update the CFG.
	/// the CFG.
	void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);		void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);
	void UpdateValueMap(const Value* I, unsigned Reg, unsigned NumRegs = 1);		void UpdateValueMap(const Value* I, unsigned Reg, unsigned NumRegs = 1);
	unsigned createResultReg(const TargetRegisterClass *RC);		unsigned createResultReg(const TargetRegisterClass *RC);
	/// TargetMaterializeConstant - Emit a constant in a register using		/// Emit a constant in a register using target-specific logic, such as
	/// target-specific logic, such as constant pool loads.		/// constant pool loads.
	virtual unsigned TargetMaterializeConstant(const Constant* C) {		virtual unsigned TargetMaterializeConstant(const Constant* C) {
	return 0;		return 0;
	}		}
	/// TargetMaterializeAlloca - Emit an alloca address in a register using		/// Emit an alloca address in a register using target-specific logic.
	/// target-specific logic.
	virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) {		virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) {
	return 0;		return 0;
	}		}
	virtual unsigned TargetMaterializeFloatZero(const ConstantFP* CF) {		virtual unsigned TargetMaterializeFloatZero(const ConstantFP* CF) {
	return 0;		return 0;
	}		}
			/// \brief Check if \c Add is an add that can be safely folded into \c GE
			P.
			///
			/// \c Add can be folded into \c GEP if:
			/// - \c Add is an add,
			/// - \c Add's size matches \c GEP's,
			/// - \c Add is in the same basic block as \c GEP, and
			/// - \c Add has a constant operand.
			bool canFoldAddIntoGEP(const User *GEP, const Value *Add);
	private:		private:
	bool SelectBinaryOp(const User *I, unsigned ISDOpcode);		bool SelectBinaryOp(const User *I, unsigned ISDOpcode);
	bool SelectFNeg(const User *I);		bool SelectFNeg(const User *I);
	bool SelectGetElementPtr(const User *I);		bool SelectGetElementPtr(const User *I);
	bool SelectCall(const User *I);		bool SelectCall(const User *I);
	bool SelectBitCast(const User *I);		bool SelectBitCast(const User *I);
	bool SelectCast(const User *I, unsigned Opcode);		bool SelectCast(const User *I, unsigned Opcode);
	bool SelectExtractValue(const User *I);		bool SelectExtractValue(const User *I);
	bool SelectInsertValue(const User *I);		bool SelectInsertValue(const User *I);
	/// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor block		/// \brief Handle PHI nodes in successor blocks.
	s.		///
	/// Emit code to ensure constants are copied into registers when needed.		/// Emit code to ensure constants are copied into registers when needed.
	/// Remember the virtual registers that need to be added to the Machine P HI		/// Remember the virtual registers that need to be added to the Machine P HI
	/// nodes as input. We cannot just directly add them, because expansion		/// nodes as input. We cannot just directly add them, because expansion
	/// might result in multiple MBB's for one BB. As such, the start of the		might
	/// BB might correspond to a different MBB than the end.		/// result in multiple MBB's for one BB. As such, the start of the BB mi
			ght
			/// correspond to a different MBB than the end.
	bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);		bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
	/// materializeRegForValue - Helper for getRegForVale. This function is		/// Helper for getRegForVale. This function is called when the value isn'
	/// called when the value isn't already available in a register and must		t
	/// be materialized with new instructions.		/// already available in a register and must be materialized with new
			/// instructions.
	unsigned materializeRegForValue(const Value *V, MVT VT);		unsigned materializeRegForValue(const Value *V, MVT VT);
	/// flushLocalValueMap - clears LocalValueMap and moves the area for the		/// Clears LocalValueMap and moves the area for the new local variables t
	/// new local variables to the beginning of the block. It helps to avoid		o the
	/// spilling cached variables across heavy instructions like calls.		/// beginning of the block. It helps to avoid spilling cached variables a
			cross
			/// heavy instructions like calls.
	void flushLocalValueMap();		void flushLocalValueMap();
	/// hasTrivialKill - Test whether the given value has exactly one use.		/// Test whether the given value has exactly one use.
	bool hasTrivialKill(const Value *V) const;		bool hasTrivialKill(const Value *V) const;
	};		};
	}		}
	#endif		#endif
End of changes. 58 change blocks.
	163 lines changed or deleted		174 lines changed or added

	FileSystem.h		FileSystem.h
	skipping to change at line 36		skipping to change at line 36
	#ifndef LLVM_SUPPORT_FILESYSTEM_H		#ifndef LLVM_SUPPORT_FILESYSTEM_H
	#define LLVM_SUPPORT_FILESYSTEM_H		#define LLVM_SUPPORT_FILESYSTEM_H
	#include "llvm/ADT/IntrusiveRefCntPtr.h"		#include "llvm/ADT/IntrusiveRefCntPtr.h"
	#include "llvm/ADT/OwningPtr.h"		#include "llvm/ADT/OwningPtr.h"
	#include "llvm/ADT/SmallString.h"		#include "llvm/ADT/SmallString.h"
	#include "llvm/ADT/Twine.h"		#include "llvm/ADT/Twine.h"
	#include "llvm/Support/DataTypes.h"		#include "llvm/Support/DataTypes.h"
	#include "llvm/Support/ErrorHandling.h"		#include "llvm/Support/ErrorHandling.h"
			#include "llvm/Support/TimeValue.h"
	#include "llvm/Support/system_error.h"		#include "llvm/Support/system_error.h"
	#include <ctime>		#include <ctime>
	#include <iterator>		#include <iterator>
	#include <stack>		#include <stack>
	#include <string>		#include <string>
	#include <vector>		#include <vector>
	#ifdef HAVE_SYS_STAT_H		#ifdef HAVE_SYS_STAT_H
	#include <sys/stat.h>		#include <sys/stat.h>
	#endif		#endif
	skipping to change at line 75		skipping to change at line 76
	};		};
	file_type(_ v) : v_(v) {}		file_type(_ v) : v_(v) {}
	explicit file_type(int v) : v_(_(v)) {}		explicit file_type(int v) : v_(_(v)) {}
	operator int() const {return v_;}		operator int() const {return v_;}
	private:		private:
	int v_;		int v_;
	};		};
	/// copy_option - An "enum class" enumeration of copy semantics for copy
	/// operations.
	struct copy_option {
	enum _ {
	fail_if_exists,
	overwrite_if_exists
	};
	copy_option(_ v) : v_(v) {}
	explicit copy_option(int v) : v_(_(v)) {}
	operator int() const {return v_;}
	private:
	int v_;
	};
	/// space_info - Self explanatory.		/// space_info - Self explanatory.
	struct space_info {		struct space_info {
	uint64_t capacity;		uint64_t capacity;
	uint64_t free;		uint64_t free;
	uint64_t available;		uint64_t available;
	};		};
	enum perms {		enum perms {
	no_perms = 0,		no_perms = 0,
	owner_read = 0400,		owner_read = 0400,
	owner_write = 0200,		owner_write = 0200,
	owner_exe = 0100,		owner_exe = 0100,
	owner_all = owner_read | owner_write | owner_exe,		owner_all = owner_read | owner_write | owner_exe,
	group_read = 040,		group_read = 040,
	group_write = 020,		group_write = 020,
	group_exe = 010,		group_exe = 010,
	group_all = group_read | group_write | group_exe,		group_all = group_read | group_write | group_exe,
	others_read = 04,		others_read = 04,
	others_write = 02,		others_write = 02,
	others_exe = 01,		others_exe = 01,
	others_all = others_read | others_write | others_exe,		others_all = others_read | others_write | others_exe,
	all_all = owner_all | group_all | others_all,		all_read = owner_read | group_read | others_read,
	set_uid_on_exe = 04000,		all_write = owner_write | group_write | others_write,
	set_gid_on_exe = 02000,		all_exe = owner_exe | group_exe | others_exe,
	sticky_bit = 01000,		all_all = owner_all | group_all | others_all,
	perms_mask = all_all | set_uid_on_exe | set_gid_on_exe | sticky_bit,		set_uid_on_exe = 04000,
	perms_not_known = 0xFFFF,		set_gid_on_exe = 02000,
	add_perms = 0x1000,		sticky_bit = 01000,
	remove_perms = 0x2000,		perms_not_known = 0xFFFF
	symlink_perms = 0x4000
	};		};
	// Helper functions so that you can use & and | to manipulate perms bits:		// Helper functions so that you can use & and | to manipulate perms bits:
	inline perms operator|(perms l , perms r) {		inline perms operator|(perms l , perms r) {
	return static_cast<perms>(		return static_cast<perms>(
	static_cast<unsigned short>(l) | static_cast<unsigned short>(r ));		static_cast<unsigned short>(l) | static_cast<unsigned short>(r ));
	}		}
	inline perms operator&(perms l , perms r) {		inline perms operator&(perms l , perms r) {
	return static_cast<perms>(		return static_cast<perms>(
	static_cast<unsigned short>(l) & static_cast<unsigned short>(r ));		static_cast<unsigned short>(l) & static_cast<unsigned short>(r ));
	skipping to change at line 144		skipping to change at line 128
	return l;		return l;
	}		}
	inline perms &operator&=(perms &l, perms r) {		inline perms &operator&=(perms &l, perms r) {
	l = l & r;		l = l & r;
	return l;		return l;
	}		}
	inline perms operator~(perms x) {		inline perms operator~(perms x) {
	return static_cast<perms>(~static_cast<unsigned short>(x));		return static_cast<perms>(~static_cast<unsigned short>(x));
	}		}
			class UniqueID {
			uint64_t Device;
			uint64_t File;
			public:
			UniqueID() {}
			UniqueID(uint64_t Device, uint64_t File) : Device(Device), File(File) {}
			bool operator==(const UniqueID &Other) const {
			return Device == Other.Device && File == Other.File;
			}
			bool operator!=(const UniqueID &Other) const { return !(*this == Other);
			}
			bool operator<(const UniqueID &Other) const {
			return Device < Other.Device ||
			(Device == Other.Device && File < Other.File);
			}
			uint64_t getDevice() const { return Device; }
			uint64_t getFile() const { return File; }
			};
	/// file_status - Represents the result of a call to stat and friends. It h as		/// file_status - Represents the result of a call to stat and friends. It h as
	/// a platform specific member to store the result.		/// a platform specific member to store the result.
	class file_status		class file_status
	{		{
	#if defined(LLVM_ON_UNIX)		#if defined(LLVM_ON_UNIX)
	dev_t fs_st_dev;		dev_t fs_st_dev;
	ino_t fs_st_ino;		ino_t fs_st_ino;
			time_t fs_st_mtime;
			uid_t fs_st_uid;
			gid_t fs_st_gid;
			off_t fs_st_size;
	#elif defined (LLVM_ON_WIN32)		#elif defined (LLVM_ON_WIN32)
	uint32_t LastWriteTimeHigh;		uint32_t LastWriteTimeHigh;
	uint32_t LastWriteTimeLow;		uint32_t LastWriteTimeLow;
	uint32_t VolumeSerialNumber;		uint32_t VolumeSerialNumber;
	uint32_t FileSizeHigh;		uint32_t FileSizeHigh;
	uint32_t FileSizeLow;		uint32_t FileSizeLow;
	uint32_t FileIndexHigh;		uint32_t FileIndexHigh;
	uint32_t FileIndexLow;		uint32_t FileIndexLow;
	#endif		#endif
	friend bool equivalent(file_status A, file_status B);		friend bool equivalent(file_status A, file_status B);
	friend error_code status(const Twine &path, file_status &result);
	file_type Type;		file_type Type;
	perms Perms;		perms Perms;
	public:		public:
	explicit file_status(file_type v=file_type::status_error,		file_status() : Type(file_type::status_error) {}
	perms prms=perms_not_known)		file_status(file_type Type) : Type(Type) {}
	: Type(v), Perms(prms) {}
			#if defined(LLVM_ON_UNIX)
			file_status(file_type Type, perms Perms, dev_t Dev, ino_t Ino, time_t M
			Time,
			uid_t UID, gid_t GID, off_t Size)
			: fs_st_dev(Dev), fs_st_ino(Ino), fs_st_mtime(MTime), fs_st_uid(UID
			),
			fs_st_gid(GID), fs_st_size(Size), Type(Type), Perms(Perms) {}
			#elif defined(LLVM_ON_WIN32)
			file_status(file_type Type, uint32_t LastWriteTimeHigh,
			uint32_t LastWriteTimeLow, uint32_t VolumeSerialNumber,
			uint32_t FileSizeHigh, uint32_t FileSizeLow,
			uint32_t FileIndexHigh, uint32_t FileIndexLow)
			: LastWriteTimeHigh(LastWriteTimeHigh),
			LastWriteTimeLow(LastWriteTimeLow),
			VolumeSerialNumber(VolumeSerialNumber), FileSizeHigh(FileSizeHigh
			),
			FileSizeLow(FileSizeLow), FileIndexHigh(FileIndexHigh),
			FileIndexLow(FileIndexLow), Type(Type), Perms(perms_not_known) {}
			#endif
	// getters		// getters
	file_type type() const { return Type; }		file_type type() const { return Type; }
	perms permissions() const { return Perms; }		perms permissions() const { return Perms; }
			TimeValue getLastModificationTime() const;
			UniqueID getUniqueID() const;
			#if defined(LLVM_ON_UNIX)
			uint32_t getUser() const { return fs_st_uid; }
			uint32_t getGroup() const { return fs_st_gid; }
			uint64_t getSize() const { return fs_st_size; }
			#elif defined (LLVM_ON_WIN32)
			uint32_t getUser() const {
			return 9999; // Not applicable to Windows, so...
			}
			uint32_t getGroup() const {
			return 9999; // Not applicable to Windows, so...
			}
			uint64_t getSize() const {
			return (uint64_t(FileSizeHigh) << 32) + FileSizeLow;
			}
			#endif
	// setters		// setters
	void type(file_type v) { Type = v; }		void type(file_type v) { Type = v; }
	void permissions(perms p) { Perms = p; }		void permissions(perms p) { Perms = p; }
	};		};
	/// file_magic - An "enum class" enumeration of file types based on magic ( the first		/// file_magic - An "enum class" enumeration of file types based on magic ( the first
	/// N bytes of the file).		/// N bytes of the file).
	struct file_magic {		struct file_magic {
	enum _ {		enum Impl {
	unknown = 0, ///< Unrecognized file		unknown = 0, ///< Unrecognized file
	bitcode, ///< Bitcode file		bitcode, ///< Bitcode file
	archive, ///< ar style archive file		archive, ///< ar style archive file
	elf_relocatable, ///< ELF Relocatable object file		elf_relocatable, ///< ELF Relocatable object file
	elf_executable, ///< ELF Executable image		elf_executable, ///< ELF Executable image
	elf_shared_object, ///< ELF dynamically linked shared lib		elf_shared_object, ///< ELF dynamically linked shared lib
	elf_core, ///< ELF core image		elf_core, ///< ELF core image
	macho_object, ///< Mach-O Object file		macho_object, ///< Mach-O Object file
	macho_executable, ///< Mach-O Executable		macho_executable, ///< Mach-O Executable
	macho_fixed_virtual_memory_shared_lib, ///< Mach-O Shared Lib, FVM		macho_fixed_virtual_memory_shared_lib, ///< Mach-O Shared Lib, FVM
	macho_core, ///< Mach-O Core File		macho_core, ///< Mach-O Core File
	macho_preload_executabl, ///< Mach-O Preloaded Executable		macho_preload_executable, ///< Mach-O Preloaded Executable
	macho_dynamically_linked_shared_lib, ///< Mach-O dynlinked shared lib		macho_dynamically_linked_shared_lib, ///< Mach-O dynlinked shared lib
	macho_dynamic_linker, ///< The Mach-O dynamic linker		macho_dynamic_linker, ///< The Mach-O dynamic linker
	macho_bundle, ///< Mach-O Bundle file		macho_bundle, ///< Mach-O Bundle file
	macho_dynamically_linked_shared_lib_stub, ///< Mach-O Shared lib stub		macho_dynamically_linked_shared_lib_stub, ///< Mach-O Shared lib stub
	macho_dsym_companion, ///< Mach-O dSYM companion file		macho_dsym_companion, ///< Mach-O dSYM companion file
			macho_universal_binary, ///< Mach-O universal binary
	coff_object, ///< COFF object file		coff_object, ///< COFF object file
	pecoff_executable ///< PECOFF executable file		coff_import_library, ///< COFF import library
			pecoff_executable, ///< PECOFF executable file
			windows_resource ///< Windows compiled resource file (.rc)
	};		};
	bool is_object() const {		bool is_object() const {
	return v_ == unknown ? false : true;		return V == unknown ? false : true;
	}		}
	file_magic() : v_(unknown) {}		file_magic() : V(unknown) {}
	file_magic(_ v) : v_(v) {}		file_magic(Impl V) : V(V) {}
	explicit file_magic(int v) : v_(_(v)) {}		operator Impl() const { return V; }
	operator int() const {return v_;}
	private:		private:
	int v_;		Impl V;
	};		};
	/// @}		/// @}
	/// @name Physical Operators		/// @name Physical Operators
	/// @{		/// @{
	/// @brief Make \a path an absolute path.		/// @brief Make \a path an absolute path.
	///		///
	/// Makes \a path absolute using the current directory if it is not already . An		/// Makes \a path absolute using the current directory if it is not already . An
	/// empty \a path will result in the current directory.		/// empty \a path will result in the current directory.
	///		///
	/// /absolute/path => /absolute/path		/// /absolute/path => /absolute/path
	/// relative/../path => <current-directory>/relative/../path		/// relative/../path => <current-directory>/relative/../path
	///		///
	/// @param path A path that is modified to be an absolute path.		/// @param path A path that is modified to be an absolute path.
	/// @returns errc::success if \a path has been made absolute, otherwise a		/// @returns errc::success if \a path has been made absolute, otherwise a
	/// platform specific error_code.		/// platform specific error_code.
	error_code make_absolute(SmallVectorImpl<char> &path);		error_code make_absolute(SmallVectorImpl<char> &path);
	/// @brief Copy the file at \a from to the path \a to.
	///
	/// @param from The path to copy the file from.
	/// @param to The path to copy the file to.
	/// @param copt Behavior if \a to already exists.
	/// @returns errc::success if the file has been successfully copied.
	/// errc::file_exists if \a to already exists and \a copt ==
	/// copy_option::fail_if_exists. Otherwise a platform specific
	/// error_code.
	error_code copy_file(const Twine &from, const Twine &to,
	copy_option copt = copy_option::fail_if_exists);
	/// @brief Create all the non-existent directories in path.		/// @brief Create all the non-existent directories in path.
	///		///
	/// @param path Directories to create.		/// @param path Directories to create.
	/// @param existed Set to true if \a path already existed, false otherwise.		/// @param existed Set to true if \a path already existed, false otherwise.
	/// @returns errc::success if is_directory(path) and existed have been set,		/// @returns errc::success if is_directory(path) and existed have been set,
	/// otherwise a platform specific error_code.		/// otherwise a platform specific error_code.
	error_code create_directories(const Twine &path, bool &existed);		error_code create_directories(const Twine &path, bool &existed);
			/// @brief Convenience function for clients that don't need to know if the
			/// directory existed or not.
			inline error_code create_directories(const Twine &Path) {
			bool Existed;
			return create_directories(Path, Existed);
			}
	/// @brief Create the directory in path.		/// @brief Create the directory in path.
	///		///
	/// @param path Directory to create.		/// @param path Directory to create.
	/// @param existed Set to true if \a path already existed, false otherwise.		/// @param existed Set to true if \a path already existed, false otherwise.
	/// @returns errc::success if is_directory(path) and existed have been set,		/// @returns errc::success if is_directory(path) and existed have been set,
	/// otherwise a platform specific error_code.		/// otherwise a platform specific error_code.
	error_code create_directory(const Twine &path, bool &existed);		error_code create_directory(const Twine &path, bool &existed);
			/// @brief Convenience function for clients that don't need to know if the
			/// directory existed or not.
			inline error_code create_directory(const Twine &Path) {
			bool Existed;
			return create_directory(Path, Existed);
			}
	/// @brief Create a hard link from \a from to \a to.		/// @brief Create a hard link from \a from to \a to.
	///		///
	/// @param to The path to hard link to.		/// @param to The path to hard link to.
	/// @param from The path to hard link from. This is created.		/// @param from The path to hard link from. This is created.
	/// @returns errc::success if exists(to) && exists(from) && equivalent(to, from)		/// @returns errc::success if exists(to) && exists(from) && equivalent(to, from)
	/// , otherwise a platform specific error_code.		/// , otherwise a platform specific error_code.
	error_code create_hard_link(const Twine &to, const Twine &from);		error_code create_hard_link(const Twine &to, const Twine &from);
	/// @brief Create a symbolic link from \a from to \a to.		/// @brief Create a symbolic link from \a from to \a to.
	///		///
	skipping to change at line 293		skipping to change at line 337
	/// @brief Remove path. Equivalent to POSIX remove().		/// @brief Remove path. Equivalent to POSIX remove().
	///		///
	/// @param path Input path.		/// @param path Input path.
	/// @param existed Set to true if \a path existed, false if it did not.		/// @param existed Set to true if \a path existed, false if it did not.
	/// undefined otherwise.		/// undefined otherwise.
	/// @returns errc::success if path has been removed and existed has been		/// @returns errc::success if path has been removed and existed has been
	/// successfully set, otherwise a platform specific error_code.		/// successfully set, otherwise a platform specific error_code.
	error_code remove(const Twine &path, bool &existed);		error_code remove(const Twine &path, bool &existed);
			/// @brief Convenience function for clients that don't need to know if the
			file
			/// existed or not.
			inline error_code remove(const Twine &Path) {
			bool Existed;
			return remove(Path, Existed);
			}
	/// @brief Recursively remove all files below \a path, then \a path. Files are		/// @brief Recursively remove all files below \a path, then \a path. Files are
	/// removed as if by POSIX remove().		/// removed as if by POSIX remove().
	///		///
	/// @param path Input path.		/// @param path Input path.
	/// @param num_removed Number of files removed.		/// @param num_removed Number of files removed.
	/// @returns errc::success if path has been removed and num_removed has bee n		/// @returns errc::success if path has been removed and num_removed has bee n
	/// successfully set, otherwise a platform specific error_code.		/// successfully set, otherwise a platform specific error_code.
	error_code remove_all(const Twine &path, uint32_t &num_removed);		error_code remove_all(const Twine &path, uint32_t &num_removed);
			/// @brief Convenience function for clients that don't need to know how man
			y
			/// files were removed.
			inline error_code remove_all(const Twine &Path) {
			uint32_t Removed;
			return remove_all(Path, Removed);
			}
	/// @brief Rename \a from to \a to. Files are renamed as if by POSIX rename ().		/// @brief Rename \a from to \a to. Files are renamed as if by POSIX rename ().
	///		///
	/// @param from The path to rename from.		/// @param from The path to rename from.
	/// @param to The path to rename to. This is created.		/// @param to The path to rename to. This is created.
	error_code rename(const Twine &from, const Twine &to);		error_code rename(const Twine &from, const Twine &to);
	/// @brief Resize path to size. File is resized as if by POSIX truncate().		/// @brief Resize path to size. File is resized as if by POSIX truncate().
	///		///
	/// @param path Input path.		/// @param path Input path.
	/// @param size Size to resize to.		/// @param size Size to resize to.
	skipping to change at line 343		skipping to change at line 401
	/// platform specific error_code.		/// platform specific error_code.
	error_code exists(const Twine &path, bool &result);		error_code exists(const Twine &path, bool &result);
	/// @brief Simpler version of exists for clients that don't need to		/// @brief Simpler version of exists for clients that don't need to
	/// differentiate between an error and false.		/// differentiate between an error and false.
	inline bool exists(const Twine &path) {		inline bool exists(const Twine &path) {
	bool result;		bool result;
	return !exists(path, result) && result;		return !exists(path, result) && result;
	}		}
			/// @brief Can we execute this file?
			///
			/// @param Path Input path.
			/// @returns True if we can execute it, false otherwise.
			bool can_execute(const Twine &Path);
			/// @brief Can we write this file?
			///
			/// @param Path Input path.
			/// @returns True if we can write to it, false otherwise.
			bool can_write(const Twine &Path);
	/// @brief Do file_status's represent the same thing?		/// @brief Do file_status's represent the same thing?
	///		///
	/// @param A Input file_status.		/// @param A Input file_status.
	/// @param B Input file_status.		/// @param B Input file_status.
	///		///
	/// assert(status_known(A) || status_known(B));		/// assert(status_known(A) || status_known(B));
	///		///
	/// @returns True if A and B both represent the same file system entity, fa lse		/// @returns True if A and B both represent the same file system entity, fa lse
	/// otherwise.		/// otherwise.
	bool equivalent(file_status A, file_status B);		bool equivalent(file_status A, file_status B);
	skipping to change at line 373		skipping to change at line 443
	/// platform specific error_code.		/// platform specific error_code.
	error_code equivalent(const Twine &A, const Twine &B, bool &result);		error_code equivalent(const Twine &A, const Twine &B, bool &result);
	/// @brief Simpler version of equivalent for clients that don't need to		/// @brief Simpler version of equivalent for clients that don't need to
	/// differentiate between an error and false.		/// differentiate between an error and false.
	inline bool equivalent(const Twine &A, const Twine &B) {		inline bool equivalent(const Twine &A, const Twine &B) {
	bool result;		bool result;
	return !equivalent(A, B, result) && result;		return !equivalent(A, B, result) && result;
	}		}
	/// @brief Get file size.
	///
	/// @param path Input path.
	/// @param result Set to the size of the file in \a path.
	/// @returns errc::success if result has been successfully set, otherwise a
	/// platform specific error_code.
	error_code file_size(const Twine &path, uint64_t &result);
	/// @brief Does status represent a directory?		/// @brief Does status represent a directory?
	///		///
	/// @param status A file_status previously returned from status.		/// @param status A file_status previously returned from status.
	/// @returns status.type() == file_type::directory_file.		/// @returns status.type() == file_type::directory_file.
	bool is_directory(file_status status);		bool is_directory(file_status status);
	/// @brief Is path a directory?		/// @brief Is path a directory?
	///		///
	/// @param path Input path.		/// @param path Input path.
	/// @param result Set to true if \a path is a directory, false if it is not .		/// @param result Set to true if \a path is a directory, false if it is not .
	/// Undefined otherwise.		/// Undefined otherwise.
	/// @returns errc::success if result has been successfully set, otherwise a		/// @returns errc::success if result has been successfully set, otherwise a
	/// platform specific error_code.		/// platform specific error_code.
	error_code is_directory(const Twine &path, bool &result);		error_code is_directory(const Twine &path, bool &result);
			/// @brief Simpler version of is_directory for clients that don't need to
			/// differentiate between an error and false.
			inline bool is_directory(const Twine &Path) {
			bool Result;
			return !is_directory(Path, Result) && Result;
			}
	/// @brief Does status represent a regular file?		/// @brief Does status represent a regular file?
	///		///
	/// @param status A file_status previously returned from status.		/// @param status A file_status previously returned from status.
	/// @returns status_known(status) && status.type() == file_type::regular_fi le.		/// @returns status_known(status) && status.type() == file_type::regular_fi le.
	bool is_regular_file(file_status status);		bool is_regular_file(file_status status);
	/// @brief Is path a regular file?		/// @brief Is path a regular file?
	///		///
	/// @param path Input path.		/// @param path Input path.
	/// @param result Set to true if \a path is a regular file, false if it is not.		/// @param result Set to true if \a path is a regular file, false if it is not.
	/// Undefined otherwise.		/// Undefined otherwise.
	/// @returns errc::success if result has been successfully set, otherwise a		/// @returns errc::success if result has been successfully set, otherwise a
	/// platform specific error_code.		/// platform specific error_code.
	error_code is_regular_file(const Twine &path, bool &result);		error_code is_regular_file(const Twine &path, bool &result);
			/// @brief Simpler version of is_regular_file for clients that don't need t
			o
			/// differentiate between an error and false.
			inline bool is_regular_file(const Twine &Path) {
			bool Result;
			if (is_regular_file(Path, Result))
			return false;
			return Result;
			}
	/// @brief Does this status represent something that exists but is not a		/// @brief Does this status represent something that exists but is not a
	/// directory, regular file, or symlink?		/// directory, regular file, or symlink?
	///		///
	/// @param status A file_status previously returned from status.		/// @param status A file_status previously returned from status.
	/// @returns exists(s) && !is_regular_file(s) && !is_directory(s) &&		/// @returns exists(s) && !is_regular_file(s) && !is_directory(s) &&
	/// !is_symlink(s)		/// !is_symlink(s)
	bool is_other(file_status status);		bool is_other(file_status status);
	/// @brief Is path something that exists but is not a directory,		/// @brief Is path something that exists but is not a directory,
	/// regular file, or symlink?		/// regular file, or symlink?
	skipping to change at line 452		skipping to change at line 530
	error_code is_symlink(const Twine &path, bool &result);		error_code is_symlink(const Twine &path, bool &result);
	/// @brief Get file status as if by POSIX stat().		/// @brief Get file status as if by POSIX stat().
	///		///
	/// @param path Input path.		/// @param path Input path.
	/// @param result Set to the file status.		/// @param result Set to the file status.
	/// @returns errc::success if result has been successfully set, otherwise a		/// @returns errc::success if result has been successfully set, otherwise a
	/// platform specific error_code.		/// platform specific error_code.
	error_code status(const Twine &path, file_status &result);		error_code status(const Twine &path, file_status &result);
	/// @brief Modifies permission bits on a file		/// @brief A version for when a file descriptor is already available.
			error_code status(int FD, file_status &Result);
			/// @brief Get file size.
	///		///
	/// @param path Input path.		/// @param Path Input path.
	/// @returns errc::success if permissions have been changed, otherwise a		/// @param Result Set to the size of the file in \a Path.
			/// @returns errc::success if result has been successfully set, otherwise a
	/// platform specific error_code.		/// platform specific error_code.
	error_code permissions(const Twine &path, perms prms);		inline error_code file_size(const Twine &Path, uint64_t &Result) {
			file_status Status;
			error_code EC = status(Path, Status);
			if (EC)
			return EC;
			Result = Status.getSize();
			return error_code::success();
			}
			error_code setLastModificationAndAccessTime(int FD, TimeValue Time);
	/// @brief Is status available?		/// @brief Is status available?
	///		///
	/// @param s Input file status.		/// @param s Input file status.
	/// @returns True if status() != status_error.		/// @returns True if status() != status_error.
	bool status_known(file_status s);		bool status_known(file_status s);
	/// @brief Is status available?		/// @brief Is status available?
	///		///
	/// @param path Input path.		/// @param path Input path.
	/// @param result Set to true if status() != status_error.		/// @param result Set to true if status() != status_error.
	/// @returns errc::success if result has been successfully set, otherwise a		/// @returns errc::success if result has been successfully set, otherwise a
	/// platform specific error_code.		/// platform specific error_code.
	error_code status_known(const Twine &path, bool &result);		error_code status_known(const Twine &path, bool &result);
	/// @brief Generate a unique path and open it as a file.		/// @brief Create a uniquely named file.
	///		///
	/// Generates a unique path suitable for a temporary file and then opens it as a		/// Generates a unique path suitable for a temporary file and then opens it as a
	/// file. The name is based on \a model with '%' replaced by a random char in		/// file. The name is based on \a model with '%' replaced by a random char in
	/// [0-9a-f]. If \a model is not an absolute path, a suitable temporary		/// [0-9a-f]. If \a model is not an absolute path, a suitable temporary
	/// directory will be prepended.		/// directory will be prepended.
	///		///
			/// Example: clang-%%-%%-%%-%%-%%.s => clang-a0-b1-c2-d3-e4.s
			///
	/// This is an atomic operation. Either the file is created and opened, or the		/// This is an atomic operation. Either the file is created and opened, or the
	/// file system is left untouched.		/// file system is left untouched.
	///		///
	/// clang-%%-%%-%%-%%-%%.s => /tmp/clang-a0-b1-c2-d3-e4.s		/// The intendend use is for files that are to be kept, possibly after
	///		/// renaming them. For example, when running 'clang -c foo.o', the file can
	/// @param model Name to base unique path off of.		/// be first created as foo-abc123.o and then renamed.
	/// @param result_fd Set to the opened file's file descriptor.		///
	/// @param result_path Set to the opened file's absolute path.		/// @param Model Name to base unique path off of.
	/// @param makeAbsolute If true and \a model is not an absolute path, a tem		/// @param ResultFD Set to the opened file's file descriptor.
	p		/// @param ResultPath Set to the opened file's absolute path.
	/// directory will be prepended.		/// @returns errc::success if Result{FD,Path} have been successfully set,
	/// @returns errc::success if result_{fd,path} have been successfully set,
	/// otherwise a platform specific error_code.		/// otherwise a platform specific error_code.
	error_code unique_file(const Twine &model, int &result_fd,		error_code createUniqueFile(const Twine &Model, int &ResultFD,
	SmallVectorImpl<char> &result_path,		SmallVectorImpl<char> &ResultPath,
	bool makeAbsolute = true, unsigned mode = 0600);		unsigned Mode = all_read | all_write);
			/// @brief Simpler version for clients that don't want an open file.
			error_code createUniqueFile(const Twine &Model,
			SmallVectorImpl<char> &ResultPath);
			/// @brief Create a file in the system temporary directory.
			///
			/// The filename is of the form prefix-random_chars.suffix. Since the direc
			tory
			/// is not know to the caller, Prefix and Suffix cannot have path separator
			s.
			/// The files are created with mode 0600.
			///
			/// This should be used for things like a temporary .s that is removed afte
			r
			/// running the assembler.
			error_code createTemporaryFile(const Twine &Prefix, StringRef Suffix,
			int &ResultFD,
			SmallVectorImpl<char> &ResultPath);
			/// @brief Simpler version for clients that don't want an open file.
			error_code createTemporaryFile(const Twine &Prefix, StringRef Suffix,
			SmallVectorImpl<char> &ResultPath);
			error_code createUniqueDirectory(const Twine &Prefix,
			SmallVectorImpl<char> &ResultPath);
			enum OpenFlags {
			F_None = 0,
			/// F_Excl - When opening a file, this flag makes raw_fd_ostream
			/// report an error if the file already exists.
			F_Excl = 1,
			/// F_Append - When opening a file, if it already exists append to the
			/// existing file instead of returning an error. This may not be specifi
			ed
			/// with F_Excl.
			F_Append = 2,
			/// F_Binary - The file should be opened in binary mode on platforms that
			/// make this distinction.
			F_Binary = 4
			};
	/// @brief Canonicalize path.		inline OpenFlags operator|(OpenFlags A, OpenFlags B) {
	///		return OpenFlags(unsigned(A) | unsigned(B));
	/// Sets result to the file system's idea of what path is. The result is al		}
	ways
	/// absolute and has the same capitalization as the file system.		inline OpenFlags &operator|=(OpenFlags &A, OpenFlags B) {
	///		A = A | B;
	/// @param path Input path.		return A;
	/// @param result Set to the canonicalized version of \a path.		}
	/// @returns errc::success if result has been successfully set, otherwise a
	/// platform specific error_code.		error_code openFileForWrite(const Twine &Name, int &ResultFD, OpenFlags Fla
	error_code canonicalize(const Twine &path, SmallVectorImpl<char> &result);		gs,
			unsigned Mode = 0666);
			error_code openFileForRead(const Twine &Name, int &ResultFD);
	/// @brief Are \a path's first bytes \a magic?		/// @brief Are \a path's first bytes \a magic?
	///		///
	/// @param path Input path.		/// @param path Input path.
	/// @param magic Byte sequence to compare \a path's first len(magic) bytes to.		/// @param magic Byte sequence to compare \a path's first len(magic) bytes to.
	/// @returns errc::success if result has been successfully set, otherwise a		/// @returns errc::success if result has been successfully set, otherwise a
	/// platform specific error_code.		/// platform specific error_code.
	error_code has_magic(const Twine &path, const Twine &magic, bool &result);		error_code has_magic(const Twine &path, const Twine &magic, bool &result);
	/// @brief Get \a path's first \a len bytes.		/// @brief Get \a path's first \a len bytes.
	skipping to change at line 534		skipping to change at line 670
	/// \a path, otherwise a platform specific error_code.		/// \a path, otherwise a platform specific error_code.
	error_code get_magic(const Twine &path, uint32_t len,		error_code get_magic(const Twine &path, uint32_t len,
	SmallVectorImpl<char> &result);		SmallVectorImpl<char> &result);
	/// @brief Identify the type of a binary file based on how magical it is.		/// @brief Identify the type of a binary file based on how magical it is.
	file_magic identify_magic(StringRef magic);		file_magic identify_magic(StringRef magic);
	/// @brief Get and identify \a path's type based on its content.		/// @brief Get and identify \a path's type based on its content.
	///		///
	/// @param path Input path.		/// @param path Input path.
	/// @param result Set to the type of file, or LLVMFileType::Unknown_FileTyp e.		/// @param result Set to the type of file, or file_magic::unknown.
	/// @returns errc::success if result has been successfully set, otherwise a		/// @returns errc::success if result has been successfully set, otherwise a
	/// platform specific error_code.		/// platform specific error_code.
	error_code identify_magic(const Twine &path, file_magic &result);		error_code identify_magic(const Twine &path, file_magic &result);
	/// @brief Get library paths the system linker uses.		error_code getUniqueID(const Twine Path, UniqueID &Result);
	///
	/// @param result Set to the list of system library paths.
	/// @returns errc::success if result has been successfully set, otherwise a
	/// platform specific error_code.
	error_code GetSystemLibraryPaths(SmallVectorImpl<std::string> &result);
	/// @brief Get bitcode library paths the system linker uses
	/// + LLVM_LIB_SEARCH_PATH + LLVM_LIBDIR.
	///
	/// @param result Set to the list of bitcode library paths.
	/// @returns errc::success if result has been successfully set, otherwise a
	/// platform specific error_code.
	error_code GetBitcodeLibraryPaths(SmallVectorImpl<std::string> &result);
	/// @brief Find a library.
	///
	/// Find the path to a library using its short name. Use the system
	/// dependent library paths to locate the library.
	///
	/// c => /usr/lib/libc.so
	///
	/// @param short_name Library name one would give to the system linker.
	/// @param result Set to the absolute path \a short_name represents.
	/// @returns errc::success if result has been successfully set, otherwise a
	/// platform specific error_code.
	error_code FindLibrary(const Twine &short_name, SmallVectorImpl<char> &resu
	lt);
	/// @brief Get absolute path of main executable.
	///
	/// @param argv0 The program name as it was spelled on the command line.
	/// @param MainAddr Address of some symbol in the executable (not in a libr
	ary).
	/// @param result Set to the absolute path of the current executable.
	/// @returns errc::success if result has been successfully set, otherwise a
	/// platform specific error_code.
	error_code GetMainExecutable(const char *argv0, void *MainAddr,
	SmallVectorImpl<char> &result);
	/// This class represents a memory mapped file. It is based on		/// This class represents a memory mapped file. It is based on
	/// boost::iostreams::mapped_file.		/// boost::iostreams::mapped_file.
	class mapped_file_region {		class mapped_file_region {
	mapped_file_region() LLVM_DELETED_FUNCTION;		mapped_file_region() LLVM_DELETED_FUNCTION;
	mapped_file_region(mapped_file_region&) LLVM_DELETED_FUNCTION;		mapped_file_region(mapped_file_region&) LLVM_DELETED_FUNCTION;
	mapped_file_region &operator =(mapped_file_region&) LLVM_DELETED_FUNCTION ;		mapped_file_region &operator =(mapped_file_region&) LLVM_DELETED_FUNCTION ;
	public:		public:
	enum mapmode {		enum mapmode {
	skipping to change at line 625		skipping to change at line 725
	/// \param path Path to the file to map. If it does not exist it will be		/// \param path Path to the file to map. If it does not exist it will be
	/// created.		/// created.
	/// \param mode How to map the memory.		/// \param mode How to map the memory.
	/// \param length Number of bytes to map in starting at \a offset. If the file		/// \param length Number of bytes to map in starting at \a offset. If the file
	/// is shorter than this, it will be extended. If \a length is		/// is shorter than this, it will be extended. If \a length is
	/// 0, the entire file will be mapped.		/// 0, the entire file will be mapped.
	/// \param offset Byte offset from the beginning of the file where the ma p		/// \param offset Byte offset from the beginning of the file where the ma p
	/// should begin. Must be a multiple of		/// should begin. Must be a multiple of
	/// mapped_file_region::alignment().		/// mapped_file_region::alignment().
	/// \param ec This is set to errc::success if the map was constructed		/// \param ec This is set to errc::success if the map was constructed
	/// sucessfully. Otherwise it is set to a platform dependent er ror.		/// successfully. Otherwise it is set to a platform dependent e rror.
	mapped_file_region(const Twine &path,		mapped_file_region(const Twine &path,
	mapmode mode,		mapmode mode,
	uint64_t length,		uint64_t length,
	uint64_t offset,		uint64_t offset,
	error_code &ec);		error_code &ec);
	/// \param fd An open file descriptor to map. mapped_file_region takes		/// \param fd An open file descriptor to map. mapped_file_region takes
	/// ownership if closefd is true. It must have been opended in the corr ect		/// ownership if closefd is true. It must have been opended in the corr ect
	/// mode.		/// mode.
	mapped_file_region(int fd,		mapped_file_region(int fd,
	skipping to change at line 649		skipping to change at line 749
	uint64_t offset,		uint64_t offset,
	error_code &ec);		error_code &ec);
	~mapped_file_region();		~mapped_file_region();
	mapmode flags() const;		mapmode flags() const;
	uint64_t size() const;		uint64_t size() const;
	char *data() const;		char *data() const;
	/// Get a const view of the data. Modifying this memory has undefined		/// Get a const view of the data. Modifying this memory has undefined
	/// behaivor.		/// behavior.
	const char *const_data() const;		const char *const_data() const;
	/// \returns The minimum alignment offset must be.		/// \returns The minimum alignment offset must be.
	static int alignment();		static int alignment();
	};		};
	/// @brief Memory maps the contents of a file		/// @brief Memory maps the contents of a file
	///		///
	/// @param path Path to file to map.		/// @param path Path to file to map.
	/// @param file_offset Byte offset in file where mapping should begin.		/// @param file_offset Byte offset in file where mapping should begin.
	skipping to change at line 679		skipping to change at line 779
	bool map_writable, void *&result);		bool map_writable, void *&result);
	/// @brief Memory unmaps the contents of a file		/// @brief Memory unmaps the contents of a file
	///		///
	/// @param base Pointer to the start of the buffer.		/// @param base Pointer to the start of the buffer.
	/// @param size Byte length of the range to unmmap.		/// @param size Byte length of the range to unmmap.
	/// @returns errc::success if result has been successfully set, otherwise a		/// @returns errc::success if result has been successfully set, otherwise a
	/// platform specific error_code.		/// platform specific error_code.
	error_code unmap_file_pages(void *base, size_t size);		error_code unmap_file_pages(void *base, size_t size);
			/// Return the path to the main executable, given the value of argv[0] from
			/// program startup and the address of main itself. In extremis, this funct
			ion
			/// may fail and return an empty path.
			std::string getMainExecutable(const char *argv0, void *MainExecAddr);
	/// @}		/// @}
	/// @name Iterators		/// @name Iterators
	/// @{		/// @{
	/// directory_entry - A single entry in a directory. Caches the status eith er		/// directory_entry - A single entry in a directory. Caches the status eith er
	/// from the result of the iteration syscall, or the first time status is		/// from the result of the iteration syscall, or the first time status is
	/// called.		/// called.
	class directory_entry {		class directory_entry {
	std::string Path;		std::string Path;
	mutable file_status Status;		mutable file_status Status;
	skipping to change at line 757		skipping to change at line 862
	ec = detail::directory_iterator_construct(*State,		ec = detail::directory_iterator_construct(*State,
	path.toStringRef(path_storage));		path.toStringRef(path_storage));
	}		}
	explicit directory_iterator(const directory_entry &de, error_code &ec) {		explicit directory_iterator(const directory_entry &de, error_code &ec) {
	State = new detail::DirIterState;		State = new detail::DirIterState;
	ec = detail::directory_iterator_construct(*State, de.path());		ec = detail::directory_iterator_construct(*State, de.path());
	}		}
	/// Construct end iterator.		/// Construct end iterator.
	directory_iterator() : State(new detail::DirIterState) {}		directory_iterator() : State(0) {}
	// No operator++ because we need error_code.		// No operator++ because we need error_code.
	directory_iterator &increment(error_code &ec) {		directory_iterator &increment(error_code &ec) {
	ec = directory_iterator_increment(*State);		ec = directory_iterator_increment(*State);
	return *this;		return *this;
	}		}
	const directory_entry &operator*() const { return State->CurrentEntry; }		const directory_entry &operator*() const { return State->CurrentEntry; }
	const directory_entry *operator->() const { return &State->CurrentEntry; }		const directory_entry *operator->() const { return &State->CurrentEntry; }
	bool operator==(const directory_iterator &RHS) const {		bool operator==(const directory_iterator &RHS) const {
			if (State == RHS.State)
			return true;
			if (RHS.State == 0)
			return State->CurrentEntry == directory_entry();
			if (State == 0)
			return RHS.State->CurrentEntry == directory_entry();
	return State->CurrentEntry == RHS.State->CurrentEntry;		return State->CurrentEntry == RHS.State->CurrentEntry;
	}		}
	bool operator!=(const directory_iterator &RHS) const {		bool operator!=(const directory_iterator &RHS) const {
	return !(*this == RHS);		return !(*this == RHS);
	}		}
	// Other members as required by		// Other members as required by
	// C++ Std, 24.1.1 Input iterators [input.iterators]		// C++ Std, 24.1.1 Input iterators [input.iterators]
	};		};
	skipping to change at line 808		skipping to change at line 919
	public:		public:
	recursive_directory_iterator() {}		recursive_directory_iterator() {}
	explicit recursive_directory_iterator(const Twine &path, error_code &ec)		explicit recursive_directory_iterator(const Twine &path, error_code &ec)
	: State(new detail::RecDirIterState) {		: State(new detail::RecDirIterState) {
	State->Stack.push(directory_iterator(path, ec));		State->Stack.push(directory_iterator(path, ec));
	if (State->Stack.top() == directory_iterator())		if (State->Stack.top() == directory_iterator())
	State.reset();		State.reset();
	}		}
	// No operator++ because we need error_code.		// No operator++ because we need error_code.
	recursive_directory_iterator &increment(error_code &ec) {		recursive_directory_iterator &increment(error_code &ec) {
	static const directory_iterator end_itr;		const directory_iterator end_itr;
	if (State->HasNoPushRequest)		if (State->HasNoPushRequest)
	State->HasNoPushRequest = false;		State->HasNoPushRequest = false;
	else {		else {
	file_status st;		file_status st;
	if ((ec = State->Stack.top()->status(st))) return *this;		if ((ec = State->Stack.top()->status(st))) return *this;
	if (is_directory(st)) {		if (is_directory(st)) {
	State->Stack.push(directory_iterator(*State->Stack.top(), ec));		State->Stack.push(directory_iterator(*State->Stack.top(), ec));
	if (ec) return *this;		if (ec) return *this;
	if (State->Stack.top() != end_itr) {		if (State->Stack.top() != end_itr) {
	skipping to change at line 852		skipping to change at line 963
	// observers		// observers
	/// Gets the current level. Starting path is at level 0.		/// Gets the current level. Starting path is at level 0.
	int level() const { return State->Level; }		int level() const { return State->Level; }
	/// Returns true if no_push has been called for this directory_entry.		/// Returns true if no_push has been called for this directory_entry.
	bool no_push_request() const { return State->HasNoPushRequest; }		bool no_push_request() const { return State->HasNoPushRequest; }
	// modifiers		// modifiers
	/// Goes up one level if Level > 0.		/// Goes up one level if Level > 0.
	void pop() {		void pop() {
	assert(State && "Cannot pop and end itertor!");		assert(State && "Cannot pop an end iterator!");
	assert(State->Level > 0 && "Cannot pop an iterator with level < 1");		assert(State->Level > 0 && "Cannot pop an iterator with level < 1");
	static const directory_iterator end_itr;		const directory_iterator end_itr;
	error_code ec;		error_code ec;
	do {		do {
	if (ec)		if (ec)
	report_fatal_error("Error incrementing directory iterator.");		report_fatal_error("Error incrementing directory iterator.");
	State->Stack.pop();		State->Stack.pop();
	--State->Level;		--State->Level;
	} while (!State->Stack.empty()		} while (!State->Stack.empty()
	&& State->Stack.top().increment(ec) == end_itr);		&& State->Stack.top().increment(ec) == end_itr);
	// Check if we are done. If so, create an end iterator.		// Check if we are done. If so, create an end iterator.
End of changes. 42 change blocks.
	145 lines changed or deleted		265 lines changed or added

	FileUtilities.h		FileUtilities.h
	skipping to change at line 30		skipping to change at line 30
	namespace llvm {		namespace llvm {
	/// DiffFilesWithTolerance - Compare the two files specified, returning 0 if		/// DiffFilesWithTolerance - Compare the two files specified, returning 0 if
	/// the files match, 1 if they are different, and 2 if there is a file er ror.		/// the files match, 1 if they are different, and 2 if there is a file er ror.
	/// This function allows you to specify an absolute and relative FP error that		/// This function allows you to specify an absolute and relative FP error that
	/// is allowed to exist. If you specify a string to fill in for the erro r		/// is allowed to exist. If you specify a string to fill in for the erro r
	/// option, it will set the string to an error message if an error occurs , or		/// option, it will set the string to an error message if an error occurs , or
	/// if the files are different.		/// if the files are different.
	///		///
	int DiffFilesWithTolerance(const sys::PathWithStatus &FileA,		int DiffFilesWithTolerance(StringRef FileA,
	const sys::PathWithStatus &FileB,		StringRef FileB,
	double AbsTol, double RelTol,		double AbsTol, double RelTol,
	std::string *Error = 0);		std::string *Error = 0);
	/// FileRemover - This class is a simple object meant to be stack allocat ed.		/// FileRemover - This class is a simple object meant to be stack allocat ed.
	/// If an exception is thrown from a region, the object removes the filen ame		/// If an exception is thrown from a region, the object removes the filen ame
	/// specified (if deleteIt is true).		/// specified (if deleteIt is true).
	///		///
	class FileRemover {		class FileRemover {
	SmallString<128> Filename;		SmallString<128> Filename;
	bool DeleteIt;		bool DeleteIt;
End of changes. 1 change blocks.
	2 lines changed or deleted		2 lines changed or added

	FoldingSet.h		FoldingSet.h
	skipping to change at line 355		skipping to change at line 355
	// Convenience type to hide the implementation of the folding set.		// Convenience type to hide the implementation of the folding set.
	typedef FoldingSetImpl::Node FoldingSetNode;		typedef FoldingSetImpl::Node FoldingSetNode;
	template<class T> class FoldingSetIterator;		template<class T> class FoldingSetIterator;
	template<class T> class FoldingSetBucketIterator;		template<class T> class FoldingSetBucketIterator;
	// Definitions of FoldingSetTrait and ContextualFoldingSetTrait functions, which		// Definitions of FoldingSetTrait and ContextualFoldingSetTrait functions, which
	// require the definition of FoldingSetNodeID.		// require the definition of FoldingSetNodeID.
	template<typename T>		template<typename T>
	inline bool		inline bool
	DefaultFoldingSetTrait<T>::Equals(T &X, const FoldingSetNodeID &ID,		DefaultFoldingSetTrait<T>::Equals(T &X, const FoldingSetNodeID &ID,
	unsigned IDHash, FoldingSetNodeID &TempID		unsigned /*IDHash*/,
	) {		FoldingSetNodeID &TempID) {
	FoldingSetTrait<T>::Profile(X, TempID);		FoldingSetTrait<T>::Profile(X, TempID);
	return TempID == ID;		return TempID == ID;
	}		}
	template<typename T>		template<typename T>
	inline unsigned		inline unsigned
	DefaultFoldingSetTrait<T>::ComputeHash(T &X, FoldingSetNodeID &TempID) {		DefaultFoldingSetTrait<T>::ComputeHash(T &X, FoldingSetNodeID &TempID) {
	FoldingSetTrait<T>::Profile(X, TempID);		FoldingSetTrait<T>::Profile(X, TempID);
	return TempID.ComputeHash();		return TempID.ComputeHash();
	}		}
	template<typename T, typename Ctx>		template<typename T, typename Ctx>
	inline bool		inline bool
	DefaultContextualFoldingSetTrait<T, Ctx>::Equals(T &X,		DefaultContextualFoldingSetTrait<T, Ctx>::Equals(T &X,
	const FoldingSetNodeID &ID ,		const FoldingSetNodeID &ID ,
	unsigned IDHash,		unsigned /*IDHash*/,
	FoldingSetNodeID &TempID,		FoldingSetNodeID &TempID,
	Ctx Context) {		Ctx Context) {
	ContextualFoldingSetTrait<T, Ctx>::Profile(X, TempID, Context);		ContextualFoldingSetTrait<T, Ctx>::Profile(X, TempID, Context);
	return TempID == ID;		return TempID == ID;
	}		}
	template<typename T, typename Ctx>		template<typename T, typename Ctx>
	inline unsigned		inline unsigned
	DefaultContextualFoldingSetTrait<T, Ctx>::ComputeHash(T &X,		DefaultContextualFoldingSetTrait<T, Ctx>::ComputeHash(T &X,
	FoldingSetNodeID &Tem pID,		FoldingSetNodeID &Tem pID,
	Ctx Context) {		Ctx Context) {
End of changes. 2 change blocks.
	3 lines changed or deleted		3 lines changed or added

	FormattedStream.h		FormattedStream.h
	skipping to change at line 19		skipping to change at line 19
	//		//
	// This file contains raw_ostream implementations for streams to do		// This file contains raw_ostream implementations for streams to do
	// things like pretty-print comments.		// things like pretty-print comments.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_SUPPORT_FORMATTEDSTREAM_H		#ifndef LLVM_SUPPORT_FORMATTEDSTREAM_H
	#define LLVM_SUPPORT_FORMATTEDSTREAM_H		#define LLVM_SUPPORT_FORMATTEDSTREAM_H
	#include "llvm/Support/raw_ostream.h"		#include "llvm/Support/raw_ostream.h"
			#include <utility>
	namespace llvm {		namespace llvm {
	/// formatted_raw_ostream - A raw_ostream that wraps another one and keeps track		/// formatted_raw_ostream - A raw_ostream that wraps another one and keeps track
	/// of column position, allowing padding out to specific column boundaries.		/// of line and column position, allowing padding out to specific column
			/// boundaries and querying the number of lines written to the stream.
	///		///
	class formatted_raw_ostream : public raw_ostream {		class formatted_raw_ostream : public raw_ostream {
	public:		public:
	/// DELETE_STREAM - Tell the destructor to delete the held stream.		/// DELETE_STREAM - Tell the destructor to delete the held stream.
	///		///
	static const bool DELETE_STREAM = true;		static const bool DELETE_STREAM = true;
	/// PRESERVE_STREAM - Tell the destructor to not delete the held		/// PRESERVE_STREAM - Tell the destructor to not delete the held
	/// stream.		/// stream.
	///		///
	skipping to change at line 47		skipping to change at line 49
	/// TheStream - The real stream we output to. We set it to be		/// TheStream - The real stream we output to. We set it to be
	/// unbuffered, since we're already doing our own buffering.		/// unbuffered, since we're already doing our own buffering.
	///		///
	raw_ostream *TheStream;		raw_ostream *TheStream;
	/// DeleteStream - Do we need to delete TheStream in the		/// DeleteStream - Do we need to delete TheStream in the
	/// destructor?		/// destructor?
	///		///
	bool DeleteStream;		bool DeleteStream;
	/// ColumnScanned - The current output column of the data that's		/// Position - The current output column and line of the data that's
	/// been flushed and the portion of the buffer that's been		/// been flushed and the portion of the buffer that's been
	/// scanned. The column scheme is zero-based.		/// scanned. The line and column scheme is zero-based.
	///		///
	unsigned ColumnScanned;		std::pair<unsigned, unsigned> Position;
	/// Scanned - This points to one past the last character in the		/// Scanned - This points to one past the last character in the
	/// buffer we've scanned.		/// buffer we've scanned.
	///		///
	const char *Scanned;		const char *Scanned;
	virtual void write_impl(const char *Ptr, size_t Size) LLVM_OVERRIDE;		virtual void write_impl(const char *Ptr, size_t Size) LLVM_OVERRIDE;
	/// current_pos - Return the current position within the stream,		/// current_pos - Return the current position within the stream,
	/// not counting the bytes currently in the buffer.		/// not counting the bytes currently in the buffer.
	virtual uint64_t current_pos() const LLVM_OVERRIDE {		virtual uint64_t current_pos() const LLVM_OVERRIDE {
	// Our current position in the stream is all the contents which have be en		// Our current position in the stream is all the contents which have be en
	// written to the underlying stream (*not* the current position of the		// written to the underlying stream (*not* the current position of the
	// underlying stream).		// underlying stream).
	return TheStream->tell();		return TheStream->tell();
	}		}
	/// ComputeColumn - Examine the given output buffer and figure out which		/// ComputePosition - Examine the given output buffer and figure out the
	/// column we end up in after output.		new
			/// position after output.
	///		///
	void ComputeColumn(const char *Ptr, size_t size);		void ComputePosition(const char *Ptr, size_t size);
	public:		public:
	/// formatted_raw_ostream - Open the specified file for		/// formatted_raw_ostream - Open the specified file for
	/// writing. If an error occurs, information about the error is		/// writing. If an error occurs, information about the error is
	/// put into ErrorInfo, and the stream should be immediately		/// put into ErrorInfo, and the stream should be immediately
	/// destroyed; the string will be empty if no error occurred.		/// destroyed; the string will be empty if no error occurred.
	///		///
	/// As a side effect, the given Stream is set to be Unbuffered.		/// As a side effect, the given Stream is set to be Unbuffered.
	/// This is because formatted_raw_ostream does its own buffering,		/// This is because formatted_raw_ostream does its own buffering,
	/// so it doesn't want another layer of buffering to be happening		/// so it doesn't want another layer of buffering to be happening
	/// underneath it.		/// underneath it.
	///		///
	formatted_raw_ostream(raw_ostream &Stream, bool Delete = false)		formatted_raw_ostream(raw_ostream &Stream, bool Delete = false)
	: raw_ostream(), TheStream(0), DeleteStream(false), ColumnScanned(0) {		: raw_ostream(), TheStream(0), DeleteStream(false), Position(0, 0) {
	setStream(Stream, Delete);		setStream(Stream, Delete);
	}		}
	explicit formatted_raw_ostream()		explicit formatted_raw_ostream()
	: raw_ostream(), TheStream(0), DeleteStream(false), ColumnScanned(0) {		: raw_ostream(), TheStream(0), DeleteStream(false), Position(0, 0) {
	Scanned = 0;		Scanned = 0;
	}		}
	~formatted_raw_ostream() {		~formatted_raw_ostream() {
	flush();		flush();
	releaseStream();		releaseStream();
	}		}
	void setStream(raw_ostream &Stream, bool Delete = false) {		void setStream(raw_ostream &Stream, bool Delete = false) {
	releaseStream();		releaseStream();
	skipping to change at line 125		skipping to change at line 127
	Scanned = 0;		Scanned = 0;
	}		}
	/// PadToColumn - Align the output to some column number. If the current		/// PadToColumn - Align the output to some column number. If the current
	/// column is already equal to or more than NewCol, PadToColumn inserts o ne		/// column is already equal to or more than NewCol, PadToColumn inserts o ne
	/// space.		/// space.
	///		///
	/// \param NewCol - The column to move to.		/// \param NewCol - The column to move to.
	formatted_raw_ostream &PadToColumn(unsigned NewCol);		formatted_raw_ostream &PadToColumn(unsigned NewCol);
			/// getColumn - Return the column number
			unsigned getColumn() { return Position.first; }
			/// getLine - Return the line number
			unsigned getLine() { return Position.second; }
			raw_ostream &resetColor() {
			TheStream->resetColor();
			return *this;
			}
			raw_ostream &reverseColor() {
			TheStream->reverseColor();
			return *this;
			}
			raw_ostream &changeColor(enum Colors Color,
			bool Bold,
			bool BG) {
			TheStream->changeColor(Color, Bold, BG);
			return *this;
			}
			bool is_displayed() const {
			return TheStream->is_displayed();
			}
	private:		private:
	void releaseStream() {		void releaseStream() {
	// Delete the stream if needed. Otherwise, transfer the buffer		// Delete the stream if needed. Otherwise, transfer the buffer
	// settings from this raw_ostream back to the underlying stream.		// settings from this raw_ostream back to the underlying stream.
	if (!TheStream)		if (!TheStream)
	return;		return;
	if (DeleteStream)		if (DeleteStream)
	delete TheStream;		delete TheStream;
	else if (size_t BufferSize = GetBufferSize())		else if (size_t BufferSize = GetBufferSize())
	TheStream->SetBufferSize(BufferSize);		TheStream->SetBufferSize(BufferSize);
End of changes. 10 change blocks.
	9 lines changed or deleted		39 lines changed or added

	Function.h		Function.h
	skipping to change at line 162		skipping to change at line 162
	/// subsequent requests for the same ID return results much faster from t he		/// subsequent requests for the same ID return results much faster from t he
	/// cache.		/// cache.
	///		///
	unsigned getIntrinsicID() const LLVM_READONLY;		unsigned getIntrinsicID() const LLVM_READONLY;
	bool isIntrinsic() const { return getName().startswith("llvm."); }		bool isIntrinsic() const { return getName().startswith("llvm."); }
	/// getCallingConv()/setCallingConv(CC) - These method get and set the		/// getCallingConv()/setCallingConv(CC) - These method get and set the
	/// calling convention of this function. The enum values for the known		/// calling convention of this function. The enum values for the known
	/// calling conventions are defined in CallingConv.h.		/// calling conventions are defined in CallingConv.h.
	CallingConv::ID getCallingConv() const {		CallingConv::ID getCallingConv() const {
	return static_cast<CallingConv::ID>(getSubclassDataFromValue() >> 1);		return static_cast<CallingConv::ID>(getSubclassDataFromValue() >> 2);
	}		}
	void setCallingConv(CallingConv::ID CC) {		void setCallingConv(CallingConv::ID CC) {
	setValueSubclassData((getSubclassDataFromValue() & 1) |		setValueSubclassData((getSubclassDataFromValue() & 3) |
	(static_cast<unsigned>(CC) << 1));		(static_cast<unsigned>(CC) << 2));
	}		}
	/// getAttributes - Return the attribute list for this Function.		/// @brief Return the attribute list for this Function.
	///
	AttributeSet getAttributes() const { return AttributeSets; }		AttributeSet getAttributes() const { return AttributeSets; }
	/// setAttributes - Set the attribute list for this Function.		/// @brief Set the attribute list for this Function.
	///
	void setAttributes(AttributeSet attrs) { AttributeSets = attrs; }		void setAttributes(AttributeSet attrs) { AttributeSets = attrs; }
	/// addFnAttr - Add function attributes to this function.		/// @brief Add function attributes to this function.
	///
	void addFnAttr(Attribute::AttrKind N) {		void addFnAttr(Attribute::AttrKind N) {
	setAttributes(AttributeSets.addAttribute(getContext(),		setAttributes(AttributeSets.addAttribute(getContext(),
	AttributeSet::FunctionIndex, N ));		AttributeSet::FunctionIndex, N ));
	}		}
	/// addFnAttr - Add function attributes to this function.		/// @brief Remove function attributes from this function.
	///		void removeFnAttr(Attribute::AttrKind N) {
			setAttributes(AttributeSets.removeAttribute(
			getContext(), AttributeSet::FunctionIndex, N));
			}
			/// @brief Add function attributes to this function.
	void addFnAttr(StringRef Kind) {		void addFnAttr(StringRef Kind) {
	setAttributes(		setAttributes(
	AttributeSets.addAttribute(getContext(),		AttributeSets.addAttribute(getContext(),
	AttributeSet::FunctionIndex, Kind));		AttributeSet::FunctionIndex, Kind));
	}		}
			void addFnAttr(StringRef Kind, StringRef Value) {
			setAttributes(
			AttributeSets.addAttribute(getContext(),
			AttributeSet::FunctionIndex, Kind, Value))
			;
			}
	/// \brief Return true if the function has the attribute.		/// @brief Return true if the function has the attribute.
	bool hasFnAttribute(Attribute::AttrKind Kind) const {		bool hasFnAttribute(Attribute::AttrKind Kind) const {
	return AttributeSets.hasAttribute(AttributeSet::FunctionIndex, Kind);		return AttributeSets.hasAttribute(AttributeSet::FunctionIndex, Kind);
	}		}
	bool hasFnAttribute(StringRef Kind) const {		bool hasFnAttribute(StringRef Kind) const {
	return AttributeSets.hasAttribute(AttributeSet::FunctionIndex, Kind);		return AttributeSets.hasAttribute(AttributeSet::FunctionIndex, Kind);
	}		}
			/// @brief Return the attribute for the given attribute kind.
			Attribute getFnAttribute(Attribute::AttrKind Kind) const {
			return AttributeSets.getAttribute(AttributeSet::FunctionIndex, Kind);
			}
			Attribute getFnAttribute(StringRef Kind) const {
			return AttributeSets.getAttribute(AttributeSet::FunctionIndex, Kind);
			}
	/// hasGC/getGC/setGC/clearGC - The name of the garbage collection algori thm		/// hasGC/getGC/setGC/clearGC - The name of the garbage collection algori thm
	/// to use during code generation.		/// to use during code generation.
	bool hasGC() const;		bool hasGC() const;
	const char *getGC() const;		const char *getGC() const;
	void setGC(const char *Str);		void setGC(const char *Str);
	void clearGC();		void clearGC();
	/// @brief adds the attribute to the list of attributes.		/// @brief adds the attribute to the list of attributes.
	void addAttribute(unsigned i, Attribute::AttrKind attr);		void addAttribute(unsigned i, Attribute::AttrKind attr);
	skipping to change at line 306		skipping to change at line 321
	/// @brief Determine if the parameter can be captured.		/// @brief Determine if the parameter can be captured.
	/// @param n The parameter to check. 1 is the first parameter, 0 is the r eturn		/// @param n The parameter to check. 1 is the first parameter, 0 is the r eturn
	bool doesNotCapture(unsigned n) const {		bool doesNotCapture(unsigned n) const {
	return AttributeSets.hasAttribute(n, Attribute::NoCapture);		return AttributeSets.hasAttribute(n, Attribute::NoCapture);
	}		}
	void setDoesNotCapture(unsigned n) {		void setDoesNotCapture(unsigned n) {
	addAttribute(n, Attribute::NoCapture);		addAttribute(n, Attribute::NoCapture);
	}		}
			bool doesNotAccessMemory(unsigned n) const {
			return AttributeSets.hasAttribute(n, Attribute::ReadNone);
			}
			void setDoesNotAccessMemory(unsigned n) {
			addAttribute(n, Attribute::ReadNone);
			}
			bool onlyReadsMemory(unsigned n) const {
			return doesNotAccessMemory(n) ||
			AttributeSets.hasAttribute(n, Attribute::ReadOnly);
			}
			void setOnlyReadsMemory(unsigned n) {
			addAttribute(n, Attribute::ReadOnly);
			}
	/// copyAttributesFrom - copy all additional attributes (those not needed to		/// copyAttributesFrom - copy all additional attributes (those not needed to
	/// create a Function) from the Function Src to this one.		/// create a Function) from the Function Src to this one.
	void copyAttributesFrom(const GlobalValue *Src);		void copyAttributesFrom(const GlobalValue *Src);
	/// deleteBody - This method deletes the body of the function, and conver ts		/// deleteBody - This method deletes the body of the function, and conver ts
	/// the linkage to external.		/// the linkage to external.
	///		///
	void deleteBody() {		void deleteBody() {
	dropAllReferences();		dropAllReferences();
	setLinkage(ExternalLinkage);		setLinkage(ExternalLinkage);
	skipping to change at line 398		skipping to change at line 428
	return ArgumentList.end();		return ArgumentList.end();
	}		}
	const_arg_iterator arg_end() const {		const_arg_iterator arg_end() const {
	CheckLazyArguments();		CheckLazyArguments();
	return ArgumentList.end();		return ArgumentList.end();
	}		}
	size_t arg_size() const;		size_t arg_size() const;
	bool arg_empty() const;		bool arg_empty() const;
			bool hasPrefixData() const {
			return getSubclassDataFromValue() & 2;
			}
			Constant *getPrefixData() const;
			void setPrefixData(Constant *PrefixData);
	/// viewCFG - This function is meant for use from the debugger. You can just		/// viewCFG - This function is meant for use from the debugger. You can just
	/// say 'call F->viewCFG()' and a ghostview window should pop up from the		/// say 'call F->viewCFG()' and a ghostview window should pop up from the
	/// program, displaying the CFG of the current function with the code for each		/// program, displaying the CFG of the current function with the code for each
	/// basic block inside. This depends on there being a 'dot' and 'gv' pro gram		/// basic block inside. This depends on there being a 'dot' and 'gv' pro gram
	/// in your path.		/// in your path.
	///		///
	void viewCFG() const;		void viewCFG() const;
	/// viewCFGOnly - This function is meant for use from the debugger. It w orks		/// viewCFGOnly - This function is meant for use from the debugger. It w orks
	/// just like viewCFG, but it does not include the contents of basic bloc ks		/// just like viewCFG, but it does not include the contents of basic bloc ks
End of changes. 11 change blocks.
	12 lines changed or deleted		50 lines changed or added

	FunctionLoweringInfo.h		FunctionLoweringInfo.h
	skipping to change at line 52		skipping to change at line 52
	class MachineModuleInfo;		class MachineModuleInfo;
	class MachineRegisterInfo;		class MachineRegisterInfo;
	class TargetLowering;		class TargetLowering;
	class Value;		class Value;
	//===--------------------------------------------------------------------== =//		//===--------------------------------------------------------------------== =//
	/// FunctionLoweringInfo - This contains information that is global to a		/// FunctionLoweringInfo - This contains information that is global to a
	/// function that is used when lowering a region of the function.		/// function that is used when lowering a region of the function.
	///		///
	class FunctionLoweringInfo {		class FunctionLoweringInfo {
			const TargetMachine &TM;
	public:		public:
	const TargetLowering &TLI;
	const Function *Fn;		const Function *Fn;
	MachineFunction *MF;		MachineFunction *MF;
	MachineRegisterInfo *RegInfo;		MachineRegisterInfo *RegInfo;
	BranchProbabilityInfo *BPI;		BranchProbabilityInfo *BPI;
	/// CanLowerReturn - true iff the function's return value can be lowered to		/// CanLowerReturn - true iff the function's return value can be lowered to
	/// registers.		/// registers.
	bool CanLowerReturn;		bool CanLowerReturn;
	/// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg		/// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
	/// allocated to hold a pointer to the hidden sret parameter.		/// allocated to hold a pointer to the hidden sret parameter.
	skipping to change at line 118		skipping to change at line 118
	/// VisitedBBs - The set of basic blocks visited thus far by instruction		/// VisitedBBs - The set of basic blocks visited thus far by instruction
	/// selection.		/// selection.
	SmallPtrSet<const BasicBlock*, 4> VisitedBBs;		SmallPtrSet<const BasicBlock*, 4> VisitedBBs;
	/// PHINodesToUpdate - A list of phi instructions whose operand list will		/// PHINodesToUpdate - A list of phi instructions whose operand list will
	/// be updated after processing the current basic block.		/// be updated after processing the current basic block.
	/// TODO: This isn't per-function state, it's per-basic-block state. But		/// TODO: This isn't per-function state, it's per-basic-block state. But
	/// there's no other convenient place for it to live right now.		/// there's no other convenient place for it to live right now.
	std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;		std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
	explicit FunctionLoweringInfo(const TargetLowering &TLI);		/// If the current MBB is a landing pad, the exception pointer and except
			ion
			/// selector registers are copied into these virtual registers by
			/// SelectionDAGISel::PrepareEHLandingPad().
			unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg;
			explicit FunctionLoweringInfo(const TargetMachine &TM) : TM(TM) {}
	/// set - Initialize this FunctionLoweringInfo with the given Function		/// set - Initialize this FunctionLoweringInfo with the given Function
	/// and its associated MachineFunction.		/// and its associated MachineFunction.
	///		///
	void set(const Function &Fn, MachineFunction &MF);		void set(const Function &Fn, MachineFunction &MF);
	/// clear - Clear out all the function-specific state. This returns this		/// clear - Clear out all the function-specific state. This returns this
	/// FunctionLoweringInfo to an empty state, ready to be used for a		/// FunctionLoweringInfo to an empty state, ready to be used for a
	/// different function.		/// different function.
	void clear();		void clear();
End of changes. 3 change blocks.
	2 lines changed or deleted		8 lines changed or added

	GCOV.h		GCOV.h
	skipping to change at line 18		skipping to change at line 18
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This header provides the interface to read and write coverage files that		// This header provides the interface to read and write coverage files that
	// use 'gcov' format.		// use 'gcov' format.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_SUPPORT_GCOV_H		#ifndef LLVM_SUPPORT_GCOV_H
	#define LLVM_SUPPORT_GCOV_H		#define LLVM_SUPPORT_GCOV_H
			#include "llvm/ADT/DenseMap.h"
	#include "llvm/ADT/SmallVector.h"		#include "llvm/ADT/SmallVector.h"
	#include "llvm/ADT/StringMap.h"		#include "llvm/ADT/StringMap.h"
	#include "llvm/Support/MemoryBuffer.h"		#include "llvm/Support/MemoryBuffer.h"
	#include "llvm/Support/raw_ostream.h"		#include "llvm/Support/raw_ostream.h"
	namespace llvm {		namespace llvm {
	class GCOVFunction;		class GCOVFunction;
	class GCOVBlock;		class GCOVBlock;
	class GCOVLines;
	class FileInfo;		class FileInfo;
	namespace GCOV {		namespace GCOV {
	enum GCOVFormat {		enum GCOVFormat {
	InvalidGCOV,		InvalidGCOV,
	GCNO_402,		GCNO_402,
	GCNO_404,		GCNO_404,
	GCDA_402,		GCDA_402,
	GCDA_404		GCDA_404
	};		};
	skipping to change at line 128		skipping to change at line 128
	StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor+4);		StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor+4);
	if (Tag.empty() ||		if (Tag.empty() ||
	Tag[0] != '\0' || Tag[1] != '\0' ||		Tag[0] != '\0' || Tag[1] != '\0' ||
	Tag[2] != '\xa1' || Tag[3] != '\1') {		Tag[2] != '\xa1' || Tag[3] != '\1') {
	return false;		return false;
	}		}
	Cursor += 4;		Cursor += 4;
	return true;		return true;
	}		}
	uint32_t readInt() {		/// readObjectTag - If cursor points to an object summary tag then increm
	uint32_t Result;		ent
			/// the cursor and return true otherwise return false.
			bool readObjectTag() {
			StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor+4);
			if (Tag.empty() ||
			Tag[0] != '\0' || Tag[1] != '\0' ||
			Tag[2] != '\0' || Tag[3] != '\xa1') {
			return false;
			}
			Cursor += 4;
			return true;
			}
			/// readProgramTag - If cursor points to a program summary tag then incre
			ment
			/// the cursor and return true otherwise return false.
			bool readProgramTag() {
			StringRef Tag = Buffer->getBuffer().slice(Cursor, Cursor+4);
			if (Tag.empty() ||
			Tag[0] != '\0' || Tag[1] != '\0' ||
			Tag[2] != '\0' || Tag[3] != '\xa3') {
			return false;
			}
			Cursor += 4;
			return true;
			}
			bool readInt(uint32_t &Val) {
			if (Buffer->getBuffer().size() < Cursor+4) {
			errs() << "Unexpected end of memory buffer: " << Cursor+4 << ".\n";
			return false;
			}
	StringRef Str = Buffer->getBuffer().slice(Cursor, Cursor+4);		StringRef Str = Buffer->getBuffer().slice(Cursor, Cursor+4);
	assert (Str.empty() == false && "Unexpected memory buffer end!");
	Cursor += 4;		Cursor += 4;
	Result = *(const uint32_t *)(Str.data());		Val = *(const uint32_t *)(Str.data());
	return Result;		return true;
	}		}
	uint64_t readInt64() {		bool readInt64(uint64_t &Val) {
	uint64_t Lo = readInt();		uint32_t Lo, Hi;
	uint64_t Hi = readInt();		if (!readInt(Lo) || !readInt(Hi)) return false;
	uint64_t Result = Lo | (Hi << 32);		Val = ((uint64_t)Hi << 32) | Lo;
	return Result;		return true;
	}		}
	StringRef readString() {		bool readString(StringRef &Str) {
	uint32_t Len = readInt() * 4;		uint32_t Len;
	StringRef Str = Buffer->getBuffer().slice(Cursor, Cursor+Len);		if (!readInt(Len)) return false;
			Len *= 4;
			if (Buffer->getBuffer().size() < Cursor+Len) {
			errs() << "Unexpected end of memory buffer: " << Cursor+Len << ".\n";
			return false;
			}
			Str = Buffer->getBuffer().slice(Cursor, Cursor+Len).split('\0').first;
	Cursor += Len;		Cursor += Len;
	return Str;		return true;
	}		}
	uint64_t getCursor() const { return Cursor; }		uint64_t getCursor() const { return Cursor; }
			void advanceCursor(uint32_t n) { Cursor += n*4; }
	private:		private:
	MemoryBuffer *Buffer;		MemoryBuffer *Buffer;
	uint64_t Cursor;		uint64_t Cursor;
	};		};
	/// GCOVFile - Collects coverage information for one pair of coverage file		/// GCOVFile - Collects coverage information for one pair of coverage file
	/// (.gcno and .gcda).		/// (.gcno and .gcda).
	class GCOVFile {		class GCOVFile {
	public:		public:
	GCOVFile() {}		GCOVFile() : Functions(), RunCount(0), ProgramCount(0) {}
	~GCOVFile();		~GCOVFile();
	bool read(GCOVBuffer &Buffer);		bool read(GCOVBuffer &Buffer);
	void dump();		void dump();
	void collectLineCounts(FileInfo &FI);		void collectLineCounts(FileInfo &FI);
	private:		private:
	SmallVector<GCOVFunction *, 16> Functions;		SmallVector<GCOVFunction *, 16> Functions;
			uint32_t RunCount;
			uint32_t ProgramCount;
	};		};
	/// GCOVFunction - Collects function information.		/// GCOVFunction - Collects function information.
	class GCOVFunction {		class GCOVFunction {
	public:		public:
	GCOVFunction() : Ident(0), LineNumber(0) {}		GCOVFunction() : Ident(0), LineNumber(0) {}
	~GCOVFunction();		~GCOVFunction();
	bool read(GCOVBuffer &Buffer, GCOV::GCOVFormat Format);		bool read(GCOVBuffer &Buffer, GCOV::GCOVFormat Format);
			StringRef getFilename() const { return Filename; }
	void dump();		void dump();
	void collectLineCounts(FileInfo &FI);		void collectLineCounts(FileInfo &FI);
	private:		private:
	uint32_t Ident;		uint32_t Ident;
	uint32_t LineNumber;		uint32_t LineNumber;
	StringRef Name;		StringRef Name;
	StringRef Filename;		StringRef Filename;
	SmallVector<GCOVBlock *, 16> Blocks;		SmallVector<GCOVBlock *, 16> Blocks;
	};		};
	/// GCOVBlock - Collects block information.		/// GCOVBlock - Collects block information.
	class GCOVBlock {		class GCOVBlock {
	public:		public:
	GCOVBlock(uint32_t N) : Number(N), Counter(0) {}		GCOVBlock(GCOVFunction &P, uint32_t N) :
			Parent(P), Number(N), Counter(0), Edges(), Lines() {}
	~GCOVBlock();		~GCOVBlock();
	void addEdge(uint32_t N) { Edges.push_back(N); }		void addEdge(uint32_t N) { Edges.push_back(N); }
	void addLine(StringRef Filename, uint32_t LineNo);		void addLine(uint32_t N) { Lines.push_back(N); }
	void addCount(uint64_t N) { Counter = N; }		void addCount(uint64_t N) { Counter += N; }
			size_t getNumEdges() { return Edges.size(); }
	void dump();		void dump();
	void collectLineCounts(FileInfo &FI);		void collectLineCounts(FileInfo &FI);
	private:		private:
			GCOVFunction &Parent;
	uint32_t Number;		uint32_t Number;
	uint64_t Counter;		uint64_t Counter;
	SmallVector<uint32_t, 16> Edges;		SmallVector<uint32_t, 16> Edges;
	StringMap<GCOVLines *> Lines;		SmallVector<uint32_t, 16> Lines;
	};
	/// GCOVLines - A wrapper around a vector of int to keep track of line nos.
	class GCOVLines {
	public:
	~GCOVLines() { Lines.clear(); }
	void add(uint32_t N) { Lines.push_back(N); }
	void collectLineCounts(FileInfo &FI, StringRef Filename, uint32_t Count);
	void dump();
	private:
	SmallVector<uint32_t, 4> Lines;
	};		};
	typedef SmallVector<uint32_t, 16> LineCounts;		typedef DenseMap<uint32_t, uint64_t> LineCounts;
	class FileInfo {		class FileInfo {
	public:		public:
	void addLineCount(StringRef Filename, uint32_t Line, uint32_t Count);		void addLineCount(StringRef Filename, uint32_t Line, uint64_t Count) {
	void print();		LineInfo[Filename][Line-1] += Count;
			}
			void setRunCount(uint32_t Runs) { RunCount = Runs; }
			void setProgramCount(uint32_t Programs) { ProgramCount = Programs; }
			void print(raw_fd_ostream &OS, StringRef gcnoFile, StringRef gcdaFile);
	private:		private:
	StringMap<LineCounts> LineInfo;		StringMap<LineCounts> LineInfo;
			uint32_t RunCount;
			uint32_t ProgramCount;
	};		};
	}		}
	#endif		#endif
End of changes. 19 change blocks.
	35 lines changed or deleted		72 lines changed or added

	GVMaterializer.h		GVMaterializer.h
	skipping to change at line 21		skipping to change at line 21
	// place. This interface allows incremental or random access loading of		// place. This interface allows incremental or random access loading of
	// functions from the file. This is useful for applications like JIT compi lers		// functions from the file. This is useful for applications like JIT compi lers
	// or interprocedural optimizers that do not need the entire program in mem ory		// or interprocedural optimizers that do not need the entire program in mem ory
	// at the same time.		// at the same time.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_GVMATERIALIZER_H		#ifndef LLVM_GVMATERIALIZER_H
	#define LLVM_GVMATERIALIZER_H		#define LLVM_GVMATERIALIZER_H
	#include <string>		#include "llvm/Support/system_error.h"
	namespace llvm {		namespace llvm {
	class Function;		class Function;
	class GlobalValue;		class GlobalValue;
	class Module;		class Module;
	class GVMaterializer {		class GVMaterializer {
	protected:		protected:
	GVMaterializer() {}		GVMaterializer() {}
	skipping to change at line 44		skipping to change at line 44
	virtual ~GVMaterializer();		virtual ~GVMaterializer();
	/// isMaterializable - True if GV can be materialized from whatever backi ng		/// isMaterializable - True if GV can be materialized from whatever backi ng
	/// store this GVMaterializer uses and has not been materialized yet.		/// store this GVMaterializer uses and has not been materialized yet.
	virtual bool isMaterializable(const GlobalValue *GV) const = 0;		virtual bool isMaterializable(const GlobalValue *GV) const = 0;
	/// isDematerializable - True if GV has been materialized and can be		/// isDematerializable - True if GV has been materialized and can be
	/// dematerialized back to whatever backing store this GVMaterializer use s.		/// dematerialized back to whatever backing store this GVMaterializer use s.
	virtual bool isDematerializable(const GlobalValue *GV) const = 0;		virtual bool isDematerializable(const GlobalValue *GV) const = 0;
	/// Materialize - make sure the given GlobalValue is fully read. If the		/// Materialize - make sure the given GlobalValue is fully read.
	/// module is corrupt, this returns true and fills in the optional string
	with
	/// information about the problem. If successful, this returns false.
	///		///
	virtual bool Materialize(GlobalValue *GV, std::string *ErrInfo = 0) = 0;		virtual error_code Materialize(GlobalValue *GV) = 0;
	/// Dematerialize - If the given GlobalValue is read in, and if the		/// Dematerialize - If the given GlobalValue is read in, and if the
	/// GVMaterializer supports it, release the memory for the GV, and set it up		/// GVMaterializer supports it, release the memory for the GV, and set it up
	/// to be materialized lazily. If the Materializer doesn't support this		/// to be materialized lazily. If the Materializer doesn't support this
	/// capability, this method is a noop.		/// capability, this method is a noop.
	///		///
	virtual void Dematerialize(GlobalValue *) {}		virtual void Dematerialize(GlobalValue *) {}
	/// MaterializeModule - make sure the entire Module has been completely r ead.		/// MaterializeModule - make sure the entire Module has been completely r ead.
	/// On error, this returns true and fills in the optional string with
	/// information about the problem. If successful, this returns false.
	///		///
	virtual bool MaterializeModule(Module *M, std::string *ErrInfo = 0) = 0;		virtual error_code MaterializeModule(Module *M) = 0;
	};		};
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 5 change blocks.
	9 lines changed or deleted		4 lines changed or added

	GetElementPtrTypeIterator.h		GetElementPtrTypeIterator.h
	skipping to change at line 108		skipping to change at line 108
	}		}
	template<typename T>		template<typename T>
	inline generic_gep_type_iterator<const T *>		inline generic_gep_type_iterator<const T *>
	gep_type_begin(Type *Op0, ArrayRef<T> A) {		gep_type_begin(Type *Op0, ArrayRef<T> A) {
	return generic_gep_type_iterator<const T *>::begin(Op0, A.begin());		return generic_gep_type_iterator<const T *>::begin(Op0, A.begin());
	}		}
	template<typename T>		template<typename T>
	inline generic_gep_type_iterator<const T *>		inline generic_gep_type_iterator<const T *>
	gep_type_end(Type *Op0, ArrayRef<T> A) {		gep_type_end(Type * /*Op0*/, ArrayRef<T> A) {
	return generic_gep_type_iterator<const T *>::end(A.end());		return generic_gep_type_iterator<const T *>::end(A.end());
	}		}
	} // end namespace llvm		} // end namespace llvm
	#endif		#endif
End of changes. 1 change blocks.
	1 lines changed or deleted		1 lines changed or added

	GlobalAlias.h		GlobalAlias.h
	skipping to change at line 69		skipping to change at line 69
	/// set/getAliasee - These methods retrive and set alias target.		/// set/getAliasee - These methods retrive and set alias target.
	void setAliasee(Constant *GV);		void setAliasee(Constant *GV);
	const Constant *getAliasee() const {		const Constant *getAliasee() const {
	return getOperand(0);		return getOperand(0);
	}		}
	Constant *getAliasee() {		Constant *getAliasee() {
	return getOperand(0);		return getOperand(0);
	}		}
	/// getAliasedGlobal() - Aliasee can be either global or bitcast of		/// getAliasedGlobal() - Aliasee can be either global or bitcast of
	/// global. This method retrives the global for both aliasee flavours.		/// global. This method retrives the global for both aliasee flavours.
	const GlobalValue *getAliasedGlobal() const;		GlobalValue *getAliasedGlobal();
			const GlobalValue *getAliasedGlobal() const {
			return const_cast<GlobalAlias *>(this)->getAliasedGlobal();
			}
	/// resolveAliasedGlobal() - This method tries to ultimately resolve the alias		/// resolveAliasedGlobal() - This method tries to ultimately resolve the alias
	/// by going through the aliasing chain and trying to find the very last		/// by going through the aliasing chain and trying to find the very last
	/// global. Returns NULL if a cycle was found. If stopOnWeak is false, th en		/// global. Returns NULL if a cycle was found. If stopOnWeak is false, th en
	/// the whole chain aliasing chain is traversed, otherwise - only strong		/// the whole chain aliasing chain is traversed, otherwise - only strong
	/// aliases.		/// aliases.
	const GlobalValue *resolveAliasedGlobal(bool stopOnWeak = true) const;		GlobalValue *resolveAliasedGlobal(bool stopOnWeak = true);
			const GlobalValue *resolveAliasedGlobal(bool stopOnWeak = true) const {
			return const_cast<GlobalAlias *>(this)->resolveAliasedGlobal(stopOnWeak
			);
			}
			static bool isValidLinkage(LinkageTypes L) {
			return isExternalLinkage(L) || isLocalLinkage(L) ||
			isWeakLinkage(L) || isLinkOnceLinkage(L);
			}
	// Methods for support type inquiry through isa, cast, and dyn_cast:		// Methods for support type inquiry through isa, cast, and dyn_cast:
	static inline bool classof(const Value *V) {		static inline bool classof(const Value *V) {
	return V->getValueID() == Value::GlobalAliasVal;		return V->getValueID() == Value::GlobalAliasVal;
	}		}
	};		};
	template <>		template <>
	struct OperandTraits<GlobalAlias> :		struct OperandTraits<GlobalAlias> :
	public FixedNumOperandTraits<GlobalAlias, 1> {		public FixedNumOperandTraits<GlobalAlias, 1> {
End of changes. 2 change blocks.
	2 lines changed or deleted		14 lines changed or added

	GlobalValue.h		GlobalValue.h
	skipping to change at line 38		skipping to change at line 38
	class GlobalValue : public Constant {		class GlobalValue : public Constant {
	GlobalValue(const GlobalValue &) LLVM_DELETED_FUNCTION;		GlobalValue(const GlobalValue &) LLVM_DELETED_FUNCTION;
	public:		public:
	/// @brief An enumeration for the kinds of linkage for global values.		/// @brief An enumeration for the kinds of linkage for global values.
	enum LinkageTypes {		enum LinkageTypes {
	ExternalLinkage = 0,///< Externally visible function		ExternalLinkage = 0,///< Externally visible function
	AvailableExternallyLinkage, ///< Available for inspection, not emission .		AvailableExternallyLinkage, ///< Available for inspection, not emission .
	LinkOnceAnyLinkage, ///< Keep one copy of function when linking (inline )		LinkOnceAnyLinkage, ///< Keep one copy of function when linking (inline )
	LinkOnceODRLinkage, ///< Same, but only replaced by something equivalen t.		LinkOnceODRLinkage, ///< Same, but only replaced by something equivalen t.
	LinkOnceODRAutoHideLinkage, ///< Like LinkOnceODRLinkage but addr not t aken.
	WeakAnyLinkage, ///< Keep one copy of named function when linking ( weak)		WeakAnyLinkage, ///< Keep one copy of named function when linking ( weak)
	WeakODRLinkage, ///< Same, but only replaced by something equivalen t.		WeakODRLinkage, ///< Same, but only replaced by something equivalen t.
	AppendingLinkage, ///< Special purpose, only applies to global arrays		AppendingLinkage, ///< Special purpose, only applies to global arrays
	InternalLinkage, ///< Rename collisions when linking (static functio ns).		InternalLinkage, ///< Rename collisions when linking (static functio ns).
	PrivateLinkage, ///< Like Internal, but omit from symbol table.		PrivateLinkage, ///< Like Internal, but omit from symbol table.
	LinkerPrivateLinkage, ///< Like Private, but linker removes.		LinkerPrivateLinkage, ///< Like Private, but linker removes.
	LinkerPrivateWeakLinkage, ///< Like LinkerPrivate, but weak.		LinkerPrivateWeakLinkage, ///< Like LinkerPrivate, but weak.
	DLLImportLinkage, ///< Function to be imported from DLL		DLLImportLinkage, ///< Function to be imported from DLL
	DLLExportLinkage, ///< Function to be accessible from DLL.		DLLExportLinkage, ///< Function to be accessible from DLL.
	ExternalWeakLinkage,///< ExternalWeak linkage description.		ExternalWeakLinkage,///< ExternalWeak linkage description.
	skipping to change at line 126		skipping to change at line 125
	return ODR ? WeakODRLinkage : WeakAnyLinkage;		return ODR ? WeakODRLinkage : WeakAnyLinkage;
	}		}
	static bool isExternalLinkage(LinkageTypes Linkage) {		static bool isExternalLinkage(LinkageTypes Linkage) {
	return Linkage == ExternalLinkage;		return Linkage == ExternalLinkage;
	}		}
	static bool isAvailableExternallyLinkage(LinkageTypes Linkage) {		static bool isAvailableExternallyLinkage(LinkageTypes Linkage) {
	return Linkage == AvailableExternallyLinkage;		return Linkage == AvailableExternallyLinkage;
	}		}
	static bool isLinkOnceLinkage(LinkageTypes Linkage) {		static bool isLinkOnceLinkage(LinkageTypes Linkage) {
	return Linkage == LinkOnceAnyLinkage ||		return Linkage == LinkOnceAnyLinkage || Linkage == LinkOnceODRLinkage;
	Linkage == LinkOnceODRLinkage ||
	Linkage == LinkOnceODRAutoHideLinkage;
	}
	static bool isLinkOnceODRAutoHideLinkage(LinkageTypes Linkage) {
	return Linkage == LinkOnceODRAutoHideLinkage;
	}		}
	static bool isWeakLinkage(LinkageTypes Linkage) {		static bool isWeakLinkage(LinkageTypes Linkage) {
	return Linkage == WeakAnyLinkage || Linkage == WeakODRLinkage;		return Linkage == WeakAnyLinkage || Linkage == WeakODRLinkage;
	}		}
	static bool isAppendingLinkage(LinkageTypes Linkage) {		static bool isAppendingLinkage(LinkageTypes Linkage) {
	return Linkage == AppendingLinkage;		return Linkage == AppendingLinkage;
	}		}
	static bool isInternalLinkage(LinkageTypes Linkage) {		static bool isInternalLinkage(LinkageTypes Linkage) {
	return Linkage == InternalLinkage;		return Linkage == InternalLinkage;
	}		}
	skipping to change at line 195		skipping to change at line 189
	/// isWeakForLinker - Whether the definition of this global may be replac ed at		/// isWeakForLinker - Whether the definition of this global may be replac ed at
	/// link time. NB: Using this method outside of the code generators is a lmost		/// link time. NB: Using this method outside of the code generators is a lmost
	/// always a mistake: when working at the IR level use mayBeOverridden in stead		/// always a mistake: when working at the IR level use mayBeOverridden in stead
	/// as it knows about ODR semantics.		/// as it knows about ODR semantics.
	static bool isWeakForLinker(LinkageTypes Linkage) {		static bool isWeakForLinker(LinkageTypes Linkage) {
	return Linkage == AvailableExternallyLinkage ||		return Linkage == AvailableExternallyLinkage ||
	Linkage == WeakAnyLinkage ||		Linkage == WeakAnyLinkage ||
	Linkage == WeakODRLinkage ||		Linkage == WeakODRLinkage ||
	Linkage == LinkOnceAnyLinkage ||		Linkage == LinkOnceAnyLinkage ||
	Linkage == LinkOnceODRLinkage ||		Linkage == LinkOnceODRLinkage ||
	Linkage == LinkOnceODRAutoHideLinkage ||
	Linkage == CommonLinkage ||		Linkage == CommonLinkage ||
	Linkage == ExternalWeakLinkage ||		Linkage == ExternalWeakLinkage ||
	Linkage == LinkerPrivateWeakLinkage;		Linkage == LinkerPrivateWeakLinkage;
	}		}
	bool hasExternalLinkage() const { return isExternalLinkage(Linkage); }		bool hasExternalLinkage() const { return isExternalLinkage(Linkage); }
	bool hasAvailableExternallyLinkage() const {		bool hasAvailableExternallyLinkage() const {
	return isAvailableExternallyLinkage(Linkage);		return isAvailableExternallyLinkage(Linkage);
	}		}
	bool hasLinkOnceLinkage() const {		bool hasLinkOnceLinkage() const {
	return isLinkOnceLinkage(Linkage);		return isLinkOnceLinkage(Linkage);
	}		}
	bool hasLinkOnceODRAutoHideLinkage() const {
	return isLinkOnceODRAutoHideLinkage(Linkage);
	}
	bool hasWeakLinkage() const {		bool hasWeakLinkage() const {
	return isWeakLinkage(Linkage);		return isWeakLinkage(Linkage);
	}		}
	bool hasAppendingLinkage() const { return isAppendingLinkage(Linkage); }		bool hasAppendingLinkage() const { return isAppendingLinkage(Linkage); }
	bool hasInternalLinkage() const { return isInternalLinkage(Linkage); }		bool hasInternalLinkage() const { return isInternalLinkage(Linkage); }
	bool hasPrivateLinkage() const { return isPrivateLinkage(Linkage); }		bool hasPrivateLinkage() const { return isPrivateLinkage(Linkage); }
	bool hasLinkerPrivateLinkage() const { return isLinkerPrivateLinkage(Link age); }		bool hasLinkerPrivateLinkage() const { return isLinkerPrivateLinkage(Link age); }
	bool hasLinkerPrivateWeakLinkage() const {		bool hasLinkerPrivateWeakLinkage() const {
	return isLinkerPrivateWeakLinkage(Linkage);		return isLinkerPrivateWeakLinkage(Linkage);
	}		}
	skipping to change at line 242		skipping to change at line 232
	}		}
	bool mayBeOverridden() const { return mayBeOverridden(Linkage); }		bool mayBeOverridden() const { return mayBeOverridden(Linkage); }
	bool isWeakForLinker() const { return isWeakForLinker(Linkage); }		bool isWeakForLinker() const { return isWeakForLinker(Linkage); }
	/// copyAttributesFrom - copy all additional attributes (those not needed to		/// copyAttributesFrom - copy all additional attributes (those not needed to
	/// create a GlobalValue) from the GlobalValue Src to this one.		/// create a GlobalValue) from the GlobalValue Src to this one.
	virtual void copyAttributesFrom(const GlobalValue *Src);		virtual void copyAttributesFrom(const GlobalValue *Src);
			/// getRealLinkageName - If special LLVM prefix that is used to inform th
			e asm
			/// printer to not emit usual symbol prefix before the symbol name is use
			d
			/// then return linkage name after skipping this special LLVM prefix.
			static StringRef getRealLinkageName(StringRef Name) {
			if (!Name.empty() && Name[0] == '\1')
			return Name.substr(1);
			return Name;
			}
	/// @name Materialization		/// @name Materialization
	/// Materialization is used to construct functions only as they're needed. This		/// Materialization is used to construct functions only as they're needed. This
	/// is useful to reduce memory usage in LLVM or parsing work done by the		/// is useful to reduce memory usage in LLVM or parsing work done by the
	/// BitcodeReader to load the Module.		/// BitcodeReader to load the Module.
	/// @{		/// @{
	/// isMaterializable - If this function's Module is being lazily streamed in		/// isMaterializable - If this function's Module is being lazily streamed in
	/// functions from disk or some other source, this method can be used to check		/// functions from disk or some other source, this method can be used to check
	/// to see if the function has been read in yet or not.		/// to see if the function has been read in yet or not.
	bool isMaterializable() const;		bool isMaterializable() const;
End of changes. 5 change blocks.
	11 lines changed or deleted		12 lines changed or added

	GlobalVariable.h		GlobalVariable.h
	skipping to change at line 87		skipping to change at line 87
	ThreadLocalMode = NotThreadLocal, unsigned AddressSpace = 0,		ThreadLocalMode = NotThreadLocal, unsigned AddressSpace = 0,
	bool isExternallyInitialized = false);		bool isExternallyInitialized = false);
	~GlobalVariable() {		~GlobalVariable() {
	NumOperands = 1; // FIXME: needed by operator delete		NumOperands = 1; // FIXME: needed by operator delete
	}		}
	/// Provide fast operand accessors		/// Provide fast operand accessors
	DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);		DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
	/// hasInitializer - Unless a global variable isExternal(), it has an		/// Definitions have initializers, declarations don't.
	/// initializer. The initializer for the global variable/constant is hel
	d by
	/// Initializer if an initializer is specified.
	///		///
	inline bool hasInitializer() const { return !isDeclaration(); }		inline bool hasInitializer() const { return !isDeclaration(); }
	/// hasDefinitiveInitializer - Whether the global variable has an initial izer,		/// hasDefinitiveInitializer - Whether the global variable has an initial izer,
	/// and any other instances of the global (this can happen due to weak		/// and any other instances of the global (this can happen due to weak
	/// linkage) are guaranteed to have the same initializer.		/// linkage) are guaranteed to have the same initializer.
	///		///
	/// Note that if you want to transform a global, you must use		/// Note that if you want to transform a global, you must use
	/// hasUniqueInitializer() instead, because of the *_odr linkage type.		/// hasUniqueInitializer() instead, because of the *_odr linkage type.
	///		///
End of changes. 1 change blocks.
	4 lines changed or deleted		1 lines changed or added

	Graph.h		Graph.h
	skipping to change at line 22		skipping to change at line 22
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_CODEGEN_PBQP_GRAPH_H		#ifndef LLVM_CODEGEN_PBQP_GRAPH_H
	#define LLVM_CODEGEN_PBQP_GRAPH_H		#define LLVM_CODEGEN_PBQP_GRAPH_H
	#include "Math.h"		#include "Math.h"
	#include "llvm/ADT/ilist.h"		#include "llvm/ADT/ilist.h"
	#include "llvm/ADT/ilist_node.h"		#include "llvm/ADT/ilist_node.h"
	#include <list>		#include <list>
	#include <map>		#include <map>
			#include <set>
	namespace PBQP {		namespace PBQP {
	/// PBQP Graph class.		/// PBQP Graph class.
	/// Instances of this class describe PBQP problems.		/// Instances of this class describe PBQP problems.
	class Graph {		class Graph {
	private:
	// ----- TYPEDEFS -----
	class NodeEntry;
	class EdgeEntry;
	typedef llvm::ilist<NodeEntry> NodeList;
	typedef llvm::ilist<EdgeEntry> EdgeList;
	public:		public:
	typedef NodeEntry* NodeItr;		typedef unsigned NodeId;
	typedef const NodeEntry* ConstNodeItr;		typedef unsigned EdgeId;
	typedef EdgeEntry* EdgeItr;
	typedef const EdgeEntry* ConstEdgeItr;
	private:		private:
	typedef std::list<EdgeItr> AdjEdgeList;		typedef std::set<NodeId> AdjEdgeList;
	public:		public:
	typedef AdjEdgeList::iterator AdjEdgeItr;		typedef AdjEdgeList::iterator AdjEdgeItr;
	private:		private:
	class NodeEntry : public llvm::ilist_node<NodeEntry> {		class NodeEntry {
	friend struct llvm::ilist_sentinel_traits<NodeEntry>;
	private:		private:
	Vector costs;		Vector costs;
	AdjEdgeList adjEdges;		AdjEdgeList adjEdges;
	unsigned degree;
	void *data;		void *data;
	NodeEntry() : costs(0, 0) {}		NodeEntry() : costs(0, 0) {}
	public:		public:
	NodeEntry(const Vector &costs) : costs(costs), degree(0) {}		NodeEntry(const Vector &costs) : costs(costs), data(0) {}
	Vector& getCosts() { return costs; }		Vector& getCosts() { return costs; }
	const Vector& getCosts() const { return costs; }		const Vector& getCosts() const { return costs; }
	unsigned getDegree() const { return degree; }		unsigned getDegree() const { return adjEdges.size(); }
	AdjEdgeItr edgesBegin() { return adjEdges.begin(); }		AdjEdgeItr edgesBegin() { return adjEdges.begin(); }
	AdjEdgeItr edgesEnd() { return adjEdges.end(); }		AdjEdgeItr edgesEnd() { return adjEdges.end(); }
	AdjEdgeItr addEdge(EdgeItr e) {		AdjEdgeItr addEdge(EdgeId e) {
	++degree;
	return adjEdges.insert(adjEdges.end(), e);		return adjEdges.insert(adjEdges.end(), e);
	}		}
	void removeEdge(AdjEdgeItr ae) {		void removeEdge(AdjEdgeItr ae) {
	--degree;
	adjEdges.erase(ae);		adjEdges.erase(ae);
	}		}
	void setData(void *data) { this->data = data; }		void setData(void *data) { this->data = data; }
	void* getData() { return data; }		void* getData() { return data; }
	};		};
	class EdgeEntry : public llvm::ilist_node<EdgeEntry> {		class EdgeEntry {
	friend struct llvm::ilist_sentinel_traits<EdgeEntry>;
	private:		private:
	NodeItr node1, node2;		NodeId node1, node2;
	Matrix costs;		Matrix costs;
	AdjEdgeItr node1AEItr, node2AEItr;		AdjEdgeItr node1AEItr, node2AEItr;
	void *data;		void *data;
	EdgeEntry() : costs(0, 0, 0) {}		EdgeEntry() : costs(0, 0, 0), data(0) {}
	public:		public:
	EdgeEntry(NodeItr node1, NodeItr node2, const Matrix &costs)		EdgeEntry(NodeId node1, NodeId node2, const Matrix &costs)
	: node1(node1), node2(node2), costs(costs) {}		: node1(node1), node2(node2), costs(costs) {}
	NodeItr getNode1() const { return node1; }		NodeId getNode1() const { return node1; }
	NodeItr getNode2() const { return node2; }		NodeId getNode2() const { return node2; }
	Matrix& getCosts() { return costs; }		Matrix& getCosts() { return costs; }
	const Matrix& getCosts() const { return costs; }		const Matrix& getCosts() const { return costs; }
	void setNode1AEItr(AdjEdgeItr ae) { node1AEItr = ae; }		void setNode1AEItr(AdjEdgeItr ae) { node1AEItr = ae; }
	AdjEdgeItr getNode1AEItr() { return node1AEItr; }		AdjEdgeItr getNode1AEItr() { return node1AEItr; }
	void setNode2AEItr(AdjEdgeItr ae) { node2AEItr = ae; }		void setNode2AEItr(AdjEdgeItr ae) { node2AEItr = ae; }
	AdjEdgeItr getNode2AEItr() { return node2AEItr; }		AdjEdgeItr getNode2AEItr() { return node2AEItr; }
	void setData(void *data) { this->data = data; }		void setData(void *data) { this->data = data; }
	void *getData() { return data; }		void *getData() { return data; }
	};		};
	// ----- MEMBERS -----		// ----- MEMBERS -----
	NodeList nodes;		typedef std::vector<NodeEntry> NodeVector;
	unsigned numNodes;		typedef std::vector<NodeId> FreeNodeVector;
			NodeVector nodes;
	EdgeList edges;		FreeNodeVector freeNodes;
	unsigned numEdges;
			typedef std::vector<EdgeEntry> EdgeVector;
			typedef std::vector<EdgeId> FreeEdgeVector;
			EdgeVector edges;
			FreeEdgeVector freeEdges;
	// ----- INTERNAL METHODS -----		// ----- INTERNAL METHODS -----
	NodeEntry& getNode(NodeItr nItr) { return *nItr; }		NodeEntry& getNode(NodeId nId) { return nodes[nId]; }
	const NodeEntry& getNode(ConstNodeItr nItr) const { return *nItr; }		const NodeEntry& getNode(NodeId nId) const { return nodes[nId]; }
	EdgeEntry& getEdge(EdgeItr eItr) { return *eItr; }		EdgeEntry& getEdge(EdgeId eId) { return edges[eId]; }
	const EdgeEntry& getEdge(ConstEdgeItr eItr) const { return *eItr; }		const EdgeEntry& getEdge(EdgeId eId) const { return edges[eId]; }
	NodeItr addConstructedNode(const NodeEntry &n) {		NodeId addConstructedNode(const NodeEntry &n) {
	++numNodes;		NodeId nodeId = 0;
	return nodes.insert(nodes.end(), n);		if (!freeNodes.empty()) {
			nodeId = freeNodes.back();
			freeNodes.pop_back();
			nodes[nodeId] = n;
			} else {
			nodeId = nodes.size();
			nodes.push_back(n);
			}
			return nodeId;
	}		}
	EdgeItr addConstructedEdge(const EdgeEntry &e) {		EdgeId addConstructedEdge(const EdgeEntry &e) {
	assert(findEdge(e.getNode1(), e.getNode2()) == edges.end() &&		assert(findEdge(e.getNode1(), e.getNode2()) == invalidEdgeId() &&
	"Attempt to add duplicate edge.");		"Attempt to add duplicate edge.");
	++numEdges;		EdgeId edgeId = 0;
	EdgeItr edgeItr = edges.insert(edges.end(), e);		if (!freeEdges.empty()) {
	EdgeEntry &ne = getEdge(edgeItr);		edgeId = freeEdges.back();
			freeEdges.pop_back();
			edges[edgeId] = e;
			} else {
			edgeId = edges.size();
			edges.push_back(e);
			}
			EdgeEntry &ne = getEdge(edgeId);
	NodeEntry &n1 = getNode(ne.getNode1());		NodeEntry &n1 = getNode(ne.getNode1());
	NodeEntry &n2 = getNode(ne.getNode2());		NodeEntry &n2 = getNode(ne.getNode2());
	// Sanity check on matrix dimensions:		// Sanity check on matrix dimensions:
	assert((n1.getCosts().getLength() == ne.getCosts().getRows()) &&		assert((n1.getCosts().getLength() == ne.getCosts().getRows()) &&
	(n2.getCosts().getLength() == ne.getCosts().getCols()) &&		(n2.getCosts().getLength() == ne.getCosts().getCols()) &&
	"Edge cost dimensions do not match node costs dimensions.");		"Edge cost dimensions do not match node costs dimensions.");
	ne.setNode1AEItr(n1.addEdge(edgeItr));
	ne.setNode2AEItr(n2.addEdge(edgeItr));		ne.setNode1AEItr(n1.addEdge(edgeId));
	return edgeItr;		ne.setNode2AEItr(n2.addEdge(edgeId));
			return edgeId;
	}		}
	inline void copyFrom(const Graph &other);		Graph(const Graph &other) {}
			void operator=(const Graph &other) {}
	public:		public:
	/// \brief Construct an empty PBQP graph.		class NodeItr {
	Graph() : numNodes(0), numEdges(0) {}		public:
			NodeItr(NodeId nodeId, const Graph &g)
			: nodeId(nodeId), endNodeId(g.nodes.size()), freeNodes(g.freeNodes)
			{
			this->nodeId = findNextInUse(nodeId); // Move to the first in-use n
			odeId
			}
	/// \brief Copy construct this graph from "other". Note: Does not copy		bool operator==(const NodeItr& n) const { return nodeId == n.nodeId;
	node		}
	/// and edge data, only graph structure and costs.		bool operator!=(const NodeItr& n) const { return !(*this == n); }
	/// @param other Source graph to copy from.		NodeItr& operator++() { nodeId = findNextInUse(++nodeId); return *thi
	Graph(const Graph &other) : numNodes(0), numEdges(0) {		s; }
	copyFrom(other);		NodeId operator*() const { return nodeId; }
	}
	/// \brief Make this graph a copy of "other". Note: Does not copy node		private:
	and		NodeId findNextInUse(NodeId n) const {
	/// edge data, only graph structure and costs.		while (n < endNodeId &&
	/// @param other The graph to copy from.		std::find(freeNodes.begin(), freeNodes.end(), n) !=
	/// @return A reference to this graph.		freeNodes.end()) {
	///		++n;
	/// This will clear the current graph, erasing any nodes and edges adde		}
	d,		return n;
	/// before copying from other.		}
	Graph& operator=(const Graph &other) {
	clear();		NodeId nodeId, endNodeId;
	copyFrom(other);		const FreeNodeVector& freeNodes;
	return *this;		};
	}
			class EdgeItr {
			public:
			EdgeItr(EdgeId edgeId, const Graph &g)
			: edgeId(edgeId), endEdgeId(g.edges.size()), freeEdges(g.freeEdges)
			{
			this->edgeId = findNextInUse(edgeId); // Move to the first in-use e
			dgeId
			}
			bool operator==(const EdgeItr& n) const { return edgeId == n.edgeId;
			}
			bool operator!=(const EdgeItr& n) const { return !(*this == n); }
			EdgeItr& operator++() { edgeId = findNextInUse(++edgeId); return *thi
			s; }
			EdgeId operator*() const { return edgeId; }
			private:
			EdgeId findNextInUse(EdgeId n) const {
			while (n < endEdgeId &&
			std::find(freeEdges.begin(), freeEdges.end(), n) !=
			freeEdges.end()) {
			++n;
			}
			return n;
			}
			EdgeId edgeId, endEdgeId;
			const FreeEdgeVector& freeEdges;
			};
			/// \brief Construct an empty PBQP graph.
			Graph() {}
	/// \brief Add a node with the given costs.		/// \brief Add a node with the given costs.
	/// @param costs Cost vector for the new node.		/// @param costs Cost vector for the new node.
	/// @return Node iterator for the added node.		/// @return Node iterator for the added node.
	NodeItr addNode(const Vector &costs) {		NodeId addNode(const Vector &costs) {
	return addConstructedNode(NodeEntry(costs));		return addConstructedNode(NodeEntry(costs));
	}		}
	/// \brief Add an edge between the given nodes with the given costs.		/// \brief Add an edge between the given nodes with the given costs.
	/// @param n1Itr First node.		/// @param n1Id First node.
	/// @param n2Itr Second node.		/// @param n2Id Second node.
	/// @return Edge iterator for the added edge.		/// @return Edge iterator for the added edge.
	EdgeItr addEdge(Graph::NodeItr n1Itr, Graph::NodeItr n2Itr,		EdgeId addEdge(NodeId n1Id, NodeId n2Id, const Matrix &costs) {
	const Matrix &costs) {		assert(getNodeCosts(n1Id).getLength() == costs.getRows() &&
	assert(getNodeCosts(n1Itr).getLength() == costs.getRows() &&		getNodeCosts(n2Id).getLength() == costs.getCols() &&
	getNodeCosts(n2Itr).getLength() == costs.getCols() &&
	"Matrix dimensions mismatch.");		"Matrix dimensions mismatch.");
	return addConstructedEdge(EdgeEntry(n1Itr, n2Itr, costs));		return addConstructedEdge(EdgeEntry(n1Id, n2Id, costs));
	}		}
	/// \brief Get the number of nodes in the graph.		/// \brief Get the number of nodes in the graph.
	/// @return Number of nodes in the graph.		/// @return Number of nodes in the graph.
	unsigned getNumNodes() const { return numNodes; }		unsigned getNumNodes() const { return nodes.size() - freeNodes.size(); }
	/// \brief Get the number of edges in the graph.		/// \brief Get the number of edges in the graph.
	/// @return Number of edges in the graph.		/// @return Number of edges in the graph.
	unsigned getNumEdges() const { return numEdges; }		unsigned getNumEdges() const { return edges.size() - freeEdges.size(); }
	/// \brief Get a node's cost vector.		/// \brief Get a node's cost vector.
	/// @param nItr Node iterator.		/// @param nId Node id.
	/// @return Node cost vector.		/// @return Node cost vector.
	Vector& getNodeCosts(NodeItr nItr) { return getNode(nItr).getCosts(); }		Vector& getNodeCosts(NodeId nId) { return getNode(nId).getCosts(); }
	/// \brief Get a node's cost vector (const version).		/// \brief Get a node's cost vector (const version).
	/// @param nItr Node iterator.		/// @param nId Node id.
	/// @return Node cost vector.		/// @return Node cost vector.
	const Vector& getNodeCosts(ConstNodeItr nItr) const {		const Vector& getNodeCosts(NodeId nId) const {
	return getNode(nItr).getCosts();		return getNode(nId).getCosts();
	}		}
	/// \brief Set a node's data pointer.		/// \brief Set a node's data pointer.
	/// @param nItr Node iterator.		/// @param nId Node id.
	/// @param data Pointer to node data.		/// @param data Pointer to node data.
	///		///
	/// Typically used by a PBQP solver to attach data to aid in solution.		/// Typically used by a PBQP solver to attach data to aid in solution.
	void setNodeData(NodeItr nItr, void *data) { getNode(nItr).setData(data ); }		void setNodeData(NodeId nId, void *data) { getNode(nId).setData(data); }
	/// \brief Get the node's data pointer.		/// \brief Get the node's data pointer.
	/// @param nItr Node iterator.		/// @param nId Node id.
	/// @return Pointer to node data.		/// @return Pointer to node data.
	void* getNodeData(NodeItr nItr) { return getNode(nItr).getData(); }		void* getNodeData(NodeId nId) { return getNode(nId).getData(); }
	/// \brief Get an edge's cost matrix.		/// \brief Get an edge's cost matrix.
	/// @param eItr Edge iterator.		/// @param eId Edge id.
	/// @return Edge cost matrix.		/// @return Edge cost matrix.
	Matrix& getEdgeCosts(EdgeItr eItr) { return getEdge(eItr).getCosts(); }		Matrix& getEdgeCosts(EdgeId eId) { return getEdge(eId).getCosts(); }
	/// \brief Get an edge's cost matrix (const version).		/// \brief Get an edge's cost matrix (const version).
	/// @param eItr Edge iterator.		/// @param eId Edge id.
	/// @return Edge cost matrix.		/// @return Edge cost matrix.
	const Matrix& getEdgeCosts(ConstEdgeItr eItr) const {		const Matrix& getEdgeCosts(EdgeId eId) const {
	return getEdge(eItr).getCosts();		return getEdge(eId).getCosts();
	}		}
	/// \brief Set an edge's data pointer.		/// \brief Set an edge's data pointer.
	/// @param eItr Edge iterator.		/// @param eId Edge id.
	/// @param data Pointer to edge data.		/// @param data Pointer to edge data.
	///		///
	/// Typically used by a PBQP solver to attach data to aid in solution.		/// Typically used by a PBQP solver to attach data to aid in solution.
	void setEdgeData(EdgeItr eItr, void *data) { getEdge(eItr).setData(data ); }		void setEdgeData(EdgeId eId, void *data) { getEdge(eId).setData(data); }
	/// \brief Get an edge's data pointer.		/// \brief Get an edge's data pointer.
	/// @param eItr Edge iterator.		/// @param eId Edge id.
	/// @return Pointer to edge data.		/// @return Pointer to edge data.
	void* getEdgeData(EdgeItr eItr) { return getEdge(eItr).getData(); }		void* getEdgeData(EdgeId eId) { return getEdge(eId).getData(); }
	/// \brief Get a node's degree.		/// \brief Get a node's degree.
	/// @param nItr Node iterator.		/// @param nId Node id.
	/// @return The degree of the node.		/// @return The degree of the node.
	unsigned getNodeDegree(NodeItr nItr) const {		unsigned getNodeDegree(NodeId nId) const {
	return getNode(nItr).getDegree();		return getNode(nId).getDegree();
	}		}
	/// \brief Begin iterator for node set.		/// \brief Begin iterator for node set.
	NodeItr nodesBegin() { return nodes.begin(); }		NodeItr nodesBegin() const { return NodeItr(0, *this); }
	/// \brief Begin const iterator for node set.
	ConstNodeItr nodesBegin() const { return nodes.begin(); }
	/// \brief End iterator for node set.		/// \brief End iterator for node set.
	NodeItr nodesEnd() { return nodes.end(); }		NodeItr nodesEnd() const { return NodeItr(nodes.size(), *this); }
	/// \brief End const iterator for node set.
	ConstNodeItr nodesEnd() const { return nodes.end(); }
	/// \brief Begin iterator for edge set.		/// \brief Begin iterator for edge set.
	EdgeItr edgesBegin() { return edges.begin(); }		EdgeItr edgesBegin() const { return EdgeItr(0, *this); }
	/// \brief End iterator for edge set.		/// \brief End iterator for edge set.
	EdgeItr edgesEnd() { return edges.end(); }		EdgeItr edgesEnd() const { return EdgeItr(edges.size(), *this); }
	/// \brief Get begin iterator for adjacent edge set.		/// \brief Get begin iterator for adjacent edge set.
	/// @param nItr Node iterator.		/// @param nId Node id.
	/// @return Begin iterator for the set of edges connected to the given node.		/// @return Begin iterator for the set of edges connected to the given node.
	AdjEdgeItr adjEdgesBegin(NodeItr nItr) {		AdjEdgeItr adjEdgesBegin(NodeId nId) {
	return getNode(nItr).edgesBegin();		return getNode(nId).edgesBegin();
	}		}
	/// \brief Get end iterator for adjacent edge set.		/// \brief Get end iterator for adjacent edge set.
	/// @param nItr Node iterator.		/// @param nId Node id.
	/// @return End iterator for the set of edges connected to the given no de.		/// @return End iterator for the set of edges connected to the given no de.
	AdjEdgeItr adjEdgesEnd(NodeItr nItr) {		AdjEdgeItr adjEdgesEnd(NodeId nId) {
	return getNode(nItr).edgesEnd();		return getNode(nId).edgesEnd();
	}		}
	/// \brief Get the first node connected to this edge.		/// \brief Get the first node connected to this edge.
	/// @param eItr Edge iterator.		/// @param eId Edge id.
	/// @return The first node connected to the given edge.		/// @return The first node connected to the given edge.
	NodeItr getEdgeNode1(EdgeItr eItr) {		NodeId getEdgeNode1(EdgeId eId) {
	return getEdge(eItr).getNode1();		return getEdge(eId).getNode1();
	}		}
	/// \brief Get the second node connected to this edge.		/// \brief Get the second node connected to this edge.
	/// @param eItr Edge iterator.		/// @param eId Edge id.
	/// @return The second node connected to the given edge.		/// @return The second node connected to the given edge.
	NodeItr getEdgeNode2(EdgeItr eItr) {		NodeId getEdgeNode2(EdgeId eId) {
	return getEdge(eItr).getNode2();		return getEdge(eId).getNode2();
	}		}
	/// \brief Get the "other" node connected to this edge.		/// \brief Get the "other" node connected to this edge.
	/// @param eItr Edge iterator.		/// @param eId Edge id.
	/// @param nItr Node iterator for the "given" node.		/// @param nId Node id for the "given" node.
	/// @return The iterator for the "other" node connected to this edge.		/// @return The iterator for the "other" node connected to this edge.
	NodeItr getEdgeOtherNode(EdgeItr eItr, NodeItr nItr) {		NodeId getEdgeOtherNode(EdgeId eId, NodeId nId) {
	EdgeEntry &e = getEdge(eItr);		EdgeEntry &e = getEdge(eId);
	if (e.getNode1() == nItr) {		if (e.getNode1() == nId) {
	return e.getNode2();		return e.getNode2();
	} // else		} // else
	return e.getNode1();		return e.getNode1();
	}		}
			EdgeId invalidEdgeId() const {
			return std::numeric_limits<EdgeId>::max();
			}
	/// \brief Get the edge connecting two nodes.		/// \brief Get the edge connecting two nodes.
	/// @param n1Itr First node iterator.		/// @param n1Id First node id.
	/// @param n2Itr Second node iterator.		/// @param n2Id Second node id.
	/// @return An iterator for edge (n1Itr, n2Itr) if such an edge exists,		/// @return An id for edge (n1Id, n2Id) if such an edge exists,
	/// otherwise returns edgesEnd().		/// otherwise returns an invalid edge id.
	EdgeItr findEdge(NodeItr n1Itr, NodeItr n2Itr) {		EdgeId findEdge(NodeId n1Id, NodeId n2Id) {
	for (AdjEdgeItr aeItr = adjEdgesBegin(n1Itr), aeEnd = adjEdgesEnd(n1I		for (AdjEdgeItr aeItr = adjEdgesBegin(n1Id), aeEnd = adjEdgesEnd(n1Id
	tr);		);
	aeItr != aeEnd; ++aeItr) {		aeItr != aeEnd; ++aeItr) {
	if ((getEdgeNode1(*aeItr) == n2Itr) ||		if ((getEdgeNode1(*aeItr) == n2Id) ||
	(getEdgeNode2(*aeItr) == n2Itr)) {		(getEdgeNode2(*aeItr) == n2Id)) {
	return *aeItr;		return *aeItr;
	}		}
	}		}
	return edges.end();		return invalidEdgeId();
	}		}
	/// \brief Remove a node from the graph.		/// \brief Remove a node from the graph.
	/// @param nItr Node iterator.		/// @param nId Node id.
	void removeNode(NodeItr nItr) {		void removeNode(NodeId nId) {
	NodeEntry &n = getNode(nItr);		NodeEntry &n = getNode(nId);
	for (AdjEdgeItr itr = n.edgesBegin(), end = n.edgesEnd(); itr != end;		for (AdjEdgeItr itr = n.edgesBegin(), end = n.edgesEnd(); itr != end;
	) {		++itr) {
	EdgeItr eItr = *itr;		EdgeId eId = *itr;
	++itr;		removeEdge(eId);
	removeEdge(eItr);
	}		}
	nodes.erase(nItr);		freeNodes.push_back(nId);
	--numNodes;
	}		}
	/// \brief Remove an edge from the graph.		/// \brief Remove an edge from the graph.
	/// @param eItr Edge iterator.		/// @param eId Edge id.
	void removeEdge(EdgeItr eItr) {		void removeEdge(EdgeId eId) {
	EdgeEntry &e = getEdge(eItr);		EdgeEntry &e = getEdge(eId);
	NodeEntry &n1 = getNode(e.getNode1());		NodeEntry &n1 = getNode(e.getNode1());
	NodeEntry &n2 = getNode(e.getNode2());		NodeEntry &n2 = getNode(e.getNode2());
	n1.removeEdge(e.getNode1AEItr());		n1.removeEdge(e.getNode1AEItr());
	n2.removeEdge(e.getNode2AEItr());		n2.removeEdge(e.getNode2AEItr());
	edges.erase(eItr);		freeEdges.push_back(eId);
	--numEdges;
	}		}
	/// \brief Remove all nodes and edges from the graph.		/// \brief Remove all nodes and edges from the graph.
	void clear() {		void clear() {
	nodes.clear();		nodes.clear();
			freeNodes.clear();
	edges.clear();		edges.clear();
	numNodes = numEdges = 0;		freeEdges.clear();
	}		}
	/// \brief Dump a graph to an output stream.		/// \brief Dump a graph to an output stream.
	template <typename OStream>		template <typename OStream>
	void dump(OStream &os) {		void dump(OStream &os) {
	os << getNumNodes() << " " << getNumEdges() << "\n";		os << getNumNodes() << " " << getNumEdges() << "\n";
	for (NodeItr nodeItr = nodesBegin(), nodeEnd = nodesEnd();		for (NodeItr nodeItr = nodesBegin(), nodeEnd = nodesEnd();
	nodeItr != nodeEnd; ++nodeItr) {		nodeItr != nodeEnd; ++nodeItr) {
	const Vector& v = getNodeCosts(nodeItr);		const Vector& v = getNodeCosts(*nodeItr);
	os << "\n" << v.getLength() << "\n";		os << "\n" << v.getLength() << "\n";
	assert(v.getLength() != 0 && "Empty vector in graph.");		assert(v.getLength() != 0 && "Empty vector in graph.");
	os << v[0];		os << v[0];
	for (unsigned i = 1; i < v.getLength(); ++i) {		for (unsigned i = 1; i < v.getLength(); ++i) {
	os << " " << v[i];		os << " " << v[i];
	}		}
	os << "\n";		os << "\n";
	}		}
	for (EdgeItr edgeItr = edgesBegin(), edgeEnd = edgesEnd();		for (EdgeItr edgeItr = edgesBegin(), edgeEnd = edgesEnd();
	edgeItr != edgeEnd; ++edgeItr) {		edgeItr != edgeEnd; ++edgeItr) {
	unsigned n1 = std::distance(nodesBegin(), getEdgeNode1(edgeItr));		NodeId n1 = getEdgeNode1(*edgeItr);
	unsigned n2 = std::distance(nodesBegin(), getEdgeNode2(edgeItr));		NodeId n2 = getEdgeNode2(*edgeItr);
	assert(n1 != n2 && "PBQP graphs shound not have self-edges.");		assert(n1 != n2 && "PBQP graphs shound not have self-edges.");
	const Matrix& m = getEdgeCosts(edgeItr);		const Matrix& m = getEdgeCosts(*edgeItr);
	os << "\n" << n1 << " " << n2 << "\n"		os << "\n" << n1 << " " << n2 << "\n"
	<< m.getRows() << " " << m.getCols() << "\n";		<< m.getRows() << " " << m.getCols() << "\n";
	assert(m.getRows() != 0 && "No rows in matrix.");		assert(m.getRows() != 0 && "No rows in matrix.");
	assert(m.getCols() != 0 && "No cols in matrix.");		assert(m.getCols() != 0 && "No cols in matrix.");
	for (unsigned i = 0; i < m.getRows(); ++i) {		for (unsigned i = 0; i < m.getRows(); ++i) {
	os << m[i][0];		os << m[i][0];
	for (unsigned j = 1; j < m.getCols(); ++j) {		for (unsigned j = 1; j < m.getCols(); ++j) {
	os << " " << m[i][j];		os << " " << m[i][j];
	}		}
	os << "\n";		os << "\n";
	skipping to change at line 405		skipping to change at line 440
	/// @param os Output stream to print on.		/// @param os Output stream to print on.
	template <typename OStream>		template <typename OStream>
	void printDot(OStream &os) {		void printDot(OStream &os) {
	os << "graph {\n";		os << "graph {\n";
	for (NodeItr nodeItr = nodesBegin(), nodeEnd = nodesEnd();		for (NodeItr nodeItr = nodesBegin(), nodeEnd = nodesEnd();
	nodeItr != nodeEnd; ++nodeItr) {		nodeItr != nodeEnd; ++nodeItr) {
	os << " node" << nodeItr << " [ label=\""		os << " node" << nodeItr << " [ label=\""
	<< nodeItr << ": " << getNodeCosts(nodeItr) << "\" ]\n";		<< nodeItr << ": " << getNodeCosts(*nodeItr) << "\" ]\n";
	}		}
	os << " edge [ len=" << getNumNodes() << " ]\n";		os << " edge [ len=" << getNumNodes() << " ]\n";
	for (EdgeItr edgeItr = edgesBegin(), edgeEnd = edgesEnd();		for (EdgeItr edgeItr = edgesBegin(), edgeEnd = edgesEnd();
	edgeItr != edgeEnd; ++edgeItr) {		edgeItr != edgeEnd; ++edgeItr) {
	os << " node" << getEdgeNode1(edgeItr)		os << " node" << getEdgeNode1(*edgeItr)
	<< " -- node" << getEdgeNode2(edgeItr)		<< " -- node" << getEdgeNode2(*edgeItr)
	<< " [ label=\"";		<< " [ label=\"";
	const Matrix &edgeCosts = getEdgeCosts(edgeItr);		const Matrix &edgeCosts = getEdgeCosts(*edgeItr);
	for (unsigned i = 0; i < edgeCosts.getRows(); ++i) {		for (unsigned i = 0; i < edgeCosts.getRows(); ++i) {
	os << edgeCosts.getRowAsVector(i) << "\\n";		os << edgeCosts.getRowAsVector(i) << "\\n";
	}		}
	os << "\" ]\n";		os << "\" ]\n";
	}		}
	os << "}\n";		os << "}\n";
	}		}
	};		};
	class NodeItrComparator {		// void Graph::copyFrom(const Graph &other) {
	public:		// std::map<Graph::ConstNodeItr, Graph::NodeItr,
	bool operator()(Graph::NodeItr n1, Graph::NodeItr n2) const {		// NodeItrComparator> nodeMap;
	return &*n1 < &*n2;
	}		// for (Graph::ConstNodeItr nItr = other.nodesBegin(),
			// nEnd = other.nodesEnd();
	bool operator()(Graph::ConstNodeItr n1, Graph::ConstNodeItr n2) const {		// nItr != nEnd; ++nItr) {
	return &*n1 < &*n2;		// nodeMap[nItr] = addNode(other.getNodeCosts(nItr));
	}		// }
	};		// }
	class EdgeItrCompartor {
	public:
	bool operator()(Graph::EdgeItr e1, Graph::EdgeItr e2) const {
	return &*e1 < &*e2;
	}
	bool operator()(Graph::ConstEdgeItr e1, Graph::ConstEdgeItr e2) const {
	return &*e1 < &*e2;
	}
	};
	void Graph::copyFrom(const Graph &other) {
	std::map<Graph::ConstNodeItr, Graph::NodeItr,
	NodeItrComparator> nodeMap;
	for (Graph::ConstNodeItr nItr = other.nodesBegin(),
	nEnd = other.nodesEnd();
	nItr != nEnd; ++nItr) {
	nodeMap[nItr] = addNode(other.getNodeCosts(nItr));
	}
	}
	}		}
	#endif // LLVM_CODEGEN_PBQP_GRAPH_HPP		#endif // LLVM_CODEGEN_PBQP_GRAPH_HPP
End of changes. 82 change blocks.
	199 lines changed or deleted		216 lines changed or added

	GraphWriter.h		GraphWriter.h
	skipping to change at line 53		skipping to change at line 53
	namespace GraphProgram {		namespace GraphProgram {
	enum Name {		enum Name {
	DOT,		DOT,
	FDP,		FDP,
	NEATO,		NEATO,
	TWOPI,		TWOPI,
	CIRCO		CIRCO
	};		};
	}		}
	void DisplayGraph(const sys::Path& Filename, bool wait=true, GraphProgram::		void DisplayGraph(StringRef Filename, bool wait = true,
	Name program = GraphProgram::DOT);		GraphProgram::Name program = GraphProgram::DOT);
	template<typename GraphType>		template<typename GraphType>
	class GraphWriter {		class GraphWriter {
	raw_ostream &O;		raw_ostream &O;
	const GraphType &G;		const GraphType &G;
	typedef DOTGraphTraits<GraphType> DOTTraits;		typedef DOTGraphTraits<GraphType> DOTTraits;
	typedef GraphTraits<GraphType> GTraits;		typedef GraphTraits<GraphType> GTraits;
	typedef typename GTraits::NodeType NodeType;		typedef typename GTraits::NodeType NodeType;
	typedef typename GTraits::nodes_iterator node_iterator;		typedef typename GTraits::nodes_iterator node_iterator;
	skipping to change at line 321		skipping to change at line 322
	const Twine &Title = "") {		const Twine &Title = "") {
	// Start the graph emission process...		// Start the graph emission process...
	GraphWriter<GraphType> W(O, G, ShortNames);		GraphWriter<GraphType> W(O, G, ShortNames);
	// Emit the graph.		// Emit the graph.
	W.writeGraph(Title.str());		W.writeGraph(Title.str());
	return O;		return O;
	}		}
	template<typename GraphType>		std::string createGraphFilename(const Twine &Name, int &FD);
	sys::Path WriteGraph(const GraphType &G, const Twine &Name,
	bool ShortNames = false, const Twine &Title = "") {		template <typename GraphType>
	std::string ErrMsg;		std::string WriteGraph(const GraphType &G, const Twine &Name,
	sys::Path Filename = sys::Path::GetTemporaryDirectory(&ErrMsg);		bool ShortNames = false, const Twine &Title = "") {
	if (Filename.isEmpty()) {		int FD;
	errs() << "Error: " << ErrMsg << "\n";		std::string Filename = createGraphFilename(Name, FD);
	return Filename;		raw_fd_ostream O(FD, /*shouldClose=*/ true);
	}
	Filename.appendComponent((Name + ".dot").str());		if (FD == -1) {
	if (Filename.makeUnique(true,&ErrMsg)) {		errs() << "error opening file '" << Filename << "' for writing!\n";
	errs() << "Error: " << ErrMsg << "\n";		return "";
	return sys::Path();
	}
	errs() << "Writing '" << Filename.str() << "'... ";
	std::string ErrorInfo;
	raw_fd_ostream O(Filename.c_str(), ErrorInfo);
	if (ErrorInfo.empty()) {
	llvm::WriteGraph(O, G, ShortNames, Title);
	errs() << " done. \n";
	} else {
	errs() << "error opening file '" << Filename.str() << "' for writing!\n
	";
	Filename.clear();
	}		}
			llvm::WriteGraph(O, G, ShortNames, Title);
			errs() << " done. \n";
	return Filename;		return Filename;
	}		}
	/// ViewGraph - Emit a dot graph, run 'dot', run gv on the postscript file,		/// ViewGraph - Emit a dot graph, run 'dot', run gv on the postscript file,
	/// then cleanup. For use from the debugger.		/// then cleanup. For use from the debugger.
	///		///
	template<typename GraphType>		template<typename GraphType>
	void ViewGraph(const GraphType &G, const Twine &Name,		void ViewGraph(const GraphType &G, const Twine &Name,
	bool ShortNames = false, const Twine &Title = "",		bool ShortNames = false, const Twine &Title = "",
	GraphProgram::Name Program = GraphProgram::DOT) {		GraphProgram::Name Program = GraphProgram::DOT) {
	sys::Path Filename = llvm::WriteGraph(G, Name, ShortNames, Title);		std::string Filename = llvm::WriteGraph(G, Name, ShortNames, Title);
	if (Filename.isEmpty())		if (Filename.empty())
	return;		return;
	DisplayGraph(Filename, true, Program);		DisplayGraph(Filename, true, Program);
	}		}
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 5 change blocks.
	31 lines changed or deleted		19 lines changed or added

	HeuristicBase.h		HeuristicBase.h
	skipping to change at line 55		skipping to change at line 55
	/// virtual, and indeed probably shouldn't for performance reasons.		/// virtual, and indeed probably shouldn't for performance reasons.
	///		///
	/// You'll also need to provide NodeData and EdgeData structs in your cla ss.		/// You'll also need to provide NodeData and EdgeData structs in your cla ss.
	/// These can be used to attach data relevant to your heuristic to each		/// These can be used to attach data relevant to your heuristic to each
	/// node/edge in the PBQP graph.		/// node/edge in the PBQP graph.
	template <typename HImpl>		template <typename HImpl>
	class HeuristicBase {		class HeuristicBase {
	private:		private:
	typedef std::list<Graph::NodeItr> OptimalList;		typedef std::list<Graph::NodeId> OptimalList;
	HeuristicSolverImpl<HImpl> &s;		HeuristicSolverImpl<HImpl> &s;
	Graph &g;		Graph &g;
	OptimalList optimalList;		OptimalList optimalList;
	// Return a reference to the derived heuristic.		// Return a reference to the derived heuristic.
	HImpl& impl() { return static_cast<HImpl&>(*this); }		HImpl& impl() { return static_cast<HImpl&>(*this); }
	// Add the given node to the optimal reductions list. Keep an iterator to		// Add the given node to the optimal reductions list. Keep an iterator to
	// its location for fast removal.		// its location for fast removal.
	void addToOptimalReductionList(Graph::NodeItr nItr) {		void addToOptimalReductionList(Graph::NodeId nId) {
	optimalList.insert(optimalList.end(), nItr);		optimalList.insert(optimalList.end(), nId);
	}		}
	public:		public:
	/// \brief Construct an instance with a reference to the given solver.		/// \brief Construct an instance with a reference to the given solver.
	/// @param solver The solver which is using this heuristic instance.		/// @param solver The solver which is using this heuristic instance.
	HeuristicBase(HeuristicSolverImpl<HImpl> &solver)		HeuristicBase(HeuristicSolverImpl<HImpl> &solver)
	: s(solver), g(s.getGraph()) { }		: s(solver), g(s.getGraph()) { }
	/// \brief Get the solver which is using this heuristic instance.		/// \brief Get the solver which is using this heuristic instance.
	skipping to change at line 108		skipping to change at line 108
	/// reduced.		/// reduced.
	/// @return Whether or not the given node should be listed for optimal		/// @return Whether or not the given node should be listed for optimal
	/// reduction (via R0, R1 or R2).		/// reduction (via R0, R1 or R2).
	///		///
	/// HeuristicBase returns true for any node with degree less than 3. Th is is		/// HeuristicBase returns true for any node with degree less than 3. Th is is
	/// sane and sensible for many situations, but not all. You can over-ri de		/// sane and sensible for many situations, but not all. You can over-ri de
	/// this method in your derived class if you want a different selection		/// this method in your derived class if you want a different selection
	/// criteria. Note however that your criteria for selecting optimal nod es		/// criteria. Note however that your criteria for selecting optimal nod es
	/// should be <i>at least</i> as strong as this. I.e. Nodes of degree 3 or		/// should be <i>at least</i> as strong as this. I.e. Nodes of degree 3 or
	/// higher should not be selected under any circumstances.		/// higher should not be selected under any circumstances.
	bool shouldOptimallyReduce(Graph::NodeItr nItr) {		bool shouldOptimallyReduce(Graph::NodeId nId) {
	if (g.getNodeDegree(nItr) < 3)		if (g.getNodeDegree(nId) < 3)
	return true;		return true;
	// else		// else
	return false;		return false;
	}		}
	/// \brief Add the given node to the list of nodes to be optimally redu ced.		/// \brief Add the given node to the list of nodes to be optimally redu ced.
	/// @param nItr Node iterator to be added.		/// @param nId Node id to be added.
	///		///
	/// You probably don't want to over-ride this, except perhaps to record		/// You probably don't want to over-ride this, except perhaps to record
	/// statistics before calling this implementation. HeuristicBase relies on		/// statistics before calling this implementation. HeuristicBase relies on
	/// its behaviour.		/// its behaviour.
	void addToOptimalReduceList(Graph::NodeItr nItr) {		void addToOptimalReduceList(Graph::NodeId nId) {
	optimalList.push_back(nItr);		optimalList.push_back(nId);
	}		}
	/// \brief Initialise the heuristic.		/// \brief Initialise the heuristic.
	///		///
	/// HeuristicBase iterates over all nodes in the problem and adds them to		/// HeuristicBase iterates over all nodes in the problem and adds them to
	/// the appropriate list using addToOptimalReduceList or		/// the appropriate list using addToOptimalReduceList or
	/// addToHeuristicReduceList based on the result of shouldOptimallyRedu ce.		/// addToHeuristicReduceList based on the result of shouldOptimallyRedu ce.
	///		///
	/// This behaviour should be fine for most situations.		/// This behaviour should be fine for most situations.
	void setup() {		void setup() {
	for (Graph::NodeItr nItr = g.nodesBegin(), nEnd = g.nodesEnd();		for (Graph::NodeItr nItr = g.nodesBegin(), nEnd = g.nodesEnd();
	nItr != nEnd; ++nItr) {		nItr != nEnd; ++nItr) {
	if (impl().shouldOptimallyReduce(nItr)) {		if (impl().shouldOptimallyReduce(*nItr)) {
	addToOptimalReduceList(nItr);		addToOptimalReduceList(*nItr);
	} else {		} else {
	impl().addToHeuristicReduceList(nItr);		impl().addToHeuristicReduceList(*nItr);
	}		}
	}		}
	}		}
	/// \brief Optimally reduce one of the nodes in the optimal reduce list .		/// \brief Optimally reduce one of the nodes in the optimal reduce list .
	/// @return True if a reduction takes place, false if the optimal reduc e		/// @return True if a reduction takes place, false if the optimal reduc e
	/// list is empty.		/// list is empty.
	///		///
	/// Selects a node from the optimal reduce list and removes it, applyin g		/// Selects a node from the optimal reduce list and removes it, applyin g
	/// R0, R1 or R2 as appropriate based on the selected node's degree.		/// R0, R1 or R2 as appropriate based on the selected node's degree.
	bool optimalReduce() {		bool optimalReduce() {
	if (optimalList.empty())		if (optimalList.empty())
	return false;		return false;
	Graph::NodeItr nItr = optimalList.front();		Graph::NodeId nId = optimalList.front();
	optimalList.pop_front();		optimalList.pop_front();
	switch (s.getSolverDegree(nItr)) {		switch (s.getSolverDegree(nId)) {
	case 0: s.applyR0(nItr); break;		case 0: s.applyR0(nId); break;
	case 1: s.applyR1(nItr); break;		case 1: s.applyR1(nId); break;
	case 2: s.applyR2(nItr); break;		case 2: s.applyR2(nId); break;
	default: llvm_unreachable(		default: llvm_unreachable(
	"Optimal reductions of degree > 2 nodes is invalid. ");		"Optimal reductions of degree > 2 nodes is invalid. ");
	}		}
	return true;		return true;
	}		}
	/// \brief Perform the PBQP reduction process.		/// \brief Perform the PBQP reduction process.
	///		///
	/// Reduces the problem to the empty graph by repeated application of t he		/// Reduces the problem to the empty graph by repeated application of t he
	skipping to change at line 187		skipping to change at line 187
	if (impl().heuristicReduce()) {		if (impl().heuristicReduce()) {
	getSolver().recordRN();		getSolver().recordRN();
	} else {		} else {
	finished = true;		finished = true;
	}		}
	}		}
	}		}
	}		}
	/// \brief Add a node to the heuristic reduce list.		/// \brief Add a node to the heuristic reduce list.
	/// @param nItr Node iterator to add to the heuristic reduce list.		/// @param nId Node id to add to the heuristic reduce list.
	void addToHeuristicList(Graph::NodeItr nItr) {		void addToHeuristicList(Graph::NodeId nId) {
	llvm_unreachable("Must be implemented in derived class.");		llvm_unreachable("Must be implemented in derived class.");
	}		}
	/// \brief Heuristically reduce one of the nodes in the heuristic		/// \brief Heuristically reduce one of the nodes in the heuristic
	/// reduce list.		/// reduce list.
	/// @return True if a reduction takes place, false if the heuristic red uce		/// @return True if a reduction takes place, false if the heuristic red uce
	/// list is empty.		/// list is empty.
	bool heuristicReduce() {		bool heuristicReduce() {
	llvm_unreachable("Must be implemented in derived class.");		llvm_unreachable("Must be implemented in derived class.");
	return false;		return false;
	}		}
	/// \brief Prepare a change in the costs on the given edge.		/// \brief Prepare a change in the costs on the given edge.
	/// @param eItr Edge iterator.		/// @param eId Edge id.
	void preUpdateEdgeCosts(Graph::EdgeItr eItr) {		void preUpdateEdgeCosts(Graph::EdgeId eId) {
	llvm_unreachable("Must be implemented in derived class.");		llvm_unreachable("Must be implemented in derived class.");
	}		}
	/// \brief Handle the change in the costs on the given edge.		/// \brief Handle the change in the costs on the given edge.
	/// @param eItr Edge iterator.		/// @param eId Edge id.
	void postUpdateEdgeCostts(Graph::EdgeItr eItr) {		void postUpdateEdgeCostts(Graph::EdgeId eId) {
	llvm_unreachable("Must be implemented in derived class.");		llvm_unreachable("Must be implemented in derived class.");
	}		}
	/// \brief Handle the addition of a new edge into the PBQP graph.		/// \brief Handle the addition of a new edge into the PBQP graph.
	/// @param eItr Edge iterator for the added edge.		/// @param eId Edge id for the added edge.
	void handleAddEdge(Graph::EdgeItr eItr) {		void handleAddEdge(Graph::EdgeId eId) {
	llvm_unreachable("Must be implemented in derived class.");		llvm_unreachable("Must be implemented in derived class.");
	}		}
	/// \brief Handle disconnection of an edge from a node.		/// \brief Handle disconnection of an edge from a node.
	/// @param eItr Edge iterator for edge being disconnected.		/// @param eId Edge id for edge being disconnected.
	/// @param nItr Node iterator for the node being disconnected from.		/// @param nId Node id for the node being disconnected from.
	///		///
	/// Edges are frequently removed due to the removal of a node. This		/// Edges are frequently removed due to the removal of a node. This
	/// method allows for the effect to be computed only for the remaining		/// method allows for the effect to be computed only for the remaining
	/// node in the graph.		/// node in the graph.
	void handleRemoveEdge(Graph::EdgeItr eItr, Graph::NodeItr nItr) {		void handleRemoveEdge(Graph::EdgeId eId, Graph::NodeId nId) {
	llvm_unreachable("Must be implemented in derived class.");		llvm_unreachable("Must be implemented in derived class.");
	}		}
	/// \brief Clean up any structures used by HeuristicBase.		/// \brief Clean up any structures used by HeuristicBase.
	///		///
	/// At present this just performs a sanity check: that the optimal redu ce		/// At present this just performs a sanity check: that the optimal redu ce
	/// list is empty now that reduction has completed.		/// list is empty now that reduction has completed.
	///		///
	/// If your derived class has more complex structures which need tearin g		/// If your derived class has more complex structures which need tearin g
	/// down you should over-ride this method but include a call back to th is		/// down you should over-ride this method but include a call back to th is
End of changes. 15 change blocks.
	27 lines changed or deleted		27 lines changed or added

	HeuristicSolver.h		HeuristicSolver.h
	skipping to change at line 43		skipping to change at line 43
	/// backpropagation phase, and maintains the internal copy of the graph o n		/// backpropagation phase, and maintains the internal copy of the graph o n
	/// which the reduction is carried out (the original being kept to facili tate		/// which the reduction is carried out (the original being kept to facili tate
	/// backpropagation).		/// backpropagation).
	template <typename HImpl>		template <typename HImpl>
	class HeuristicSolverImpl {		class HeuristicSolverImpl {
	private:		private:
	typedef typename HImpl::NodeData HeuristicNodeData;		typedef typename HImpl::NodeData HeuristicNodeData;
	typedef typename HImpl::EdgeData HeuristicEdgeData;		typedef typename HImpl::EdgeData HeuristicEdgeData;
	typedef std::list<Graph::EdgeItr> SolverEdges;		typedef std::list<Graph::EdgeId> SolverEdges;
	public:		public:
	/// \brief Iterator type for edges in the solver graph.		/// \brief Iterator type for edges in the solver graph.
	typedef SolverEdges::iterator SolverEdgeItr;		typedef SolverEdges::iterator SolverEdgeItr;
	private:		private:
	class NodeData {		class NodeData {
	public:		public:
	NodeData() : solverDegree(0) {}		NodeData() : solverDegree(0) {}
	HeuristicNodeData& getHeuristicData() { return hData; }		HeuristicNodeData& getHeuristicData() { return hData; }
	SolverEdgeItr addSolverEdge(Graph::EdgeItr eItr) {		SolverEdgeItr addSolverEdge(Graph::EdgeId eId) {
	++solverDegree;		++solverDegree;
	return solverEdges.insert(solverEdges.end(), eItr);		return solverEdges.insert(solverEdges.end(), eId);
	}		}
	void removeSolverEdge(SolverEdgeItr seItr) {		void removeSolverEdge(SolverEdgeItr seItr) {
	--solverDegree;		--solverDegree;
	solverEdges.erase(seItr);		solverEdges.erase(seItr);
	}		}
	SolverEdgeItr solverEdgesBegin() { return solverEdges.begin(); }		SolverEdgeItr solverEdgesBegin() { return solverEdges.begin(); }
	SolverEdgeItr solverEdgesEnd() { return solverEdges.end(); }		SolverEdgeItr solverEdgesEnd() { return solverEdges.end(); }
	unsigned getSolverDegree() const { return solverDegree; }		unsigned getSolverDegree() const { return solverDegree; }
	skipping to change at line 107		skipping to change at line 107
	private:		private:
	HeuristicEdgeData hData;		HeuristicEdgeData hData;
	SolverEdgeItr n1SolverEdgeItr, n2SolverEdgeItr;		SolverEdgeItr n1SolverEdgeItr, n2SolverEdgeItr;
	};		};
	Graph &g;		Graph &g;
	HImpl h;		HImpl h;
	Solution s;		Solution s;
	std::vector<Graph::NodeItr> stack;		std::vector<Graph::NodeId> stack;
	typedef std::list<NodeData> NodeDataList;		typedef std::list<NodeData> NodeDataList;
	NodeDataList nodeDataList;		NodeDataList nodeDataList;
	typedef std::list<EdgeData> EdgeDataList;		typedef std::list<EdgeData> EdgeDataList;
	EdgeDataList edgeDataList;		EdgeDataList edgeDataList;
	public:		public:
	/// \brief Construct a heuristic solver implementation to solve the giv en		/// \brief Construct a heuristic solver implementation to solve the giv en
	/// graph.		/// graph.
	/// @param g The graph representing the problem instance to be solved.		/// @param g The graph representing the problem instance to be solved.
	HeuristicSolverImpl(Graph &g) : g(g), h(*this) {}		HeuristicSolverImpl(Graph &g) : g(g), h(*this) {}
	/// \brief Get the graph being solved by this solver.		/// \brief Get the graph being solved by this solver.
	/// @return The graph representing the problem instance being solved by this		/// @return The graph representing the problem instance being solved by this
	/// solver.		/// solver.
	Graph& getGraph() { return g; }		Graph& getGraph() { return g; }
	/// \brief Get the heuristic data attached to the given node.		/// \brief Get the heuristic data attached to the given node.
	/// @param nItr Node iterator.		/// @param nId Node id.
	/// @return The heuristic data attached to the given node.		/// @return The heuristic data attached to the given node.
	HeuristicNodeData& getHeuristicNodeData(Graph::NodeItr nItr) {		HeuristicNodeData& getHeuristicNodeData(Graph::NodeId nId) {
	return getSolverNodeData(nItr).getHeuristicData();		return getSolverNodeData(nId).getHeuristicData();
	}		}
	/// \brief Get the heuristic data attached to the given edge.		/// \brief Get the heuristic data attached to the given edge.
	/// @param eItr Edge iterator.		/// @param eId Edge id.
	/// @return The heuristic data attached to the given node.		/// @return The heuristic data attached to the given node.
	HeuristicEdgeData& getHeuristicEdgeData(Graph::EdgeItr eItr) {		HeuristicEdgeData& getHeuristicEdgeData(Graph::EdgeId eId) {
	return getSolverEdgeData(eItr).getHeuristicData();		return getSolverEdgeData(eId).getHeuristicData();
	}		}
	/// \brief Begin iterator for the set of edges adjacent to the given no de in		/// \brief Begin iterator for the set of edges adjacent to the given no de in
	/// the solver graph.		/// the solver graph.
	/// @param nItr Node iterator.		/// @param nId Node id.
	/// @return Begin iterator for the set of edges adjacent to the given n ode		/// @return Begin iterator for the set of edges adjacent to the given n ode
	/// in the solver graph.		/// in the solver graph.
	SolverEdgeItr solverEdgesBegin(Graph::NodeItr nItr) {		SolverEdgeItr solverEdgesBegin(Graph::NodeId nId) {
	return getSolverNodeData(nItr).solverEdgesBegin();		return getSolverNodeData(nId).solverEdgesBegin();
	}		}
	/// \brief End iterator for the set of edges adjacent to the given node in		/// \brief End iterator for the set of edges adjacent to the given node in
	/// the solver graph.		/// the solver graph.
	/// @param nItr Node iterator.		/// @param nId Node id.
	/// @return End iterator for the set of edges adjacent to the given nod e in		/// @return End iterator for the set of edges adjacent to the given nod e in
	/// the solver graph.		/// the solver graph.
	SolverEdgeItr solverEdgesEnd(Graph::NodeItr nItr) {		SolverEdgeItr solverEdgesEnd(Graph::NodeId nId) {
	return getSolverNodeData(nItr).solverEdgesEnd();		return getSolverNodeData(nId).solverEdgesEnd();
	}		}
	/// \brief Remove a node from the solver graph.		/// \brief Remove a node from the solver graph.
	/// @param eItr Edge iterator for edge to be removed.		/// @param eId Edge id for edge to be removed.
	///		///
	/// Does <i>not</i> notify the heuristic of the removal. That should be		/// Does <i>not</i> notify the heuristic of the removal. That should be
	/// done manually if necessary.		/// done manually if necessary.
	void removeSolverEdge(Graph::EdgeItr eItr) {		void removeSolverEdge(Graph::EdgeId eId) {
	EdgeData &eData = getSolverEdgeData(eItr);		EdgeData &eData = getSolverEdgeData(eId);
	NodeData &n1Data = getSolverNodeData(g.getEdgeNode1(eItr)),		NodeData &n1Data = getSolverNodeData(g.getEdgeNode1(eId)),
	&n2Data = getSolverNodeData(g.getEdgeNode2(eItr));		&n2Data = getSolverNodeData(g.getEdgeNode2(eId));
	n1Data.removeSolverEdge(eData.getN1SolverEdgeItr());		n1Data.removeSolverEdge(eData.getN1SolverEdgeItr());
	n2Data.removeSolverEdge(eData.getN2SolverEdgeItr());		n2Data.removeSolverEdge(eData.getN2SolverEdgeItr());
	}		}
	/// \brief Compute a solution to the PBQP problem instance with which t his		/// \brief Compute a solution to the PBQP problem instance with which t his
	/// heuristic solver was constructed.		/// heuristic solver was constructed.
	/// @return A solution to the PBQP problem.		/// @return A solution to the PBQP problem.
	///		///
	/// Performs the full PBQP heuristic solver algorithm, including setup,		/// Performs the full PBQP heuristic solver algorithm, including setup,
	skipping to change at line 191		skipping to change at line 191
	setup();		setup();
	h.setup();		h.setup();
	h.reduce();		h.reduce();
	backpropagate();		backpropagate();
	h.cleanup();		h.cleanup();
	cleanup();		cleanup();
	return s;		return s;
	}		}
	/// \brief Add to the end of the stack.		/// \brief Add to the end of the stack.
	/// @param nItr Node iterator to add to the reduction stack.		/// @param nId Node id to add to the reduction stack.
	void pushToStack(Graph::NodeItr nItr) {		void pushToStack(Graph::NodeId nId) {
	getSolverNodeData(nItr).clearSolverEdges();		getSolverNodeData(nId).clearSolverEdges();
	stack.push_back(nItr);		stack.push_back(nId);
	}		}
	/// \brief Returns the solver degree of the given node.		/// \brief Returns the solver degree of the given node.
	/// @param nItr Node iterator for which degree is requested.		/// @param nId Node id for which degree is requested.
	/// @return Node degree in the <i>solver</i> graph (not the original gr aph).		/// @return Node degree in the <i>solver</i> graph (not the original gr aph).
	unsigned getSolverDegree(Graph::NodeItr nItr) {		unsigned getSolverDegree(Graph::NodeId nId) {
	return getSolverNodeData(nItr).getSolverDegree();		return getSolverNodeData(nId).getSolverDegree();
	}		}
	/// \brief Set the solution of the given node.		/// \brief Set the solution of the given node.
	/// @param nItr Node iterator to set solution for.		/// @param nId Node id to set solution for.
	/// @param selection Selection for node.		/// @param selection Selection for node.
	void setSolution(const Graph::NodeItr &nItr, unsigned selection) {		void setSolution(const Graph::NodeId &nId, unsigned selection) {
	s.setSelection(nItr, selection);		s.setSelection(nId, selection);
	for (Graph::AdjEdgeItr aeItr = g.adjEdgesBegin(nItr),		for (Graph::AdjEdgeItr aeItr = g.adjEdgesBegin(nId),
	aeEnd = g.adjEdgesEnd(nItr);		aeEnd = g.adjEdgesEnd(nId);
	aeItr != aeEnd; ++aeItr) {		aeItr != aeEnd; ++aeItr) {
	Graph::EdgeItr eItr(*aeItr);		Graph::EdgeId eId(*aeItr);
	Graph::NodeItr anItr(g.getEdgeOtherNode(eItr, nItr));		Graph::NodeId anId(g.getEdgeOtherNode(eId, nId));
	getSolverNodeData(anItr).addSolverEdge(eItr);		getSolverNodeData(anId).addSolverEdge(eId);
	}		}
	}		}
	/// \brief Apply rule R0.		/// \brief Apply rule R0.
	/// @param nItr Node iterator for node to apply R0 to.		/// @param nId Node id for node to apply R0 to.
	///		///
	/// Node will be automatically pushed to the solver stack.		/// Node will be automatically pushed to the solver stack.
	void applyR0(Graph::NodeItr nItr) {		void applyR0(Graph::NodeId nId) {
	assert(getSolverNodeData(nItr).getSolverDegree() == 0 &&		assert(getSolverNodeData(nId).getSolverDegree() == 0 &&
	"R0 applied to node with degree != 0.");		"R0 applied to node with degree != 0.");
	// Nothing to do. Just push the node onto the reduction stack.		// Nothing to do. Just push the node onto the reduction stack.
	pushToStack(nItr);		pushToStack(nId);
	s.recordR0();		s.recordR0();
	}		}
	/// \brief Apply rule R1.		/// \brief Apply rule R1.
	/// @param xnItr Node iterator for node to apply R1 to.		/// @param xnId Node id for node to apply R1 to.
	///		///
	/// Node will be automatically pushed to the solver stack.		/// Node will be automatically pushed to the solver stack.
	void applyR1(Graph::NodeItr xnItr) {		void applyR1(Graph::NodeId xnId) {
	NodeData &nd = getSolverNodeData(xnItr);		NodeData &nd = getSolverNodeData(xnId);
	assert(nd.getSolverDegree() == 1 &&		assert(nd.getSolverDegree() == 1 &&
	"R1 applied to node with degree != 1.");		"R1 applied to node with degree != 1.");
	Graph::EdgeItr eItr = *nd.solverEdgesBegin();		Graph::EdgeId eId = *nd.solverEdgesBegin();
	const Matrix &eCosts = g.getEdgeCosts(eItr);		const Matrix &eCosts = g.getEdgeCosts(eId);
	const Vector &xCosts = g.getNodeCosts(xnItr);		const Vector &xCosts = g.getNodeCosts(xnId);
	// Duplicate a little to avoid transposing matrices.		// Duplicate a little to avoid transposing matrices.
	if (xnItr == g.getEdgeNode1(eItr)) {		if (xnId == g.getEdgeNode1(eId)) {
	Graph::NodeItr ynItr = g.getEdgeNode2(eItr);		Graph::NodeId ynId = g.getEdgeNode2(eId);
	Vector &yCosts = g.getNodeCosts(ynItr);		Vector &yCosts = g.getNodeCosts(ynId);
	for (unsigned j = 0; j < yCosts.getLength(); ++j) {		for (unsigned j = 0; j < yCosts.getLength(); ++j) {
	PBQPNum min = eCosts[0][j] + xCosts[0];		PBQPNum min = eCosts[0][j] + xCosts[0];
	for (unsigned i = 1; i < xCosts.getLength(); ++i) {		for (unsigned i = 1; i < xCosts.getLength(); ++i) {
	PBQPNum c = eCosts[i][j] + xCosts[i];		PBQPNum c = eCosts[i][j] + xCosts[i];
	if (c < min)		if (c < min)
	min = c;		min = c;
	}		}
	yCosts[j] += min;		yCosts[j] += min;
	}		}
	h.handleRemoveEdge(eItr, ynItr);		h.handleRemoveEdge(eId, ynId);
	} else {		} else {
	Graph::NodeItr ynItr = g.getEdgeNode1(eItr);		Graph::NodeId ynId = g.getEdgeNode1(eId);
	Vector &yCosts = g.getNodeCosts(ynItr);		Vector &yCosts = g.getNodeCosts(ynId);
	for (unsigned i = 0; i < yCosts.getLength(); ++i) {		for (unsigned i = 0; i < yCosts.getLength(); ++i) {
	PBQPNum min = eCosts[i][0] + xCosts[0];		PBQPNum min = eCosts[i][0] + xCosts[0];
	for (unsigned j = 1; j < xCosts.getLength(); ++j) {		for (unsigned j = 1; j < xCosts.getLength(); ++j) {
	PBQPNum c = eCosts[i][j] + xCosts[j];		PBQPNum c = eCosts[i][j] + xCosts[j];
	if (c < min)		if (c < min)
	min = c;		min = c;
	}		}
	yCosts[i] += min;		yCosts[i] += min;
	}		}
	h.handleRemoveEdge(eItr, ynItr);		h.handleRemoveEdge(eId, ynId);
	}		}
	removeSolverEdge(eItr);		removeSolverEdge(eId);
	assert(nd.getSolverDegree() == 0 &&		assert(nd.getSolverDegree() == 0 &&
	"Degree 1 with edge removed should be 0.");		"Degree 1 with edge removed should be 0.");
	pushToStack(xnItr);		pushToStack(xnId);
	s.recordR1();		s.recordR1();
	}		}
	/// \brief Apply rule R2.		/// \brief Apply rule R2.
	/// @param xnItr Node iterator for node to apply R2 to.		/// @param xnId Node id for node to apply R2 to.
	///		///
	/// Node will be automatically pushed to the solver stack.		/// Node will be automatically pushed to the solver stack.
	void applyR2(Graph::NodeItr xnItr) {		void applyR2(Graph::NodeId xnId) {
	assert(getSolverNodeData(xnItr).getSolverDegree() == 2 &&		assert(getSolverNodeData(xnId).getSolverDegree() == 2 &&
	"R2 applied to node with degree != 2.");		"R2 applied to node with degree != 2.");
	NodeData &nd = getSolverNodeData(xnItr);		NodeData &nd = getSolverNodeData(xnId);
	const Vector &xCosts = g.getNodeCosts(xnItr);		const Vector &xCosts = g.getNodeCosts(xnId);
	SolverEdgeItr aeItr = nd.solverEdgesBegin();		SolverEdgeItr aeItr = nd.solverEdgesBegin();
	Graph::EdgeItr yxeItr = *aeItr,		Graph::EdgeId yxeId = *aeItr,
	zxeItr = *(++aeItr);		zxeId = *(++aeItr);
	Graph::NodeItr ynItr = g.getEdgeOtherNode(yxeItr, xnItr),		Graph::NodeId ynId = g.getEdgeOtherNode(yxeId, xnId),
	znItr = g.getEdgeOtherNode(zxeItr, xnItr);		znId = g.getEdgeOtherNode(zxeId, xnId);
	bool flipEdge1 = (g.getEdgeNode1(yxeItr) == xnItr),		bool flipEdge1 = (g.getEdgeNode1(yxeId) == xnId),
	flipEdge2 = (g.getEdgeNode1(zxeItr) == xnItr);		flipEdge2 = (g.getEdgeNode1(zxeId) == xnId);
	const Matrix *yxeCosts = flipEdge1 ?		const Matrix *yxeCosts = flipEdge1 ?
	new Matrix(g.getEdgeCosts(yxeItr).transpose()) :		new Matrix(g.getEdgeCosts(yxeId).transpose()) :
	&g.getEdgeCosts(yxeItr);		&g.getEdgeCosts(yxeId);
	const Matrix *zxeCosts = flipEdge2 ?		const Matrix *zxeCosts = flipEdge2 ?
	new Matrix(g.getEdgeCosts(zxeItr).transpose()) :		new Matrix(g.getEdgeCosts(zxeId).transpose()) :
	&g.getEdgeCosts(zxeItr);		&g.getEdgeCosts(zxeId);
	unsigned xLen = xCosts.getLength(),		unsigned xLen = xCosts.getLength(),
	yLen = yxeCosts->getRows(),		yLen = yxeCosts->getRows(),
	zLen = zxeCosts->getRows();		zLen = zxeCosts->getRows();
	Matrix delta(yLen, zLen);		Matrix delta(yLen, zLen);
	for (unsigned i = 0; i < yLen; ++i) {		for (unsigned i = 0; i < yLen; ++i) {
	for (unsigned j = 0; j < zLen; ++j) {		for (unsigned j = 0; j < zLen; ++j) {
	PBQPNum min = (*yxeCosts)[i][0] + (*zxeCosts)[j][0] + xCosts[0];		PBQPNum min = (*yxeCosts)[i][0] + (*zxeCosts)[j][0] + xCosts[0];
	skipping to change at line 336		skipping to change at line 336
	delta[i][j] = min;		delta[i][j] = min;
	}		}
	}		}
	if (flipEdge1)		if (flipEdge1)
	delete yxeCosts;		delete yxeCosts;
	if (flipEdge2)		if (flipEdge2)
	delete zxeCosts;		delete zxeCosts;
	Graph::EdgeItr yzeItr = g.findEdge(ynItr, znItr);		Graph::EdgeId yzeId = g.findEdge(ynId, znId);
	bool addedEdge = false;		bool addedEdge = false;
	if (yzeItr == g.edgesEnd()) {		if (yzeId == g.invalidEdgeId()) {
	yzeItr = g.addEdge(ynItr, znItr, delta);		yzeId = g.addEdge(ynId, znId, delta);
	addedEdge = true;		addedEdge = true;
	} else {		} else {
	Matrix &yzeCosts = g.getEdgeCosts(yzeItr);		Matrix &yzeCosts = g.getEdgeCosts(yzeId);
	h.preUpdateEdgeCosts(yzeItr);		h.preUpdateEdgeCosts(yzeId);
	if (ynItr == g.getEdgeNode1(yzeItr)) {		if (ynId == g.getEdgeNode1(yzeId)) {
	yzeCosts += delta;		yzeCosts += delta;
	} else {		} else {
	yzeCosts += delta.transpose();		yzeCosts += delta.transpose();
	}		}
	}		}
	bool nullCostEdge = tryNormaliseEdgeMatrix(yzeItr);		bool nullCostEdge = tryNormaliseEdgeMatrix(yzeId);
	if (!addedEdge) {		if (!addedEdge) {
	// If we modified the edge costs let the heuristic know.		// If we modified the edge costs let the heuristic know.
	h.postUpdateEdgeCosts(yzeItr);		h.postUpdateEdgeCosts(yzeId);
	}		}
	if (nullCostEdge) {		if (nullCostEdge) {
	// If this edge ended up null remove it.		// If this edge ended up null remove it.
	if (!addedEdge) {		if (!addedEdge) {
	// We didn't just add it, so we need to notify the heuristic		// We didn't just add it, so we need to notify the heuristic
	// and remove it from the solver.		// and remove it from the solver.
	h.handleRemoveEdge(yzeItr, ynItr);		h.handleRemoveEdge(yzeId, ynId);
	h.handleRemoveEdge(yzeItr, znItr);		h.handleRemoveEdge(yzeId, znId);
	removeSolverEdge(yzeItr);		removeSolverEdge(yzeId);
	}		}
	g.removeEdge(yzeItr);		g.removeEdge(yzeId);
	} else if (addedEdge) {		} else if (addedEdge) {
	// If the edge was added, and non-null, finish setting it up, add i t to		// If the edge was added, and non-null, finish setting it up, add i t to
	// the solver & notify heuristic.		// the solver & notify heuristic.
	edgeDataList.push_back(EdgeData());		edgeDataList.push_back(EdgeData());
	g.setEdgeData(yzeItr, &edgeDataList.back());		g.setEdgeData(yzeId, &edgeDataList.back());
	addSolverEdge(yzeItr);		addSolverEdge(yzeId);
	h.handleAddEdge(yzeItr);		h.handleAddEdge(yzeId);
	}		}
	h.handleRemoveEdge(yxeItr, ynItr);		h.handleRemoveEdge(yxeId, ynId);
	removeSolverEdge(yxeItr);		removeSolverEdge(yxeId);
	h.handleRemoveEdge(zxeItr, znItr);		h.handleRemoveEdge(zxeId, znId);
	removeSolverEdge(zxeItr);		removeSolverEdge(zxeId);
	pushToStack(xnItr);		pushToStack(xnId);
	s.recordR2();		s.recordR2();
	}		}
	/// \brief Record an application of the RN rule.		/// \brief Record an application of the RN rule.
	///		///
	/// For use by the HeuristicBase.		/// For use by the HeuristicBase.
	void recordRN() { s.recordRN(); }		void recordRN() { s.recordRN(); }
	private:		private:
	NodeData& getSolverNodeData(Graph::NodeItr nItr) {		NodeData& getSolverNodeData(Graph::NodeId nId) {
	return *static_cast<NodeData*>(g.getNodeData(nItr));		return *static_cast<NodeData*>(g.getNodeData(nId));
	}		}
	EdgeData& getSolverEdgeData(Graph::EdgeItr eItr) {		EdgeData& getSolverEdgeData(Graph::EdgeId eId) {
	return *static_cast<EdgeData*>(g.getEdgeData(eItr));		return *static_cast<EdgeData*>(g.getEdgeData(eId));
	}		}
	void addSolverEdge(Graph::EdgeItr eItr) {		void addSolverEdge(Graph::EdgeId eId) {
	EdgeData &eData = getSolverEdgeData(eItr);		EdgeData &eData = getSolverEdgeData(eId);
	NodeData &n1Data = getSolverNodeData(g.getEdgeNode1(eItr)),		NodeData &n1Data = getSolverNodeData(g.getEdgeNode1(eId)),
	&n2Data = getSolverNodeData(g.getEdgeNode2(eItr));		&n2Data = getSolverNodeData(g.getEdgeNode2(eId));
	eData.setN1SolverEdgeItr(n1Data.addSolverEdge(eItr));		eData.setN1SolverEdgeItr(n1Data.addSolverEdge(eId));
	eData.setN2SolverEdgeItr(n2Data.addSolverEdge(eItr));		eData.setN2SolverEdgeItr(n2Data.addSolverEdge(eId));
	}		}
	void setup() {		void setup() {
	if (h.solverRunSimplify()) {		if (h.solverRunSimplify()) {
	simplify();		simplify();
	}		}
	// Create node data objects.		// Create node data objects.
	for (Graph::NodeItr nItr = g.nodesBegin(), nEnd = g.nodesEnd();		for (Graph::NodeItr nItr = g.nodesBegin(), nEnd = g.nodesEnd();
	nItr != nEnd; ++nItr) {		nItr != nEnd; ++nItr) {
	nodeDataList.push_back(NodeData());		nodeDataList.push_back(NodeData());
	g.setNodeData(nItr, &nodeDataList.back());		g.setNodeData(*nItr, &nodeDataList.back());
	}		}
	// Create edge data objects.		// Create edge data objects.
	for (Graph::EdgeItr eItr = g.edgesBegin(), eEnd = g.edgesEnd();		for (Graph::EdgeItr eItr = g.edgesBegin(), eEnd = g.edgesEnd();
	eItr != eEnd; ++eItr) {		eItr != eEnd; ++eItr) {
	edgeDataList.push_back(EdgeData());		edgeDataList.push_back(EdgeData());
	g.setEdgeData(eItr, &edgeDataList.back());		g.setEdgeData(*eItr, &edgeDataList.back());
	addSolverEdge(eItr);		addSolverEdge(*eItr);
	}		}
	}		}
	void simplify() {		void simplify() {
	disconnectTrivialNodes();		disconnectTrivialNodes();
	eliminateIndependentEdges();		eliminateIndependentEdges();
	}		}
	// Eliminate trivial nodes.		// Eliminate trivial nodes.
	void disconnectTrivialNodes() {		void disconnectTrivialNodes() {
	unsigned numDisconnected = 0;		unsigned numDisconnected = 0;
	for (Graph::NodeItr nItr = g.nodesBegin(), nEnd = g.nodesEnd();		for (Graph::NodeItr nItr = g.nodesBegin(), nEnd = g.nodesEnd();
	nItr != nEnd; ++nItr) {		nItr != nEnd; ++nItr) {
	if (g.getNodeCosts(nItr).getLength() == 1) {		Graph::NodeId nId = *nItr;
	std::vector<Graph::EdgeItr> edgesToRemove;		if (g.getNodeCosts(nId).getLength() == 1) {
	for (Graph::AdjEdgeItr aeItr = g.adjEdgesBegin(nItr),		std::vector<Graph::EdgeId> edgesToRemove;
	aeEnd = g.adjEdgesEnd(nItr);
			for (Graph::AdjEdgeItr aeItr = g.adjEdgesBegin(nId),
			aeEnd = g.adjEdgesEnd(nId);
	aeItr != aeEnd; ++aeItr) {		aeItr != aeEnd; ++aeItr) {
	Graph::EdgeItr eItr = *aeItr;		Graph::EdgeId eId = *aeItr;
	if (g.getEdgeNode1(eItr) == nItr) {		if (g.getEdgeNode1(eId) == nId) {
	Graph::NodeItr otherNodeItr = g.getEdgeNode2(eItr);		Graph::NodeId otherNodeId = g.getEdgeNode2(eId);
	g.getNodeCosts(otherNodeItr) +=		g.getNodeCosts(otherNodeId) +=
	g.getEdgeCosts(eItr).getRowAsVector(0);		g.getEdgeCosts(eId).getRowAsVector(0);
	}		}
	else {		else {
	Graph::NodeItr otherNodeItr = g.getEdgeNode1(eItr);		Graph::NodeId otherNodeId = g.getEdgeNode1(eId);
	g.getNodeCosts(otherNodeItr) +=		g.getNodeCosts(otherNodeId) +=
	g.getEdgeCosts(eItr).getColAsVector(0);		g.getEdgeCosts(eId).getColAsVector(0);
	}		}
	edgesToRemove.push_back(eItr);		edgesToRemove.push_back(eId);
	}		}
	if (!edgesToRemove.empty())		if (!edgesToRemove.empty())
	++numDisconnected;		++numDisconnected;
	while (!edgesToRemove.empty()) {		while (!edgesToRemove.empty()) {
	g.removeEdge(edgesToRemove.back());		g.removeEdge(edgesToRemove.back());
	edgesToRemove.pop_back();		edgesToRemove.pop_back();
	}		}
	}		}
	}		}
	}		}
	void eliminateIndependentEdges() {		void eliminateIndependentEdges() {
	std::vector<Graph::EdgeItr> edgesToProcess;		std::vector<Graph::EdgeId> edgesToProcess;
	unsigned numEliminated = 0;		unsigned numEliminated = 0;
	for (Graph::EdgeItr eItr = g.edgesBegin(), eEnd = g.edgesEnd();		for (Graph::EdgeItr eItr = g.edgesBegin(), eEnd = g.edgesEnd();
	eItr != eEnd; ++eItr) {		eItr != eEnd; ++eItr) {
	edgesToProcess.push_back(eItr);		edgesToProcess.push_back(*eItr);
	}		}
	while (!edgesToProcess.empty()) {		while (!edgesToProcess.empty()) {
	if (tryToEliminateEdge(edgesToProcess.back()))		if (tryToEliminateEdge(edgesToProcess.back()))
	++numEliminated;		++numEliminated;
	edgesToProcess.pop_back();		edgesToProcess.pop_back();
	}		}
	}		}
	bool tryToEliminateEdge(Graph::EdgeItr eItr) {		bool tryToEliminateEdge(Graph::EdgeId eId) {
	if (tryNormaliseEdgeMatrix(eItr)) {		if (tryNormaliseEdgeMatrix(eId)) {
	g.removeEdge(eItr);		g.removeEdge(eId);
	return true;		return true;
	}		}
	return false;		return false;
	}		}
	bool tryNormaliseEdgeMatrix(Graph::EdgeItr &eItr) {		bool tryNormaliseEdgeMatrix(Graph::EdgeId &eId) {
	const PBQPNum infinity = std::numeric_limits<PBQPNum>::infinity();		const PBQPNum infinity = std::numeric_limits<PBQPNum>::infinity();
	Matrix &edgeCosts = g.getEdgeCosts(eItr);		Matrix &edgeCosts = g.getEdgeCosts(eId);
	Vector &uCosts = g.getNodeCosts(g.getEdgeNode1(eItr)),		Vector &uCosts = g.getNodeCosts(g.getEdgeNode1(eId)),
	&vCosts = g.getNodeCosts(g.getEdgeNode2(eItr));		&vCosts = g.getNodeCosts(g.getEdgeNode2(eId));
	for (unsigned r = 0; r < edgeCosts.getRows(); ++r) {		for (unsigned r = 0; r < edgeCosts.getRows(); ++r) {
	PBQPNum rowMin = infinity;		PBQPNum rowMin = infinity;
	for (unsigned c = 0; c < edgeCosts.getCols(); ++c) {		for (unsigned c = 0; c < edgeCosts.getCols(); ++c) {
	if (vCosts[c] != infinity && edgeCosts[r][c] < rowMin)		if (vCosts[c] != infinity && edgeCosts[r][c] < rowMin)
	rowMin = edgeCosts[r][c];		rowMin = edgeCosts[r][c];
	}		}
	uCosts[r] += rowMin;		uCosts[r] += rowMin;
	skipping to change at line 557		skipping to change at line 559
	return edgeCosts.isZero();		return edgeCosts.isZero();
	}		}
	void backpropagate() {		void backpropagate() {
	while (!stack.empty()) {		while (!stack.empty()) {
	computeSolution(stack.back());		computeSolution(stack.back());
	stack.pop_back();		stack.pop_back();
	}		}
	}		}
	void computeSolution(Graph::NodeItr nItr) {		void computeSolution(Graph::NodeId nId) {
	NodeData &nodeData = getSolverNodeData(nItr);		NodeData &nodeData = getSolverNodeData(nId);
	Vector v(g.getNodeCosts(nItr));		Vector v(g.getNodeCosts(nId));
	// Solve based on existing solved edges.		// Solve based on existing solved edges.
	for (SolverEdgeItr solvedEdgeItr = nodeData.solverEdgesBegin(),		for (SolverEdgeItr solvedEdgeItr = nodeData.solverEdgesBegin(),
	solvedEdgeEnd = nodeData.solverEdgesEnd();		solvedEdgeEnd = nodeData.solverEdgesEnd();
	solvedEdgeItr != solvedEdgeEnd; ++solvedEdgeItr) {		solvedEdgeItr != solvedEdgeEnd; ++solvedEdgeItr) {
	Graph::EdgeItr eItr(*solvedEdgeItr);		Graph::EdgeId eId(*solvedEdgeItr);
	Matrix &edgeCosts = g.getEdgeCosts(eItr);		Matrix &edgeCosts = g.getEdgeCosts(eId);
	if (nItr == g.getEdgeNode1(eItr)) {		if (nId == g.getEdgeNode1(eId)) {
	Graph::NodeItr adjNode(g.getEdgeNode2(eItr));		Graph::NodeId adjNode(g.getEdgeNode2(eId));
	unsigned adjSolution = s.getSelection(adjNode);		unsigned adjSolution = s.getSelection(adjNode);
	v += edgeCosts.getColAsVector(adjSolution);		v += edgeCosts.getColAsVector(adjSolution);
	}		}
	else {		else {
	Graph::NodeItr adjNode(g.getEdgeNode1(eItr));		Graph::NodeId adjNode(g.getEdgeNode1(eId));
	unsigned adjSolution = s.getSelection(adjNode);		unsigned adjSolution = s.getSelection(adjNode);
	v += edgeCosts.getRowAsVector(adjSolution);		v += edgeCosts.getRowAsVector(adjSolution);
	}		}
	}		}
	setSolution(nItr, v.minIndex());		setSolution(nId, v.minIndex());
	}		}
	void cleanup() {		void cleanup() {
	h.cleanup();		h.cleanup();
	nodeDataList.clear();		nodeDataList.clear();
	edgeDataList.clear();		edgeDataList.clear();
	}		}
	};		};
	/// \brief PBQP heuristic solver class.		/// \brief PBQP heuristic solver class.
End of changes. 77 change blocks.
	134 lines changed or deleted		136 lines changed or added

	Host.h		Host.h
	skipping to change at line 19		skipping to change at line 19
	//		//
	// Methods for querying the nature of the host machine.		// Methods for querying the nature of the host machine.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_SUPPORT_HOST_H		#ifndef LLVM_SUPPORT_HOST_H
	#define LLVM_SUPPORT_HOST_H		#define LLVM_SUPPORT_HOST_H
	#include "llvm/ADT/StringMap.h"		#include "llvm/ADT/StringMap.h"
	#if defined(__linux__)		#if defined(__linux__) || defined(__GNU__)
	#include <endian.h>		#include <endian.h>
	#else		#else
	#ifndef LLVM_ON_WIN32		#if !defined(BYTE_ORDER) && !defined(LLVM_ON_WIN32)
	#include <machine/endian.h>		#include <machine/endian.h>
	#endif		#endif
	#endif		#endif
	#include <string>		#include <string>
	namespace llvm {		namespace llvm {
	namespace sys {		namespace sys {
	#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && BYTE_ORDER == BIG_ENDIAN		#if defined(BYTE_ORDER) && defined(BIG_ENDIAN) && BYTE_ORDER == BIG_ENDIAN
End of changes. 2 change blocks.
	2 lines changed or deleted		2 lines changed or added

	IPO.h		IPO.h
	skipping to change at line 104		skipping to change at line 104
	Pass *createAlwaysInlinerPass(bool InsertLifetime);		Pass *createAlwaysInlinerPass(bool InsertLifetime);
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	/// createPruneEHPass - Return a new pass object which transforms invoke		/// createPruneEHPass - Return a new pass object which transforms invoke
	/// instructions into calls, if the callee can _not_ unwind the stack.		/// instructions into calls, if the callee can _not_ unwind the stack.
	///		///
	Pass *createPruneEHPass();		Pass *createPruneEHPass();
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	/// createInternalizePass - This pass loops over all of the functions in th e		/// createInternalizePass - This pass loops over all of the functions in th e
	/// input module, internalizing all globals (functions and variables) not i		/// input module, internalizing all globals (functions and variables) it ca
	n the		n.
	/// given exportList.		////
			/// The symbols in \p ExportList are never internalized.
			///
			/// The symbol in DSOList are internalized if it is safe to drop them from
			/// the symbol table.
	///		///
	/// Note that commandline options that are used with the above function are not		/// Note that commandline options that are used with the above function are not
	/// used now!		/// used now!
	ModulePass *createInternalizePass(ArrayRef<const char *> exportList);		ModulePass *createInternalizePass(ArrayRef<const char *> ExportList);
	/// createInternalizePass - Same as above, but with an empty exportList.		/// createInternalizePass - Same as above, but with an empty exportList.
	ModulePass *createInternalizePass();		ModulePass *createInternalizePass();
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	/// createDeadArgEliminationPass - This pass removes arguments from functio ns		/// createDeadArgEliminationPass - This pass removes arguments from functio ns
	/// which are not used by the body of the function.		/// which are not used by the body of the function.
	///		///
	ModulePass *createDeadArgEliminationPass();		ModulePass *createDeadArgEliminationPass();
	/// DeadArgHacking pass - Same as DAE, but delete arguments of external		/// DeadArgHacking pass - Same as DAE, but delete arguments of external
End of changes. 2 change blocks.
	4 lines changed or deleted		8 lines changed or added

	IRBuilder.h		IRBuilder.h
	skipping to change at line 28		skipping to change at line 28
	#include "llvm/ADT/ArrayRef.h"		#include "llvm/ADT/ArrayRef.h"
	#include "llvm/ADT/StringRef.h"		#include "llvm/ADT/StringRef.h"
	#include "llvm/ADT/Twine.h"		#include "llvm/ADT/Twine.h"
	#include "llvm/IR/BasicBlock.h"		#include "llvm/IR/BasicBlock.h"
	#include "llvm/IR/DataLayout.h"		#include "llvm/IR/DataLayout.h"
	#include "llvm/IR/Instructions.h"		#include "llvm/IR/Instructions.h"
	#include "llvm/IR/LLVMContext.h"		#include "llvm/IR/LLVMContext.h"
	#include "llvm/IR/Operator.h"		#include "llvm/IR/Operator.h"
	#include "llvm/Support/CBindingWrapping.h"		#include "llvm/Support/CBindingWrapping.h"
	#include "llvm/Support/ConstantFolder.h"		#include "llvm/Support/ConstantFolder.h"
			#include "llvm/Support/ValueHandle.h"
	namespace llvm {		namespace llvm {
	class MDNode;		class MDNode;
	/// \brief This provides the default implementation of the IRBuilder		/// \brief This provides the default implementation of the IRBuilder
	/// 'InsertHelper' method that is called whenever an instruction is created by		/// 'InsertHelper' method that is called whenever an instruction is created by
	/// IRBuilder and needs to be inserted.		/// IRBuilder and needs to be inserted.
	///		///
	/// By default, this inserts the instruction at the insertion point.		/// By default, this inserts the instruction at the insertion point.
	template <bool preserveNames = true>		template <bool preserveNames = true>
	skipping to change at line 52		skipping to change at line 53
	if (BB) BB->getInstList().insert(InsertPt, I);		if (BB) BB->getInstList().insert(InsertPt, I);
	if (preserveNames)		if (preserveNames)
	I->setName(Name);		I->setName(Name);
	}		}
	};		};
	/// \brief Common base class shared among various IRBuilders.		/// \brief Common base class shared among various IRBuilders.
	class IRBuilderBase {		class IRBuilderBase {
	DebugLoc CurDbgLocation;		DebugLoc CurDbgLocation;
	protected:		protected:
	/// Save the current debug location here while we are suppressing
	/// line table entries.
	llvm::DebugLoc SavedDbgLocation;
	BasicBlock *BB;		BasicBlock *BB;
	BasicBlock::iterator InsertPt;		BasicBlock::iterator InsertPt;
	LLVMContext &Context;		LLVMContext &Context;
			MDNode *DefaultFPMathTag;
			FastMathFlags FMF;
	public:		public:
	IRBuilderBase(LLVMContext &context)		IRBuilderBase(LLVMContext &context, MDNode *FPMathTag = 0)
	: Context(context) {		: Context(context), DefaultFPMathTag(FPMathTag), FMF() {
	ClearInsertionPoint();		ClearInsertionPoint();
	}		}
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	// Builder configuration methods		// Builder configuration methods
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	/// \brief Clear the insertion point: created instructions will not be		/// \brief Clear the insertion point: created instructions will not be
	/// inserted into a block.		/// inserted into a block.
	void ClearInsertionPoint() {		void ClearInsertionPoint() {
	BB = 0;		BB = 0;
			InsertPt = 0;
	}		}
	BasicBlock *GetInsertBlock() const { return BB; }		BasicBlock *GetInsertBlock() const { return BB; }
	BasicBlock::iterator GetInsertPoint() const { return InsertPt; }		BasicBlock::iterator GetInsertPoint() const { return InsertPt; }
	LLVMContext &getContext() const { return Context; }		LLVMContext &getContext() const { return Context; }
	/// \brief This specifies that created instructions should be appended to the		/// \brief This specifies that created instructions should be appended to the
	/// end of the specified block.		/// end of the specified block.
	void SetInsertPoint(BasicBlock *TheBB) {		void SetInsertPoint(BasicBlock *TheBB) {
	BB = TheBB;		BB = TheBB;
	InsertPt = BB->end();		InsertPt = BB->end();
	}		}
	/// \brief This specifies that created instructions should be inserted be fore		/// \brief This specifies that created instructions should be inserted be fore
	/// the specified instruction.		/// the specified instruction.
	void SetInsertPoint(Instruction *I) {		void SetInsertPoint(Instruction *I) {
	BB = I->getParent();		BB = I->getParent();
	InsertPt = I;		InsertPt = I;
			assert(I != BB->end() && "Can't read debug loc from end()");
	SetCurrentDebugLocation(I->getDebugLoc());		SetCurrentDebugLocation(I->getDebugLoc());
	}		}
	/// \brief This specifies that created instructions should be inserted at the		/// \brief This specifies that created instructions should be inserted at the
	/// specified point.		/// specified point.
	void SetInsertPoint(BasicBlock *TheBB, BasicBlock::iterator IP) {		void SetInsertPoint(BasicBlock *TheBB, BasicBlock::iterator IP) {
	BB = TheBB;		BB = TheBB;
	InsertPt = IP;		InsertPt = IP;
	}		}
	skipping to change at line 120		skipping to change at line 122
	return;		return;
	}		}
	SetInsertPoint(UseInst);		SetInsertPoint(UseInst);
	}		}
	/// \brief Set location information used by debugging information.		/// \brief Set location information used by debugging information.
	void SetCurrentDebugLocation(const DebugLoc &L) {		void SetCurrentDebugLocation(const DebugLoc &L) {
	CurDbgLocation = L;		CurDbgLocation = L;
	}		}
	/// \brief Temporarily suppress DebugLocations from being attached
	/// to emitted instructions, until the next call to
	/// SetCurrentDebugLocation() or EnableDebugLocations(). Use this
	/// if you want an instruction to be counted towards the prologue or
	/// if there is no useful source location.
	void DisableDebugLocations() {
	llvm::DebugLoc Empty;
	SavedDbgLocation = getCurrentDebugLocation();
	SetCurrentDebugLocation(Empty);
	}
	/// \brief Restore the previously saved DebugLocation.
	void EnableDebugLocations() {
	assert(CurDbgLocation.isUnknown());
	SetCurrentDebugLocation(SavedDbgLocation);
	}
	/// \brief Get location information used by debugging information.		/// \brief Get location information used by debugging information.
	DebugLoc getCurrentDebugLocation() const { return CurDbgLocation; }		DebugLoc getCurrentDebugLocation() const { return CurDbgLocation; }
	/// \brief If this builder has a current debug location, set it on the		/// \brief If this builder has a current debug location, set it on the
	/// specified instruction.		/// specified instruction.
	void SetInstDebugLocation(Instruction *I) const {		void SetInstDebugLocation(Instruction *I) const {
	if (!CurDbgLocation.isUnknown())		if (!CurDbgLocation.isUnknown())
	I->setDebugLoc(CurDbgLocation);		I->setDebugLoc(CurDbgLocation);
	}		}
	skipping to change at line 191		skipping to change at line 176
	}		}
	/// \brief Sets the current insert point to a previously-saved location.		/// \brief Sets the current insert point to a previously-saved location.
	void restoreIP(InsertPoint IP) {		void restoreIP(InsertPoint IP) {
	if (IP.isSet())		if (IP.isSet())
	SetInsertPoint(IP.getBlock(), IP.getPoint());		SetInsertPoint(IP.getBlock(), IP.getPoint());
	else		else
	ClearInsertionPoint();		ClearInsertionPoint();
	}		}
			/// \brief Get the floating point math metadata being used.
			MDNode *getDefaultFPMathTag() const { return DefaultFPMathTag; }
			/// \brief Get the flags to be applied to created floating point ops
			FastMathFlags getFastMathFlags() const { return FMF; }
			/// \brief Clear the fast-math flags.
			void clearFastMathFlags() { FMF.clear(); }
			/// \brief Set the floating point math metadata to be used.
			void SetDefaultFPMathTag(MDNode *FPMathTag) { DefaultFPMathTag = FPMathTa
			g; }
			/// \brief Set the fast-math flags to be used with generated fp-math oper
			ators
			void SetFastMathFlags(FastMathFlags NewFMF) { FMF = NewFMF; }
			//===--------------------------------------------------------------------
			===//
			// RAII helpers.
			//===--------------------------------------------------------------------
			===//
			// \brief RAII object that stores the current insertion point and restore
			s it
			// when the object is destroyed. This includes the debug location.
			class InsertPointGuard {
			IRBuilderBase &Builder;
			AssertingVH<BasicBlock> Block;
			BasicBlock::iterator Point;
			DebugLoc DbgLoc;
			InsertPointGuard(const InsertPointGuard &) LLVM_DELETED_FUNCTION;
			InsertPointGuard &operator=(const InsertPointGuard &) LLVM_DELETED_FUNC
			TION;
			public:
			InsertPointGuard(IRBuilderBase &B)
			: Builder(B), Block(B.GetInsertBlock()), Point(B.GetInsertPoint()),
			DbgLoc(B.getCurrentDebugLocation()) {}
			~InsertPointGuard() {
			Builder.restoreIP(InsertPoint(Block, Point));
			Builder.SetCurrentDebugLocation(DbgLoc);
			}
			};
			// \brief RAII object that stores the current fast math settings and rest
			ores
			// them when the object is destroyed.
			class FastMathFlagGuard {
			IRBuilderBase &Builder;
			FastMathFlags FMF;
			MDNode *FPMathTag;
			FastMathFlagGuard(const FastMathFlagGuard &) LLVM_DELETED_FUNCTION;
			FastMathFlagGuard &operator=(
			const FastMathFlagGuard &) LLVM_DELETED_FUNCTION;
			public:
			FastMathFlagGuard(IRBuilderBase &B)
			: Builder(B), FMF(B.FMF), FPMathTag(B.DefaultFPMathTag) {}
			~FastMathFlagGuard() {
			Builder.FMF = FMF;
			Builder.DefaultFPMathTag = FPMathTag;
			}
			};
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	// Miscellaneous creation methods.		// Miscellaneous creation methods.
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	/// \brief Make a new global variable with initializer type i8*		/// \brief Make a new global variable with initializer type i8*
	///		///
	/// Make a new global variable with an initializer that has array of i8 t ype		/// Make a new global variable with an initializer that has array of i8 t ype
	/// filled in with the null terminated string value specified. The new g lobal		/// filled in with the null terminated string value specified. The new g lobal
	/// variable will be marked mergable with any others of the same contents . If		/// variable will be marked mergable with any others of the same contents . If
	/// Name is specified, it is the name of the global variable created.		/// Name is specified, it is the name of the global variable created.
	skipping to change at line 293		skipping to change at line 340
	Type *getVoidTy() {		Type *getVoidTy() {
	return Type::getVoidTy(Context);		return Type::getVoidTy(Context);
	}		}
	/// \brief Fetch the type representing a pointer to an 8-bit integer valu e.		/// \brief Fetch the type representing a pointer to an 8-bit integer valu e.
	PointerType *getInt8PtrTy(unsigned AddrSpace = 0) {		PointerType *getInt8PtrTy(unsigned AddrSpace = 0) {
	return Type::getInt8PtrTy(Context, AddrSpace);		return Type::getInt8PtrTy(Context, AddrSpace);
	}		}
	/// \brief Fetch the type representing a pointer to an integer value.		/// \brief Fetch the type representing a pointer to an integer value.
	IntegerType* getIntPtrTy(DataLayout *DL, unsigned AddrSpace = 0) {		IntegerType* getIntPtrTy(const DataLayout *DL, unsigned AddrSpace = 0) {
	return DL->getIntPtrType(Context, AddrSpace);		return DL->getIntPtrType(Context, AddrSpace);
	}		}
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	// Intrinsic creation methods		// Intrinsic creation methods
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	/// \brief Create and insert a memset to the specified pointer and the		/// \brief Create and insert a memset to the specified pointer and the
	/// specified value.		/// specified value.
	///		///
	skipping to change at line 376		skipping to change at line 423
	/// The first template argument handles whether or not to preserve names in the		/// The first template argument handles whether or not to preserve names in the
	/// final instruction output. This defaults to on. The second template arg ument		/// final instruction output. This defaults to on. The second template arg ument
	/// specifies a class to use for creating constants. This defaults to crea ting		/// specifies a class to use for creating constants. This defaults to crea ting
	/// minimally folded constants. The fourth template argument allows client s to		/// minimally folded constants. The fourth template argument allows client s to
	/// specify custom insertion hooks that are called on every newly created		/// specify custom insertion hooks that are called on every newly created
	/// insertion.		/// insertion.
	template<bool preserveNames = true, typename T = ConstantFolder,		template<bool preserveNames = true, typename T = ConstantFolder,
	typename Inserter = IRBuilderDefaultInserter<preserveNames> >		typename Inserter = IRBuilderDefaultInserter<preserveNames> >
	class IRBuilder : public IRBuilderBase, public Inserter {		class IRBuilder : public IRBuilderBase, public Inserter {
	T Folder;		T Folder;
	MDNode *DefaultFPMathTag;
	FastMathFlags FMF;
	public:		public:
	IRBuilder(LLVMContext &C, const T &F, const Inserter &I = Inserter(),		IRBuilder(LLVMContext &C, const T &F, const Inserter &I = Inserter(),
	MDNode *FPMathTag = 0)		MDNode *FPMathTag = 0)
	: IRBuilderBase(C), Inserter(I), Folder(F), DefaultFPMathTag(FPMathTag)		: IRBuilderBase(C, FPMathTag), Inserter(I), Folder(F) {
	,
	FMF() {
	}		}
	explicit IRBuilder(LLVMContext &C, MDNode *FPMathTag = 0)		explicit IRBuilder(LLVMContext &C, MDNode *FPMathTag = 0)
	: IRBuilderBase(C), Folder(), DefaultFPMathTag(FPMathTag), FMF() {		: IRBuilderBase(C, FPMathTag), Folder() {
	}		}
	explicit IRBuilder(BasicBlock *TheBB, const T &F, MDNode *FPMathTag = 0)		explicit IRBuilder(BasicBlock *TheBB, const T &F, MDNode *FPMathTag = 0)
	: IRBuilderBase(TheBB->getContext()), Folder(F),		: IRBuilderBase(TheBB->getContext(), FPMathTag), Folder(F) {
	DefaultFPMathTag(FPMathTag), FMF() {
	SetInsertPoint(TheBB);		SetInsertPoint(TheBB);
	}		}
	explicit IRBuilder(BasicBlock *TheBB, MDNode *FPMathTag = 0)		explicit IRBuilder(BasicBlock *TheBB, MDNode *FPMathTag = 0)
	: IRBuilderBase(TheBB->getContext()), Folder(),		: IRBuilderBase(TheBB->getContext(), FPMathTag), Folder() {
	DefaultFPMathTag(FPMathTag), FMF() {
	SetInsertPoint(TheBB);		SetInsertPoint(TheBB);
	}		}
	explicit IRBuilder(Instruction *IP, MDNode *FPMathTag = 0)		explicit IRBuilder(Instruction *IP, MDNode *FPMathTag = 0)
	: IRBuilderBase(IP->getContext()), Folder(), DefaultFPMathTag(FPMathTag		: IRBuilderBase(IP->getContext(), FPMathTag), Folder() {
	),
	FMF() {
	SetInsertPoint(IP);		SetInsertPoint(IP);
	SetCurrentDebugLocation(IP->getDebugLoc());		SetCurrentDebugLocation(IP->getDebugLoc());
	}		}
	explicit IRBuilder(Use &U, MDNode *FPMathTag = 0)		explicit IRBuilder(Use &U, MDNode *FPMathTag = 0)
	: IRBuilderBase(U->getContext()), Folder(), DefaultFPMathTag(FPMathTag)		: IRBuilderBase(U->getContext(), FPMathTag), Folder() {
	,
	FMF() {
	SetInsertPoint(U);		SetInsertPoint(U);
	SetCurrentDebugLocation(cast<Instruction>(U.getUser())->getDebugLoc());		SetCurrentDebugLocation(cast<Instruction>(U.getUser())->getDebugLoc());
	}		}
	IRBuilder(BasicBlock *TheBB, BasicBlock::iterator IP, const T& F,		IRBuilder(BasicBlock *TheBB, BasicBlock::iterator IP, const T& F,
	MDNode *FPMathTag = 0)		MDNode *FPMathTag = 0)
	: IRBuilderBase(TheBB->getContext()), Folder(F),		: IRBuilderBase(TheBB->getContext(), FPMathTag), Folder(F) {
	DefaultFPMathTag(FPMathTag), FMF() {
	SetInsertPoint(TheBB, IP);		SetInsertPoint(TheBB, IP);
	}		}
	IRBuilder(BasicBlock *TheBB, BasicBlock::iterator IP, MDNode *FPMathTag = 0)		IRBuilder(BasicBlock *TheBB, BasicBlock::iterator IP, MDNode *FPMathTag = 0)
	: IRBuilderBase(TheBB->getContext()), Folder(),		: IRBuilderBase(TheBB->getContext(), FPMathTag), Folder() {
	DefaultFPMathTag(FPMathTag), FMF() {
	SetInsertPoint(TheBB, IP);		SetInsertPoint(TheBB, IP);
	}		}
	/// \brief Get the constant folder being used.		/// \brief Get the constant folder being used.
	const T &getFolder() { return Folder; }		const T &getFolder() { return Folder; }
	/// \brief Get the floating point math metadata being used.
	MDNode *getDefaultFPMathTag() const { return DefaultFPMathTag; }
	/// \brief Get the flags to be applied to created floating point ops
	FastMathFlags getFastMathFlags() const { return FMF; }
	/// \brief Clear the fast-math flags.
	void clearFastMathFlags() { FMF.clear(); }
	/// \brief SetDefaultFPMathTag - Set the floating point math metadata to
	be used.
	void SetDefaultFPMathTag(MDNode *FPMathTag) { DefaultFPMathTag = FPMathTa
	g; }
	/// \brief Set the fast-math flags to be used with generated fp-math oper
	ators
	void SetFastMathFlags(FastMathFlags NewFMF) { FMF = NewFMF; }
	/// \brief Return true if this builder is configured to actually add the		/// \brief Return true if this builder is configured to actually add the
	/// requested names to IR created through it.		/// requested names to IR created through it.
	bool isNamePreserving() const { return preserveNames; }		bool isNamePreserving() const { return preserveNames; }
	/// \brief Insert and return the specified instruction.		/// \brief Insert and return the specified instruction.
	template<typename InstTy>		template<typename InstTy>
	InstTy *Insert(InstTy *I, const Twine &Name = "") const {		InstTy *Insert(InstTy *I, const Twine &Name = "") const {
	this->InsertHelper(I, Name, BB, InsertPt);		this->InsertHelper(I, Name, BB, InsertPt);
	this->SetInstDebugLocation(I);		this->SetInstDebugLocation(I);
	return I;		return I;
	skipping to change at line 1113		skipping to change at line 1136
	return CreateCast(Instruction::PtrToInt, V, DestTy, Name);		return CreateCast(Instruction::PtrToInt, V, DestTy, Name);
	}		}
	Value *CreateIntToPtr(Value *V, Type *DestTy,		Value *CreateIntToPtr(Value *V, Type *DestTy,
	const Twine &Name = "") {		const Twine &Name = "") {
	return CreateCast(Instruction::IntToPtr, V, DestTy, Name);		return CreateCast(Instruction::IntToPtr, V, DestTy, Name);
	}		}
	Value *CreateBitCast(Value *V, Type *DestTy,		Value *CreateBitCast(Value *V, Type *DestTy,
	const Twine &Name = "") {		const Twine &Name = "") {
	return CreateCast(Instruction::BitCast, V, DestTy, Name);		return CreateCast(Instruction::BitCast, V, DestTy, Name);
	}		}
			Value *CreateAddrSpaceCast(Value *V, Type *DestTy,
			const Twine &Name = "") {
			return CreateCast(Instruction::AddrSpaceCast, V, DestTy, Name);
			}
	Value *CreateZExtOrBitCast(Value *V, Type *DestTy,		Value *CreateZExtOrBitCast(Value *V, Type *DestTy,
	const Twine &Name = "") {		const Twine &Name = "") {
	if (V->getType() == DestTy)		if (V->getType() == DestTy)
	return V;		return V;
	if (Constant *VC = dyn_cast<Constant>(V))		if (Constant *VC = dyn_cast<Constant>(V))
	return Insert(Folder.CreateZExtOrBitCast(VC, DestTy), Name);		return Insert(Folder.CreateZExtOrBitCast(VC, DestTy), Name);
	return Insert(CastInst::CreateZExtOrBitCast(V, DestTy), Name);		return Insert(CastInst::CreateZExtOrBitCast(V, DestTy), Name);
	}		}
	Value *CreateSExtOrBitCast(Value *V, Type *DestTy,		Value *CreateSExtOrBitCast(Value *V, Type *DestTy,
	const Twine &Name = "") {		const Twine &Name = "") {
End of changes. 20 change blocks.
	62 lines changed or deleted		90 lines changed or added

	IRReader.h		IRReader.h
	//===---- llvm/IRReader/IRReader.h - Reader for LLVM IR files ---*- C++ -*-		/*===-- llvm-c/IRReader.h - IR Reader C Interface -----------------*- C -*-
	===//		===*\
	//		|*
	// The LLVM Compiler Infrastructure		*|
	//		|* The LLVM Compiler Infrastructure
	// This file is distributed under the University of Illinois Open Source		*|
	// License. See LICENSE.TXT for details.		|*
	//		*|
	//===----------------------------------------------------------------------		|* This file is distributed under the University of Illinois Open Source
	===//		*|
	//		|* License. See LICENSE.TXT for details.
	// This file defines functions for reading LLVM IR. They support both		*|
	// Bitcode and Assembly, automatically detecting the input format.		|*
	//		*|
	//===----------------------------------------------------------------------		|*===----------------------------------------------------------------------
	===//		===*|
			|*
	#ifndef LLVM_IRREADER_IRREADER_H		*|
	#define LLVM_IRREADER_IRREADER_H		|* This file defines the C interface to the IR Reader.
			*|
	#include <string>		|*
			*|
	namespace llvm {		\*===----------------------------------------------------------------------
			===*/
	class Module;
	class MemoryBuffer;
	class SMDiagnostic;
	class LLVMContext;
	/// If the given MemoryBuffer holds a bitcode image, return a Module for it
	/// which does lazy deserialization of function bodies. Otherwise, attempt
	to
	/// parse it as LLVM Assembly and return a fully populated Module. This
	/// function *always* takes ownership of the given MemoryBuffer.
	Module *getLazyIRModule(MemoryBuffer *Buffer, SMDiagnostic &Err,
	LLVMContext &Context);
	/// If the given file holds a bitcode image, return a Module
	/// for it which does lazy deserialization of function bodies. Otherwise,
	/// attempt to parse it as LLVM Assembly and return a fully populated
	/// Module.
	Module *getLazyIRFileModule(const std::string &Filename, SMDiagnostic &Err,
	LLVMContext &Context);
	/// If the given MemoryBuffer holds a bitcode image, return a Module
	/// for it. Otherwise, attempt to parse it as LLVM Assembly and return
	/// a Module for it. This function *always* takes ownership of the given
	/// MemoryBuffer.
	Module *ParseIR(MemoryBuffer *Buffer, SMDiagnostic &Err, LLVMContext &Conte
	xt);
	/// If the given file holds a bitcode image, return a Module for it.
	/// Otherwise, attempt to parse it as LLVM Assembly and return a Module
	/// for it.
	Module *ParseIRFile(const std::string &Filename, SMDiagnostic &Err,
	LLVMContext &Context);
			#ifndef LLVM_C_IRREADER_H
			#define LLVM_C_IRREADER_H
			#include "llvm-c/Core.h"
			#ifdef __cplusplus
			extern "C" {
			#endif
			/**
			* Read LLVM IR from a memory buffer and convert it into an in-memory Modul
			e
			* object. Returns 0 on success.
			* Optionally returns a human-readable description of any errors that
			* occured during parsing IR. OutMessage must be disposed with
			* LLVMDisposeMessage.
			*
			* @see llvm::ParseIR()
			*/
			LLVMBool LLVMParseIRInContext(LLVMContextRef ContextRef,
			LLVMMemoryBufferRef MemBuf, LLVMModuleRef *Ou
			tM,
			char **OutMessage);
			#ifdef __cplusplus
	}		}
			#endif
	#endif		#endif
End of changes. 3 change blocks.
	56 lines changed or deleted		50 lines changed or added

	ISDOpcodes.h		ISDOpcodes.h
	skipping to change at line 80		skipping to change at line 80
	/// of the frame or return address to return. An index of zero corresp onds		/// of the frame or return address to return. An index of zero corresp onds
	/// to the current function's frame or return address, an index of one to		/// to the current function's frame or return address, an index of one to
	/// the parent's frame or return address, and so on.		/// the parent's frame or return address, and so on.
	FRAMEADDR, RETURNADDR,		FRAMEADDR, RETURNADDR,
	/// FRAME_TO_ARGS_OFFSET - This node represents offset from frame point er to		/// FRAME_TO_ARGS_OFFSET - This node represents offset from frame point er to
	/// first (possible) on-stack argument. This is needed for correct stac k		/// first (possible) on-stack argument. This is needed for correct stac k
	/// adjustment during unwind.		/// adjustment during unwind.
	FRAME_TO_ARGS_OFFSET,		FRAME_TO_ARGS_OFFSET,
	/// RESULT, OUTCHAIN = EXCEPTIONADDR(INCHAIN) - This node represents th
	e
	/// address of the exception block on entry to an landing pad block.
	EXCEPTIONADDR,
	/// RESULT, OUTCHAIN = LSDAADDR(INCHAIN) - This node represents the
	/// address of the Language Specific Data Area for the enclosing functi
	on.
	LSDAADDR,
	/// RESULT, OUTCHAIN = EHSELECTION(INCHAIN, EXCEPTION) - This node
	/// represents the selection index of the exception thrown.
	EHSELECTION,
	/// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represen ts		/// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represen ts
	/// 'eh_return' gcc dwarf builtin, which is used to return from		/// 'eh_return' gcc dwarf builtin, which is used to return from
	/// exception. The general meaning is: adjust stack by OFFSET and pass		/// exception. The general meaning is: adjust stack by OFFSET and pass
	/// execution to HANDLER. Many platform-related details also :)		/// execution to HANDLER. Many platform-related details also :)
	EH_RETURN,		EH_RETURN,
	/// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer)		/// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer)
	/// This corresponds to the eh.sjlj.setjmp intrinsic.		/// This corresponds to the eh.sjlj.setjmp intrinsic.
	/// It takes an input chain and a pointer to the jump buffer as inputs		/// It takes an input chain and a pointer to the jump buffer as inputs
	/// and returns an outchain.		/// and returns an outchain.
	skipping to change at line 434		skipping to change at line 422
	/// BITCAST - This operator converts between integer, vector and FP		/// BITCAST - This operator converts between integer, vector and FP
	/// values, as if the value was stored to memory with one type and load ed		/// values, as if the value was stored to memory with one type and load ed
	/// from the same address with the other type (or equivalently for vect or		/// from the same address with the other type (or equivalently for vect or
	/// format conversions, etc). The source and result are required to ha ve		/// format conversions, etc). The source and result are required to ha ve
	/// the same bit size (e.g. f32 <-> i32). This can also be used for		/// the same bit size (e.g. f32 <-> i32). This can also be used for
	/// int-to-int or fp-to-fp conversions, but that is a noop, deleted by		/// int-to-int or fp-to-fp conversions, but that is a noop, deleted by
	/// getNode().		/// getNode().
	BITCAST,		BITCAST,
			/// ADDRSPACECAST - This operator converts between pointers of differen
			t
			/// address spaces.
			ADDRSPACECAST,
	/// CONVERT_RNDSAT - This operator is used to support various conversio ns		/// CONVERT_RNDSAT - This operator is used to support various conversio ns
	/// between various types (float, signed, unsigned and vectors of those		/// between various types (float, signed, unsigned and vectors of those
	/// types) with rounding and saturation. NOTE: Avoid using this operato r as		/// types) with rounding and saturation. NOTE: Avoid using this operato r as
	/// most target don't support it and the operator might be removed in t he		/// most target don't support it and the operator might be removed in t he
	/// future. It takes the following arguments:		/// future. It takes the following arguments:
	/// 0) value		/// 0) value
	/// 1) dest type (type to convert to)		/// 1) dest type (type to convert to)
	/// 2) src type (type to convert from)		/// 2) src type (type to convert from)
	/// 3) rounding imm		/// 3) rounding imm
	/// 4) saturation imm		/// 4) saturation imm
	skipping to change at line 455		skipping to change at line 447
	CONVERT_RNDSAT,		CONVERT_RNDSAT,
	/// FP16_TO_FP32, FP32_TO_FP16 - These operators are used to perform		/// FP16_TO_FP32, FP32_TO_FP16 - These operators are used to perform
	/// promotions and truncation for half-precision (16 bit) floating		/// promotions and truncation for half-precision (16 bit) floating
	/// numbers. We need special nodes since FP16 is a storage-only type wi th		/// numbers. We need special nodes since FP16 is a storage-only type wi th
	/// special semantics of operations.		/// special semantics of operations.
	FP16_TO_FP32, FP32_TO_FP16,		FP16_TO_FP32, FP32_TO_FP16,
	/// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,		/// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
	/// FLOG, FLOG2, FLOG10, FEXP, FEXP2,		/// FLOG, FLOG2, FLOG10, FEXP, FEXP2,
	/// FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR - Perform various unary		/// FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary
	/// floating point operations. These are inspired by libm.		/// floating point operations. These are inspired by libm.
	FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,		FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
	FLOG, FLOG2, FLOG10, FEXP, FEXP2,		FLOG, FLOG2, FLOG10, FEXP, FEXP2,
	FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR,		FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR,
	/// FSINCOS - Compute both fsin and fcos as a single operation.		/// FSINCOS - Compute both fsin and fcos as a single operation.
	FSINCOS,		FSINCOS,
	/// LOAD and STORE have token chains as their first operand, then the s ame		/// LOAD and STORE have token chains as their first operand, then the s ame
	/// operands as an LLVM load/store instruction, then an offset node tha t		/// operands as an LLVM load/store instruction, then an offset node tha t
	/// is added / subtracted from the base pointer to form the address (fo r		/// is added / subtracted from the base pointer to form the address (fo r
	/// indexed memory ops).		/// indexed memory ops).
	LOAD, STORE,		LOAD, STORE,
	skipping to change at line 619		skipping to change at line 611
	/// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr)		/// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr)
	/// This corresponds to "load atomic" instruction.		/// This corresponds to "load atomic" instruction.
	ATOMIC_LOAD,		ATOMIC_LOAD,
	/// OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr, val)		/// OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr, val)
	/// This corresponds to "store atomic" instruction.		/// This corresponds to "store atomic" instruction.
	ATOMIC_STORE,		ATOMIC_STORE,
	/// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)		/// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
			/// For double-word atomic operations:
			/// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi
			,
			/// swapLo, swapHi)
	/// This corresponds to the cmpxchg instruction.		/// This corresponds to the cmpxchg instruction.
	ATOMIC_CMP_SWAP,		ATOMIC_CMP_SWAP,
	/// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt)		/// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt)
	/// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt)		/// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt)
			/// For double-word atomic operations:
			/// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi)
			/// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo,
			amtHi)
	/// These correspond to the atomicrmw instruction.		/// These correspond to the atomicrmw instruction.
	ATOMIC_SWAP,		ATOMIC_SWAP,
	ATOMIC_LOAD_ADD,		ATOMIC_LOAD_ADD,
	ATOMIC_LOAD_SUB,		ATOMIC_LOAD_SUB,
	ATOMIC_LOAD_AND,		ATOMIC_LOAD_AND,
	ATOMIC_LOAD_OR,		ATOMIC_LOAD_OR,
	ATOMIC_LOAD_XOR,		ATOMIC_LOAD_XOR,
	ATOMIC_LOAD_NAND,		ATOMIC_LOAD_NAND,
	ATOMIC_LOAD_MIN,		ATOMIC_LOAD_MIN,
	ATOMIC_LOAD_MAX,		ATOMIC_LOAD_MAX,
	skipping to change at line 650		skipping to change at line 648
	/// BUILTIN_OP_END - This must be the last enum value in this list.		/// BUILTIN_OP_END - This must be the last enum value in this list.
	/// The target-specific pre-isel opcode values start here.		/// The target-specific pre-isel opcode values start here.
	BUILTIN_OP_END		BUILTIN_OP_END
	};		};
	/// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations		/// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations
	/// which do not reference a specific memory location should be less than		/// which do not reference a specific memory location should be less than
	/// this value. Those that do must not be less than this value, and can		/// this value. Those that do must not be less than this value, and can
	/// be used with SelectionDAG::getMemIntrinsicNode.		/// be used with SelectionDAG::getMemIntrinsicNode.
	static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+150;		static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+180;
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	/// MemIndexedMode enum - This enum defines the load / store indexed		/// MemIndexedMode enum - This enum defines the load / store indexed
	/// addressing modes.		/// addressing modes.
	///		///
	/// UNINDEXED "Normal" load / store. The effective address is already		/// UNINDEXED "Normal" load / store. The effective address is already
	/// computed and is available in the base pointer. The offse t		/// computed and is available in the base pointer. The offse t
	/// operand is always undefined. In addition to producing a		/// operand is always undefined. In addition to producing a
	/// chain, an unindexed load produces one value (result of t he		/// chain, an unindexed load produces one value (result of t he
	/// load); an unindexed store does not produce a value.		/// load); an unindexed store does not produce a value.
End of changes. 7 change blocks.
	17 lines changed or deleted		16 lines changed or added

	ImmutableMap.h		ImmutableMap.h
	skipping to change at line 213		skipping to change at line 213
	//===--------------------------------------------------===//		//===--------------------------------------------------===//
	class iterator {		class iterator {
	typename TreeTy::iterator itr;		typename TreeTy::iterator itr;
	iterator() {}		iterator() {}
	iterator(TreeTy* t) : itr(t) {}		iterator(TreeTy* t) : itr(t) {}
	friend class ImmutableMap;		friend class ImmutableMap;
	public:		public:
			typedef ptrdiff_t difference_type;
	typedef typename ImmutableMap<KeyT,ValT,ValInfo>::value_type value_type ;		typedef typename ImmutableMap<KeyT,ValT,ValInfo>::value_type value_type ;
	typedef typename ImmutableMap<KeyT,ValT,ValInfo>::value_type_ref refere nce;		typedef typename ImmutableMap<KeyT,ValT,ValInfo>::value_type_ref refere nce;
	typedef typename iterator::value_type *pointer;		typedef typename iterator::value_type *pointer;
	typedef std::bidirectional_iterator_tag iterator_category;		typedef std::bidirectional_iterator_tag iterator_category;
	typename iterator::reference operator*() const { return itr->getValue() ; }		typename iterator::reference operator*() const { return itr->getValue() ; }
	typename iterator::pointer operator->() const { return &itr->getValue (); }		typename iterator::pointer operator->() const { return &itr->getValue (); }
	key_type_ref getKey() const { return itr->getValue().first; }		key_type_ref getKey() const { return itr->getValue().first; }
	data_type_ref getData() const { return itr->getValue().second; }		data_type_ref getData() const { return itr->getValue().second; }
End of changes. 1 change blocks.
	0 lines changed or deleted		1 lines changed or added

	ImmutableSet.h		ImmutableSet.h
	skipping to change at line 852		skipping to change at line 852
	PROFILE_INTEGER_INFO(unsigned short)		PROFILE_INTEGER_INFO(unsigned short)
	PROFILE_INTEGER_INFO(unsigned)		PROFILE_INTEGER_INFO(unsigned)
	PROFILE_INTEGER_INFO(signed)		PROFILE_INTEGER_INFO(signed)
	PROFILE_INTEGER_INFO(long)		PROFILE_INTEGER_INFO(long)
	PROFILE_INTEGER_INFO(unsigned long)		PROFILE_INTEGER_INFO(unsigned long)
	PROFILE_INTEGER_INFO(long long)		PROFILE_INTEGER_INFO(long long)
	PROFILE_INTEGER_INFO(unsigned long long)		PROFILE_INTEGER_INFO(unsigned long long)
	#undef PROFILE_INTEGER_INFO		#undef PROFILE_INTEGER_INFO
			/// Profile traits for booleans.
			template <>
			struct ImutProfileInfo<bool> {
			typedef const bool value_type;
			typedef const bool& value_type_ref;
			static inline void Profile(FoldingSetNodeID& ID, value_type_ref X) {
			ID.AddBoolean(X);
			}
			};
	/// Generic profile trait for pointer types. We treat pointers as		/// Generic profile trait for pointer types. We treat pointers as
	/// references to unique objects.		/// references to unique objects.
	template <typename T>		template <typename T>
	struct ImutProfileInfo<T*> {		struct ImutProfileInfo<T*> {
	typedef const T* value_type;		typedef const T* value_type;
	typedef value_type value_type_ref;		typedef value_type value_type_ref;
	static inline void Profile(FoldingSetNodeID &ID, value_type_ref X) {		static inline void Profile(FoldingSetNodeID &ID, value_type_ref X) {
	ID.AddPointer(X);		ID.AddPointer(X);
	}		}
	skipping to change at line 1060		skipping to change at line 1071
	//===--------------------------------------------------===//		//===--------------------------------------------------===//
	class iterator {		class iterator {
	typename TreeTy::iterator itr;		typename TreeTy::iterator itr;
	iterator() {}		iterator() {}
	iterator(TreeTy* t) : itr(t) {}		iterator(TreeTy* t) : itr(t) {}
	friend class ImmutableSet<ValT,ValInfo>;		friend class ImmutableSet<ValT,ValInfo>;
	public:		public:
			typedef ptrdiff_t difference_type;
	typedef typename ImmutableSet<ValT,ValInfo>::value_type value_type;		typedef typename ImmutableSet<ValT,ValInfo>::value_type value_type;
	typedef typename ImmutableSet<ValT,ValInfo>::value_type_ref reference;		typedef typename ImmutableSet<ValT,ValInfo>::value_type_ref reference;
	typedef typename iterator::value_type *pointer;		typedef typename iterator::value_type *pointer;
	typedef std::bidirectional_iterator_tag iterator_category;		typedef std::bidirectional_iterator_tag iterator_category;
	typename iterator::reference operator*() const { return itr->getValue() ; }		typename iterator::reference operator*() const { return itr->getValue() ; }
	typename iterator::pointer operator->() const { return &(operator*()) ; }		typename iterator::pointer operator->() const { return &(operator*()) ; }
	iterator& operator++() { ++itr; return *this; }		iterator& operator++() { ++itr; return *this; }
	iterator operator++(int) { iterator tmp(*this); ++itr; return tmp; }		iterator operator++(int) { iterator tmp(*this); ++itr; return tmp; }
End of changes. 2 change blocks.
	0 lines changed or deleted		12 lines changed or added

	InitializePasses.h		InitializePasses.h
	skipping to change at line 73		skipping to change at line 73
	void initializeTarget(PassRegistry&);		void initializeTarget(PassRegistry&);
	void initializeAAEvalPass(PassRegistry&);		void initializeAAEvalPass(PassRegistry&);
	void initializeADCEPass(PassRegistry&);		void initializeADCEPass(PassRegistry&);
	void initializeAliasAnalysisAnalysisGroup(PassRegistry&);		void initializeAliasAnalysisAnalysisGroup(PassRegistry&);
	void initializeAliasAnalysisCounterPass(PassRegistry&);		void initializeAliasAnalysisCounterPass(PassRegistry&);
	void initializeAliasDebuggerPass(PassRegistry&);		void initializeAliasDebuggerPass(PassRegistry&);
	void initializeAliasSetPrinterPass(PassRegistry&);		void initializeAliasSetPrinterPass(PassRegistry&);
	void initializeAlwaysInlinerPass(PassRegistry&);		void initializeAlwaysInlinerPass(PassRegistry&);
	void initializeArgPromotionPass(PassRegistry&);		void initializeArgPromotionPass(PassRegistry&);
			void initializeSampleProfileLoaderPass(PassRegistry&);
	void initializeBarrierNoopPass(PassRegistry&);		void initializeBarrierNoopPass(PassRegistry&);
	void initializeBasicAliasAnalysisPass(PassRegistry&);		void initializeBasicAliasAnalysisPass(PassRegistry&);
	void initializeBasicCallGraphPass(PassRegistry&);		void initializeCallGraphPass(PassRegistry&);
	void initializeBasicTTIPass(PassRegistry&);		void initializeBasicTTIPass(PassRegistry&);
	void initializeBlockExtractorPassPass(PassRegistry&);		void initializeBlockExtractorPassPass(PassRegistry&);
	void initializeBlockFrequencyInfoPass(PassRegistry&);		void initializeBlockFrequencyInfoPass(PassRegistry&);
	void initializeBlockPlacementPass(PassRegistry&);
	void initializeBoundsCheckingPass(PassRegistry&);		void initializeBoundsCheckingPass(PassRegistry&);
	void initializeBranchFolderPassPass(PassRegistry&);		void initializeBranchFolderPassPass(PassRegistry&);
	void initializeBranchProbabilityInfoPass(PassRegistry&);		void initializeBranchProbabilityInfoPass(PassRegistry&);
	void initializeBreakCriticalEdgesPass(PassRegistry&);		void initializeBreakCriticalEdgesPass(PassRegistry&);
	void initializeCallGraphPrinterPass(PassRegistry&);		void initializeCallGraphPrinterPass(PassRegistry&);
	void initializeCallGraphViewerPass(PassRegistry&);		void initializeCallGraphViewerPass(PassRegistry&);
	void initializeCFGOnlyPrinterPass(PassRegistry&);		void initializeCFGOnlyPrinterPass(PassRegistry&);
	void initializeCFGOnlyViewerPass(PassRegistry&);		void initializeCFGOnlyViewerPass(PassRegistry&);
	void initializeCFGPrinterPass(PassRegistry&);		void initializeCFGPrinterPass(PassRegistry&);
	void initializeCFGSimplifyPassPass(PassRegistry&);		void initializeCFGSimplifyPassPass(PassRegistry&);
			void initializeFlattenCFGPassPass(PassRegistry&);
			void initializeStructurizeCFGPass(PassRegistry&);
	void initializeCFGViewerPass(PassRegistry&);		void initializeCFGViewerPass(PassRegistry&);
	void initializeCalculateSpillWeightsPass(PassRegistry&);
	void initializeCallGraphAnalysisGroup(PassRegistry&);
	void initializeCodeGenPreparePass(PassRegistry&);		void initializeCodeGenPreparePass(PassRegistry&);
	void initializeConstantMergePass(PassRegistry&);		void initializeConstantMergePass(PassRegistry&);
	void initializeConstantPropagationPass(PassRegistry&);		void initializeConstantPropagationPass(PassRegistry&);
	void initializeMachineCopyPropagationPass(PassRegistry&);		void initializeMachineCopyPropagationPass(PassRegistry&);
	void initializeCostModelAnalysisPass(PassRegistry&);		void initializeCostModelAnalysisPass(PassRegistry&);
	void initializeCorrelatedValuePropagationPass(PassRegistry&);		void initializeCorrelatedValuePropagationPass(PassRegistry&);
	void initializeDAEPass(PassRegistry&);		void initializeDAEPass(PassRegistry&);
	void initializeDAHPass(PassRegistry&);		void initializeDAHPass(PassRegistry&);
	void initializeDCEPass(PassRegistry&);		void initializeDCEPass(PassRegistry&);
	void initializeDSEPass(PassRegistry&);		void initializeDSEPass(PassRegistry&);
			void initializeDebugIRPass(PassRegistry&);
	void initializeDeadInstEliminationPass(PassRegistry&);		void initializeDeadInstEliminationPass(PassRegistry&);
	void initializeDeadMachineInstructionElimPass(PassRegistry&);		void initializeDeadMachineInstructionElimPass(PassRegistry&);
			void initializeDelinearizationPass(PassRegistry &);
	void initializeDependenceAnalysisPass(PassRegistry&);		void initializeDependenceAnalysisPass(PassRegistry&);
	void initializeDomOnlyPrinterPass(PassRegistry&);		void initializeDomOnlyPrinterPass(PassRegistry&);
	void initializeDomOnlyViewerPass(PassRegistry&);		void initializeDomOnlyViewerPass(PassRegistry&);
	void initializeDomPrinterPass(PassRegistry&);		void initializeDomPrinterPass(PassRegistry&);
	void initializeDomViewerPass(PassRegistry&);		void initializeDomViewerPass(PassRegistry&);
	void initializeDominanceFrontierPass(PassRegistry&);		void initializeDominanceFrontierPass(PassRegistry&);
	void initializeDominatorTreePass(PassRegistry&);		void initializeDominatorTreePass(PassRegistry&);
	void initializeEarlyIfConverterPass(PassRegistry&);		void initializeEarlyIfConverterPass(PassRegistry&);
	void initializeEdgeBundlesPass(PassRegistry&);		void initializeEdgeBundlesPass(PassRegistry&);
	void initializeEdgeProfilerPass(PassRegistry&);
	void initializeExpandPostRAPass(PassRegistry&);		void initializeExpandPostRAPass(PassRegistry&);
	void initializePathProfilerPass(PassRegistry&);
	void initializeGCOVProfilerPass(PassRegistry&);		void initializeGCOVProfilerPass(PassRegistry&);
	void initializeAddressSanitizerPass(PassRegistry&);		void initializeAddressSanitizerPass(PassRegistry&);
	void initializeAddressSanitizerModulePass(PassRegistry&);		void initializeAddressSanitizerModulePass(PassRegistry&);
	void initializeMemorySanitizerPass(PassRegistry&);		void initializeMemorySanitizerPass(PassRegistry&);
	void initializeThreadSanitizerPass(PassRegistry&);		void initializeThreadSanitizerPass(PassRegistry&);
			void initializeDataFlowSanitizerPass(PassRegistry&);
	void initializeEarlyCSEPass(PassRegistry&);		void initializeEarlyCSEPass(PassRegistry&);
	void initializeExpandISelPseudosPass(PassRegistry&);		void initializeExpandISelPseudosPass(PassRegistry&);
	void initializeFindUsedTypesPass(PassRegistry&);		void initializeFindUsedTypesPass(PassRegistry&);
	void initializeFunctionAttrsPass(PassRegistry&);		void initializeFunctionAttrsPass(PassRegistry&);
	void initializeGCMachineCodeAnalysisPass(PassRegistry&);		void initializeGCMachineCodeAnalysisPass(PassRegistry&);
	void initializeGCModuleInfoPass(PassRegistry&);		void initializeGCModuleInfoPass(PassRegistry&);
	void initializeGVNPass(PassRegistry&);		void initializeGVNPass(PassRegistry&);
	void initializeGlobalDCEPass(PassRegistry&);		void initializeGlobalDCEPass(PassRegistry&);
	void initializeGlobalOptPass(PassRegistry&);		void initializeGlobalOptPass(PassRegistry&);
	void initializeGlobalsModRefPass(PassRegistry&);		void initializeGlobalsModRefPass(PassRegistry&);
	skipping to change at line 155		skipping to change at line 156
	void initializeLICMPass(PassRegistry&);		void initializeLICMPass(PassRegistry&);
	void initializeLazyValueInfoPass(PassRegistry&);		void initializeLazyValueInfoPass(PassRegistry&);
	void initializeLibCallAliasAnalysisPass(PassRegistry&);		void initializeLibCallAliasAnalysisPass(PassRegistry&);
	void initializeLintPass(PassRegistry&);		void initializeLintPass(PassRegistry&);
	void initializeLiveDebugVariablesPass(PassRegistry&);		void initializeLiveDebugVariablesPass(PassRegistry&);
	void initializeLiveIntervalsPass(PassRegistry&);		void initializeLiveIntervalsPass(PassRegistry&);
	void initializeLiveRegMatrixPass(PassRegistry&);		void initializeLiveRegMatrixPass(PassRegistry&);
	void initializeLiveStacksPass(PassRegistry&);		void initializeLiveStacksPass(PassRegistry&);
	void initializeLiveVariablesPass(PassRegistry&);		void initializeLiveVariablesPass(PassRegistry&);
	void initializeLoaderPassPass(PassRegistry&);		void initializeLoaderPassPass(PassRegistry&);
	void initializeProfileMetadataLoaderPassPass(PassRegistry&);
	void initializePathProfileLoaderPassPass(PassRegistry&);
	void initializeLocalStackSlotPassPass(PassRegistry&);		void initializeLocalStackSlotPassPass(PassRegistry&);
	void initializeLoopDeletionPass(PassRegistry&);		void initializeLoopDeletionPass(PassRegistry&);
	void initializeLoopExtractorPass(PassRegistry&);		void initializeLoopExtractorPass(PassRegistry&);
	void initializeLoopInfoPass(PassRegistry&);		void initializeLoopInfoPass(PassRegistry&);
	void initializeLoopInstSimplifyPass(PassRegistry&);		void initializeLoopInstSimplifyPass(PassRegistry&);
	void initializeLoopRotatePass(PassRegistry&);		void initializeLoopRotatePass(PassRegistry&);
	void initializeLoopSimplifyPass(PassRegistry&);		void initializeLoopSimplifyPass(PassRegistry&);
	void initializeLoopStrengthReducePass(PassRegistry&);		void initializeLoopStrengthReducePass(PassRegistry&);
	void initializeGlobalMergePass(PassRegistry&);		void initializeGlobalMergePass(PassRegistry&);
			void initializeLoopRerollPass(PassRegistry&);
	void initializeLoopUnrollPass(PassRegistry&);		void initializeLoopUnrollPass(PassRegistry&);
	void initializeLoopUnswitchPass(PassRegistry&);		void initializeLoopUnswitchPass(PassRegistry&);
	void initializeLoopIdiomRecognizePass(PassRegistry&);		void initializeLoopIdiomRecognizePass(PassRegistry&);
	void initializeLowerAtomicPass(PassRegistry&);		void initializeLowerAtomicPass(PassRegistry&);
	void initializeLowerExpectIntrinsicPass(PassRegistry&);		void initializeLowerExpectIntrinsicPass(PassRegistry&);
	void initializeLowerIntrinsicsPass(PassRegistry&);		void initializeLowerIntrinsicsPass(PassRegistry&);
	void initializeLowerInvokePass(PassRegistry&);		void initializeLowerInvokePass(PassRegistry&);
	void initializeLowerSwitchPass(PassRegistry&);		void initializeLowerSwitchPass(PassRegistry&);
	void initializeMachineBlockFrequencyInfoPass(PassRegistry&);		void initializeMachineBlockFrequencyInfoPass(PassRegistry&);
	void initializeMachineBlockPlacementPass(PassRegistry&);		void initializeMachineBlockPlacementPass(PassRegistry&);
	skipping to change at line 195		skipping to change at line 195
	void initializeMachineSinkingPass(PassRegistry&);		void initializeMachineSinkingPass(PassRegistry&);
	void initializeMachineTraceMetricsPass(PassRegistry&);		void initializeMachineTraceMetricsPass(PassRegistry&);
	void initializeMachineVerifierPassPass(PassRegistry&);		void initializeMachineVerifierPassPass(PassRegistry&);
	void initializeMemCpyOptPass(PassRegistry&);		void initializeMemCpyOptPass(PassRegistry&);
	void initializeMemDepPrinterPass(PassRegistry&);		void initializeMemDepPrinterPass(PassRegistry&);
	void initializeMemoryDependenceAnalysisPass(PassRegistry&);		void initializeMemoryDependenceAnalysisPass(PassRegistry&);
	void initializeMetaRenamerPass(PassRegistry&);		void initializeMetaRenamerPass(PassRegistry&);
	void initializeMergeFunctionsPass(PassRegistry&);		void initializeMergeFunctionsPass(PassRegistry&);
	void initializeModuleDebugInfoPrinterPass(PassRegistry&);		void initializeModuleDebugInfoPrinterPass(PassRegistry&);
	void initializeNoAAPass(PassRegistry&);		void initializeNoAAPass(PassRegistry&);
	void initializeNoProfileInfoPass(PassRegistry&);
	void initializeNoPathProfileInfoPass(PassRegistry&);
	void initializeObjCARCAliasAnalysisPass(PassRegistry&);		void initializeObjCARCAliasAnalysisPass(PassRegistry&);
	void initializeObjCARCAPElimPass(PassRegistry&);		void initializeObjCARCAPElimPass(PassRegistry&);
	void initializeObjCARCExpandPass(PassRegistry&);		void initializeObjCARCExpandPass(PassRegistry&);
	void initializeObjCARCContractPass(PassRegistry&);		void initializeObjCARCContractPass(PassRegistry&);
	void initializeObjCARCOptPass(PassRegistry&);		void initializeObjCARCOptPass(PassRegistry&);
	void initializeOptimalEdgeProfilerPass(PassRegistry&);
	void initializeOptimizePHIsPass(PassRegistry&);		void initializeOptimizePHIsPass(PassRegistry&);
			void initializePartiallyInlineLibCallsPass(PassRegistry&);
	void initializePEIPass(PassRegistry&);		void initializePEIPass(PassRegistry&);
	void initializePHIEliminationPass(PassRegistry&);		void initializePHIEliminationPass(PassRegistry&);
	void initializePartialInlinerPass(PassRegistry&);		void initializePartialInlinerPass(PassRegistry&);
	void initializePeepholeOptimizerPass(PassRegistry&);		void initializePeepholeOptimizerPass(PassRegistry&);
	void initializePostDomOnlyPrinterPass(PassRegistry&);		void initializePostDomOnlyPrinterPass(PassRegistry&);
	void initializePostDomOnlyViewerPass(PassRegistry&);		void initializePostDomOnlyViewerPass(PassRegistry&);
	void initializePostDomPrinterPass(PassRegistry&);		void initializePostDomPrinterPass(PassRegistry&);
	void initializePostDomViewerPass(PassRegistry&);		void initializePostDomViewerPass(PassRegistry&);
	void initializePostDominatorTreePass(PassRegistry&);		void initializePostDominatorTreePass(PassRegistry&);
	void initializePostRASchedulerPass(PassRegistry&);		void initializePostRASchedulerPass(PassRegistry&);
	void initializePreVerifierPass(PassRegistry&);		void initializePreVerifierPass(PassRegistry&);
	void initializePrintFunctionPassPass(PassRegistry&);		void initializePrintFunctionPassPass(PassRegistry&);
	void initializePrintModulePassPass(PassRegistry&);		void initializePrintModulePassPass(PassRegistry&);
	void initializePrintBasicBlockPassPass(PassRegistry&);		void initializePrintBasicBlockPassPass(PassRegistry&);
	void initializeProcessImplicitDefsPass(PassRegistry&);		void initializeProcessImplicitDefsPass(PassRegistry&);
	void initializeProfileEstimatorPassPass(PassRegistry&);
	void initializeProfileInfoAnalysisGroup(PassRegistry&);
	void initializePathProfileInfoAnalysisGroup(PassRegistry&);
	void initializePathProfileVerifierPass(PassRegistry&);
	void initializeProfileVerifierPassPass(PassRegistry&);
	void initializePromotePassPass(PassRegistry&);		void initializePromotePassPass(PassRegistry&);
	void initializePruneEHPass(PassRegistry&);		void initializePruneEHPass(PassRegistry&);
	void initializeReassociatePass(PassRegistry&);		void initializeReassociatePass(PassRegistry&);
	void initializeRegToMemPass(PassRegistry&);		void initializeRegToMemPass(PassRegistry&);
	void initializeRegionInfoPass(PassRegistry&);		void initializeRegionInfoPass(PassRegistry&);
	void initializeRegionOnlyPrinterPass(PassRegistry&);		void initializeRegionOnlyPrinterPass(PassRegistry&);
	void initializeRegionOnlyViewerPass(PassRegistry&);		void initializeRegionOnlyViewerPass(PassRegistry&);
	void initializeRegionPrinterPass(PassRegistry&);		void initializeRegionPrinterPass(PassRegistry&);
	void initializeRegionViewerPass(PassRegistry&);		void initializeRegionViewerPass(PassRegistry&);
	void initializeSCCPPass(PassRegistry&);		void initializeSCCPPass(PassRegistry&);
	void initializeSROAPass(PassRegistry&);		void initializeSROAPass(PassRegistry&);
	void initializeSROA_DTPass(PassRegistry&);		void initializeSROA_DTPass(PassRegistry&);
	void initializeSROA_SSAUpPass(PassRegistry&);		void initializeSROA_SSAUpPass(PassRegistry&);
	void initializeScalarEvolutionAliasAnalysisPass(PassRegistry&);		void initializeScalarEvolutionAliasAnalysisPass(PassRegistry&);
	void initializeScalarEvolutionPass(PassRegistry&);		void initializeScalarEvolutionPass(PassRegistry&);
	void initializeSimpleInlinerPass(PassRegistry&);		void initializeSimpleInlinerPass(PassRegistry&);
	void initializeRegisterCoalescerPass(PassRegistry&);		void initializeRegisterCoalescerPass(PassRegistry&);
	void initializeSimplifyLibCallsPass(PassRegistry&);
	void initializeSingleLoopExtractorPass(PassRegistry&);		void initializeSingleLoopExtractorPass(PassRegistry&);
	void initializeSinkingPass(PassRegistry&);		void initializeSinkingPass(PassRegistry&);
	void initializeSlotIndexesPass(PassRegistry&);		void initializeSlotIndexesPass(PassRegistry&);
	void initializeSpillPlacementPass(PassRegistry&);		void initializeSpillPlacementPass(PassRegistry&);
	void initializeStackProtectorPass(PassRegistry&);		void initializeStackProtectorPass(PassRegistry&);
	void initializeStackColoringPass(PassRegistry&);		void initializeStackColoringPass(PassRegistry&);
	void initializeStackSlotColoringPass(PassRegistry&);		void initializeStackSlotColoringPass(PassRegistry&);
	void initializeStripDeadDebugInfoPass(PassRegistry&);		void initializeStripDeadDebugInfoPass(PassRegistry&);
	void initializeStripDeadPrototypesPassPass(PassRegistry&);		void initializeStripDeadPrototypesPassPass(PassRegistry&);
	void initializeStripDebugDeclarePass(PassRegistry&);		void initializeStripDebugDeclarePass(PassRegistry&);
	void initializeStripNonDebugSymbolsPass(PassRegistry&);		void initializeStripNonDebugSymbolsPass(PassRegistry&);
	void initializeStripSymbolsPass(PassRegistry&);		void initializeStripSymbolsPass(PassRegistry&);
	void initializeStrongPHIEliminationPass(PassRegistry&);
	void initializeTailCallElimPass(PassRegistry&);		void initializeTailCallElimPass(PassRegistry&);
	void initializeTailDuplicatePassPass(PassRegistry&);		void initializeTailDuplicatePassPass(PassRegistry&);
	void initializeTargetPassConfigPass(PassRegistry&);		void initializeTargetPassConfigPass(PassRegistry&);
	void initializeDataLayoutPass(PassRegistry&);		void initializeDataLayoutPass(PassRegistry&);
	void initializeTargetTransformInfoAnalysisGroup(PassRegistry&);		void initializeTargetTransformInfoAnalysisGroup(PassRegistry&);
	void initializeNoTTIPass(PassRegistry&);		void initializeNoTTIPass(PassRegistry&);
	void initializeTargetLibraryInfoPass(PassRegistry&);		void initializeTargetLibraryInfoPass(PassRegistry&);
	void initializeTwoAddressInstructionPassPass(PassRegistry&);		void initializeTwoAddressInstructionPassPass(PassRegistry&);
	void initializeTypeBasedAliasAnalysisPass(PassRegistry&);		void initializeTypeBasedAliasAnalysisPass(PassRegistry&);
	void initializeUnifyFunctionExitNodesPass(PassRegistry&);		void initializeUnifyFunctionExitNodesPass(PassRegistry&);
End of changes. 18 change blocks.
	18 lines changed or deleted		9 lines changed or added

	InlineAsm.h		InlineAsm.h
	skipping to change at line 199		skipping to change at line 199
	}		}
	// Methods for support type inquiry through isa, cast, and dyn_cast:		// Methods for support type inquiry through isa, cast, and dyn_cast:
	static inline bool classof(const Value *V) {		static inline bool classof(const Value *V) {
	return V->getValueID() == Value::InlineAsmVal;		return V->getValueID() == Value::InlineAsmVal;
	}		}
	// These are helper methods for dealing with flags in the INLINEASM SDNod e		// These are helper methods for dealing with flags in the INLINEASM SDNod e
	// in the backend.		// in the backend.
	enum {		enum LLVM_ENUM_INT_TYPE(uint32_t) {
	// Fixed operands on an INLINEASM SDNode.		// Fixed operands on an INLINEASM SDNode.
	Op_InputChain = 0,		Op_InputChain = 0,
	Op_AsmString = 1,		Op_AsmString = 1,
	Op_MDNode = 2,		Op_MDNode = 2,
	Op_ExtraInfo = 3, // HasSideEffects, IsAlignStack, AsmDialect.		Op_ExtraInfo = 3, // HasSideEffects, IsAlignStack, AsmDialect.
	Op_FirstOperand = 4,		Op_FirstOperand = 4,
	// Fixed operands on an INLINEASM MachineInstr.		// Fixed operands on an INLINEASM MachineInstr.
	MIOp_AsmString = 0,		MIOp_AsmString = 0,
	MIOp_ExtraInfo = 1, // HasSideEffects, IsAlignStack, AsmDialect.		MIOp_ExtraInfo = 1, // HasSideEffects, IsAlignStack, AsmDialect.
End of changes. 1 change blocks.
	1 lines changed or deleted		1 lines changed or added

	InlineCost.h		InlineCost.h
	skipping to change at line 17		skipping to change at line 17
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This file implements heuristics for inlining decisions.		// This file implements heuristics for inlining decisions.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_ANALYSIS_INLINECOST_H		#ifndef LLVM_ANALYSIS_INLINECOST_H
	#define LLVM_ANALYSIS_INLINECOST_H		#define LLVM_ANALYSIS_INLINECOST_H
	#include "llvm/Analysis/CodeMetrics.h"
	#include "llvm/Analysis/CallGraphSCCPass.h"		#include "llvm/Analysis/CallGraphSCCPass.h"
	#include <cassert>		#include <cassert>
	#include <climits>		#include <climits>
	namespace llvm {		namespace llvm {
	class CallSite;		class CallSite;
	class DataLayout;		class DataLayout;
	class Function;		class Function;
	class TargetTransformInfo;		class TargetTransformInfo;
	skipping to change at line 80		skipping to change at line 79
	return InlineCost(Cost, Threshold);		return InlineCost(Cost, Threshold);
	}		}
	static InlineCost getAlways() {		static InlineCost getAlways() {
	return InlineCost(AlwaysInlineCost, 0);		return InlineCost(AlwaysInlineCost, 0);
	}		}
	static InlineCost getNever() {		static InlineCost getNever() {
	return InlineCost(NeverInlineCost, 0);		return InlineCost(NeverInlineCost, 0);
	}		}
	/// \brief Test whether the inline cost is low enough for inlining.		/// \brief Test whether the inline cost is low enough for inlining.
	operator bool() const {		LLVM_EXPLICIT operator bool() const {
	return Cost < Threshold;		return Cost < Threshold;
	}		}
	bool isAlways() const { return Cost == AlwaysInlineCost; }		bool isAlways() const { return Cost == AlwaysInlineCost; }
	bool isNever() const { return Cost == NeverInlineCost; }		bool isNever() const { return Cost == NeverInlineCost; }
	bool isVariable() const { return !isAlways() && !isNever(); }		bool isVariable() const { return !isAlways() && !isNever(); }
	/// \brief Get the inline cost estimate.		/// \brief Get the inline cost estimate.
	/// It is an error to call this on an "always" or "never" InlineCost.		/// It is an error to call this on an "always" or "never" InlineCost.
	int getCost() const {		int getCost() const {
End of changes. 2 change blocks.
	2 lines changed or deleted		1 lines changed or added

	InstVisitor.h		InstVisitor.h
	skipping to change at line 192		skipping to change at line 192
	RetTy visitSExtInst(SExtInst &I) { DELEGATE(CastInst);}		RetTy visitSExtInst(SExtInst &I) { DELEGATE(CastInst);}
	RetTy visitFPTruncInst(FPTruncInst &I) { DELEGATE(CastInst);}		RetTy visitFPTruncInst(FPTruncInst &I) { DELEGATE(CastInst);}
	RetTy visitFPExtInst(FPExtInst &I) { DELEGATE(CastInst);}		RetTy visitFPExtInst(FPExtInst &I) { DELEGATE(CastInst);}
	RetTy visitFPToUIInst(FPToUIInst &I) { DELEGATE(CastInst);}		RetTy visitFPToUIInst(FPToUIInst &I) { DELEGATE(CastInst);}
	RetTy visitFPToSIInst(FPToSIInst &I) { DELEGATE(CastInst);}		RetTy visitFPToSIInst(FPToSIInst &I) { DELEGATE(CastInst);}
	RetTy visitUIToFPInst(UIToFPInst &I) { DELEGATE(CastInst);}		RetTy visitUIToFPInst(UIToFPInst &I) { DELEGATE(CastInst);}
	RetTy visitSIToFPInst(SIToFPInst &I) { DELEGATE(CastInst);}		RetTy visitSIToFPInst(SIToFPInst &I) { DELEGATE(CastInst);}
	RetTy visitPtrToIntInst(PtrToIntInst &I) { DELEGATE(CastInst);}		RetTy visitPtrToIntInst(PtrToIntInst &I) { DELEGATE(CastInst);}
	RetTy visitIntToPtrInst(IntToPtrInst &I) { DELEGATE(CastInst);}		RetTy visitIntToPtrInst(IntToPtrInst &I) { DELEGATE(CastInst);}
	RetTy visitBitCastInst(BitCastInst &I) { DELEGATE(CastInst);}		RetTy visitBitCastInst(BitCastInst &I) { DELEGATE(CastInst);}
			RetTy visitAddrSpaceCastInst(AddrSpaceCastInst &I) { DELEGATE(CastInst);}
	RetTy visitSelectInst(SelectInst &I) { DELEGATE(Instruction);}		RetTy visitSelectInst(SelectInst &I) { DELEGATE(Instruction);}
	RetTy visitVAArgInst(VAArgInst &I) { DELEGATE(UnaryInstructi on);}		RetTy visitVAArgInst(VAArgInst &I) { DELEGATE(UnaryInstructi on);}
	RetTy visitExtractElementInst(ExtractElementInst &I) { DELEGATE(Instructi on);}		RetTy visitExtractElementInst(ExtractElementInst &I) { DELEGATE(Instructi on);}
	RetTy visitInsertElementInst(InsertElementInst &I) { DELEGATE(Instruction );}		RetTy visitInsertElementInst(InsertElementInst &I) { DELEGATE(Instruction );}
	RetTy visitShuffleVectorInst(ShuffleVectorInst &I) { DELEGATE(Instruction );}		RetTy visitShuffleVectorInst(ShuffleVectorInst &I) { DELEGATE(Instruction );}
	RetTy visitExtractValueInst(ExtractValueInst &I){ DELEGATE(UnaryInstructi on);}		RetTy visitExtractValueInst(ExtractValueInst &I){ DELEGATE(UnaryInstructi on);}
	RetTy visitInsertValueInst(InsertValueInst &I) { DELEGATE(Instruction); }		RetTy visitInsertValueInst(InsertValueInst &I) { DELEGATE(Instruction); }
	RetTy visitLandingPadInst(LandingPadInst &I) { DELEGATE(Instruction); }		RetTy visitLandingPadInst(LandingPadInst &I) { DELEGATE(Instruction); }
	// Handle the special instrinsic instruction classes.		// Handle the special instrinsic instruction classes.
End of changes. 1 change blocks.
	0 lines changed or deleted		1 lines changed or added

	InstrTypes.h		InstrTypes.h
	skipping to change at line 533		skipping to change at line 533
	const Twine &Name, ///< The name for the instruction		const Twine &Name, ///< The name for the instruction
	BasicBlock *InsertAtEnd ///< The block to insert the instruction into		BasicBlock *InsertAtEnd ///< The block to insert the instruction into
	);		);
	/// @brief Check whether it is valid to call getCastOpcode for these type s.		/// @brief Check whether it is valid to call getCastOpcode for these type s.
	static bool isCastable(		static bool isCastable(
	Type *SrcTy, ///< The Type from which the value should be cast.		Type *SrcTy, ///< The Type from which the value should be cast.
	Type *DestTy ///< The Type to which the value should be cast.		Type *DestTy ///< The Type to which the value should be cast.
	);		);
			/// @brief Check whether a bitcast between these types is valid
			static bool isBitCastable(
			Type *SrcTy, ///< The Type from which the value should be cast.
			Type *DestTy ///< The Type to which the value should be cast.
			);
	/// Returns the opcode necessary to cast Val into Ty using usual casting		/// Returns the opcode necessary to cast Val into Ty using usual casting
	/// rules.		/// rules.
	/// @brief Infer the opcode for cast operand and type		/// @brief Infer the opcode for cast operand and type
	static Instruction::CastOps getCastOpcode(		static Instruction::CastOps getCastOpcode(
	const Value *Val, ///< The value to cast		const Value *Val, ///< The value to cast
	bool SrcIsSigned, ///< Whether to treat the source as signed		bool SrcIsSigned, ///< Whether to treat the source as signed
	Type *Ty, ///< The Type to which the value should be casted		Type *Ty, ///< The Type to which the value should be casted
	bool DstIsSigned ///< Whether to treate the dest. as signed		bool DstIsSigned ///< Whether to treate the dest. as signed
	);		);
	skipping to change at line 570		skipping to change at line 576
	/// involving Integer and Pointer types. They are no-op casts if the inte ger		/// involving Integer and Pointer types. They are no-op casts if the inte ger
	/// is the same size as the pointer. However, pointer size varies with		/// is the same size as the pointer. However, pointer size varies with
	/// platform. Generally, the result of DataLayout::getIntPtrType() should be		/// platform. Generally, the result of DataLayout::getIntPtrType() should be
	/// passed in. If that's not available, use Type::Int64Ty, which will mak e		/// passed in. If that's not available, use Type::Int64Ty, which will mak e
	/// the isNoopCast call conservative.		/// the isNoopCast call conservative.
	/// @brief Determine if the described cast is a no-op cast.		/// @brief Determine if the described cast is a no-op cast.
	static bool isNoopCast(		static bool isNoopCast(
	Instruction::CastOps Opcode, ///< Opcode of cast		Instruction::CastOps Opcode, ///< Opcode of cast
	Type *SrcTy, ///< SrcTy of cast		Type *SrcTy, ///< SrcTy of cast
	Type *DstTy, ///< DstTy of cast		Type *DstTy, ///< DstTy of cast
	Type *IntPtrTy ///< Integer type corresponding to Ptr types, or null		Type *IntPtrTy ///< Integer type corresponding to Ptr types
	);		);
	/// @brief Determine if this cast is a no-op cast.		/// @brief Determine if this cast is a no-op cast.
	bool isNoopCast(		bool isNoopCast(
	Type *IntPtrTy ///< Integer type corresponding to pointer		Type *IntPtrTy ///< Integer type corresponding to pointer
	) const;		) const;
	/// Determine how a pair of casts can be eliminated, if they can be at al l.		/// Determine how a pair of casts can be eliminated, if they can be at al l.
	/// This is a helper function for both CastInst and ConstantExpr.		/// This is a helper function for both CastInst and ConstantExpr.
	/// @returns 0 if the CastInst pair can't be eliminated, otherwise		/// @returns 0 if the CastInst pair can't be eliminated, otherwise
End of changes. 2 change blocks.
	1 lines changed or deleted		7 lines changed or added

	Instruction.def		Instruction.def
	skipping to change at line 156		skipping to change at line 156
	HANDLE_CAST_INST(35, SExt , SExtInst ) // Sign extend integers		HANDLE_CAST_INST(35, SExt , SExtInst ) // Sign extend integers
	HANDLE_CAST_INST(36, FPToUI , FPToUIInst ) // floating point -> UInt		HANDLE_CAST_INST(36, FPToUI , FPToUIInst ) // floating point -> UInt
	HANDLE_CAST_INST(37, FPToSI , FPToSIInst ) // floating point -> SInt		HANDLE_CAST_INST(37, FPToSI , FPToSIInst ) // floating point -> SInt
	HANDLE_CAST_INST(38, UIToFP , UIToFPInst ) // UInt -> floating point		HANDLE_CAST_INST(38, UIToFP , UIToFPInst ) // UInt -> floating point
	HANDLE_CAST_INST(39, SIToFP , SIToFPInst ) // SInt -> floating point		HANDLE_CAST_INST(39, SIToFP , SIToFPInst ) // SInt -> floating point
	HANDLE_CAST_INST(40, FPTrunc , FPTruncInst ) // Truncate floating point		HANDLE_CAST_INST(40, FPTrunc , FPTruncInst ) // Truncate floating point
	HANDLE_CAST_INST(41, FPExt , FPExtInst ) // Extend floating point		HANDLE_CAST_INST(41, FPExt , FPExtInst ) // Extend floating point
	HANDLE_CAST_INST(42, PtrToInt, PtrToIntInst) // Pointer -> Integer		HANDLE_CAST_INST(42, PtrToInt, PtrToIntInst) // Pointer -> Integer
	HANDLE_CAST_INST(43, IntToPtr, IntToPtrInst) // Integer -> Pointer		HANDLE_CAST_INST(43, IntToPtr, IntToPtrInst) // Integer -> Pointer
	HANDLE_CAST_INST(44, BitCast , BitCastInst ) // Type cast		HANDLE_CAST_INST(44, BitCast , BitCastInst ) // Type cast
	LAST_CAST_INST(44)		HANDLE_CAST_INST(45, AddrSpaceCast, AddrSpaceCastInst) // addrspace cast
			LAST_CAST_INST(45)
	// Other operators...		// Other operators...
	FIRST_OTHER_INST(45)		FIRST_OTHER_INST(46)
	HANDLE_OTHER_INST(45, ICmp , ICmpInst ) // Integer comparison instruct		HANDLE_OTHER_INST(46, ICmp , ICmpInst ) // Integer comparison instruct
	ion		ion
	HANDLE_OTHER_INST(46, FCmp , FCmpInst ) // Floating point comparison i		HANDLE_OTHER_INST(47, FCmp , FCmpInst ) // Floating point comparison i
	nstr.		nstr.
	HANDLE_OTHER_INST(47, PHI , PHINode ) // PHI node instruction		HANDLE_OTHER_INST(48, PHI , PHINode ) // PHI node instruction
	HANDLE_OTHER_INST(48, Call , CallInst ) // Call a function		HANDLE_OTHER_INST(49, Call , CallInst ) // Call a function
	HANDLE_OTHER_INST(49, Select , SelectInst ) // select instruction		HANDLE_OTHER_INST(50, Select , SelectInst ) // select instruction
	HANDLE_OTHER_INST(50, UserOp1, Instruction) // May be used internally in a		HANDLE_OTHER_INST(51, UserOp1, Instruction) // May be used internally in a
	pass		pass
	HANDLE_OTHER_INST(51, UserOp2, Instruction) // Internal to passes only		HANDLE_OTHER_INST(52, UserOp2, Instruction) // Internal to passes only
	HANDLE_OTHER_INST(52, VAArg , VAArgInst ) // vaarg instruction		HANDLE_OTHER_INST(53, VAArg , VAArgInst ) // vaarg instruction
	HANDLE_OTHER_INST(53, ExtractElement, ExtractElementInst)// extract from ve		HANDLE_OTHER_INST(54, ExtractElement, ExtractElementInst)// extract from ve
	ctor		ctor
	HANDLE_OTHER_INST(54, InsertElement, InsertElementInst) // insert into vec		HANDLE_OTHER_INST(55, InsertElement, InsertElementInst) // insert into vec
	tor		tor
	HANDLE_OTHER_INST(55, ShuffleVector, ShuffleVectorInst) // shuffle two vec		HANDLE_OTHER_INST(56, ShuffleVector, ShuffleVectorInst) // shuffle two vec
	tors.		tors.
	HANDLE_OTHER_INST(56, ExtractValue, ExtractValueInst)// extract from aggreg		HANDLE_OTHER_INST(57, ExtractValue, ExtractValueInst)// extract from aggreg
	ate		ate
	HANDLE_OTHER_INST(57, InsertValue, InsertValueInst) // insert into aggrega		HANDLE_OTHER_INST(58, InsertValue, InsertValueInst) // insert into aggrega
	te		te
	HANDLE_OTHER_INST(58, LandingPad, LandingPadInst) // Landing pad instructi		HANDLE_OTHER_INST(59, LandingPad, LandingPadInst) // Landing pad instructi
	on.		on.
	LAST_OTHER_INST(58)		LAST_OTHER_INST(59)
	#undef FIRST_TERM_INST		#undef FIRST_TERM_INST
	#undef HANDLE_TERM_INST		#undef HANDLE_TERM_INST
	#undef LAST_TERM_INST		#undef LAST_TERM_INST
	#undef FIRST_BINARY_INST		#undef FIRST_BINARY_INST
	#undef HANDLE_BINARY_INST		#undef HANDLE_BINARY_INST
	#undef LAST_BINARY_INST		#undef LAST_BINARY_INST
	#undef FIRST_MEMORY_INST		#undef FIRST_MEMORY_INST
End of changes. 2 change blocks.
	26 lines changed or deleted		27 lines changed or added

	InstructionSimplify.h		InstructionSimplify.h
	//===-- InstructionSimplify.h - Fold instructions into simpler forms ------ ===//		//===-- InstructionSimplify.h - Fold instrs into simpler forms --*- C++ -*- ===//
	//		//
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This file declares routines for folding instructions into simpler forms		// This file declares routines for folding instructions into simpler forms
	// that do not require creating new instructions. This does constant foldi ng		// that do not require creating new instructions. This does constant foldi ng
End of changes. 1 change blocks.
	1 lines changed or deleted		1 lines changed or added

	Instructions.h		Instructions.h
	skipping to change at line 26		skipping to change at line 26
	#ifndef LLVM_IR_INSTRUCTIONS_H		#ifndef LLVM_IR_INSTRUCTIONS_H
	#define LLVM_IR_INSTRUCTIONS_H		#define LLVM_IR_INSTRUCTIONS_H
	#include "llvm/ADT/ArrayRef.h"		#include "llvm/ADT/ArrayRef.h"
	#include "llvm/ADT/SmallVector.h"		#include "llvm/ADT/SmallVector.h"
	#include "llvm/IR/Attributes.h"		#include "llvm/IR/Attributes.h"
	#include "llvm/IR/CallingConv.h"		#include "llvm/IR/CallingConv.h"
	#include "llvm/IR/DerivedTypes.h"		#include "llvm/IR/DerivedTypes.h"
	#include "llvm/IR/InstrTypes.h"		#include "llvm/IR/InstrTypes.h"
	#include "llvm/Support/ErrorHandling.h"		#include "llvm/Support/ErrorHandling.h"
	#include "llvm/Support/IntegersSubset.h"
	#include "llvm/Support/IntegersSubsetMapping.h"
	#include <iterator>		#include <iterator>
	namespace llvm {		namespace llvm {
	class APInt;		class APInt;
	class ConstantInt;		class ConstantInt;
	class ConstantRange;		class ConstantRange;
	class DataLayout;		class DataLayout;
	class LLVMContext;		class LLVMContext;
	skipping to change at line 908		skipping to change at line 906
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// ICmpInst Class		// ICmpInst Class
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	/// This instruction compares its operands according to the predicate given		/// This instruction compares its operands according to the predicate given
	/// to the constructor. It only operates on integers or pointers. The opera nds		/// to the constructor. It only operates on integers or pointers. The opera nds
	/// must be identical types.		/// must be identical types.
	/// \brief Represent an integer comparison operator.		/// \brief Represent an integer comparison operator.
	class ICmpInst: public CmpInst {		class ICmpInst: public CmpInst {
			void AssertOK() {
			assert(getPredicate() >= CmpInst::FIRST_ICMP_PREDICATE &&
			getPredicate() <= CmpInst::LAST_ICMP_PREDICATE &&
			"Invalid ICmp predicate value");
			assert(getOperand(0)->getType() == getOperand(1)->getType() &&
			"Both operands to ICmp instruction are not of the same type!");
			// Check that the operands are the right type
			assert((getOperand(0)->getType()->isIntOrIntVectorTy() ||
			getOperand(0)->getType()->isPtrOrPtrVectorTy()) &&
			"Invalid operand types for ICmp instruction");
			}
	protected:		protected:
	/// \brief Clone an identical ICmpInst		/// \brief Clone an identical ICmpInst
	virtual ICmpInst *clone_impl() const;		virtual ICmpInst *clone_impl() const;
	public:		public:
	/// \brief Constructor with insert-before-instruction semantics.		/// \brief Constructor with insert-before-instruction semantics.
	ICmpInst(		ICmpInst(
	Instruction *InsertBefore, ///< Where to insert		Instruction *InsertBefore, ///< Where to insert
	Predicate pred, ///< The predicate to use for the comparison		Predicate pred, ///< The predicate to use for the comparison
	Value *LHS, ///< The left-hand-side of the expression		Value *LHS, ///< The left-hand-side of the expression
	Value *RHS, ///< The right-hand-side of the expression		Value *RHS, ///< The right-hand-side of the expression
	const Twine &NameStr = "" ///< Name of the instruction		const Twine &NameStr = "" ///< Name of the instruction
	) : CmpInst(makeCmpResultType(LHS->getType()),		) : CmpInst(makeCmpResultType(LHS->getType()),
	Instruction::ICmp, pred, LHS, RHS, NameStr,		Instruction::ICmp, pred, LHS, RHS, NameStr,
	InsertBefore) {		InsertBefore) {
	assert(pred >= CmpInst::FIRST_ICMP_PREDICATE &&		#ifndef NDEBUG
	pred <= CmpInst::LAST_ICMP_PREDICATE &&		AssertOK();
	"Invalid ICmp predicate value");		#endif
	assert(getOperand(0)->getType() == getOperand(1)->getType() &&
	"Both operands to ICmp instruction are not of the same type!");
	// Check that the operands are the right type
	assert((getOperand(0)->getType()->isIntOrIntVectorTy() ||
	getOperand(0)->getType()->getScalarType()->isPointerTy()) &&
	"Invalid operand types for ICmp instruction");
	}		}
	/// \brief Constructor with insert-at-end semantics.		/// \brief Constructor with insert-at-end semantics.
	ICmpInst(		ICmpInst(
	BasicBlock &InsertAtEnd, ///< Block to insert into.		BasicBlock &InsertAtEnd, ///< Block to insert into.
	Predicate pred, ///< The predicate to use for the comparison		Predicate pred, ///< The predicate to use for the comparison
	Value *LHS, ///< The left-hand-side of the expression		Value *LHS, ///< The left-hand-side of the expression
	Value *RHS, ///< The right-hand-side of the expression		Value *RHS, ///< The right-hand-side of the expression
	const Twine &NameStr = "" ///< Name of the instruction		const Twine &NameStr = "" ///< Name of the instruction
	) : CmpInst(makeCmpResultType(LHS->getType()),		) : CmpInst(makeCmpResultType(LHS->getType()),
	Instruction::ICmp, pred, LHS, RHS, NameStr,		Instruction::ICmp, pred, LHS, RHS, NameStr,
	&InsertAtEnd) {		&InsertAtEnd) {
	assert(pred >= CmpInst::FIRST_ICMP_PREDICATE &&		#ifndef NDEBUG
	pred <= CmpInst::LAST_ICMP_PREDICATE &&		AssertOK();
	"Invalid ICmp predicate value");		#endif
	assert(getOperand(0)->getType() == getOperand(1)->getType() &&
	"Both operands to ICmp instruction are not of the same type!");
	// Check that the operands are the right type
	assert((getOperand(0)->getType()->isIntOrIntVectorTy() ||
	getOperand(0)->getType()->getScalarType()->isPointerTy()) &&
	"Invalid operand types for ICmp instruction");
	}		}
	/// \brief Constructor with no-insertion semantics		/// \brief Constructor with no-insertion semantics
	ICmpInst(		ICmpInst(
	Predicate pred, ///< The predicate to use for the comparison		Predicate pred, ///< The predicate to use for the comparison
	Value *LHS, ///< The left-hand-side of the expression		Value *LHS, ///< The left-hand-side of the expression
	Value *RHS, ///< The right-hand-side of the expression		Value *RHS, ///< The right-hand-side of the expression
	const Twine &NameStr = "" ///< Name of the instruction		const Twine &NameStr = "" ///< Name of the instruction
	) : CmpInst(makeCmpResultType(LHS->getType()),		) : CmpInst(makeCmpResultType(LHS->getType()),
	Instruction::ICmp, pred, LHS, RHS, NameStr) {		Instruction::ICmp, pred, LHS, RHS, NameStr) {
	assert(pred >= CmpInst::FIRST_ICMP_PREDICATE &&		#ifndef NDEBUG
	pred <= CmpInst::LAST_ICMP_PREDICATE &&		AssertOK();
	"Invalid ICmp predicate value");		#endif
	assert(getOperand(0)->getType() == getOperand(1)->getType() &&
	"Both operands to ICmp instruction are not of the same type!");
	// Check that the operands are the right type
	assert((getOperand(0)->getType()->isIntOrIntVectorTy() ||
	getOperand(0)->getType()->getScalarType()->isPointerTy()) &&
	"Invalid operand types for ICmp instruction");
	}		}
	/// For example, EQ->EQ, SLE->SLE, UGT->SGT, etc.		/// For example, EQ->EQ, SLE->SLE, UGT->SGT, etc.
	/// @returns the predicate that would be the result if the operand were		/// @returns the predicate that would be the result if the operand were
	/// regarded as signed.		/// regarded as signed.
	/// \brief Return the signed version of the predicate		/// \brief Return the signed version of the predicate
	Predicate getSignedPredicate() const {		Predicate getSignedPredicate() const {
	return getSignedPredicate(getPredicate());		return getSignedPredicate(getPredicate());
	}		}
	skipping to change at line 1275		skipping to change at line 1267
	///		///
	void setAttributes(const AttributeSet &Attrs) { AttributeList = Attrs; }		void setAttributes(const AttributeSet &Attrs) { AttributeList = Attrs; }
	/// addAttribute - adds the attribute to the list of attributes.		/// addAttribute - adds the attribute to the list of attributes.
	void addAttribute(unsigned i, Attribute::AttrKind attr);		void addAttribute(unsigned i, Attribute::AttrKind attr);
	/// removeAttribute - removes the attribute from the list of attributes.		/// removeAttribute - removes the attribute from the list of attributes.
	void removeAttribute(unsigned i, Attribute attr);		void removeAttribute(unsigned i, Attribute attr);
	/// \brief Determine whether this call has the given attribute.		/// \brief Determine whether this call has the given attribute.
	bool hasFnAttr(Attribute::AttrKind A) const;		bool hasFnAttr(Attribute::AttrKind A) const {
			assert(A != Attribute::NoBuiltin &&
			"Use CallInst::isNoBuiltin() to check for Attribute::NoBuiltin")
			;
			return hasFnAttrImpl(A);
			}
	/// \brief Determine whether the call or the callee has the given attribu tes.		/// \brief Determine whether the call or the callee has the given attribu tes.
	bool paramHasAttr(unsigned i, Attribute::AttrKind A) const;		bool paramHasAttr(unsigned i, Attribute::AttrKind A) const;
	/// \brief Extract the alignment for a call or parameter (0=unknown).		/// \brief Extract the alignment for a call or parameter (0=unknown).
	unsigned getParamAlignment(unsigned i) const {		unsigned getParamAlignment(unsigned i) const {
	return AttributeList.getParamAlignment(i);		return AttributeList.getParamAlignment(i);
	}		}
			/// \brief Return true if the call should not be treated as a call to a
			/// builtin.
			bool isNoBuiltin() const {
			return hasFnAttrImpl(Attribute::NoBuiltin) &&
			!hasFnAttrImpl(Attribute::Builtin);
			}
	/// \brief Return true if the call should not be inlined.		/// \brief Return true if the call should not be inlined.
	bool isNoInline() const { return hasFnAttr(Attribute::NoInline); }		bool isNoInline() const { return hasFnAttr(Attribute::NoInline); }
	void setIsNoInline() {		void setIsNoInline() {
	addAttribute(AttributeSet::FunctionIndex, Attribute::NoInline);		addAttribute(AttributeSet::FunctionIndex, Attribute::NoInline);
	}		}
	/// \brief Return true if the call can return twice		/// \brief Return true if the call can return twice
	bool canReturnTwice() const {		bool canReturnTwice() const {
	return hasFnAttr(Attribute::ReturnsTwice);		return hasFnAttr(Attribute::ReturnsTwice);
	}		}
	skipping to change at line 1375		skipping to change at line 1378
	}		}
	// Methods for support type inquiry through isa, cast, and dyn_cast:		// Methods for support type inquiry through isa, cast, and dyn_cast:
	static inline bool classof(const Instruction *I) {		static inline bool classof(const Instruction *I) {
	return I->getOpcode() == Instruction::Call;		return I->getOpcode() == Instruction::Call;
	}		}
	static inline bool classof(const Value *V) {		static inline bool classof(const Value *V) {
	return isa<Instruction>(V) && classof(cast<Instruction>(V));		return isa<Instruction>(V) && classof(cast<Instruction>(V));
	}		}
	private:		private:
			bool hasFnAttrImpl(Attribute::AttrKind A) const;
	// Shadow Instruction::setInstructionSubclassData with a private forwardi ng		// Shadow Instruction::setInstructionSubclassData with a private forwardi ng
	// method so that subclasses cannot accidentally use it.		// method so that subclasses cannot accidentally use it.
	void setInstructionSubclassData(unsigned short D) {		void setInstructionSubclassData(unsigned short D) {
	Instruction::setInstructionSubclassData(D);		Instruction::setInstructionSubclassData(D);
	}		}
	};		};
	template <>		template <>
	struct OperandTraits<CallInst> : public VariadicOperandTraits<CallInst, 1> {		struct OperandTraits<CallInst> : public VariadicOperandTraits<CallInst, 1> {
	};		};
	skipping to change at line 2436		skipping to change at line 2442
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// SwitchInst Class		// SwitchInst Class
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//===---------------------------------------------------------------------- -----		//===---------------------------------------------------------------------- -----
	/// SwitchInst - Multiway switch		/// SwitchInst - Multiway switch
	///		///
	class SwitchInst : public TerminatorInst {		class SwitchInst : public TerminatorInst {
	void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;		void *operator new(size_t, unsigned) LLVM_DELETED_FUNCTION;
	unsigned ReservedSpace;		unsigned ReservedSpace;
	// Operands format:
	// Operand[0] = Value to switch on		// Operand[0] = Value to switch on
	// Operand[1] = Default basic block destination		// Operand[1] = Default basic block destination
	// Operand[2n ] = Value to match		// Operand[2n ] = Value to match
	// Operand[2n+1] = BasicBlock to go to on match		// Operand[2n+1] = BasicBlock to go to on match
	// Store case values separately from operands list. We needn't User-Use
	// concept here, since it is just a case value, it will always constant,
	// and case value couldn't reused with another instructions/values.
	// Additionally:
	// It allows us to use custom type for case values that is not inherited
	// from Value. Since case value is a complex type that implements
	// the subset of integers, we needn't extract sub-constants within
	// slow getAggregateElement method.
	// For case values we will use std::list to by two reasons:
	// 1. It allows to add/remove cases without whole collection reallocation
	.
	// 2. In most of cases we needn't random access.
	// Currently case values are also stored in Operands List, but it will mo
	ved
	// out in future commits.
	typedef std::list<IntegersSubset> Subsets;
	typedef Subsets::iterator SubsetsIt;
	typedef Subsets::const_iterator SubsetsConstIt;
	Subsets TheSubsets;
	SwitchInst(const SwitchInst &SI);		SwitchInst(const SwitchInst &SI);
	void init(Value *Value, BasicBlock *Default, unsigned NumReserved);		void init(Value *Value, BasicBlock *Default, unsigned NumReserved);
	void growOperands();		void growOperands();
	// allocate space for exactly zero operands		// allocate space for exactly zero operands
	void *operator new(size_t s) {		void *operator new(size_t s) {
	return User::operator new(s, 0);		return User::operator new(s, 0);
	}		}
	/// SwitchInst ctor - Create a new switch instruction, specifying a value to		/// SwitchInst ctor - Create a new switch instruction, specifying a value to
	/// switch on and a default destination. The number of additional cases can		/// switch on and a default destination. The number of additional cases can
	/// be specified here to make memory allocation more efficient. This		/// be specified here to make memory allocation more efficient. This
	skipping to change at line 2485		skipping to change at line 2470
	/// SwitchInst ctor - Create a new switch instruction, specifying a value to		/// SwitchInst ctor - Create a new switch instruction, specifying a value to
	/// switch on and a default destination. The number of additional cases can		/// switch on and a default destination. The number of additional cases can
	/// be specified here to make memory allocation more efficient. This		/// be specified here to make memory allocation more efficient. This
	/// constructor also autoinserts at the end of the specified BasicBlock.		/// constructor also autoinserts at the end of the specified BasicBlock.
	SwitchInst(Value *Value, BasicBlock *Default, unsigned NumCases,		SwitchInst(Value *Value, BasicBlock *Default, unsigned NumCases,
	BasicBlock *InsertAtEnd);		BasicBlock *InsertAtEnd);
	protected:		protected:
	virtual SwitchInst *clone_impl() const;		virtual SwitchInst *clone_impl() const;
	public:		public:
	// FIXME: Currently there are a lot of unclean template parameters,
	// we need to make refactoring in future.
	// All these parameters are used to implement both iterator and const_ite
	rator
	// without code duplication.
	// SwitchInstTy may be "const SwitchInst" or "SwitchInst"
	// ConstantIntTy may be "const ConstantInt" or "ConstantInt"
	// SubsetsItTy may be SubsetsConstIt or SubsetsIt
	// BasicBlockTy may be "const BasicBlock" or "BasicBlock"
	template <class SwitchInstTy, class ConstantIntTy,
	class SubsetsItTy, class BasicBlockTy>
	class CaseIteratorT;
	typedef CaseIteratorT<const SwitchInst, const ConstantInt,
	SubsetsConstIt, const BasicBlock> ConstCaseIt;
	class CaseIt;
	// -2		// -2
	static const unsigned DefaultPseudoIndex = static_cast<unsigned>(~0L-1);		static const unsigned DefaultPseudoIndex = static_cast<unsigned>(~0L-1);
			template <class SwitchInstTy, class ConstantIntTy, class BasicBlockTy>
			class CaseIteratorT {
			protected:
			SwitchInstTy *SI;
			unsigned Index;
			public:
			typedef CaseIteratorT<SwitchInstTy, ConstantIntTy, BasicBlockTy> Self;
			/// Initializes case iterator for given SwitchInst and for given
			/// case number.
			CaseIteratorT(SwitchInstTy *SI, unsigned CaseNum) {
			this->SI = SI;
			Index = CaseNum;
			}
			/// Initializes case iterator for given SwitchInst and for given
			/// TerminatorInst's successor index.
			static Self fromSuccessorIndex(SwitchInstTy *SI, unsigned SuccessorInde
			x) {
			assert(SuccessorIndex < SI->getNumSuccessors() &&
			"Successor index # out of range!");
			return SuccessorIndex != 0 ?
			Self(SI, SuccessorIndex - 1) :
			Self(SI, DefaultPseudoIndex);
			}
			/// Resolves case value for current case.
			ConstantIntTy *getCaseValue() {
			assert(Index < SI->getNumCases() && "Index out the number of cases.")
			;
			return reinterpret_cast<ConstantIntTy*>(SI->getOperand(2 + Index*2));
			}
			/// Resolves successor for current case.
			BasicBlockTy *getCaseSuccessor() {
			assert((Index < SI->getNumCases() ||
			Index == DefaultPseudoIndex) &&
			"Index out the number of cases.");
			return SI->getSuccessor(getSuccessorIndex());
			}
			/// Returns number of current case.
			unsigned getCaseIndex() const { return Index; }
			/// Returns TerminatorInst's successor index for current case successor
			.
			unsigned getSuccessorIndex() const {
			assert((Index == DefaultPseudoIndex || Index < SI->getNumCases()) &&
			"Index out the number of cases.");
			return Index != DefaultPseudoIndex ? Index + 1 : 0;
			}
			Self operator++() {
			// Check index correctness after increment.
			// Note: Index == getNumCases() means end().
			assert(Index+1 <= SI->getNumCases() && "Index out the number of cases
			.");
			++Index;
			return *this;
			}
			Self operator++(int) {
			Self tmp = *this;
			++(*this);
			return tmp;
			}
			Self operator--() {
			// Check index correctness after decrement.
			// Note: Index == getNumCases() means end().
			// Also allow "-1" iterator here. That will became valid after ++.
			assert((Index == 0 || Index-1 <= SI->getNumCases()) &&
			"Index out the number of cases.");
			--Index;
			return *this;
			}
			Self operator--(int) {
			Self tmp = *this;
			--(*this);
			return tmp;
			}
			bool operator==(const Self& RHS) const {
			assert(RHS.SI == SI && "Incompatible operators.");
			return RHS.Index == Index;
			}
			bool operator!=(const Self& RHS) const {
			assert(RHS.SI == SI && "Incompatible operators.");
			return RHS.Index != Index;
			}
			};
			typedef CaseIteratorT<const SwitchInst, const ConstantInt, const BasicBlo
			ck>
			ConstCaseIt;
			class CaseIt : public CaseIteratorT<SwitchInst, ConstantInt, BasicBlock>
			{
			typedef CaseIteratorT<SwitchInst, ConstantInt, BasicBlock> ParentTy;
			public:
			CaseIt(const ParentTy& Src) : ParentTy(Src) {}
			CaseIt(SwitchInst *SI, unsigned CaseNum) : ParentTy(SI, CaseNum) {}
			/// Sets the new value for current case.
			void setValue(ConstantInt *V) {
			assert(Index < SI->getNumCases() && "Index out the number of cases.")
			;
			SI->setOperand(2 + Index*2, reinterpret_cast<Value*>(V));
			}
			/// Sets the new successor for current case.
			void setSuccessor(BasicBlock *S) {
			SI->setSuccessor(getSuccessorIndex(), S);
			}
			};
	static SwitchInst *Create(Value *Value, BasicBlock *Default,		static SwitchInst *Create(Value *Value, BasicBlock *Default,
	unsigned NumCases, Instruction *InsertBefore = 0) {		unsigned NumCases, Instruction *InsertBefore = 0) {
	return new SwitchInst(Value, Default, NumCases, InsertBefore);		return new SwitchInst(Value, Default, NumCases, InsertBefore);
	}		}
	static SwitchInst *Create(Value *Value, BasicBlock *Default,		static SwitchInst *Create(Value *Value, BasicBlock *Default,
	unsigned NumCases, BasicBlock *InsertAtEnd) {		unsigned NumCases, BasicBlock *InsertAtEnd) {
	return new SwitchInst(Value, Default, NumCases, InsertAtEnd);		return new SwitchInst(Value, Default, NumCases, InsertAtEnd);
	}		}
	~SwitchInst();		~SwitchInst();
	skipping to change at line 2539		skipping to change at line 2620
	/// getNumCases - return the number of 'cases' in this switch instruction ,		/// getNumCases - return the number of 'cases' in this switch instruction ,
	/// except the default case		/// except the default case
	unsigned getNumCases() const {		unsigned getNumCases() const {
	return getNumOperands()/2 - 1;		return getNumOperands()/2 - 1;
	}		}
	/// Returns a read/write iterator that points to the first		/// Returns a read/write iterator that points to the first
	/// case in SwitchInst.		/// case in SwitchInst.
	CaseIt case_begin() {		CaseIt case_begin() {
	return CaseIt(this, 0, TheSubsets.begin());		return CaseIt(this, 0);
	}		}
	/// Returns a read-only iterator that points to the first		/// Returns a read-only iterator that points to the first
	/// case in the SwitchInst.		/// case in the SwitchInst.
	ConstCaseIt case_begin() const {		ConstCaseIt case_begin() const {
	return ConstCaseIt(this, 0, TheSubsets.begin());		return ConstCaseIt(this, 0);
	}		}
	/// Returns a read/write iterator that points one past the last		/// Returns a read/write iterator that points one past the last
	/// in the SwitchInst.		/// in the SwitchInst.
	CaseIt case_end() {		CaseIt case_end() {
	return CaseIt(this, getNumCases(), TheSubsets.end());		return CaseIt(this, getNumCases());
	}		}
	/// Returns a read-only iterator that points one past the last		/// Returns a read-only iterator that points one past the last
	/// in the SwitchInst.		/// in the SwitchInst.
	ConstCaseIt case_end() const {		ConstCaseIt case_end() const {
	return ConstCaseIt(this, getNumCases(), TheSubsets.end());		return ConstCaseIt(this, getNumCases());
	}		}
	/// Returns an iterator that points to the default case.		/// Returns an iterator that points to the default case.
	/// Note: this iterator allows to resolve successor only. Attempt		/// Note: this iterator allows to resolve successor only. Attempt
	/// to resolve case value causes an assertion.		/// to resolve case value causes an assertion.
	/// Also note, that increment and decrement also causes an assertion and		/// Also note, that increment and decrement also causes an assertion and
	/// makes iterator invalid.		/// makes iterator invalid.
	CaseIt case_default() {		CaseIt case_default() {
	return CaseIt(this, DefaultPseudoIndex, TheSubsets.end());		return CaseIt(this, DefaultPseudoIndex);
	}		}
	ConstCaseIt case_default() const {		ConstCaseIt case_default() const {
	return ConstCaseIt(this, DefaultPseudoIndex, TheSubsets.end());		return ConstCaseIt(this, DefaultPseudoIndex);
	}		}
	/// findCaseValue - Search all of the case values for the specified const ant.		/// findCaseValue - Search all of the case values for the specified const ant.
	/// If it is explicitly handled, return the case iterator of it, otherwis e		/// If it is explicitly handled, return the case iterator of it, otherwis e
	/// return default case iterator to indicate		/// return default case iterator to indicate
	/// that it is handled by the default handler.		/// that it is handled by the default handler.
	CaseIt findCaseValue(const ConstantInt *C) {		CaseIt findCaseValue(const ConstantInt *C) {
	for (CaseIt i = case_begin(), e = case_end(); i != e; ++i)		for (CaseIt i = case_begin(), e = case_end(); i != e; ++i)
	if (i.getCaseValueEx().isSatisfies(IntItem::fromConstantInt(C)))		if (i.getCaseValue() == C)
	return i;		return i;
	return case_default();		return case_default();
	}		}
	ConstCaseIt findCaseValue(const ConstantInt *C) const {		ConstCaseIt findCaseValue(const ConstantInt *C) const {
	for (ConstCaseIt i = case_begin(), e = case_end(); i != e; ++i)		for (ConstCaseIt i = case_begin(), e = case_end(); i != e; ++i)
	if (i.getCaseValueEx().isSatisfies(IntItem::fromConstantInt(C)))		if (i.getCaseValue() == C)
	return i;		return i;
	return case_default();		return case_default();
	}		}
	/// findCaseDest - Finds the unique case value for a given successor. Ret urns		/// findCaseDest - Finds the unique case value for a given successor. Ret urns
	/// null if the successor is not found, not unique, or is the default cas e.		/// null if the successor is not found, not unique, or is the default cas e.
	ConstantInt *findCaseDest(BasicBlock *BB) {		ConstantInt *findCaseDest(BasicBlock *BB) {
	if (BB == getDefaultDest()) return NULL;		if (BB == getDefaultDest()) return NULL;
	ConstantInt *CI = NULL;		ConstantInt *CI = NULL;
	for (CaseIt i = case_begin(), e = case_end(); i != e; ++i) {		for (CaseIt i = case_begin(), e = case_end(); i != e; ++i) {
	if (i.getCaseSuccessor() == BB) {		if (i.getCaseSuccessor() == BB) {
	if (CI) return NULL; // Multiple cases lead to BB.		if (CI) return NULL; // Multiple cases lead to BB.
	else CI = i.getCaseValue();		else CI = i.getCaseValue();
	}		}
	}		}
	return CI;		return CI;
	}		}
	/// addCase - Add an entry to the switch instruction...		/// addCase - Add an entry to the switch instruction...
	/// @deprecated
	/// Note:		/// Note:
	/// This action invalidates case_end(). Old case_end() iterator will		/// This action invalidates case_end(). Old case_end() iterator will
	/// point to the added case.		/// point to the added case.
	void addCase(ConstantInt *OnVal, BasicBlock *Dest);		void addCase(ConstantInt *OnVal, BasicBlock *Dest);
	/// addCase - Add an entry to the switch instruction.
	/// Note:
	/// This action invalidates case_end(). Old case_end() iterator will
	/// point to the added case.
	void addCase(IntegersSubset& OnVal, BasicBlock *Dest);
	/// removeCase - This method removes the specified case and its successor		/// removeCase - This method removes the specified case and its successor
	/// from the switch instruction. Note that this operation may reorder the		/// from the switch instruction. Note that this operation may reorder the
	/// remaining cases at index idx and above.		/// remaining cases at index idx and above.
	/// Note:		/// Note:
	/// This action invalidates iterators for all cases following the one rem oved,		/// This action invalidates iterators for all cases following the one rem oved,
	/// including the case_end() iterator.		/// including the case_end() iterator.
	void removeCase(CaseIt& i);		void removeCase(CaseIt i);
	unsigned getNumSuccessors() const { return getNumOperands()/2; }		unsigned getNumSuccessors() const { return getNumOperands()/2; }
	BasicBlock *getSuccessor(unsigned idx) const {		BasicBlock *getSuccessor(unsigned idx) const {
	assert(idx < getNumSuccessors() &&"Successor idx out of range for switc h!");		assert(idx < getNumSuccessors() &&"Successor idx out of range for switc h!");
	return cast<BasicBlock>(getOperand(idx*2+1));		return cast<BasicBlock>(getOperand(idx*2+1));
	}		}
	void setSuccessor(unsigned idx, BasicBlock *NewSucc) {		void setSuccessor(unsigned idx, BasicBlock *NewSucc) {
	assert(idx < getNumSuccessors() && "Successor # out of range for switch !");		assert(idx < getNumSuccessors() && "Successor # out of range for switch !");
	setOperand(idx*2+1, (Value*)NewSucc);		setOperand(idx*2+1, (Value*)NewSucc);
	}		}
	uint16_t hash() const {
	uint32_t NumberOfCases = (uint32_t)getNumCases();
	uint16_t Hash = (0xFFFF & NumberOfCases) ^ (NumberOfCases >> 16);
	for (ConstCaseIt i = case_begin(), e = case_end();
	i != e; ++i) {
	uint32_t NumItems = (uint32_t)i.getCaseValueEx().getNumItems();
	Hash = (Hash << 1) ^ (0xFFFF & NumItems) ^ (NumItems >> 16);
	}
	return Hash;
	}
	// Case iterators definition.
	template <class SwitchInstTy, class ConstantIntTy,
	class SubsetsItTy, class BasicBlockTy>
	class CaseIteratorT {
	protected:
	SwitchInstTy *SI;
	unsigned Index;
	SubsetsItTy SubsetIt;
	/// Initializes case iterator for given SwitchInst and for given
	/// case number.
	friend class SwitchInst;
	CaseIteratorT(SwitchInstTy *SI, unsigned SuccessorIndex,
	SubsetsItTy CaseValueIt) {
	this->SI = SI;
	Index = SuccessorIndex;
	this->SubsetIt = CaseValueIt;
	}
	public:
	typedef typename SubsetsItTy::reference IntegersSubsetRef;
	typedef CaseIteratorT<SwitchInstTy, ConstantIntTy,
	SubsetsItTy, BasicBlockTy> Self;
	CaseIteratorT(SwitchInstTy *SI, unsigned CaseNum) {
	this->SI = SI;
	Index = CaseNum;
	SubsetIt = SI->TheSubsets.begin();
	std::advance(SubsetIt, CaseNum);
	}
	/// Initializes case iterator for given SwitchInst and for given
	/// TerminatorInst's successor index.
	static Self fromSuccessorIndex(SwitchInstTy *SI, unsigned SuccessorInde
	x) {
	assert(SuccessorIndex < SI->getNumSuccessors() &&
	"Successor index # out of range!");
	return SuccessorIndex != 0 ?
	Self(SI, SuccessorIndex - 1) :
	Self(SI, DefaultPseudoIndex);
	}
	/// Resolves case value for current case.
	/// @deprecated
	ConstantIntTy *getCaseValue() {
	assert(Index < SI->getNumCases() && "Index out the number of cases.")
	;
	IntegersSubsetRef CaseRanges = *SubsetIt;
	// FIXME: Currently we work with ConstantInt based cases.
	// So return CaseValue as ConstantInt.
	return CaseRanges.getSingleNumber(0).toConstantInt();
	}
	/// Resolves case value for current case.
	IntegersSubsetRef getCaseValueEx() {
	assert(Index < SI->getNumCases() && "Index out the number of cases.")
	;
	return *SubsetIt;
	}
	/// Resolves successor for current case.
	BasicBlockTy *getCaseSuccessor() {
	assert((Index < SI->getNumCases() ||
	Index == DefaultPseudoIndex) &&
	"Index out the number of cases.");
	return SI->getSuccessor(getSuccessorIndex());
	}
	/// Returns number of current case.
	unsigned getCaseIndex() const { return Index; }
	/// Returns TerminatorInst's successor index for current case successor
	.
	unsigned getSuccessorIndex() const {
	assert((Index == DefaultPseudoIndex || Index < SI->getNumCases()) &&
	"Index out the number of cases.");
	return Index != DefaultPseudoIndex ? Index + 1 : 0;
	}
	Self operator++() {
	// Check index correctness after increment.
	// Note: Index == getNumCases() means end().
	assert(Index+1 <= SI->getNumCases() && "Index out the number of cases
	.");
	++Index;
	if (Index == 0)
	SubsetIt = SI->TheSubsets.begin();
	else
	++SubsetIt;
	return *this;
	}
	Self operator++(int) {
	Self tmp = *this;
	++(*this);
	return tmp;
	}
	Self operator--() {
	// Check index correctness after decrement.
	// Note: Index == getNumCases() means end().
	// Also allow "-1" iterator here. That will became valid after ++.
	unsigned NumCases = SI->getNumCases();
	assert((Index == 0 || Index-1 <= NumCases) &&
	"Index out the number of cases.");
	--Index;
	if (Index == NumCases) {
	SubsetIt = SI->TheSubsets.end();
	return *this;
	}
	if (Index != -1U)
	--SubsetIt;
	return *this;
	}
	Self operator--(int) {
	Self tmp = *this;
	--(*this);
	return tmp;
	}
	bool operator==(const Self& RHS) const {
	assert(RHS.SI == SI && "Incompatible operators.");
	return RHS.Index == Index;
	}
	bool operator!=(const Self& RHS) const {
	assert(RHS.SI == SI && "Incompatible operators.");
	return RHS.Index != Index;
	}
	};
	class CaseIt : public CaseIteratorT<SwitchInst, ConstantInt,
	SubsetsIt, BasicBlock> {
	typedef CaseIteratorT<SwitchInst, ConstantInt, SubsetsIt, BasicBlock>
	ParentTy;
	protected:
	friend class SwitchInst;
	CaseIt(SwitchInst *SI, unsigned CaseNum, SubsetsIt SubsetIt) :
	ParentTy(SI, CaseNum, SubsetIt) {}
	void updateCaseValueOperand(IntegersSubset& V) {
	SI->setOperand(2 + Index*2, reinterpret_cast<Value*>((Constant*)V));
	}
	public:
	CaseIt(SwitchInst *SI, unsigned CaseNum) : ParentTy(SI, CaseNum) {}
	CaseIt(const ParentTy& Src) : ParentTy(Src) {}
	/// Sets the new value for current case.
	/// @deprecated.
	void setValue(ConstantInt *V) {
	assert(Index < SI->getNumCases() && "Index out the number of cases.")
	;
	IntegersSubsetToBB Mapping;
	// FIXME: Currently we work with ConstantInt based cases.
	// So inititalize IntItem container directly from ConstantInt.
	Mapping.add(IntItem::fromConstantInt(V));
	*SubsetIt = Mapping.getCase();
	updateCaseValueOperand(*SubsetIt);
	}
	/// Sets the new value for current case.
	void setValueEx(IntegersSubset& V) {
	assert(Index < SI->getNumCases() && "Index out the number of cases.")
	;
	*SubsetIt = V;
	updateCaseValueOperand(*SubsetIt);
	}
	/// Sets the new successor for current case.
	void setSuccessor(BasicBlock *S) {
	SI->setSuccessor(getSuccessorIndex(), S);
	}
	};
	// Methods for support type inquiry through isa, cast, and dyn_cast:		// Methods for support type inquiry through isa, cast, and dyn_cast:
	static inline bool classof(const Instruction *I) {		static inline bool classof(const Instruction *I) {
	return I->getOpcode() == Instruction::Switch;		return I->getOpcode() == Instruction::Switch;
	}		}
	static inline bool classof(const Value *V) {		static inline bool classof(const Value *V) {
	return isa<Instruction>(V) && classof(cast<Instruction>(V));		return isa<Instruction>(V) && classof(cast<Instruction>(V));
	}		}
	private:		private:
	virtual BasicBlock *getSuccessorV(unsigned idx) const;		virtual BasicBlock *getSuccessorV(unsigned idx) const;
	virtual unsigned getNumSuccessorsV() const;		virtual unsigned getNumSuccessorsV() const;
	virtual void setSuccessorV(unsigned idx, BasicBlock *B);		virtual void setSuccessorV(unsigned idx, BasicBlock *B);
	skipping to change at line 3012		skipping to change at line 2902
	/// setAttributes - Set the parameter attributes for this invoke.		/// setAttributes - Set the parameter attributes for this invoke.
	///		///
	void setAttributes(const AttributeSet &Attrs) { AttributeList = Attrs; }		void setAttributes(const AttributeSet &Attrs) { AttributeList = Attrs; }
	/// addAttribute - adds the attribute to the list of attributes.		/// addAttribute - adds the attribute to the list of attributes.
	void addAttribute(unsigned i, Attribute::AttrKind attr);		void addAttribute(unsigned i, Attribute::AttrKind attr);
	/// removeAttribute - removes the attribute from the list of attributes.		/// removeAttribute - removes the attribute from the list of attributes.
	void removeAttribute(unsigned i, Attribute attr);		void removeAttribute(unsigned i, Attribute attr);
	/// \brief Determine whether this call has the NoAlias attribute.		/// \brief Determine whether this call has the given attribute.
	bool hasFnAttr(Attribute::AttrKind A) const;		bool hasFnAttr(Attribute::AttrKind A) const {
			assert(A != Attribute::NoBuiltin &&
			"Use CallInst::isNoBuiltin() to check for Attribute::NoBuiltin")
			;
			return hasFnAttrImpl(A);
			}
	/// \brief Determine whether the call or the callee has the given attribu tes.		/// \brief Determine whether the call or the callee has the given attribu tes.
	bool paramHasAttr(unsigned i, Attribute::AttrKind A) const;		bool paramHasAttr(unsigned i, Attribute::AttrKind A) const;
	/// \brief Extract the alignment for a call or parameter (0=unknown).		/// \brief Extract the alignment for a call or parameter (0=unknown).
	unsigned getParamAlignment(unsigned i) const {		unsigned getParamAlignment(unsigned i) const {
	return AttributeList.getParamAlignment(i);		return AttributeList.getParamAlignment(i);
	}		}
			/// \brief Return true if the call should not be treated as a call to a
			/// builtin.
			bool isNoBuiltin() const {
			// We assert in hasFnAttr if one passes in Attribute::NoBuiltin, so we
			have
			// to check it by hand.
			return hasFnAttrImpl(Attribute::NoBuiltin) &&
			!hasFnAttrImpl(Attribute::Builtin);
			}
	/// \brief Return true if the call should not be inlined.		/// \brief Return true if the call should not be inlined.
	bool isNoInline() const { return hasFnAttr(Attribute::NoInline); }		bool isNoInline() const { return hasFnAttr(Attribute::NoInline); }
	void setIsNoInline() {		void setIsNoInline() {
	addAttribute(AttributeSet::FunctionIndex, Attribute::NoInline);		addAttribute(AttributeSet::FunctionIndex, Attribute::NoInline);
	}		}
	/// \brief Determine if the call does not access memory.		/// \brief Determine if the call does not access memory.
	bool doesNotAccessMemory() const {		bool doesNotAccessMemory() const {
	return hasFnAttr(Attribute::ReadNone);		return hasFnAttr(Attribute::ReadNone);
	}		}
	skipping to change at line 3129		skipping to change at line 3032
	}		}
	static inline bool classof(const Value *V) {		static inline bool classof(const Value *V) {
	return isa<Instruction>(V) && classof(cast<Instruction>(V));		return isa<Instruction>(V) && classof(cast<Instruction>(V));
	}		}
	private:		private:
	virtual BasicBlock *getSuccessorV(unsigned idx) const;		virtual BasicBlock *getSuccessorV(unsigned idx) const;
	virtual unsigned getNumSuccessorsV() const;		virtual unsigned getNumSuccessorsV() const;
	virtual void setSuccessorV(unsigned idx, BasicBlock *B);		virtual void setSuccessorV(unsigned idx, BasicBlock *B);
			bool hasFnAttrImpl(Attribute::AttrKind A) const;
	// Shadow Instruction::setInstructionSubclassData with a private forwardi ng		// Shadow Instruction::setInstructionSubclassData with a private forwardi ng
	// method so that subclasses cannot accidentally use it.		// method so that subclasses cannot accidentally use it.
	void setInstructionSubclassData(unsigned short D) {		void setInstructionSubclassData(unsigned short D) {
	Instruction::setInstructionSubclassData(D);		Instruction::setInstructionSubclassData(D);
	}		}
	};		};
	template <>		template <>
	struct OperandTraits<InvokeInst> : public VariadicOperandTraits<InvokeInst, 3> {		struct OperandTraits<InvokeInst> : public VariadicOperandTraits<InvokeInst, 3> {
	};		};
	skipping to change at line 3700		skipping to change at line 3605
	// Methods for support type inquiry through isa, cast, and dyn_cast:		// Methods for support type inquiry through isa, cast, and dyn_cast:
	static inline bool classof(const Instruction *I) {		static inline bool classof(const Instruction *I) {
	return I->getOpcode() == BitCast;		return I->getOpcode() == BitCast;
	}		}
	static inline bool classof(const Value *V) {		static inline bool classof(const Value *V) {
	return isa<Instruction>(V) && classof(cast<Instruction>(V));		return isa<Instruction>(V) && classof(cast<Instruction>(V));
	}		}
	};		};
			//===----------------------------------------------------------------------
			===//
			// AddrSpaceCastInst Class
			//===----------------------------------------------------------------------
			===//
			/// \brief This class represents a conversion between pointers from
			/// one address space to another.
			class AddrSpaceCastInst : public CastInst {
			protected:
			/// \brief Clone an identical AddrSpaceCastInst
			virtual AddrSpaceCastInst *clone_impl() const;
			public:
			/// \brief Constructor with insert-before-instruction semantics
			AddrSpaceCastInst(
			Value *S, ///< The value to be casted
			Type *Ty, ///< The type to casted to
			const Twine &NameStr = "", ///< A name for the new instruction
			Instruction *InsertBefore = 0 ///< Where to insert the new instruction
			);
			/// \brief Constructor with insert-at-end-of-block semantics
			AddrSpaceCastInst(
			Value *S, ///< The value to be casted
			Type *Ty, ///< The type to casted to
			const Twine &NameStr, ///< A name for the new instruction
			BasicBlock *InsertAtEnd ///< The block to insert the instruction
			into
			);
			// Methods for support type inquiry through isa, cast, and dyn_cast:
			static inline bool classof(const Instruction *I) {
			return I->getOpcode() == AddrSpaceCast;
			}
			static inline bool classof(const Value *V) {
			return isa<Instruction>(V) && classof(cast<Instruction>(V));
			}
			};
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 29 change blocks.
	279 lines changed or deleted		224 lines changed or added

	Instrumentation.h		Instrumentation.h
	skipping to change at line 19		skipping to change at line 19
	//		//
	// This file defines constructor functions for instrumentation passes.		// This file defines constructor functions for instrumentation passes.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_TRANSFORMS_INSTRUMENTATION_H		#ifndef LLVM_TRANSFORMS_INSTRUMENTATION_H
	#define LLVM_TRANSFORMS_INSTRUMENTATION_H		#define LLVM_TRANSFORMS_INSTRUMENTATION_H
	#include "llvm/ADT/StringRef.h"		#include "llvm/ADT/StringRef.h"
			#if defined(__GNUC__) && defined(__linux__)
			inline void *getDFSanArgTLSPtrForJIT() {
			extern __thread __attribute__((tls_model("initial-exec")))
			void *__dfsan_arg_tls;
			return (void *)&__dfsan_arg_tls;
			}
			inline void *getDFSanRetValTLSPtrForJIT() {
			extern __thread __attribute__((tls_model("initial-exec")))
			void *__dfsan_retval_tls;
			return (void *)&__dfsan_retval_tls;
			}
			#endif
	namespace llvm {		namespace llvm {
	class ModulePass;		class ModulePass;
	class FunctionPass;		class FunctionPass;
	// Insert edge profiling instrumentation
	ModulePass *createEdgeProfilerPass();
	// Insert optimal edge profiling instrumentation
	ModulePass *createOptimalEdgeProfilerPass();
	// Insert path profiling instrumentation
	ModulePass *createPathProfilerPass();
	// Insert GCOV profiling instrumentation		// Insert GCOV profiling instrumentation
	struct GCOVOptions {		struct GCOVOptions {
	static GCOVOptions getDefault();		static GCOVOptions getDefault();
	// Specify whether to emit .gcno files.		// Specify whether to emit .gcno files.
	bool EmitNotes;		bool EmitNotes;
	// Specify whether to modify the program to emit .gcda files when run.		// Specify whether to modify the program to emit .gcda files when run.
	bool EmitData;		bool EmitData;
	skipping to change at line 77		skipping to change at line 82
	bool CheckInitOrder = true, StringRef BlacklistFile = StringRef(),		bool CheckInitOrder = true, StringRef BlacklistFile = StringRef(),
	bool ZeroBaseShadow = false);		bool ZeroBaseShadow = false);
	// Insert MemorySanitizer instrumentation (detection of uninitialized reads )		// Insert MemorySanitizer instrumentation (detection of uninitialized reads )
	FunctionPass *createMemorySanitizerPass(bool TrackOrigins = false,		FunctionPass *createMemorySanitizerPass(bool TrackOrigins = false,
	StringRef BlacklistFile = StringRef ());		StringRef BlacklistFile = StringRef ());
	// Insert ThreadSanitizer (race detection) instrumentation		// Insert ThreadSanitizer (race detection) instrumentation
	FunctionPass *createThreadSanitizerPass(StringRef BlacklistFile = StringRef ());		FunctionPass *createThreadSanitizerPass(StringRef BlacklistFile = StringRef ());
			// Insert DataFlowSanitizer (dynamic data flow analysis) instrumentation
			ModulePass *createDataFlowSanitizerPass(StringRef ABIListFile = StringRef()
			,
			void *(*getArgTLS)() = 0,
			void *(*getRetValTLS)() = 0);
			#if defined(__GNUC__) && defined(__linux__)
			inline ModulePass *createDataFlowSanitizerPassForJIT(StringRef ABIListFile
			=
			StringRef()) {
			return createDataFlowSanitizerPass(ABIListFile, getDFSanArgTLSPtrForJIT,
			getDFSanRetValTLSPtrForJIT);
			}
			#endif
	// BoundsChecking - This pass instruments the code to perform run-time boun ds		// BoundsChecking - This pass instruments the code to perform run-time boun ds
	// checking on loads, stores, and other memory intrinsics.		// checking on loads, stores, and other memory intrinsics.
	FunctionPass *createBoundsCheckingPass();		FunctionPass *createBoundsCheckingPass();
			/// createDebugIRPass - Enable interactive stepping through LLVM IR in LLDB
			(or
			/// GDB) and generate a file with the LLVM IR to be
			/// displayed in the debugger.
			///
			/// Existing debug metadata is preserved (but may be modified) in order to
			allow
			/// accessing variables in the original source. The line table and file
			/// information is modified to correspond to the lines in the LLVM IR. If
			/// Filename and Directory are empty, a file name is generated based on exi
			sting
			/// debug information. If no debug information is available, a temporary fi
			le
			/// name is generated.
			///
			/// @param HideDebugIntrinsics Omit debug intrinsics in emitted IR source
			file.
			/// @param HideDebugMetadata Omit debug metadata in emitted IR source fi
			le.
			/// @param Directory Embed this directory in the debug informati
			on.
			/// @param Filename Embed this file name in the debug informati
			on.
			ModulePass *createDebugIRPass(bool HideDebugIntrinsics,
			bool HideDebugMetadata,
			StringRef Directory = StringRef(),
			StringRef Filename = StringRef());
			/// createDebugIRPass - Enable interactive stepping through LLVM IR in LLDB
			/// (or GDB) with an existing IR file on disk. When cre
			ating
			/// a DebugIR pass with this function, no source file i
			s
			/// output to disk and the existing one is unmodified.
			Debug
			/// metadata in the Module is created/updated to point
			to
			/// the existing textual IR file on disk.
			/// NOTE: If the IR file to be debugged is not on disk, use the version of
			this
			/// function with parameters in order to generate the file that will
			be
			/// seen by the debugger.
			ModulePass *createDebugIRPass();
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 4 change blocks.
	9 lines changed or deleted		74 lines changed or added

	IntervalMap.h		IntervalMap.h
	skipping to change at line 495		skipping to change at line 495
	static inline void *getFromVoidPointer(void *P) { return P; }		static inline void *getFromVoidPointer(void *P) { return P; }
	enum { NumLowBitsAvailable = Log2CacheLine };		enum { NumLowBitsAvailable = Log2CacheLine };
	};		};
	PointerIntPair<void*, Log2CacheLine, unsigned, CacheAlignedPointerTraits> pip;		PointerIntPair<void*, Log2CacheLine, unsigned, CacheAlignedPointerTraits> pip;
	public:		public:
	/// NodeRef - Create a null ref.		/// NodeRef - Create a null ref.
	NodeRef() {}		NodeRef() {}
	/// operator bool - Detect a null ref.		/// operator bool - Detect a null ref.
	operator bool() const { return pip.getOpaqueValue(); }		LLVM_EXPLICIT operator bool() const { return pip.getOpaqueValue(); }
	/// NodeRef - Create a reference to the node p with n elements.		/// NodeRef - Create a reference to the node p with n elements.
	template <typename NodeT>		template <typename NodeT>
	NodeRef(NodeT *p, unsigned n) : pip(p, n - 1) {		NodeRef(NodeT *p, unsigned n) : pip(p, n - 1) {
	assert(n <= NodeT::Capacity && "Size too big for node");		assert(n <= NodeT::Capacity && "Size too big for node");
	}		}
	/// size - Return the number of elements in the referenced node.		/// size - Return the number of elements in the referenced node.
	unsigned size() const { return pip.getInt() + 1; }		unsigned size() const { return pip.getInt() + 1; }
	skipping to change at line 611		skipping to change at line 611
	unsigned i = safeFind(0, x);		unsigned i = safeFind(0, x);
	return Traits::startLess(x, start(i)) ? NotFound : value(i);		return Traits::startLess(x, start(i)) ? NotFound : value(i);
	}		}
	unsigned insertFrom(unsigned &Pos, unsigned Size, KeyT a, KeyT b, ValT y) ;		unsigned insertFrom(unsigned &Pos, unsigned Size, KeyT a, KeyT b, ValT y) ;
	};		};
	/// insertFrom - Add mapping of [a;b] to y if possible, coalescing as much as		/// insertFrom - Add mapping of [a;b] to y if possible, coalescing as much as
	/// possible. This may cause the node to grow by 1, or it may cause the nod e		/// possible. This may cause the node to grow by 1, or it may cause the nod e
	/// to shrink because of coalescing.		/// to shrink because of coalescing.
	/// @param i Starting index = insertFrom(0, size, a)		/// @param Pos Starting index = insertFrom(0, size, a)
	/// @param Size Number of elements in node.		/// @param Size Number of elements in node.
	/// @param a Interval start.		/// @param a Interval start.
	/// @param b Interval stop.		/// @param b Interval stop.
	/// @param y Value be mapped.		/// @param y Value be mapped.
	/// @return (insert position, new size), or (i, Capacity+1) on overflow .		/// @return (insert position, new size), or (i, Capacity+1) on overflow .
	template <typename KeyT, typename ValT, unsigned N, typename Traits>		template <typename KeyT, typename ValT, unsigned N, typename Traits>
	unsigned LeafNode<KeyT, ValT, N, Traits>::		unsigned LeafNode<KeyT, ValT, N, Traits>::
	insertFrom(unsigned &Pos, unsigned Size, KeyT a, KeyT b, ValT y) {		insertFrom(unsigned &Pos, unsigned Size, KeyT a, KeyT b, ValT y) {
	unsigned i = Pos;		unsigned i = Pos;
	assert(i <= Size && Size <= N && "Invalid index");		assert(i <= Size && Size <= N && "Invalid index");
	skipping to change at line 1951		skipping to change at line 1951
	// Update path cache for the new right sibling position.		// Update path cache for the new right sibling position.
	if (P.valid()) {		if (P.valid()) {
	P.reset(Level + 1);		P.reset(Level + 1);
	P.offset(Level + 1) = 0;		P.offset(Level + 1) = 0;
	}		}
	}		}
	/// overflow - Distribute entries of the current node evenly among		/// overflow - Distribute entries of the current node evenly among
	/// its siblings and ensure that the current node is not full.		/// its siblings and ensure that the current node is not full.
	/// This may require allocating a new node.		/// This may require allocating a new node.
	/// @param NodeT The type of node at Level (Leaf or Branch).		/// @tparam NodeT The type of node at Level (Leaf or Branch).
	/// @param Level path index of the overflowing node.		/// @param Level path index of the overflowing node.
	/// @return True when the tree height was changed.		/// @return True when the tree height was changed.
	template <typename KeyT, typename ValT, unsigned N, typename Traits>		template <typename KeyT, typename ValT, unsigned N, typename Traits>
	template <typename NodeT>		template <typename NodeT>
	bool IntervalMap<KeyT, ValT, N, Traits>::		bool IntervalMap<KeyT, ValT, N, Traits>::
	iterator::overflow(unsigned Level) {		iterator::overflow(unsigned Level) {
	using namespace IntervalMapImpl;		using namespace IntervalMapImpl;
	Path &P = this->path;		Path &P = this->path;
	unsigned CurSize[4];		unsigned CurSize[4];
	NodeT *Node[4];		NodeT *Node[4];
End of changes. 3 change blocks.
	3 lines changed or deleted		3 lines changed or added

	Intrinsics.gen		Intrinsics.gen
	skipping to change at line 19		skipping to change at line 19
	// VisualStudio defines setjmp as _setjmp		// VisualStudio defines setjmp as _setjmp
	#if defined(_MSC_VER) && defined(setjmp) && \		#if defined(_MSC_VER) && defined(setjmp) && \
	!defined(setjmp_undefined_for_msvc)		!defined(setjmp_undefined_for_msvc)
	# pragma push_macro("setjmp")		# pragma push_macro("setjmp")
	# undef setjmp		# undef setjmp
	# define setjmp_undefined_for_msvc		# define setjmp_undefined_for_msvc
	#endif		#endif
	// Enum values for Intrinsics.h		// Enum values for Intrinsics.h
	#ifdef GET_INTRINSIC_ENUM_VALUES		#ifdef GET_INTRINSIC_ENUM_VALUES
			aarch64_neon_fcvtas, // llvm.aarch64.neon.fcvtas
			aarch64_neon_fcvtau, // llvm.aarch64.neon.fcvtau
			aarch64_neon_fcvtms, // llvm.aarch64.neon.fcvtms
			aarch64_neon_fcvtmu, // llvm.aarch64.neon.fcvtmu
			aarch64_neon_fcvtns, // llvm.aarch64.neon.fcvtns
			aarch64_neon_fcvtnu, // llvm.aarch64.neon.fcvtnu
			aarch64_neon_fcvtps, // llvm.aarch64.neon.fcvtps
			aarch64_neon_fcvtpu, // llvm.aarch64.neon.fcvtpu
			aarch64_neon_fcvtxn, // llvm.aarch64.neon.fcvtxn
			aarch64_neon_fcvtzs, // llvm.aarch64.neon.fcvtzs
			aarch64_neon_fcvtzu, // llvm.aarch64.neon.fcvtzu
			aarch64_neon_frintn, // llvm.aarch64.neon.frintn
			aarch64_neon_fsqrt, // llvm.aarch64.neon.fsqrt
			aarch64_neon_rbit, // llvm.aarch64.neon.rbit
			aarch64_neon_saddlv, // llvm.aarch64.neon.saddlv
			aarch64_neon_sha1c, // llvm.aarch64.neon.sha1c
			aarch64_neon_sha1m, // llvm.aarch64.neon.sha1m
			aarch64_neon_sha1p, // llvm.aarch64.neon.sha1p
			aarch64_neon_smaxv, // llvm.aarch64.neon.smaxv
			aarch64_neon_sminv, // llvm.aarch64.neon.sminv
			aarch64_neon_suqadd, // llvm.aarch64.neon.suqadd
			aarch64_neon_uaddlv, // llvm.aarch64.neon.uaddlv
			aarch64_neon_umaxv, // llvm.aarch64.neon.umaxv
			aarch64_neon_uminv, // llvm.aarch64.neon.uminv
			aarch64_neon_usqadd, // llvm.aarch64.neon.usqadd
			aarch64_neon_vabd, // llvm.aarch64.neon.vabd
			aarch64_neon_vabs, // llvm.aarch64.neon.vabs
			aarch64_neon_vacgeq, // llvm.aarch64.neon.vacgeq
			aarch64_neon_vacgtq, // llvm.aarch64.neon.vacgtq
			aarch64_neon_vaddds, // llvm.aarch64.neon.vaddds
			aarch64_neon_vadddu, // llvm.aarch64.neon.vadddu
			aarch64_neon_vaddv, // llvm.aarch64.neon.vaddv
			aarch64_neon_vcage, // llvm.aarch64.neon.vcage
			aarch64_neon_vcagt, // llvm.aarch64.neon.vcagt
			aarch64_neon_vceq, // llvm.aarch64.neon.vceq
			aarch64_neon_vcge, // llvm.aarch64.neon.vcge
			aarch64_neon_vcgt, // llvm.aarch64.neon.vcgt
			aarch64_neon_vchi, // llvm.aarch64.neon.vchi
			aarch64_neon_vchs, // llvm.aarch64.neon.vchs
			aarch64_neon_vclez, // llvm.aarch64.neon.vclez
			aarch64_neon_vcltz, // llvm.aarch64.neon.vcltz
			aarch64_neon_vcvtd_n_s64_f64, // llvm.aarch64.neon.vcvtd.n.
			s64.f64
			aarch64_neon_vcvtd_n_u64_f64, // llvm.aarch64.neon.vcvtd.n.
			u64.f64
			aarch64_neon_vcvtf32_n_s32, // llvm.aarch64.neon.vcvtf32.
			n.s32
			aarch64_neon_vcvtf32_n_u32, // llvm.aarch64.neon.vcvtf32.
			n.u32
			aarch64_neon_vcvtf32_s32, // llvm.aarch64.neon.vcvtf32.
			s32
			aarch64_neon_vcvtf32_u32, // llvm.aarch64.neon.vcvtf32.
			u32
			aarch64_neon_vcvtf64_n_s64, // llvm.aarch64.neon.vcvtf64.
			n.s64
			aarch64_neon_vcvtf64_n_u64, // llvm.aarch64.neon.vcvtf64.
			n.u64
			aarch64_neon_vcvtf64_s64, // llvm.aarch64.neon.vcvtf64.
			s64
			aarch64_neon_vcvtf64_u64, // llvm.aarch64.neon.vcvtf64.
			u64
			aarch64_neon_vcvts_n_s32_f32, // llvm.aarch64.neon.vcvts.n.
			s32.f32
			aarch64_neon_vcvts_n_u32_f32, // llvm.aarch64.neon.vcvts.n.
			u32.f32
			aarch64_neon_vld1x2, // llvm.aarch64.neon.vld1x2
			aarch64_neon_vld1x3, // llvm.aarch64.neon.vld1x3
			aarch64_neon_vld1x4, // llvm.aarch64.neon.vld1x4
			aarch64_neon_vmaxnm, // llvm.aarch64.neon.vmaxnm
			aarch64_neon_vmaxnmv, // llvm.aarch64.neon.vmaxnmv
			aarch64_neon_vmaxv, // llvm.aarch64.neon.vmaxv
			aarch64_neon_vminnm, // llvm.aarch64.neon.vminnm
			aarch64_neon_vminnmv, // llvm.aarch64.neon.vminnmv
			aarch64_neon_vminv, // llvm.aarch64.neon.vminv
			aarch64_neon_vmulx, // llvm.aarch64.neon.vmulx
			aarch64_neon_vneg, // llvm.aarch64.neon.vneg
			aarch64_neon_vpadd, // llvm.aarch64.neon.vpadd
			aarch64_neon_vpfadd, // llvm.aarch64.neon.vpfadd
			aarch64_neon_vpfaddq, // llvm.aarch64.neon.vpfaddq
			aarch64_neon_vpfmaxnm, // llvm.aarch64.neon.vpfmaxnm
			aarch64_neon_vpfmaxnmq, // llvm.aarch64.neon.vpfmaxnm
			q
			aarch64_neon_vpfminnm, // llvm.aarch64.neon.vpfminnm
			aarch64_neon_vpfminnmq, // llvm.aarch64.neon.vpfminnm
			q
			aarch64_neon_vpmax, // llvm.aarch64.neon.vpmax
			aarch64_neon_vpmaxnm, // llvm.aarch64.neon.vpmaxnm
			aarch64_neon_vpmaxq, // llvm.aarch64.neon.vpmaxq
			aarch64_neon_vpmin, // llvm.aarch64.neon.vpmin
			aarch64_neon_vpminnm, // llvm.aarch64.neon.vpminnm
			aarch64_neon_vpminq, // llvm.aarch64.neon.vpminq
			aarch64_neon_vqdmlal, // llvm.aarch64.neon.vqdmlal
			aarch64_neon_vqdmlsl, // llvm.aarch64.neon.vqdmlsl
			aarch64_neon_vqrshls, // llvm.aarch64.neon.vqrshls
			aarch64_neon_vqrshlu, // llvm.aarch64.neon.vqrshlu
			aarch64_neon_vqshls, // llvm.aarch64.neon.vqshls
			aarch64_neon_vqshls_n, // llvm.aarch64.neon.vqshls.n
			aarch64_neon_vqshlu, // llvm.aarch64.neon.vqshlu
			aarch64_neon_vqshlu_n, // llvm.aarch64.neon.vqshlu.n
			aarch64_neon_vqshlus_n, // llvm.aarch64.neon.vqshlus.
			n
			aarch64_neon_vrecpx, // llvm.aarch64.neon.vrecpx
			aarch64_neon_vrshlds, // llvm.aarch64.neon.vrshlds
			aarch64_neon_vrshldu, // llvm.aarch64.neon.vrshldu
			aarch64_neon_vrshrn, // llvm.aarch64.neon.vrshrn
			aarch64_neon_vrsrads_n, // llvm.aarch64.neon.vrsrads.
			n
			aarch64_neon_vrsradu_n, // llvm.aarch64.neon.vrsradu.
			n
			aarch64_neon_vshld_n, // llvm.aarch64.neon.vshld.n
			aarch64_neon_vshlds, // llvm.aarch64.neon.vshlds
			aarch64_neon_vshldu, // llvm.aarch64.neon.vshldu
			aarch64_neon_vshrds_n, // llvm.aarch64.neon.vshrds.n
			aarch64_neon_vshrdu_n, // llvm.aarch64.neon.vshrdu.n
			aarch64_neon_vsli, // llvm.aarch64.neon.vsli
			aarch64_neon_vsqadd, // llvm.aarch64.neon.vsqadd
			aarch64_neon_vsqrshrn, // llvm.aarch64.neon.vsqrshrn
			aarch64_neon_vsqrshrun, // llvm.aarch64.neon.vsqrshru
			n
			aarch64_neon_vsqshlu, // llvm.aarch64.neon.vsqshlu
			aarch64_neon_vsqshrn, // llvm.aarch64.neon.vsqshrn
			aarch64_neon_vsqshrun, // llvm.aarch64.neon.vsqshrun
			aarch64_neon_vsrads_n, // llvm.aarch64.neon.vsrads.n
			aarch64_neon_vsradu_n, // llvm.aarch64.neon.vsradu.n
			aarch64_neon_vsri, // llvm.aarch64.neon.vsri
			aarch64_neon_vsrshr, // llvm.aarch64.neon.vsrshr
			aarch64_neon_vst1x2, // llvm.aarch64.neon.vst1x2
			aarch64_neon_vst1x3, // llvm.aarch64.neon.vst1x3
			aarch64_neon_vst1x4, // llvm.aarch64.neon.vst1x4
			aarch64_neon_vsubds, // llvm.aarch64.neon.vsubds
			aarch64_neon_vsubdu, // llvm.aarch64.neon.vsubdu
			aarch64_neon_vtbl1, // llvm.aarch64.neon.vtbl1
			aarch64_neon_vtbl2, // llvm.aarch64.neon.vtbl2
			aarch64_neon_vtbl3, // llvm.aarch64.neon.vtbl3
			aarch64_neon_vtbl4, // llvm.aarch64.neon.vtbl4
			aarch64_neon_vtbx1, // llvm.aarch64.neon.vtbx1
			aarch64_neon_vtbx2, // llvm.aarch64.neon.vtbx2
			aarch64_neon_vtbx3, // llvm.aarch64.neon.vtbx3
			aarch64_neon_vtbx4, // llvm.aarch64.neon.vtbx4
			aarch64_neon_vtstd, // llvm.aarch64.neon.vtstd
			aarch64_neon_vuqadd, // llvm.aarch64.neon.vuqadd
			aarch64_neon_vuqrshrn, // llvm.aarch64.neon.vuqrshrn
			aarch64_neon_vuqshrn, // llvm.aarch64.neon.vuqshrn
			aarch64_neon_vurshr, // llvm.aarch64.neon.vurshr
			aarch64_neon_xtn, // llvm.aarch64.neon.xtn
	adjust_trampoline, // llvm.adjust.trampoline		adjust_trampoline, // llvm.adjust.trampoline
	annotation, // llvm.annotation		annotation, // llvm.annotation
	arm_cdp, // llvm.arm.cdp		arm_cdp, // llvm.arm.cdp
	arm_cdp2, // llvm.arm.cdp2		arm_cdp2, // llvm.arm.cdp2
			arm_clrex, // llvm.arm.clrex
			arm_crc32b, // llvm.arm.crc32b
			arm_crc32cb, // llvm.arm.crc32cb
			arm_crc32ch, // llvm.arm.crc32ch
			arm_crc32cw, // llvm.arm.crc32cw
			arm_crc32h, // llvm.arm.crc32h
			arm_crc32w, // llvm.arm.crc32w
			arm_dmb, // llvm.arm.dmb
			arm_dsb, // llvm.arm.dsb
	arm_get_fpscr, // llvm.arm.get.fpscr		arm_get_fpscr, // llvm.arm.get.fpscr
			arm_ldrex, // llvm.arm.ldrex
	arm_ldrexd, // llvm.arm.ldrexd		arm_ldrexd, // llvm.arm.ldrexd
	arm_mcr, // llvm.arm.mcr		arm_mcr, // llvm.arm.mcr
	arm_mcr2, // llvm.arm.mcr2		arm_mcr2, // llvm.arm.mcr2
	arm_mcrr, // llvm.arm.mcrr		arm_mcrr, // llvm.arm.mcrr
	arm_mcrr2, // llvm.arm.mcrr2		arm_mcrr2, // llvm.arm.mcrr2
	arm_mrc, // llvm.arm.mrc		arm_mrc, // llvm.arm.mrc
	arm_mrc2, // llvm.arm.mrc2		arm_mrc2, // llvm.arm.mrc2
			arm_neon_aesd, // llvm.arm.neon.aesd
			arm_neon_aese, // llvm.arm.neon.aese
			arm_neon_aesimc, // llvm.arm.neon.aesimc
			arm_neon_aesmc, // llvm.arm.neon.aesmc
			arm_neon_sha1c, // llvm.arm.neon.sha1c
			arm_neon_sha1h, // llvm.arm.neon.sha1h
			arm_neon_sha1m, // llvm.arm.neon.sha1m
			arm_neon_sha1p, // llvm.arm.neon.sha1p
			arm_neon_sha1su0, // llvm.arm.neon.sha1su0
			arm_neon_sha1su1, // llvm.arm.neon.sha1su1
			arm_neon_sha256h, // llvm.arm.neon.sha256h
			arm_neon_sha256h2, // llvm.arm.neon.sha256h2
			arm_neon_sha256su0, // llvm.arm.neon.sha256su0
			arm_neon_sha256su1, // llvm.arm.neon.sha256su1
	arm_neon_vabds, // llvm.arm.neon.vabds		arm_neon_vabds, // llvm.arm.neon.vabds
	arm_neon_vabdu, // llvm.arm.neon.vabdu		arm_neon_vabdu, // llvm.arm.neon.vabdu
	arm_neon_vabs, // llvm.arm.neon.vabs		arm_neon_vabs, // llvm.arm.neon.vabs
	arm_neon_vacged, // llvm.arm.neon.vacged		arm_neon_vacged, // llvm.arm.neon.vacged
	arm_neon_vacgeq, // llvm.arm.neon.vacgeq		arm_neon_vacgeq, // llvm.arm.neon.vacgeq
	arm_neon_vacgtd, // llvm.arm.neon.vacgtd		arm_neon_vacgtd, // llvm.arm.neon.vacgtd
	arm_neon_vacgtq, // llvm.arm.neon.vacgtq		arm_neon_vacgtq, // llvm.arm.neon.vacgtq
	arm_neon_vaddhn, // llvm.arm.neon.vaddhn
	arm_neon_vbsl, // llvm.arm.neon.vbsl		arm_neon_vbsl, // llvm.arm.neon.vbsl
	arm_neon_vcls, // llvm.arm.neon.vcls		arm_neon_vcls, // llvm.arm.neon.vcls
	arm_neon_vclz, // llvm.arm.neon.vclz		arm_neon_vclz, // llvm.arm.neon.vclz
	arm_neon_vcnt, // llvm.arm.neon.vcnt		arm_neon_vcnt, // llvm.arm.neon.vcnt
			arm_neon_vcvtas, // llvm.arm.neon.vcvtas
			arm_neon_vcvtau, // llvm.arm.neon.vcvtau
	arm_neon_vcvtfp2fxs, // llvm.arm.neon.vcvtfp2fxs		arm_neon_vcvtfp2fxs, // llvm.arm.neon.vcvtfp2fxs
	arm_neon_vcvtfp2fxu, // llvm.arm.neon.vcvtfp2fxu		arm_neon_vcvtfp2fxu, // llvm.arm.neon.vcvtfp2fxu
	arm_neon_vcvtfp2hf, // llvm.arm.neon.vcvtfp2hf		arm_neon_vcvtfp2hf, // llvm.arm.neon.vcvtfp2hf
	arm_neon_vcvtfxs2fp, // llvm.arm.neon.vcvtfxs2fp		arm_neon_vcvtfxs2fp, // llvm.arm.neon.vcvtfxs2fp
	arm_neon_vcvtfxu2fp, // llvm.arm.neon.vcvtfxu2fp		arm_neon_vcvtfxu2fp, // llvm.arm.neon.vcvtfxu2fp
	arm_neon_vcvthf2fp, // llvm.arm.neon.vcvthf2fp		arm_neon_vcvthf2fp, // llvm.arm.neon.vcvthf2fp
			arm_neon_vcvtms, // llvm.arm.neon.vcvtms
			arm_neon_vcvtmu, // llvm.arm.neon.vcvtmu
			arm_neon_vcvtns, // llvm.arm.neon.vcvtns
			arm_neon_vcvtnu, // llvm.arm.neon.vcvtnu
			arm_neon_vcvtps, // llvm.arm.neon.vcvtps
			arm_neon_vcvtpu, // llvm.arm.neon.vcvtpu
	arm_neon_vhadds, // llvm.arm.neon.vhadds		arm_neon_vhadds, // llvm.arm.neon.vhadds
	arm_neon_vhaddu, // llvm.arm.neon.vhaddu		arm_neon_vhaddu, // llvm.arm.neon.vhaddu
	arm_neon_vhsubs, // llvm.arm.neon.vhsubs		arm_neon_vhsubs, // llvm.arm.neon.vhsubs
	arm_neon_vhsubu, // llvm.arm.neon.vhsubu		arm_neon_vhsubu, // llvm.arm.neon.vhsubu
	arm_neon_vld1, // llvm.arm.neon.vld1		arm_neon_vld1, // llvm.arm.neon.vld1
	arm_neon_vld2, // llvm.arm.neon.vld2		arm_neon_vld2, // llvm.arm.neon.vld2
	arm_neon_vld2lane, // llvm.arm.neon.vld2lane		arm_neon_vld2lane, // llvm.arm.neon.vld2lane
	arm_neon_vld3, // llvm.arm.neon.vld3		arm_neon_vld3, // llvm.arm.neon.vld3
	arm_neon_vld3lane, // llvm.arm.neon.vld3lane		arm_neon_vld3lane, // llvm.arm.neon.vld3lane
	arm_neon_vld4, // llvm.arm.neon.vld4		arm_neon_vld4, // llvm.arm.neon.vld4
	arm_neon_vld4lane, // llvm.arm.neon.vld4lane		arm_neon_vld4lane, // llvm.arm.neon.vld4lane
			arm_neon_vmaxnm, // llvm.arm.neon.vmaxnm
	arm_neon_vmaxs, // llvm.arm.neon.vmaxs		arm_neon_vmaxs, // llvm.arm.neon.vmaxs
	arm_neon_vmaxu, // llvm.arm.neon.vmaxu		arm_neon_vmaxu, // llvm.arm.neon.vmaxu
			arm_neon_vminnm, // llvm.arm.neon.vminnm
	arm_neon_vmins, // llvm.arm.neon.vmins		arm_neon_vmins, // llvm.arm.neon.vmins
	arm_neon_vminu, // llvm.arm.neon.vminu		arm_neon_vminu, // llvm.arm.neon.vminu
	arm_neon_vmullp, // llvm.arm.neon.vmullp		arm_neon_vmullp, // llvm.arm.neon.vmullp
	arm_neon_vmulls, // llvm.arm.neon.vmulls		arm_neon_vmulls, // llvm.arm.neon.vmulls
	arm_neon_vmullu, // llvm.arm.neon.vmullu		arm_neon_vmullu, // llvm.arm.neon.vmullu
	arm_neon_vmulp, // llvm.arm.neon.vmulp		arm_neon_vmulp, // llvm.arm.neon.vmulp
	arm_neon_vpadals, // llvm.arm.neon.vpadals		arm_neon_vpadals, // llvm.arm.neon.vpadals
	arm_neon_vpadalu, // llvm.arm.neon.vpadalu		arm_neon_vpadalu, // llvm.arm.neon.vpadalu
	arm_neon_vpadd, // llvm.arm.neon.vpadd		arm_neon_vpadd, // llvm.arm.neon.vpadd
	arm_neon_vpaddls, // llvm.arm.neon.vpaddls		arm_neon_vpaddls, // llvm.arm.neon.vpaddls
	arm_neon_vpaddlu, // llvm.arm.neon.vpaddlu		arm_neon_vpaddlu, // llvm.arm.neon.vpaddlu
	arm_neon_vpmaxs, // llvm.arm.neon.vpmaxs		arm_neon_vpmaxs, // llvm.arm.neon.vpmaxs
	arm_neon_vpmaxu, // llvm.arm.neon.vpmaxu		arm_neon_vpmaxu, // llvm.arm.neon.vpmaxu
	arm_neon_vpmins, // llvm.arm.neon.vpmins		arm_neon_vpmins, // llvm.arm.neon.vpmins
	arm_neon_vpminu, // llvm.arm.neon.vpminu		arm_neon_vpminu, // llvm.arm.neon.vpminu
	arm_neon_vqabs, // llvm.arm.neon.vqabs		arm_neon_vqabs, // llvm.arm.neon.vqabs
	arm_neon_vqadds, // llvm.arm.neon.vqadds		arm_neon_vqadds, // llvm.arm.neon.vqadds
	arm_neon_vqaddu, // llvm.arm.neon.vqaddu		arm_neon_vqaddu, // llvm.arm.neon.vqaddu
	arm_neon_vqdmlal, // llvm.arm.neon.vqdmlal
	arm_neon_vqdmlsl, // llvm.arm.neon.vqdmlsl
	arm_neon_vqdmulh, // llvm.arm.neon.vqdmulh		arm_neon_vqdmulh, // llvm.arm.neon.vqdmulh
	arm_neon_vqdmull, // llvm.arm.neon.vqdmull		arm_neon_vqdmull, // llvm.arm.neon.vqdmull
	arm_neon_vqmovns, // llvm.arm.neon.vqmovns		arm_neon_vqmovns, // llvm.arm.neon.vqmovns
	arm_neon_vqmovnsu, // llvm.arm.neon.vqmovnsu		arm_neon_vqmovnsu, // llvm.arm.neon.vqmovnsu
	arm_neon_vqmovnu, // llvm.arm.neon.vqmovnu		arm_neon_vqmovnu, // llvm.arm.neon.vqmovnu
	arm_neon_vqneg, // llvm.arm.neon.vqneg		arm_neon_vqneg, // llvm.arm.neon.vqneg
	arm_neon_vqrdmulh, // llvm.arm.neon.vqrdmulh		arm_neon_vqrdmulh, // llvm.arm.neon.vqrdmulh
	arm_neon_vqrshiftns, // llvm.arm.neon.vqrshiftns		arm_neon_vqrshiftns, // llvm.arm.neon.vqrshiftns
	arm_neon_vqrshiftnsu, // llvm.arm.neon.vqrshiftnsu		arm_neon_vqrshiftnsu, // llvm.arm.neon.vqrshiftnsu
	arm_neon_vqrshiftnu, // llvm.arm.neon.vqrshiftnu		arm_neon_vqrshiftnu, // llvm.arm.neon.vqrshiftnu
	skipping to change at line 107		skipping to change at line 265
	arm_neon_vqshifts, // llvm.arm.neon.vqshifts		arm_neon_vqshifts, // llvm.arm.neon.vqshifts
	arm_neon_vqshiftsu, // llvm.arm.neon.vqshiftsu		arm_neon_vqshiftsu, // llvm.arm.neon.vqshiftsu
	arm_neon_vqshiftu, // llvm.arm.neon.vqshiftu		arm_neon_vqshiftu, // llvm.arm.neon.vqshiftu
	arm_neon_vqsubs, // llvm.arm.neon.vqsubs		arm_neon_vqsubs, // llvm.arm.neon.vqsubs
	arm_neon_vqsubu, // llvm.arm.neon.vqsubu		arm_neon_vqsubu, // llvm.arm.neon.vqsubu
	arm_neon_vraddhn, // llvm.arm.neon.vraddhn		arm_neon_vraddhn, // llvm.arm.neon.vraddhn
	arm_neon_vrecpe, // llvm.arm.neon.vrecpe		arm_neon_vrecpe, // llvm.arm.neon.vrecpe
	arm_neon_vrecps, // llvm.arm.neon.vrecps		arm_neon_vrecps, // llvm.arm.neon.vrecps
	arm_neon_vrhadds, // llvm.arm.neon.vrhadds		arm_neon_vrhadds, // llvm.arm.neon.vrhadds
	arm_neon_vrhaddu, // llvm.arm.neon.vrhaddu		arm_neon_vrhaddu, // llvm.arm.neon.vrhaddu
			arm_neon_vrinta, // llvm.arm.neon.vrinta
			arm_neon_vrintm, // llvm.arm.neon.vrintm
			arm_neon_vrintn, // llvm.arm.neon.vrintn
			arm_neon_vrintp, // llvm.arm.neon.vrintp
			arm_neon_vrintx, // llvm.arm.neon.vrintx
			arm_neon_vrintz, // llvm.arm.neon.vrintz
	arm_neon_vrshiftn, // llvm.arm.neon.vrshiftn		arm_neon_vrshiftn, // llvm.arm.neon.vrshiftn
	arm_neon_vrshifts, // llvm.arm.neon.vrshifts		arm_neon_vrshifts, // llvm.arm.neon.vrshifts
	arm_neon_vrshiftu, // llvm.arm.neon.vrshiftu		arm_neon_vrshiftu, // llvm.arm.neon.vrshiftu
	arm_neon_vrsqrte, // llvm.arm.neon.vrsqrte		arm_neon_vrsqrte, // llvm.arm.neon.vrsqrte
	arm_neon_vrsqrts, // llvm.arm.neon.vrsqrts		arm_neon_vrsqrts, // llvm.arm.neon.vrsqrts
	arm_neon_vrsubhn, // llvm.arm.neon.vrsubhn		arm_neon_vrsubhn, // llvm.arm.neon.vrsubhn
	arm_neon_vshiftins, // llvm.arm.neon.vshiftins		arm_neon_vshiftins, // llvm.arm.neon.vshiftins
	arm_neon_vshiftls, // llvm.arm.neon.vshiftls		arm_neon_vshiftls, // llvm.arm.neon.vshiftls
	arm_neon_vshiftlu, // llvm.arm.neon.vshiftlu		arm_neon_vshiftlu, // llvm.arm.neon.vshiftlu
	arm_neon_vshiftn, // llvm.arm.neon.vshiftn		arm_neon_vshiftn, // llvm.arm.neon.vshiftn
	arm_neon_vshifts, // llvm.arm.neon.vshifts		arm_neon_vshifts, // llvm.arm.neon.vshifts
	arm_neon_vshiftu, // llvm.arm.neon.vshiftu		arm_neon_vshiftu, // llvm.arm.neon.vshiftu
	arm_neon_vst1, // llvm.arm.neon.vst1		arm_neon_vst1, // llvm.arm.neon.vst1
	arm_neon_vst2, // llvm.arm.neon.vst2		arm_neon_vst2, // llvm.arm.neon.vst2
	arm_neon_vst2lane, // llvm.arm.neon.vst2lane		arm_neon_vst2lane, // llvm.arm.neon.vst2lane
	arm_neon_vst3, // llvm.arm.neon.vst3		arm_neon_vst3, // llvm.arm.neon.vst3
	arm_neon_vst3lane, // llvm.arm.neon.vst3lane		arm_neon_vst3lane, // llvm.arm.neon.vst3lane
	arm_neon_vst4, // llvm.arm.neon.vst4		arm_neon_vst4, // llvm.arm.neon.vst4
	arm_neon_vst4lane, // llvm.arm.neon.vst4lane		arm_neon_vst4lane, // llvm.arm.neon.vst4lane
	arm_neon_vsubhn, // llvm.arm.neon.vsubhn
	arm_neon_vtbl1, // llvm.arm.neon.vtbl1		arm_neon_vtbl1, // llvm.arm.neon.vtbl1
	arm_neon_vtbl2, // llvm.arm.neon.vtbl2		arm_neon_vtbl2, // llvm.arm.neon.vtbl2
	arm_neon_vtbl3, // llvm.arm.neon.vtbl3		arm_neon_vtbl3, // llvm.arm.neon.vtbl3
	arm_neon_vtbl4, // llvm.arm.neon.vtbl4		arm_neon_vtbl4, // llvm.arm.neon.vtbl4
	arm_neon_vtbx1, // llvm.arm.neon.vtbx1		arm_neon_vtbx1, // llvm.arm.neon.vtbx1
	arm_neon_vtbx2, // llvm.arm.neon.vtbx2		arm_neon_vtbx2, // llvm.arm.neon.vtbx2
	arm_neon_vtbx3, // llvm.arm.neon.vtbx3		arm_neon_vtbx3, // llvm.arm.neon.vtbx3
	arm_neon_vtbx4, // llvm.arm.neon.vtbx4		arm_neon_vtbx4, // llvm.arm.neon.vtbx4
	arm_qadd, // llvm.arm.qadd		arm_qadd, // llvm.arm.qadd
	arm_qsub, // llvm.arm.qsub		arm_qsub, // llvm.arm.qsub
	arm_set_fpscr, // llvm.arm.set.fpscr		arm_set_fpscr, // llvm.arm.set.fpscr
			arm_sevl, // llvm.arm.sevl
	arm_ssat, // llvm.arm.ssat		arm_ssat, // llvm.arm.ssat
			arm_strex, // llvm.arm.strex
	arm_strexd, // llvm.arm.strexd		arm_strexd, // llvm.arm.strexd
	arm_thread_pointer, // llvm.arm.thread.pointer		arm_thread_pointer, // llvm.arm.thread.pointer
	arm_usat, // llvm.arm.usat		arm_usat, // llvm.arm.usat
	arm_vcvtr, // llvm.arm.vcvtr		arm_vcvtr, // llvm.arm.vcvtr
	arm_vcvtru, // llvm.arm.vcvtru		arm_vcvtru, // llvm.arm.vcvtru
	bswap, // llvm.bswap		bswap, // llvm.bswap
	ceil, // llvm.ceil		ceil, // llvm.ceil
	convert_from_fp16, // llvm.convert.from.fp16		convert_from_fp16, // llvm.convert.from.fp16
	convert_to_fp16, // llvm.convert.to.fp16		convert_to_fp16, // llvm.convert.to.fp16
	convertff, // llvm.convertff		convertff, // llvm.convertff
	convertfsi, // llvm.convertfsi		convertfsi, // llvm.convertfsi
	convertfui, // llvm.convertfui		convertfui, // llvm.convertfui
	convertsif, // llvm.convertsif		convertsif, // llvm.convertsif
	convertss, // llvm.convertss		convertss, // llvm.convertss
	convertsu, // llvm.convertsu		convertsu, // llvm.convertsu
	convertuif, // llvm.convertuif		convertuif, // llvm.convertuif
	convertus, // llvm.convertus		convertus, // llvm.convertus
	convertuu, // llvm.convertuu		convertuu, // llvm.convertuu
			copysign, // llvm.copysign
	cos, // llvm.cos		cos, // llvm.cos
	ctlz, // llvm.ctlz		ctlz, // llvm.ctlz
	ctpop, // llvm.ctpop		ctpop, // llvm.ctpop
	cttz, // llvm.cttz		cttz, // llvm.cttz
	cuda_syncthreads, // llvm.cuda.syncthreads		cuda_syncthreads, // llvm.cuda.syncthreads
	dbg_declare, // llvm.dbg.declare		dbg_declare, // llvm.dbg.declare
	dbg_value, // llvm.dbg.value		dbg_value, // llvm.dbg.value
	debugtrap, // llvm.debugtrap		debugtrap, // llvm.debugtrap
	donothing, // llvm.donothing		donothing, // llvm.donothing
	eh_dwarf_cfa, // llvm.eh.dwarf.cfa		eh_dwarf_cfa, // llvm.eh.dwarf.cfa
	skipping to change at line 179		skipping to change at line 345
	eh_sjlj_callsite, // llvm.eh.sjlj.callsite		eh_sjlj_callsite, // llvm.eh.sjlj.callsite
	eh_sjlj_functioncontext, // llvm.eh.sjlj.functionconte xt		eh_sjlj_functioncontext, // llvm.eh.sjlj.functionconte xt
	eh_sjlj_longjmp, // llvm.eh.sjlj.longjmp		eh_sjlj_longjmp, // llvm.eh.sjlj.longjmp
	eh_sjlj_lsda, // llvm.eh.sjlj.lsda		eh_sjlj_lsda, // llvm.eh.sjlj.lsda
	eh_sjlj_setjmp, // llvm.eh.sjlj.setjmp		eh_sjlj_setjmp, // llvm.eh.sjlj.setjmp
	eh_typeid_for, // llvm.eh.typeid.for		eh_typeid_for, // llvm.eh.typeid.for
	eh_unwind_init, // llvm.eh.unwind.init		eh_unwind_init, // llvm.eh.unwind.init
	exp, // llvm.exp		exp, // llvm.exp
	exp2, // llvm.exp2		exp2, // llvm.exp2
	expect, // llvm.expect		expect, // llvm.expect
			experimental_patchpoint_i64, // llvm.experimental.patchpoi
			nt.i64
			experimental_patchpoint_void, // llvm.experimental.patchpoi
			nt.void
			experimental_stackmap, // llvm.experimental.stackmap
	fabs, // llvm.fabs		fabs, // llvm.fabs
	floor, // llvm.floor		floor, // llvm.floor
	flt_rounds, // llvm.flt.rounds		flt_rounds, // llvm.flt.rounds
	fma, // llvm.fma		fma, // llvm.fma
	fmuladd, // llvm.fmuladd		fmuladd, // llvm.fmuladd
	frameaddress, // llvm.frameaddress		frameaddress, // llvm.frameaddress
	gcread, // llvm.gcread		gcread, // llvm.gcread
	gcroot, // llvm.gcroot		gcroot, // llvm.gcroot
	gcwrite, // llvm.gcwrite		gcwrite, // llvm.gcwrite
	hexagon_A2_abs, // llvm.hexagon.A2.abs		hexagon_A2_abs, // llvm.hexagon.A2.abs
	skipping to change at line 1056		skipping to change at line 1225
	log, // llvm.log		log, // llvm.log
	log10, // llvm.log10		log10, // llvm.log10
	log2, // llvm.log2		log2, // llvm.log2
	longjmp, // llvm.longjmp		longjmp, // llvm.longjmp
	memcpy, // llvm.memcpy		memcpy, // llvm.memcpy
	memmove, // llvm.memmove		memmove, // llvm.memmove
	memset, // llvm.memset		memset, // llvm.memset
	mips_absq_s_ph, // llvm.mips.absq.s.ph		mips_absq_s_ph, // llvm.mips.absq.s.ph
	mips_absq_s_qb, // llvm.mips.absq.s.qb		mips_absq_s_qb, // llvm.mips.absq.s.qb
	mips_absq_s_w, // llvm.mips.absq.s.w		mips_absq_s_w, // llvm.mips.absq.s.w
			mips_add_a_b, // llvm.mips.add.a.b
			mips_add_a_d, // llvm.mips.add.a.d
			mips_add_a_h, // llvm.mips.add.a.h
			mips_add_a_w, // llvm.mips.add.a.w
	mips_addq_ph, // llvm.mips.addq.ph		mips_addq_ph, // llvm.mips.addq.ph
	mips_addq_s_ph, // llvm.mips.addq.s.ph		mips_addq_s_ph, // llvm.mips.addq.s.ph
	mips_addq_s_w, // llvm.mips.addq.s.w		mips_addq_s_w, // llvm.mips.addq.s.w
	mips_addqh_ph, // llvm.mips.addqh.ph		mips_addqh_ph, // llvm.mips.addqh.ph
	mips_addqh_r_ph, // llvm.mips.addqh.r.ph		mips_addqh_r_ph, // llvm.mips.addqh.r.ph
	mips_addqh_r_w, // llvm.mips.addqh.r.w		mips_addqh_r_w, // llvm.mips.addqh.r.w
	mips_addqh_w, // llvm.mips.addqh.w		mips_addqh_w, // llvm.mips.addqh.w
			mips_adds_a_b, // llvm.mips.adds.a.b
			mips_adds_a_d, // llvm.mips.adds.a.d
			mips_adds_a_h, // llvm.mips.adds.a.h
			mips_adds_a_w, // llvm.mips.adds.a.w
			mips_adds_s_b, // llvm.mips.adds.s.b
			mips_adds_s_d, // llvm.mips.adds.s.d
			mips_adds_s_h, // llvm.mips.adds.s.h
			mips_adds_s_w, // llvm.mips.adds.s.w
			mips_adds_u_b, // llvm.mips.adds.u.b
			mips_adds_u_d, // llvm.mips.adds.u.d
			mips_adds_u_h, // llvm.mips.adds.u.h
			mips_adds_u_w, // llvm.mips.adds.u.w
	mips_addsc, // llvm.mips.addsc		mips_addsc, // llvm.mips.addsc
	mips_addu_ph, // llvm.mips.addu.ph		mips_addu_ph, // llvm.mips.addu.ph
	mips_addu_qb, // llvm.mips.addu.qb		mips_addu_qb, // llvm.mips.addu.qb
	mips_addu_s_ph, // llvm.mips.addu.s.ph		mips_addu_s_ph, // llvm.mips.addu.s.ph
	mips_addu_s_qb, // llvm.mips.addu.s.qb		mips_addu_s_qb, // llvm.mips.addu.s.qb
	mips_adduh_qb, // llvm.mips.adduh.qb		mips_adduh_qb, // llvm.mips.adduh.qb
	mips_adduh_r_qb, // llvm.mips.adduh.r.qb		mips_adduh_r_qb, // llvm.mips.adduh.r.qb
			mips_addv_b, // llvm.mips.addv.b
			mips_addv_d, // llvm.mips.addv.d
			mips_addv_h, // llvm.mips.addv.h
			mips_addv_w, // llvm.mips.addv.w
			mips_addvi_b, // llvm.mips.addvi.b
			mips_addvi_d, // llvm.mips.addvi.d
			mips_addvi_h, // llvm.mips.addvi.h
			mips_addvi_w, // llvm.mips.addvi.w
	mips_addwc, // llvm.mips.addwc		mips_addwc, // llvm.mips.addwc
			mips_and_v, // llvm.mips.and.v
			mips_andi_b, // llvm.mips.andi.b
	mips_append, // llvm.mips.append		mips_append, // llvm.mips.append
			mips_asub_s_b, // llvm.mips.asub.s.b
			mips_asub_s_d, // llvm.mips.asub.s.d
			mips_asub_s_h, // llvm.mips.asub.s.h
			mips_asub_s_w, // llvm.mips.asub.s.w
			mips_asub_u_b, // llvm.mips.asub.u.b
			mips_asub_u_d, // llvm.mips.asub.u.d
			mips_asub_u_h, // llvm.mips.asub.u.h
			mips_asub_u_w, // llvm.mips.asub.u.w
			mips_ave_s_b, // llvm.mips.ave.s.b
			mips_ave_s_d, // llvm.mips.ave.s.d
			mips_ave_s_h, // llvm.mips.ave.s.h
			mips_ave_s_w, // llvm.mips.ave.s.w
			mips_ave_u_b, // llvm.mips.ave.u.b
			mips_ave_u_d, // llvm.mips.ave.u.d
			mips_ave_u_h, // llvm.mips.ave.u.h
			mips_ave_u_w, // llvm.mips.ave.u.w
			mips_aver_s_b, // llvm.mips.aver.s.b
			mips_aver_s_d, // llvm.mips.aver.s.d
			mips_aver_s_h, // llvm.mips.aver.s.h
			mips_aver_s_w, // llvm.mips.aver.s.w
			mips_aver_u_b, // llvm.mips.aver.u.b
			mips_aver_u_d, // llvm.mips.aver.u.d
			mips_aver_u_h, // llvm.mips.aver.u.h
			mips_aver_u_w, // llvm.mips.aver.u.w
	mips_balign, // llvm.mips.balign		mips_balign, // llvm.mips.balign
			mips_bclr_b, // llvm.mips.bclr.b
			mips_bclr_d, // llvm.mips.bclr.d
			mips_bclr_h, // llvm.mips.bclr.h
			mips_bclr_w, // llvm.mips.bclr.w
			mips_bclri_b, // llvm.mips.bclri.b
			mips_bclri_d, // llvm.mips.bclri.d
			mips_bclri_h, // llvm.mips.bclri.h
			mips_bclri_w, // llvm.mips.bclri.w
			mips_binsl_b, // llvm.mips.binsl.b
			mips_binsl_d, // llvm.mips.binsl.d
			mips_binsl_h, // llvm.mips.binsl.h
			mips_binsl_w, // llvm.mips.binsl.w
			mips_binsli_b, // llvm.mips.binsli.b
			mips_binsli_d, // llvm.mips.binsli.d
			mips_binsli_h, // llvm.mips.binsli.h
			mips_binsli_w, // llvm.mips.binsli.w
			mips_binsr_b, // llvm.mips.binsr.b
			mips_binsr_d, // llvm.mips.binsr.d
			mips_binsr_h, // llvm.mips.binsr.h
			mips_binsr_w, // llvm.mips.binsr.w
			mips_binsri_b, // llvm.mips.binsri.b
			mips_binsri_d, // llvm.mips.binsri.d
			mips_binsri_h, // llvm.mips.binsri.h
			mips_binsri_w, // llvm.mips.binsri.w
	mips_bitrev, // llvm.mips.bitrev		mips_bitrev, // llvm.mips.bitrev
			mips_bmnz_v, // llvm.mips.bmnz.v
			mips_bmnzi_b, // llvm.mips.bmnzi.b
			mips_bmz_v, // llvm.mips.bmz.v
			mips_bmzi_b, // llvm.mips.bmzi.b
			mips_bneg_b, // llvm.mips.bneg.b
			mips_bneg_d, // llvm.mips.bneg.d
			mips_bneg_h, // llvm.mips.bneg.h
			mips_bneg_w, // llvm.mips.bneg.w
			mips_bnegi_b, // llvm.mips.bnegi.b
			mips_bnegi_d, // llvm.mips.bnegi.d
			mips_bnegi_h, // llvm.mips.bnegi.h
			mips_bnegi_w, // llvm.mips.bnegi.w
			mips_bnz_b, // llvm.mips.bnz.b
			mips_bnz_d, // llvm.mips.bnz.d
			mips_bnz_h, // llvm.mips.bnz.h
			mips_bnz_v, // llvm.mips.bnz.v
			mips_bnz_w, // llvm.mips.bnz.w
	mips_bposge32, // llvm.mips.bposge32		mips_bposge32, // llvm.mips.bposge32
			mips_bsel_v, // llvm.mips.bsel.v
			mips_bseli_b, // llvm.mips.bseli.b
			mips_bset_b, // llvm.mips.bset.b
			mips_bset_d, // llvm.mips.bset.d
			mips_bset_h, // llvm.mips.bset.h
			mips_bset_w, // llvm.mips.bset.w
			mips_bseti_b, // llvm.mips.bseti.b
			mips_bseti_d, // llvm.mips.bseti.d
			mips_bseti_h, // llvm.mips.bseti.h
			mips_bseti_w, // llvm.mips.bseti.w
			mips_bz_b, // llvm.mips.bz.b
			mips_bz_d, // llvm.mips.bz.d
			mips_bz_h, // llvm.mips.bz.h
			mips_bz_v, // llvm.mips.bz.v
			mips_bz_w, // llvm.mips.bz.w
			mips_ceq_b, // llvm.mips.ceq.b
			mips_ceq_d, // llvm.mips.ceq.d
			mips_ceq_h, // llvm.mips.ceq.h
			mips_ceq_w, // llvm.mips.ceq.w
			mips_ceqi_b, // llvm.mips.ceqi.b
			mips_ceqi_d, // llvm.mips.ceqi.d
			mips_ceqi_h, // llvm.mips.ceqi.h
			mips_ceqi_w, // llvm.mips.ceqi.w
			mips_cfcmsa, // llvm.mips.cfcmsa
			mips_cle_s_b, // llvm.mips.cle.s.b
			mips_cle_s_d, // llvm.mips.cle.s.d
			mips_cle_s_h, // llvm.mips.cle.s.h
			mips_cle_s_w, // llvm.mips.cle.s.w
			mips_cle_u_b, // llvm.mips.cle.u.b
			mips_cle_u_d, // llvm.mips.cle.u.d
			mips_cle_u_h, // llvm.mips.cle.u.h
			mips_cle_u_w, // llvm.mips.cle.u.w
			mips_clei_s_b, // llvm.mips.clei.s.b
			mips_clei_s_d, // llvm.mips.clei.s.d
			mips_clei_s_h, // llvm.mips.clei.s.h
			mips_clei_s_w, // llvm.mips.clei.s.w
			mips_clei_u_b, // llvm.mips.clei.u.b
			mips_clei_u_d, // llvm.mips.clei.u.d
			mips_clei_u_h, // llvm.mips.clei.u.h
			mips_clei_u_w, // llvm.mips.clei.u.w
			mips_clt_s_b, // llvm.mips.clt.s.b
			mips_clt_s_d, // llvm.mips.clt.s.d
			mips_clt_s_h, // llvm.mips.clt.s.h
			mips_clt_s_w, // llvm.mips.clt.s.w
			mips_clt_u_b, // llvm.mips.clt.u.b
			mips_clt_u_d, // llvm.mips.clt.u.d
			mips_clt_u_h, // llvm.mips.clt.u.h
			mips_clt_u_w, // llvm.mips.clt.u.w
			mips_clti_s_b, // llvm.mips.clti.s.b
			mips_clti_s_d, // llvm.mips.clti.s.d
			mips_clti_s_h, // llvm.mips.clti.s.h
			mips_clti_s_w, // llvm.mips.clti.s.w
			mips_clti_u_b, // llvm.mips.clti.u.b
			mips_clti_u_d, // llvm.mips.clti.u.d
			mips_clti_u_h, // llvm.mips.clti.u.h
			mips_clti_u_w, // llvm.mips.clti.u.w
	mips_cmp_eq_ph, // llvm.mips.cmp.eq.ph		mips_cmp_eq_ph, // llvm.mips.cmp.eq.ph
	mips_cmp_le_ph, // llvm.mips.cmp.le.ph		mips_cmp_le_ph, // llvm.mips.cmp.le.ph
	mips_cmp_lt_ph, // llvm.mips.cmp.lt.ph		mips_cmp_lt_ph, // llvm.mips.cmp.lt.ph
	mips_cmpgdu_eq_qb, // llvm.mips.cmpgdu.eq.qb		mips_cmpgdu_eq_qb, // llvm.mips.cmpgdu.eq.qb
	mips_cmpgdu_le_qb, // llvm.mips.cmpgdu.le.qb		mips_cmpgdu_le_qb, // llvm.mips.cmpgdu.le.qb
	mips_cmpgdu_lt_qb, // llvm.mips.cmpgdu.lt.qb		mips_cmpgdu_lt_qb, // llvm.mips.cmpgdu.lt.qb
	mips_cmpgu_eq_qb, // llvm.mips.cmpgu.eq.qb		mips_cmpgu_eq_qb, // llvm.mips.cmpgu.eq.qb
	mips_cmpgu_le_qb, // llvm.mips.cmpgu.le.qb		mips_cmpgu_le_qb, // llvm.mips.cmpgu.le.qb
	mips_cmpgu_lt_qb, // llvm.mips.cmpgu.lt.qb		mips_cmpgu_lt_qb, // llvm.mips.cmpgu.lt.qb
	mips_cmpu_eq_qb, // llvm.mips.cmpu.eq.qb		mips_cmpu_eq_qb, // llvm.mips.cmpu.eq.qb
	mips_cmpu_le_qb, // llvm.mips.cmpu.le.qb		mips_cmpu_le_qb, // llvm.mips.cmpu.le.qb
	mips_cmpu_lt_qb, // llvm.mips.cmpu.lt.qb		mips_cmpu_lt_qb, // llvm.mips.cmpu.lt.qb
			mips_copy_s_b, // llvm.mips.copy.s.b
			mips_copy_s_d, // llvm.mips.copy.s.d
			mips_copy_s_h, // llvm.mips.copy.s.h
			mips_copy_s_w, // llvm.mips.copy.s.w
			mips_copy_u_b, // llvm.mips.copy.u.b
			mips_copy_u_d, // llvm.mips.copy.u.d
			mips_copy_u_h, // llvm.mips.copy.u.h
			mips_copy_u_w, // llvm.mips.copy.u.w
			mips_ctcmsa, // llvm.mips.ctcmsa
			mips_div_s_b, // llvm.mips.div.s.b
			mips_div_s_d, // llvm.mips.div.s.d
			mips_div_s_h, // llvm.mips.div.s.h
			mips_div_s_w, // llvm.mips.div.s.w
			mips_div_u_b, // llvm.mips.div.u.b
			mips_div_u_d, // llvm.mips.div.u.d
			mips_div_u_h, // llvm.mips.div.u.h
			mips_div_u_w, // llvm.mips.div.u.w
			mips_dotp_s_d, // llvm.mips.dotp.s.d
			mips_dotp_s_h, // llvm.mips.dotp.s.h
			mips_dotp_s_w, // llvm.mips.dotp.s.w
			mips_dotp_u_d, // llvm.mips.dotp.u.d
			mips_dotp_u_h, // llvm.mips.dotp.u.h
			mips_dotp_u_w, // llvm.mips.dotp.u.w
	mips_dpa_w_ph, // llvm.mips.dpa.w.ph		mips_dpa_w_ph, // llvm.mips.dpa.w.ph
			mips_dpadd_s_d, // llvm.mips.dpadd.s.d
			mips_dpadd_s_h, // llvm.mips.dpadd.s.h
			mips_dpadd_s_w, // llvm.mips.dpadd.s.w
			mips_dpadd_u_d, // llvm.mips.dpadd.u.d
			mips_dpadd_u_h, // llvm.mips.dpadd.u.h
			mips_dpadd_u_w, // llvm.mips.dpadd.u.w
	mips_dpaq_s_w_ph, // llvm.mips.dpaq.s.w.ph		mips_dpaq_s_w_ph, // llvm.mips.dpaq.s.w.ph
	mips_dpaq_sa_l_w, // llvm.mips.dpaq.sa.l.w		mips_dpaq_sa_l_w, // llvm.mips.dpaq.sa.l.w
	mips_dpaqx_s_w_ph, // llvm.mips.dpaqx.s.w.ph		mips_dpaqx_s_w_ph, // llvm.mips.dpaqx.s.w.ph
	mips_dpaqx_sa_w_ph, // llvm.mips.dpaqx.sa.w.ph		mips_dpaqx_sa_w_ph, // llvm.mips.dpaqx.sa.w.ph
	mips_dpau_h_qbl, // llvm.mips.dpau.h.qbl		mips_dpau_h_qbl, // llvm.mips.dpau.h.qbl
	mips_dpau_h_qbr, // llvm.mips.dpau.h.qbr		mips_dpau_h_qbr, // llvm.mips.dpau.h.qbr
	mips_dpax_w_ph, // llvm.mips.dpax.w.ph		mips_dpax_w_ph, // llvm.mips.dpax.w.ph
	mips_dps_w_ph, // llvm.mips.dps.w.ph		mips_dps_w_ph, // llvm.mips.dps.w.ph
	mips_dpsq_s_w_ph, // llvm.mips.dpsq.s.w.ph		mips_dpsq_s_w_ph, // llvm.mips.dpsq.s.w.ph
	mips_dpsq_sa_l_w, // llvm.mips.dpsq.sa.l.w		mips_dpsq_sa_l_w, // llvm.mips.dpsq.sa.l.w
	mips_dpsqx_s_w_ph, // llvm.mips.dpsqx.s.w.ph		mips_dpsqx_s_w_ph, // llvm.mips.dpsqx.s.w.ph
	mips_dpsqx_sa_w_ph, // llvm.mips.dpsqx.sa.w.ph		mips_dpsqx_sa_w_ph, // llvm.mips.dpsqx.sa.w.ph
	mips_dpsu_h_qbl, // llvm.mips.dpsu.h.qbl		mips_dpsu_h_qbl, // llvm.mips.dpsu.h.qbl
	mips_dpsu_h_qbr, // llvm.mips.dpsu.h.qbr		mips_dpsu_h_qbr, // llvm.mips.dpsu.h.qbr
			mips_dpsub_s_d, // llvm.mips.dpsub.s.d
			mips_dpsub_s_h, // llvm.mips.dpsub.s.h
			mips_dpsub_s_w, // llvm.mips.dpsub.s.w
			mips_dpsub_u_d, // llvm.mips.dpsub.u.d
			mips_dpsub_u_h, // llvm.mips.dpsub.u.h
			mips_dpsub_u_w, // llvm.mips.dpsub.u.w
	mips_dpsx_w_ph, // llvm.mips.dpsx.w.ph		mips_dpsx_w_ph, // llvm.mips.dpsx.w.ph
	mips_extp, // llvm.mips.extp		mips_extp, // llvm.mips.extp
	mips_extpdp, // llvm.mips.extpdp		mips_extpdp, // llvm.mips.extpdp
	mips_extr_r_w, // llvm.mips.extr.r.w		mips_extr_r_w, // llvm.mips.extr.r.w
	mips_extr_rs_w, // llvm.mips.extr.rs.w		mips_extr_rs_w, // llvm.mips.extr.rs.w
	mips_extr_s_h, // llvm.mips.extr.s.h		mips_extr_s_h, // llvm.mips.extr.s.h
	mips_extr_w, // llvm.mips.extr.w		mips_extr_w, // llvm.mips.extr.w
			mips_fadd_d, // llvm.mips.fadd.d
			mips_fadd_w, // llvm.mips.fadd.w
			mips_fcaf_d, // llvm.mips.fcaf.d
			mips_fcaf_w, // llvm.mips.fcaf.w
			mips_fceq_d, // llvm.mips.fceq.d
			mips_fceq_w, // llvm.mips.fceq.w
			mips_fclass_d, // llvm.mips.fclass.d
			mips_fclass_w, // llvm.mips.fclass.w
			mips_fcle_d, // llvm.mips.fcle.d
			mips_fcle_w, // llvm.mips.fcle.w
			mips_fclt_d, // llvm.mips.fclt.d
			mips_fclt_w, // llvm.mips.fclt.w
			mips_fcne_d, // llvm.mips.fcne.d
			mips_fcne_w, // llvm.mips.fcne.w
			mips_fcor_d, // llvm.mips.fcor.d
			mips_fcor_w, // llvm.mips.fcor.w
			mips_fcueq_d, // llvm.mips.fcueq.d
			mips_fcueq_w, // llvm.mips.fcueq.w
			mips_fcule_d, // llvm.mips.fcule.d
			mips_fcule_w, // llvm.mips.fcule.w
			mips_fcult_d, // llvm.mips.fcult.d
			mips_fcult_w, // llvm.mips.fcult.w
			mips_fcun_d, // llvm.mips.fcun.d
			mips_fcun_w, // llvm.mips.fcun.w
			mips_fcune_d, // llvm.mips.fcune.d
			mips_fcune_w, // llvm.mips.fcune.w
			mips_fdiv_d, // llvm.mips.fdiv.d
			mips_fdiv_w, // llvm.mips.fdiv.w
			mips_fexdo_h, // llvm.mips.fexdo.h
			mips_fexdo_w, // llvm.mips.fexdo.w
			mips_fexp2_d, // llvm.mips.fexp2.d
			mips_fexp2_w, // llvm.mips.fexp2.w
			mips_fexupl_d, // llvm.mips.fexupl.d
			mips_fexupl_w, // llvm.mips.fexupl.w
			mips_fexupr_d, // llvm.mips.fexupr.d
			mips_fexupr_w, // llvm.mips.fexupr.w
			mips_ffint_s_d, // llvm.mips.ffint.s.d
			mips_ffint_s_w, // llvm.mips.ffint.s.w
			mips_ffint_u_d, // llvm.mips.ffint.u.d
			mips_ffint_u_w, // llvm.mips.ffint.u.w
			mips_ffql_d, // llvm.mips.ffql.d
			mips_ffql_w, // llvm.mips.ffql.w
			mips_ffqr_d, // llvm.mips.ffqr.d
			mips_ffqr_w, // llvm.mips.ffqr.w
			mips_fill_b, // llvm.mips.fill.b
			mips_fill_d, // llvm.mips.fill.d
			mips_fill_h, // llvm.mips.fill.h
			mips_fill_w, // llvm.mips.fill.w
			mips_flog2_d, // llvm.mips.flog2.d
			mips_flog2_w, // llvm.mips.flog2.w
			mips_fmadd_d, // llvm.mips.fmadd.d
			mips_fmadd_w, // llvm.mips.fmadd.w
			mips_fmax_a_d, // llvm.mips.fmax.a.d
			mips_fmax_a_w, // llvm.mips.fmax.a.w
			mips_fmax_d, // llvm.mips.fmax.d
			mips_fmax_w, // llvm.mips.fmax.w
			mips_fmin_a_d, // llvm.mips.fmin.a.d
			mips_fmin_a_w, // llvm.mips.fmin.a.w
			mips_fmin_d, // llvm.mips.fmin.d
			mips_fmin_w, // llvm.mips.fmin.w
			mips_fmsub_d, // llvm.mips.fmsub.d
			mips_fmsub_w, // llvm.mips.fmsub.w
			mips_fmul_d, // llvm.mips.fmul.d
			mips_fmul_w, // llvm.mips.fmul.w
			mips_frcp_d, // llvm.mips.frcp.d
			mips_frcp_w, // llvm.mips.frcp.w
			mips_frint_d, // llvm.mips.frint.d
			mips_frint_w, // llvm.mips.frint.w
			mips_frsqrt_d, // llvm.mips.frsqrt.d
			mips_frsqrt_w, // llvm.mips.frsqrt.w
			mips_fsaf_d, // llvm.mips.fsaf.d
			mips_fsaf_w, // llvm.mips.fsaf.w
			mips_fseq_d, // llvm.mips.fseq.d
			mips_fseq_w, // llvm.mips.fseq.w
			mips_fsle_d, // llvm.mips.fsle.d
			mips_fsle_w, // llvm.mips.fsle.w
			mips_fslt_d, // llvm.mips.fslt.d
			mips_fslt_w, // llvm.mips.fslt.w
			mips_fsne_d, // llvm.mips.fsne.d
			mips_fsne_w, // llvm.mips.fsne.w
			mips_fsor_d, // llvm.mips.fsor.d
			mips_fsor_w, // llvm.mips.fsor.w
			mips_fsqrt_d, // llvm.mips.fsqrt.d
			mips_fsqrt_w, // llvm.mips.fsqrt.w
			mips_fsub_d, // llvm.mips.fsub.d
			mips_fsub_w, // llvm.mips.fsub.w
			mips_fsueq_d, // llvm.mips.fsueq.d
			mips_fsueq_w, // llvm.mips.fsueq.w
			mips_fsule_d, // llvm.mips.fsule.d
			mips_fsule_w, // llvm.mips.fsule.w
			mips_fsult_d, // llvm.mips.fsult.d
			mips_fsult_w, // llvm.mips.fsult.w
			mips_fsun_d, // llvm.mips.fsun.d
			mips_fsun_w, // llvm.mips.fsun.w
			mips_fsune_d, // llvm.mips.fsune.d
			mips_fsune_w, // llvm.mips.fsune.w
			mips_ftint_s_d, // llvm.mips.ftint.s.d
			mips_ftint_s_w, // llvm.mips.ftint.s.w
			mips_ftint_u_d, // llvm.mips.ftint.u.d
			mips_ftint_u_w, // llvm.mips.ftint.u.w
			mips_ftq_h, // llvm.mips.ftq.h
			mips_ftq_w, // llvm.mips.ftq.w
			mips_ftrunc_s_d, // llvm.mips.ftrunc.s.d
			mips_ftrunc_s_w, // llvm.mips.ftrunc.s.w
			mips_ftrunc_u_d, // llvm.mips.ftrunc.u.d
			mips_ftrunc_u_w, // llvm.mips.ftrunc.u.w
			mips_hadd_s_d, // llvm.mips.hadd.s.d
			mips_hadd_s_h, // llvm.mips.hadd.s.h
			mips_hadd_s_w, // llvm.mips.hadd.s.w
			mips_hadd_u_d, // llvm.mips.hadd.u.d
			mips_hadd_u_h, // llvm.mips.hadd.u.h
			mips_hadd_u_w, // llvm.mips.hadd.u.w
			mips_hsub_s_d, // llvm.mips.hsub.s.d
			mips_hsub_s_h, // llvm.mips.hsub.s.h
			mips_hsub_s_w, // llvm.mips.hsub.s.w
			mips_hsub_u_d, // llvm.mips.hsub.u.d
			mips_hsub_u_h, // llvm.mips.hsub.u.h
			mips_hsub_u_w, // llvm.mips.hsub.u.w
			mips_ilvev_b, // llvm.mips.ilvev.b
			mips_ilvev_d, // llvm.mips.ilvev.d
			mips_ilvev_h, // llvm.mips.ilvev.h
			mips_ilvev_w, // llvm.mips.ilvev.w
			mips_ilvl_b, // llvm.mips.ilvl.b
			mips_ilvl_d, // llvm.mips.ilvl.d
			mips_ilvl_h, // llvm.mips.ilvl.h
			mips_ilvl_w, // llvm.mips.ilvl.w
			mips_ilvod_b, // llvm.mips.ilvod.b
			mips_ilvod_d, // llvm.mips.ilvod.d
			mips_ilvod_h, // llvm.mips.ilvod.h
			mips_ilvod_w, // llvm.mips.ilvod.w
			mips_ilvr_b, // llvm.mips.ilvr.b
			mips_ilvr_d, // llvm.mips.ilvr.d
			mips_ilvr_h, // llvm.mips.ilvr.h
			mips_ilvr_w, // llvm.mips.ilvr.w
			mips_insert_b, // llvm.mips.insert.b
			mips_insert_d, // llvm.mips.insert.d
			mips_insert_h, // llvm.mips.insert.h
			mips_insert_w, // llvm.mips.insert.w
	mips_insv, // llvm.mips.insv		mips_insv, // llvm.mips.insv
			mips_insve_b, // llvm.mips.insve.b
			mips_insve_d, // llvm.mips.insve.d
			mips_insve_h, // llvm.mips.insve.h
			mips_insve_w, // llvm.mips.insve.w
	mips_lbux, // llvm.mips.lbux		mips_lbux, // llvm.mips.lbux
			mips_ld_b, // llvm.mips.ld.b
			mips_ld_d, // llvm.mips.ld.d
			mips_ld_h, // llvm.mips.ld.h
			mips_ld_w, // llvm.mips.ld.w
			mips_ldi_b, // llvm.mips.ldi.b
			mips_ldi_d, // llvm.mips.ldi.d
			mips_ldi_h, // llvm.mips.ldi.h
			mips_ldi_w, // llvm.mips.ldi.w
	mips_lhx, // llvm.mips.lhx		mips_lhx, // llvm.mips.lhx
			mips_lsa, // llvm.mips.lsa
	mips_lwx, // llvm.mips.lwx		mips_lwx, // llvm.mips.lwx
	mips_madd, // llvm.mips.madd		mips_madd, // llvm.mips.madd
			mips_madd_q_h, // llvm.mips.madd.q.h
			mips_madd_q_w, // llvm.mips.madd.q.w
			mips_maddr_q_h, // llvm.mips.maddr.q.h
			mips_maddr_q_w, // llvm.mips.maddr.q.w
	mips_maddu, // llvm.mips.maddu		mips_maddu, // llvm.mips.maddu
			mips_maddv_b, // llvm.mips.maddv.b
			mips_maddv_d, // llvm.mips.maddv.d
			mips_maddv_h, // llvm.mips.maddv.h
			mips_maddv_w, // llvm.mips.maddv.w
	mips_maq_s_w_phl, // llvm.mips.maq.s.w.phl		mips_maq_s_w_phl, // llvm.mips.maq.s.w.phl
	mips_maq_s_w_phr, // llvm.mips.maq.s.w.phr		mips_maq_s_w_phr, // llvm.mips.maq.s.w.phr
	mips_maq_sa_w_phl, // llvm.mips.maq.sa.w.phl		mips_maq_sa_w_phl, // llvm.mips.maq.sa.w.phl
	mips_maq_sa_w_phr, // llvm.mips.maq.sa.w.phr		mips_maq_sa_w_phr, // llvm.mips.maq.sa.w.phr
			mips_max_a_b, // llvm.mips.max.a.b
			mips_max_a_d, // llvm.mips.max.a.d
			mips_max_a_h, // llvm.mips.max.a.h
			mips_max_a_w, // llvm.mips.max.a.w
			mips_max_s_b, // llvm.mips.max.s.b
			mips_max_s_d, // llvm.mips.max.s.d
			mips_max_s_h, // llvm.mips.max.s.h
			mips_max_s_w, // llvm.mips.max.s.w
			mips_max_u_b, // llvm.mips.max.u.b
			mips_max_u_d, // llvm.mips.max.u.d
			mips_max_u_h, // llvm.mips.max.u.h
			mips_max_u_w, // llvm.mips.max.u.w
			mips_maxi_s_b, // llvm.mips.maxi.s.b
			mips_maxi_s_d, // llvm.mips.maxi.s.d
			mips_maxi_s_h, // llvm.mips.maxi.s.h
			mips_maxi_s_w, // llvm.mips.maxi.s.w
			mips_maxi_u_b, // llvm.mips.maxi.u.b
			mips_maxi_u_d, // llvm.mips.maxi.u.d
			mips_maxi_u_h, // llvm.mips.maxi.u.h
			mips_maxi_u_w, // llvm.mips.maxi.u.w
			mips_min_a_b, // llvm.mips.min.a.b
			mips_min_a_d, // llvm.mips.min.a.d
			mips_min_a_h, // llvm.mips.min.a.h
			mips_min_a_w, // llvm.mips.min.a.w
			mips_min_s_b, // llvm.mips.min.s.b
			mips_min_s_d, // llvm.mips.min.s.d
			mips_min_s_h, // llvm.mips.min.s.h
			mips_min_s_w, // llvm.mips.min.s.w
			mips_min_u_b, // llvm.mips.min.u.b
			mips_min_u_d, // llvm.mips.min.u.d
			mips_min_u_h, // llvm.mips.min.u.h
			mips_min_u_w, // llvm.mips.min.u.w
			mips_mini_s_b, // llvm.mips.mini.s.b
			mips_mini_s_d, // llvm.mips.mini.s.d
			mips_mini_s_h, // llvm.mips.mini.s.h
			mips_mini_s_w, // llvm.mips.mini.s.w
			mips_mini_u_b, // llvm.mips.mini.u.b
			mips_mini_u_d, // llvm.mips.mini.u.d
			mips_mini_u_h, // llvm.mips.mini.u.h
			mips_mini_u_w, // llvm.mips.mini.u.w
			mips_mod_s_b, // llvm.mips.mod.s.b
			mips_mod_s_d, // llvm.mips.mod.s.d
			mips_mod_s_h, // llvm.mips.mod.s.h
			mips_mod_s_w, // llvm.mips.mod.s.w
			mips_mod_u_b, // llvm.mips.mod.u.b
			mips_mod_u_d, // llvm.mips.mod.u.d
			mips_mod_u_h, // llvm.mips.mod.u.h
			mips_mod_u_w, // llvm.mips.mod.u.w
	mips_modsub, // llvm.mips.modsub		mips_modsub, // llvm.mips.modsub
			mips_move_v, // llvm.mips.move.v
	mips_msub, // llvm.mips.msub		mips_msub, // llvm.mips.msub
			mips_msub_q_h, // llvm.mips.msub.q.h
			mips_msub_q_w, // llvm.mips.msub.q.w
			mips_msubr_q_h, // llvm.mips.msubr.q.h
			mips_msubr_q_w, // llvm.mips.msubr.q.w
	mips_msubu, // llvm.mips.msubu		mips_msubu, // llvm.mips.msubu
			mips_msubv_b, // llvm.mips.msubv.b
			mips_msubv_d, // llvm.mips.msubv.d
			mips_msubv_h, // llvm.mips.msubv.h
			mips_msubv_w, // llvm.mips.msubv.w
	mips_mthlip, // llvm.mips.mthlip		mips_mthlip, // llvm.mips.mthlip
	mips_mul_ph, // llvm.mips.mul.ph		mips_mul_ph, // llvm.mips.mul.ph
			mips_mul_q_h, // llvm.mips.mul.q.h
			mips_mul_q_w, // llvm.mips.mul.q.w
	mips_mul_s_ph, // llvm.mips.mul.s.ph		mips_mul_s_ph, // llvm.mips.mul.s.ph
	mips_muleq_s_w_phl, // llvm.mips.muleq.s.w.phl		mips_muleq_s_w_phl, // llvm.mips.muleq.s.w.phl
	mips_muleq_s_w_phr, // llvm.mips.muleq.s.w.phr		mips_muleq_s_w_phr, // llvm.mips.muleq.s.w.phr
	mips_muleu_s_ph_qbl, // llvm.mips.muleu.s.ph.qbl		mips_muleu_s_ph_qbl, // llvm.mips.muleu.s.ph.qbl
	mips_muleu_s_ph_qbr, // llvm.mips.muleu.s.ph.qbr		mips_muleu_s_ph_qbr, // llvm.mips.muleu.s.ph.qbr
	mips_mulq_rs_ph, // llvm.mips.mulq.rs.ph		mips_mulq_rs_ph, // llvm.mips.mulq.rs.ph
	mips_mulq_rs_w, // llvm.mips.mulq.rs.w		mips_mulq_rs_w, // llvm.mips.mulq.rs.w
	mips_mulq_s_ph, // llvm.mips.mulq.s.ph		mips_mulq_s_ph, // llvm.mips.mulq.s.ph
	mips_mulq_s_w, // llvm.mips.mulq.s.w		mips_mulq_s_w, // llvm.mips.mulq.s.w
			mips_mulr_q_h, // llvm.mips.mulr.q.h
			mips_mulr_q_w, // llvm.mips.mulr.q.w
	mips_mulsa_w_ph, // llvm.mips.mulsa.w.ph		mips_mulsa_w_ph, // llvm.mips.mulsa.w.ph
	mips_mulsaq_s_w_ph, // llvm.mips.mulsaq.s.w.ph		mips_mulsaq_s_w_ph, // llvm.mips.mulsaq.s.w.ph
	mips_mult, // llvm.mips.mult		mips_mult, // llvm.mips.mult
	mips_multu, // llvm.mips.multu		mips_multu, // llvm.mips.multu
			mips_mulv_b, // llvm.mips.mulv.b
			mips_mulv_d, // llvm.mips.mulv.d
			mips_mulv_h, // llvm.mips.mulv.h
			mips_mulv_w, // llvm.mips.mulv.w
			mips_nloc_b, // llvm.mips.nloc.b
			mips_nloc_d, // llvm.mips.nloc.d
			mips_nloc_h, // llvm.mips.nloc.h
			mips_nloc_w, // llvm.mips.nloc.w
			mips_nlzc_b, // llvm.mips.nlzc.b
			mips_nlzc_d, // llvm.mips.nlzc.d
			mips_nlzc_h, // llvm.mips.nlzc.h
			mips_nlzc_w, // llvm.mips.nlzc.w
			mips_nor_v, // llvm.mips.nor.v
			mips_nori_b, // llvm.mips.nori.b
			mips_or_v, // llvm.mips.or.v
			mips_ori_b, // llvm.mips.ori.b
	mips_packrl_ph, // llvm.mips.packrl.ph		mips_packrl_ph, // llvm.mips.packrl.ph
			mips_pckev_b, // llvm.mips.pckev.b
			mips_pckev_d, // llvm.mips.pckev.d
			mips_pckev_h, // llvm.mips.pckev.h
			mips_pckev_w, // llvm.mips.pckev.w
			mips_pckod_b, // llvm.mips.pckod.b
			mips_pckod_d, // llvm.mips.pckod.d
			mips_pckod_h, // llvm.mips.pckod.h
			mips_pckod_w, // llvm.mips.pckod.w
			mips_pcnt_b, // llvm.mips.pcnt.b
			mips_pcnt_d, // llvm.mips.pcnt.d
			mips_pcnt_h, // llvm.mips.pcnt.h
			mips_pcnt_w, // llvm.mips.pcnt.w
	mips_pick_ph, // llvm.mips.pick.ph		mips_pick_ph, // llvm.mips.pick.ph
	mips_pick_qb, // llvm.mips.pick.qb		mips_pick_qb, // llvm.mips.pick.qb
	mips_preceq_w_phl, // llvm.mips.preceq.w.phl		mips_preceq_w_phl, // llvm.mips.preceq.w.phl
	mips_preceq_w_phr, // llvm.mips.preceq.w.phr		mips_preceq_w_phr, // llvm.mips.preceq.w.phr
	mips_precequ_ph_qbl, // llvm.mips.precequ.ph.qbl		mips_precequ_ph_qbl, // llvm.mips.precequ.ph.qbl
	mips_precequ_ph_qbla, // llvm.mips.precequ.ph.qbla		mips_precequ_ph_qbla, // llvm.mips.precequ.ph.qbla
	mips_precequ_ph_qbr, // llvm.mips.precequ.ph.qbr		mips_precequ_ph_qbr, // llvm.mips.precequ.ph.qbr
	mips_precequ_ph_qbra, // llvm.mips.precequ.ph.qbra		mips_precequ_ph_qbra, // llvm.mips.precequ.ph.qbra
	mips_preceu_ph_qbl, // llvm.mips.preceu.ph.qbl		mips_preceu_ph_qbl, // llvm.mips.preceu.ph.qbl
	mips_preceu_ph_qbla, // llvm.mips.preceu.ph.qbla		mips_preceu_ph_qbla, // llvm.mips.preceu.ph.qbla
	skipping to change at line 1162		skipping to change at line 1761
	mips_precr_sra_r_ph_w, // llvm.mips.precr.sra.r.ph.w		mips_precr_sra_r_ph_w, // llvm.mips.precr.sra.r.ph.w
	mips_precrq_ph_w, // llvm.mips.precrq.ph.w		mips_precrq_ph_w, // llvm.mips.precrq.ph.w
	mips_precrq_qb_ph, // llvm.mips.precrq.qb.ph		mips_precrq_qb_ph, // llvm.mips.precrq.qb.ph
	mips_precrq_rs_ph_w, // llvm.mips.precrq.rs.ph.w		mips_precrq_rs_ph_w, // llvm.mips.precrq.rs.ph.w
	mips_precrqu_s_qb_ph, // llvm.mips.precrqu.s.qb.ph		mips_precrqu_s_qb_ph, // llvm.mips.precrqu.s.qb.ph
	mips_prepend, // llvm.mips.prepend		mips_prepend, // llvm.mips.prepend
	mips_raddu_w_qb, // llvm.mips.raddu.w.qb		mips_raddu_w_qb, // llvm.mips.raddu.w.qb
	mips_rddsp, // llvm.mips.rddsp		mips_rddsp, // llvm.mips.rddsp
	mips_repl_ph, // llvm.mips.repl.ph		mips_repl_ph, // llvm.mips.repl.ph
	mips_repl_qb, // llvm.mips.repl.qb		mips_repl_qb, // llvm.mips.repl.qb
			mips_sat_s_b, // llvm.mips.sat.s.b
			mips_sat_s_d, // llvm.mips.sat.s.d
			mips_sat_s_h, // llvm.mips.sat.s.h
			mips_sat_s_w, // llvm.mips.sat.s.w
			mips_sat_u_b, // llvm.mips.sat.u.b
			mips_sat_u_d, // llvm.mips.sat.u.d
			mips_sat_u_h, // llvm.mips.sat.u.h
			mips_sat_u_w, // llvm.mips.sat.u.w
			mips_shf_b, // llvm.mips.shf.b
			mips_shf_h, // llvm.mips.shf.h
			mips_shf_w, // llvm.mips.shf.w
	mips_shilo, // llvm.mips.shilo		mips_shilo, // llvm.mips.shilo
	mips_shll_ph, // llvm.mips.shll.ph		mips_shll_ph, // llvm.mips.shll.ph
	mips_shll_qb, // llvm.mips.shll.qb		mips_shll_qb, // llvm.mips.shll.qb
	mips_shll_s_ph, // llvm.mips.shll.s.ph		mips_shll_s_ph, // llvm.mips.shll.s.ph
	mips_shll_s_w, // llvm.mips.shll.s.w		mips_shll_s_w, // llvm.mips.shll.s.w
	mips_shra_ph, // llvm.mips.shra.ph		mips_shra_ph, // llvm.mips.shra.ph
	mips_shra_qb, // llvm.mips.shra.qb		mips_shra_qb, // llvm.mips.shra.qb
	mips_shra_r_ph, // llvm.mips.shra.r.ph		mips_shra_r_ph, // llvm.mips.shra.r.ph
	mips_shra_r_qb, // llvm.mips.shra.r.qb		mips_shra_r_qb, // llvm.mips.shra.r.qb
	mips_shra_r_w, // llvm.mips.shra.r.w		mips_shra_r_w, // llvm.mips.shra.r.w
	mips_shrl_ph, // llvm.mips.shrl.ph		mips_shrl_ph, // llvm.mips.shrl.ph
	mips_shrl_qb, // llvm.mips.shrl.qb		mips_shrl_qb, // llvm.mips.shrl.qb
			mips_sld_b, // llvm.mips.sld.b
			mips_sld_d, // llvm.mips.sld.d
			mips_sld_h, // llvm.mips.sld.h
			mips_sld_w, // llvm.mips.sld.w
			mips_sldi_b, // llvm.mips.sldi.b
			mips_sldi_d, // llvm.mips.sldi.d
			mips_sldi_h, // llvm.mips.sldi.h
			mips_sldi_w, // llvm.mips.sldi.w
			mips_sll_b, // llvm.mips.sll.b
			mips_sll_d, // llvm.mips.sll.d
			mips_sll_h, // llvm.mips.sll.h
			mips_sll_w, // llvm.mips.sll.w
			mips_slli_b, // llvm.mips.slli.b
			mips_slli_d, // llvm.mips.slli.d
			mips_slli_h, // llvm.mips.slli.h
			mips_slli_w, // llvm.mips.slli.w
			mips_splat_b, // llvm.mips.splat.b
			mips_splat_d, // llvm.mips.splat.d
			mips_splat_h, // llvm.mips.splat.h
			mips_splat_w, // llvm.mips.splat.w
			mips_splati_b, // llvm.mips.splati.b
			mips_splati_d, // llvm.mips.splati.d
			mips_splati_h, // llvm.mips.splati.h
			mips_splati_w, // llvm.mips.splati.w
			mips_sra_b, // llvm.mips.sra.b
			mips_sra_d, // llvm.mips.sra.d
			mips_sra_h, // llvm.mips.sra.h
			mips_sra_w, // llvm.mips.sra.w
			mips_srai_b, // llvm.mips.srai.b
			mips_srai_d, // llvm.mips.srai.d
			mips_srai_h, // llvm.mips.srai.h
			mips_srai_w, // llvm.mips.srai.w
			mips_srar_b, // llvm.mips.srar.b
			mips_srar_d, // llvm.mips.srar.d
			mips_srar_h, // llvm.mips.srar.h
			mips_srar_w, // llvm.mips.srar.w
			mips_srari_b, // llvm.mips.srari.b
			mips_srari_d, // llvm.mips.srari.d
			mips_srari_h, // llvm.mips.srari.h
			mips_srari_w, // llvm.mips.srari.w
			mips_srl_b, // llvm.mips.srl.b
			mips_srl_d, // llvm.mips.srl.d
			mips_srl_h, // llvm.mips.srl.h
			mips_srl_w, // llvm.mips.srl.w
			mips_srli_b, // llvm.mips.srli.b
			mips_srli_d, // llvm.mips.srli.d
			mips_srli_h, // llvm.mips.srli.h
			mips_srli_w, // llvm.mips.srli.w
			mips_srlr_b, // llvm.mips.srlr.b
			mips_srlr_d, // llvm.mips.srlr.d
			mips_srlr_h, // llvm.mips.srlr.h
			mips_srlr_w, // llvm.mips.srlr.w
			mips_srlri_b, // llvm.mips.srlri.b
			mips_srlri_d, // llvm.mips.srlri.d
			mips_srlri_h, // llvm.mips.srlri.h
			mips_srlri_w, // llvm.mips.srlri.w
			mips_st_b, // llvm.mips.st.b
			mips_st_d, // llvm.mips.st.d
			mips_st_h, // llvm.mips.st.h
			mips_st_w, // llvm.mips.st.w
	mips_subq_ph, // llvm.mips.subq.ph		mips_subq_ph, // llvm.mips.subq.ph
	mips_subq_s_ph, // llvm.mips.subq.s.ph		mips_subq_s_ph, // llvm.mips.subq.s.ph
	mips_subq_s_w, // llvm.mips.subq.s.w		mips_subq_s_w, // llvm.mips.subq.s.w
	mips_subqh_ph, // llvm.mips.subqh.ph		mips_subqh_ph, // llvm.mips.subqh.ph
	mips_subqh_r_ph, // llvm.mips.subqh.r.ph		mips_subqh_r_ph, // llvm.mips.subqh.r.ph
	mips_subqh_r_w, // llvm.mips.subqh.r.w		mips_subqh_r_w, // llvm.mips.subqh.r.w
	mips_subqh_w, // llvm.mips.subqh.w		mips_subqh_w, // llvm.mips.subqh.w
			mips_subs_s_b, // llvm.mips.subs.s.b
			mips_subs_s_d, // llvm.mips.subs.s.d
			mips_subs_s_h, // llvm.mips.subs.s.h
			mips_subs_s_w, // llvm.mips.subs.s.w
			mips_subs_u_b, // llvm.mips.subs.u.b
			mips_subs_u_d, // llvm.mips.subs.u.d
			mips_subs_u_h, // llvm.mips.subs.u.h
			mips_subs_u_w, // llvm.mips.subs.u.w
			mips_subsus_u_b, // llvm.mips.subsus.u.b
			mips_subsus_u_d, // llvm.mips.subsus.u.d
			mips_subsus_u_h, // llvm.mips.subsus.u.h
			mips_subsus_u_w, // llvm.mips.subsus.u.w
			mips_subsuu_s_b, // llvm.mips.subsuu.s.b
			mips_subsuu_s_d, // llvm.mips.subsuu.s.d
			mips_subsuu_s_h, // llvm.mips.subsuu.s.h
			mips_subsuu_s_w, // llvm.mips.subsuu.s.w
	mips_subu_ph, // llvm.mips.subu.ph		mips_subu_ph, // llvm.mips.subu.ph
	mips_subu_qb, // llvm.mips.subu.qb		mips_subu_qb, // llvm.mips.subu.qb
	mips_subu_s_ph, // llvm.mips.subu.s.ph		mips_subu_s_ph, // llvm.mips.subu.s.ph
	mips_subu_s_qb, // llvm.mips.subu.s.qb		mips_subu_s_qb, // llvm.mips.subu.s.qb
	mips_subuh_qb, // llvm.mips.subuh.qb		mips_subuh_qb, // llvm.mips.subuh.qb
	mips_subuh_r_qb, // llvm.mips.subuh.r.qb		mips_subuh_r_qb, // llvm.mips.subuh.r.qb
			mips_subv_b, // llvm.mips.subv.b
			mips_subv_d, // llvm.mips.subv.d
			mips_subv_h, // llvm.mips.subv.h
			mips_subv_w, // llvm.mips.subv.w
			mips_subvi_b, // llvm.mips.subvi.b
			mips_subvi_d, // llvm.mips.subvi.d
			mips_subvi_h, // llvm.mips.subvi.h
			mips_subvi_w, // llvm.mips.subvi.w
			mips_vshf_b, // llvm.mips.vshf.b
			mips_vshf_d, // llvm.mips.vshf.d
			mips_vshf_h, // llvm.mips.vshf.h
			mips_vshf_w, // llvm.mips.vshf.w
	mips_wrdsp, // llvm.mips.wrdsp		mips_wrdsp, // llvm.mips.wrdsp
			mips_xor_v, // llvm.mips.xor.v
			mips_xori_b, // llvm.mips.xori.b
	nearbyint, // llvm.nearbyint		nearbyint, // llvm.nearbyint
	nvvm_abs_i, // llvm.nvvm.abs.i		nvvm_abs_i, // llvm.nvvm.abs.i
	nvvm_abs_ll, // llvm.nvvm.abs.ll		nvvm_abs_ll, // llvm.nvvm.abs.ll
	nvvm_add_rm_d, // llvm.nvvm.add.rm.d		nvvm_add_rm_d, // llvm.nvvm.add.rm.d
	nvvm_add_rm_f, // llvm.nvvm.add.rm.f		nvvm_add_rm_f, // llvm.nvvm.add.rm.f
	nvvm_add_rm_ftz_f, // llvm.nvvm.add.rm.ftz.f		nvvm_add_rm_ftz_f, // llvm.nvvm.add.rm.ftz.f
	nvvm_add_rn_d, // llvm.nvvm.add.rn.d		nvvm_add_rn_d, // llvm.nvvm.add.rn.d
	nvvm_add_rn_f, // llvm.nvvm.add.rn.f		nvvm_add_rn_f, // llvm.nvvm.add.rn.f
	nvvm_add_rn_ftz_f, // llvm.nvvm.add.rn.ftz.f		nvvm_add_rn_ftz_f, // llvm.nvvm.add.rn.ftz.f
	nvvm_add_rp_d, // llvm.nvvm.add.rp.d		nvvm_add_rp_d, // llvm.nvvm.add.rp.d
	skipping to change at line 1369		skipping to change at line 2069
	nvvm_membar_sys, // llvm.nvvm.membar.sys		nvvm_membar_sys, // llvm.nvvm.membar.sys
	nvvm_min_i, // llvm.nvvm.min.i		nvvm_min_i, // llvm.nvvm.min.i
	nvvm_min_ll, // llvm.nvvm.min.ll		nvvm_min_ll, // llvm.nvvm.min.ll
	nvvm_min_ui, // llvm.nvvm.min.ui		nvvm_min_ui, // llvm.nvvm.min.ui
	nvvm_min_ull, // llvm.nvvm.min.ull		nvvm_min_ull, // llvm.nvvm.min.ull
	nvvm_move_double, // llvm.nvvm.move.double		nvvm_move_double, // llvm.nvvm.move.double
	nvvm_move_float, // llvm.nvvm.move.float		nvvm_move_float, // llvm.nvvm.move.float
	nvvm_move_i16, // llvm.nvvm.move.i16		nvvm_move_i16, // llvm.nvvm.move.i16
	nvvm_move_i32, // llvm.nvvm.move.i32		nvvm_move_i32, // llvm.nvvm.move.i32
	nvvm_move_i64, // llvm.nvvm.move.i64		nvvm_move_i64, // llvm.nvvm.move.i64
	nvvm_move_i8, // llvm.nvvm.move.i8
	nvvm_move_ptr, // llvm.nvvm.move.ptr		nvvm_move_ptr, // llvm.nvvm.move.ptr
	nvvm_mul24_i, // llvm.nvvm.mul24.i		nvvm_mul24_i, // llvm.nvvm.mul24.i
	nvvm_mul24_ui, // llvm.nvvm.mul24.ui		nvvm_mul24_ui, // llvm.nvvm.mul24.ui
	nvvm_mul_rm_d, // llvm.nvvm.mul.rm.d		nvvm_mul_rm_d, // llvm.nvvm.mul.rm.d
	nvvm_mul_rm_f, // llvm.nvvm.mul.rm.f		nvvm_mul_rm_f, // llvm.nvvm.mul.rm.f
	nvvm_mul_rm_ftz_f, // llvm.nvvm.mul.rm.ftz.f		nvvm_mul_rm_ftz_f, // llvm.nvvm.mul.rm.ftz.f
	nvvm_mul_rn_d, // llvm.nvvm.mul.rn.d		nvvm_mul_rn_d, // llvm.nvvm.mul.rn.d
	nvvm_mul_rn_f, // llvm.nvvm.mul.rn.f		nvvm_mul_rn_f, // llvm.nvvm.mul.rn.f
	nvvm_mul_rn_ftz_f, // llvm.nvvm.mul.rn.ftz.f		nvvm_mul_rn_ftz_f, // llvm.nvvm.mul.rn.ftz.f
	nvvm_mul_rp_d, // llvm.nvvm.mul.rp.d		nvvm_mul_rp_d, // llvm.nvvm.mul.rp.d
	skipping to change at line 1633		skipping to change at line 2332
	ppc_altivec_vupklsb, // llvm.ppc.altivec.vupklsb		ppc_altivec_vupklsb, // llvm.ppc.altivec.vupklsb
	ppc_altivec_vupklsh, // llvm.ppc.altivec.vupklsh		ppc_altivec_vupklsh, // llvm.ppc.altivec.vupklsh
	ppc_dcba, // llvm.ppc.dcba		ppc_dcba, // llvm.ppc.dcba
	ppc_dcbf, // llvm.ppc.dcbf		ppc_dcbf, // llvm.ppc.dcbf
	ppc_dcbi, // llvm.ppc.dcbi		ppc_dcbi, // llvm.ppc.dcbi
	ppc_dcbst, // llvm.ppc.dcbst		ppc_dcbst, // llvm.ppc.dcbst
	ppc_dcbt, // llvm.ppc.dcbt		ppc_dcbt, // llvm.ppc.dcbt
	ppc_dcbtst, // llvm.ppc.dcbtst		ppc_dcbtst, // llvm.ppc.dcbtst
	ppc_dcbz, // llvm.ppc.dcbz		ppc_dcbz, // llvm.ppc.dcbz
	ppc_dcbzl, // llvm.ppc.dcbzl		ppc_dcbzl, // llvm.ppc.dcbzl
			ppc_is_decremented_ctr_nonzero, // llvm.ppc.is.decremented.ct
			r.nonzero
			ppc_mtctr, // llvm.ppc.mtctr
	ppc_sync, // llvm.ppc.sync		ppc_sync, // llvm.ppc.sync
	prefetch, // llvm.prefetch		prefetch, // llvm.prefetch
	ptr_annotation, // llvm.ptr.annotation		ptr_annotation, // llvm.ptr.annotation
	ptx_bar_sync, // llvm.ptx.bar.sync		ptx_bar_sync, // llvm.ptx.bar.sync
	ptx_read_clock, // llvm.ptx.read.clock		ptx_read_clock, // llvm.ptx.read.clock
	ptx_read_clock64, // llvm.ptx.read.clock64		ptx_read_clock64, // llvm.ptx.read.clock64
	ptx_read_ctaid_w, // llvm.ptx.read.ctaid.w		ptx_read_ctaid_w, // llvm.ptx.read.ctaid.w
	ptx_read_ctaid_x, // llvm.ptx.read.ctaid.x		ptx_read_ctaid_x, // llvm.ptx.read.ctaid.x
	ptx_read_ctaid_y, // llvm.ptx.read.ctaid.y		ptx_read_ctaid_y, // llvm.ptx.read.ctaid.y
	ptx_read_ctaid_z, // llvm.ptx.read.ctaid.z		ptx_read_ctaid_z, // llvm.ptx.read.ctaid.z
	skipping to change at line 1688		skipping to change at line 2389
	r600_read_ngroups_z, // llvm.r600.read.ngroups.z		r600_read_ngroups_z, // llvm.r600.read.ngroups.z
	r600_read_tgid_x, // llvm.r600.read.tgid.x		r600_read_tgid_x, // llvm.r600.read.tgid.x
	r600_read_tgid_y, // llvm.r600.read.tgid.y		r600_read_tgid_y, // llvm.r600.read.tgid.y
	r600_read_tgid_z, // llvm.r600.read.tgid.z		r600_read_tgid_z, // llvm.r600.read.tgid.z
	r600_read_tidig_x, // llvm.r600.read.tidig.x		r600_read_tidig_x, // llvm.r600.read.tidig.x
	r600_read_tidig_y, // llvm.r600.read.tidig.y		r600_read_tidig_y, // llvm.r600.read.tidig.y
	r600_read_tidig_z, // llvm.r600.read.tidig.z		r600_read_tidig_z, // llvm.r600.read.tidig.z
	readcyclecounter, // llvm.readcyclecounter		readcyclecounter, // llvm.readcyclecounter
	returnaddress, // llvm.returnaddress		returnaddress, // llvm.returnaddress
	rint, // llvm.rint		rint, // llvm.rint
			round, // llvm.round
	sadd_with_overflow, // llvm.sadd.with.overflow		sadd_with_overflow, // llvm.sadd.with.overflow
	setjmp, // llvm.setjmp		setjmp, // llvm.setjmp
	siglongjmp, // llvm.siglongjmp		siglongjmp, // llvm.siglongjmp
	sigsetjmp, // llvm.sigsetjmp		sigsetjmp, // llvm.sigsetjmp
	sin, // llvm.sin		sin, // llvm.sin
	smul_with_overflow, // llvm.smul.with.overflow		smul_with_overflow, // llvm.smul.with.overflow
	sqrt, // llvm.sqrt		sqrt, // llvm.sqrt
	ssub_with_overflow, // llvm.ssub.with.overflow		ssub_with_overflow, // llvm.ssub.with.overflow
	stackprotector, // llvm.stackprotector		stackprotector, // llvm.stackprotector
			stackprotectorcheck, // llvm.stackprotectorcheck
	stackrestore, // llvm.stackrestore		stackrestore, // llvm.stackrestore
	stacksave, // llvm.stacksave		stacksave, // llvm.stacksave
	trap, // llvm.trap		trap, // llvm.trap
	trunc, // llvm.trunc		trunc, // llvm.trunc
	uadd_with_overflow, // llvm.uadd.with.overflow		uadd_with_overflow, // llvm.uadd.with.overflow
	umul_with_overflow, // llvm.umul.with.overflow		umul_with_overflow, // llvm.umul.with.overflow
	usub_with_overflow, // llvm.usub.with.overflow		usub_with_overflow, // llvm.usub.with.overflow
	vacopy, // llvm.va_copy		vacopy, // llvm.va_copy
	vaend, // llvm.va_end		vaend, // llvm.va_end
	var_annotation, // llvm.var.annotation		var_annotation, // llvm.var.annotation
	skipping to change at line 1875		skipping to change at line 2578
	x86_avx2_psubs_w, // llvm.x86.avx2.psubs.w		x86_avx2_psubs_w, // llvm.x86.avx2.psubs.w
	x86_avx2_psubus_b, // llvm.x86.avx2.psubus.b		x86_avx2_psubus_b, // llvm.x86.avx2.psubus.b
	x86_avx2_psubus_w, // llvm.x86.avx2.psubus.w		x86_avx2_psubus_w, // llvm.x86.avx2.psubus.w
	x86_avx2_vbroadcast_sd_pd_256, // llvm.x86.avx2.vbroadcast.s d.pd.256		x86_avx2_vbroadcast_sd_pd_256, // llvm.x86.avx2.vbroadcast.s d.pd.256
	x86_avx2_vbroadcast_ss_ps, // llvm.x86.avx2.vbroadcast.s s.ps		x86_avx2_vbroadcast_ss_ps, // llvm.x86.avx2.vbroadcast.s s.ps
	x86_avx2_vbroadcast_ss_ps_256, // llvm.x86.avx2.vbroadcast.s s.ps.256		x86_avx2_vbroadcast_ss_ps_256, // llvm.x86.avx2.vbroadcast.s s.ps.256
	x86_avx2_vbroadcasti128, // llvm.x86.avx2.vbroadcasti1 28		x86_avx2_vbroadcasti128, // llvm.x86.avx2.vbroadcasti1 28
	x86_avx2_vextracti128, // llvm.x86.avx2.vextracti128		x86_avx2_vextracti128, // llvm.x86.avx2.vextracti128
	x86_avx2_vinserti128, // llvm.x86.avx2.vinserti128		x86_avx2_vinserti128, // llvm.x86.avx2.vinserti128
	x86_avx2_vperm2i128, // llvm.x86.avx2.vperm2i128		x86_avx2_vperm2i128, // llvm.x86.avx2.vperm2i128
			x86_avx512_and_pi, // llvm.x86.avx512.and.pi
			x86_avx512_cmpeq_pi_512, // llvm.x86.avx512.cmpeq.pi.5
			12
			x86_avx512_conflict_d_512, // llvm.x86.avx512.conflict.d
			.512
			x86_avx512_conflict_d_mask_512, // llvm.x86.avx512.conflict.d
			.mask.512
			x86_avx512_conflict_d_maskz_512, // llvm.x86.avx512.conflict.d
			.maskz.512
			x86_avx512_conflict_q_512, // llvm.x86.avx512.conflict.q
			.512
			x86_avx512_conflict_q_mask_512, // llvm.x86.avx512.conflict.q
			.mask.512
			x86_avx512_conflict_q_maskz_512, // llvm.x86.avx512.conflict.q
			.maskz.512
			x86_avx512_cvt_ps2dq_512, // llvm.x86.avx512.cvt.ps2dq.
			512
			x86_avx512_cvtdq2_ps_512, // llvm.x86.avx512.cvtdq2.ps.
			512
			x86_avx512_cvtsd2usi, // llvm.x86.avx512.cvtsd2usi
			x86_avx512_cvtsd2usi64, // llvm.x86.avx512.cvtsd2usi6
			4
			x86_avx512_cvtss2usi, // llvm.x86.avx512.cvtss2usi
			x86_avx512_cvtss2usi64, // llvm.x86.avx512.cvtss2usi6
			4
			x86_avx512_cvttsd2usi, // llvm.x86.avx512.cvttsd2usi
			x86_avx512_cvttsd2usi64, // llvm.x86.avx512.cvttsd2usi
			64
			x86_avx512_cvttss2usi, // llvm.x86.avx512.cvttss2usi
			x86_avx512_cvttss2usi64, // llvm.x86.avx512.cvttss2usi
			64
			x86_avx512_cvtusi2sd, // llvm.x86.avx512.cvtusi2sd
			x86_avx512_cvtusi2ss, // llvm.x86.avx512.cvtusi2ss
			x86_avx512_cvtusi642sd, // llvm.x86.avx512.cvtusi642s
			d
			x86_avx512_cvtusi642ss, // llvm.x86.avx512.cvtusi642s
			s
			x86_avx512_gather_dpd_512, // llvm.x86.avx512.gather.dpd
			.512
			x86_avx512_gather_dpd_mask_512, // llvm.x86.avx512.gather.dpd
			.mask.512
			x86_avx512_gather_dpi_512, // llvm.x86.avx512.gather.dpi
			.512
			x86_avx512_gather_dpi_mask_512, // llvm.x86.avx512.gather.dpi
			.mask.512
			x86_avx512_gather_dpq_512, // llvm.x86.avx512.gather.dpq
			.512
			x86_avx512_gather_dpq_mask_512, // llvm.x86.avx512.gather.dpq
			.mask.512
			x86_avx512_gather_dps_512, // llvm.x86.avx512.gather.dps
			.512
			x86_avx512_gather_dps_mask_512, // llvm.x86.avx512.gather.dps
			.mask.512
			x86_avx512_gather_qpd_512, // llvm.x86.avx512.gather.qpd
			.512
			x86_avx512_gather_qpd_mask_512, // llvm.x86.avx512.gather.qpd
			.mask.512
			x86_avx512_gather_qpi_512, // llvm.x86.avx512.gather.qpi
			.512
			x86_avx512_gather_qpi_mask_512, // llvm.x86.avx512.gather.qpi
			.mask.512
			x86_avx512_gather_qpq_512, // llvm.x86.avx512.gather.qpq
			.512
			x86_avx512_gather_qpq_mask_512, // llvm.x86.avx512.gather.qpq
			.mask.512
			x86_avx512_gather_qps_512, // llvm.x86.avx512.gather.qps
			.512
			x86_avx512_gather_qps_mask_512, // llvm.x86.avx512.gather.qps
			.mask.512
			x86_avx512_kortestc, // llvm.x86.avx512.kortestc
			x86_avx512_kortestz, // llvm.x86.avx512.kortestz
			x86_avx512_max_pd_512, // llvm.x86.avx512.max.pd.512
			x86_avx512_max_ps_512, // llvm.x86.avx512.max.ps.512
			x86_avx512_min_pd_512, // llvm.x86.avx512.min.pd.512
			x86_avx512_min_ps_512, // llvm.x86.avx512.min.ps.512
			x86_avx512_mskblend_d_512, // llvm.x86.avx512.mskblend.d
			.512
			x86_avx512_mskblend_pd_512, // llvm.x86.avx512.mskblend.p
			d.512
			x86_avx512_mskblend_ps_512, // llvm.x86.avx512.mskblend.p
			s.512
			x86_avx512_mskblend_q_512, // llvm.x86.avx512.mskblend.q
			.512
			x86_avx512_pbroadcastd_512, // llvm.x86.avx512.pbroadcast
			d.512
			x86_avx512_pbroadcastd_i32_512, // llvm.x86.avx512.pbroadcast
			d.i32.512
			x86_avx512_pbroadcastq_512, // llvm.x86.avx512.pbroadcast
			q.512
			x86_avx512_pbroadcastq_i64_512, // llvm.x86.avx512.pbroadcast
			q.i64.512
			x86_avx512_pmaxs_d, // llvm.x86.avx512.pmaxs.d
			x86_avx512_pmaxs_q, // llvm.x86.avx512.pmaxs.q
			x86_avx512_pmaxu_d, // llvm.x86.avx512.pmaxu.d
			x86_avx512_pmaxu_q, // llvm.x86.avx512.pmaxu.q
			x86_avx512_pmins_d, // llvm.x86.avx512.pmins.d
			x86_avx512_pmins_q, // llvm.x86.avx512.pmins.q
			x86_avx512_pminu_d, // llvm.x86.avx512.pminu.d
			x86_avx512_pminu_q, // llvm.x86.avx512.pminu.q
			x86_avx512_pmovzxbd, // llvm.x86.avx512.pmovzxbd
			x86_avx512_pmovzxbq, // llvm.x86.avx512.pmovzxbq
			x86_avx512_pmovzxdq, // llvm.x86.avx512.pmovzxdq
			x86_avx512_pmovzxwd, // llvm.x86.avx512.pmovzxwd
			x86_avx512_pmovzxwq, // llvm.x86.avx512.pmovzxwq
			x86_avx512_psll_dq, // llvm.x86.avx512.psll.dq
			x86_avx512_psll_dq_bs, // llvm.x86.avx512.psll.dq.bs
			x86_avx512_psrl_dq, // llvm.x86.avx512.psrl.dq
			x86_avx512_psrl_dq_bs, // llvm.x86.avx512.psrl.dq.bs
			x86_avx512_rcp14_pd_512, // llvm.x86.avx512.rcp14.pd.5
			12
			x86_avx512_rcp14_ps_512, // llvm.x86.avx512.rcp14.ps.5
			12
			x86_avx512_rcp14_sd, // llvm.x86.avx512.rcp14.sd
			x86_avx512_rcp14_ss, // llvm.x86.avx512.rcp14.ss
			x86_avx512_rcp28_pd_512, // llvm.x86.avx512.rcp28.pd.5
			12
			x86_avx512_rcp28_ps_512, // llvm.x86.avx512.rcp28.ps.5
			12
			x86_avx512_rcp28_sd, // llvm.x86.avx512.rcp28.sd
			x86_avx512_rcp28_ss, // llvm.x86.avx512.rcp28.ss
			x86_avx512_rndscale_pd_512, // llvm.x86.avx512.rndscale.p
			d.512
			x86_avx512_rndscale_ps_512, // llvm.x86.avx512.rndscale.p
			s.512
			x86_avx512_rndscale_sd, // llvm.x86.avx512.rndscale.s
			d
			x86_avx512_rndscale_ss, // llvm.x86.avx512.rndscale.s
			s
			x86_avx512_rsqrt14_pd_512, // llvm.x86.avx512.rsqrt14.pd
			.512
			x86_avx512_rsqrt14_ps_512, // llvm.x86.avx512.rsqrt14.ps
			.512
			x86_avx512_rsqrt14_sd, // llvm.x86.avx512.rsqrt14.sd
			x86_avx512_rsqrt14_ss, // llvm.x86.avx512.rsqrt14.ss
			x86_avx512_rsqrt28_pd_512, // llvm.x86.avx512.rsqrt28.pd
			.512
			x86_avx512_rsqrt28_ps_512, // llvm.x86.avx512.rsqrt28.ps
			.512
			x86_avx512_rsqrt28_sd, // llvm.x86.avx512.rsqrt28.sd
			x86_avx512_rsqrt28_ss, // llvm.x86.avx512.rsqrt28.ss
			x86_avx512_scatter_dpd_512, // llvm.x86.avx512.scatter.dp
			d.512
			x86_avx512_scatter_dpd_mask_512, // llvm.x86.avx512.scatter.dp
			d.mask.512
			x86_avx512_scatter_dpi_512, // llvm.x86.avx512.scatter.dp
			i.512
			x86_avx512_scatter_dpi_mask_512, // llvm.x86.avx512.scatter.dp
			i.mask.512
			x86_avx512_scatter_dpq_512, // llvm.x86.avx512.scatter.dp
			q.512
			x86_avx512_scatter_dpq_mask_512, // llvm.x86.avx512.scatter.dp
			q.mask.512
			x86_avx512_scatter_dps_512, // llvm.x86.avx512.scatter.dp
			s.512
			x86_avx512_scatter_dps_mask_512, // llvm.x86.avx512.scatter.dp
			s.mask.512
			x86_avx512_scatter_qpd_512, // llvm.x86.avx512.scatter.qp
			d.512
			x86_avx512_scatter_qpd_mask_512, // llvm.x86.avx512.scatter.qp
			d.mask.512
			x86_avx512_scatter_qpi_512, // llvm.x86.avx512.scatter.qp
			i.512
			x86_avx512_scatter_qpi_mask_512, // llvm.x86.avx512.scatter.qp
			i.mask.512
			x86_avx512_scatter_qpq_512, // llvm.x86.avx512.scatter.qp
			q.512
			x86_avx512_scatter_qpq_mask_512, // llvm.x86.avx512.scatter.qp
			q.mask.512
			x86_avx512_scatter_qps_512, // llvm.x86.avx512.scatter.qp
			s.512
			x86_avx512_scatter_qps_mask_512, // llvm.x86.avx512.scatter.qp
			s.mask.512
			x86_avx512_sqrt_pd_512, // llvm.x86.avx512.sqrt.pd.51
			2
			x86_avx512_sqrt_ps_512, // llvm.x86.avx512.sqrt.ps.51
			2
			x86_avx512_sqrt_sd, // llvm.x86.avx512.sqrt.sd
			x86_avx512_sqrt_ss, // llvm.x86.avx512.sqrt.ss
			x86_avx512_vbroadcast_sd_512, // llvm.x86.avx512.vbroadcast
			.sd.512
			x86_avx512_vbroadcast_sd_pd_512, // llvm.x86.avx512.vbroadcast
			.sd.pd.512
			x86_avx512_vbroadcast_ss_512, // llvm.x86.avx512.vbroadcast
			.ss.512
			x86_avx512_vbroadcast_ss_ps_512, // llvm.x86.avx512.vbroadcast
			.ss.ps.512
			x86_avx512_vcvtph2ps_512, // llvm.x86.avx512.vcvtph2ps.
			512
			x86_avx512_vcvtps2ph_512, // llvm.x86.avx512.vcvtps2ph.
			512
	x86_avx_addsub_pd_256, // llvm.x86.avx.addsub.pd.256		x86_avx_addsub_pd_256, // llvm.x86.avx.addsub.pd.256
	x86_avx_addsub_ps_256, // llvm.x86.avx.addsub.ps.256		x86_avx_addsub_ps_256, // llvm.x86.avx.addsub.ps.256
	x86_avx_blend_pd_256, // llvm.x86.avx.blend.pd.256		x86_avx_blend_pd_256, // llvm.x86.avx.blend.pd.256
	x86_avx_blend_ps_256, // llvm.x86.avx.blend.ps.256		x86_avx_blend_ps_256, // llvm.x86.avx.blend.ps.256
	x86_avx_blendv_pd_256, // llvm.x86.avx.blendv.pd.256		x86_avx_blendv_pd_256, // llvm.x86.avx.blendv.pd.256
	x86_avx_blendv_ps_256, // llvm.x86.avx.blendv.ps.256		x86_avx_blendv_ps_256, // llvm.x86.avx.blendv.ps.256
	x86_avx_cmp_pd_256, // llvm.x86.avx.cmp.pd.256		x86_avx_cmp_pd_256, // llvm.x86.avx.cmp.pd.256
	x86_avx_cmp_ps_256, // llvm.x86.avx.cmp.ps.256		x86_avx_cmp_ps_256, // llvm.x86.avx.cmp.ps.256
	x86_avx_cvt_pd2_ps_256, // llvm.x86.avx.cvt.pd2.ps.25 6		x86_avx_cvt_pd2_ps_256, // llvm.x86.avx.cvt.pd2.ps.25 6
	x86_avx_cvt_pd2dq_256, // llvm.x86.avx.cvt.pd2dq.256		x86_avx_cvt_pd2dq_256, // llvm.x86.avx.cvt.pd2dq.256
	skipping to change at line 1965		skipping to change at line 2783
	x86_bmi_bextr_32, // llvm.x86.bmi.bextr.32		x86_bmi_bextr_32, // llvm.x86.bmi.bextr.32
	x86_bmi_bextr_64, // llvm.x86.bmi.bextr.64		x86_bmi_bextr_64, // llvm.x86.bmi.bextr.64
	x86_bmi_bzhi_32, // llvm.x86.bmi.bzhi.32		x86_bmi_bzhi_32, // llvm.x86.bmi.bzhi.32
	x86_bmi_bzhi_64, // llvm.x86.bmi.bzhi.64		x86_bmi_bzhi_64, // llvm.x86.bmi.bzhi.64
	x86_bmi_pdep_32, // llvm.x86.bmi.pdep.32		x86_bmi_pdep_32, // llvm.x86.bmi.pdep.32
	x86_bmi_pdep_64, // llvm.x86.bmi.pdep.64		x86_bmi_pdep_64, // llvm.x86.bmi.pdep.64
	x86_bmi_pext_32, // llvm.x86.bmi.pext.32		x86_bmi_pext_32, // llvm.x86.bmi.pext.32
	x86_bmi_pext_64, // llvm.x86.bmi.pext.64		x86_bmi_pext_64, // llvm.x86.bmi.pext.64
	x86_fma_vfmadd_pd, // llvm.x86.fma.vfmadd.pd		x86_fma_vfmadd_pd, // llvm.x86.fma.vfmadd.pd
	x86_fma_vfmadd_pd_256, // llvm.x86.fma.vfmadd.pd.256		x86_fma_vfmadd_pd_256, // llvm.x86.fma.vfmadd.pd.256
			x86_fma_vfmadd_pd_512, // llvm.x86.fma.vfmadd.pd.512
	x86_fma_vfmadd_ps, // llvm.x86.fma.vfmadd.ps		x86_fma_vfmadd_ps, // llvm.x86.fma.vfmadd.ps
	x86_fma_vfmadd_ps_256, // llvm.x86.fma.vfmadd.ps.256		x86_fma_vfmadd_ps_256, // llvm.x86.fma.vfmadd.ps.256
			x86_fma_vfmadd_ps_512, // llvm.x86.fma.vfmadd.ps.512
	x86_fma_vfmadd_sd, // llvm.x86.fma.vfmadd.sd		x86_fma_vfmadd_sd, // llvm.x86.fma.vfmadd.sd
	x86_fma_vfmadd_ss, // llvm.x86.fma.vfmadd.ss		x86_fma_vfmadd_ss, // llvm.x86.fma.vfmadd.ss
	x86_fma_vfmaddsub_pd, // llvm.x86.fma.vfmaddsub.pd		x86_fma_vfmaddsub_pd, // llvm.x86.fma.vfmaddsub.pd
	x86_fma_vfmaddsub_pd_256, // llvm.x86.fma.vfmaddsub.pd. 256		x86_fma_vfmaddsub_pd_256, // llvm.x86.fma.vfmaddsub.pd. 256
			x86_fma_vfmaddsub_pd_512, // llvm.x86.fma.vfmaddsub.pd. 512
	x86_fma_vfmaddsub_ps, // llvm.x86.fma.vfmaddsub.ps		x86_fma_vfmaddsub_ps, // llvm.x86.fma.vfmaddsub.ps
	x86_fma_vfmaddsub_ps_256, // llvm.x86.fma.vfmaddsub.ps. 256		x86_fma_vfmaddsub_ps_256, // llvm.x86.fma.vfmaddsub.ps. 256
			x86_fma_vfmaddsub_ps_512, // llvm.x86.fma.vfmaddsub.ps. 512
	x86_fma_vfmsub_pd, // llvm.x86.fma.vfmsub.pd		x86_fma_vfmsub_pd, // llvm.x86.fma.vfmsub.pd
	x86_fma_vfmsub_pd_256, // llvm.x86.fma.vfmsub.pd.256		x86_fma_vfmsub_pd_256, // llvm.x86.fma.vfmsub.pd.256
			x86_fma_vfmsub_pd_512, // llvm.x86.fma.vfmsub.pd.512
	x86_fma_vfmsub_ps, // llvm.x86.fma.vfmsub.ps		x86_fma_vfmsub_ps, // llvm.x86.fma.vfmsub.ps
	x86_fma_vfmsub_ps_256, // llvm.x86.fma.vfmsub.ps.256		x86_fma_vfmsub_ps_256, // llvm.x86.fma.vfmsub.ps.256
			x86_fma_vfmsub_ps_512, // llvm.x86.fma.vfmsub.ps.512
	x86_fma_vfmsub_sd, // llvm.x86.fma.vfmsub.sd		x86_fma_vfmsub_sd, // llvm.x86.fma.vfmsub.sd
	x86_fma_vfmsub_ss, // llvm.x86.fma.vfmsub.ss		x86_fma_vfmsub_ss, // llvm.x86.fma.vfmsub.ss
	x86_fma_vfmsubadd_pd, // llvm.x86.fma.vfmsubadd.pd		x86_fma_vfmsubadd_pd, // llvm.x86.fma.vfmsubadd.pd
	x86_fma_vfmsubadd_pd_256, // llvm.x86.fma.vfmsubadd.pd. 256		x86_fma_vfmsubadd_pd_256, // llvm.x86.fma.vfmsubadd.pd. 256
			x86_fma_vfmsubadd_pd_512, // llvm.x86.fma.vfmsubadd.pd. 512
	x86_fma_vfmsubadd_ps, // llvm.x86.fma.vfmsubadd.ps		x86_fma_vfmsubadd_ps, // llvm.x86.fma.vfmsubadd.ps
	x86_fma_vfmsubadd_ps_256, // llvm.x86.fma.vfmsubadd.ps. 256		x86_fma_vfmsubadd_ps_256, // llvm.x86.fma.vfmsubadd.ps. 256
			x86_fma_vfmsubadd_ps_512, // llvm.x86.fma.vfmsubadd.ps. 512
	x86_fma_vfnmadd_pd, // llvm.x86.fma.vfnmadd.pd		x86_fma_vfnmadd_pd, // llvm.x86.fma.vfnmadd.pd
	x86_fma_vfnmadd_pd_256, // llvm.x86.fma.vfnmadd.pd.25 6		x86_fma_vfnmadd_pd_256, // llvm.x86.fma.vfnmadd.pd.25 6
			x86_fma_vfnmadd_pd_512, // llvm.x86.fma.vfnmadd.pd.51 2
	x86_fma_vfnmadd_ps, // llvm.x86.fma.vfnmadd.ps		x86_fma_vfnmadd_ps, // llvm.x86.fma.vfnmadd.ps
	x86_fma_vfnmadd_ps_256, // llvm.x86.fma.vfnmadd.ps.25 6		x86_fma_vfnmadd_ps_256, // llvm.x86.fma.vfnmadd.ps.25 6
			x86_fma_vfnmadd_ps_512, // llvm.x86.fma.vfnmadd.ps.51 2
	x86_fma_vfnmadd_sd, // llvm.x86.fma.vfnmadd.sd		x86_fma_vfnmadd_sd, // llvm.x86.fma.vfnmadd.sd
	x86_fma_vfnmadd_ss, // llvm.x86.fma.vfnmadd.ss		x86_fma_vfnmadd_ss, // llvm.x86.fma.vfnmadd.ss
	x86_fma_vfnmsub_pd, // llvm.x86.fma.vfnmsub.pd		x86_fma_vfnmsub_pd, // llvm.x86.fma.vfnmsub.pd
	x86_fma_vfnmsub_pd_256, // llvm.x86.fma.vfnmsub.pd.25 6		x86_fma_vfnmsub_pd_256, // llvm.x86.fma.vfnmsub.pd.25 6
			x86_fma_vfnmsub_pd_512, // llvm.x86.fma.vfnmsub.pd.51 2
	x86_fma_vfnmsub_ps, // llvm.x86.fma.vfnmsub.ps		x86_fma_vfnmsub_ps, // llvm.x86.fma.vfnmsub.ps
	x86_fma_vfnmsub_ps_256, // llvm.x86.fma.vfnmsub.ps.25 6		x86_fma_vfnmsub_ps_256, // llvm.x86.fma.vfnmsub.ps.25 6
			x86_fma_vfnmsub_ps_512, // llvm.x86.fma.vfnmsub.ps.51 2
	x86_fma_vfnmsub_sd, // llvm.x86.fma.vfnmsub.sd		x86_fma_vfnmsub_sd, // llvm.x86.fma.vfnmsub.sd
	x86_fma_vfnmsub_ss, // llvm.x86.fma.vfnmsub.ss		x86_fma_vfnmsub_ss, // llvm.x86.fma.vfnmsub.ss
	x86_int, // llvm.x86.int		x86_int, // llvm.x86.int
			x86_int2mask_v16i1, // llvm.x86.int2mask.v16i1
			x86_kadd_v16i1, // llvm.x86.kadd.v16i1
			x86_kand_v16i1, // llvm.x86.kand.v16i1
			x86_kandn_v16i1, // llvm.x86.kandn.v16i1
			x86_knot_v16i1, // llvm.x86.knot.v16i1
			x86_kor_v16i1, // llvm.x86.kor.v16i1
			x86_kunpck_v16i1, // llvm.x86.kunpck.v16i1
			x86_kxnor_v16i1, // llvm.x86.kxnor.v16i1
			x86_kxor_v16i1, // llvm.x86.kxor.v16i1
			x86_mask2int_v16i1, // llvm.x86.mask2int.v16i1
	x86_mmx_emms, // llvm.x86.mmx.emms		x86_mmx_emms, // llvm.x86.mmx.emms
	x86_mmx_femms, // llvm.x86.mmx.femms		x86_mmx_femms, // llvm.x86.mmx.femms
	x86_mmx_maskmovq, // llvm.x86.mmx.maskmovq		x86_mmx_maskmovq, // llvm.x86.mmx.maskmovq
	x86_mmx_movnt_dq, // llvm.x86.mmx.movnt.dq		x86_mmx_movnt_dq, // llvm.x86.mmx.movnt.dq
	x86_mmx_packssdw, // llvm.x86.mmx.packssdw		x86_mmx_packssdw, // llvm.x86.mmx.packssdw
	x86_mmx_packsswb, // llvm.x86.mmx.packsswb		x86_mmx_packsswb, // llvm.x86.mmx.packsswb
	x86_mmx_packuswb, // llvm.x86.mmx.packuswb		x86_mmx_packuswb, // llvm.x86.mmx.packuswb
	x86_mmx_padd_b, // llvm.x86.mmx.padd.b		x86_mmx_padd_b, // llvm.x86.mmx.padd.b
	x86_mmx_padd_d, // llvm.x86.mmx.padd.d		x86_mmx_padd_d, // llvm.x86.mmx.padd.d
	x86_mmx_padd_q, // llvm.x86.mmx.padd.q		x86_mmx_padd_q, // llvm.x86.mmx.padd.q
	skipping to change at line 2078		skipping to change at line 2918
	x86_rdfsbase_32, // llvm.x86.rdfsbase.32		x86_rdfsbase_32, // llvm.x86.rdfsbase.32
	x86_rdfsbase_64, // llvm.x86.rdfsbase.64		x86_rdfsbase_64, // llvm.x86.rdfsbase.64
	x86_rdgsbase_32, // llvm.x86.rdgsbase.32		x86_rdgsbase_32, // llvm.x86.rdgsbase.32
	x86_rdgsbase_64, // llvm.x86.rdgsbase.64		x86_rdgsbase_64, // llvm.x86.rdgsbase.64
	x86_rdrand_16, // llvm.x86.rdrand.16		x86_rdrand_16, // llvm.x86.rdrand.16
	x86_rdrand_32, // llvm.x86.rdrand.32		x86_rdrand_32, // llvm.x86.rdrand.32
	x86_rdrand_64, // llvm.x86.rdrand.64		x86_rdrand_64, // llvm.x86.rdrand.64
	x86_rdseed_16, // llvm.x86.rdseed.16		x86_rdseed_16, // llvm.x86.rdseed.16
	x86_rdseed_32, // llvm.x86.rdseed.32		x86_rdseed_32, // llvm.x86.rdseed.32
	x86_rdseed_64, // llvm.x86.rdseed.64		x86_rdseed_64, // llvm.x86.rdseed.64
			x86_sha1msg1, // llvm.x86.sha1msg1
			x86_sha1msg2, // llvm.x86.sha1msg2
			x86_sha1nexte, // llvm.x86.sha1nexte
			x86_sha1rnds4, // llvm.x86.sha1rnds4
			x86_sha256msg1, // llvm.x86.sha256msg1
			x86_sha256msg2, // llvm.x86.sha256msg2
			x86_sha256rnds2, // llvm.x86.sha256rnds2
	x86_sse2_add_sd, // llvm.x86.sse2.add.sd		x86_sse2_add_sd, // llvm.x86.sse2.add.sd
	x86_sse2_clflush, // llvm.x86.sse2.clflush		x86_sse2_clflush, // llvm.x86.sse2.clflush
	x86_sse2_cmp_pd, // llvm.x86.sse2.cmp.pd		x86_sse2_cmp_pd, // llvm.x86.sse2.cmp.pd
	x86_sse2_cmp_sd, // llvm.x86.sse2.cmp.sd		x86_sse2_cmp_sd, // llvm.x86.sse2.cmp.sd
	x86_sse2_comieq_sd, // llvm.x86.sse2.comieq.sd		x86_sse2_comieq_sd, // llvm.x86.sse2.comieq.sd
	x86_sse2_comige_sd, // llvm.x86.sse2.comige.sd		x86_sse2_comige_sd, // llvm.x86.sse2.comige.sd
	x86_sse2_comigt_sd, // llvm.x86.sse2.comigt.sd		x86_sse2_comigt_sd, // llvm.x86.sse2.comigt.sd
	x86_sse2_comile_sd, // llvm.x86.sse2.comile.sd		x86_sse2_comile_sd, // llvm.x86.sse2.comile.sd
	x86_sse2_comilt_sd, // llvm.x86.sse2.comilt.sd		x86_sse2_comilt_sd, // llvm.x86.sse2.comilt.sd
	x86_sse2_comineq_sd, // llvm.x86.sse2.comineq.sd		x86_sse2_comineq_sd, // llvm.x86.sse2.comineq.sd
	skipping to change at line 2227		skipping to change at line 3074
	x86_sse41_ptestnzc, // llvm.x86.sse41.ptestnzc		x86_sse41_ptestnzc, // llvm.x86.sse41.ptestnzc
	x86_sse41_ptestz, // llvm.x86.sse41.ptestz		x86_sse41_ptestz, // llvm.x86.sse41.ptestz
	x86_sse41_round_pd, // llvm.x86.sse41.round.pd		x86_sse41_round_pd, // llvm.x86.sse41.round.pd
	x86_sse41_round_ps, // llvm.x86.sse41.round.ps		x86_sse41_round_ps, // llvm.x86.sse41.round.ps
	x86_sse41_round_sd, // llvm.x86.sse41.round.sd		x86_sse41_round_sd, // llvm.x86.sse41.round.sd
	x86_sse41_round_ss, // llvm.x86.sse41.round.ss		x86_sse41_round_ss, // llvm.x86.sse41.round.ss
	x86_sse42_crc32_32_16, // llvm.x86.sse42.crc32.32.16		x86_sse42_crc32_32_16, // llvm.x86.sse42.crc32.32.16
	x86_sse42_crc32_32_32, // llvm.x86.sse42.crc32.32.32		x86_sse42_crc32_32_32, // llvm.x86.sse42.crc32.32.32
	x86_sse42_crc32_32_8, // llvm.x86.sse42.crc32.32.8		x86_sse42_crc32_32_8, // llvm.x86.sse42.crc32.32.8
	x86_sse42_crc32_64_64, // llvm.x86.sse42.crc32.64.64		x86_sse42_crc32_64_64, // llvm.x86.sse42.crc32.64.64
	x86_sse42_crc32_64_8, // llvm.x86.sse42.crc32.64.8
	x86_sse42_pcmpestri128, // llvm.x86.sse42.pcmpestri12 8		x86_sse42_pcmpestri128, // llvm.x86.sse42.pcmpestri12 8
	x86_sse42_pcmpestria128, // llvm.x86.sse42.pcmpestria1 28		x86_sse42_pcmpestria128, // llvm.x86.sse42.pcmpestria1 28
	x86_sse42_pcmpestric128, // llvm.x86.sse42.pcmpestric1 28		x86_sse42_pcmpestric128, // llvm.x86.sse42.pcmpestric1 28
	x86_sse42_pcmpestrio128, // llvm.x86.sse42.pcmpestrio1 28		x86_sse42_pcmpestrio128, // llvm.x86.sse42.pcmpestrio1 28
	x86_sse42_pcmpestris128, // llvm.x86.sse42.pcmpestris1 28		x86_sse42_pcmpestris128, // llvm.x86.sse42.pcmpestris1 28
	x86_sse42_pcmpestriz128, // llvm.x86.sse42.pcmpestriz1 28		x86_sse42_pcmpestriz128, // llvm.x86.sse42.pcmpestriz1 28
	x86_sse42_pcmpestrm128, // llvm.x86.sse42.pcmpestrm12 8		x86_sse42_pcmpestrm128, // llvm.x86.sse42.pcmpestrm12 8
	x86_sse42_pcmpistri128, // llvm.x86.sse42.pcmpistri12 8		x86_sse42_pcmpistri128, // llvm.x86.sse42.pcmpistri12 8
	x86_sse42_pcmpistria128, // llvm.x86.sse42.pcmpistria1 28		x86_sse42_pcmpistria128, // llvm.x86.sse42.pcmpistria1 28
	x86_sse42_pcmpistric128, // llvm.x86.sse42.pcmpistric1 28		x86_sse42_pcmpistric128, // llvm.x86.sse42.pcmpistric1 28
	skipping to change at line 2324		skipping to change at line 3170
	x86_ssse3_pmul_hr_sw, // llvm.x86.ssse3.pmul.hr.sw		x86_ssse3_pmul_hr_sw, // llvm.x86.ssse3.pmul.hr.sw
	x86_ssse3_pmul_hr_sw_128, // llvm.x86.ssse3.pmul.hr.sw. 128		x86_ssse3_pmul_hr_sw_128, // llvm.x86.ssse3.pmul.hr.sw. 128
	x86_ssse3_pshuf_b, // llvm.x86.ssse3.pshuf.b		x86_ssse3_pshuf_b, // llvm.x86.ssse3.pshuf.b
	x86_ssse3_pshuf_b_128, // llvm.x86.ssse3.pshuf.b.128		x86_ssse3_pshuf_b_128, // llvm.x86.ssse3.pshuf.b.128
	x86_ssse3_psign_b, // llvm.x86.ssse3.psign.b		x86_ssse3_psign_b, // llvm.x86.ssse3.psign.b
	x86_ssse3_psign_b_128, // llvm.x86.ssse3.psign.b.128		x86_ssse3_psign_b_128, // llvm.x86.ssse3.psign.b.128
	x86_ssse3_psign_d, // llvm.x86.ssse3.psign.d		x86_ssse3_psign_d, // llvm.x86.ssse3.psign.d
	x86_ssse3_psign_d_128, // llvm.x86.ssse3.psign.d.128		x86_ssse3_psign_d_128, // llvm.x86.ssse3.psign.d.128
	x86_ssse3_psign_w, // llvm.x86.ssse3.psign.w		x86_ssse3_psign_w, // llvm.x86.ssse3.psign.w
	x86_ssse3_psign_w_128, // llvm.x86.ssse3.psign.w.128		x86_ssse3_psign_w_128, // llvm.x86.ssse3.psign.w.128
			x86_tbm_bextri_u32, // llvm.x86.tbm.bextri.u32
			x86_tbm_bextri_u64, // llvm.x86.tbm.bextri.u64
	x86_vcvtph2ps_128, // llvm.x86.vcvtph2ps.128		x86_vcvtph2ps_128, // llvm.x86.vcvtph2ps.128
	x86_vcvtph2ps_256, // llvm.x86.vcvtph2ps.256		x86_vcvtph2ps_256, // llvm.x86.vcvtph2ps.256
	x86_vcvtps2ph_128, // llvm.x86.vcvtps2ph.128		x86_vcvtps2ph_128, // llvm.x86.vcvtps2ph.128
	x86_vcvtps2ph_256, // llvm.x86.vcvtps2ph.256		x86_vcvtps2ph_256, // llvm.x86.vcvtps2ph.256
	x86_wrfsbase_32, // llvm.x86.wrfsbase.32		x86_wrfsbase_32, // llvm.x86.wrfsbase.32
	x86_wrfsbase_64, // llvm.x86.wrfsbase.64		x86_wrfsbase_64, // llvm.x86.wrfsbase.64
	x86_wrgsbase_32, // llvm.x86.wrgsbase.32		x86_wrgsbase_32, // llvm.x86.wrgsbase.32
	x86_wrgsbase_64, // llvm.x86.wrgsbase.64		x86_wrgsbase_64, // llvm.x86.wrgsbase.64
	x86_xabort, // llvm.x86.xabort		x86_xabort, // llvm.x86.xabort
	x86_xbegin, // llvm.x86.xbegin		x86_xbegin, // llvm.x86.xbegin
	skipping to change at line 2456		skipping to change at line 3304
	xcore_syncr, // llvm.xcore.syncr		xcore_syncr, // llvm.xcore.syncr
	xcore_testct, // llvm.xcore.testct		xcore_testct, // llvm.xcore.testct
	xcore_testwct, // llvm.xcore.testwct		xcore_testwct, // llvm.xcore.testwct
	xcore_waitevent, // llvm.xcore.waitevent		xcore_waitevent, // llvm.xcore.waitevent
	xcore_zext // llvm.xcore.zext		xcore_zext // llvm.xcore.zext
	#endif		#endif
	// Intrinsic ID to name table		// Intrinsic ID to name table
	#ifdef GET_INTRINSIC_NAME_TABLE		#ifdef GET_INTRINSIC_NAME_TABLE
	// Note that entry #0 is the invalid intrinsic!		// Note that entry #0 is the invalid intrinsic!
			"llvm.aarch64.neon.fcvtas",
			"llvm.aarch64.neon.fcvtau",
			"llvm.aarch64.neon.fcvtms",
			"llvm.aarch64.neon.fcvtmu",
			"llvm.aarch64.neon.fcvtns",
			"llvm.aarch64.neon.fcvtnu",
			"llvm.aarch64.neon.fcvtps",
			"llvm.aarch64.neon.fcvtpu",
			"llvm.aarch64.neon.fcvtxn",
			"llvm.aarch64.neon.fcvtzs",
			"llvm.aarch64.neon.fcvtzu",
			"llvm.aarch64.neon.frintn",
			"llvm.aarch64.neon.fsqrt",
			"llvm.aarch64.neon.rbit",
			"llvm.aarch64.neon.saddlv",
			"llvm.aarch64.neon.sha1c",
			"llvm.aarch64.neon.sha1m",
			"llvm.aarch64.neon.sha1p",
			"llvm.aarch64.neon.smaxv",
			"llvm.aarch64.neon.sminv",
			"llvm.aarch64.neon.suqadd",
			"llvm.aarch64.neon.uaddlv",
			"llvm.aarch64.neon.umaxv",
			"llvm.aarch64.neon.uminv",
			"llvm.aarch64.neon.usqadd",
			"llvm.aarch64.neon.vabd",
			"llvm.aarch64.neon.vabs",
			"llvm.aarch64.neon.vacgeq",
			"llvm.aarch64.neon.vacgtq",
			"llvm.aarch64.neon.vaddds",
			"llvm.aarch64.neon.vadddu",
			"llvm.aarch64.neon.vaddv",
			"llvm.aarch64.neon.vcage",
			"llvm.aarch64.neon.vcagt",
			"llvm.aarch64.neon.vceq",
			"llvm.aarch64.neon.vcge",
			"llvm.aarch64.neon.vcgt",
			"llvm.aarch64.neon.vchi",
			"llvm.aarch64.neon.vchs",
			"llvm.aarch64.neon.vclez",
			"llvm.aarch64.neon.vcltz",
			"llvm.aarch64.neon.vcvtd.n.s64.f64",
			"llvm.aarch64.neon.vcvtd.n.u64.f64",
			"llvm.aarch64.neon.vcvtf32.n.s32",
			"llvm.aarch64.neon.vcvtf32.n.u32",
			"llvm.aarch64.neon.vcvtf32.s32",
			"llvm.aarch64.neon.vcvtf32.u32",
			"llvm.aarch64.neon.vcvtf64.n.s64",
			"llvm.aarch64.neon.vcvtf64.n.u64",
			"llvm.aarch64.neon.vcvtf64.s64",
			"llvm.aarch64.neon.vcvtf64.u64",
			"llvm.aarch64.neon.vcvts.n.s32.f32",
			"llvm.aarch64.neon.vcvts.n.u32.f32",
			"llvm.aarch64.neon.vld1x2",
			"llvm.aarch64.neon.vld1x3",
			"llvm.aarch64.neon.vld1x4",
			"llvm.aarch64.neon.vmaxnm",
			"llvm.aarch64.neon.vmaxnmv",
			"llvm.aarch64.neon.vmaxv",
			"llvm.aarch64.neon.vminnm",
			"llvm.aarch64.neon.vminnmv",
			"llvm.aarch64.neon.vminv",
			"llvm.aarch64.neon.vmulx",
			"llvm.aarch64.neon.vneg",
			"llvm.aarch64.neon.vpadd",
			"llvm.aarch64.neon.vpfadd",
			"llvm.aarch64.neon.vpfaddq",
			"llvm.aarch64.neon.vpfmaxnm",
			"llvm.aarch64.neon.vpfmaxnmq",
			"llvm.aarch64.neon.vpfminnm",
			"llvm.aarch64.neon.vpfminnmq",
			"llvm.aarch64.neon.vpmax",
			"llvm.aarch64.neon.vpmaxnm",
			"llvm.aarch64.neon.vpmaxq",
			"llvm.aarch64.neon.vpmin",
			"llvm.aarch64.neon.vpminnm",
			"llvm.aarch64.neon.vpminq",
			"llvm.aarch64.neon.vqdmlal",
			"llvm.aarch64.neon.vqdmlsl",
			"llvm.aarch64.neon.vqrshls",
			"llvm.aarch64.neon.vqrshlu",
			"llvm.aarch64.neon.vqshls",
			"llvm.aarch64.neon.vqshls.n",
			"llvm.aarch64.neon.vqshlu",
			"llvm.aarch64.neon.vqshlu.n",
			"llvm.aarch64.neon.vqshlus.n",
			"llvm.aarch64.neon.vrecpx",
			"llvm.aarch64.neon.vrshlds",
			"llvm.aarch64.neon.vrshldu",
			"llvm.aarch64.neon.vrshrn",
			"llvm.aarch64.neon.vrsrads.n",
			"llvm.aarch64.neon.vrsradu.n",
			"llvm.aarch64.neon.vshld.n",
			"llvm.aarch64.neon.vshlds",
			"llvm.aarch64.neon.vshldu",
			"llvm.aarch64.neon.vshrds.n",
			"llvm.aarch64.neon.vshrdu.n",
			"llvm.aarch64.neon.vsli",
			"llvm.aarch64.neon.vsqadd",
			"llvm.aarch64.neon.vsqrshrn",
			"llvm.aarch64.neon.vsqrshrun",
			"llvm.aarch64.neon.vsqshlu",
			"llvm.aarch64.neon.vsqshrn",
			"llvm.aarch64.neon.vsqshrun",
			"llvm.aarch64.neon.vsrads.n",
			"llvm.aarch64.neon.vsradu.n",
			"llvm.aarch64.neon.vsri",
			"llvm.aarch64.neon.vsrshr",
			"llvm.aarch64.neon.vst1x2",
			"llvm.aarch64.neon.vst1x3",
			"llvm.aarch64.neon.vst1x4",
			"llvm.aarch64.neon.vsubds",
			"llvm.aarch64.neon.vsubdu",
			"llvm.aarch64.neon.vtbl1",
			"llvm.aarch64.neon.vtbl2",
			"llvm.aarch64.neon.vtbl3",
			"llvm.aarch64.neon.vtbl4",
			"llvm.aarch64.neon.vtbx1",
			"llvm.aarch64.neon.vtbx2",
			"llvm.aarch64.neon.vtbx3",
			"llvm.aarch64.neon.vtbx4",
			"llvm.aarch64.neon.vtstd",
			"llvm.aarch64.neon.vuqadd",
			"llvm.aarch64.neon.vuqrshrn",
			"llvm.aarch64.neon.vuqshrn",
			"llvm.aarch64.neon.vurshr",
			"llvm.aarch64.neon.xtn",
	"llvm.adjust.trampoline",		"llvm.adjust.trampoline",
	"llvm.annotation",		"llvm.annotation",
	"llvm.arm.cdp",		"llvm.arm.cdp",
	"llvm.arm.cdp2",		"llvm.arm.cdp2",
			"llvm.arm.clrex",
			"llvm.arm.crc32b",
			"llvm.arm.crc32cb",
			"llvm.arm.crc32ch",
			"llvm.arm.crc32cw",
			"llvm.arm.crc32h",
			"llvm.arm.crc32w",
			"llvm.arm.dmb",
			"llvm.arm.dsb",
	"llvm.arm.get.fpscr",		"llvm.arm.get.fpscr",
			"llvm.arm.ldrex",
	"llvm.arm.ldrexd",		"llvm.arm.ldrexd",
	"llvm.arm.mcr",		"llvm.arm.mcr",
	"llvm.arm.mcr2",		"llvm.arm.mcr2",
	"llvm.arm.mcrr",		"llvm.arm.mcrr",
	"llvm.arm.mcrr2",		"llvm.arm.mcrr2",
	"llvm.arm.mrc",		"llvm.arm.mrc",
	"llvm.arm.mrc2",		"llvm.arm.mrc2",
			"llvm.arm.neon.aesd",
			"llvm.arm.neon.aese",
			"llvm.arm.neon.aesimc",
			"llvm.arm.neon.aesmc",
			"llvm.arm.neon.sha1c",
			"llvm.arm.neon.sha1h",
			"llvm.arm.neon.sha1m",
			"llvm.arm.neon.sha1p",
			"llvm.arm.neon.sha1su0",
			"llvm.arm.neon.sha1su1",
			"llvm.arm.neon.sha256h",
			"llvm.arm.neon.sha256h2",
			"llvm.arm.neon.sha256su0",
			"llvm.arm.neon.sha256su1",
	"llvm.arm.neon.vabds",		"llvm.arm.neon.vabds",
	"llvm.arm.neon.vabdu",		"llvm.arm.neon.vabdu",
	"llvm.arm.neon.vabs",		"llvm.arm.neon.vabs",
	"llvm.arm.neon.vacged",		"llvm.arm.neon.vacged",
	"llvm.arm.neon.vacgeq",		"llvm.arm.neon.vacgeq",
	"llvm.arm.neon.vacgtd",		"llvm.arm.neon.vacgtd",
	"llvm.arm.neon.vacgtq",		"llvm.arm.neon.vacgtq",
	"llvm.arm.neon.vaddhn",
	"llvm.arm.neon.vbsl",		"llvm.arm.neon.vbsl",
	"llvm.arm.neon.vcls",		"llvm.arm.neon.vcls",
	"llvm.arm.neon.vclz",		"llvm.arm.neon.vclz",
	"llvm.arm.neon.vcnt",		"llvm.arm.neon.vcnt",
			"llvm.arm.neon.vcvtas",
			"llvm.arm.neon.vcvtau",
	"llvm.arm.neon.vcvtfp2fxs",		"llvm.arm.neon.vcvtfp2fxs",
	"llvm.arm.neon.vcvtfp2fxu",		"llvm.arm.neon.vcvtfp2fxu",
	"llvm.arm.neon.vcvtfp2hf",		"llvm.arm.neon.vcvtfp2hf",
	"llvm.arm.neon.vcvtfxs2fp",		"llvm.arm.neon.vcvtfxs2fp",
	"llvm.arm.neon.vcvtfxu2fp",		"llvm.arm.neon.vcvtfxu2fp",
	"llvm.arm.neon.vcvthf2fp",		"llvm.arm.neon.vcvthf2fp",
			"llvm.arm.neon.vcvtms",
			"llvm.arm.neon.vcvtmu",
			"llvm.arm.neon.vcvtns",
			"llvm.arm.neon.vcvtnu",
			"llvm.arm.neon.vcvtps",
			"llvm.arm.neon.vcvtpu",
	"llvm.arm.neon.vhadds",		"llvm.arm.neon.vhadds",
	"llvm.arm.neon.vhaddu",		"llvm.arm.neon.vhaddu",
	"llvm.arm.neon.vhsubs",		"llvm.arm.neon.vhsubs",
	"llvm.arm.neon.vhsubu",		"llvm.arm.neon.vhsubu",
	"llvm.arm.neon.vld1",		"llvm.arm.neon.vld1",
	"llvm.arm.neon.vld2",		"llvm.arm.neon.vld2",
	"llvm.arm.neon.vld2lane",		"llvm.arm.neon.vld2lane",
	"llvm.arm.neon.vld3",		"llvm.arm.neon.vld3",
	"llvm.arm.neon.vld3lane",		"llvm.arm.neon.vld3lane",
	"llvm.arm.neon.vld4",		"llvm.arm.neon.vld4",
	"llvm.arm.neon.vld4lane",		"llvm.arm.neon.vld4lane",
			"llvm.arm.neon.vmaxnm",
	"llvm.arm.neon.vmaxs",		"llvm.arm.neon.vmaxs",
	"llvm.arm.neon.vmaxu",		"llvm.arm.neon.vmaxu",
			"llvm.arm.neon.vminnm",
	"llvm.arm.neon.vmins",		"llvm.arm.neon.vmins",
	"llvm.arm.neon.vminu",		"llvm.arm.neon.vminu",
	"llvm.arm.neon.vmullp",		"llvm.arm.neon.vmullp",
	"llvm.arm.neon.vmulls",		"llvm.arm.neon.vmulls",
	"llvm.arm.neon.vmullu",		"llvm.arm.neon.vmullu",
	"llvm.arm.neon.vmulp",		"llvm.arm.neon.vmulp",
	"llvm.arm.neon.vpadals",		"llvm.arm.neon.vpadals",
	"llvm.arm.neon.vpadalu",		"llvm.arm.neon.vpadalu",
	"llvm.arm.neon.vpadd",		"llvm.arm.neon.vpadd",
	"llvm.arm.neon.vpaddls",		"llvm.arm.neon.vpaddls",
	"llvm.arm.neon.vpaddlu",		"llvm.arm.neon.vpaddlu",
	"llvm.arm.neon.vpmaxs",		"llvm.arm.neon.vpmaxs",
	"llvm.arm.neon.vpmaxu",		"llvm.arm.neon.vpmaxu",
	"llvm.arm.neon.vpmins",		"llvm.arm.neon.vpmins",
	"llvm.arm.neon.vpminu",		"llvm.arm.neon.vpminu",
	"llvm.arm.neon.vqabs",		"llvm.arm.neon.vqabs",
	"llvm.arm.neon.vqadds",		"llvm.arm.neon.vqadds",
	"llvm.arm.neon.vqaddu",		"llvm.arm.neon.vqaddu",
	"llvm.arm.neon.vqdmlal",
	"llvm.arm.neon.vqdmlsl",
	"llvm.arm.neon.vqdmulh",		"llvm.arm.neon.vqdmulh",
	"llvm.arm.neon.vqdmull",		"llvm.arm.neon.vqdmull",
	"llvm.arm.neon.vqmovns",		"llvm.arm.neon.vqmovns",
	"llvm.arm.neon.vqmovnsu",		"llvm.arm.neon.vqmovnsu",
	"llvm.arm.neon.vqmovnu",		"llvm.arm.neon.vqmovnu",
	"llvm.arm.neon.vqneg",		"llvm.arm.neon.vqneg",
	"llvm.arm.neon.vqrdmulh",		"llvm.arm.neon.vqrdmulh",
	"llvm.arm.neon.vqrshiftns",		"llvm.arm.neon.vqrshiftns",
	"llvm.arm.neon.vqrshiftnsu",		"llvm.arm.neon.vqrshiftnsu",
	"llvm.arm.neon.vqrshiftnu",		"llvm.arm.neon.vqrshiftnu",
	skipping to change at line 2544		skipping to change at line 3550
	"llvm.arm.neon.vqshifts",		"llvm.arm.neon.vqshifts",
	"llvm.arm.neon.vqshiftsu",		"llvm.arm.neon.vqshiftsu",
	"llvm.arm.neon.vqshiftu",		"llvm.arm.neon.vqshiftu",
	"llvm.arm.neon.vqsubs",		"llvm.arm.neon.vqsubs",
	"llvm.arm.neon.vqsubu",		"llvm.arm.neon.vqsubu",
	"llvm.arm.neon.vraddhn",		"llvm.arm.neon.vraddhn",
	"llvm.arm.neon.vrecpe",		"llvm.arm.neon.vrecpe",
	"llvm.arm.neon.vrecps",		"llvm.arm.neon.vrecps",
	"llvm.arm.neon.vrhadds",		"llvm.arm.neon.vrhadds",
	"llvm.arm.neon.vrhaddu",		"llvm.arm.neon.vrhaddu",
			"llvm.arm.neon.vrinta",
			"llvm.arm.neon.vrintm",
			"llvm.arm.neon.vrintn",
			"llvm.arm.neon.vrintp",
			"llvm.arm.neon.vrintx",
			"llvm.arm.neon.vrintz",
	"llvm.arm.neon.vrshiftn",		"llvm.arm.neon.vrshiftn",
	"llvm.arm.neon.vrshifts",		"llvm.arm.neon.vrshifts",
	"llvm.arm.neon.vrshiftu",		"llvm.arm.neon.vrshiftu",
	"llvm.arm.neon.vrsqrte",		"llvm.arm.neon.vrsqrte",
	"llvm.arm.neon.vrsqrts",		"llvm.arm.neon.vrsqrts",
	"llvm.arm.neon.vrsubhn",		"llvm.arm.neon.vrsubhn",
	"llvm.arm.neon.vshiftins",		"llvm.arm.neon.vshiftins",
	"llvm.arm.neon.vshiftls",		"llvm.arm.neon.vshiftls",
	"llvm.arm.neon.vshiftlu",		"llvm.arm.neon.vshiftlu",
	"llvm.arm.neon.vshiftn",		"llvm.arm.neon.vshiftn",
	"llvm.arm.neon.vshifts",		"llvm.arm.neon.vshifts",
	"llvm.arm.neon.vshiftu",		"llvm.arm.neon.vshiftu",
	"llvm.arm.neon.vst1",		"llvm.arm.neon.vst1",
	"llvm.arm.neon.vst2",		"llvm.arm.neon.vst2",
	"llvm.arm.neon.vst2lane",		"llvm.arm.neon.vst2lane",
	"llvm.arm.neon.vst3",		"llvm.arm.neon.vst3",
	"llvm.arm.neon.vst3lane",		"llvm.arm.neon.vst3lane",
	"llvm.arm.neon.vst4",		"llvm.arm.neon.vst4",
	"llvm.arm.neon.vst4lane",		"llvm.arm.neon.vst4lane",
	"llvm.arm.neon.vsubhn",
	"llvm.arm.neon.vtbl1",		"llvm.arm.neon.vtbl1",
	"llvm.arm.neon.vtbl2",		"llvm.arm.neon.vtbl2",
	"llvm.arm.neon.vtbl3",		"llvm.arm.neon.vtbl3",
	"llvm.arm.neon.vtbl4",		"llvm.arm.neon.vtbl4",
	"llvm.arm.neon.vtbx1",		"llvm.arm.neon.vtbx1",
	"llvm.arm.neon.vtbx2",		"llvm.arm.neon.vtbx2",
	"llvm.arm.neon.vtbx3",		"llvm.arm.neon.vtbx3",
	"llvm.arm.neon.vtbx4",		"llvm.arm.neon.vtbx4",
	"llvm.arm.qadd",		"llvm.arm.qadd",
	"llvm.arm.qsub",		"llvm.arm.qsub",
	"llvm.arm.set.fpscr",		"llvm.arm.set.fpscr",
			"llvm.arm.sevl",
	"llvm.arm.ssat",		"llvm.arm.ssat",
			"llvm.arm.strex",
	"llvm.arm.strexd",		"llvm.arm.strexd",
	"llvm.arm.thread.pointer",		"llvm.arm.thread.pointer",
	"llvm.arm.usat",		"llvm.arm.usat",
	"llvm.arm.vcvtr",		"llvm.arm.vcvtr",
	"llvm.arm.vcvtru",		"llvm.arm.vcvtru",
	"llvm.bswap",		"llvm.bswap",
	"llvm.ceil",		"llvm.ceil",
	"llvm.convert.from.fp16",		"llvm.convert.from.fp16",
	"llvm.convert.to.fp16",		"llvm.convert.to.fp16",
	"llvm.convertff",		"llvm.convertff",
	"llvm.convertfsi",		"llvm.convertfsi",
	"llvm.convertfui",		"llvm.convertfui",
	"llvm.convertsif",		"llvm.convertsif",
	"llvm.convertss",		"llvm.convertss",
	"llvm.convertsu",		"llvm.convertsu",
	"llvm.convertuif",		"llvm.convertuif",
	"llvm.convertus",		"llvm.convertus",
	"llvm.convertuu",		"llvm.convertuu",
			"llvm.copysign",
	"llvm.cos",		"llvm.cos",
	"llvm.ctlz",		"llvm.ctlz",
	"llvm.ctpop",		"llvm.ctpop",
	"llvm.cttz",		"llvm.cttz",
	"llvm.cuda.syncthreads",		"llvm.cuda.syncthreads",
	"llvm.dbg.declare",		"llvm.dbg.declare",
	"llvm.dbg.value",		"llvm.dbg.value",
	"llvm.debugtrap",		"llvm.debugtrap",
	"llvm.donothing",		"llvm.donothing",
	"llvm.eh.dwarf.cfa",		"llvm.eh.dwarf.cfa",
	skipping to change at line 2616		skipping to change at line 3630
	"llvm.eh.sjlj.callsite",		"llvm.eh.sjlj.callsite",
	"llvm.eh.sjlj.functioncontext",		"llvm.eh.sjlj.functioncontext",
	"llvm.eh.sjlj.longjmp",		"llvm.eh.sjlj.longjmp",
	"llvm.eh.sjlj.lsda",		"llvm.eh.sjlj.lsda",
	"llvm.eh.sjlj.setjmp",		"llvm.eh.sjlj.setjmp",
	"llvm.eh.typeid.for",		"llvm.eh.typeid.for",
	"llvm.eh.unwind.init",		"llvm.eh.unwind.init",
	"llvm.exp",		"llvm.exp",
	"llvm.exp2",		"llvm.exp2",
	"llvm.expect",		"llvm.expect",
			"llvm.experimental.patchpoint.i64",
			"llvm.experimental.patchpoint.void",
			"llvm.experimental.stackmap",
	"llvm.fabs",		"llvm.fabs",
	"llvm.floor",		"llvm.floor",
	"llvm.flt.rounds",		"llvm.flt.rounds",
	"llvm.fma",		"llvm.fma",
	"llvm.fmuladd",		"llvm.fmuladd",
	"llvm.frameaddress",		"llvm.frameaddress",
	"llvm.gcread",		"llvm.gcread",
	"llvm.gcroot",		"llvm.gcroot",
	"llvm.gcwrite",		"llvm.gcwrite",
	"llvm.hexagon.A2.abs",		"llvm.hexagon.A2.abs",
	skipping to change at line 3493		skipping to change at line 4510
	"llvm.log",		"llvm.log",
	"llvm.log10",		"llvm.log10",
	"llvm.log2",		"llvm.log2",
	"llvm.longjmp",		"llvm.longjmp",
	"llvm.memcpy",		"llvm.memcpy",
	"llvm.memmove",		"llvm.memmove",
	"llvm.memset",		"llvm.memset",
	"llvm.mips.absq.s.ph",		"llvm.mips.absq.s.ph",
	"llvm.mips.absq.s.qb",		"llvm.mips.absq.s.qb",
	"llvm.mips.absq.s.w",		"llvm.mips.absq.s.w",
			"llvm.mips.add.a.b",
			"llvm.mips.add.a.d",
			"llvm.mips.add.a.h",
			"llvm.mips.add.a.w",
	"llvm.mips.addq.ph",		"llvm.mips.addq.ph",
	"llvm.mips.addq.s.ph",		"llvm.mips.addq.s.ph",
	"llvm.mips.addq.s.w",		"llvm.mips.addq.s.w",
	"llvm.mips.addqh.ph",		"llvm.mips.addqh.ph",
	"llvm.mips.addqh.r.ph",		"llvm.mips.addqh.r.ph",
	"llvm.mips.addqh.r.w",		"llvm.mips.addqh.r.w",
	"llvm.mips.addqh.w",		"llvm.mips.addqh.w",
			"llvm.mips.adds.a.b",
			"llvm.mips.adds.a.d",
			"llvm.mips.adds.a.h",
			"llvm.mips.adds.a.w",
			"llvm.mips.adds.s.b",
			"llvm.mips.adds.s.d",
			"llvm.mips.adds.s.h",
			"llvm.mips.adds.s.w",
			"llvm.mips.adds.u.b",
			"llvm.mips.adds.u.d",
			"llvm.mips.adds.u.h",
			"llvm.mips.adds.u.w",
	"llvm.mips.addsc",		"llvm.mips.addsc",
	"llvm.mips.addu.ph",		"llvm.mips.addu.ph",
	"llvm.mips.addu.qb",		"llvm.mips.addu.qb",
	"llvm.mips.addu.s.ph",		"llvm.mips.addu.s.ph",
	"llvm.mips.addu.s.qb",		"llvm.mips.addu.s.qb",
	"llvm.mips.adduh.qb",		"llvm.mips.adduh.qb",
	"llvm.mips.adduh.r.qb",		"llvm.mips.adduh.r.qb",
			"llvm.mips.addv.b",
			"llvm.mips.addv.d",
			"llvm.mips.addv.h",
			"llvm.mips.addv.w",
			"llvm.mips.addvi.b",
			"llvm.mips.addvi.d",
			"llvm.mips.addvi.h",
			"llvm.mips.addvi.w",
	"llvm.mips.addwc",		"llvm.mips.addwc",
			"llvm.mips.and.v",
			"llvm.mips.andi.b",
	"llvm.mips.append",		"llvm.mips.append",
			"llvm.mips.asub.s.b",
			"llvm.mips.asub.s.d",
			"llvm.mips.asub.s.h",
			"llvm.mips.asub.s.w",
			"llvm.mips.asub.u.b",
			"llvm.mips.asub.u.d",
			"llvm.mips.asub.u.h",
			"llvm.mips.asub.u.w",
			"llvm.mips.ave.s.b",
			"llvm.mips.ave.s.d",
			"llvm.mips.ave.s.h",
			"llvm.mips.ave.s.w",
			"llvm.mips.ave.u.b",
			"llvm.mips.ave.u.d",
			"llvm.mips.ave.u.h",
			"llvm.mips.ave.u.w",
			"llvm.mips.aver.s.b",
			"llvm.mips.aver.s.d",
			"llvm.mips.aver.s.h",
			"llvm.mips.aver.s.w",
			"llvm.mips.aver.u.b",
			"llvm.mips.aver.u.d",
			"llvm.mips.aver.u.h",
			"llvm.mips.aver.u.w",
	"llvm.mips.balign",		"llvm.mips.balign",
			"llvm.mips.bclr.b",
			"llvm.mips.bclr.d",
			"llvm.mips.bclr.h",
			"llvm.mips.bclr.w",
			"llvm.mips.bclri.b",
			"llvm.mips.bclri.d",
			"llvm.mips.bclri.h",
			"llvm.mips.bclri.w",
			"llvm.mips.binsl.b",
			"llvm.mips.binsl.d",
			"llvm.mips.binsl.h",
			"llvm.mips.binsl.w",
			"llvm.mips.binsli.b",
			"llvm.mips.binsli.d",
			"llvm.mips.binsli.h",
			"llvm.mips.binsli.w",
			"llvm.mips.binsr.b",
			"llvm.mips.binsr.d",
			"llvm.mips.binsr.h",
			"llvm.mips.binsr.w",
			"llvm.mips.binsri.b",
			"llvm.mips.binsri.d",
			"llvm.mips.binsri.h",
			"llvm.mips.binsri.w",
	"llvm.mips.bitrev",		"llvm.mips.bitrev",
			"llvm.mips.bmnz.v",
			"llvm.mips.bmnzi.b",
			"llvm.mips.bmz.v",
			"llvm.mips.bmzi.b",
			"llvm.mips.bneg.b",
			"llvm.mips.bneg.d",
			"llvm.mips.bneg.h",
			"llvm.mips.bneg.w",
			"llvm.mips.bnegi.b",
			"llvm.mips.bnegi.d",
			"llvm.mips.bnegi.h",
			"llvm.mips.bnegi.w",
			"llvm.mips.bnz.b",
			"llvm.mips.bnz.d",
			"llvm.mips.bnz.h",
			"llvm.mips.bnz.v",
			"llvm.mips.bnz.w",
	"llvm.mips.bposge32",		"llvm.mips.bposge32",
			"llvm.mips.bsel.v",
			"llvm.mips.bseli.b",
			"llvm.mips.bset.b",
			"llvm.mips.bset.d",
			"llvm.mips.bset.h",
			"llvm.mips.bset.w",
			"llvm.mips.bseti.b",
			"llvm.mips.bseti.d",
			"llvm.mips.bseti.h",
			"llvm.mips.bseti.w",
			"llvm.mips.bz.b",
			"llvm.mips.bz.d",
			"llvm.mips.bz.h",
			"llvm.mips.bz.v",
			"llvm.mips.bz.w",
			"llvm.mips.ceq.b",
			"llvm.mips.ceq.d",
			"llvm.mips.ceq.h",
			"llvm.mips.ceq.w",
			"llvm.mips.ceqi.b",
			"llvm.mips.ceqi.d",
			"llvm.mips.ceqi.h",
			"llvm.mips.ceqi.w",
			"llvm.mips.cfcmsa",
			"llvm.mips.cle.s.b",
			"llvm.mips.cle.s.d",
			"llvm.mips.cle.s.h",
			"llvm.mips.cle.s.w",
			"llvm.mips.cle.u.b",
			"llvm.mips.cle.u.d",
			"llvm.mips.cle.u.h",
			"llvm.mips.cle.u.w",
			"llvm.mips.clei.s.b",
			"llvm.mips.clei.s.d",
			"llvm.mips.clei.s.h",
			"llvm.mips.clei.s.w",
			"llvm.mips.clei.u.b",
			"llvm.mips.clei.u.d",
			"llvm.mips.clei.u.h",
			"llvm.mips.clei.u.w",
			"llvm.mips.clt.s.b",
			"llvm.mips.clt.s.d",
			"llvm.mips.clt.s.h",
			"llvm.mips.clt.s.w",
			"llvm.mips.clt.u.b",
			"llvm.mips.clt.u.d",
			"llvm.mips.clt.u.h",
			"llvm.mips.clt.u.w",
			"llvm.mips.clti.s.b",
			"llvm.mips.clti.s.d",
			"llvm.mips.clti.s.h",
			"llvm.mips.clti.s.w",
			"llvm.mips.clti.u.b",
			"llvm.mips.clti.u.d",
			"llvm.mips.clti.u.h",
			"llvm.mips.clti.u.w",
	"llvm.mips.cmp.eq.ph",		"llvm.mips.cmp.eq.ph",
	"llvm.mips.cmp.le.ph",		"llvm.mips.cmp.le.ph",
	"llvm.mips.cmp.lt.ph",		"llvm.mips.cmp.lt.ph",
	"llvm.mips.cmpgdu.eq.qb",		"llvm.mips.cmpgdu.eq.qb",
	"llvm.mips.cmpgdu.le.qb",		"llvm.mips.cmpgdu.le.qb",
	"llvm.mips.cmpgdu.lt.qb",		"llvm.mips.cmpgdu.lt.qb",
	"llvm.mips.cmpgu.eq.qb",		"llvm.mips.cmpgu.eq.qb",
	"llvm.mips.cmpgu.le.qb",		"llvm.mips.cmpgu.le.qb",
	"llvm.mips.cmpgu.lt.qb",		"llvm.mips.cmpgu.lt.qb",
	"llvm.mips.cmpu.eq.qb",		"llvm.mips.cmpu.eq.qb",
	"llvm.mips.cmpu.le.qb",		"llvm.mips.cmpu.le.qb",
	"llvm.mips.cmpu.lt.qb",		"llvm.mips.cmpu.lt.qb",
			"llvm.mips.copy.s.b",
			"llvm.mips.copy.s.d",
			"llvm.mips.copy.s.h",
			"llvm.mips.copy.s.w",
			"llvm.mips.copy.u.b",
			"llvm.mips.copy.u.d",
			"llvm.mips.copy.u.h",
			"llvm.mips.copy.u.w",
			"llvm.mips.ctcmsa",
			"llvm.mips.div.s.b",
			"llvm.mips.div.s.d",
			"llvm.mips.div.s.h",
			"llvm.mips.div.s.w",
			"llvm.mips.div.u.b",
			"llvm.mips.div.u.d",
			"llvm.mips.div.u.h",
			"llvm.mips.div.u.w",
			"llvm.mips.dotp.s.d",
			"llvm.mips.dotp.s.h",
			"llvm.mips.dotp.s.w",
			"llvm.mips.dotp.u.d",
			"llvm.mips.dotp.u.h",
			"llvm.mips.dotp.u.w",
	"llvm.mips.dpa.w.ph",		"llvm.mips.dpa.w.ph",
			"llvm.mips.dpadd.s.d",
			"llvm.mips.dpadd.s.h",
			"llvm.mips.dpadd.s.w",
			"llvm.mips.dpadd.u.d",
			"llvm.mips.dpadd.u.h",
			"llvm.mips.dpadd.u.w",
	"llvm.mips.dpaq.s.w.ph",		"llvm.mips.dpaq.s.w.ph",
	"llvm.mips.dpaq.sa.l.w",		"llvm.mips.dpaq.sa.l.w",
	"llvm.mips.dpaqx.s.w.ph",		"llvm.mips.dpaqx.s.w.ph",
	"llvm.mips.dpaqx.sa.w.ph",		"llvm.mips.dpaqx.sa.w.ph",
	"llvm.mips.dpau.h.qbl",		"llvm.mips.dpau.h.qbl",
	"llvm.mips.dpau.h.qbr",		"llvm.mips.dpau.h.qbr",
	"llvm.mips.dpax.w.ph",		"llvm.mips.dpax.w.ph",
	"llvm.mips.dps.w.ph",		"llvm.mips.dps.w.ph",
	"llvm.mips.dpsq.s.w.ph",		"llvm.mips.dpsq.s.w.ph",
	"llvm.mips.dpsq.sa.l.w",		"llvm.mips.dpsq.sa.l.w",
	"llvm.mips.dpsqx.s.w.ph",		"llvm.mips.dpsqx.s.w.ph",
	"llvm.mips.dpsqx.sa.w.ph",		"llvm.mips.dpsqx.sa.w.ph",
	"llvm.mips.dpsu.h.qbl",		"llvm.mips.dpsu.h.qbl",
	"llvm.mips.dpsu.h.qbr",		"llvm.mips.dpsu.h.qbr",
			"llvm.mips.dpsub.s.d",
			"llvm.mips.dpsub.s.h",
			"llvm.mips.dpsub.s.w",
			"llvm.mips.dpsub.u.d",
			"llvm.mips.dpsub.u.h",
			"llvm.mips.dpsub.u.w",
	"llvm.mips.dpsx.w.ph",		"llvm.mips.dpsx.w.ph",
	"llvm.mips.extp",		"llvm.mips.extp",
	"llvm.mips.extpdp",		"llvm.mips.extpdp",
	"llvm.mips.extr.r.w",		"llvm.mips.extr.r.w",
	"llvm.mips.extr.rs.w",		"llvm.mips.extr.rs.w",
	"llvm.mips.extr.s.h",		"llvm.mips.extr.s.h",
	"llvm.mips.extr.w",		"llvm.mips.extr.w",
			"llvm.mips.fadd.d",
			"llvm.mips.fadd.w",
			"llvm.mips.fcaf.d",
			"llvm.mips.fcaf.w",
			"llvm.mips.fceq.d",
			"llvm.mips.fceq.w",
			"llvm.mips.fclass.d",
			"llvm.mips.fclass.w",
			"llvm.mips.fcle.d",
			"llvm.mips.fcle.w",
			"llvm.mips.fclt.d",
			"llvm.mips.fclt.w",
			"llvm.mips.fcne.d",
			"llvm.mips.fcne.w",
			"llvm.mips.fcor.d",
			"llvm.mips.fcor.w",
			"llvm.mips.fcueq.d",
			"llvm.mips.fcueq.w",
			"llvm.mips.fcule.d",
			"llvm.mips.fcule.w",
			"llvm.mips.fcult.d",
			"llvm.mips.fcult.w",
			"llvm.mips.fcun.d",
			"llvm.mips.fcun.w",
			"llvm.mips.fcune.d",
			"llvm.mips.fcune.w",
			"llvm.mips.fdiv.d",
			"llvm.mips.fdiv.w",
			"llvm.mips.fexdo.h",
			"llvm.mips.fexdo.w",
			"llvm.mips.fexp2.d",
			"llvm.mips.fexp2.w",
			"llvm.mips.fexupl.d",
			"llvm.mips.fexupl.w",
			"llvm.mips.fexupr.d",
			"llvm.mips.fexupr.w",
			"llvm.mips.ffint.s.d",
			"llvm.mips.ffint.s.w",
			"llvm.mips.ffint.u.d",
			"llvm.mips.ffint.u.w",
			"llvm.mips.ffql.d",
			"llvm.mips.ffql.w",
			"llvm.mips.ffqr.d",
			"llvm.mips.ffqr.w",
			"llvm.mips.fill.b",
			"llvm.mips.fill.d",
			"llvm.mips.fill.h",
			"llvm.mips.fill.w",
			"llvm.mips.flog2.d",
			"llvm.mips.flog2.w",
			"llvm.mips.fmadd.d",
			"llvm.mips.fmadd.w",
			"llvm.mips.fmax.a.d",
			"llvm.mips.fmax.a.w",
			"llvm.mips.fmax.d",
			"llvm.mips.fmax.w",
			"llvm.mips.fmin.a.d",
			"llvm.mips.fmin.a.w",
			"llvm.mips.fmin.d",
			"llvm.mips.fmin.w",
			"llvm.mips.fmsub.d",
			"llvm.mips.fmsub.w",
			"llvm.mips.fmul.d",
			"llvm.mips.fmul.w",
			"llvm.mips.frcp.d",
			"llvm.mips.frcp.w",
			"llvm.mips.frint.d",
			"llvm.mips.frint.w",
			"llvm.mips.frsqrt.d",
			"llvm.mips.frsqrt.w",
			"llvm.mips.fsaf.d",
			"llvm.mips.fsaf.w",
			"llvm.mips.fseq.d",
			"llvm.mips.fseq.w",
			"llvm.mips.fsle.d",
			"llvm.mips.fsle.w",
			"llvm.mips.fslt.d",
			"llvm.mips.fslt.w",
			"llvm.mips.fsne.d",
			"llvm.mips.fsne.w",
			"llvm.mips.fsor.d",
			"llvm.mips.fsor.w",
			"llvm.mips.fsqrt.d",
			"llvm.mips.fsqrt.w",
			"llvm.mips.fsub.d",
			"llvm.mips.fsub.w",
			"llvm.mips.fsueq.d",
			"llvm.mips.fsueq.w",
			"llvm.mips.fsule.d",
			"llvm.mips.fsule.w",
			"llvm.mips.fsult.d",
			"llvm.mips.fsult.w",
			"llvm.mips.fsun.d",
			"llvm.mips.fsun.w",
			"llvm.mips.fsune.d",
			"llvm.mips.fsune.w",
			"llvm.mips.ftint.s.d",
			"llvm.mips.ftint.s.w",
			"llvm.mips.ftint.u.d",
			"llvm.mips.ftint.u.w",
			"llvm.mips.ftq.h",
			"llvm.mips.ftq.w",
			"llvm.mips.ftrunc.s.d",
			"llvm.mips.ftrunc.s.w",
			"llvm.mips.ftrunc.u.d",
			"llvm.mips.ftrunc.u.w",
			"llvm.mips.hadd.s.d",
			"llvm.mips.hadd.s.h",
			"llvm.mips.hadd.s.w",
			"llvm.mips.hadd.u.d",
			"llvm.mips.hadd.u.h",
			"llvm.mips.hadd.u.w",
			"llvm.mips.hsub.s.d",
			"llvm.mips.hsub.s.h",
			"llvm.mips.hsub.s.w",
			"llvm.mips.hsub.u.d",
			"llvm.mips.hsub.u.h",
			"llvm.mips.hsub.u.w",
			"llvm.mips.ilvev.b",
			"llvm.mips.ilvev.d",
			"llvm.mips.ilvev.h",
			"llvm.mips.ilvev.w",
			"llvm.mips.ilvl.b",
			"llvm.mips.ilvl.d",
			"llvm.mips.ilvl.h",
			"llvm.mips.ilvl.w",
			"llvm.mips.ilvod.b",
			"llvm.mips.ilvod.d",
			"llvm.mips.ilvod.h",
			"llvm.mips.ilvod.w",
			"llvm.mips.ilvr.b",
			"llvm.mips.ilvr.d",
			"llvm.mips.ilvr.h",
			"llvm.mips.ilvr.w",
			"llvm.mips.insert.b",
			"llvm.mips.insert.d",
			"llvm.mips.insert.h",
			"llvm.mips.insert.w",
	"llvm.mips.insv",		"llvm.mips.insv",
			"llvm.mips.insve.b",
			"llvm.mips.insve.d",
			"llvm.mips.insve.h",
			"llvm.mips.insve.w",
	"llvm.mips.lbux",		"llvm.mips.lbux",
			"llvm.mips.ld.b",
			"llvm.mips.ld.d",
			"llvm.mips.ld.h",
			"llvm.mips.ld.w",
			"llvm.mips.ldi.b",
			"llvm.mips.ldi.d",
			"llvm.mips.ldi.h",
			"llvm.mips.ldi.w",
	"llvm.mips.lhx",		"llvm.mips.lhx",
			"llvm.mips.lsa",
	"llvm.mips.lwx",		"llvm.mips.lwx",
	"llvm.mips.madd",		"llvm.mips.madd",
			"llvm.mips.madd.q.h",
			"llvm.mips.madd.q.w",
			"llvm.mips.maddr.q.h",
			"llvm.mips.maddr.q.w",
	"llvm.mips.maddu",		"llvm.mips.maddu",
			"llvm.mips.maddv.b",
			"llvm.mips.maddv.d",
			"llvm.mips.maddv.h",
			"llvm.mips.maddv.w",
	"llvm.mips.maq.s.w.phl",		"llvm.mips.maq.s.w.phl",
	"llvm.mips.maq.s.w.phr",		"llvm.mips.maq.s.w.phr",
	"llvm.mips.maq.sa.w.phl",		"llvm.mips.maq.sa.w.phl",
	"llvm.mips.maq.sa.w.phr",		"llvm.mips.maq.sa.w.phr",
			"llvm.mips.max.a.b",
			"llvm.mips.max.a.d",
			"llvm.mips.max.a.h",
			"llvm.mips.max.a.w",
			"llvm.mips.max.s.b",
			"llvm.mips.max.s.d",
			"llvm.mips.max.s.h",
			"llvm.mips.max.s.w",
			"llvm.mips.max.u.b",
			"llvm.mips.max.u.d",
			"llvm.mips.max.u.h",
			"llvm.mips.max.u.w",
			"llvm.mips.maxi.s.b",
			"llvm.mips.maxi.s.d",
			"llvm.mips.maxi.s.h",
			"llvm.mips.maxi.s.w",
			"llvm.mips.maxi.u.b",
			"llvm.mips.maxi.u.d",
			"llvm.mips.maxi.u.h",
			"llvm.mips.maxi.u.w",
			"llvm.mips.min.a.b",
			"llvm.mips.min.a.d",
			"llvm.mips.min.a.h",
			"llvm.mips.min.a.w",
			"llvm.mips.min.s.b",
			"llvm.mips.min.s.d",
			"llvm.mips.min.s.h",
			"llvm.mips.min.s.w",
			"llvm.mips.min.u.b",
			"llvm.mips.min.u.d",
			"llvm.mips.min.u.h",
			"llvm.mips.min.u.w",
			"llvm.mips.mini.s.b",
			"llvm.mips.mini.s.d",
			"llvm.mips.mini.s.h",
			"llvm.mips.mini.s.w",
			"llvm.mips.mini.u.b",
			"llvm.mips.mini.u.d",
			"llvm.mips.mini.u.h",
			"llvm.mips.mini.u.w",
			"llvm.mips.mod.s.b",
			"llvm.mips.mod.s.d",
			"llvm.mips.mod.s.h",
			"llvm.mips.mod.s.w",
			"llvm.mips.mod.u.b",
			"llvm.mips.mod.u.d",
			"llvm.mips.mod.u.h",
			"llvm.mips.mod.u.w",
	"llvm.mips.modsub",		"llvm.mips.modsub",
			"llvm.mips.move.v",
	"llvm.mips.msub",		"llvm.mips.msub",
			"llvm.mips.msub.q.h",
			"llvm.mips.msub.q.w",
			"llvm.mips.msubr.q.h",
			"llvm.mips.msubr.q.w",
	"llvm.mips.msubu",		"llvm.mips.msubu",
			"llvm.mips.msubv.b",
			"llvm.mips.msubv.d",
			"llvm.mips.msubv.h",
			"llvm.mips.msubv.w",
	"llvm.mips.mthlip",		"llvm.mips.mthlip",
	"llvm.mips.mul.ph",		"llvm.mips.mul.ph",
			"llvm.mips.mul.q.h",
			"llvm.mips.mul.q.w",
	"llvm.mips.mul.s.ph",		"llvm.mips.mul.s.ph",
	"llvm.mips.muleq.s.w.phl",		"llvm.mips.muleq.s.w.phl",
	"llvm.mips.muleq.s.w.phr",		"llvm.mips.muleq.s.w.phr",
	"llvm.mips.muleu.s.ph.qbl",		"llvm.mips.muleu.s.ph.qbl",
	"llvm.mips.muleu.s.ph.qbr",		"llvm.mips.muleu.s.ph.qbr",
	"llvm.mips.mulq.rs.ph",		"llvm.mips.mulq.rs.ph",
	"llvm.mips.mulq.rs.w",		"llvm.mips.mulq.rs.w",
	"llvm.mips.mulq.s.ph",		"llvm.mips.mulq.s.ph",
	"llvm.mips.mulq.s.w",		"llvm.mips.mulq.s.w",
			"llvm.mips.mulr.q.h",
			"llvm.mips.mulr.q.w",
	"llvm.mips.mulsa.w.ph",		"llvm.mips.mulsa.w.ph",
	"llvm.mips.mulsaq.s.w.ph",		"llvm.mips.mulsaq.s.w.ph",
	"llvm.mips.mult",		"llvm.mips.mult",
	"llvm.mips.multu",		"llvm.mips.multu",
			"llvm.mips.mulv.b",
			"llvm.mips.mulv.d",
			"llvm.mips.mulv.h",
			"llvm.mips.mulv.w",
			"llvm.mips.nloc.b",
			"llvm.mips.nloc.d",
			"llvm.mips.nloc.h",
			"llvm.mips.nloc.w",
			"llvm.mips.nlzc.b",
			"llvm.mips.nlzc.d",
			"llvm.mips.nlzc.h",
			"llvm.mips.nlzc.w",
			"llvm.mips.nor.v",
			"llvm.mips.nori.b",
			"llvm.mips.or.v",
			"llvm.mips.ori.b",
	"llvm.mips.packrl.ph",		"llvm.mips.packrl.ph",
			"llvm.mips.pckev.b",
			"llvm.mips.pckev.d",
			"llvm.mips.pckev.h",
			"llvm.mips.pckev.w",
			"llvm.mips.pckod.b",
			"llvm.mips.pckod.d",
			"llvm.mips.pckod.h",
			"llvm.mips.pckod.w",
			"llvm.mips.pcnt.b",
			"llvm.mips.pcnt.d",
			"llvm.mips.pcnt.h",
			"llvm.mips.pcnt.w",
	"llvm.mips.pick.ph",		"llvm.mips.pick.ph",
	"llvm.mips.pick.qb",		"llvm.mips.pick.qb",
	"llvm.mips.preceq.w.phl",		"llvm.mips.preceq.w.phl",
	"llvm.mips.preceq.w.phr",		"llvm.mips.preceq.w.phr",
	"llvm.mips.precequ.ph.qbl",		"llvm.mips.precequ.ph.qbl",
	"llvm.mips.precequ.ph.qbla",		"llvm.mips.precequ.ph.qbla",
	"llvm.mips.precequ.ph.qbr",		"llvm.mips.precequ.ph.qbr",
	"llvm.mips.precequ.ph.qbra",		"llvm.mips.precequ.ph.qbra",
	"llvm.mips.preceu.ph.qbl",		"llvm.mips.preceu.ph.qbl",
	"llvm.mips.preceu.ph.qbla",		"llvm.mips.preceu.ph.qbla",
	skipping to change at line 3599		skipping to change at line 5046
	"llvm.mips.precr.sra.r.ph.w",		"llvm.mips.precr.sra.r.ph.w",
	"llvm.mips.precrq.ph.w",		"llvm.mips.precrq.ph.w",
	"llvm.mips.precrq.qb.ph",		"llvm.mips.precrq.qb.ph",
	"llvm.mips.precrq.rs.ph.w",		"llvm.mips.precrq.rs.ph.w",
	"llvm.mips.precrqu.s.qb.ph",		"llvm.mips.precrqu.s.qb.ph",
	"llvm.mips.prepend",		"llvm.mips.prepend",
	"llvm.mips.raddu.w.qb",		"llvm.mips.raddu.w.qb",
	"llvm.mips.rddsp",		"llvm.mips.rddsp",
	"llvm.mips.repl.ph",		"llvm.mips.repl.ph",
	"llvm.mips.repl.qb",		"llvm.mips.repl.qb",
			"llvm.mips.sat.s.b",
			"llvm.mips.sat.s.d",
			"llvm.mips.sat.s.h",
			"llvm.mips.sat.s.w",
			"llvm.mips.sat.u.b",
			"llvm.mips.sat.u.d",
			"llvm.mips.sat.u.h",
			"llvm.mips.sat.u.w",
			"llvm.mips.shf.b",
			"llvm.mips.shf.h",
			"llvm.mips.shf.w",
	"llvm.mips.shilo",		"llvm.mips.shilo",
	"llvm.mips.shll.ph",		"llvm.mips.shll.ph",
	"llvm.mips.shll.qb",		"llvm.mips.shll.qb",
	"llvm.mips.shll.s.ph",		"llvm.mips.shll.s.ph",
	"llvm.mips.shll.s.w",		"llvm.mips.shll.s.w",
	"llvm.mips.shra.ph",		"llvm.mips.shra.ph",
	"llvm.mips.shra.qb",		"llvm.mips.shra.qb",
	"llvm.mips.shra.r.ph",		"llvm.mips.shra.r.ph",
	"llvm.mips.shra.r.qb",		"llvm.mips.shra.r.qb",
	"llvm.mips.shra.r.w",		"llvm.mips.shra.r.w",
	"llvm.mips.shrl.ph",		"llvm.mips.shrl.ph",
	"llvm.mips.shrl.qb",		"llvm.mips.shrl.qb",
			"llvm.mips.sld.b",
			"llvm.mips.sld.d",
			"llvm.mips.sld.h",
			"llvm.mips.sld.w",
			"llvm.mips.sldi.b",
			"llvm.mips.sldi.d",
			"llvm.mips.sldi.h",
			"llvm.mips.sldi.w",
			"llvm.mips.sll.b",
			"llvm.mips.sll.d",
			"llvm.mips.sll.h",
			"llvm.mips.sll.w",
			"llvm.mips.slli.b",
			"llvm.mips.slli.d",
			"llvm.mips.slli.h",
			"llvm.mips.slli.w",
			"llvm.mips.splat.b",
			"llvm.mips.splat.d",
			"llvm.mips.splat.h",
			"llvm.mips.splat.w",
			"llvm.mips.splati.b",
			"llvm.mips.splati.d",
			"llvm.mips.splati.h",
			"llvm.mips.splati.w",
			"llvm.mips.sra.b",
			"llvm.mips.sra.d",
			"llvm.mips.sra.h",
			"llvm.mips.sra.w",
			"llvm.mips.srai.b",
			"llvm.mips.srai.d",
			"llvm.mips.srai.h",
			"llvm.mips.srai.w",
			"llvm.mips.srar.b",
			"llvm.mips.srar.d",
			"llvm.mips.srar.h",
			"llvm.mips.srar.w",
			"llvm.mips.srari.b",
			"llvm.mips.srari.d",
			"llvm.mips.srari.h",
			"llvm.mips.srari.w",
			"llvm.mips.srl.b",
			"llvm.mips.srl.d",
			"llvm.mips.srl.h",
			"llvm.mips.srl.w",
			"llvm.mips.srli.b",
			"llvm.mips.srli.d",
			"llvm.mips.srli.h",
			"llvm.mips.srli.w",
			"llvm.mips.srlr.b",
			"llvm.mips.srlr.d",
			"llvm.mips.srlr.h",
			"llvm.mips.srlr.w",
			"llvm.mips.srlri.b",
			"llvm.mips.srlri.d",
			"llvm.mips.srlri.h",
			"llvm.mips.srlri.w",
			"llvm.mips.st.b",
			"llvm.mips.st.d",
			"llvm.mips.st.h",
			"llvm.mips.st.w",
	"llvm.mips.subq.ph",		"llvm.mips.subq.ph",
	"llvm.mips.subq.s.ph",		"llvm.mips.subq.s.ph",
	"llvm.mips.subq.s.w",		"llvm.mips.subq.s.w",
	"llvm.mips.subqh.ph",		"llvm.mips.subqh.ph",
	"llvm.mips.subqh.r.ph",		"llvm.mips.subqh.r.ph",
	"llvm.mips.subqh.r.w",		"llvm.mips.subqh.r.w",
	"llvm.mips.subqh.w",		"llvm.mips.subqh.w",
			"llvm.mips.subs.s.b",
			"llvm.mips.subs.s.d",
			"llvm.mips.subs.s.h",
			"llvm.mips.subs.s.w",
			"llvm.mips.subs.u.b",
			"llvm.mips.subs.u.d",
			"llvm.mips.subs.u.h",
			"llvm.mips.subs.u.w",
			"llvm.mips.subsus.u.b",
			"llvm.mips.subsus.u.d",
			"llvm.mips.subsus.u.h",
			"llvm.mips.subsus.u.w",
			"llvm.mips.subsuu.s.b",
			"llvm.mips.subsuu.s.d",
			"llvm.mips.subsuu.s.h",
			"llvm.mips.subsuu.s.w",
	"llvm.mips.subu.ph",		"llvm.mips.subu.ph",
	"llvm.mips.subu.qb",		"llvm.mips.subu.qb",
	"llvm.mips.subu.s.ph",		"llvm.mips.subu.s.ph",
	"llvm.mips.subu.s.qb",		"llvm.mips.subu.s.qb",
	"llvm.mips.subuh.qb",		"llvm.mips.subuh.qb",
	"llvm.mips.subuh.r.qb",		"llvm.mips.subuh.r.qb",
			"llvm.mips.subv.b",
			"llvm.mips.subv.d",
			"llvm.mips.subv.h",
			"llvm.mips.subv.w",
			"llvm.mips.subvi.b",
			"llvm.mips.subvi.d",
			"llvm.mips.subvi.h",
			"llvm.mips.subvi.w",
			"llvm.mips.vshf.b",
			"llvm.mips.vshf.d",
			"llvm.mips.vshf.h",
			"llvm.mips.vshf.w",
	"llvm.mips.wrdsp",		"llvm.mips.wrdsp",
			"llvm.mips.xor.v",
			"llvm.mips.xori.b",
	"llvm.nearbyint",		"llvm.nearbyint",
	"llvm.nvvm.abs.i",		"llvm.nvvm.abs.i",
	"llvm.nvvm.abs.ll",		"llvm.nvvm.abs.ll",
	"llvm.nvvm.add.rm.d",		"llvm.nvvm.add.rm.d",
	"llvm.nvvm.add.rm.f",		"llvm.nvvm.add.rm.f",
	"llvm.nvvm.add.rm.ftz.f",		"llvm.nvvm.add.rm.ftz.f",
	"llvm.nvvm.add.rn.d",		"llvm.nvvm.add.rn.d",
	"llvm.nvvm.add.rn.f",		"llvm.nvvm.add.rn.f",
	"llvm.nvvm.add.rn.ftz.f",		"llvm.nvvm.add.rn.ftz.f",
	"llvm.nvvm.add.rp.d",		"llvm.nvvm.add.rp.d",
	skipping to change at line 3806		skipping to change at line 5354
	"llvm.nvvm.membar.sys",		"llvm.nvvm.membar.sys",
	"llvm.nvvm.min.i",		"llvm.nvvm.min.i",
	"llvm.nvvm.min.ll",		"llvm.nvvm.min.ll",
	"llvm.nvvm.min.ui",		"llvm.nvvm.min.ui",
	"llvm.nvvm.min.ull",		"llvm.nvvm.min.ull",
	"llvm.nvvm.move.double",		"llvm.nvvm.move.double",
	"llvm.nvvm.move.float",		"llvm.nvvm.move.float",
	"llvm.nvvm.move.i16",		"llvm.nvvm.move.i16",
	"llvm.nvvm.move.i32",		"llvm.nvvm.move.i32",
	"llvm.nvvm.move.i64",		"llvm.nvvm.move.i64",
	"llvm.nvvm.move.i8",
	"llvm.nvvm.move.ptr",		"llvm.nvvm.move.ptr",
	"llvm.nvvm.mul24.i",		"llvm.nvvm.mul24.i",
	"llvm.nvvm.mul24.ui",		"llvm.nvvm.mul24.ui",
	"llvm.nvvm.mul.rm.d",		"llvm.nvvm.mul.rm.d",
	"llvm.nvvm.mul.rm.f",		"llvm.nvvm.mul.rm.f",
	"llvm.nvvm.mul.rm.ftz.f",		"llvm.nvvm.mul.rm.ftz.f",
	"llvm.nvvm.mul.rn.d",		"llvm.nvvm.mul.rn.d",
	"llvm.nvvm.mul.rn.f",		"llvm.nvvm.mul.rn.f",
	"llvm.nvvm.mul.rn.ftz.f",		"llvm.nvvm.mul.rn.ftz.f",
	"llvm.nvvm.mul.rp.d",		"llvm.nvvm.mul.rp.d",
	skipping to change at line 4070		skipping to change at line 5617
	"llvm.ppc.altivec.vupklsb",		"llvm.ppc.altivec.vupklsb",
	"llvm.ppc.altivec.vupklsh",		"llvm.ppc.altivec.vupklsh",
	"llvm.ppc.dcba",		"llvm.ppc.dcba",
	"llvm.ppc.dcbf",		"llvm.ppc.dcbf",
	"llvm.ppc.dcbi",		"llvm.ppc.dcbi",
	"llvm.ppc.dcbst",		"llvm.ppc.dcbst",
	"llvm.ppc.dcbt",		"llvm.ppc.dcbt",
	"llvm.ppc.dcbtst",		"llvm.ppc.dcbtst",
	"llvm.ppc.dcbz",		"llvm.ppc.dcbz",
	"llvm.ppc.dcbzl",		"llvm.ppc.dcbzl",
			"llvm.ppc.is.decremented.ctr.nonzero",
			"llvm.ppc.mtctr",
	"llvm.ppc.sync",		"llvm.ppc.sync",
	"llvm.prefetch",		"llvm.prefetch",
	"llvm.ptr.annotation",		"llvm.ptr.annotation",
	"llvm.ptx.bar.sync",		"llvm.ptx.bar.sync",
	"llvm.ptx.read.clock",		"llvm.ptx.read.clock",
	"llvm.ptx.read.clock64",		"llvm.ptx.read.clock64",
	"llvm.ptx.read.ctaid.w",		"llvm.ptx.read.ctaid.w",
	"llvm.ptx.read.ctaid.x",		"llvm.ptx.read.ctaid.x",
	"llvm.ptx.read.ctaid.y",		"llvm.ptx.read.ctaid.y",
	"llvm.ptx.read.ctaid.z",		"llvm.ptx.read.ctaid.z",
	skipping to change at line 4125		skipping to change at line 5674
	"llvm.r600.read.ngroups.z",		"llvm.r600.read.ngroups.z",
	"llvm.r600.read.tgid.x",		"llvm.r600.read.tgid.x",
	"llvm.r600.read.tgid.y",		"llvm.r600.read.tgid.y",
	"llvm.r600.read.tgid.z",		"llvm.r600.read.tgid.z",
	"llvm.r600.read.tidig.x",		"llvm.r600.read.tidig.x",
	"llvm.r600.read.tidig.y",		"llvm.r600.read.tidig.y",
	"llvm.r600.read.tidig.z",		"llvm.r600.read.tidig.z",
	"llvm.readcyclecounter",		"llvm.readcyclecounter",
	"llvm.returnaddress",		"llvm.returnaddress",
	"llvm.rint",		"llvm.rint",
			"llvm.round",
	"llvm.sadd.with.overflow",		"llvm.sadd.with.overflow",
	"llvm.setjmp",		"llvm.setjmp",
	"llvm.siglongjmp",		"llvm.siglongjmp",
	"llvm.sigsetjmp",		"llvm.sigsetjmp",
	"llvm.sin",		"llvm.sin",
	"llvm.smul.with.overflow",		"llvm.smul.with.overflow",
	"llvm.sqrt",		"llvm.sqrt",
	"llvm.ssub.with.overflow",		"llvm.ssub.with.overflow",
	"llvm.stackprotector",		"llvm.stackprotector",
			"llvm.stackprotectorcheck",
	"llvm.stackrestore",		"llvm.stackrestore",
	"llvm.stacksave",		"llvm.stacksave",
	"llvm.trap",		"llvm.trap",
	"llvm.trunc",		"llvm.trunc",
	"llvm.uadd.with.overflow",		"llvm.uadd.with.overflow",
	"llvm.umul.with.overflow",		"llvm.umul.with.overflow",
	"llvm.usub.with.overflow",		"llvm.usub.with.overflow",
	"llvm.va_copy",		"llvm.va_copy",
	"llvm.va_end",		"llvm.va_end",
	"llvm.var.annotation",		"llvm.var.annotation",
	skipping to change at line 4312		skipping to change at line 5863
	"llvm.x86.avx2.psubs.w",		"llvm.x86.avx2.psubs.w",
	"llvm.x86.avx2.psubus.b",		"llvm.x86.avx2.psubus.b",
	"llvm.x86.avx2.psubus.w",		"llvm.x86.avx2.psubus.w",
	"llvm.x86.avx2.vbroadcast.sd.pd.256",		"llvm.x86.avx2.vbroadcast.sd.pd.256",
	"llvm.x86.avx2.vbroadcast.ss.ps",		"llvm.x86.avx2.vbroadcast.ss.ps",
	"llvm.x86.avx2.vbroadcast.ss.ps.256",		"llvm.x86.avx2.vbroadcast.ss.ps.256",
	"llvm.x86.avx2.vbroadcasti128",		"llvm.x86.avx2.vbroadcasti128",
	"llvm.x86.avx2.vextracti128",		"llvm.x86.avx2.vextracti128",
	"llvm.x86.avx2.vinserti128",		"llvm.x86.avx2.vinserti128",
	"llvm.x86.avx2.vperm2i128",		"llvm.x86.avx2.vperm2i128",
			"llvm.x86.avx512.and.pi",
			"llvm.x86.avx512.cmpeq.pi.512",
			"llvm.x86.avx512.conflict.d.512",
			"llvm.x86.avx512.conflict.d.mask.512",
			"llvm.x86.avx512.conflict.d.maskz.512",
			"llvm.x86.avx512.conflict.q.512",
			"llvm.x86.avx512.conflict.q.mask.512",
			"llvm.x86.avx512.conflict.q.maskz.512",
			"llvm.x86.avx512.cvt.ps2dq.512",
			"llvm.x86.avx512.cvtdq2.ps.512",
			"llvm.x86.avx512.cvtsd2usi",
			"llvm.x86.avx512.cvtsd2usi64",
			"llvm.x86.avx512.cvtss2usi",
			"llvm.x86.avx512.cvtss2usi64",
			"llvm.x86.avx512.cvttsd2usi",
			"llvm.x86.avx512.cvttsd2usi64",
			"llvm.x86.avx512.cvttss2usi",
			"llvm.x86.avx512.cvttss2usi64",
			"llvm.x86.avx512.cvtusi2sd",
			"llvm.x86.avx512.cvtusi2ss",
			"llvm.x86.avx512.cvtusi642sd",
			"llvm.x86.avx512.cvtusi642ss",
			"llvm.x86.avx512.gather.dpd.512",
			"llvm.x86.avx512.gather.dpd.mask.512",
			"llvm.x86.avx512.gather.dpi.512",
			"llvm.x86.avx512.gather.dpi.mask.512",
			"llvm.x86.avx512.gather.dpq.512",
			"llvm.x86.avx512.gather.dpq.mask.512",
			"llvm.x86.avx512.gather.dps.512",
			"llvm.x86.avx512.gather.dps.mask.512",
			"llvm.x86.avx512.gather.qpd.512",
			"llvm.x86.avx512.gather.qpd.mask.512",
			"llvm.x86.avx512.gather.qpi.512",
			"llvm.x86.avx512.gather.qpi.mask.512",
			"llvm.x86.avx512.gather.qpq.512",
			"llvm.x86.avx512.gather.qpq.mask.512",
			"llvm.x86.avx512.gather.qps.512",
			"llvm.x86.avx512.gather.qps.mask.512",
			"llvm.x86.avx512.kortestc",
			"llvm.x86.avx512.kortestz",
			"llvm.x86.avx512.max.pd.512",
			"llvm.x86.avx512.max.ps.512",
			"llvm.x86.avx512.min.pd.512",
			"llvm.x86.avx512.min.ps.512",
			"llvm.x86.avx512.mskblend.d.512",
			"llvm.x86.avx512.mskblend.pd.512",
			"llvm.x86.avx512.mskblend.ps.512",
			"llvm.x86.avx512.mskblend.q.512",
			"llvm.x86.avx512.pbroadcastd.512",
			"llvm.x86.avx512.pbroadcastd.i32.512",
			"llvm.x86.avx512.pbroadcastq.512",
			"llvm.x86.avx512.pbroadcastq.i64.512",
			"llvm.x86.avx512.pmaxs.d",
			"llvm.x86.avx512.pmaxs.q",
			"llvm.x86.avx512.pmaxu.d",
			"llvm.x86.avx512.pmaxu.q",
			"llvm.x86.avx512.pmins.d",
			"llvm.x86.avx512.pmins.q",
			"llvm.x86.avx512.pminu.d",
			"llvm.x86.avx512.pminu.q",
			"llvm.x86.avx512.pmovzxbd",
			"llvm.x86.avx512.pmovzxbq",
			"llvm.x86.avx512.pmovzxdq",
			"llvm.x86.avx512.pmovzxwd",
			"llvm.x86.avx512.pmovzxwq",
			"llvm.x86.avx512.psll.dq",
			"llvm.x86.avx512.psll.dq.bs",
			"llvm.x86.avx512.psrl.dq",
			"llvm.x86.avx512.psrl.dq.bs",
			"llvm.x86.avx512.rcp14.pd.512",
			"llvm.x86.avx512.rcp14.ps.512",
			"llvm.x86.avx512.rcp14.sd",
			"llvm.x86.avx512.rcp14.ss",
			"llvm.x86.avx512.rcp28.pd.512",
			"llvm.x86.avx512.rcp28.ps.512",
			"llvm.x86.avx512.rcp28.sd",
			"llvm.x86.avx512.rcp28.ss",
			"llvm.x86.avx512.rndscale.pd.512",
			"llvm.x86.avx512.rndscale.ps.512",
			"llvm.x86.avx512.rndscale.sd",
			"llvm.x86.avx512.rndscale.ss",
			"llvm.x86.avx512.rsqrt14.pd.512",
			"llvm.x86.avx512.rsqrt14.ps.512",
			"llvm.x86.avx512.rsqrt14.sd",
			"llvm.x86.avx512.rsqrt14.ss",
			"llvm.x86.avx512.rsqrt28.pd.512",
			"llvm.x86.avx512.rsqrt28.ps.512",
			"llvm.x86.avx512.rsqrt28.sd",
			"llvm.x86.avx512.rsqrt28.ss",
			"llvm.x86.avx512.scatter.dpd.512",
			"llvm.x86.avx512.scatter.dpd.mask.512",
			"llvm.x86.avx512.scatter.dpi.512",
			"llvm.x86.avx512.scatter.dpi.mask.512",
			"llvm.x86.avx512.scatter.dpq.512",
			"llvm.x86.avx512.scatter.dpq.mask.512",
			"llvm.x86.avx512.scatter.dps.512",
			"llvm.x86.avx512.scatter.dps.mask.512",
			"llvm.x86.avx512.scatter.qpd.512",
			"llvm.x86.avx512.scatter.qpd.mask.512",
			"llvm.x86.avx512.scatter.qpi.512",
			"llvm.x86.avx512.scatter.qpi.mask.512",
			"llvm.x86.avx512.scatter.qpq.512",
			"llvm.x86.avx512.scatter.qpq.mask.512",
			"llvm.x86.avx512.scatter.qps.512",
			"llvm.x86.avx512.scatter.qps.mask.512",
			"llvm.x86.avx512.sqrt.pd.512",
			"llvm.x86.avx512.sqrt.ps.512",
			"llvm.x86.avx512.sqrt.sd",
			"llvm.x86.avx512.sqrt.ss",
			"llvm.x86.avx512.vbroadcast.sd.512",
			"llvm.x86.avx512.vbroadcast.sd.pd.512",
			"llvm.x86.avx512.vbroadcast.ss.512",
			"llvm.x86.avx512.vbroadcast.ss.ps.512",
			"llvm.x86.avx512.vcvtph2ps.512",
			"llvm.x86.avx512.vcvtps2ph.512",
	"llvm.x86.avx.addsub.pd.256",		"llvm.x86.avx.addsub.pd.256",
	"llvm.x86.avx.addsub.ps.256",		"llvm.x86.avx.addsub.ps.256",
	"llvm.x86.avx.blend.pd.256",		"llvm.x86.avx.blend.pd.256",
	"llvm.x86.avx.blend.ps.256",		"llvm.x86.avx.blend.ps.256",
	"llvm.x86.avx.blendv.pd.256",		"llvm.x86.avx.blendv.pd.256",
	"llvm.x86.avx.blendv.ps.256",		"llvm.x86.avx.blendv.ps.256",
	"llvm.x86.avx.cmp.pd.256",		"llvm.x86.avx.cmp.pd.256",
	"llvm.x86.avx.cmp.ps.256",		"llvm.x86.avx.cmp.ps.256",
	"llvm.x86.avx.cvt.pd2.ps.256",		"llvm.x86.avx.cvt.pd2.ps.256",
	"llvm.x86.avx.cvt.pd2dq.256",		"llvm.x86.avx.cvt.pd2dq.256",
	skipping to change at line 4402		skipping to change at line 6068
	"llvm.x86.bmi.bextr.32",		"llvm.x86.bmi.bextr.32",
	"llvm.x86.bmi.bextr.64",		"llvm.x86.bmi.bextr.64",
	"llvm.x86.bmi.bzhi.32",		"llvm.x86.bmi.bzhi.32",
	"llvm.x86.bmi.bzhi.64",		"llvm.x86.bmi.bzhi.64",
	"llvm.x86.bmi.pdep.32",		"llvm.x86.bmi.pdep.32",
	"llvm.x86.bmi.pdep.64",		"llvm.x86.bmi.pdep.64",
	"llvm.x86.bmi.pext.32",		"llvm.x86.bmi.pext.32",
	"llvm.x86.bmi.pext.64",		"llvm.x86.bmi.pext.64",
	"llvm.x86.fma.vfmadd.pd",		"llvm.x86.fma.vfmadd.pd",
	"llvm.x86.fma.vfmadd.pd.256",		"llvm.x86.fma.vfmadd.pd.256",
			"llvm.x86.fma.vfmadd.pd.512",
	"llvm.x86.fma.vfmadd.ps",		"llvm.x86.fma.vfmadd.ps",
	"llvm.x86.fma.vfmadd.ps.256",		"llvm.x86.fma.vfmadd.ps.256",
			"llvm.x86.fma.vfmadd.ps.512",
	"llvm.x86.fma.vfmadd.sd",		"llvm.x86.fma.vfmadd.sd",
	"llvm.x86.fma.vfmadd.ss",		"llvm.x86.fma.vfmadd.ss",
	"llvm.x86.fma.vfmaddsub.pd",		"llvm.x86.fma.vfmaddsub.pd",
	"llvm.x86.fma.vfmaddsub.pd.256",		"llvm.x86.fma.vfmaddsub.pd.256",
			"llvm.x86.fma.vfmaddsub.pd.512",
	"llvm.x86.fma.vfmaddsub.ps",		"llvm.x86.fma.vfmaddsub.ps",
	"llvm.x86.fma.vfmaddsub.ps.256",		"llvm.x86.fma.vfmaddsub.ps.256",
			"llvm.x86.fma.vfmaddsub.ps.512",
	"llvm.x86.fma.vfmsub.pd",		"llvm.x86.fma.vfmsub.pd",
	"llvm.x86.fma.vfmsub.pd.256",		"llvm.x86.fma.vfmsub.pd.256",
			"llvm.x86.fma.vfmsub.pd.512",
	"llvm.x86.fma.vfmsub.ps",		"llvm.x86.fma.vfmsub.ps",
	"llvm.x86.fma.vfmsub.ps.256",		"llvm.x86.fma.vfmsub.ps.256",
			"llvm.x86.fma.vfmsub.ps.512",
	"llvm.x86.fma.vfmsub.sd",		"llvm.x86.fma.vfmsub.sd",
	"llvm.x86.fma.vfmsub.ss",		"llvm.x86.fma.vfmsub.ss",
	"llvm.x86.fma.vfmsubadd.pd",		"llvm.x86.fma.vfmsubadd.pd",
	"llvm.x86.fma.vfmsubadd.pd.256",		"llvm.x86.fma.vfmsubadd.pd.256",
			"llvm.x86.fma.vfmsubadd.pd.512",
	"llvm.x86.fma.vfmsubadd.ps",		"llvm.x86.fma.vfmsubadd.ps",
	"llvm.x86.fma.vfmsubadd.ps.256",		"llvm.x86.fma.vfmsubadd.ps.256",
			"llvm.x86.fma.vfmsubadd.ps.512",
	"llvm.x86.fma.vfnmadd.pd",		"llvm.x86.fma.vfnmadd.pd",
	"llvm.x86.fma.vfnmadd.pd.256",		"llvm.x86.fma.vfnmadd.pd.256",
			"llvm.x86.fma.vfnmadd.pd.512",
	"llvm.x86.fma.vfnmadd.ps",		"llvm.x86.fma.vfnmadd.ps",
	"llvm.x86.fma.vfnmadd.ps.256",		"llvm.x86.fma.vfnmadd.ps.256",
			"llvm.x86.fma.vfnmadd.ps.512",
	"llvm.x86.fma.vfnmadd.sd",		"llvm.x86.fma.vfnmadd.sd",
	"llvm.x86.fma.vfnmadd.ss",		"llvm.x86.fma.vfnmadd.ss",
	"llvm.x86.fma.vfnmsub.pd",		"llvm.x86.fma.vfnmsub.pd",
	"llvm.x86.fma.vfnmsub.pd.256",		"llvm.x86.fma.vfnmsub.pd.256",
			"llvm.x86.fma.vfnmsub.pd.512",
	"llvm.x86.fma.vfnmsub.ps",		"llvm.x86.fma.vfnmsub.ps",
	"llvm.x86.fma.vfnmsub.ps.256",		"llvm.x86.fma.vfnmsub.ps.256",
			"llvm.x86.fma.vfnmsub.ps.512",
	"llvm.x86.fma.vfnmsub.sd",		"llvm.x86.fma.vfnmsub.sd",
	"llvm.x86.fma.vfnmsub.ss",		"llvm.x86.fma.vfnmsub.ss",
	"llvm.x86.int",		"llvm.x86.int",
			"llvm.x86.int2mask.v16i1",
			"llvm.x86.kadd.v16i1",
			"llvm.x86.kand.v16i1",
			"llvm.x86.kandn.v16i1",
			"llvm.x86.knot.v16i1",
			"llvm.x86.kor.v16i1",
			"llvm.x86.kunpck.v16i1",
			"llvm.x86.kxnor.v16i1",
			"llvm.x86.kxor.v16i1",
			"llvm.x86.mask2int.v16i1",
	"llvm.x86.mmx.emms",		"llvm.x86.mmx.emms",
	"llvm.x86.mmx.femms",		"llvm.x86.mmx.femms",
	"llvm.x86.mmx.maskmovq",		"llvm.x86.mmx.maskmovq",
	"llvm.x86.mmx.movnt.dq",		"llvm.x86.mmx.movnt.dq",
	"llvm.x86.mmx.packssdw",		"llvm.x86.mmx.packssdw",
	"llvm.x86.mmx.packsswb",		"llvm.x86.mmx.packsswb",
	"llvm.x86.mmx.packuswb",		"llvm.x86.mmx.packuswb",
	"llvm.x86.mmx.padd.b",		"llvm.x86.mmx.padd.b",
	"llvm.x86.mmx.padd.d",		"llvm.x86.mmx.padd.d",
	"llvm.x86.mmx.padd.q",		"llvm.x86.mmx.padd.q",
	skipping to change at line 4515		skipping to change at line 6203
	"llvm.x86.rdfsbase.32",		"llvm.x86.rdfsbase.32",
	"llvm.x86.rdfsbase.64",		"llvm.x86.rdfsbase.64",
	"llvm.x86.rdgsbase.32",		"llvm.x86.rdgsbase.32",
	"llvm.x86.rdgsbase.64",		"llvm.x86.rdgsbase.64",
	"llvm.x86.rdrand.16",		"llvm.x86.rdrand.16",
	"llvm.x86.rdrand.32",		"llvm.x86.rdrand.32",
	"llvm.x86.rdrand.64",		"llvm.x86.rdrand.64",
	"llvm.x86.rdseed.16",		"llvm.x86.rdseed.16",
	"llvm.x86.rdseed.32",		"llvm.x86.rdseed.32",
	"llvm.x86.rdseed.64",		"llvm.x86.rdseed.64",
			"llvm.x86.sha1msg1",
			"llvm.x86.sha1msg2",
			"llvm.x86.sha1nexte",
			"llvm.x86.sha1rnds4",
			"llvm.x86.sha256msg1",
			"llvm.x86.sha256msg2",
			"llvm.x86.sha256rnds2",
	"llvm.x86.sse2.add.sd",		"llvm.x86.sse2.add.sd",
	"llvm.x86.sse2.clflush",		"llvm.x86.sse2.clflush",
	"llvm.x86.sse2.cmp.pd",		"llvm.x86.sse2.cmp.pd",
	"llvm.x86.sse2.cmp.sd",		"llvm.x86.sse2.cmp.sd",
	"llvm.x86.sse2.comieq.sd",		"llvm.x86.sse2.comieq.sd",
	"llvm.x86.sse2.comige.sd",		"llvm.x86.sse2.comige.sd",
	"llvm.x86.sse2.comigt.sd",		"llvm.x86.sse2.comigt.sd",
	"llvm.x86.sse2.comile.sd",		"llvm.x86.sse2.comile.sd",
	"llvm.x86.sse2.comilt.sd",		"llvm.x86.sse2.comilt.sd",
	"llvm.x86.sse2.comineq.sd",		"llvm.x86.sse2.comineq.sd",
	skipping to change at line 4664		skipping to change at line 6359
	"llvm.x86.sse41.ptestnzc",		"llvm.x86.sse41.ptestnzc",
	"llvm.x86.sse41.ptestz",		"llvm.x86.sse41.ptestz",
	"llvm.x86.sse41.round.pd",		"llvm.x86.sse41.round.pd",
	"llvm.x86.sse41.round.ps",		"llvm.x86.sse41.round.ps",
	"llvm.x86.sse41.round.sd",		"llvm.x86.sse41.round.sd",
	"llvm.x86.sse41.round.ss",		"llvm.x86.sse41.round.ss",
	"llvm.x86.sse42.crc32.32.16",		"llvm.x86.sse42.crc32.32.16",
	"llvm.x86.sse42.crc32.32.32",		"llvm.x86.sse42.crc32.32.32",
	"llvm.x86.sse42.crc32.32.8",		"llvm.x86.sse42.crc32.32.8",
	"llvm.x86.sse42.crc32.64.64",		"llvm.x86.sse42.crc32.64.64",
	"llvm.x86.sse42.crc32.64.8",
	"llvm.x86.sse42.pcmpestri128",		"llvm.x86.sse42.pcmpestri128",
	"llvm.x86.sse42.pcmpestria128",		"llvm.x86.sse42.pcmpestria128",
	"llvm.x86.sse42.pcmpestric128",		"llvm.x86.sse42.pcmpestric128",
	"llvm.x86.sse42.pcmpestrio128",		"llvm.x86.sse42.pcmpestrio128",
	"llvm.x86.sse42.pcmpestris128",		"llvm.x86.sse42.pcmpestris128",
	"llvm.x86.sse42.pcmpestriz128",		"llvm.x86.sse42.pcmpestriz128",
	"llvm.x86.sse42.pcmpestrm128",		"llvm.x86.sse42.pcmpestrm128",
	"llvm.x86.sse42.pcmpistri128",		"llvm.x86.sse42.pcmpistri128",
	"llvm.x86.sse42.pcmpistria128",		"llvm.x86.sse42.pcmpistria128",
	"llvm.x86.sse42.pcmpistric128",		"llvm.x86.sse42.pcmpistric128",
	skipping to change at line 4761		skipping to change at line 6455
	"llvm.x86.ssse3.pmul.hr.sw",		"llvm.x86.ssse3.pmul.hr.sw",
	"llvm.x86.ssse3.pmul.hr.sw.128",		"llvm.x86.ssse3.pmul.hr.sw.128",
	"llvm.x86.ssse3.pshuf.b",		"llvm.x86.ssse3.pshuf.b",
	"llvm.x86.ssse3.pshuf.b.128",		"llvm.x86.ssse3.pshuf.b.128",
	"llvm.x86.ssse3.psign.b",		"llvm.x86.ssse3.psign.b",
	"llvm.x86.ssse3.psign.b.128",		"llvm.x86.ssse3.psign.b.128",
	"llvm.x86.ssse3.psign.d",		"llvm.x86.ssse3.psign.d",
	"llvm.x86.ssse3.psign.d.128",		"llvm.x86.ssse3.psign.d.128",
	"llvm.x86.ssse3.psign.w",		"llvm.x86.ssse3.psign.w",
	"llvm.x86.ssse3.psign.w.128",		"llvm.x86.ssse3.psign.w.128",
			"llvm.x86.tbm.bextri.u32",
			"llvm.x86.tbm.bextri.u64",
	"llvm.x86.vcvtph2ps.128",		"llvm.x86.vcvtph2ps.128",
	"llvm.x86.vcvtph2ps.256",		"llvm.x86.vcvtph2ps.256",
	"llvm.x86.vcvtps2ph.128",		"llvm.x86.vcvtps2ph.128",
	"llvm.x86.vcvtps2ph.256",		"llvm.x86.vcvtps2ph.256",
	"llvm.x86.wrfsbase.32",		"llvm.x86.wrfsbase.32",
	"llvm.x86.wrfsbase.64",		"llvm.x86.wrfsbase.64",
	"llvm.x86.wrgsbase.32",		"llvm.x86.wrgsbase.32",
	"llvm.x86.wrgsbase.64",		"llvm.x86.wrgsbase.64",
	"llvm.x86.xabort",		"llvm.x86.xabort",
	"llvm.x86.xbegin",		"llvm.x86.xbegin",
	skipping to change at line 4893		skipping to change at line 6589
	"llvm.xcore.syncr",		"llvm.xcore.syncr",
	"llvm.xcore.testct",		"llvm.xcore.testct",
	"llvm.xcore.testwct",		"llvm.xcore.testwct",
	"llvm.xcore.waitevent",		"llvm.xcore.waitevent",
	"llvm.xcore.zext",		"llvm.xcore.zext",
	#endif		#endif
	// Intrinsic ID to overload bitset		// Intrinsic ID to overload bitset
	#ifdef GET_INTRINSIC_OVERLOAD_TABLE		#ifdef GET_INTRINSIC_OVERLOAD_TABLE
	static const uint8_t OTable[] = {		static const uint8_t OTable[] = {
			0 | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7),
			0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7)
			,
			0 | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7),
			0 | (1<<0) | (1<<1) | (1<<2),
			0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7)
			,
			0 | (1<<0) | (1<<1),
			0 | (1<<6) | (1<<7),
			0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7)
			,
			0,
			0 | (1<<1) | (1<<4) | (1<<6) | (1<<7),
			0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7)
			,
	0 | (1<<2),		0 | (1<<2),
	0 | (1<<5) | (1<<6) | (1<<7),		0 | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7),
	0 | (1<<4) | (1<<5) | (1<<6) | (1<<7),		0 | (1<<0) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7),
			0 | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7),
			0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7)
			,
			0 | (1<<1),
			0 | (1<<6),
			0 | (1<<6) | (1<<7),
			0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7)
			,
			0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6),
			0 | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7),
	0 | (1<<0) | (1<<1) | (1<<2) | (1<<4) | (1<<5) | (1<<7),		0 | (1<<0) | (1<<1) | (1<<2) | (1<<4) | (1<<5) | (1<<7),
	0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,		0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,
	0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,		0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,
	0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,		0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,
	0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,		0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,
	0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,		0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,
	0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,		0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,
	0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,		0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,
	0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,		0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,
	0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,		0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7) ,
			0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7)
			,
			0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7)
			,
			0,
			0 | (1<<5),
			0 | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<7),
			0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7)
			,
	0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4),		0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4),
	0,		0,
	0 | (1<<4) | (1<<5) | (1<<6) | (1<<7),		0 | (1<<4) | (1<<5) | (1<<6),
	0 | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7),		0 | (1<<2) | (1<<3) | (1<<5) | (1<<6),
	0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6),
	0,		0,
	0 | (1<<6) | (1<<7),
	0 | (1<<0) | (1<<1) | (1<<2) | (1<<4) | (1<<5),
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	skipping to change at line 5020		skipping to change at line 6738
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
			0 | (1<<5) | (1<<6) | (1<<7),
			0 | (1<<1) | (1<<2) | (1<<3),
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
	0,		0,
	0 | (1<<4) | (1<<5) | (1<<6),
	0 | (1<<0) | (1<<1) | (1<<2),
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0 | (1<<2),
	0,		0,
	0 | (1<<1) | (1<<2) | (1<<3),
	0,		0,
	0 | (1<<3) | (1<<4),
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0 | (1<<5) | (1<<6) | (1<<7),
	0 | (1<<0) | (1<<1) | (1<<2),
	0,		0,
	0,		0,
	0,		0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0 | (1<<6),
			0,
			0 | (1<<5) | (1<<6) | (1<<7),
			0,
			0 | (1<<7),
	0 | (1<<0),		0 | (1<<0),
	0,		0,
	0 | (1<<6) | (1<<7),
	0 | (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6),
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0 | (1<<0) | (1<<2) | (1<<3),
	0,		0,
	0,		0,
	0,		0,
			0 | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6),
	0,		0,
	0,		0,
	0,		0,
			0 | (1<<3),
			0,
			0,
			0 | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5) | (1<<6) | (1<<7),
			0 | (1<<0) | (1<<1),
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0 | (1<<3) | (1<<5) | (1<<6),
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0,
			0 | (1<<3) | (1<<6),
			0,
			0,
			0,
			0,
			0,
			0,
			0 | (1<<2) | (1<<3) | (1<<4),
			0 | (1<<0) | (1<<1) | (1<<2) | (1<<3),
			0 | (1<<1) | (1<<2) | (1<<3) | (1<<4),
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0 | (1<<1),
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0 | (1<<5) | (1<<6),
	0 | (1<<2) | (1<<3) | (1<<4) | (1<<5),
	0 | (1<<2) | (1<<3) | (1<<4) | (1<<5),
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	0,		0,
	skipping to change at line 5209		skipping to change at line 7011
	return (OTable[id/8] & (1 << (id%8))) != 0;		return (OTable[id/8] & (1 << (id%8))) != 0;
	#endif		#endif
	// Function name -> enum value recognizer code.		// Function name -> enum value recognizer code.
	#ifdef GET_FUNCTION_RECOGNIZER		#ifdef GET_FUNCTION_RECOGNIZER
	StringRef NameR(Name+6, Len-6); // Skip over 'llvm.'		StringRef NameR(Name+6, Len-6); // Skip over 'llvm.'
	switch (Name[5]) { // Dispatch on first letter.		switch (Name[5]) { // Dispatch on first letter.
	default: break;		default: break;
	case 'a':		case 'a':
	if (NameR.startswith("nnotation.")) return Intrinsic::annotation;
	if (NameR.startswith("rm.neon.vabds.")) return Intrinsic::arm_neon_vabd
	s;
	if (NameR.startswith("rm.neon.vabdu.")) return Intrinsic::arm_neon_vabd
	u;
	if (NameR.startswith("rm.neon.vabs.")) return Intrinsic::arm_neon_vabs;
	if (NameR.startswith("rm.neon.vaddhn.")) return Intrinsic::arm_neon_vad
	dhn;
	if (NameR.startswith("rm.neon.vbsl.")) return Intrinsic::arm_neon_vbsl;
	if (NameR.startswith("rm.neon.vcls.")) return Intrinsic::arm_neon_vcls;
	if (NameR.startswith("rm.neon.vclz.")) return Intrinsic::arm_neon_vclz;
	if (NameR.startswith("rm.neon.vcnt.")) return Intrinsic::arm_neon_vcnt;
	if (NameR.startswith("rm.neon.vcvtfp2fxs.")) return Intrinsic::arm_neon
	_vcvtfp2fxs;
	if (NameR.startswith("rm.neon.vcvtfp2fxu.")) return Intrinsic::arm_neon
	_vcvtfp2fxu;
	if (NameR.startswith("rm.neon.vcvtfxs2fp.")) return Intrinsic::arm_neon
	_vcvtfxs2fp;
	if (NameR.startswith("rm.neon.vcvtfxu2fp.")) return Intrinsic::arm_neon
	_vcvtfxu2fp;
	if (NameR.startswith("rm.neon.vhadds.")) return Intrinsic::arm_neon_vha
	dds;
	if (NameR.startswith("rm.neon.vhaddu.")) return Intrinsic::arm_neon_vha
	ddu;
	if (NameR.startswith("rm.neon.vhsubs.")) return Intrinsic::arm_neon_vhs
	ubs;
	if (NameR.startswith("rm.neon.vhsubu.")) return Intrinsic::arm_neon_vhs
	ubu;
	if (NameR.startswith("rm.neon.vld1.")) return Intrinsic::arm_neon_vld1;
	if (NameR.startswith("rm.neon.vld2.")) return Intrinsic::arm_neon_vld2;
	if (NameR.startswith("rm.neon.vld2lane.")) return Intrinsic::arm_neon_v
	ld2lane;
	if (NameR.startswith("rm.neon.vld3.")) return Intrinsic::arm_neon_vld3;
	if (NameR.startswith("rm.neon.vld3lane.")) return Intrinsic::arm_neon_v
	ld3lane;
	if (NameR.startswith("rm.neon.vld4.")) return Intrinsic::arm_neon_vld4;
	if (NameR.startswith("rm.neon.vld4lane.")) return Intrinsic::arm_neon_v
	ld4lane;
	if (NameR.startswith("rm.neon.vmaxs.")) return Intrinsic::arm_neon_vmax
	s;
	if (NameR.startswith("rm.neon.vmaxu.")) return Intrinsic::arm_neon_vmax
	u;
	if (NameR.startswith("rm.neon.vmins.")) return Intrinsic::arm_neon_vmin
	s;
	if (NameR.startswith("rm.neon.vminu.")) return Intrinsic::arm_neon_vmin
	u;
	if (NameR.startswith("rm.neon.vmullp.")) return Intrinsic::arm_neon_vmu
	llp;
	if (NameR.startswith("rm.neon.vmulls.")) return Intrinsic::arm_neon_vmu
	lls;
	if (NameR.startswith("rm.neon.vmullu.")) return Intrinsic::arm_neon_vmu
	llu;
	if (NameR.startswith("rm.neon.vmulp.")) return Intrinsic::arm_neon_vmul
	p;
	if (NameR.startswith("rm.neon.vpadals.")) return Intrinsic::arm_neon_vp
	adals;
	if (NameR.startswith("rm.neon.vpadalu.")) return Intrinsic::arm_neon_vp
	adalu;
	if (NameR.startswith("rm.neon.vpadd.")) return Intrinsic::arm_neon_vpad
	d;
	if (NameR.startswith("rm.neon.vpaddls.")) return Intrinsic::arm_neon_vp
	addls;
	if (NameR.startswith("rm.neon.vpaddlu.")) return Intrinsic::arm_neon_vp
	addlu;
	if (NameR.startswith("rm.neon.vpmaxs.")) return Intrinsic::arm_neon_vpm
	axs;
	if (NameR.startswith("rm.neon.vpmaxu.")) return Intrinsic::arm_neon_vpm
	axu;
	if (NameR.startswith("rm.neon.vpmins.")) return Intrinsic::arm_neon_vpm
	ins;
	if (NameR.startswith("rm.neon.vpminu.")) return Intrinsic::arm_neon_vpm
	inu;
	if (NameR.startswith("rm.neon.vqabs.")) return Intrinsic::arm_neon_vqab
	s;
	if (NameR.startswith("rm.neon.vqadds.")) return Intrinsic::arm_neon_vqa
	dds;
	if (NameR.startswith("rm.neon.vqaddu.")) return Intrinsic::arm_neon_vqa
	ddu;
	if (NameR.startswith("rm.neon.vqdmlal.")) return Intrinsic::arm_neon_vq
	dmlal;
	if (NameR.startswith("rm.neon.vqdmlsl.")) return Intrinsic::arm_neon_vq
	dmlsl;
	if (NameR.startswith("rm.neon.vqdmulh.")) return Intrinsic::arm_neon_vq
	dmulh;
	if (NameR.startswith("rm.neon.vqdmull.")) return Intrinsic::arm_neon_vq
	dmull;
	if (NameR.startswith("rm.neon.vqmovns.")) return Intrinsic::arm_neon_vq
	movns;
	if (NameR.startswith("rm.neon.vqmovnsu.")) return Intrinsic::arm_neon_v
	qmovnsu;
	if (NameR.startswith("rm.neon.vqmovnu.")) return Intrinsic::arm_neon_vq
	movnu;
	if (NameR.startswith("rm.neon.vqneg.")) return Intrinsic::arm_neon_vqne
	g;
	if (NameR.startswith("rm.neon.vqrdmulh.")) return Intrinsic::arm_neon_v
	qrdmulh;
	if (NameR.startswith("rm.neon.vqrshiftns.")) return Intrinsic::arm_neon
	_vqrshiftns;
	if (NameR.startswith("rm.neon.vqrshiftnsu.")) return Intrinsic::arm_neo
	n_vqrshiftnsu;
	if (NameR.startswith("rm.neon.vqrshiftnu.")) return Intrinsic::arm_neon
	_vqrshiftnu;
	if (NameR.startswith("rm.neon.vqrshifts.")) return Intrinsic::arm_neon_
	vqrshifts;
	if (NameR.startswith("rm.neon.vqrshiftu.")) return Intrinsic::arm_neon_
	vqrshiftu;
	if (NameR.startswith("rm.neon.vqshiftns.")) return Intrinsic::arm_neon_
	vqshiftns;
	if (NameR.startswith("rm.neon.vqshiftnsu.")) return Intrinsic::arm_neon
	_vqshiftnsu;
	if (NameR.startswith("rm.neon.vqshiftnu.")) return Intrinsic::arm_neon_
	vqshiftnu;
	if (NameR.startswith("rm.neon.vqshifts.")) return Intrinsic::arm_neon_v
	qshifts;
	if (NameR.startswith("rm.neon.vqshiftsu.")) return Intrinsic::arm_neon_
	vqshiftsu;
	if (NameR.startswith("rm.neon.vqshiftu.")) return Intrinsic::arm_neon_v
	qshiftu;
	if (NameR.startswith("rm.neon.vqsubs.")) return Intrinsic::arm_neon_vqs
	ubs;
	if (NameR.startswith("rm.neon.vqsubu.")) return Intrinsic::arm_neon_vqs
	ubu;
	if (NameR.startswith("rm.neon.vraddhn.")) return Intrinsic::arm_neon_vr
	addhn;
	if (NameR.startswith("rm.neon.vrecpe.")) return Intrinsic::arm_neon_vre
	cpe;
	if (NameR.startswith("rm.neon.vrecps.")) return Intrinsic::arm_neon_vre
	cps;
	if (NameR.startswith("rm.neon.vrhadds.")) return Intrinsic::arm_neon_vr
	hadds;
	if (NameR.startswith("rm.neon.vrhaddu.")) return Intrinsic::arm_neon_vr
	haddu;
	if (NameR.startswith("rm.neon.vrshiftn.")) return Intrinsic::arm_neon_v
	rshiftn;
	if (NameR.startswith("rm.neon.vrshifts.")) return Intrinsic::arm_neon_v
	rshifts;
	if (NameR.startswith("rm.neon.vrshiftu.")) return Intrinsic::arm_neon_v
	rshiftu;
	if (NameR.startswith("rm.neon.vrsqrte.")) return Intrinsic::arm_neon_vr
	sqrte;
	if (NameR.startswith("rm.neon.vrsqrts.")) return Intrinsic::arm_neon_vr
	sqrts;
	if (NameR.startswith("rm.neon.vrsubhn.")) return Intrinsic::arm_neon_vr
	subhn;
	if (NameR.startswith("rm.neon.vshiftins.")) return Intrinsic::arm_neon_
	vshiftins;
	if (NameR.startswith("rm.neon.vshiftls.")) return Intrinsic::arm_neon_v
	shiftls;
	if (NameR.startswith("rm.neon.vshiftlu.")) return Intrinsic::arm_neon_v
	shiftlu;
	if (NameR.startswith("rm.neon.vshiftn.")) return Intrinsic::arm_neon_vs
	hiftn;
	if (NameR.startswith("rm.neon.vshifts.")) return Intrinsic::arm_neon_vs
	hifts;
	if (NameR.startswith("rm.neon.vshiftu.")) return Intrinsic::arm_neon_vs
	hiftu;
	if (NameR.startswith("rm.neon.vst1.")) return Intrinsic::arm_neon_vst1;
	if (NameR.startswith("rm.neon.vst2.")) return Intrinsic::arm_neon_vst2;
	if (NameR.startswith("rm.neon.vst2lane.")) return Intrinsic::arm_neon_v
	st2lane;
	if (NameR.startswith("rm.neon.vst3.")) return Intrinsic::arm_neon_vst3;
	if (NameR.startswith("rm.neon.vst3lane.")) return Intrinsic::arm_neon_v
	st3lane;
	if (NameR.startswith("rm.neon.vst4.")) return Intrinsic::arm_neon_vst4;
	if (NameR.startswith("rm.neon.vst4lane.")) return Intrinsic::arm_neon_v
	st4lane;
	if (NameR.startswith("rm.neon.vsubhn.")) return Intrinsic::arm_neon_vsu
	bhn;
	if (NameR.startswith("rm.vcvtr.")) return Intrinsic::arm_vcvtr;
	if (NameR.startswith("rm.vcvtru.")) return Intrinsic::arm_vcvtru;		if (NameR.startswith("rm.vcvtru.")) return Intrinsic::arm_vcvtru;
			if (NameR.startswith("rm.vcvtr.")) return Intrinsic::arm_vcvtr;
			if (NameR.startswith("rm.strex.")) return Intrinsic::arm_strex;
			if (NameR.startswith("rm.neon.vst4lane.")) return Intrinsic::arm_neon_v
			st4lane;
			if (NameR.startswith("rm.neon.vst4.")) return Intrinsic::arm_neon_vst4;
			if (NameR.startswith("rm.neon.vst3lane.")) return Intrinsic::arm_neon_v
			st3lane;
			if (NameR.startswith("rm.neon.vst3.")) return Intrinsic::arm_neon_vst3;
			if (NameR.startswith("rm.neon.vst2lane.")) return Intrinsic::arm_neon_v
			st2lane;
			if (NameR.startswith("rm.neon.vst2.")) return Intrinsic::arm_neon_vst2;
			if (NameR.startswith("rm.neon.vst1.")) return Intrinsic::arm_neon_vst1;
			if (NameR.startswith("rm.neon.vshiftu.")) return Intrinsic::arm_neon_vs
			hiftu;
			if (NameR.startswith("rm.neon.vshifts.")) return Intrinsic::arm_neon_vs
			hifts;
			if (NameR.startswith("rm.neon.vshiftn.")) return Intrinsic::arm_neon_vs
			hiftn;
			if (NameR.startswith("rm.neon.vshiftlu.")) return Intrinsic::arm_neon_v
			shiftlu;
			if (NameR.startswith("rm.neon.vshiftls.")) return Intrinsic::arm_neon_v
			shiftls;
			if (NameR.startswith("rm.neon.vshiftins.")) return Intrinsic::arm_neon_
			vshiftins;
			if (NameR.startswith("rm.neon.vrsubhn.")) return Intrinsic::arm_neon_vr
			subhn;
			if (NameR.startswith("rm.neon.vrsqrts.")) return Intrinsic::arm_neon_vr
			sqrts;
			if (NameR.startswith("rm.neon.vrsqrte.")) return Intrinsic::arm_neon_vr
			sqrte;
			if (NameR.startswith("rm.neon.vrshiftu.")) return Intrinsic::arm_neon_v
			rshiftu;
			if (NameR.startswith("rm.neon.vrshifts.")) return Intrinsic::arm_neon_v
			rshifts;
			if (NameR.startswith("rm.neon.vrshiftn.")) return Intrinsic::arm_neon_v
			rshiftn;
			if (NameR.startswith("rm.neon.vrintz.")) return Intrinsic::arm_neon_vri
			ntz;
			if (NameR.startswith("rm.neon.vrintx.")) return Intrinsic::arm_neon_vri
			ntx;
			if (NameR.startswith("rm.neon.vrintp.")) return Intrinsic::arm_neon_vri
			ntp;
			if (NameR.startswith("rm.neon.vrintn.")) return Intrinsic::arm_neon_vri
			ntn;
			if (NameR.startswith("rm.neon.vrintm.")) return Intrinsic::arm_neon_vri
			ntm;
			if (NameR.startswith("rm.neon.vrinta.")) return Intrinsic::arm_neon_vri
			nta;
			if (NameR.startswith("rm.neon.vrhaddu.")) return Intrinsic::arm_neon_vr
			haddu;
			if (NameR.startswith("rm.neon.vrhadds.")) return Intrinsic::arm_neon_vr
			hadds;
			if (NameR.startswith("rm.neon.vrecps.")) return Intrinsic::arm_neon_vre
			cps;
			if (NameR.startswith("rm.neon.vrecpe.")) return Intrinsic::arm_neon_vre
			cpe;
			if (NameR.startswith("rm.neon.vraddhn.")) return Intrinsic::arm_neon_vr
			addhn;
			if (NameR.startswith("rm.neon.vqsubu.")) return Intrinsic::arm_neon_vqs
			ubu;
			if (NameR.startswith("rm.neon.vqsubs.")) return Intrinsic::arm_neon_vqs
			ubs;
			if (NameR.startswith("rm.neon.vqshiftu.")) return Intrinsic::arm_neon_v
			qshiftu;
			if (NameR.startswith("rm.neon.vqshiftsu.")) return Intrinsic::arm_neon_
			vqshiftsu;
			if (NameR.startswith("rm.neon.vqshifts.")) return Intrinsic::arm_neon_v
			qshifts;
			if (NameR.startswith("rm.neon.vqshiftnu.")) return Intrinsic::arm_neon_
			vqshiftnu;
			if (NameR.startswith("rm.neon.vqshiftnsu.")) return Intrinsic::arm_neon
			_vqshiftnsu;
			if (NameR.startswith("rm.neon.vqshiftns.")) return Intrinsic::arm_neon_
			vqshiftns;
			if (NameR.startswith("rm.neon.vqrshiftu.")) return Intrinsic::arm_neon_
			vqrshiftu;
			if (NameR.startswith("rm.neon.vqrshifts.")) return Intrinsic::arm_neon_
			vqrshifts;
			if (NameR.startswith("rm.neon.vqrshiftnu.")) return Intrinsic::arm_neon
			_vqrshiftnu;
			if (NameR.startswith("rm.neon.vqrshiftnsu.")) return Intrinsic::arm_neo
			n_vqrshiftnsu;
			if (NameR.startswith("rm.neon.vqrshiftns.")) return Intrinsic::arm_neon
			_vqrshiftns;
			if (NameR.startswith("rm.neon.vqrdmulh.")) return Intrinsic::arm_neon_v
			qrdmulh;
			if (NameR.startswith("rm.neon.vqneg.")) return Intrinsic::arm_neon_vqne
			g;
			if (NameR.startswith("rm.neon.vqmovnu.")) return Intrinsic::arm_neon_vq
			movnu;
			if (NameR.startswith("rm.neon.vqmovnsu.")) return Intrinsic::arm_neon_v
			qmovnsu;
			if (NameR.startswith("rm.neon.vqmovns.")) return Intrinsic::arm_neon_vq
			movns;
			if (NameR.startswith("rm.neon.vqdmull.")) return Intrinsic::arm_neon_vq
			dmull;
			if (NameR.startswith("rm.neon.vqdmulh.")) return Intrinsic::arm_neon_vq
			dmulh;
			if (NameR.startswith("rm.neon.vqaddu.")) return Intrinsic::arm_neon_vqa
			ddu;
			if (NameR.startswith("rm.neon.vqadds.")) return Intrinsic::arm_neon_vqa
			dds;
			if (NameR.startswith("rm.neon.vqabs.")) return Intrinsic::arm_neon_vqab
			s;
			if (NameR.startswith("rm.neon.vpminu.")) return Intrinsic::arm_neon_vpm
			inu;
			if (NameR.startswith("rm.neon.vpmins.")) return Intrinsic::arm_neon_vpm
			ins;
			if (NameR.startswith("rm.neon.vpmaxu.")) return Intrinsic::arm_neon_vpm
			axu;
			if (NameR.startswith("rm.neon.vpmaxs.")) return Intrinsic::arm_neon_vpm
			axs;
			if (NameR.startswith("rm.neon.vpaddlu.")) return Intrinsic::arm_neon_vp
			addlu;
			if (NameR.startswith("rm.neon.vpaddls.")) return Intrinsic::arm_neon_vp
			addls;
			if (NameR.startswith("rm.neon.vpadd.")) return Intrinsic::arm_neon_vpad
			d;
			if (NameR.startswith("rm.neon.vpadalu.")) return Intrinsic::arm_neon_vp
			adalu;
			if (NameR.startswith("rm.neon.vpadals.")) return Intrinsic::arm_neon_vp
			adals;
			if (NameR.startswith("rm.neon.vmulp.")) return Intrinsic::arm_neon_vmul
			p;
			if (NameR.startswith("rm.neon.vmullu.")) return Intrinsic::arm_neon_vmu
			llu;
			if (NameR.startswith("rm.neon.vmulls.")) return Intrinsic::arm_neon_vmu
			lls;
			if (NameR.startswith("rm.neon.vmullp.")) return Intrinsic::arm_neon_vmu
			llp;
			if (NameR.startswith("rm.neon.vminu.")) return Intrinsic::arm_neon_vmin
			u;
			if (NameR.startswith("rm.neon.vmins.")) return Intrinsic::arm_neon_vmin
			s;
			if (NameR.startswith("rm.neon.vminnm.")) return Intrinsic::arm_neon_vmi
			nnm;
			if (NameR.startswith("rm.neon.vmaxu.")) return Intrinsic::arm_neon_vmax
			u;
			if (NameR.startswith("rm.neon.vmaxs.")) return Intrinsic::arm_neon_vmax
			s;
			if (NameR.startswith("rm.neon.vmaxnm.")) return Intrinsic::arm_neon_vma
			xnm;
			if (NameR.startswith("rm.neon.vld4lane.")) return Intrinsic::arm_neon_v
			ld4lane;
			if (NameR.startswith("rm.neon.vld4.")) return Intrinsic::arm_neon_vld4;
			if (NameR.startswith("rm.neon.vld3lane.")) return Intrinsic::arm_neon_v
			ld3lane;
			if (NameR.startswith("rm.neon.vld3.")) return Intrinsic::arm_neon_vld3;
			if (NameR.startswith("rm.neon.vld2lane.")) return Intrinsic::arm_neon_v
			ld2lane;
			if (NameR.startswith("rm.neon.vld2.")) return Intrinsic::arm_neon_vld2;
			if (NameR.startswith("rm.neon.vld1.")) return Intrinsic::arm_neon_vld1;
			if (NameR.startswith("rm.neon.vhsubu.")) return Intrinsic::arm_neon_vhs
			ubu;
			if (NameR.startswith("rm.neon.vhsubs.")) return Intrinsic::arm_neon_vhs
			ubs;
			if (NameR.startswith("rm.neon.vhaddu.")) return Intrinsic::arm_neon_vha
			ddu;
			if (NameR.startswith("rm.neon.vhadds.")) return Intrinsic::arm_neon_vha
			dds;
			if (NameR.startswith("rm.neon.vcvtpu.")) return Intrinsic::arm_neon_vcv
			tpu;
			if (NameR.startswith("rm.neon.vcvtps.")) return Intrinsic::arm_neon_vcv
			tps;
			if (NameR.startswith("rm.neon.vcvtnu.")) return Intrinsic::arm_neon_vcv
			tnu;
			if (NameR.startswith("rm.neon.vcvtns.")) return Intrinsic::arm_neon_vcv
			tns;
			if (NameR.startswith("rm.neon.vcvtmu.")) return Intrinsic::arm_neon_vcv
			tmu;
			if (NameR.startswith("rm.neon.vcvtms.")) return Intrinsic::arm_neon_vcv
			tms;
			if (NameR.startswith("rm.neon.vcvtfxu2fp.")) return Intrinsic::arm_neon
			_vcvtfxu2fp;
			if (NameR.startswith("rm.neon.vcvtfxs2fp.")) return Intrinsic::arm_neon
			_vcvtfxs2fp;
			if (NameR.startswith("rm.neon.vcvtfp2fxu.")) return Intrinsic::arm_neon
			_vcvtfp2fxu;
			if (NameR.startswith("rm.neon.vcvtfp2fxs.")) return Intrinsic::arm_neon
			_vcvtfp2fxs;
			if (NameR.startswith("rm.neon.vcvtau.")) return Intrinsic::arm_neon_vcv
			tau;
			if (NameR.startswith("rm.neon.vcvtas.")) return Intrinsic::arm_neon_vcv
			tas;
			if (NameR.startswith("rm.neon.vcnt.")) return Intrinsic::arm_neon_vcnt;
			if (NameR.startswith("rm.neon.vclz.")) return Intrinsic::arm_neon_vclz;
			if (NameR.startswith("rm.neon.vcls.")) return Intrinsic::arm_neon_vcls;
			if (NameR.startswith("rm.neon.vbsl.")) return Intrinsic::arm_neon_vbsl;
			if (NameR.startswith("rm.neon.vabs.")) return Intrinsic::arm_neon_vabs;
			if (NameR.startswith("rm.neon.vabdu.")) return Intrinsic::arm_neon_vabd
			u;
			if (NameR.startswith("rm.neon.vabds.")) return Intrinsic::arm_neon_vabd
			s;
			if (NameR.startswith("rm.neon.sha256su1.")) return Intrinsic::arm_neon_
			sha256su1;
			if (NameR.startswith("rm.neon.sha256su0.")) return Intrinsic::arm_neon_
			sha256su0;
			if (NameR.startswith("rm.neon.sha256h2.")) return Intrinsic::arm_neon_s
			ha256h2;
			if (NameR.startswith("rm.neon.sha256h.")) return Intrinsic::arm_neon_sh
			a256h;
			if (NameR.startswith("rm.neon.sha1su1.")) return Intrinsic::arm_neon_sh
			a1su1;
			if (NameR.startswith("rm.neon.sha1su0.")) return Intrinsic::arm_neon_sh
			a1su0;
			if (NameR.startswith("rm.neon.sha1p.")) return Intrinsic::arm_neon_sha1
			p;
			if (NameR.startswith("rm.neon.sha1m.")) return Intrinsic::arm_neon_sha1
			m;
			if (NameR.startswith("rm.neon.sha1h.")) return Intrinsic::arm_neon_sha1
			h;
			if (NameR.startswith("rm.neon.sha1c.")) return Intrinsic::arm_neon_sha1
			c;
			if (NameR.startswith("rm.neon.aesmc.")) return Intrinsic::arm_neon_aesm
			c;
			if (NameR.startswith("rm.neon.aesimc.")) return Intrinsic::arm_neon_aes
			imc;
			if (NameR.startswith("rm.neon.aese.")) return Intrinsic::arm_neon_aese;
			if (NameR.startswith("rm.neon.aesd.")) return Intrinsic::arm_neon_aesd;
			if (NameR.startswith("rm.ldrex.")) return Intrinsic::arm_ldrex;
			if (NameR.startswith("nnotation.")) return Intrinsic::annotation;
			if (NameR.startswith("arch64.neon.xtn.")) return Intrinsic::aarch64_neo
			n_xtn;
			if (NameR.startswith("arch64.neon.vurshr.")) return Intrinsic::aarch64_
			neon_vurshr;
			if (NameR.startswith("arch64.neon.vuqshrn.")) return Intrinsic::aarch64
			_neon_vuqshrn;
			if (NameR.startswith("arch64.neon.vuqrshrn.")) return Intrinsic::aarch6
			4_neon_vuqrshrn;
			if (NameR.startswith("arch64.neon.vuqadd.")) return Intrinsic::aarch64_
			neon_vuqadd;
			if (NameR.startswith("arch64.neon.vtstd.")) return Intrinsic::aarch64_n
			eon_vtstd;
			if (NameR.startswith("arch64.neon.vtbx4.")) return Intrinsic::aarch64_n
			eon_vtbx4;
			if (NameR.startswith("arch64.neon.vtbx3.")) return Intrinsic::aarch64_n
			eon_vtbx3;
			if (NameR.startswith("arch64.neon.vtbx2.")) return Intrinsic::aarch64_n
			eon_vtbx2;
			if (NameR.startswith("arch64.neon.vtbx1.")) return Intrinsic::aarch64_n
			eon_vtbx1;
			if (NameR.startswith("arch64.neon.vtbl4.")) return Intrinsic::aarch64_n
			eon_vtbl4;
			if (NameR.startswith("arch64.neon.vtbl3.")) return Intrinsic::aarch64_n
			eon_vtbl3;
			if (NameR.startswith("arch64.neon.vtbl2.")) return Intrinsic::aarch64_n
			eon_vtbl2;
			if (NameR.startswith("arch64.neon.vtbl1.")) return Intrinsic::aarch64_n
			eon_vtbl1;
			if (NameR.startswith("arch64.neon.vst1x4.")) return Intrinsic::aarch64_
			neon_vst1x4;
			if (NameR.startswith("arch64.neon.vst1x3.")) return Intrinsic::aarch64_
			neon_vst1x3;
			if (NameR.startswith("arch64.neon.vst1x2.")) return Intrinsic::aarch64_
			neon_vst1x2;
			if (NameR.startswith("arch64.neon.vsrshr.")) return Intrinsic::aarch64_
			neon_vsrshr;
			if (NameR.startswith("arch64.neon.vsri.")) return Intrinsic::aarch64_ne
			on_vsri;
			if (NameR.startswith("arch64.neon.vsqshrun.")) return Intrinsic::aarch6
			4_neon_vsqshrun;
			if (NameR.startswith("arch64.neon.vsqshrn.")) return Intrinsic::aarch64
			_neon_vsqshrn;
			if (NameR.startswith("arch64.neon.vsqshlu.")) return Intrinsic::aarch64
			_neon_vsqshlu;
			if (NameR.startswith("arch64.neon.vsqrshrun.")) return Intrinsic::aarch
			64_neon_vsqrshrun;
			if (NameR.startswith("arch64.neon.vsqrshrn.")) return Intrinsic::aarch6
			4_neon_vsqrshrn;
			if (NameR.startswith("arch64.neon.vsqadd.")) return Intrinsic::aarch64_
			neon_vsqadd;
			if (NameR.startswith("arch64.neon.vsli.")) return Intrinsic::aarch64_ne
			on_vsli;
			if (NameR.startswith("arch64.neon.vrshrn.")) return Intrinsic::aarch64_
			neon_vrshrn;
			if (NameR.startswith("arch64.neon.vrecpx.")) return Intrinsic::aarch64_
			neon_vrecpx;
			if (NameR.startswith("arch64.neon.vqshlus.n.")) return Intrinsic::aarch
			64_neon_vqshlus_n;
			if (NameR.startswith("arch64.neon.vqshlu.n.")) return Intrinsic::aarch6
			4_neon_vqshlu_n;
			if (NameR.startswith("arch64.neon.vqshlu.")) return Intrinsic::aarch64_
			neon_vqshlu;
			if (NameR.startswith("arch64.neon.vqshls.n.")) return Intrinsic::aarch6
			4_neon_vqshls_n;
			if (NameR.startswith("arch64.neon.vqshls.")) return Intrinsic::aarch64_
			neon_vqshls;
			if (NameR.startswith("arch64.neon.vqrshlu.")) return Intrinsic::aarch64
			_neon_vqrshlu;
			if (NameR.startswith("arch64.neon.vqrshls.")) return Intrinsic::aarch64
			_neon_vqrshls;
			if (NameR.startswith("arch64.neon.vqdmlsl.")) return Intrinsic::aarch64
			_neon_vqdmlsl;
			if (NameR.startswith("arch64.neon.vqdmlal.")) return Intrinsic::aarch64
			_neon_vqdmlal;
			if (NameR.startswith("arch64.neon.vpminnm.")) return Intrinsic::aarch64
			_neon_vpminnm;
			if (NameR.startswith("arch64.neon.vpmaxnm.")) return Intrinsic::aarch64
			_neon_vpmaxnm;
			if (NameR.startswith("arch64.neon.vmulx.")) return Intrinsic::aarch64_n
			eon_vmulx;
			if (NameR.startswith("arch64.neon.vminv.")) return Intrinsic::aarch64_n
			eon_vminv;
			if (NameR.startswith("arch64.neon.vminnmv.")) return Intrinsic::aarch64
			_neon_vminnmv;
			if (NameR.startswith("arch64.neon.vminnm.")) return Intrinsic::aarch64_
			neon_vminnm;
			if (NameR.startswith("arch64.neon.vmaxv.")) return Intrinsic::aarch64_n
			eon_vmaxv;
			if (NameR.startswith("arch64.neon.vmaxnmv.")) return Intrinsic::aarch64
			_neon_vmaxnmv;
			if (NameR.startswith("arch64.neon.vmaxnm.")) return Intrinsic::aarch64_
			neon_vmaxnm;
			if (NameR.startswith("arch64.neon.vld1x4.")) return Intrinsic::aarch64_
			neon_vld1x4;
			if (NameR.startswith("arch64.neon.vld1x3.")) return Intrinsic::aarch64_
			neon_vld1x3;
			if (NameR.startswith("arch64.neon.vld1x2.")) return Intrinsic::aarch64_
			neon_vld1x2;
			if (NameR.startswith("arch64.neon.vcltz.")) return Intrinsic::aarch64_n
			eon_vcltz;
			if (NameR.startswith("arch64.neon.vclez.")) return Intrinsic::aarch64_n
			eon_vclez;
			if (NameR.startswith("arch64.neon.vchs.")) return Intrinsic::aarch64_ne
			on_vchs;
			if (NameR.startswith("arch64.neon.vchi.")) return Intrinsic::aarch64_ne
			on_vchi;
			if (NameR.startswith("arch64.neon.vcgt.")) return Intrinsic::aarch64_ne
			on_vcgt;
			if (NameR.startswith("arch64.neon.vcge.")) return Intrinsic::aarch64_ne
			on_vcge;
			if (NameR.startswith("arch64.neon.vceq.")) return Intrinsic::aarch64_ne
			on_vceq;
			if (NameR.startswith("arch64.neon.vcagt.")) return Intrinsic::aarch64_n
			eon_vcagt;
			if (NameR.startswith("arch64.neon.vcage.")) return Intrinsic::aarch64_n
			eon_vcage;
			if (NameR.startswith("arch64.neon.vaddv.")) return Intrinsic::aarch64_n
			eon_vaddv;
			if (NameR.startswith("arch64.neon.vabd.")) return Intrinsic::aarch64_ne
			on_vabd;
			if (NameR.startswith("arch64.neon.usqadd.")) return Intrinsic::aarch64_
			neon_usqadd;
			if (NameR.startswith("arch64.neon.uminv.")) return Intrinsic::aarch64_n
			eon_uminv;
			if (NameR.startswith("arch64.neon.umaxv.")) return Intrinsic::aarch64_n
			eon_umaxv;
			if (NameR.startswith("arch64.neon.uaddlv.")) return Intrinsic::aarch64_
			neon_uaddlv;
			if (NameR.startswith("arch64.neon.suqadd.")) return Intrinsic::aarch64_
			neon_suqadd;
			if (NameR.startswith("arch64.neon.sminv.")) return Intrinsic::aarch64_n
			eon_sminv;
			if (NameR.startswith("arch64.neon.smaxv.")) return Intrinsic::aarch64_n
			eon_smaxv;
			if (NameR.startswith("arch64.neon.saddlv.")) return Intrinsic::aarch64_
			neon_saddlv;
			if (NameR.startswith("arch64.neon.rbit.")) return Intrinsic::aarch64_ne
			on_rbit;
			if (NameR.startswith("arch64.neon.fsqrt.")) return Intrinsic::aarch64_n
			eon_fsqrt;
			if (NameR.startswith("arch64.neon.frintn.")) return Intrinsic::aarch64_
			neon_frintn;
			if (NameR.startswith("arch64.neon.fcvtzu.")) return Intrinsic::aarch64_
			neon_fcvtzu;
			if (NameR.startswith("arch64.neon.fcvtzs.")) return Intrinsic::aarch64_
			neon_fcvtzs;
			if (NameR.startswith("arch64.neon.fcvtxn.")) return Intrinsic::aarch64_
			neon_fcvtxn;
			if (NameR.startswith("arch64.neon.fcvtpu.")) return Intrinsic::aarch64_
			neon_fcvtpu;
			if (NameR.startswith("arch64.neon.fcvtps.")) return Intrinsic::aarch64_
			neon_fcvtps;
			if (NameR.startswith("arch64.neon.fcvtnu.")) return Intrinsic::aarch64_
			neon_fcvtnu;
			if (NameR.startswith("arch64.neon.fcvtns.")) return Intrinsic::aarch64_
			neon_fcvtns;
			if (NameR.startswith("arch64.neon.fcvtmu.")) return Intrinsic::aarch64_
			neon_fcvtmu;
			if (NameR.startswith("arch64.neon.fcvtms.")) return Intrinsic::aarch64_
			neon_fcvtms;
			if (NameR.startswith("arch64.neon.fcvtau.")) return Intrinsic::aarch64_
			neon_fcvtau;
			if (NameR.startswith("arch64.neon.fcvtas.")) return Intrinsic::aarch64_
			neon_fcvtas;
	switch (NameR.size()) {		switch (NameR.size()) {
	default: break;		default: break;
	case 6: // 3 strings to match.		case 6: // 5 strings to match.
	if (memcmp(NameR.data()+0, "rm.", 3))		if (memcmp(NameR.data()+0, "rm.", 3))
	break;		break;
	switch (NameR[3]) {		switch (NameR[3]) {
	default: break;		default: break;
	case 'c': // 1 string to match.		case 'c': // 1 string to match.
	if (memcmp(NameR.data()+4, "dp", 2))		if (memcmp(NameR.data()+4, "dp", 2))
	break;		break;
	return Intrinsic::arm_cdp; // "rm.cdp"		return Intrinsic::arm_cdp; // "rm.cdp"
			case 'd': // 2 strings to match.
			switch (NameR[4]) {
			default: break;
			case 'm': // 1 string to match.
			if (NameR[5] != 'b')
			break;
			return Intrinsic::arm_dmb; // "rm.dmb"
			case 's': // 1 string to match.
			if (NameR[5] != 'b')
			break;
			return Intrinsic::arm_dsb; // "rm.dsb"
			}
			break;
	case 'm': // 2 strings to match.		case 'm': // 2 strings to match.
	switch (NameR[4]) {		switch (NameR[4]) {
	default: break;		default: break;
	case 'c': // 1 string to match.		case 'c': // 1 string to match.
	if (NameR[5] != 'r')		if (NameR[5] != 'r')
	break;		break;
	return Intrinsic::arm_mcr; // "rm.mcr"		return Intrinsic::arm_mcr; // "rm.mcr"
	case 'r': // 1 string to match.		case 'r': // 1 string to match.
	if (NameR[5] != 'c')		if (NameR[5] != 'c')
	break;		break;
	return Intrinsic::arm_mrc; // "rm.mrc"		return Intrinsic::arm_mrc; // "rm.mrc"
	}		}
	break;		break;
	}		}
	break;		break;
	case 7: // 8 strings to match.		case 7: // 9 strings to match.
	if (memcmp(NameR.data()+0, "rm.", 3))		if (memcmp(NameR.data()+0, "rm.", 3))
	break;		break;
	switch (NameR[3]) {		switch (NameR[3]) {
	default: break;		default: break;
	case 'c': // 1 string to match.		case 'c': // 1 string to match.
	if (memcmp(NameR.data()+4, "dp2", 3))		if (memcmp(NameR.data()+4, "dp2", 3))
	break;		break;
	return Intrinsic::arm_cdp2; // "rm.cdp2"		return Intrinsic::arm_cdp2; // "rm.cdp2"
	case 'm': // 3 strings to match.		case 'm': // 3 strings to match.
	switch (NameR[4]) {		switch (NameR[4]) {
	skipping to change at line 5370		skipping to change at line 7295
	case 'a': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(NameR.data()+5, "dd", 2))		if (memcmp(NameR.data()+5, "dd", 2))
	break;		break;
	return Intrinsic::arm_qadd; // "rm.qadd"		return Intrinsic::arm_qadd; // "rm.qadd"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(NameR.data()+5, "ub", 2))		if (memcmp(NameR.data()+5, "ub", 2))
	break;		break;
	return Intrinsic::arm_qsub; // "rm.qsub"		return Intrinsic::arm_qsub; // "rm.qsub"
	}		}
	break;		break;
	case 's': // 1 string to match.		case 's': // 2 strings to match.
	if (memcmp(NameR.data()+4, "sat", 3))		switch (NameR[4]) {
	break;		default: break;
	return Intrinsic::arm_ssat; // "rm.ssat"		case 'e': // 1 string to match.
			if (memcmp(NameR.data()+5, "vl", 2))
			break;
			return Intrinsic::arm_sevl; // "rm.sevl"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+5, "at", 2))
			break;
			return Intrinsic::arm_ssat; // "rm.ssat"
			}
			break;
	case 'u': // 1 string to match.		case 'u': // 1 string to match.
	if (memcmp(NameR.data()+4, "sat", 3))		if (memcmp(NameR.data()+4, "sat", 3))
	break;		break;
	return Intrinsic::arm_usat; // "rm.usat"		return Intrinsic::arm_usat; // "rm.usat"
	}		}
	break;		break;
	case 8: // 1 string to match.		case 8: // 2 strings to match.
	if (memcmp(NameR.data()+0, "rm.mcrr2", 8))		if (memcmp(NameR.data()+0, "rm.", 3))
	break;		break;
	return Intrinsic::arm_mcrr2; // "rm.mcrr2"		switch (NameR[3]) {
	case 9: // 2 strings to match.		default: break;
			case 'c': // 1 string to match.
			if (memcmp(NameR.data()+4, "lrex", 4))
			break;
			return Intrinsic::arm_clrex; // "rm.clrex"
			case 'm': // 1 string to match.
			if (memcmp(NameR.data()+4, "crr2", 4))
			break;
			return Intrinsic::arm_mcrr2; // "rm.mcrr2"
			}
			break;
			case 9: // 5 strings to match.
	if (memcmp(NameR.data()+0, "rm.", 3))		if (memcmp(NameR.data()+0, "rm.", 3))
	break;		break;
	switch (NameR[3]) {		switch (NameR[3]) {
	default: break;		default: break;
			case 'c': // 3 strings to match.
			if (memcmp(NameR.data()+4, "rc32", 4))
			break;
			switch (NameR[8]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::arm_crc32b; // "rm.crc32b"
			case 'h': // 1 string to match.
			return Intrinsic::arm_crc32h; // "rm.crc32h"
			case 'w': // 1 string to match.
			return Intrinsic::arm_crc32w; // "rm.crc32w"
			}
			break;
	case 'l': // 1 string to match.		case 'l': // 1 string to match.
	if (memcmp(NameR.data()+4, "drexd", 5))		if (memcmp(NameR.data()+4, "drexd", 5))
	break;		break;
	return Intrinsic::arm_ldrexd; // "rm.ldrexd"		return Intrinsic::arm_ldrexd; // "rm.ldrexd"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(NameR.data()+4, "trexd", 5))		if (memcmp(NameR.data()+4, "trexd", 5))
	break;		break;
	return Intrinsic::arm_strexd; // "rm.strexd"		return Intrinsic::arm_strexd; // "rm.strexd"
	}		}
	break;		break;
			case 10: // 3 strings to match.
			if (memcmp(NameR.data()+0, "rm.crc32c", 9))
			break;
			switch (NameR[9]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::arm_crc32cb; // "rm.crc32cb"
			case 'h': // 1 string to match.
			return Intrinsic::arm_crc32ch; // "rm.crc32ch"
			case 'w': // 1 string to match.
			return Intrinsic::arm_crc32cw; // "rm.crc32cw"
			}
			break;
	case 12: // 2 strings to match.		case 12: // 2 strings to match.
	if (memcmp(NameR.data()+0, "rm.", 3))		if (memcmp(NameR.data()+0, "rm.", 3))
	break;		break;
	switch (NameR[3]) {		switch (NameR[3]) {
	default: break;		default: break;
	case 'g': // 1 string to match.		case 'g': // 1 string to match.
	if (memcmp(NameR.data()+4, "et.fpscr", 8))		if (memcmp(NameR.data()+4, "et.fpscr", 8))
	break;		break;
	return Intrinsic::arm_get_fpscr; // "rm.get.fpscr"		return Intrinsic::arm_get_fpscr; // "rm.get.fpscr"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	skipping to change at line 5472		skipping to change at line 7443
	switch (NameR[13]) {		switch (NameR[13]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::arm_neon_vacgtd; // "rm.neon.vacgtd"		return Intrinsic::arm_neon_vacgtd; // "rm.neon.vacgtd"
	case 'q': // 1 string to match.		case 'q': // 1 string to match.
	return Intrinsic::arm_neon_vacgtq; // "rm.neon.vacgtq"		return Intrinsic::arm_neon_vacgtq; // "rm.neon.vacgtq"
	}		}
	break;		break;
	}		}
	break;		break;
	case 16: // 1 string to match.		case 16: // 3 strings to match.
	if (memcmp(NameR.data()+0, "djust.trampoline", 16))		switch (NameR[0]) {
	break;
	return Intrinsic::adjust_trampoline; // "djust.trampoline"
	case 17: // 3 strings to match.
	if (memcmp(NameR.data()+0, "rm.", 3))
	break;
	switch (NameR[3]) {
	default: break;		default: break;
	case 'n': // 2 strings to match.		case 'a': // 2 strings to match.
	if (memcmp(NameR.data()+4, "eon.vcvt", 8))		if (memcmp(NameR.data()+1, "rch64.neon.v", 12))
	break;		break;
	switch (NameR[12]) {		switch (NameR[13]) {
	default: break;		default: break;
	case 'f': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(NameR.data()+13, "p2hf", 4))		if (memcmp(NameR.data()+14, "bs", 2))
	break;		break;
	return Intrinsic::arm_neon_vcvtfp2hf; // "rm.neon.vcvtfp2		return Intrinsic::aarch64_neon_vabs; // "arch64.neon.vabs"
	hf"		case 'n': // 1 string to match.
	case 'h': // 1 string to match.		if (memcmp(NameR.data()+14, "eg", 2))
	if (memcmp(NameR.data()+13, "f2fp", 4))
	break;		break;
	return Intrinsic::arm_neon_vcvthf2fp; // "rm.neon.vcvthf2 fp"		return Intrinsic::aarch64_neon_vneg; // "arch64.neon.vneg"
	}		}
	break;		break;
	case 't': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+4, "hread.pointer", 13))		if (memcmp(NameR.data()+1, "just.trampoline", 15))
	break;		break;
	return Intrinsic::arm_thread_pointer; // "rm.thread.pointer"		return Intrinsic::adjust_trampoline; // "djust.trampoline"
	}		}
	break;		break;
	}		case 17: // 9 strings to match.
	break; // end of 'a' case.
	case 'b':
	if (NameR.startswith("swap.")) return Intrinsic::bswap;
	break; // end of 'b' case.
	case 'c':
	if (NameR.startswith("eil.")) return Intrinsic::ceil;
	if (NameR.startswith("onvertff.")) return Intrinsic::convertff;
	if (NameR.startswith("onvertfsi.")) return Intrinsic::convertfsi;
	if (NameR.startswith("onvertfui.")) return Intrinsic::convertfui;
	if (NameR.startswith("onvertsif.")) return Intrinsic::convertsif;
	if (NameR.startswith("onvertss.")) return Intrinsic::convertss;
	if (NameR.startswith("onvertsu.")) return Intrinsic::convertsu;
	if (NameR.startswith("onvertuif.")) return Intrinsic::convertuif;
	if (NameR.startswith("onvertus.")) return Intrinsic::convertus;
	if (NameR.startswith("onvertuu.")) return Intrinsic::convertuu;
	if (NameR.startswith("os.")) return Intrinsic::cos;
	if (NameR.startswith("tlz.")) return Intrinsic::ctlz;
	if (NameR.startswith("tpop.")) return Intrinsic::ctpop;
	if (NameR.startswith("ttz.")) return Intrinsic::cttz;
	switch (NameR.size()) {
	default: break;
	case 14: // 1 string to match.
	if (memcmp(NameR.data()+0, "onvert.to.fp16", 14))
	break;
	return Intrinsic::convert_to_fp16; // "onvert.to.fp16"
	case 15: // 1 string to match.
	if (memcmp(NameR.data()+0, "uda.syncthreads", 15))
	break;
	return Intrinsic::cuda_syncthreads; // "uda.syncthreads"
	case 16: // 1 string to match.
	if (memcmp(NameR.data()+0, "onvert.from.fp16", 16))
	break;
	return Intrinsic::convert_from_fp16; // "onvert.from.fp16"
	}
	break; // end of 'c' case.
	case 'd':
	switch (NameR.size()) {
	default: break;
	case 8: // 3 strings to match.
	switch (NameR[0]) {		switch (NameR[0]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'a': // 6 strings to match.
	if (memcmp(NameR.data()+1, "g.value", 7))		if (memcmp(NameR.data()+1, "rch64.neon.", 11))
	break;		break;
	return Intrinsic::dbg_value; // "bg.value"		switch (NameR[12]) {
	case 'e': // 1 string to match.		default: break;
	if (memcmp(NameR.data()+1, "bugtrap", 7))		case 's': // 3 strings to match.
			if (memcmp(NameR.data()+13, "ha1", 3))
			break;
			switch (NameR[16]) {
			default: break;
			case 'c': // 1 string to match.
			return Intrinsic::aarch64_neon_sha1c; // "arch64.neon.sha
			1c"
			case 'm': // 1 string to match.
			return Intrinsic::aarch64_neon_sha1m; // "arch64.neon.sha
			1m"
			case 'p': // 1 string to match.
			return Intrinsic::aarch64_neon_sha1p; // "arch64.neon.sha
			1p"
			}
	break;		break;
	return Intrinsic::debugtrap; // "ebugtrap"		case 'v': // 3 strings to match.
	case 'o': // 1 string to match.		if (NameR[13] != 'p')
	if (memcmp(NameR.data()+1, "nothing", 7))		break;
			switch (NameR[14]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(NameR.data()+15, "dd", 2))
			break;
			return Intrinsic::aarch64_neon_vpadd; // "arch64.neon.vpa
			dd"
			case 'm': // 2 strings to match.
			switch (NameR[15]) {
			default: break;
			case 'a': // 1 string to match.
			if (NameR[16] != 'x')
			break;
			return Intrinsic::aarch64_neon_vpmax; // "arch64.neon.vpm
			ax"
			case 'i': // 1 string to match.
			if (NameR[16] != 'n')
			break;
			return Intrinsic::aarch64_neon_vpmin; // "arch64.neon.vpm
			in"
			}
			break;
			}
	break;		break;
	return Intrinsic::donothing; // "onothing"		}
	}
	break;
	case 10: // 1 string to match.
	if (memcmp(NameR.data()+0, "bg.declare", 10))
	break;
	return Intrinsic::dbg_declare; // "bg.declare"
	}
	break; // end of 'd' case.
	case 'e':
	if (NameR.startswith("xp.")) return Intrinsic::exp;
	if (NameR.startswith("xp2.")) return Intrinsic::exp2;
	if (NameR.startswith("xpect.")) return Intrinsic::expect;
	switch (NameR.size()) {
	default: break;
	case 11: // 2 strings to match.
	if (memcmp(NameR.data()+0, "h.", 2))
	break;		break;
	switch (NameR[2]) {		case 'r': // 3 strings to match.
	default: break;		if (memcmp(NameR.data()+1, "m.", 2))
	case 'd': // 1 string to match.
	if (memcmp(NameR.data()+3, "warf.cfa", 8))
	break;		break;
	return Intrinsic::eh_dwarf_cfa; // "h.dwarf.cfa"		switch (NameR[3]) {
	case 's': // 1 string to match.		default: break;
	if (memcmp(NameR.data()+3, "jlj.lsda", 8))		case 'n': // 2 strings to match.
			if (memcmp(NameR.data()+4, "eon.vcvt", 8))
			break;
			switch (NameR[12]) {
			default: break;
			case 'f': // 1 string to match.
			if (memcmp(NameR.data()+13, "p2hf", 4))
			break;
			return Intrinsic::arm_neon_vcvtfp2hf; // "rm.neon.vcvtfp2
			hf"
			case 'h': // 1 string to match.
			if (memcmp(NameR.data()+13, "f2fp", 4))
			break;
			return Intrinsic::arm_neon_vcvthf2fp; // "rm.neon.vcvthf2
			fp"
			}
	break;		break;
	return Intrinsic::eh_sjlj_lsda; // "h.sjlj.lsda"		case 't': // 1 string to match.
			if (memcmp(NameR.data()+4, "hread.pointer", 13))
			break;
			return Intrinsic::arm_thread_pointer; // "rm.thread.point
			er"
			}
			break;
	}		}
	break;		break;
	case 12: // 3 strings to match.		case 18: // 11 strings to match.
	if (memcmp(NameR.data()+0, "h.", 2))		if (memcmp(NameR.data()+0, "arch64.neon.v", 13))
	break;		break;
	switch (NameR[2]) {		switch (NameR[13]) {
	default: break;		default: break;
	case 'r': // 2 strings to match.		case 'a': // 4 strings to match.
	if (memcmp(NameR.data()+3, "eturn.i", 7))		switch (NameR[14]) {
	break;
	switch (NameR[10]) {
	default: break;		default: break;
	case '3': // 1 string to match.		case 'c': // 2 strings to match.
	if (NameR[11] != '2')		if (NameR[15] != 'g')
	break;		break;
	return Intrinsic::eh_return_i32; // "h.return.i32"		switch (NameR[16]) {
	case '6': // 1 string to match.		default: break;
	if (NameR[11] != '4')		case 'e': // 1 string to match.
			if (NameR[17] != 'q')
			break;
			return Intrinsic::aarch64_neon_vacgeq; // "arch64.neon.vac
			geq"
			case 't': // 1 string to match.
			if (NameR[17] != 'q')
			break;
			return Intrinsic::aarch64_neon_vacgtq; // "arch64.neon.vac
			gtq"
			}
			break;
			case 'd': // 2 strings to match.
			if (memcmp(NameR.data()+15, "dd", 2))
	break;		break;
	return Intrinsic::eh_return_i64; // "h.return.i64"		switch (NameR[17]) {
			default: break;
			case 's': // 1 string to match.
			return Intrinsic::aarch64_neon_vaddds; // "arch64.neon.vad
			dds"
			case 'u': // 1 string to match.
			return Intrinsic::aarch64_neon_vadddu; // "arch64.neon.vad
			ddu"
			}
			break;
			}
			break;
			case 'p': // 3 strings to match.
			switch (NameR[14]) {
			default: break;
			case 'f': // 1 string to match.
			if (memcmp(NameR.data()+15, "add", 3))
			break;
			return Intrinsic::aarch64_neon_vpfadd; // "arch64.neon.vpf
			add"
			case 'm': // 2 strings to match.
			switch (NameR[15]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(NameR.data()+16, "xq", 2))
			break;
			return Intrinsic::aarch64_neon_vpmaxq; // "arch64.neon.vpm
			axq"
			case 'i': // 1 string to match.
			if (memcmp(NameR.data()+16, "nq", 2))
			break;
			return Intrinsic::aarch64_neon_vpminq; // "arch64.neon.vpm
			inq"
			}
			break;
			}
			break;
			case 's': // 4 strings to match.
			switch (NameR[14]) {
			default: break;
			case 'h': // 2 strings to match.
			if (memcmp(NameR.data()+15, "ld", 2))
			break;
			switch (NameR[17]) {
			default: break;
			case 's': // 1 string to match.
			return Intrinsic::aarch64_neon_vshlds; // "arch64.neon.vsh
			lds"
			case 'u': // 1 string to match.
			return Intrinsic::aarch64_neon_vshldu; // "arch64.neon.vsh
			ldu"
			}
			break;
			case 'u': // 2 strings to match.
			if (memcmp(NameR.data()+15, "bd", 2))
			break;
			switch (NameR[17]) {
			default: break;
			case 's': // 1 string to match.
			return Intrinsic::aarch64_neon_vsubds; // "arch64.neon.vsu
			bds"
			case 'u': // 1 string to match.
			return Intrinsic::aarch64_neon_vsubdu; // "arch64.neon.vsu
			bdu"
			}
			break;
			}
			break;
			}
			break;
			case 19: // 4 strings to match.
			if (memcmp(NameR.data()+0, "arch64.neon.v", 13))
			break;
			switch (NameR[13]) {
			default: break;
			case 'p': // 1 string to match.
			if (memcmp(NameR.data()+14, "faddq", 5))
			break;
			return Intrinsic::aarch64_neon_vpfaddq; // "arch64.neon.vpf
			addq"
			case 'r': // 2 strings to match.
			if (memcmp(NameR.data()+14, "shld", 4))
			break;
			switch (NameR[18]) {
			default: break;
			case 's': // 1 string to match.
			return Intrinsic::aarch64_neon_vrshlds; // "arch64.neon.vrs
			hlds"
			case 'u': // 1 string to match.
			return Intrinsic::aarch64_neon_vrshldu; // "arch64.neon.vrs
			hldu"
			}
			break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+14, "hld.n", 5))
			break;
			return Intrinsic::aarch64_neon_vshld_n; // "arch64.neon.vsh
			ld.n"
			}
			break;
			case 20: // 6 strings to match.
			if (memcmp(NameR.data()+0, "arch64.neon.v", 13))
			break;
			switch (NameR[13]) {
			default: break;
			case 'p': // 2 strings to match.
			if (memcmp(NameR.data()+14, "fm", 2))
			break;
			switch (NameR[16]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(NameR.data()+17, "xnm", 3))
			break;
			return Intrinsic::aarch64_neon_vpfmaxnm; // "arch64.neon.vpf
			maxnm"
			case 'i': // 1 string to match.
			if (memcmp(NameR.data()+17, "nnm", 3))
			break;
			return Intrinsic::aarch64_neon_vpfminnm; // "arch64.neon.vpf
			minnm"
			}
			break;
			case 's': // 4 strings to match.
			switch (NameR[14]) {
			default: break;
			case 'h': // 2 strings to match.
			if (memcmp(NameR.data()+15, "rd", 2))
			break;
			switch (NameR[17]) {
			default: break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+18, ".n", 2))
			break;
			return Intrinsic::aarch64_neon_vshrds_n; // "arch64.neon.vsh
			rds.n"
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+18, ".n", 2))
			break;
			return Intrinsic::aarch64_neon_vshrdu_n; // "arch64.neon.vsh
			rdu.n"
			}
			break;
			case 'r': // 2 strings to match.
			if (memcmp(NameR.data()+15, "ad", 2))
			break;
			switch (NameR[17]) {
			default: break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+18, ".n", 2))
			break;
			return Intrinsic::aarch64_neon_vsrads_n; // "arch64.neon.vsr
			ads.n"
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+18, ".n", 2))
			break;
			return Intrinsic::aarch64_neon_vsradu_n; // "arch64.neon.vsr
			adu.n"
			}
			break;
			}
			break;
			}
			break;
			case 21: // 4 strings to match.
			if (memcmp(NameR.data()+0, "arch64.neon.v", 13))
			break;
			switch (NameR[13]) {
			default: break;
			case 'p': // 2 strings to match.
			if (memcmp(NameR.data()+14, "fm", 2))
			break;
			switch (NameR[16]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(NameR.data()+17, "xnmq", 4))
			break;
			return Intrinsic::aarch64_neon_vpfmaxnmq; // "arch64.neon.vpf
			maxnmq"
			case 'i': // 1 string to match.
			if (memcmp(NameR.data()+17, "nnmq", 4))
			break;
			return Intrinsic::aarch64_neon_vpfminnmq; // "arch64.neon.vpf
			minnmq"
			}
			break;
			case 'r': // 2 strings to match.
			if (memcmp(NameR.data()+14, "srad", 4))
			break;
			switch (NameR[18]) {
			default: break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+19, ".n", 2))
			break;
			return Intrinsic::aarch64_neon_vrsrads_n; // "arch64.neon.vrs
			rads.n"
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+19, ".n", 2))
			break;
			return Intrinsic::aarch64_neon_vrsradu_n; // "arch64.neon.vrs
			radu.n"
			}
			break;
			}
			break;
			case 23: // 4 strings to match.
			if (memcmp(NameR.data()+0, "arch64.neon.vcvtf", 17))
			break;
			switch (NameR[17]) {
			default: break;
			case '3': // 2 strings to match.
			if (memcmp(NameR.data()+18, "2.", 2))
			break;
			switch (NameR[20]) {
			default: break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+21, "32", 2))
			break;
			return Intrinsic::aarch64_neon_vcvtf32_s32; // "arch64.neon.vcv
			tf32.s32"
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+21, "32", 2))
			break;
			return Intrinsic::aarch64_neon_vcvtf32_u32; // "arch64.neon.vcv
			tf32.u32"
			}
			break;
			case '6': // 2 strings to match.
			if (memcmp(NameR.data()+18, "4.", 2))
			break;
			switch (NameR[20]) {
			default: break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+21, "64", 2))
			break;
			return Intrinsic::aarch64_neon_vcvtf64_s64; // "arch64.neon.vcv
			tf64.s64"
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+21, "64", 2))
			break;
			return Intrinsic::aarch64_neon_vcvtf64_u64; // "arch64.neon.vcv
			tf64.u64"
			}
			break;
			}
			break;
			case 25: // 4 strings to match.
			if (memcmp(NameR.data()+0, "arch64.neon.vcvtf", 17))
			break;
			switch (NameR[17]) {
			default: break;
			case '3': // 2 strings to match.
			if (memcmp(NameR.data()+18, "2.n.", 4))
			break;
			switch (NameR[22]) {
			default: break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+23, "32", 2))
			break;
			return Intrinsic::aarch64_neon_vcvtf32_n_s32; // "arch64.
			neon.vcvtf32.n.s32"
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+23, "32", 2))
			break;
			return Intrinsic::aarch64_neon_vcvtf32_n_u32; // "arch64.
			neon.vcvtf32.n.u32"
			}
			break;
			case '6': // 2 strings to match.
			if (memcmp(NameR.data()+18, "4.n.", 4))
			break;
			switch (NameR[22]) {
			default: break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+23, "64", 2))
			break;
			return Intrinsic::aarch64_neon_vcvtf64_n_s64; // "arch64.
			neon.vcvtf64.n.s64"
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+23, "64", 2))
			break;
			return Intrinsic::aarch64_neon_vcvtf64_n_u64; // "arch64.
			neon.vcvtf64.n.u64"
			}
			break;
			}
			break;
			case 27: // 4 strings to match.
			if (memcmp(NameR.data()+0, "arch64.neon.vcvt", 16))
			break;
			switch (NameR[16]) {
			default: break;
			case 'd': // 2 strings to match.
			if (memcmp(NameR.data()+17, ".n.", 3))
			break;
			switch (NameR[20]) {
			default: break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+21, "64.f64", 6))
			break;
			return Intrinsic::aarch64_neon_vcvtd_n_s64_f64; // "arch64.
			neon.vcvtd.n.s64.f64"
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+21, "64.f64", 6))
			break;
			return Intrinsic::aarch64_neon_vcvtd_n_u64_f64; // "arch64.
			neon.vcvtd.n.u64.f64"
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(NameR.data()+17, ".n.", 3))
			break;
			switch (NameR[20]) {
			default: break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+21, "32.f32", 6))
			break;
			return Intrinsic::aarch64_neon_vcvts_n_s32_f32; // "arch64.
			neon.vcvts.n.s32.f32"
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+21, "32.f32", 6))
			break;
			return Intrinsic::aarch64_neon_vcvts_n_u32_f32; // "arch64.
			neon.vcvts.n.u32.f32"
			}
			break;
			}
			break;
			}
			break; // end of 'a' case.
			case 'b':
			if (NameR.startswith("swap.")) return Intrinsic::bswap;
			break; // end of 'b' case.
			case 'c':
			if (NameR.startswith("ttz.")) return Intrinsic::cttz;
			if (NameR.startswith("tpop.")) return Intrinsic::ctpop;
			if (NameR.startswith("tlz.")) return Intrinsic::ctlz;
			if (NameR.startswith("os.")) return Intrinsic::cos;
			if (NameR.startswith("opysign.")) return Intrinsic::copysign;
			if (NameR.startswith("onvertuu.")) return Intrinsic::convertuu;
			if (NameR.startswith("onvertus.")) return Intrinsic::convertus;
			if (NameR.startswith("onvertuif.")) return Intrinsic::convertuif;
			if (NameR.startswith("onvertsu.")) return Intrinsic::convertsu;
			if (NameR.startswith("onvertss.")) return Intrinsic::convertss;
			if (NameR.startswith("onvertsif.")) return Intrinsic::convertsif;
			if (NameR.startswith("onvertfui.")) return Intrinsic::convertfui;
			if (NameR.startswith("onvertfsi.")) return Intrinsic::convertfsi;
			if (NameR.startswith("onvertff.")) return Intrinsic::convertff;
			if (NameR.startswith("eil.")) return Intrinsic::ceil;
			switch (NameR.size()) {
			default: break;
			case 14: // 1 string to match.
			if (memcmp(NameR.data()+0, "onvert.to.fp16", 14))
			break;
			return Intrinsic::convert_to_fp16; // "onvert.to.fp16"
			case 15: // 1 string to match.
			if (memcmp(NameR.data()+0, "uda.syncthreads", 15))
			break;
			return Intrinsic::cuda_syncthreads; // "uda.syncthreads"
			case 16: // 1 string to match.
			if (memcmp(NameR.data()+0, "onvert.from.fp16", 16))
			break;
			return Intrinsic::convert_from_fp16; // "onvert.from.fp16"
			}
			break; // end of 'c' case.
			case 'd':
			switch (NameR.size()) {
			default: break;
			case 8: // 3 strings to match.
			switch (NameR[0]) {
			default: break;
			case 'b': // 1 string to match.
			if (memcmp(NameR.data()+1, "g.value", 7))
			break;
			return Intrinsic::dbg_value; // "bg.value"
			case 'e': // 1 string to match.
			if (memcmp(NameR.data()+1, "bugtrap", 7))
			break;
			return Intrinsic::debugtrap; // "ebugtrap"
			case 'o': // 1 string to match.
			if (memcmp(NameR.data()+1, "nothing", 7))
			break;
			return Intrinsic::donothing; // "onothing"
			}
			break;
			case 10: // 1 string to match.
			if (memcmp(NameR.data()+0, "bg.declare", 10))
			break;
			return Intrinsic::dbg_declare; // "bg.declare"
			}
			break; // end of 'd' case.
			case 'e':
			if (NameR.startswith("xpect.")) return Intrinsic::expect;
			if (NameR.startswith("xp2.")) return Intrinsic::exp2;
			if (NameR.startswith("xp.")) return Intrinsic::exp;
			switch (NameR.size()) {
			default: break;
			case 11: // 2 strings to match.
			if (memcmp(NameR.data()+0, "h.", 2))
			break;
			switch (NameR[2]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+3, "warf.cfa", 8))
			break;
			return Intrinsic::eh_dwarf_cfa; // "h.dwarf.cfa"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+3, "jlj.lsda", 8))
			break;
			return Intrinsic::eh_sjlj_lsda; // "h.sjlj.lsda"
			}
			break;
			case 12: // 3 strings to match.
			if (memcmp(NameR.data()+0, "h.", 2))
			break;
			switch (NameR[2]) {
			default: break;
			case 'r': // 2 strings to match.
			if (memcmp(NameR.data()+3, "eturn.i", 7))
			break;
			switch (NameR[10]) {
			default: break;
			case '3': // 1 string to match.
			if (NameR[11] != '2')
			break;
			return Intrinsic::eh_return_i32; // "h.return.i32"
			case '6': // 1 string to match.
			if (NameR[11] != '4')
			break;
			return Intrinsic::eh_return_i64; // "h.return.i64"
	}		}
	break;		break;
	case 't': // 1 string to match.		case 't': // 1 string to match.
	if (memcmp(NameR.data()+3, "ypeid.for", 9))		if (memcmp(NameR.data()+3, "ypeid.for", 9))
	break;		break;
	return Intrinsic::eh_typeid_for; // "h.typeid.for"		return Intrinsic::eh_typeid_for; // "h.typeid.for"
	}		}
	break;		break;
	case 13: // 2 strings to match.		case 13: // 2 strings to match.
	if (memcmp(NameR.data()+0, "h.", 2))		if (memcmp(NameR.data()+0, "h.", 2))
	skipping to change at line 5634		skipping to change at line 7993
	}		}
	break;		break;
	case 14: // 1 string to match.		case 14: // 1 string to match.
	if (memcmp(NameR.data()+0, "h.sjlj.longjmp", 14))		if (memcmp(NameR.data()+0, "h.sjlj.longjmp", 14))
	break;		break;
	return Intrinsic::eh_sjlj_longjmp; // "h.sjlj.longjmp"		return Intrinsic::eh_sjlj_longjmp; // "h.sjlj.longjmp"
	case 15: // 1 string to match.		case 15: // 1 string to match.
	if (memcmp(NameR.data()+0, "h.sjlj.callsite", 15))		if (memcmp(NameR.data()+0, "h.sjlj.callsite", 15))
	break;		break;
	return Intrinsic::eh_sjlj_callsite; // "h.sjlj.callsite"		return Intrinsic::eh_sjlj_callsite; // "h.sjlj.callsite"
			case 20: // 1 string to match.
			if (memcmp(NameR.data()+0, "xperimental.stackmap", 20))
			break;
			return Intrinsic::experimental_stackmap; // "xperimental.stackmap"
	case 22: // 1 string to match.		case 22: // 1 string to match.
	if (memcmp(NameR.data()+0, "h.sjlj.functioncontext", 22))		if (memcmp(NameR.data()+0, "h.sjlj.functioncontext", 22))
	break;		break;
	return Intrinsic::eh_sjlj_functioncontext; // "h.sjlj.function context"		return Intrinsic::eh_sjlj_functioncontext; // "h.sjlj.function context"
			case 26: // 1 string to match.
			if (memcmp(NameR.data()+0, "xperimental.patchpoint.i64", 26))
			break;
			return Intrinsic::experimental_patchpoint_i64; // "xperimental.pat
			chpoint.i64"
			case 27: // 1 string to match.
			if (memcmp(NameR.data()+0, "xperimental.patchpoint.void", 27))
			break;
			return Intrinsic::experimental_patchpoint_void; // "xperimental.pat
			chpoint.void"
	}		}
	break; // end of 'e' case.		break; // end of 'e' case.
	case 'f':		case 'f':
	if (NameR.startswith("abs.")) return Intrinsic::fabs;
	if (NameR.startswith("loor.")) return Intrinsic::floor;
	if (NameR.startswith("ma.")) return Intrinsic::fma;
	if (NameR.startswith("muladd.")) return Intrinsic::fmuladd;		if (NameR.startswith("muladd.")) return Intrinsic::fmuladd;
			if (NameR.startswith("ma.")) return Intrinsic::fma;
			if (NameR.startswith("loor.")) return Intrinsic::floor;
			if (NameR.startswith("abs.")) return Intrinsic::fabs;
	switch (NameR.size()) {		switch (NameR.size()) {
	default: break;		default: break;
	case 9: // 1 string to match.		case 9: // 1 string to match.
	if (memcmp(NameR.data()+0, "lt.rounds", 9))		if (memcmp(NameR.data()+0, "lt.rounds", 9))
	break;		break;
	return Intrinsic::flt_rounds; // "lt.rounds"		return Intrinsic::flt_rounds; // "lt.rounds"
	case 11: // 1 string to match.		case 11: // 1 string to match.
	if (memcmp(NameR.data()+0, "rameaddress", 11))		if (memcmp(NameR.data()+0, "rameaddress", 11))
	break;		break;
	return Intrinsic::frameaddress; // "rameaddress"		return Intrinsic::frameaddress; // "rameaddress"
	skipping to change at line 12472		skipping to change at line 14843
	return Intrinsic::init_trampoline; // "nit.trampoline"		return Intrinsic::init_trampoline; // "nit.trampoline"
	case 'v': // 1 string to match.		case 'v': // 1 string to match.
	if (memcmp(NameR.data()+2, "ariant.start", 12))		if (memcmp(NameR.data()+2, "ariant.start", 12))
	break;		break;
	return Intrinsic::invariant_start; // "nvariant.start"		return Intrinsic::invariant_start; // "nvariant.start"
	}		}
	break;		break;
	}		}
	break; // end of 'i' case.		break; // end of 'i' case.
	case 'l':		case 'l':
	if (NameR.startswith("og.")) return Intrinsic::log;
	if (NameR.startswith("og10.")) return Intrinsic::log10;
	if (NameR.startswith("og2.")) return Intrinsic::log2;		if (NameR.startswith("og2.")) return Intrinsic::log2;
			if (NameR.startswith("og10.")) return Intrinsic::log10;
			if (NameR.startswith("og.")) return Intrinsic::log;
	switch (NameR.size()) {		switch (NameR.size()) {
	default: break;		default: break;
	case 6: // 1 string to match.		case 6: // 1 string to match.
	if (memcmp(NameR.data()+0, "ongjmp", 6))		if (memcmp(NameR.data()+0, "ongjmp", 6))
	break;		break;
	return Intrinsic::longjmp; // "ongjmp"		return Intrinsic::longjmp; // "ongjmp"
	case 11: // 1 string to match.		case 11: // 1 string to match.
	if (memcmp(NameR.data()+0, "ifetime.end", 11))		if (memcmp(NameR.data()+0, "ifetime.end", 11))
	break;		break;
	return Intrinsic::lifetime_end; // "ifetime.end"		return Intrinsic::lifetime_end; // "ifetime.end"
	case 13: // 1 string to match.		case 13: // 1 string to match.
	if (memcmp(NameR.data()+0, "ifetime.start", 13))		if (memcmp(NameR.data()+0, "ifetime.start", 13))
	break;		break;
	return Intrinsic::lifetime_start; // "ifetime.start"		return Intrinsic::lifetime_start; // "ifetime.start"
	}		}
	break; // end of 'l' case.		break; // end of 'l' case.
	case 'm':		case 'm':
	if (NameR.startswith("emcpy.")) return Intrinsic::memcpy;
	if (NameR.startswith("emmove.")) return Intrinsic::memmove;
	if (NameR.startswith("emset.")) return Intrinsic::memset;		if (NameR.startswith("emset.")) return Intrinsic::memset;
			if (NameR.startswith("emmove.")) return Intrinsic::memmove;
			if (NameR.startswith("emcpy.")) return Intrinsic::memcpy;
	switch (NameR.size()) {		switch (NameR.size()) {
	default: break;		default: break;
	case 7: // 2 strings to match.		case 7: // 3 strings to match.
	if (memcmp(NameR.data()+0, "ips.l", 5))		if (memcmp(NameR.data()+0, "ips.l", 5))
	break;		break;
	switch (NameR[5]) {		switch (NameR[5]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'h': // 1 string to match.
	if (NameR[6] != 'x')		if (NameR[6] != 'x')
	break;		break;
	return Intrinsic::mips_lhx; // "ips.lhx"		return Intrinsic::mips_lhx; // "ips.lhx"
			case 's': // 1 string to match.
			if (NameR[6] != 'a')
			break;
			return Intrinsic::mips_lsa; // "ips.lsa"
	case 'w': // 1 string to match.		case 'w': // 1 string to match.
	if (NameR[6] != 'x')		if (NameR[6] != 'x')
	break;		break;
	return Intrinsic::mips_lwx; // "ips.lwx"		return Intrinsic::mips_lwx; // "ips.lwx"
	}		}
	break;		break;
	case 8: // 6 strings to match.		case 8: // 20 strings to match.
	if (memcmp(NameR.data()+0, "ips.", 4))		if (memcmp(NameR.data()+0, "ips.", 4))
	break;		break;
	switch (NameR[4]) {		switch (NameR[4]) {
	default: break;		default: break;
			case 'b': // 5 strings to match.
			if (memcmp(NameR.data()+5, "z.", 2))
			break;
			switch (NameR[7]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_bz_b; // "ips.bz.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_bz_d; // "ips.bz.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_bz_h; // "ips.bz.h"
			case 'v': // 1 string to match.
			return Intrinsic::mips_bz_v; // "ips.bz.v"
			case 'w': // 1 string to match.
			return Intrinsic::mips_bz_w; // "ips.bz.w"
			}
			break;
	case 'e': // 1 string to match.		case 'e': // 1 string to match.
	if (memcmp(NameR.data()+5, "xtp", 3))		if (memcmp(NameR.data()+5, "xtp", 3))
	break;		break;
	return Intrinsic::mips_extp; // "ips.extp"		return Intrinsic::mips_extp; // "ips.extp"
	case 'i': // 1 string to match.		case 'i': // 1 string to match.
	if (memcmp(NameR.data()+5, "nsv", 3))		if (memcmp(NameR.data()+5, "nsv", 3))
	break;		break;
	return Intrinsic::mips_insv; // "ips.insv"		return Intrinsic::mips_insv; // "ips.insv"
	case 'l': // 1 string to match.		case 'l': // 5 strings to match.
	if (memcmp(NameR.data()+5, "bux", 3))		switch (NameR[5]) {
			default: break;
			case 'b': // 1 string to match.
			if (memcmp(NameR.data()+6, "ux", 2))
			break;
			return Intrinsic::mips_lbux; // "ips.lbux"
			case 'd': // 4 strings to match.
			if (NameR[6] != '.')
			break;
			switch (NameR[7]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_ld_b; // "ips.ld.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_ld_d; // "ips.ld.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_ld_h; // "ips.ld.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ld_w; // "ips.ld.w"
			}
	break;		break;
	return Intrinsic::mips_lbux; // "ips.lbux"		}
			break;
	case 'm': // 3 strings to match.		case 'm': // 3 strings to match.
	switch (NameR[5]) {		switch (NameR[5]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(NameR.data()+6, "dd", 2))		if (memcmp(NameR.data()+6, "dd", 2))
	break;		break;
	return Intrinsic::mips_madd; // "ips.madd"		return Intrinsic::mips_madd; // "ips.madd"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(NameR.data()+6, "ub", 2))		if (memcmp(NameR.data()+6, "ub", 2))
	break;		break;
	return Intrinsic::mips_msub; // "ips.msub"		return Intrinsic::mips_msub; // "ips.msub"
	case 'u': // 1 string to match.		case 'u': // 1 string to match.
	if (memcmp(NameR.data()+6, "lt", 2))		if (memcmp(NameR.data()+6, "lt", 2))
	break;		break;
	return Intrinsic::mips_mult; // "ips.mult"		return Intrinsic::mips_mult; // "ips.mult"
	}		}
	break;		break;
			case 'o': // 1 string to match.
			if (memcmp(NameR.data()+5, "r.v", 3))
			break;
			return Intrinsic::mips_or_v; // "ips.or.v"
			case 's': // 4 strings to match.
			if (memcmp(NameR.data()+5, "t.", 2))
			break;
			switch (NameR[7]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_st_b; // "ips.st.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_st_d; // "ips.st.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_st_h; // "ips.st.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_st_w; // "ips.st.w"
			}
			break;
	}		}
	break;		break;
	case 9: // 8 strings to match.		case 9: // 47 strings to match.
	if (memcmp(NameR.data()+0, "ips.", 4))		if (memcmp(NameR.data()+0, "ips.", 4))
	break;		break;
	switch (NameR[4]) {		switch (NameR[4]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'a': // 3 strings to match.
	if (memcmp(NameR.data()+5, "dd", 2))		switch (NameR[5]) {
			default: break;
			case 'd': // 2 strings to match.
			if (NameR[6] != 'd')
			break;
			switch (NameR[7]) {
			default: break;
			case 's': // 1 string to match.
			if (NameR[8] != 'c')
			break;
			return Intrinsic::mips_addsc; // "ips.addsc"
			case 'w': // 1 string to match.
			if (NameR[8] != 'c')
			break;
			return Intrinsic::mips_addwc; // "ips.addwc"
			}
	break;		break;
	switch (NameR[7]) {		case 'n': // 1 string to match.
			if (memcmp(NameR.data()+6, "d.v", 3))
			break;
			return Intrinsic::mips_and_v; // "ips.and.v"
			}
			break;
			case 'b': // 6 strings to match.
			switch (NameR[5]) {
	default: break;		default: break;
	case 's': // 1 string to match.		case 'm': // 1 string to match.
	if (NameR[8] != 'c')		if (memcmp(NameR.data()+6, "z.v", 3))
	break;		break;
	return Intrinsic::mips_addsc; // "ips.addsc"		return Intrinsic::mips_bmz_v; // "ips.bmz.v"
	case 'w': // 1 string to match.		case 'n': // 5 strings to match.
	if (NameR[8] != 'c')		if (memcmp(NameR.data()+6, "z.", 2))
	break;		break;
	return Intrinsic::mips_addwc; // "ips.addwc"		switch (NameR[8]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_bnz_b; // "ips.bnz.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_bnz_d; // "ips.bnz.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_bnz_h; // "ips.bnz.h"
			case 'v': // 1 string to match.
			return Intrinsic::mips_bnz_v; // "ips.bnz.v"
			case 'w': // 1 string to match.
			return Intrinsic::mips_bnz_w; // "ips.bnz.w"
			}
			break;
			}
			break;
			case 'c': // 4 strings to match.
			if (memcmp(NameR.data()+5, "eq.", 3))
			break;
			switch (NameR[8]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_ceq_b; // "ips.ceq.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_ceq_d; // "ips.ceq.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_ceq_h; // "ips.ceq.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ceq_w; // "ips.ceq.w"
			}
			break;
			case 'f': // 2 strings to match.
			if (memcmp(NameR.data()+5, "tq.", 3))
			break;
			switch (NameR[8]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::mips_ftq_h; // "ips.ftq.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ftq_w; // "ips.ftq.w"
			}
			break;
			case 'l': // 4 strings to match.
			if (memcmp(NameR.data()+5, "di.", 3))
			break;
			switch (NameR[8]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_ldi_b; // "ips.ldi.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_ldi_d; // "ips.ldi.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_ldi_h; // "ips.ldi.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ldi_w; // "ips.ldi.w"
	}		}
	break;		break;
	case 'm': // 3 strings to match.		case 'm': // 3 strings to match.
	switch (NameR[5]) {		switch (NameR[5]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(NameR.data()+6, "ddu", 3))		if (memcmp(NameR.data()+6, "ddu", 3))
	break;		break;
	return Intrinsic::mips_maddu; // "ips.maddu"		return Intrinsic::mips_maddu; // "ips.maddu"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(NameR.data()+6, "ubu", 3))		if (memcmp(NameR.data()+6, "ubu", 3))
	break;		break;
	return Intrinsic::mips_msubu; // "ips.msubu"		return Intrinsic::mips_msubu; // "ips.msubu"
	case 'u': // 1 string to match.		case 'u': // 1 string to match.
	if (memcmp(NameR.data()+6, "ltu", 3))		if (memcmp(NameR.data()+6, "ltu", 3))
	break;		break;
	return Intrinsic::mips_multu; // "ips.multu"		return Intrinsic::mips_multu; // "ips.multu"
	}		}
	break;		break;
			case 'n': // 1 string to match.
			if (memcmp(NameR.data()+5, "or.v", 4))
			break;
			return Intrinsic::mips_nor_v; // "ips.nor.v"
			case 'o': // 1 string to match.
			if (memcmp(NameR.data()+5, "ri.b", 4))
			break;
			return Intrinsic::mips_ori_b; // "ips.ori.b"
	case 'r': // 1 string to match.		case 'r': // 1 string to match.
	if (memcmp(NameR.data()+5, "ddsp", 4))		if (memcmp(NameR.data()+5, "ddsp", 4))
	break;		break;
	return Intrinsic::mips_rddsp; // "ips.rddsp"		return Intrinsic::mips_rddsp; // "ips.rddsp"
	case 's': // 1 string to match.		case 's': // 20 strings to match.
	if (memcmp(NameR.data()+5, "hilo", 4))		switch (NameR[5]) {
			default: break;
			case 'h': // 4 strings to match.
			switch (NameR[6]) {
			default: break;
			case 'f': // 3 strings to match.
			if (NameR[7] != '.')
			break;
			switch (NameR[8]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_shf_b; // "ips.shf.b"
			case 'h': // 1 string to match.
			return Intrinsic::mips_shf_h; // "ips.shf.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_shf_w; // "ips.shf.w"
			}
			break;
			case 'i': // 1 string to match.
			if (memcmp(NameR.data()+7, "lo", 2))
			break;
			return Intrinsic::mips_shilo; // "ips.shilo"
			}
			break;
			case 'l': // 8 strings to match.
			switch (NameR[6]) {
			default: break;
			case 'd': // 4 strings to match.
			if (NameR[7] != '.')
			break;
			switch (NameR[8]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_sld_b; // "ips.sld.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_sld_d; // "ips.sld.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_sld_h; // "ips.sld.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_sld_w; // "ips.sld.w"
			}
			break;
			case 'l': // 4 strings to match.
			if (NameR[7] != '.')
			break;
			switch (NameR[8]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_sll_b; // "ips.sll.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_sll_d; // "ips.sll.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_sll_h; // "ips.sll.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_sll_w; // "ips.sll.w"
			}
			break;
			}
			break;
			case 'r': // 8 strings to match.
			switch (NameR[6]) {
			default: break;
			case 'a': // 4 strings to match.
			if (NameR[7] != '.')
			break;
			switch (NameR[8]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_sra_b; // "ips.sra.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_sra_d; // "ips.sra.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_sra_h; // "ips.sra.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_sra_w; // "ips.sra.w"
			}
			break;
			case 'l': // 4 strings to match.
			if (NameR[7] != '.')
			break;
			switch (NameR[8]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_srl_b; // "ips.srl.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_srl_d; // "ips.srl.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_srl_h; // "ips.srl.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_srl_w; // "ips.srl.w"
			}
			break;
			}
	break;		break;
	return Intrinsic::mips_shilo; // "ips.shilo"		}
			break;
	case 'w': // 1 string to match.		case 'w': // 1 string to match.
	if (memcmp(NameR.data()+5, "rdsp", 4))		if (memcmp(NameR.data()+5, "rdsp", 4))
	break;		break;
	return Intrinsic::mips_wrdsp; // "ips.wrdsp"		return Intrinsic::mips_wrdsp; // "ips.wrdsp"
			case 'x': // 1 string to match.
			if (memcmp(NameR.data()+5, "or.v", 4))
			break;
			return Intrinsic::mips_xor_v; // "ips.xor.v"
	}		}
	break;		break;
	case 10: // 8 strings to match.		case 10: // 143 strings to match.
	if (memcmp(NameR.data()+0, "ips.", 4))		if (memcmp(NameR.data()+0, "ips.", 4))
	break;		break;
	switch (NameR[4]) {		switch (NameR[4]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'a': // 6 strings to match.
	if (memcmp(NameR.data()+5, "ppend", 5))		switch (NameR[5]) {
			default: break;
			case 'd': // 4 strings to match.
			if (memcmp(NameR.data()+6, "dv.", 3))
			break;
			switch (NameR[9]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_addv_b; // "ips.addv.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_addv_d; // "ips.addv.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_addv_h; // "ips.addv.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_addv_w; // "ips.addv.w"
			}
	break;		break;
	return Intrinsic::mips_append; // "ips.append"		case 'n': // 1 string to match.
	case 'b': // 2 strings to match.		if (memcmp(NameR.data()+6, "di.b", 4))
			break;
			return Intrinsic::mips_andi_b; // "ips.andi.b"
			case 'p': // 1 string to match.
			if (memcmp(NameR.data()+6, "pend", 4))
			break;
			return Intrinsic::mips_append; // "ips.append"
			}
			break;
			case 'b': // 17 strings to match.
	switch (NameR[5]) {		switch (NameR[5]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(NameR.data()+6, "lign", 4))		if (memcmp(NameR.data()+6, "lign", 4))
	break;		break;
	return Intrinsic::mips_balign; // "ips.balign"		return Intrinsic::mips_balign; // "ips.balign"
	case 'i': // 1 string to match.		case 'c': // 4 strings to match.
	if (memcmp(NameR.data()+6, "trev", 4))		if (memcmp(NameR.data()+6, "lr.", 3))
	break;		break;
	return Intrinsic::mips_bitrev; // "ips.bitrev"		switch (NameR[9]) {
	}		default: break;
	break;		case 'b': // 1 string to match.
	case 'e': // 2 strings to match.		return Intrinsic::mips_bclr_b; // "ips.bclr.b"
	if (memcmp(NameR.data()+5, "xt", 2))		case 'd': // 1 string to match.
			return Intrinsic::mips_bclr_d; // "ips.bclr.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_bclr_h; // "ips.bclr.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_bclr_w; // "ips.bclr.w"
			}
	break;		break;
	switch (NameR[7]) {		case 'i': // 1 string to match.
	default: break;		if (memcmp(NameR.data()+6, "trev", 4))
	case 'p': // 1 string to match.
	if (memcmp(NameR.data()+8, "dp", 2))
	break;
	return Intrinsic::mips_extpdp; // "ips.extpdp"
	case 'r': // 1 string to match.
	if (memcmp(NameR.data()+8, ".w", 2))
	break;
	return Intrinsic::mips_extr_w; // "ips.extr.w"
	}
	break;
	case 'm': // 3 strings to match.
	switch (NameR[5]) {
	default: break;
	case 'o': // 1 string to match.
	if (memcmp(NameR.data()+6, "dsub", 4))
	break;
	return Intrinsic::mips_modsub; // "ips.modsub"
	case 't': // 1 string to match.
	if (memcmp(NameR.data()+6, "hlip", 4))
	break;
	return Intrinsic::mips_mthlip; // "ips.mthlip"
	case 'u': // 1 string to match.
	if (memcmp(NameR.data()+6, "l.ph", 4))
	break;		break;
	return Intrinsic::mips_mul_ph; // "ips.mul.ph"		return Intrinsic::mips_bitrev; // "ips.bitrev"
	}		case 'm': // 2 strings to match.
	break;		switch (NameR[6]) {
	}
	break;
	case 11: // 19 strings to match.
	if (memcmp(NameR.data()+0, "ips.", 4))
	break;
	switch (NameR[4]) {
	default: break;
	case 'a': // 4 strings to match.
	if (memcmp(NameR.data()+5, "dd", 2))
	break;
	switch (NameR[7]) {
	default: break;
	case 'q': // 2 strings to match.
	switch (NameR[8]) {
	default: break;		default: break;
	case '.': // 1 string to match.		case 'n': // 1 string to match.
	if (memcmp(NameR.data()+9, "ph", 2))		if (memcmp(NameR.data()+7, "z.v", 3))
	break;		break;
	return Intrinsic::mips_addq_ph; // "ips.addq.ph"		return Intrinsic::mips_bmnz_v; // "ips.bmnz.v"
	case 'h': // 1 string to match.		case 'z': // 1 string to match.
	if (memcmp(NameR.data()+9, ".w", 2))		if (memcmp(NameR.data()+7, "i.b", 3))
	break;		break;
	return Intrinsic::mips_addqh_w; // "ips.addqh.w"		return Intrinsic::mips_bmzi_b; // "ips.bmzi.b"
	}		}
	break;		break;
	case 'u': // 2 strings to match.		case 'n': // 4 strings to match.
	if (NameR[8] != '.')		if (memcmp(NameR.data()+6, "eg.", 3))
	break;		break;
	switch (NameR[9]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'b': // 1 string to match.
	if (NameR[10] != 'h')		return Intrinsic::mips_bneg_b; // "ips.bneg.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_bneg_d; // "ips.bneg.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_bneg_h; // "ips.bneg.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_bneg_w; // "ips.bneg.w"
			}
			break;
			case 's': // 5 strings to match.
			if (NameR[6] != 'e')
			break;
			switch (NameR[7]) {
			default: break;
			case 'l': // 1 string to match.
			if (memcmp(NameR.data()+8, ".v", 2))
	break;		break;
	return Intrinsic::mips_addu_ph; // "ips.addu.ph"		return Intrinsic::mips_bsel_v; // "ips.bsel.v"
	case 'q': // 1 string to match.		case 't': // 4 strings to match.
	if (NameR[10] != 'b')		if (NameR[8] != '.')
	break;		break;
	return Intrinsic::mips_addu_qb; // "ips.addu.qb"		switch (NameR[9]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_bset_b; // "ips.bset.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_bset_d; // "ips.bset.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_bset_h; // "ips.bset.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_bset_w; // "ips.bset.w"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'p': // 3 strings to match.		case 'c': // 6 strings to match.
	switch (NameR[5]) {		switch (NameR[5]) {
	default: break;		default: break;
	case 'i': // 2 strings to match.		case 'e': // 4 strings to match.
	if (memcmp(NameR.data()+6, "ck.", 3))		if (memcmp(NameR.data()+6, "qi.", 3))
	break;		break;
	switch (NameR[9]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'b': // 1 string to match.
	if (NameR[10] != 'h')		return Intrinsic::mips_ceqi_b; // "ips.ceqi.b"
	break;		case 'd': // 1 string to match.
	return Intrinsic::mips_pick_ph; // "ips.pick.ph"		return Intrinsic::mips_ceqi_d; // "ips.ceqi.d"
	case 'q': // 1 string to match.		case 'h': // 1 string to match.
	if (NameR[10] != 'b')		return Intrinsic::mips_ceqi_h; // "ips.ceqi.h"
	break;		case 'w': // 1 string to match.
	return Intrinsic::mips_pick_qb; // "ips.pick.qb"		return Intrinsic::mips_ceqi_w; // "ips.ceqi.w"
	}		}
	break;		break;
	case 'r': // 1 string to match.		case 'f': // 1 string to match.
	if (memcmp(NameR.data()+6, "epend", 5))		if (memcmp(NameR.data()+6, "cmsa", 4))
	break;		break;
	return Intrinsic::mips_prepend; // "ips.prepend"		return Intrinsic::mips_cfcmsa; // "ips.cfcmsa"
			case 't': // 1 string to match.
			if (memcmp(NameR.data()+6, "cmsa", 4))
			break;
			return Intrinsic::mips_ctcmsa; // "ips.ctcmsa"
	}		}
	break;		break;
	case 'r': // 2 strings to match.		case 'e': // 2 strings to match.
	if (memcmp(NameR.data()+5, "epl.", 4))		if (memcmp(NameR.data()+5, "xt", 2))
	break;		break;
	switch (NameR[9]) {		switch (NameR[7]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'p': // 1 string to match.
	if (NameR[10] != 'h')		if (memcmp(NameR.data()+8, "dp", 2))
	break;		break;
	return Intrinsic::mips_repl_ph; // "ips.repl.ph"		return Intrinsic::mips_extpdp; // "ips.extpdp"
	case 'q': // 1 string to match.		case 'r': // 1 string to match.
	if (NameR[10] != 'b')		if (memcmp(NameR.data()+8, ".w", 2))
	break;		break;
	return Intrinsic::mips_repl_qb; // "ips.repl.qb"		return Intrinsic::mips_extr_w; // "ips.extr.w"
	}		}
	break;		break;
	case 's': // 10 strings to match.		case 'f': // 50 strings to match.
	switch (NameR[5]) {		switch (NameR[5]) {
	default: break;		default: break;
	case 'h': // 6 strings to match.		case 'a': // 2 strings to match.
			if (memcmp(NameR.data()+6, "dd.", 3))
			break;
			switch (NameR[9]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fadd_d; // "ips.fadd.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fadd_w; // "ips.fadd.w"
			}
			break;
			case 'c': // 14 strings to match.
	switch (NameR[6]) {		switch (NameR[6]) {
	default: break;		default: break;
	case 'l': // 2 strings to match.		case 'a': // 2 strings to match.
	if (memcmp(NameR.data()+7, "l.", 2))		if (memcmp(NameR.data()+7, "f.", 2))
	break;		break;
	switch (NameR[9]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'd': // 1 string to match.
	if (NameR[10] != 'h')		return Intrinsic::mips_fcaf_d; // "ips.fcaf.d"
	break;		case 'w': // 1 string to match.
	return Intrinsic::mips_shll_ph; // "ips.shll.ph"		return Intrinsic::mips_fcaf_w; // "ips.fcaf.w"
	case 'q': // 1 string to match.
	if (NameR[10] != 'b')
	break;
	return Intrinsic::mips_shll_qb; // "ips.shll.qb"
	}		}
	break;		break;
	case 'r': // 4 strings to match.		case 'e': // 2 strings to match.
			if (memcmp(NameR.data()+7, "q.", 2))
			break;
			switch (NameR[9]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fceq_d; // "ips.fceq.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fceq_w; // "ips.fceq.w"
			}
			break;
			case 'l': // 4 strings to match.
	switch (NameR[7]) {		switch (NameR[7]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'e': // 2 strings to match.
	if (NameR[8] != '.')		if (NameR[8] != '.')
	break;		break;
	switch (NameR[9]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'd': // 1 string to match.
	if (NameR[10] != 'h')		return Intrinsic::mips_fcle_d; // "ips.fcle.d"
	break;		case 'w': // 1 string to match.
	return Intrinsic::mips_shra_ph; // "ips.shra.ph"		return Intrinsic::mips_fcle_w; // "ips.fcle.w"
	case 'q': // 1 string to match.
	if (NameR[10] != 'b')
	break;
	return Intrinsic::mips_shra_qb; // "ips.shra.qb"
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 't': // 2 strings to match.
	if (NameR[8] != '.')		if (NameR[8] != '.')
	break;		break;
	switch (NameR[9]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'd': // 1 string to match.
	if (NameR[10] != 'h')		return Intrinsic::mips_fclt_d; // "ips.fclt.d"
	break;		case 'w': // 1 string to match.
	return Intrinsic::mips_shrl_ph; // "ips.shrl.ph"		return Intrinsic::mips_fclt_w; // "ips.fclt.w"
	case 'q': // 1 string to match.
	if (NameR[10] != 'b')
	break;
	return Intrinsic::mips_shrl_qb; // "ips.shrl.qb"
	}		}
	break;		break;
	}		}
	break;		break;
			case 'n': // 2 strings to match.
			if (memcmp(NameR.data()+7, "e.", 2))
			break;
			switch (NameR[9]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fcne_d; // "ips.fcne.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fcne_w; // "ips.fcne.w"
			}
			break;
			case 'o': // 2 strings to match.
			if (memcmp(NameR.data()+7, "r.", 2))
			break;
			switch (NameR[9]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fcor_d; // "ips.fcor.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fcor_w; // "ips.fcor.w"
			}
			break;
			case 'u': // 2 strings to match.
			if (memcmp(NameR.data()+7, "n.", 2))
			break;
			switch (NameR[9]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fcun_d; // "ips.fcun.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fcun_w; // "ips.fcun.w"
			}
			break;
	}		}
	break;		break;
	case 'u': // 4 strings to match.		case 'd': // 2 strings to match.
	if (NameR[6] != 'b')		if (memcmp(NameR.data()+6, "iv.", 3))
			break;
			switch (NameR[9]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fdiv_d; // "ips.fdiv.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fdiv_w; // "ips.fdiv.w"
			}
			break;
			case 'f': // 4 strings to match.
			if (NameR[6] != 'q')
	break;		break;
	switch (NameR[7]) {		switch (NameR[7]) {
	default: break;		default: break;
	case 'q': // 2 strings to match.		case 'l': // 2 strings to match.
	switch (NameR[8]) {		if (NameR[8] != '.')
			break;
			switch (NameR[9]) {
	default: break;		default: break;
	case '.': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+9, "ph", 2))		return Intrinsic::mips_ffql_d; // "ips.ffql.d"
	break;		case 'w': // 1 string to match.
	return Intrinsic::mips_subq_ph; // "ips.subq.ph"		return Intrinsic::mips_ffql_w; // "ips.ffql.w"
	case 'h': // 1 string to match.
	if (memcmp(NameR.data()+9, ".w", 2))
	break;
	return Intrinsic::mips_subqh_w; // "ips.subqh.w"
	}		}
	break;		break;
	case 'u': // 2 strings to match.		case 'r': // 2 strings to match.
	if (NameR[8] != '.')		if (NameR[8] != '.')
	break;		break;
	switch (NameR[9]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'd': // 1 string to match.
	if (NameR[10] != 'h')		return Intrinsic::mips_ffqr_d; // "ips.ffqr.d"
	break;		case 'w': // 1 string to match.
	return Intrinsic::mips_subu_ph; // "ips.subu.ph"		return Intrinsic::mips_ffqr_w; // "ips.ffqr.w"
	case 'q': // 1 string to match.
	if (NameR[10] != 'b')
	break;
	return Intrinsic::mips_subu_qb; // "ips.subu.qb"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'i': // 4 strings to match.
	break;		if (memcmp(NameR.data()+6, "ll.", 3))
	}
	break;
	case 12: // 16 strings to match.
	if (memcmp(NameR.data()+0, "ips.", 4))
	break;
	switch (NameR[4]) {
	default: break;
	case 'a': // 4 strings to match.
	switch (NameR[5]) {
	default: break;
	case 'b': // 1 string to match.
	if (memcmp(NameR.data()+6, "sq.s.w", 6))
	break;
	return Intrinsic::mips_absq_s_w; // "ips.absq.s.w"
	case 'd': // 3 strings to match.
	if (NameR[6] != 'd')
	break;		break;
	switch (NameR[7]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'q': // 2 strings to match.		case 'b': // 1 string to match.
	switch (NameR[8]) {		return Intrinsic::mips_fill_b; // "ips.fill.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_fill_d; // "ips.fill.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_fill_h; // "ips.fill.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fill_w; // "ips.fill.w"
			}
			break;
			case 'm': // 6 strings to match.
			switch (NameR[6]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(NameR.data()+7, "x.", 2))
			break;
			switch (NameR[9]) {
	default: break;		default: break;
	case '.': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+9, "s.w", 3))		return Intrinsic::mips_fmax_d; // "ips.fmax.d"
	break;		case 'w': // 1 string to match.
	return Intrinsic::mips_addq_s_w; // "ips.addq.s.w"		return Intrinsic::mips_fmax_w; // "ips.fmax.w"
	case 'h': // 1 string to match.
	if (memcmp(NameR.data()+9, ".ph", 3))
	break;
	return Intrinsic::mips_addqh_ph; // "ips.addqh.ph"
	}		}
	break;		break;
	case 'u': // 1 string to match.		case 'i': // 2 strings to match.
	if (memcmp(NameR.data()+8, "h.qb", 4))		if (memcmp(NameR.data()+7, "n.", 2))
	break;		break;
	return Intrinsic::mips_adduh_qb; // "ips.adduh.qb"		switch (NameR[9]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fmin_d; // "ips.fmin.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fmin_w; // "ips.fmin.w"
			}
			break;
			case 'u': // 2 strings to match.
			if (memcmp(NameR.data()+7, "l.", 2))
			break;
			switch (NameR[9]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fmul_d; // "ips.fmul.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fmul_w; // "ips.fmul.w"
			}
			break;
	}		}
	break;		break;
	}		case 'r': // 2 strings to match.
	break;		if (memcmp(NameR.data()+6, "cp.", 3))
	case 'b': // 1 string to match.		break;
	if (memcmp(NameR.data()+5, "posge32", 7))		switch (NameR[9]) {
	break;		default: break;
	return Intrinsic::mips_bposge32; // "ips.bposge32"		case 'd': // 1 string to match.
	case 'd': // 2 strings to match.		return Intrinsic::mips_frcp_d; // "ips.frcp.d"
	if (NameR[5] != 'p')		case 'w': // 1 string to match.
			return Intrinsic::mips_frcp_w; // "ips.frcp.w"
			}
	break;		break;
	switch (NameR[6]) {		case 's': // 16 strings to match.
	default: break;		switch (NameR[6]) {
	case 'a': // 1 string to match.		default: break;
	if (memcmp(NameR.data()+7, ".w.ph", 5))		case 'a': // 2 strings to match.
			if (memcmp(NameR.data()+7, "f.", 2))
			break;
			switch (NameR[9]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fsaf_d; // "ips.fsaf.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fsaf_w; // "ips.fsaf.w"
			}
	break;		break;
	return Intrinsic::mips_dpa_w_ph; // "ips.dpa.w.ph"		case 'e': // 2 strings to match.
	case 's': // 1 string to match.		if (memcmp(NameR.data()+7, "q.", 2))
	if (memcmp(NameR.data()+7, ".w.ph", 5))		break;
			switch (NameR[9]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fseq_d; // "ips.fseq.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fseq_w; // "ips.fseq.w"
			}
	break;		break;
	return Intrinsic::mips_dps_w_ph; // "ips.dps.w.ph"		case 'l': // 4 strings to match.
	}		switch (NameR[7]) {
	break;		default: break;
	case 'e': // 2 strings to match.		case 'e': // 2 strings to match.
	if (memcmp(NameR.data()+5, "xtr.", 4))		if (NameR[8] != '.')
	break;		break;
	switch (NameR[9]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'r': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+10, ".w", 2))		return Intrinsic::mips_fsle_d; // "ips.fsle.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fsle_w; // "ips.fsle.w"
			}
			break;
			case 't': // 2 strings to match.
			if (NameR[8] != '.')
			break;
			switch (NameR[9]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fslt_d; // "ips.fslt.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fslt_w; // "ips.fslt.w"
			}
			break;
			}
	break;		break;
	return Intrinsic::mips_extr_r_w; // "ips.extr.r.w"		case 'n': // 2 strings to match.
	case 's': // 1 string to match.		if (memcmp(NameR.data()+7, "e.", 2))
	if (memcmp(NameR.data()+10, ".h", 2))		break;
			switch (NameR[9]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fsne_d; // "ips.fsne.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fsne_w; // "ips.fsne.w"
			}
	break;		break;
	return Intrinsic::mips_extr_s_h; // "ips.extr.s.h"		case 'o': // 2 strings to match.
			if (memcmp(NameR.data()+7, "r.", 2))
			break;
			switch (NameR[9]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fsor_d; // "ips.fsor.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fsor_w; // "ips.fsor.w"
			}
			break;
			case 'u': // 4 strings to match.
			switch (NameR[7]) {
			default: break;
			case 'b': // 2 strings to match.
			if (NameR[8] != '.')
			break;
			switch (NameR[9]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fsub_d; // "ips.fsub.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fsub_w; // "ips.fsub.w"
			}
			break;
			case 'n': // 2 strings to match.
			if (NameR[8] != '.')
			break;
			switch (NameR[9]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fsun_d; // "ips.fsun.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fsun_w; // "ips.fsun.w"
			}
			break;
			}
			break;
			}
			break;
	}		}
	break;		break;
	case 'm': // 2 strings to match.		case 'i': // 8 strings to match.
	if (memcmp(NameR.data()+5, "ul", 2))		if (memcmp(NameR.data()+5, "lv", 2))
	break;		break;
	switch (NameR[7]) {		switch (NameR[7]) {
	default: break;		default: break;
	case '.': // 1 string to match.		case 'l': // 4 strings to match.
	if (memcmp(NameR.data()+8, "s.ph", 4))		if (NameR[8] != '.')
	break;		break;
	return Intrinsic::mips_mul_s_ph; // "ips.mul.s.ph"		switch (NameR[9]) {
	case 'q': // 1 string to match.		default: break;
	if (memcmp(NameR.data()+8, ".s.w", 4))		case 'b': // 1 string to match.
			return Intrinsic::mips_ilvl_b; // "ips.ilvl.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_ilvl_d; // "ips.ilvl.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_ilvl_h; // "ips.ilvl.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ilvl_w; // "ips.ilvl.w"
			}
			break;
			case 'r': // 4 strings to match.
			if (NameR[8] != '.')
	break;		break;
	return Intrinsic::mips_mulq_s_w; // "ips.mulq.s.w"		switch (NameR[9]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_ilvr_b; // "ips.ilvr.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_ilvr_d; // "ips.ilvr.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_ilvr_h; // "ips.ilvr.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ilvr_w; // "ips.ilvr.w"
			}
			break;
	}		}
	break;		break;
	case 's': // 5 strings to match.		case 'm': // 8 strings to match.
	switch (NameR[5]) {		switch (NameR[5]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'o': // 2 strings to match.
	switch (NameR[6]) {		switch (NameR[6]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+7, "l.s.w", 5))		if (memcmp(NameR.data()+7, "sub", 3))
	break;		break;
	return Intrinsic::mips_shll_s_w; // "ips.shll.s.w"		return Intrinsic::mips_modsub; // "ips.modsub"
	case 'r': // 1 string to match.		case 'v': // 1 string to match.
	if (memcmp(NameR.data()+7, "a.r.w", 5))		if (memcmp(NameR.data()+7, "e.v", 3))
	break;		break;
	return Intrinsic::mips_shra_r_w; // "ips.shra.r.w"		return Intrinsic::mips_move_v; // "ips.move.v"
	}		}
	break;		break;
	case 'u': // 3 strings to match.		case 't': // 1 string to match.
	if (NameR[6] != 'b')		if (memcmp(NameR.data()+6, "hlip", 4))
			break;
			return Intrinsic::mips_mthlip; // "ips.mthlip"
			case 'u': // 5 strings to match.
			if (NameR[6] != 'l')
	break;		break;
	switch (NameR[7]) {		switch (NameR[7]) {
	default: break;		default: break;
	case 'q': // 2 strings to match.		case '.': // 1 string to match.
	switch (NameR[8]) {		if (memcmp(NameR.data()+8, "ph", 2))
			break;
			return Intrinsic::mips_mul_ph; // "ips.mul.ph"
			case 'v': // 4 strings to match.
			if (NameR[8] != '.')
			break;
			switch (NameR[9]) {
	default: break;		default: break;
	case '.': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(NameR.data()+9, "s.w", 3))		return Intrinsic::mips_mulv_b; // "ips.mulv.b"
	break;		case 'd': // 1 string to match.
	return Intrinsic::mips_subq_s_w; // "ips.subq.s.w"		return Intrinsic::mips_mulv_d; // "ips.mulv.d"
	case 'h': // 1 string to match.		case 'h': // 1 string to match.
	if (memcmp(NameR.data()+9, ".ph", 3))		return Intrinsic::mips_mulv_h; // "ips.mulv.h"
	break;		case 'w': // 1 string to match.
	return Intrinsic::mips_subqh_ph; // "ips.subqh.ph"		return Intrinsic::mips_mulv_w; // "ips.mulv.w"
	}		}
	break;		break;
	case 'u': // 1 string to match.
	if (memcmp(NameR.data()+8, "h.qb", 4))
	break;
	return Intrinsic::mips_subuh_qb; // "ips.subuh.qb"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'n': // 9 strings to match.
	break;
	case 13: // 22 strings to match.
	if (memcmp(NameR.data()+0, "ips.", 4))
	break;
	switch (NameR[4]) {
	default: break;
	case 'a': // 6 strings to match.
	switch (NameR[5]) {		switch (NameR[5]) {
	default: break;		default: break;
	case 'b': // 2 strings to match.		case 'l': // 8 strings to match.
	if (memcmp(NameR.data()+6, "sq.s.", 5))		switch (NameR[6]) {
	break;
	switch (NameR[11]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'o': // 4 strings to match.
	if (NameR[12] != 'h')		if (memcmp(NameR.data()+7, "c.", 2))
	break;		break;
	return Intrinsic::mips_absq_s_ph; // "ips.absq.s.ph"		switch (NameR[9]) {
	case 'q': // 1 string to match.		default: break;
	if (NameR[12] != 'b')		case 'b': // 1 string to match.
			return Intrinsic::mips_nloc_b; // "ips.nloc.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_nloc_d; // "ips.nloc.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_nloc_h; // "ips.nloc.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_nloc_w; // "ips.nloc.w"
			}
			break;
			case 'z': // 4 strings to match.
			if (memcmp(NameR.data()+7, "c.", 2))
	break;		break;
	return Intrinsic::mips_absq_s_qb; // "ips.absq.s.qb"		switch (NameR[9]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_nlzc_b; // "ips.nlzc.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_nlzc_d; // "ips.nlzc.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_nlzc_h; // "ips.nlzc.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_nlzc_w; // "ips.nlzc.w"
			}
			break;
	}		}
	break;		break;
	case 'd': // 4 strings to match.		case 'o': // 1 string to match.
	if (NameR[6] != 'd')		if (memcmp(NameR.data()+6, "ri.b", 4))
	break;		break;
	switch (NameR[7]) {		return Intrinsic::mips_nori_b; // "ips.nori.b"
			}
			break;
			case 'p': // 4 strings to match.
			if (memcmp(NameR.data()+5, "cnt.", 4))
			break;
			switch (NameR[9]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_pcnt_b; // "ips.pcnt.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_pcnt_d; // "ips.pcnt.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_pcnt_h; // "ips.pcnt.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_pcnt_w; // "ips.pcnt.w"
			}
			break;
			case 's': // 28 strings to match.
			switch (NameR[5]) {
			default: break;
			case 'l': // 8 strings to match.
			switch (NameR[6]) {
	default: break;		default: break;
	case 'q': // 2 strings to match.		case 'd': // 4 strings to match.
	switch (NameR[8]) {		if (memcmp(NameR.data()+7, "i.", 2))
			break;
			switch (NameR[9]) {
	default: break;		default: break;
	case '.': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(NameR.data()+9, "s.ph", 4))		return Intrinsic::mips_sldi_b; // "ips.sldi.b"
	break;		case 'd': // 1 string to match.
	return Intrinsic::mips_addq_s_ph; // "ips.addq.s.ph"		return Intrinsic::mips_sldi_d; // "ips.sldi.d"
	case 'h': // 1 string to match.		case 'h': // 1 string to match.
	if (memcmp(NameR.data()+9, ".r.w", 4))		return Intrinsic::mips_sldi_h; // "ips.sldi.h"
	break;		case 'w': // 1 string to match.
	return Intrinsic::mips_addqh_r_w; // "ips.addqh.r.w"		return Intrinsic::mips_sldi_w; // "ips.sldi.w"
	}		}
	break;		break;
	case 'u': // 2 strings to match.		case 'l': // 4 strings to match.
	if (memcmp(NameR.data()+8, ".s.", 3))		if (memcmp(NameR.data()+7, "i.", 2))
	break;		break;
	switch (NameR[11]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'b': // 1 string to match.
	if (NameR[12] != 'h')		return Intrinsic::mips_slli_b; // "ips.slli.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_slli_d; // "ips.slli.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_slli_h; // "ips.slli.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_slli_w; // "ips.slli.w"
			}
			break;
			}
			break;
			case 'r': // 16 strings to match.
			switch (NameR[6]) {
			default: break;
			case 'a': // 8 strings to match.
			switch (NameR[7]) {
			default: break;
			case 'i': // 4 strings to match.
			if (NameR[8] != '.')
	break;		break;
	return Intrinsic::mips_addu_s_ph; // "ips.addu.s.ph"		switch (NameR[9]) {
	case 'q': // 1 string to match.		default: break;
	if (NameR[12] != 'b')		case 'b': // 1 string to match.
			return Intrinsic::mips_srai_b; // "ips.srai.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_srai_d; // "ips.srai.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_srai_h; // "ips.srai.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_srai_w; // "ips.srai.w"
			}
			break;
			case 'r': // 4 strings to match.
			if (NameR[8] != '.')
	break;		break;
	return Intrinsic::mips_addu_s_qb; // "ips.addu.s.qb"		switch (NameR[9]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_srar_b; // "ips.srar.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_srar_d; // "ips.srar.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_srar_h; // "ips.srar.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_srar_w; // "ips.srar.w"
			}
			break;
			}
			break;
			case 'l': // 8 strings to match.
			switch (NameR[7]) {
			default: break;
			case 'i': // 4 strings to match.
			if (NameR[8] != '.')
			break;
			switch (NameR[9]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_srli_b; // "ips.srli.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_srli_d; // "ips.srli.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_srli_h; // "ips.srli.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_srli_w; // "ips.srli.w"
			}
			break;
			case 'r': // 4 strings to match.
			if (NameR[8] != '.')
			break;
			switch (NameR[9]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_srlr_b; // "ips.srlr.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_srlr_d; // "ips.srlr.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_srlr_h; // "ips.srlr.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_srlr_w; // "ips.srlr.w"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'u': // 4 strings to match.
	break;		if (memcmp(NameR.data()+6, "bv.", 3))
	case 'c': // 3 strings to match.
	if (memcmp(NameR.data()+5, "mp.", 3))
	break;
	switch (NameR[8]) {
	default: break;
	case 'e': // 1 string to match.
	if (memcmp(NameR.data()+9, "q.ph", 4))
	break;		break;
	return Intrinsic::mips_cmp_eq_ph; // "ips.cmp.eq.ph"
	case 'l': // 2 strings to match.
	switch (NameR[9]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ph", 3))		return Intrinsic::mips_subv_b; // "ips.subv.b"
	break;		case 'd': // 1 string to match.
	return Intrinsic::mips_cmp_le_ph; // "ips.cmp.le.ph"		return Intrinsic::mips_subv_d; // "ips.subv.d"
	case 't': // 1 string to match.		case 'h': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ph", 3))		return Intrinsic::mips_subv_h; // "ips.subv.h"
	break;		case 'w': // 1 string to match.
	return Intrinsic::mips_cmp_lt_ph; // "ips.cmp.lt.ph"		return Intrinsic::mips_subv_w; // "ips.subv.w"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'd': // 2 strings to match.		case 'v': // 4 strings to match.
	if (NameR[5] != 'p')		if (memcmp(NameR.data()+5, "shf.", 4))
	break;
	switch (NameR[6]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(NameR.data()+7, "x.w.ph", 6))
	break;
	return Intrinsic::mips_dpax_w_ph; // "ips.dpax.w.ph"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+7, "x.w.ph", 6))
	break;
	return Intrinsic::mips_dpsx_w_ph; // "ips.dpsx.w.ph"
	}
	break;
	case 'e': // 1 string to match.
	if (memcmp(NameR.data()+5, "xtr.rs.w", 8))
	break;
	return Intrinsic::mips_extr_rs_w; // "ips.extr.rs.w"
	case 'm': // 2 strings to match.
	if (memcmp(NameR.data()+5, "ulq.", 4))
	break;		break;
	switch (NameR[9]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'r': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(NameR.data()+10, "s.w", 3))		return Intrinsic::mips_vshf_b; // "ips.vshf.b"
	break;		case 'd': // 1 string to match.
	return Intrinsic::mips_mulq_rs_w; // "ips.mulq.rs.w"		return Intrinsic::mips_vshf_d; // "ips.vshf.d"
	case 's': // 1 string to match.		case 'h': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ph", 3))		return Intrinsic::mips_vshf_h; // "ips.vshf.h"
	break;		case 'w': // 1 string to match.
	return Intrinsic::mips_mulq_s_ph; // "ips.mulq.s.ph"		return Intrinsic::mips_vshf_w; // "ips.vshf.w"
	}		}
	break;		break;
	case 'p': // 1 string to match.		case 'x': // 1 string to match.
	if (memcmp(NameR.data()+5, "ackrl.ph", 8))		if (memcmp(NameR.data()+5, "ori.b", 5))
	break;		break;
	return Intrinsic::mips_packrl_ph; // "ips.packrl.ph"		return Intrinsic::mips_xori_b; // "ips.xori.b"
	case 's': // 7 strings to match.		}
			break;
			case 11: // 197 strings to match.
			if (memcmp(NameR.data()+0, "ips.", 4))
			break;
			switch (NameR[4]) {
			default: break;
			case 'a': // 20 strings to match.
	switch (NameR[5]) {		switch (NameR[5]) {
	default: break;		default: break;
	case 'h': // 3 strings to match.		case 'd': // 12 strings to match.
	switch (NameR[6]) {		if (NameR[6] != 'd')
			break;
			switch (NameR[7]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case '.': // 4 strings to match.
	if (memcmp(NameR.data()+7, "l.s.ph", 6))		if (memcmp(NameR.data()+8, "a.", 2))
	break;
	return Intrinsic::mips_shll_s_ph; // "ips.shll.s.ph"
	case 'r': // 2 strings to match.
	if (memcmp(NameR.data()+7, "a.r.", 4))
	break;		break;
	switch (NameR[11]) {		switch (NameR[10]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'b': // 1 string to match.
	if (NameR[12] != 'h')		return Intrinsic::mips_add_a_b; // "ips.add.a.b"
	break;		case 'd': // 1 string to match.
	return Intrinsic::mips_shra_r_ph; // "ips.shra.r.ph"		return Intrinsic::mips_add_a_d; // "ips.add.a.d"
	case 'q': // 1 string to match.		case 'h': // 1 string to match.
	if (NameR[12] != 'b')		return Intrinsic::mips_add_a_h; // "ips.add.a.h"
	break;		case 'w': // 1 string to match.
	return Intrinsic::mips_shra_r_qb; // "ips.shra.r.qb"		return Intrinsic::mips_add_a_w; // "ips.add.a.w"
	}		}
	break;		break;
	}
	break;
	case 'u': // 4 strings to match.
	if (NameR[6] != 'b')
	break;
	switch (NameR[7]) {
	default: break;
	case 'q': // 2 strings to match.		case 'q': // 2 strings to match.
	switch (NameR[8]) {		switch (NameR[8]) {
	default: break;		default: break;
	case '.': // 1 string to match.		case '.': // 1 string to match.
	if (memcmp(NameR.data()+9, "s.ph", 4))		if (memcmp(NameR.data()+9, "ph", 2))
	break;		break;
	return Intrinsic::mips_subq_s_ph; // "ips.subq.s.ph"		return Intrinsic::mips_addq_ph; // "ips.addq.ph"
	case 'h': // 1 string to match.		case 'h': // 1 string to match.
	if (memcmp(NameR.data()+9, ".r.w", 4))		if (memcmp(NameR.data()+9, ".w", 2))
	break;		break;
	return Intrinsic::mips_subqh_r_w; // "ips.subqh.r.w"		return Intrinsic::mips_addqh_w; // "ips.addqh.w"
	}		}
	break;		break;
	case 'u': // 2 strings to match.		case 'u': // 2 strings to match.
	if (memcmp(NameR.data()+8, ".s.", 3))		if (NameR[8] != '.')
	break;		break;
	switch (NameR[11]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'p': // 1 string to match.
	if (NameR[12] != 'h')		if (NameR[10] != 'h')
	break;		break;
	return Intrinsic::mips_subu_s_ph; // "ips.subu.s.ph"		return Intrinsic::mips_addu_ph; // "ips.addu.ph"
	case 'q': // 1 string to match.		case 'q': // 1 string to match.
	if (NameR[12] != 'b')		if (NameR[10] != 'b')
	break;		break;
	return Intrinsic::mips_subu_s_qb; // "ips.subu.s.qb"		return Intrinsic::mips_addu_qb; // "ips.addu.qb"
			}
			break;
			case 'v': // 4 strings to match.
			if (memcmp(NameR.data()+8, "i.", 2))
			break;
			switch (NameR[10]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_addvi_b; // "ips.addvi.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_addvi_d; // "ips.addvi.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_addvi_h; // "ips.addvi.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_addvi_w; // "ips.addvi.w"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'v': // 8 strings to match.
	break;		if (memcmp(NameR.data()+6, "e.", 2))
	}
	break;
	case 14: // 14 strings to match.
	if (memcmp(NameR.data()+0, "ips.", 4))
	break;
	switch (NameR[4]) {
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(NameR.data()+5, "dd", 2))
	break;
	switch (NameR[7]) {
	default: break;
	case 'q': // 1 string to match.
	if (memcmp(NameR.data()+8, "h.r.ph", 6))
	break;		break;
	return Intrinsic::mips_addqh_r_ph; // "ips.addqh.r.ph"		switch (NameR[8]) {
	case 'u': // 1 string to match.		default: break;
	if (memcmp(NameR.data()+8, "h.r.qb", 6))		case 's': // 4 strings to match.
			if (NameR[9] != '.')
			break;
			switch (NameR[10]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_ave_s_b; // "ips.ave.s.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_ave_s_d; // "ips.ave.s.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_ave_s_h; // "ips.ave.s.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ave_s_w; // "ips.ave.s.w"
			}
	break;		break;
	return Intrinsic::mips_adduh_r_qb; // "ips.adduh.r.qb"		case 'u': // 4 strings to match.
			if (NameR[9] != '.')
			break;
			switch (NameR[10]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_ave_u_b; // "ips.ave.u.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_ave_u_d; // "ips.ave.u.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_ave_u_h; // "ips.ave.u.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ave_u_w; // "ips.ave.u.w"
			}
			break;
			}
			break;
	}		}
	break;		break;
	case 'c': // 3 strings to match.		case 'b': // 22 strings to match.
	if (memcmp(NameR.data()+5, "mpu.", 4))		switch (NameR[5]) {
	break;
	switch (NameR[9]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'c': // 4 strings to match.
	if (memcmp(NameR.data()+10, "q.qb", 4))		if (memcmp(NameR.data()+6, "lri.", 4))
	break;		break;
	return Intrinsic::mips_cmpu_eq_qb; // "ips.cmpu.eq.qb"
	case 'l': // 2 strings to match.
	switch (NameR[10]) {		switch (NameR[10]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(NameR.data()+11, ".qb", 3))		return Intrinsic::mips_bclri_b; // "ips.bclri.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_bclri_d; // "ips.bclri.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_bclri_h; // "ips.bclri.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_bclri_w; // "ips.bclri.w"
			}
			break;
			case 'i': // 8 strings to match.
			if (memcmp(NameR.data()+6, "ns", 2))
			break;
			switch (NameR[8]) {
			default: break;
			case 'l': // 4 strings to match.
			if (NameR[9] != '.')
	break;		break;
	return Intrinsic::mips_cmpu_le_qb; // "ips.cmpu.le.qb"		switch (NameR[10]) {
	case 't': // 1 string to match.		default: break;
	if (memcmp(NameR.data()+11, ".qb", 3))		case 'b': // 1 string to match.
			return Intrinsic::mips_binsl_b; // "ips.binsl.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_binsl_d; // "ips.binsl.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_binsl_h; // "ips.binsl.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_binsl_w; // "ips.binsl.w"
			}
			break;
			case 'r': // 4 strings to match.
			if (NameR[9] != '.')
	break;		break;
	return Intrinsic::mips_cmpu_lt_qb; // "ips.cmpu.lt.qb"		switch (NameR[10]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_binsr_b; // "ips.binsr.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_binsr_d; // "ips.binsr.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_binsr_h; // "ips.binsr.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_binsr_w; // "ips.binsr.w"
			}
			break;
	}		}
	break;		break;
	}		case 'm': // 1 string to match.
	break;		if (memcmp(NameR.data()+6, "nzi.b", 5))
	case 'd': // 4 strings to match.
	if (NameR[5] != 'p')
	break;
	switch (NameR[6]) {
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(NameR.data()+7, "u.h.qb", 6))
	break;		break;
	switch (NameR[13]) {		return Intrinsic::mips_bmnzi_b; // "ips.bmnzi.b"
			case 'n': // 4 strings to match.
			if (memcmp(NameR.data()+6, "egi.", 4))
			break;
			switch (NameR[10]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::mips_dpau_h_qbl; // "ips.dpau.h.qbl"		return Intrinsic::mips_bnegi_b; // "ips.bnegi.b"
	case 'r': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::mips_dpau_h_qbr; // "ips.dpau.h.qbr"		return Intrinsic::mips_bnegi_d; // "ips.bnegi.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_bnegi_h; // "ips.bnegi.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_bnegi_w; // "ips.bnegi.w"
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 's': // 5 strings to match.
	if (memcmp(NameR.data()+7, "u.h.qb", 6))		if (NameR[6] != 'e')
	break;		break;
	switch (NameR[13]) {		switch (NameR[7]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'l': // 1 string to match.
	return Intrinsic::mips_dpsu_h_qbl; // "ips.dpsu.h.qbl"		if (memcmp(NameR.data()+8, "i.b", 3))
	case 'r': // 1 string to match.		break;
	return Intrinsic::mips_dpsu_h_qbr; // "ips.dpsu.h.qbr"		return Intrinsic::mips_bseli_b; // "ips.bseli.b"
			case 't': // 4 strings to match.
			if (memcmp(NameR.data()+8, "i.", 2))
			break;
			switch (NameR[10]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_bseti_b; // "ips.bseti.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_bseti_d; // "ips.bseti.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_bseti_h; // "ips.bseti.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_bseti_w; // "ips.bseti.w"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'm': // 2 strings to match.		case 'c': // 16 strings to match.
	if (memcmp(NameR.data()+5, "ul", 2))		if (NameR[5] != 'l')
	break;		break;
	switch (NameR[7]) {		switch (NameR[6]) {
	default: break;		default: break;
	case 'q': // 1 string to match.		case 'e': // 8 strings to match.
	if (memcmp(NameR.data()+8, ".rs.ph", 6))		if (NameR[7] != '.')
	break;
	return Intrinsic::mips_mulq_rs_ph; // "ips.mulq.rs.ph"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+8, "a.w.ph", 6))
	break;		break;
	return Intrinsic::mips_mulsa_w_ph; // "ips.mulsa.w.ph"		switch (NameR[8]) {
	}		default: break;
	break;		case 's': // 4 strings to match.
	case 'r': // 1 string to match.		if (NameR[9] != '.')
	if (memcmp(NameR.data()+5, "addu.w.qb", 9))		break;
	break;		switch (NameR[10]) {
	return Intrinsic::mips_raddu_w_qb; // "ips.raddu.w.qb"		default: break;
	case 's': // 2 strings to match.		case 'b': // 1 string to match.
	if (memcmp(NameR.data()+5, "ub", 2))		return Intrinsic::mips_cle_s_b; // "ips.cle.s.b"
	break;		case 'd': // 1 string to match.
	switch (NameR[7]) {		return Intrinsic::mips_cle_s_d; // "ips.cle.s.d"
	default: break;		case 'h': // 1 string to match.
	case 'q': // 1 string to match.		return Intrinsic::mips_cle_s_h; // "ips.cle.s.h"
	if (memcmp(NameR.data()+8, "h.r.ph", 6))		case 'w': // 1 string to match.
			return Intrinsic::mips_cle_s_w; // "ips.cle.s.w"
			}
	break;		break;
	return Intrinsic::mips_subqh_r_ph; // "ips.subqh.r.ph"		case 'u': // 4 strings to match.
	case 'u': // 1 string to match.		if (NameR[9] != '.')
	if (memcmp(NameR.data()+8, "h.r.qb", 6))		break;
			switch (NameR[10]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_cle_u_b; // "ips.cle.u.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_cle_u_d; // "ips.cle.u.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_cle_u_h; // "ips.cle.u.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_cle_u_w; // "ips.cle.u.w"
			}
	break;		break;
	return Intrinsic::mips_subuh_r_qb; // "ips.subuh.r.qb"		}
	}
	break;
	}
	break;
	case 15: // 11 strings to match.
	if (memcmp(NameR.data()+0, "ips.", 4))
	break;
	switch (NameR[4]) {
	default: break;
	case 'c': // 3 strings to match.
	if (memcmp(NameR.data()+5, "mpgu.", 5))
	break;		break;
	switch (NameR[10]) {		case 't': // 8 strings to match.
	default: break;		if (NameR[7] != '.')
	case 'e': // 1 string to match.
	if (memcmp(NameR.data()+11, "q.qb", 4))
	break;		break;
	return Intrinsic::mips_cmpgu_eq_qb; // "ips.cmpgu.eq.qb"		switch (NameR[8]) {
	case 'l': // 2 strings to match.
	switch (NameR[11]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 's': // 4 strings to match.
	if (memcmp(NameR.data()+12, ".qb", 3))		if (NameR[9] != '.')
	break;		break;
	return Intrinsic::mips_cmpgu_le_qb; // "ips.cmpgu.le.qb		switch (NameR[10]) {
	"		default: break;
	case 't': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(NameR.data()+12, ".qb", 3))		return Intrinsic::mips_clt_s_b; // "ips.clt.s.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_clt_s_d; // "ips.clt.s.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_clt_s_h; // "ips.clt.s.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_clt_s_w; // "ips.clt.s.w"
			}
			break;
			case 'u': // 4 strings to match.
			if (NameR[9] != '.')
	break;		break;
	return Intrinsic::mips_cmpgu_lt_qb; // "ips.cmpgu.lt.qb		switch (NameR[10]) {
	"		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_clt_u_b; // "ips.clt.u.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_clt_u_d; // "ips.clt.u.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_clt_u_h; // "ips.clt.u.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_clt_u_w; // "ips.clt.u.w"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'd': // 4 strings to match.		case 'd': // 8 strings to match.
	if (NameR[5] != 'p')		if (memcmp(NameR.data()+5, "iv.", 3))
	break;		break;
	switch (NameR[6]) {		switch (NameR[8]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 's': // 4 strings to match.
	if (memcmp(NameR.data()+7, "q.s", 3))		if (NameR[9] != '.')
	break;		break;
	switch (NameR[10]) {		switch (NameR[10]) {
	default: break;		default: break;
	case '.': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(NameR.data()+11, "w.ph", 4))		return Intrinsic::mips_div_s_b; // "ips.div.s.b"
	break;		case 'd': // 1 string to match.
	return Intrinsic::mips_dpaq_s_w_ph; // "ips.dpaq.s.w.ph		return Intrinsic::mips_div_s_d; // "ips.div.s.d"
	"		case 'h': // 1 string to match.
	case 'a': // 1 string to match.		return Intrinsic::mips_div_s_h; // "ips.div.s.h"
	if (memcmp(NameR.data()+11, ".l.w", 4))		case 'w': // 1 string to match.
	break;		return Intrinsic::mips_div_s_w; // "ips.div.s.w"
	return Intrinsic::mips_dpaq_sa_l_w; // "ips.dpaq.sa.l.w
	"
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 'u': // 4 strings to match.
	if (memcmp(NameR.data()+7, "q.s", 3))		if (NameR[9] != '.')
	break;		break;
	switch (NameR[10]) {		switch (NameR[10]) {
	default: break;		default: break;
	case '.': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(NameR.data()+11, "w.ph", 4))		return Intrinsic::mips_div_u_b; // "ips.div.u.b"
	break;		case 'd': // 1 string to match.
	return Intrinsic::mips_dpsq_s_w_ph; // "ips.dpsq.s.w.ph		return Intrinsic::mips_div_u_d; // "ips.div.u.d"
	"		case 'h': // 1 string to match.
	case 'a': // 1 string to match.		return Intrinsic::mips_div_u_h; // "ips.div.u.h"
	if (memcmp(NameR.data()+11, ".l.w", 4))		case 'w': // 1 string to match.
	break;		return Intrinsic::mips_div_u_w; // "ips.div.u.w"
	return Intrinsic::mips_dpsq_sa_l_w; // "ips.dpsq.sa.l.w
	"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'm': // 2 strings to match.		case 'f': // 30 strings to match.
	if (memcmp(NameR.data()+5, "aq.s.w.ph", 9))		switch (NameR[5]) {
	break;
	switch (NameR[14]) {
	default: break;
	case 'l': // 1 string to match.
	return Intrinsic::mips_maq_s_w_phl; // "ips.maq.s.w.phl"
	case 'r': // 1 string to match.
	return Intrinsic::mips_maq_s_w_phr; // "ips.maq.s.w.phr"
	}
	break;
	case 'p': // 2 strings to match.
	if (memcmp(NameR.data()+5, "recr", 4))
	break;
	switch (NameR[9]) {
	default: break;		default: break;
	case '.': // 1 string to match.		case 'c': // 8 strings to match.
	if (memcmp(NameR.data()+10, "qb.ph", 5))		if (NameR[6] != 'u')
	break;		break;
	return Intrinsic::mips_precr_qb_ph; // "ips.precr.qb.ph"		switch (NameR[7]) {
	case 'q': // 1 string to match.		default: break;
	if (memcmp(NameR.data()+10, ".ph.w", 5))		case 'e': // 2 strings to match.
			if (memcmp(NameR.data()+8, "q.", 2))
			break;
			switch (NameR[10]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fcueq_d; // "ips.fcueq.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fcueq_w; // "ips.fcueq.w"
			}
	break;		break;
	return Intrinsic::mips_precrq_ph_w; // "ips.precrq.ph.w"		case 'l': // 4 strings to match.
	}		switch (NameR[8]) {
	break;		default: break;
	}		case 'e': // 2 strings to match.
	break;		if (NameR[9] != '.')
	case 16: // 10 strings to match.		break;
	if (memcmp(NameR.data()+0, "ips.", 4))		switch (NameR[10]) {
	break;		default: break;
	switch (NameR[4]) {		case 'd': // 1 string to match.
	default: break;		return Intrinsic::mips_fcule_d; // "ips.fcule.d"
	case 'c': // 3 strings to match.		case 'w': // 1 string to match.
	if (memcmp(NameR.data()+5, "mpgdu.", 6))		return Intrinsic::mips_fcule_w; // "ips.fcule.w"
			}
			break;
			case 't': // 2 strings to match.
			if (NameR[9] != '.')
			break;
			switch (NameR[10]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fcult_d; // "ips.fcult.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fcult_w; // "ips.fcult.w"
			}
			break;
			}
			break;
			case 'n': // 2 strings to match.
			if (memcmp(NameR.data()+8, "e.", 2))
			break;
			switch (NameR[10]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fcune_d; // "ips.fcune.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fcune_w; // "ips.fcune.w"
			}
			break;
			}
	break;		break;
	switch (NameR[11]) {		case 'e': // 4 strings to match.
	default: break;		if (NameR[6] != 'x')
	case 'e': // 1 string to match.
	if (memcmp(NameR.data()+12, "q.qb", 4))
	break;		break;
	return Intrinsic::mips_cmpgdu_eq_qb; // "ips.cmpgdu.eq.qb"		switch (NameR[7]) {
			default: break;
			case 'd': // 2 strings to match.
			if (memcmp(NameR.data()+8, "o.", 2))
			break;
			switch (NameR[10]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::mips_fexdo_h; // "ips.fexdo.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fexdo_w; // "ips.fexdo.w"
			}
			break;
			case 'p': // 2 strings to match.
			if (memcmp(NameR.data()+8, "2.", 2))
			break;
			switch (NameR[10]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fexp2_d; // "ips.fexp2.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fexp2_w; // "ips.fexp2.w"
			}
			break;
			}
			break;
	case 'l': // 2 strings to match.		case 'l': // 2 strings to match.
	switch (NameR[12]) {		if (memcmp(NameR.data()+6, "og2.", 4))
			break;
			switch (NameR[10]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+13, ".qb", 3))		return Intrinsic::mips_flog2_d; // "ips.flog2.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_flog2_w; // "ips.flog2.w"
			}
			break;
			case 'm': // 4 strings to match.
			switch (NameR[6]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(NameR.data()+7, "dd.", 3))
	break;		break;
	return Intrinsic::mips_cmpgdu_le_qb; // "ips.cmpgdu.le.q		switch (NameR[10]) {
	b"		default: break;
	case 't': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+13, ".qb", 3))		return Intrinsic::mips_fmadd_d; // "ips.fmadd.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fmadd_w; // "ips.fmadd.w"
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(NameR.data()+7, "ub.", 3))
	break;		break;
	return Intrinsic::mips_cmpgdu_lt_qb; // "ips.cmpgdu.lt.q		switch (NameR[10]) {
	b"		default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fmsub_d; // "ips.fmsub.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fmsub_w; // "ips.fmsub.w"
			}
			break;
	}		}
	break;		break;
	}		case 'r': // 2 strings to match.
	break;		if (memcmp(NameR.data()+6, "int.", 4))
	case 'd': // 2 strings to match.		break;
	if (NameR[5] != 'p')		switch (NameR[10]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_frint_d; // "ips.frint.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_frint_w; // "ips.frint.w"
			}
	break;		break;
	switch (NameR[6]) {		case 's': // 10 strings to match.
	default: break;		switch (NameR[6]) {
	case 'a': // 1 string to match.		default: break;
	if (memcmp(NameR.data()+7, "qx.s.w.ph", 9))		case 'q': // 2 strings to match.
			if (memcmp(NameR.data()+7, "rt.", 3))
			break;
			switch (NameR[10]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fsqrt_d; // "ips.fsqrt.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fsqrt_w; // "ips.fsqrt.w"
			}
	break;		break;
	return Intrinsic::mips_dpaqx_s_w_ph; // "ips.dpaqx.s.w.ph"		case 'u': // 8 strings to match.
	case 's': // 1 string to match.		switch (NameR[7]) {
	if (memcmp(NameR.data()+7, "qx.s.w.ph", 9))		default: break;
			case 'e': // 2 strings to match.
			if (memcmp(NameR.data()+8, "q.", 2))
			break;
			switch (NameR[10]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fsueq_d; // "ips.fsueq.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fsueq_w; // "ips.fsueq.w"
			}
			break;
			case 'l': // 4 strings to match.
			switch (NameR[8]) {
			default: break;
			case 'e': // 2 strings to match.
			if (NameR[9] != '.')
			break;
			switch (NameR[10]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fsule_d; // "ips.fsule.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fsule_w; // "ips.fsule.w"
			}
			break;
			case 't': // 2 strings to match.
			if (NameR[9] != '.')
			break;
			switch (NameR[10]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fsult_d; // "ips.fsult.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fsult_w; // "ips.fsult.w"
			}
			break;
			}
			break;
			case 'n': // 2 strings to match.
			if (memcmp(NameR.data()+8, "e.", 2))
			break;
			switch (NameR[10]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fsune_d; // "ips.fsune.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fsune_w; // "ips.fsune.w"
			}
			break;
			}
	break;		break;
	return Intrinsic::mips_dpsqx_s_w_ph; // "ips.dpsqx.s.w.ph"		}
	}
	break;
	case 'm': // 2 strings to match.
	if (memcmp(NameR.data()+5, "aq.sa.w.ph", 10))
	break;		break;
	switch (NameR[15]) {
	default: break;
	case 'l': // 1 string to match.
	return Intrinsic::mips_maq_sa_w_phl; // "ips.maq.sa.w.phl"
	case 'r': // 1 string to match.
	return Intrinsic::mips_maq_sa_w_phr; // "ips.maq.sa.w.phr"
	}		}
	break;		break;
	case 'p': // 3 strings to match.		case 'i': // 12 strings to match.
	if (memcmp(NameR.data()+5, "rec", 3))		switch (NameR[5]) {
	break;
	switch (NameR[8]) {
	default: break;		default: break;
	case 'e': // 2 strings to match.		case 'l': // 8 strings to match.
	if (memcmp(NameR.data()+9, "q.w.ph", 6))		if (NameR[6] != 'v')
	break;		break;
	switch (NameR[15]) {		switch (NameR[7]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'e': // 4 strings to match.
	return Intrinsic::mips_preceq_w_phl; // "ips.preceq.w.ph		if (memcmp(NameR.data()+8, "v.", 2))
	l"		break;
	case 'r': // 1 string to match.		switch (NameR[10]) {
	return Intrinsic::mips_preceq_w_phr; // "ips.preceq.w.ph		default: break;
	r"		case 'b': // 1 string to match.
			return Intrinsic::mips_ilvev_b; // "ips.ilvev.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_ilvev_d; // "ips.ilvev.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_ilvev_h; // "ips.ilvev.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ilvev_w; // "ips.ilvev.w"
			}
			break;
			case 'o': // 4 strings to match.
			if (memcmp(NameR.data()+8, "d.", 2))
			break;
			switch (NameR[10]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_ilvod_b; // "ips.ilvod.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_ilvod_d; // "ips.ilvod.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_ilvod_h; // "ips.ilvod.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ilvod_w; // "ips.ilvod.w"
			}
			break;
	}		}
	break;		break;
	case 'r': // 1 string to match.		case 'n': // 4 strings to match.
	if (memcmp(NameR.data()+9, "q.qb.ph", 7))		if (memcmp(NameR.data()+6, "sve.", 4))
	break;		break;
	return Intrinsic::mips_precrq_qb_ph; // "ips.precrq.qb.ph"		switch (NameR[10]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_insve_b; // "ips.insve.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_insve_d; // "ips.insve.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_insve_h; // "ips.insve.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_insve_w; // "ips.insve.w"
			}
			break;
	}		}
	break;		break;
	}		case 'm': // 42 strings to match.
	break;		switch (NameR[5]) {
	case 17: // 7 strings to match.
	if (memcmp(NameR.data()+0, "ips.", 4))
	break;
	switch (NameR[4]) {
	default: break;
	case 'd': // 2 strings to match.
	if (NameR[5] != 'p')
	break;
	switch (NameR[6]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'a': // 16 strings to match.
	if (memcmp(NameR.data()+7, "qx.sa.w.ph", 10))		switch (NameR[6]) {
			default: break;
			case 'd': // 4 strings to match.
			if (memcmp(NameR.data()+7, "dv.", 3))
			break;
			switch (NameR[10]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_maddv_b; // "ips.maddv.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_maddv_d; // "ips.maddv.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_maddv_h; // "ips.maddv.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_maddv_w; // "ips.maddv.w"
			}
	break;		break;
	return Intrinsic::mips_dpaqx_sa_w_ph; // "ips.dpaqx.sa.w.		case 'x': // 12 strings to match.
	ph"		if (NameR[7] != '.')
	case 's': // 1 string to match.		break;
	if (memcmp(NameR.data()+7, "qx.sa.w.ph", 10))		switch (NameR[8]) {
			default: break;
			case 'a': // 4 strings to match.
			if (NameR[9] != '.')
			break;
			switch (NameR[10]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_max_a_b; // "ips.max.a.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_max_a_d; // "ips.max.a.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_max_a_h; // "ips.max.a.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_max_a_w; // "ips.max.a.w"
			}
			break;
			case 's': // 4 strings to match.
			if (NameR[9] != '.')
			break;
			switch (NameR[10]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_max_s_b; // "ips.max.s.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_max_s_d; // "ips.max.s.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_max_s_h; // "ips.max.s.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_max_s_w; // "ips.max.s.w"
			}
			break;
			case 'u': // 4 strings to match.
			if (NameR[9] != '.')
			break;
			switch (NameR[10]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_max_u_b; // "ips.max.u.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_max_u_d; // "ips.max.u.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_max_u_h; // "ips.max.u.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_max_u_w; // "ips.max.u.w"
			}
			break;
			}
	break;		break;
	return Intrinsic::mips_dpsqx_sa_w_ph; // "ips.dpsqx.sa.w.		}
	ph"
	}
	break;
	case 'm': // 3 strings to match.
	if (memcmp(NameR.data()+5, "ul", 2))
	break;		break;
	switch (NameR[7]) {		case 'i': // 12 strings to match.
	default: break;		if (memcmp(NameR.data()+6, "n.", 2))
	case 'e': // 2 strings to match.
	if (memcmp(NameR.data()+8, "q.s.w.ph", 8))
	break;		break;
	switch (NameR[16]) {		switch (NameR[8]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'a': // 4 strings to match.
	return Intrinsic::mips_muleq_s_w_phl; // "ips.muleq.s.w.p		if (NameR[9] != '.')
	hl"		break;
	case 'r': // 1 string to match.		switch (NameR[10]) {
	return Intrinsic::mips_muleq_s_w_phr; // "ips.muleq.s.w.p		default: break;
	hr"		case 'b': // 1 string to match.
			return Intrinsic::mips_min_a_b; // "ips.min.a.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_min_a_d; // "ips.min.a.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_min_a_h; // "ips.min.a.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_min_a_w; // "ips.min.a.w"
			}
			break;
			case 's': // 4 strings to match.
			if (NameR[9] != '.')
			break;
			switch (NameR[10]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_min_s_b; // "ips.min.s.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_min_s_d; // "ips.min.s.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_min_s_h; // "ips.min.s.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_min_s_w; // "ips.min.s.w"
			}
			break;
			case 'u': // 4 strings to match.
			if (NameR[9] != '.')
			break;
			switch (NameR[10]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_min_u_b; // "ips.min.u.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_min_u_d; // "ips.min.u.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_min_u_h; // "ips.min.u.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_min_u_w; // "ips.min.u.w"
			}
			break;
	}		}
	break;		break;
	case 's': // 1 string to match.		case 'o': // 8 strings to match.
	if (memcmp(NameR.data()+8, "aq.s.w.ph", 9))		if (memcmp(NameR.data()+6, "d.", 2))
	break;		break;
	return Intrinsic::mips_mulsaq_s_w_ph; // "ips.mulsaq.s.w.		switch (NameR[8]) {
	ph"		default: break;
	}		case 's': // 4 strings to match.
	break;		if (NameR[9] != '.')
	case 'p': // 2 strings to match.		break;
	if (memcmp(NameR.data()+5, "receu.ph.qb", 11))		switch (NameR[10]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_mod_s_b; // "ips.mod.s.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_mod_s_d; // "ips.mod.s.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_mod_s_h; // "ips.mod.s.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_mod_s_w; // "ips.mod.s.w"
			}
			break;
			case 'u': // 4 strings to match.
			if (NameR[9] != '.')
			break;
			switch (NameR[10]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_mod_u_b; // "ips.mod.u.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_mod_u_d; // "ips.mod.u.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_mod_u_h; // "ips.mod.u.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_mod_u_w; // "ips.mod.u.w"
			}
			break;
			}
	break;		break;
	switch (NameR[16]) {		case 's': // 4 strings to match.
	default: break;		if (memcmp(NameR.data()+6, "ubv.", 4))
	case 'l': // 1 string to match.		break;
	return Intrinsic::mips_preceu_ph_qbl; // "ips.preceu.ph.q		switch (NameR[10]) {
	bl"		default: break;
	case 'r': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::mips_preceu_ph_qbr; // "ips.preceu.ph.q		return Intrinsic::mips_msubv_b; // "ips.msubv.b"
	br"		case 'd': // 1 string to match.
	}		return Intrinsic::mips_msubv_d; // "ips.msubv.d"
	break;		case 'h': // 1 string to match.
	}		return Intrinsic::mips_msubv_h; // "ips.msubv.h"
	break;		case 'w': // 1 string to match.
	case 18: // 8 strings to match.		return Intrinsic::mips_msubv_w; // "ips.msubv.w"
	if (memcmp(NameR.data()+0, "ips.", 4))		}
	break;		break;
	switch (NameR[4]) {		case 'u': // 2 strings to match.
	default: break;		if (memcmp(NameR.data()+6, "l.q.", 4))
	case 'm': // 2 strings to match.		break;
	if (memcmp(NameR.data()+5, "uleu.s.ph.qb", 12))		switch (NameR[10]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::mips_mul_q_h; // "ips.mul.q.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_mul_q_w; // "ips.mul.q.w"
			}
	break;		break;
	switch (NameR[17]) {
	default: break;
	case 'l': // 1 string to match.
	return Intrinsic::mips_muleu_s_ph_qbl; // "ips.muleu.s.ph.
	qbl"
	case 'r': // 1 string to match.
	return Intrinsic::mips_muleu_s_ph_qbr; // "ips.muleu.s.ph.
	qbr"
	}		}
	break;		break;
	case 'p': // 6 strings to match.		case 'p': // 11 strings to match.
	if (memcmp(NameR.data()+5, "rec", 3))		switch (NameR[5]) {
	break;
	switch (NameR[8]) {
	default: break;		default: break;
	case 'e': // 4 strings to match.		case 'c': // 8 strings to match.
	switch (NameR[9]) {		if (NameR[6] != 'k')
			break;
			switch (NameR[7]) {
	default: break;		default: break;
	case 'q': // 2 strings to match.		case 'e': // 4 strings to match.
	if (memcmp(NameR.data()+10, "u.ph.qb", 7))		if (memcmp(NameR.data()+8, "v.", 2))
	break;		break;
	switch (NameR[17]) {		switch (NameR[10]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::mips_precequ_ph_qbl; // "ips.precequ.ph.		return Intrinsic::mips_pckev_b; // "ips.pckev.b"
	qbl"		case 'd': // 1 string to match.
	case 'r': // 1 string to match.		return Intrinsic::mips_pckev_d; // "ips.pckev.d"
	return Intrinsic::mips_precequ_ph_qbr; // "ips.precequ.ph.		case 'h': // 1 string to match.
	qbr"		return Intrinsic::mips_pckev_h; // "ips.pckev.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_pckev_w; // "ips.pckev.w"
	}		}
	break;		break;
	case 'u': // 2 strings to match.		case 'o': // 4 strings to match.
	if (memcmp(NameR.data()+10, ".ph.qb", 6))		if (memcmp(NameR.data()+8, "d.", 2))
	break;		break;
	switch (NameR[16]) {		switch (NameR[10]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'b': // 1 string to match.
	if (NameR[17] != 'a')		return Intrinsic::mips_pckod_b; // "ips.pckod.b"
	break;		case 'd': // 1 string to match.
	return Intrinsic::mips_preceu_ph_qbla; // "ips.preceu.ph.q		return Intrinsic::mips_pckod_d; // "ips.pckod.d"
	bla"		case 'h': // 1 string to match.
	case 'r': // 1 string to match.		return Intrinsic::mips_pckod_h; // "ips.pckod.h"
	if (NameR[17] != 'a')		case 'w': // 1 string to match.
	break;		return Intrinsic::mips_pckod_w; // "ips.pckod.w"
	return Intrinsic::mips_preceu_ph_qbra; // "ips.preceu.ph.q
	bra"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'r': // 2 strings to match.		case 'i': // 2 strings to match.
			if (memcmp(NameR.data()+6, "ck.", 3))
			break;
	switch (NameR[9]) {		switch (NameR[9]) {
	default: break;		default: break;
	case '.': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(NameR.data()+10, "sra.ph.w", 8))		if (NameR[10] != 'h')
	break;		break;
	return Intrinsic::mips_precr_sra_ph_w; // "ips.precr.sra.p h.w"		return Intrinsic::mips_pick_ph; // "ips.pick.ph"
	case 'q': // 1 string to match.		case 'q': // 1 string to match.
	if (memcmp(NameR.data()+10, ".rs.ph.w", 8))		if (NameR[10] != 'b')
	break;		break;
	return Intrinsic::mips_precrq_rs_ph_w; // "ips.precrq.rs.p h.w"		return Intrinsic::mips_pick_qb; // "ips.pick.qb"
	}		}
	break;		break;
			case 'r': // 1 string to match.
			if (memcmp(NameR.data()+6, "epend", 5))
			break;
			return Intrinsic::mips_prepend; // "ips.prepend"
	}		}
	break;		break;
	}		case 'r': // 2 strings to match.
	break;		if (memcmp(NameR.data()+5, "epl.", 4))
	case 19: // 3 strings to match.
	if (memcmp(NameR.data()+0, "ips.prec", 8))
	break;
	switch (NameR[8]) {
	default: break;
	case 'e': // 2 strings to match.
	if (memcmp(NameR.data()+9, "qu.ph.qb", 8))
	break;		break;
	switch (NameR[17]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'p': // 1 string to match.
	if (NameR[18] != 'a')		if (NameR[10] != 'h')
	break;		break;
	return Intrinsic::mips_precequ_ph_qbla; // "ips.precequ.ph.		return Intrinsic::mips_repl_ph; // "ips.repl.ph"
	qbla"		case 'q': // 1 string to match.
	case 'r': // 1 string to match.		if (NameR[10] != 'b')
	if (NameR[18] != 'a')
	break;		break;
	return Intrinsic::mips_precequ_ph_qbra; // "ips.precequ.ph. qbra"		return Intrinsic::mips_repl_qb; // "ips.repl.qb"
	}		}
	break;		break;
	case 'r': // 1 string to match.		case 's': // 34 strings to match.
	if (memcmp(NameR.data()+9, "qu.s.qb.ph", 10))
	break;
	return Intrinsic::mips_precrqu_s_qb_ph; // "ips.precrqu.s.q
	b.ph"
	}
	break;
	case 20: // 1 string to match.
	if (memcmp(NameR.data()+0, "ips.precr.sra.r.ph.w", 20))
	break;
	return Intrinsic::mips_precr_sra_r_ph_w; // "ips.precr.sra.r.ph.w"
	}
	break; // end of 'm' case.
	case 'n':
	if (NameR.startswith("earbyint.")) return Intrinsic::nearbyint;
	if (NameR.startswith("vvm.atomic.load.add.f32.")) return Intrinsic::nvv
	m_atomic_load_add_f32;
	if (NameR.startswith("vvm.atomic.load.dec.32.")) return Intrinsic::nvvm
	_atomic_load_dec_32;
	if (NameR.startswith("vvm.atomic.load.inc.32.")) return Intrinsic::nvvm
	_atomic_load_inc_32;
	if (NameR.startswith("vvm.compiler.error.")) return Intrinsic::nvvm_com
	piler_error;
	if (NameR.startswith("vvm.compiler.warn.")) return Intrinsic::nvvm_comp
	iler_warn;
	if (NameR.startswith("vvm.ldg.global.f.")) return Intrinsic::nvvm_ldg_g
	lobal_f;
	if (NameR.startswith("vvm.ldg.global.i.")) return Intrinsic::nvvm_ldg_g
	lobal_i;
	if (NameR.startswith("vvm.ldg.global.p.")) return Intrinsic::nvvm_ldg_g
	lobal_p;
	if (NameR.startswith("vvm.ldu.global.f.")) return Intrinsic::nvvm_ldu_g
	lobal_f;
	if (NameR.startswith("vvm.ldu.global.i.")) return Intrinsic::nvvm_ldu_g
	lobal_i;
	if (NameR.startswith("vvm.ldu.global.p.")) return Intrinsic::nvvm_ldu_g
	lobal_p;
	if (NameR.startswith("vvm.move.ptr.")) return Intrinsic::nvvm_move_ptr;
	if (NameR.startswith("vvm.ptr.constant.to.gen.")) return Intrinsic::nvv
	m_ptr_constant_to_gen;
	if (NameR.startswith("vvm.ptr.gen.to.constant.")) return Intrinsic::nvv
	m_ptr_gen_to_constant;
	if (NameR.startswith("vvm.ptr.gen.to.global.")) return Intrinsic::nvvm_
	ptr_gen_to_global;
	if (NameR.startswith("vvm.ptr.gen.to.local.")) return Intrinsic::nvvm_p
	tr_gen_to_local;
	if (NameR.startswith("vvm.ptr.gen.to.param.")) return Intrinsic::nvvm_p
	tr_gen_to_param;
	if (NameR.startswith("vvm.ptr.gen.to.shared.")) return Intrinsic::nvvm_
	ptr_gen_to_shared;
	if (NameR.startswith("vvm.ptr.global.to.gen.")) return Intrinsic::nvvm_
	ptr_global_to_gen;
	if (NameR.startswith("vvm.ptr.local.to.gen.")) return Intrinsic::nvvm_p
	tr_local_to_gen;
	if (NameR.startswith("vvm.ptr.shared.to.gen.")) return Intrinsic::nvvm_
	ptr_shared_to_gen;
	switch (NameR.size()) {
	default: break;
	case 7: // 1 string to match.
	if (memcmp(NameR.data()+0, "vvm.h2f", 7))
	break;
	return Intrinsic::nvvm_h2f; // "vvm.h2f"
	case 8: // 1 string to match.
	if (memcmp(NameR.data()+0, "vvm.prmt", 8))
	break;
	return Intrinsic::nvvm_prmt; // "vvm.prmt"
	case 9: // 5 strings to match.
	if (memcmp(NameR.data()+0, "vvm.", 4))
	break;
	switch (NameR[4]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(NameR.data()+5, "bs.i", 4))
	break;
	return Intrinsic::nvvm_abs_i; // "vvm.abs.i"
	case 'c': // 1 string to match.
	if (memcmp(NameR.data()+5, "lz.i", 4))
	break;
	return Intrinsic::nvvm_clz_i; // "vvm.clz.i"
	case 'm': // 2 strings to match.
	switch (NameR[5]) {		switch (NameR[5]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'a': // 8 strings to match.
	if (memcmp(NameR.data()+6, "x.i", 3))		if (memcmp(NameR.data()+6, "t.", 2))
	break;		break;
	return Intrinsic::nvvm_max_i; // "vvm.max.i"		switch (NameR[8]) {
	case 'i': // 1 string to match.		default: break;
	if (memcmp(NameR.data()+6, "n.i", 3))		case 's': // 4 strings to match.
			if (NameR[9] != '.')
			break;
			switch (NameR[10]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_sat_s_b; // "ips.sat.s.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_sat_s_d; // "ips.sat.s.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_sat_s_h; // "ips.sat.s.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_sat_s_w; // "ips.sat.s.w"
			}
	break;		break;
	return Intrinsic::nvvm_min_i; // "vvm.min.i"		case 'u': // 4 strings to match.
	}		if (NameR[9] != '.')
	break;		break;
	case 's': // 1 string to match.		switch (NameR[10]) {
	if (memcmp(NameR.data()+5, "ad.i", 4))		default: break;
	break;		case 'b': // 1 string to match.
	return Intrinsic::nvvm_sad_i; // "vvm.sad.i"		return Intrinsic::mips_sat_u_b; // "ips.sat.u.b"
	}		case 'd': // 1 string to match.
	break;		return Intrinsic::mips_sat_u_d; // "ips.sat.u.d"
	case 10: // 42 strings to match.		case 'h': // 1 string to match.
	if (memcmp(NameR.data()+0, "vvm.", 4))		return Intrinsic::mips_sat_u_h; // "ips.sat.u.h"
	break;		case 'w': // 1 string to match.
	switch (NameR[4]) {		return Intrinsic::mips_sat_u_w; // "ips.sat.u.w"
	default: break;		}
	case 'a': // 1 string to match.		break;
	if (memcmp(NameR.data()+5, "bs.ll", 5))		}
	break;
	return Intrinsic::nvvm_abs_ll; // "vvm.abs.ll"
	case 'b': // 2 strings to match.
	if (memcmp(NameR.data()+5, "rev", 3))
	break;		break;
	switch (NameR[8]) {		case 'h': // 6 strings to match.
	default: break;		switch (NameR[6]) {
	case '3': // 1 string to match.		default: break;
	if (NameR[9] != '2')		case 'l': // 2 strings to match.
			if (memcmp(NameR.data()+7, "l.", 2))
			break;
			switch (NameR[9]) {
			default: break;
			case 'p': // 1 string to match.
			if (NameR[10] != 'h')
			break;
			return Intrinsic::mips_shll_ph; // "ips.shll.ph"
			case 'q': // 1 string to match.
			if (NameR[10] != 'b')
			break;
			return Intrinsic::mips_shll_qb; // "ips.shll.qb"
			}
	break;		break;
	return Intrinsic::nvvm_brev32; // "vvm.brev32"		case 'r': // 4 strings to match.
	case '6': // 1 string to match.		switch (NameR[7]) {
	if (NameR[9] != '4')		default: break;
			case 'a': // 2 strings to match.
			if (NameR[8] != '.')
			break;
			switch (NameR[9]) {
			default: break;
			case 'p': // 1 string to match.
			if (NameR[10] != 'h')
			break;
			return Intrinsic::mips_shra_ph; // "ips.shra.ph"
			case 'q': // 1 string to match.
			if (NameR[10] != 'b')
			break;
			return Intrinsic::mips_shra_qb; // "ips.shra.qb"
			}
			break;
			case 'l': // 2 strings to match.
			if (NameR[8] != '.')
			break;
			switch (NameR[9]) {
			default: break;
			case 'p': // 1 string to match.
			if (NameR[10] != 'h')
			break;
			return Intrinsic::mips_shrl_ph; // "ips.shrl.ph"
			case 'q': // 1 string to match.
			if (NameR[10] != 'b')
			break;
			return Intrinsic::mips_shrl_qb; // "ips.shrl.qb"
			}
			break;
			}
	break;		break;
	return Intrinsic::nvvm_brev64; // "vvm.brev64"		}
	}		break;
	break;		case 'p': // 4 strings to match.
	case 'c': // 3 strings to match.		if (memcmp(NameR.data()+6, "lat.", 4))
	switch (NameR[5]) {
	default: break;
	case 'e': // 2 strings to match.
	if (memcmp(NameR.data()+6, "il.", 3))
	break;		break;
	switch (NameR[9]) {		switch (NameR[10]) {
	default: break;		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_splat_b; // "ips.splat.b"
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::nvvm_ceil_d; // "vvm.ceil.d"		return Intrinsic::mips_splat_d; // "ips.splat.d"
	case 'f': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::nvvm_ceil_f; // "vvm.ceil.f"		return Intrinsic::mips_splat_h; // "ips.splat.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_splat_w; // "ips.splat.w"
	}		}
	break;		break;
	case 'l': // 1 string to match.		case 'r': // 8 strings to match.
	if (memcmp(NameR.data()+6, "z.ll", 4))		switch (NameR[6]) {
			default: break;
			case 'a': // 4 strings to match.
			if (memcmp(NameR.data()+7, "ri.", 3))
			break;
			switch (NameR[10]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_srari_b; // "ips.srari.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_srari_d; // "ips.srari.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_srari_h; // "ips.srari.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_srari_w; // "ips.srari.w"
			}
	break;		break;
	return Intrinsic::nvvm_clz_ll; // "vvm.clz.ll"		case 'l': // 4 strings to match.
	}		if (memcmp(NameR.data()+7, "ri.", 3))
	break;		break;
	case 'd': // 10 strings to match.		switch (NameR[10]) {
	if (NameR[5] != '2')		default: break;
	break;		case 'b': // 1 string to match.
	switch (NameR[6]) {		return Intrinsic::mips_srlri_b; // "ips.srlri.b"
	default: break;		case 'd': // 1 string to match.
	case 'f': // 4 strings to match.		return Intrinsic::mips_srlri_d; // "ips.srlri.d"
	if (memcmp(NameR.data()+7, ".r", 2))		case 'h': // 1 string to match.
			return Intrinsic::mips_srlri_h; // "ips.srlri.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_srlri_w; // "ips.srlri.w"
			}
	break;		break;
	switch (NameR[9]) {
	default: break;
	case 'm': // 1 string to match.
	return Intrinsic::nvvm_d2f_rm; // "vvm.d2f.rm"
	case 'n': // 1 string to match.
	return Intrinsic::nvvm_d2f_rn; // "vvm.d2f.rn"
	case 'p': // 1 string to match.
	return Intrinsic::nvvm_d2f_rp; // "vvm.d2f.rp"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_d2f_rz; // "vvm.d2f.rz"
	}		}
	break;		break;
	case 'i': // 6 strings to match.		case 'u': // 8 strings to match.
	if (NameR[7] != '.')		if (NameR[6] != 'b')
	break;		break;
	switch (NameR[8]) {		switch (NameR[7]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'q': // 2 strings to match.
	if (NameR[9] != 'i')		switch (NameR[8]) {
	break;		default: break;
	return Intrinsic::nvvm_d2i_hi; // "vvm.d2i.hi"		case '.': // 1 string to match.
	case 'l': // 1 string to match.		if (memcmp(NameR.data()+9, "ph", 2))
	if (NameR[9] != 'o')		break;
			return Intrinsic::mips_subq_ph; // "ips.subq.ph"
			case 'h': // 1 string to match.
			if (memcmp(NameR.data()+9, ".w", 2))
			break;
			return Intrinsic::mips_subqh_w; // "ips.subqh.w"
			}
			break;
			case 'u': // 2 strings to match.
			if (NameR[8] != '.')
	break;		break;
	return Intrinsic::nvvm_d2i_lo; // "vvm.d2i.lo"
	case 'r': // 4 strings to match.
	switch (NameR[9]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'm': // 1 string to match.
	return Intrinsic::nvvm_d2i_rm; // "vvm.d2i.rm"
	case 'n': // 1 string to match.
	return Intrinsic::nvvm_d2i_rn; // "vvm.d2i.rn"
	case 'p': // 1 string to match.		case 'p': // 1 string to match.
	return Intrinsic::nvvm_d2i_rp; // "vvm.d2i.rp"		if (NameR[10] != 'h')
	case 'z': // 1 string to match.		break;
	return Intrinsic::nvvm_d2i_rz; // "vvm.d2i.rz"		return Intrinsic::mips_subu_ph; // "ips.subu.ph"
			case 'q': // 1 string to match.
			if (NameR[10] != 'b')
			break;
			return Intrinsic::mips_subu_qb; // "ips.subu.qb"
			}
			break;
			case 'v': // 4 strings to match.
			if (memcmp(NameR.data()+8, "i.", 2))
			break;
			switch (NameR[10]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_subvi_b; // "ips.subvi.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_subvi_d; // "ips.subvi.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_subvi_h; // "ips.subvi.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_subvi_w; // "ips.subvi.w"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'f': // 11 strings to match.		}
			break;
			case 12: // 144 strings to match.
			if (memcmp(NameR.data()+0, "ips.", 4))
			break;
			switch (NameR[4]) {
			default: break;
			case 'a': // 32 strings to match.
	switch (NameR[5]) {		switch (NameR[5]) {
	default: break;		default: break;
	case '2': // 5 strings to match.		case 'b': // 1 string to match.
	switch (NameR[6]) {		if (memcmp(NameR.data()+6, "sq.s.w", 6))
			break;
			return Intrinsic::mips_absq_s_w; // "ips.absq.s.w"
			case 'd': // 15 strings to match.
			if (NameR[6] != 'd')
			break;
			switch (NameR[7]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'q': // 2 strings to match.
	if (memcmp(NameR.data()+7, ".rn", 3))		switch (NameR[8]) {
	break;		default: break;
	return Intrinsic::nvvm_f2h_rn; // "vvm.f2h.rn"		case '.': // 1 string to match.
	case 'i': // 4 strings to match.		if (memcmp(NameR.data()+9, "s.w", 3))
	if (memcmp(NameR.data()+7, ".r", 2))		break;
			return Intrinsic::mips_addq_s_w; // "ips.addq.s.w"
			case 'h': // 1 string to match.
			if (memcmp(NameR.data()+9, ".ph", 3))
			break;
			return Intrinsic::mips_addqh_ph; // "ips.addqh.ph"
			}
			break;
			case 's': // 12 strings to match.
			if (NameR[8] != '.')
	break;		break;
	switch (NameR[9]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'a': // 4 strings to match.
	return Intrinsic::nvvm_f2i_rm; // "vvm.f2i.rm"		if (NameR[10] != '.')
	case 'n': // 1 string to match.		break;
	return Intrinsic::nvvm_f2i_rn; // "vvm.f2i.rn"		switch (NameR[11]) {
	case 'p': // 1 string to match.		default: break;
	return Intrinsic::nvvm_f2i_rp; // "vvm.f2i.rp"		case 'b': // 1 string to match.
	case 'z': // 1 string to match.		return Intrinsic::mips_adds_a_b; // "ips.adds.a.b"
	return Intrinsic::nvvm_f2i_rz; // "vvm.f2i.rz"		case 'd': // 1 string to match.
			return Intrinsic::mips_adds_a_d; // "ips.adds.a.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_adds_a_h; // "ips.adds.a.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_adds_a_w; // "ips.adds.a.w"
			}
			break;
			case 's': // 4 strings to match.
			if (NameR[10] != '.')
			break;
			switch (NameR[11]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_adds_s_b; // "ips.adds.s.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_adds_s_d; // "ips.adds.s.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_adds_s_h; // "ips.adds.s.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_adds_s_w; // "ips.adds.s.w"
			}
			break;
			case 'u': // 4 strings to match.
			if (NameR[10] != '.')
			break;
			switch (NameR[11]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_adds_u_b; // "ips.adds.u.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_adds_u_d; // "ips.adds.u.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_adds_u_h; // "ips.adds.u.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_adds_u_w; // "ips.adds.u.w"
			}
			break;
	}		}
	break;		break;
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+8, "h.qb", 4))
			break;
			return Intrinsic::mips_adduh_qb; // "ips.adduh.qb"
	}		}
	break;		break;
	case 'a': // 2 strings to match.		case 's': // 8 strings to match.
	if (memcmp(NameR.data()+6, "bs.", 3))		if (memcmp(NameR.data()+6, "ub.", 3))
	break;		break;
	switch (NameR[9]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 's': // 4 strings to match.
	return Intrinsic::nvvm_fabs_d; // "vvm.fabs.d"		if (NameR[10] != '.')
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_fabs_f; // "vvm.fabs.f"
	}
	break;
	case 'm': // 4 strings to match.
	switch (NameR[6]) {
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(NameR.data()+7, "x.", 2))
	break;		break;
	switch (NameR[9]) {		switch (NameR[11]) {
	default: break;		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_asub_s_b; // "ips.asub.s.b"
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::nvvm_fmax_d; // "vvm.fmax.d"		return Intrinsic::mips_asub_s_d; // "ips.asub.s.d"
	case 'f': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::nvvm_fmax_f; // "vvm.fmax.f"		return Intrinsic::mips_asub_s_h; // "ips.asub.s.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_asub_s_w; // "ips.asub.s.w"
	}		}
	break;		break;
	case 'i': // 2 strings to match.		case 'u': // 4 strings to match.
	if (memcmp(NameR.data()+7, "n.", 2))		if (NameR[10] != '.')
	break;		break;
	switch (NameR[9]) {		switch (NameR[11]) {
	default: break;		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_asub_u_b; // "ips.asub.u.b"
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::nvvm_fmin_d; // "vvm.fmin.d"		return Intrinsic::mips_asub_u_d; // "ips.asub.u.d"
	case 'f': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::nvvm_fmin_f; // "vvm.fmin.f"		return Intrinsic::mips_asub_u_h; // "ips.asub.u.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_asub_u_w; // "ips.asub.u.w"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'v': // 8 strings to match.
	break;		if (memcmp(NameR.data()+6, "er.", 3))
	case 'i': // 8 strings to match.
	if (NameR[5] != '2')
	break;
	switch (NameR[6]) {
	default: break;
	case 'd': // 4 strings to match.
	if (memcmp(NameR.data()+7, ".r", 2))
	break;		break;
	switch (NameR[9]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 's': // 4 strings to match.
	return Intrinsic::nvvm_i2d_rm; // "vvm.i2d.rm"		if (NameR[10] != '.')
	case 'n': // 1 string to match.		break;
	return Intrinsic::nvvm_i2d_rn; // "vvm.i2d.rn"		switch (NameR[11]) {
	case 'p': // 1 string to match.		default: break;
	return Intrinsic::nvvm_i2d_rp; // "vvm.i2d.rp"		case 'b': // 1 string to match.
	case 'z': // 1 string to match.		return Intrinsic::mips_aver_s_b; // "ips.aver.s.b"
	return Intrinsic::nvvm_i2d_rz; // "vvm.i2d.rz"		case 'd': // 1 string to match.
	}		return Intrinsic::mips_aver_s_d; // "ips.aver.s.d"
	break;		case 'h': // 1 string to match.
	case 'f': // 4 strings to match.		return Intrinsic::mips_aver_s_h; // "ips.aver.s.h"
	if (memcmp(NameR.data()+7, ".r", 2))		case 'w': // 1 string to match.
			return Intrinsic::mips_aver_s_w; // "ips.aver.s.w"
			}
			break;
			case 'u': // 4 strings to match.
			if (NameR[10] != '.')
			break;
			switch (NameR[11]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_aver_u_b; // "ips.aver.u.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_aver_u_d; // "ips.aver.u.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_aver_u_h; // "ips.aver.u.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_aver_u_w; // "ips.aver.u.w"
			}
	break;		break;
	switch (NameR[9]) {
	default: break;
	case 'm': // 1 string to match.
	return Intrinsic::nvvm_i2f_rm; // "vvm.i2f.rm"
	case 'n': // 1 string to match.
	return Intrinsic::nvvm_i2f_rn; // "vvm.i2f.rn"
	case 'p': // 1 string to match.
	return Intrinsic::nvvm_i2f_rp; // "vvm.i2f.rp"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_i2f_rz; // "vvm.i2f.rz"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'm': // 4 strings to match.		case 'b': // 9 strings to match.
	switch (NameR[5]) {		switch (NameR[5]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'i': // 8 strings to match.
	if (memcmp(NameR.data()+6, "x.", 2))		if (memcmp(NameR.data()+6, "ns", 2))
	break;		break;
	switch (NameR[8]) {		switch (NameR[8]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'l': // 4 strings to match.
	if (NameR[9] != 'l')		if (memcmp(NameR.data()+9, "i.", 2))
	break;
	return Intrinsic::nvvm_max_ll; // "vvm.max.ll"
	case 'u': // 1 string to match.
	if (NameR[9] != 'i')
	break;		break;
	return Intrinsic::nvvm_max_ui; // "vvm.max.ui"		switch (NameR[11]) {
	}		default: break;
	break;		case 'b': // 1 string to match.
	case 'i': // 2 strings to match.		return Intrinsic::mips_binsli_b; // "ips.binsli.b"
	if (memcmp(NameR.data()+6, "n.", 2))		case 'd': // 1 string to match.
			return Intrinsic::mips_binsli_d; // "ips.binsli.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_binsli_h; // "ips.binsli.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_binsli_w; // "ips.binsli.w"
			}
	break;		break;
	switch (NameR[8]) {		case 'r': // 4 strings to match.
	default: break;		if (memcmp(NameR.data()+9, "i.", 2))
	case 'l': // 1 string to match.
	if (NameR[9] != 'l')
	break;
	return Intrinsic::nvvm_min_ll; // "vvm.min.ll"
	case 'u': // 1 string to match.
	if (NameR[9] != 'i')
	break;		break;
	return Intrinsic::nvvm_min_ui; // "vvm.min.ui"		switch (NameR[11]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_binsri_b; // "ips.binsri.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_binsri_d; // "ips.binsri.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_binsri_h; // "ips.binsri.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_binsri_w; // "ips.binsri.w"
			}
			break;
	}		}
	break;		break;
	}		case 'p': // 1 string to match.
	break;		if (memcmp(NameR.data()+6, "osge32", 6))
	case 'p': // 1 string to match.
	if (memcmp(NameR.data()+5, "opc.i", 5))
	break;
	return Intrinsic::nvvm_popc_i; // "vvm.popc.i"
	case 's': // 2 strings to match.
	switch (NameR[5]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(NameR.data()+6, "d.ui", 4))
	break;
	return Intrinsic::nvvm_sad_ui; // "vvm.sad.ui"
	case 'q': // 1 string to match.
	if (memcmp(NameR.data()+6, "rt.f", 4))
	break;		break;
	return Intrinsic::nvvm_sqrt_f; // "vvm.sqrt.f"		return Intrinsic::mips_bposge32; // "ips.bposge32"
	}		}
	break;		break;
	}		case 'c': // 24 strings to match.
	break;		switch (NameR[5]) {
	case 11: // 44 strings to match.
	if (memcmp(NameR.data()+0, "vvm.", 4))
	break;
	switch (NameR[4]) {
	default: break;
	case 'd': // 8 strings to match.
	if (NameR[5] != '2')
	break;
	switch (NameR[6]) {
	default: break;		default: break;
	case 'l': // 4 strings to match.		case 'l': // 16 strings to match.
	if (memcmp(NameR.data()+7, "l.r", 3))		switch (NameR[6]) {
	break;
	switch (NameR[10]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'e': // 8 strings to match.
	return Intrinsic::nvvm_d2ll_rm; // "vvm.d2ll.rm"		if (memcmp(NameR.data()+7, "i.", 2))
	case 'n': // 1 string to match.
	return Intrinsic::nvvm_d2ll_rn; // "vvm.d2ll.rn"
	case 'p': // 1 string to match.
	return Intrinsic::nvvm_d2ll_rp; // "vvm.d2ll.rp"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_d2ll_rz; // "vvm.d2ll.rz"
	}
	break;
	case 'u': // 4 strings to match.
	if (memcmp(NameR.data()+7, "i.r", 3))
	break;
	switch (NameR[10]) {
	default: break;
	case 'm': // 1 string to match.
	return Intrinsic::nvvm_d2ui_rm; // "vvm.d2ui.rm"
	case 'n': // 1 string to match.
	return Intrinsic::nvvm_d2ui_rn; // "vvm.d2ui.rn"
	case 'p': // 1 string to match.
	return Intrinsic::nvvm_d2ui_rp; // "vvm.d2ui.rp"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_d2ui_rz; // "vvm.d2ui.rz"
	}
	break;
	}
	break;
	case 'f': // 10 strings to match.
	switch (NameR[5]) {
	default: break;
	case '2': // 8 strings to match.
	switch (NameR[6]) {
	default: break;
	case 'l': // 4 strings to match.
	if (memcmp(NameR.data()+7, "l.r", 3))
	break;		break;
	switch (NameR[10]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 's': // 4 strings to match.
	return Intrinsic::nvvm_f2ll_rm; // "vvm.f2ll.rm"		if (NameR[10] != '.')
	case 'n': // 1 string to match.		break;
	return Intrinsic::nvvm_f2ll_rn; // "vvm.f2ll.rn"		switch (NameR[11]) {
	case 'p': // 1 string to match.		default: break;
	return Intrinsic::nvvm_f2ll_rp; // "vvm.f2ll.rp"		case 'b': // 1 string to match.
	case 'z': // 1 string to match.		return Intrinsic::mips_clei_s_b; // "ips.clei.s.b"
	return Intrinsic::nvvm_f2ll_rz; // "vvm.f2ll.rz"		case 'd': // 1 string to match.
			return Intrinsic::mips_clei_s_d; // "ips.clei.s.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_clei_s_h; // "ips.clei.s.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_clei_s_w; // "ips.clei.s.w"
			}
			break;
			case 'u': // 4 strings to match.
			if (NameR[10] != '.')
			break;
			switch (NameR[11]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_clei_u_b; // "ips.clei.u.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_clei_u_d; // "ips.clei.u.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_clei_u_h; // "ips.clei.u.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_clei_u_w; // "ips.clei.u.w"
			}
			break;
	}		}
	break;		break;
	case 'u': // 4 strings to match.		case 't': // 8 strings to match.
	if (memcmp(NameR.data()+7, "i.r", 3))		if (memcmp(NameR.data()+7, "i.", 2))
	break;		break;
	switch (NameR[10]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 's': // 4 strings to match.
	return Intrinsic::nvvm_f2ui_rm; // "vvm.f2ui.rm"		if (NameR[10] != '.')
	case 'n': // 1 string to match.		break;
	return Intrinsic::nvvm_f2ui_rn; // "vvm.f2ui.rn"		switch (NameR[11]) {
	case 'p': // 1 string to match.		default: break;
	return Intrinsic::nvvm_f2ui_rp; // "vvm.f2ui.rp"		case 'b': // 1 string to match.
	case 'z': // 1 string to match.		return Intrinsic::mips_clti_s_b; // "ips.clti.s.b"
	return Intrinsic::nvvm_f2ui_rz; // "vvm.f2ui.rz"		case 'd': // 1 string to match.
			return Intrinsic::mips_clti_s_d; // "ips.clti.s.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_clti_s_h; // "ips.clti.s.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_clti_s_w; // "ips.clti.s.w"
			}
			break;
			case 'u': // 4 strings to match.
			if (NameR[10] != '.')
			break;
			switch (NameR[11]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_clti_u_b; // "ips.clti.u.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_clti_u_d; // "ips.clti.u.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_clti_u_h; // "ips.clti.u.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_clti_u_w; // "ips.clti.u.w"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'o': // 8 strings to match.
	if (memcmp(NameR.data()+6, "oor.", 4))		if (memcmp(NameR.data()+6, "py.", 3))
	break;		break;
	switch (NameR[10]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 's': // 4 strings to match.
	return Intrinsic::nvvm_floor_d; // "vvm.floor.d"		if (NameR[10] != '.')
	case 'f': // 1 string to match.		break;
	return Intrinsic::nvvm_floor_f; // "vvm.floor.f"		switch (NameR[11]) {
	}		default: break;
	break;		case 'b': // 1 string to match.
	}		return Intrinsic::mips_copy_s_b; // "ips.copy.s.b"
	break;		case 'd': // 1 string to match.
	case 'l': // 8 strings to match.		return Intrinsic::mips_copy_s_d; // "ips.copy.s.d"
	if (memcmp(NameR.data()+5, "l2", 2))		case 'h': // 1 string to match.
	break;		return Intrinsic::mips_copy_s_h; // "ips.copy.s.h"
	switch (NameR[7]) {		case 'w': // 1 string to match.
	default: break;		return Intrinsic::mips_copy_s_w; // "ips.copy.s.w"
	case 'd': // 4 strings to match.		}
	if (memcmp(NameR.data()+8, ".r", 2))
	break;		break;
	switch (NameR[10]) {		case 'u': // 4 strings to match.
	default: break;		if (NameR[10] != '.')
	case 'm': // 1 string to match.		break;
	return Intrinsic::nvvm_ll2d_rm; // "vvm.ll2d.rm"		switch (NameR[11]) {
	case 'n': // 1 string to match.		default: break;
	return Intrinsic::nvvm_ll2d_rn; // "vvm.ll2d.rn"		case 'b': // 1 string to match.
	case 'p': // 1 string to match.		return Intrinsic::mips_copy_u_b; // "ips.copy.u.b"
	return Intrinsic::nvvm_ll2d_rp; // "vvm.ll2d.rp"		case 'd': // 1 string to match.
	case 'z': // 1 string to match.		return Intrinsic::mips_copy_u_d; // "ips.copy.u.d"
	return Intrinsic::nvvm_ll2d_rz; // "vvm.ll2d.rz"		case 'h': // 1 string to match.
	}		return Intrinsic::mips_copy_u_h; // "ips.copy.u.h"
	break;		case 'w': // 1 string to match.
	case 'f': // 4 strings to match.		return Intrinsic::mips_copy_u_w; // "ips.copy.u.w"
	if (memcmp(NameR.data()+8, ".r", 2))		}
	break;		break;
	switch (NameR[10]) {
	default: break;
	case 'm': // 1 string to match.
	return Intrinsic::nvvm_ll2f_rm; // "vvm.ll2f.rm"
	case 'n': // 1 string to match.
	return Intrinsic::nvvm_ll2f_rn; // "vvm.ll2f.rn"
	case 'p': // 1 string to match.
	return Intrinsic::nvvm_ll2f_rp; // "vvm.ll2f.rp"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_ll2f_rz; // "vvm.ll2f.rz"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'm': // 5 strings to match.		case 'd': // 8 strings to match.
	switch (NameR[5]) {		switch (NameR[5]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'o': // 6 strings to match.
	if (memcmp(NameR.data()+6, "x.ull", 5))		if (memcmp(NameR.data()+6, "tp.", 3))
	break;
	return Intrinsic::nvvm_max_ull; // "vvm.max.ull"
	case 'i': // 1 string to match.
	if (memcmp(NameR.data()+6, "n.ull", 5))
	break;		break;
	return Intrinsic::nvvm_min_ull; // "vvm.min.ull"		switch (NameR[9]) {
	case 'o': // 1 string to match.
	if (memcmp(NameR.data()+6, "ve.i8", 5))
	break;
	return Intrinsic::nvvm_move_i8; // "vvm.move.i8"
	case 'u': // 2 strings to match.
	if (NameR[6] != 'l')
	break;
	switch (NameR[7]) {
	default: break;		default: break;
	case '2': // 1 string to match.		case 's': // 3 strings to match.
	if (memcmp(NameR.data()+8, "4.i", 3))		if (NameR[10] != '.')
	break;		break;
	return Intrinsic::nvvm_mul24_i; // "vvm.mul24.i"		switch (NameR[11]) {
	case 'h': // 1 string to match.		default: break;
	if (memcmp(NameR.data()+8, "i.i", 3))		case 'd': // 1 string to match.
			return Intrinsic::mips_dotp_s_d; // "ips.dotp.s.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_dotp_s_h; // "ips.dotp.s.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_dotp_s_w; // "ips.dotp.s.w"
			}
			break;
			case 'u': // 3 strings to match.
			if (NameR[10] != '.')
	break;		break;
	return Intrinsic::nvvm_mulhi_i; // "vvm.mulhi.i"		switch (NameR[11]) {
	}		default: break;
	break;		case 'd': // 1 string to match.
	}		return Intrinsic::mips_dotp_u_d; // "ips.dotp.u.d"
	break;		case 'h': // 1 string to match.
	case 'p': // 1 string to match.		return Intrinsic::mips_dotp_u_h; // "ips.dotp.u.h"
	if (memcmp(NameR.data()+5, "opc.ll", 6))		case 'w': // 1 string to match.
	break;		return Intrinsic::mips_dotp_u_w; // "ips.dotp.u.w"
	return Intrinsic::nvvm_popc_ll; // "vvm.popc.ll"		}
	case 'r': // 2 strings to match.
	if (memcmp(NameR.data()+5, "ound.", 5))
	break;
	switch (NameR[10]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_round_d; // "vvm.round.d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_round_f; // "vvm.round.f"
	}
	break;
	case 't': // 2 strings to match.
	if (memcmp(NameR.data()+5, "runc.", 5))
	break;
	switch (NameR[10]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_trunc_d; // "vvm.trunc.d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_trunc_f; // "vvm.trunc.f"
	}
	break;
	case 'u': // 8 strings to match.
	if (memcmp(NameR.data()+5, "i2", 2))
	break;
	switch (NameR[7]) {
	default: break;
	case 'd': // 4 strings to match.
	if (memcmp(NameR.data()+8, ".r", 2))
	break;		break;
	switch (NameR[10]) {
	default: break;
	case 'm': // 1 string to match.
	return Intrinsic::nvvm_ui2d_rm; // "vvm.ui2d.rm"
	case 'n': // 1 string to match.
	return Intrinsic::nvvm_ui2d_rn; // "vvm.ui2d.rn"
	case 'p': // 1 string to match.
	return Intrinsic::nvvm_ui2d_rp; // "vvm.ui2d.rp"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_ui2d_rz; // "vvm.ui2d.rz"
	}		}
	break;		break;
	case 'f': // 4 strings to match.		case 'p': // 2 strings to match.
	if (memcmp(NameR.data()+8, ".r", 2))		switch (NameR[6]) {
	break;
	switch (NameR[10]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'a': // 1 string to match.
	return Intrinsic::nvvm_ui2f_rm; // "vvm.ui2f.rm"		if (memcmp(NameR.data()+7, ".w.ph", 5))
	case 'n': // 1 string to match.		break;
	return Intrinsic::nvvm_ui2f_rn; // "vvm.ui2f.rn"		return Intrinsic::mips_dpa_w_ph; // "ips.dpa.w.ph"
	case 'p': // 1 string to match.		case 's': // 1 string to match.
	return Intrinsic::nvvm_ui2f_rp; // "vvm.ui2f.rp"		if (memcmp(NameR.data()+7, ".w.ph", 5))
	case 'z': // 1 string to match.		break;
	return Intrinsic::nvvm_ui2f_rz; // "vvm.ui2f.rz"		return Intrinsic::mips_dps_w_ph; // "ips.dps.w.ph"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'e': // 2 strings to match.
	break;		if (memcmp(NameR.data()+5, "xtr.", 4))
	case 12: // 64 strings to match.
	if (memcmp(NameR.data()+0, "vvm.", 4))
	break;
	switch (NameR[4]) {
	default: break;
	case 'a': // 8 strings to match.
	if (memcmp(NameR.data()+5, "dd.r", 4))
	break;		break;
	switch (NameR[9]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'm': // 2 strings to match.		case 'r': // 1 string to match.
	if (NameR[10] != '.')		if (memcmp(NameR.data()+10, ".w", 2))
	break;
	switch (NameR[11]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_add_rm_d; // "vvm.add.rm.d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_add_rm_f; // "vvm.add.rm.f"
	}
	break;
	case 'n': // 2 strings to match.
	if (NameR[10] != '.')
	break;
	switch (NameR[11]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_add_rn_d; // "vvm.add.rn.d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_add_rn_f; // "vvm.add.rn.f"
	}
	break;
	case 'p': // 2 strings to match.
	if (NameR[10] != '.')
	break;		break;
	switch (NameR[11]) {		return Intrinsic::mips_extr_r_w; // "ips.extr.r.w"
	default: break;		case 's': // 1 string to match.
	case 'd': // 1 string to match.		if (memcmp(NameR.data()+10, ".h", 2))
	return Intrinsic::nvvm_add_rp_d; // "vvm.add.rp.d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_add_rp_f; // "vvm.add.rp.f"
	}
	break;
	case 'z': // 2 strings to match.
	if (NameR[10] != '.')
	break;		break;
	switch (NameR[11]) {		return Intrinsic::mips_extr_s_h; // "ips.extr.s.h"
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_add_rz_d; // "vvm.add.rz.d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_add_rz_f; // "vvm.add.rz.f"
	}
	break;
	}		}
	break;		break;
	case 'b': // 1 string to match.		case 'f': // 12 strings to match.
	if (memcmp(NameR.data()+5, "arrier0", 7))
	break;
	return Intrinsic::nvvm_barrier0; // "vvm.barrier0"
	case 'd': // 12 strings to match.
	switch (NameR[5]) {		switch (NameR[5]) {
	default: break;		default: break;
	case '2': // 4 strings to match.		case 'c': // 2 strings to match.
	if (memcmp(NameR.data()+6, "ull.r", 5))		if (memcmp(NameR.data()+6, "lass.", 5))
	break;		break;
	switch (NameR[11]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::nvvm_d2ull_rm; // "vvm.d2ull.rm"		return Intrinsic::mips_fclass_d; // "ips.fclass.d"
	case 'n': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::nvvm_d2ull_rn; // "vvm.d2ull.rn"		return Intrinsic::mips_fclass_w; // "ips.fclass.w"
	case 'p': // 1 string to match.
	return Intrinsic::nvvm_d2ull_rp; // "vvm.d2ull.rp"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_d2ull_rz; // "vvm.d2ull.rz"
	}		}
	break;		break;
	case 'i': // 8 strings to match.		case 'e': // 4 strings to match.
	if (memcmp(NameR.data()+6, "v.r", 3))		if (memcmp(NameR.data()+6, "xup", 3))
	break;		break;
	switch (NameR[9]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'm': // 2 strings to match.		case 'l': // 2 strings to match.
	if (NameR[10] != '.')		if (NameR[10] != '.')
	break;		break;
	switch (NameR[11]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::nvvm_div_rm_d; // "vvm.div.rm.d"		return Intrinsic::mips_fexupl_d; // "ips.fexupl.d"
	case 'f': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::nvvm_div_rm_f; // "vvm.div.rm.f"		return Intrinsic::mips_fexupl_w; // "ips.fexupl.w"
	}		}
	break;		break;
	case 'n': // 2 strings to match.		case 'r': // 2 strings to match.
	if (NameR[10] != '.')		if (NameR[10] != '.')
	break;		break;
	switch (NameR[11]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::nvvm_div_rn_d; // "vvm.div.rn.d"		return Intrinsic::mips_fexupr_d; // "ips.fexupr.d"
	case 'f': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::nvvm_div_rn_f; // "vvm.div.rn.f"		return Intrinsic::mips_fexupr_w; // "ips.fexupr.w"
	}		}
	break;		break;
	case 'p': // 2 strings to match.		}
	if (NameR[10] != '.')		break;
			case 'm': // 4 strings to match.
			switch (NameR[6]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(NameR.data()+7, "x.a.", 4))
	break;		break;
	switch (NameR[11]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::nvvm_div_rp_d; // "vvm.div.rp.d"		return Intrinsic::mips_fmax_a_d; // "ips.fmax.a.d"
	case 'f': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::nvvm_div_rp_f; // "vvm.div.rp.f"		return Intrinsic::mips_fmax_a_w; // "ips.fmax.a.w"
	}		}
	break;		break;
	case 'z': // 2 strings to match.		case 'i': // 2 strings to match.
	if (NameR[10] != '.')		if (memcmp(NameR.data()+7, "n.a.", 4))
	break;		break;
	switch (NameR[11]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::nvvm_div_rz_d; // "vvm.div.rz.d"		return Intrinsic::mips_fmin_a_d; // "ips.fmin.a.d"
	case 'f': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::nvvm_div_rz_f; // "vvm.div.rz.f"		return Intrinsic::mips_fmin_a_w; // "ips.fmin.a.w"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'r': // 2 strings to match.
	break;		if (memcmp(NameR.data()+6, "sqrt.", 5))
	case 'f': // 12 strings to match.
	switch (NameR[5]) {
	default: break;
	case '2': // 4 strings to match.
	if (memcmp(NameR.data()+6, "ull.r", 5))
	break;		break;
	switch (NameR[11]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::nvvm_f2ull_rm; // "vvm.f2ull.rm"		return Intrinsic::mips_frsqrt_d; // "ips.frsqrt.d"
	case 'n': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::nvvm_f2ull_rn; // "vvm.f2ull.rn"		return Intrinsic::mips_frsqrt_w; // "ips.frsqrt.w"
	case 'p': // 1 string to match.
	return Intrinsic::nvvm_f2ull_rp; // "vvm.f2ull.rp"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_f2ull_rz; // "vvm.f2ull.rz"
	}		}
	break;		break;
	case 'm': // 8 strings to match.		}
	if (memcmp(NameR.data()+6, "a.r", 3))		break;
			case 'h': // 12 strings to match.
			switch (NameR[5]) {
			default: break;
			case 'a': // 6 strings to match.
			if (memcmp(NameR.data()+6, "dd.", 3))
	break;		break;
	switch (NameR[9]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'm': // 2 strings to match.		case 's': // 3 strings to match.
	if (NameR[10] != '.')		if (NameR[10] != '.')
	break;		break;
	switch (NameR[11]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::nvvm_fma_rm_d; // "vvm.fma.rm.d"		return Intrinsic::mips_hadd_s_d; // "ips.hadd.s.d"
	case 'f': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::nvvm_fma_rm_f; // "vvm.fma.rm.f"		return Intrinsic::mips_hadd_s_h; // "ips.hadd.s.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_hadd_s_w; // "ips.hadd.s.w"
	}		}
	break;		break;
	case 'n': // 2 strings to match.		case 'u': // 3 strings to match.
	if (NameR[10] != '.')		if (NameR[10] != '.')
	break;		break;
	switch (NameR[11]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::nvvm_fma_rn_d; // "vvm.fma.rn.d"		return Intrinsic::mips_hadd_u_d; // "ips.hadd.u.d"
	case 'f': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::nvvm_fma_rn_f; // "vvm.fma.rn.f"		return Intrinsic::mips_hadd_u_h; // "ips.hadd.u.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_hadd_u_w; // "ips.hadd.u.w"
	}		}
	break;		break;
	case 'p': // 2 strings to match.		}
			break;
			case 's': // 6 strings to match.
			if (memcmp(NameR.data()+6, "ub.", 3))
			break;
			switch (NameR[9]) {
			default: break;
			case 's': // 3 strings to match.
	if (NameR[10] != '.')		if (NameR[10] != '.')
	break;		break;
	switch (NameR[11]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::nvvm_fma_rp_d; // "vvm.fma.rp.d"		return Intrinsic::mips_hsub_s_d; // "ips.hsub.s.d"
	case 'f': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::nvvm_fma_rp_f; // "vvm.fma.rp.f"		return Intrinsic::mips_hsub_s_h; // "ips.hsub.s.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_hsub_s_w; // "ips.hsub.s.w"
	}		}
	break;		break;
	case 'z': // 2 strings to match.		case 'u': // 3 strings to match.
	if (NameR[10] != '.')		if (NameR[10] != '.')
	break;		break;
	switch (NameR[11]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::nvvm_fma_rz_d; // "vvm.fma.rz.d"		return Intrinsic::mips_hsub_u_d; // "ips.hsub.u.d"
	case 'f': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::nvvm_fma_rz_f; // "vvm.fma.rz.f"		return Intrinsic::mips_hsub_u_h; // "ips.hsub.u.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_hsub_u_w; // "ips.hsub.u.w"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'l': // 1 string to match.		case 'i': // 4 strings to match.
	if (memcmp(NameR.data()+5, "ohi.i2d", 7))		if (memcmp(NameR.data()+5, "nsert.", 6))
	break;		break;
	return Intrinsic::nvvm_lohi_i2d; // "vvm.lohi.i2d"		switch (NameR[11]) {
	case 'm': // 14 strings to match.		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_insert_b; // "ips.insert.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_insert_d; // "ips.insert.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_insert_h; // "ips.insert.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_insert_w; // "ips.insert.w"
			}
			break;
			case 'm': // 24 strings to match.
	switch (NameR[5]) {		switch (NameR[5]) {
	default: break;		default: break;
	case 'o': // 3 strings to match.		case 'a': // 10 strings to match.
	if (memcmp(NameR.data()+6, "ve.i", 4))		switch (NameR[6]) {
	break;
	switch (NameR[10]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case 'd': // 2 strings to match.
	if (NameR[11] != '6')		if (memcmp(NameR.data()+7, "d.q.", 4))
	break;
	return Intrinsic::nvvm_move_i16; // "vvm.move.i16"
	case '3': // 1 string to match.
	if (NameR[11] != '2')
	break;
	return Intrinsic::nvvm_move_i32; // "vvm.move.i32"
	case '6': // 1 string to match.
	if (NameR[11] != '4')
	break;		break;
	return Intrinsic::nvvm_move_i64; // "vvm.move.i64"		switch (NameR[11]) {
	}		default: break;
	break;		case 'h': // 1 string to match.
	case 'u': // 11 strings to match.		return Intrinsic::mips_madd_q_h; // "ips.madd.q.h"
	if (NameR[6] != 'l')		case 'w': // 1 string to match.
			return Intrinsic::mips_madd_q_w; // "ips.madd.q.w"
			}
	break;		break;
	switch (NameR[7]) {		case 'x': // 8 strings to match.
	default: break;		if (memcmp(NameR.data()+7, "i.", 2))
	case '.': // 8 strings to match.
	if (NameR[8] != 'r')
	break;		break;
	switch (NameR[9]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'm': // 2 strings to match.		case 's': // 4 strings to match.
	if (NameR[10] != '.')
	break;
	switch (NameR[11]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_mul_rm_d; // "vvm.mul.rm.d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_mul_rm_f; // "vvm.mul.rm.f"
	}
	break;
	case 'n': // 2 strings to match.
	if (NameR[10] != '.')		if (NameR[10] != '.')
	break;		break;
	switch (NameR[11]) {		switch (NameR[11]) {
	default: break;		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_maxi_s_b; // "ips.maxi.s.b"
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::nvvm_mul_rn_d; // "vvm.mul.rn.d"		return Intrinsic::mips_maxi_s_d; // "ips.maxi.s.d"
	case 'f': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::nvvm_mul_rn_f; // "vvm.mul.rn.f"		return Intrinsic::mips_maxi_s_h; // "ips.maxi.s.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_maxi_s_w; // "ips.maxi.s.w"
	}		}
	break;		break;
	case 'p': // 2 strings to match.		case 'u': // 4 strings to match.
	if (NameR[10] != '.')		if (NameR[10] != '.')
	break;		break;
	switch (NameR[11]) {		switch (NameR[11]) {
	default: break;		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_maxi_u_b; // "ips.maxi.u.b"
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::nvvm_mul_rp_d; // "vvm.mul.rp.d"		return Intrinsic::mips_maxi_u_d; // "ips.maxi.u.d"
	case 'f': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::nvvm_mul_rp_f; // "vvm.mul.rp.f"		return Intrinsic::mips_maxi_u_h; // "ips.maxi.u.h"
	}		case 'w': // 1 string to match.
	break;		return Intrinsic::mips_maxi_u_w; // "ips.maxi.u.w"
	case 'z': // 2 strings to match.
	if (NameR[10] != '.')
	break;
	switch (NameR[11]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_mul_rz_d; // "vvm.mul.rz.d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_mul_rz_f; // "vvm.mul.rz.f"
	}		}
	break;		break;
	}		}
	break;		break;
	case '2': // 1 string to match.		}
	if (memcmp(NameR.data()+8, "4.ui", 4))		break;
			case 'i': // 8 strings to match.
			if (memcmp(NameR.data()+6, "ni.", 3))
			break;
			switch (NameR[9]) {
			default: break;
			case 's': // 4 strings to match.
			if (NameR[10] != '.')
	break;		break;
	return Intrinsic::nvvm_mul24_ui; // "vvm.mul24.ui"		switch (NameR[11]) {
	case 'h': // 2 strings to match.		default: break;
	if (memcmp(NameR.data()+8, "i.", 2))		case 'b': // 1 string to match.
			return Intrinsic::mips_mini_s_b; // "ips.mini.s.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_mini_s_d; // "ips.mini.s.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_mini_s_h; // "ips.mini.s.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_mini_s_w; // "ips.mini.s.w"
			}
			break;
			case 'u': // 4 strings to match.
			if (NameR[10] != '.')
	break;		break;
	switch (NameR[10]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'b': // 1 string to match.
	if (NameR[11] != 'l')		return Intrinsic::mips_mini_u_b; // "ips.mini.u.b"
	break;		case 'd': // 1 string to match.
	return Intrinsic::nvvm_mulhi_ll; // "vvm.mulhi.ll"		return Intrinsic::mips_mini_u_d; // "ips.mini.u.d"
	case 'u': // 1 string to match.		case 'h': // 1 string to match.
	if (NameR[11] != 'i')		return Intrinsic::mips_mini_u_h; // "ips.mini.u.h"
	break;		case 'w': // 1 string to match.
	return Intrinsic::nvvm_mulhi_ui; // "vvm.mulhi.ui"		return Intrinsic::mips_mini_u_w; // "ips.mini.u.w"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 's': // 2 strings to match.
	break;		if (memcmp(NameR.data()+6, "ub.q.", 5))
	case 'r': // 8 strings to match.
	if (memcmp(NameR.data()+5, "cp.r", 4))
	break;
	switch (NameR[9]) {
	default: break;
	case 'm': // 2 strings to match.
	if (NameR[10] != '.')
	break;		break;
	switch (NameR[11]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::nvvm_rcp_rm_d; // "vvm.rcp.rm.d"		return Intrinsic::mips_msub_q_h; // "ips.msub.q.h"
	case 'f': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::nvvm_rcp_rm_f; // "vvm.rcp.rm.f"		return Intrinsic::mips_msub_q_w; // "ips.msub.q.w"
	}		}
	break;		break;
	case 'n': // 2 strings to match.		case 'u': // 4 strings to match.
	if (NameR[10] != '.')		if (NameR[6] != 'l')
	break;		break;
	switch (NameR[11]) {		switch (NameR[7]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case '.': // 1 string to match.
	return Intrinsic::nvvm_rcp_rn_d; // "vvm.rcp.rn.d"		if (memcmp(NameR.data()+8, "s.ph", 4))
	case 'f': // 1 string to match.		break;
	return Intrinsic::nvvm_rcp_rn_f; // "vvm.rcp.rn.f"		return Intrinsic::mips_mul_s_ph; // "ips.mul.s.ph"
			case 'q': // 1 string to match.
			if (memcmp(NameR.data()+8, ".s.w", 4))
			break;
			return Intrinsic::mips_mulq_s_w; // "ips.mulq.s.w"
			case 'r': // 2 strings to match.
			if (memcmp(NameR.data()+8, ".q.", 3))
			break;
			switch (NameR[11]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::mips_mulr_q_h; // "ips.mulr.q.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_mulr_q_w; // "ips.mulr.q.w"
			}
			break;
	}		}
	break;		break;
	case 'p': // 2 strings to match.		}
	if (NameR[10] != '.')		break;
	break;		case 's': // 17 strings to match.
	switch (NameR[11]) {		switch (NameR[5]) {
			default: break;
			case 'h': // 2 strings to match.
			switch (NameR[6]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'l': // 1 string to match.
	return Intrinsic::nvvm_rcp_rp_d; // "vvm.rcp.rp.d"		if (memcmp(NameR.data()+7, "l.s.w", 5))
	case 'f': // 1 string to match.		break;
	return Intrinsic::nvvm_rcp_rp_f; // "vvm.rcp.rp.f"		return Intrinsic::mips_shll_s_w; // "ips.shll.s.w"
			case 'r': // 1 string to match.
			if (memcmp(NameR.data()+7, "a.r.w", 5))
			break;
			return Intrinsic::mips_shra_r_w; // "ips.shra.r.w"
	}		}
	break;		break;
	case 'z': // 2 strings to match.		case 'p': // 4 strings to match.
	if (NameR[10] != '.')		if (memcmp(NameR.data()+6, "lati.", 5))
	break;		break;
	switch (NameR[11]) {		switch (NameR[11]) {
	default: break;		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_splati_b; // "ips.splati.b"
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::nvvm_rcp_rz_d; // "vvm.rcp.rz.d"		return Intrinsic::mips_splati_d; // "ips.splati.d"
	case 'f': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::nvvm_rcp_rz_f; // "vvm.rcp.rz.f"		return Intrinsic::mips_splati_h; // "ips.splati.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_splati_w; // "ips.splati.w"
	}		}
	break;		break;
	}		case 'u': // 11 strings to match.
	break;		if (NameR[6] != 'b')
	case 'u': // 8 strings to match.
	if (memcmp(NameR.data()+5, "ll2", 3))
	break;
	switch (NameR[8]) {
	default: break;
	case 'd': // 4 strings to match.
	if (memcmp(NameR.data()+9, ".r", 2))
	break;		break;
	switch (NameR[11]) {		switch (NameR[7]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'q': // 2 strings to match.
	return Intrinsic::nvvm_ull2d_rm; // "vvm.ull2d.rm"		switch (NameR[8]) {
	case 'n': // 1 string to match.		default: break;
	return Intrinsic::nvvm_ull2d_rn; // "vvm.ull2d.rn"		case '.': // 1 string to match.
	case 'p': // 1 string to match.		if (memcmp(NameR.data()+9, "s.w", 3))
	return Intrinsic::nvvm_ull2d_rp; // "vvm.ull2d.rp"		break;
	case 'z': // 1 string to match.		return Intrinsic::mips_subq_s_w; // "ips.subq.s.w"
	return Intrinsic::nvvm_ull2d_rz; // "vvm.ull2d.rz"		case 'h': // 1 string to match.
	}		if (memcmp(NameR.data()+9, ".ph", 3))
	break;		break;
	case 'f': // 4 strings to match.		return Intrinsic::mips_subqh_ph; // "ips.subqh.ph"
	if (memcmp(NameR.data()+9, ".r", 2))		}
	break;		break;
	switch (NameR[11]) {		case 's': // 8 strings to match.
	default: break;		if (NameR[8] != '.')
	case 'm': // 1 string to match.		break;
	return Intrinsic::nvvm_ull2f_rm; // "vvm.ull2f.rm"		switch (NameR[9]) {
	case 'n': // 1 string to match.		default: break;
	return Intrinsic::nvvm_ull2f_rn; // "vvm.ull2f.rn"		case 's': // 4 strings to match.
	case 'p': // 1 string to match.		if (NameR[10] != '.')
	return Intrinsic::nvvm_ull2f_rp; // "vvm.ull2f.rp"		break;
	case 'z': // 1 string to match.		switch (NameR[11]) {
	return Intrinsic::nvvm_ull2f_rz; // "vvm.ull2f.rz"		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_subs_s_b; // "ips.subs.s.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_subs_s_d; // "ips.subs.s.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_subs_s_h; // "ips.subs.s.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_subs_s_w; // "ips.subs.s.w"
			}
			break;
			case 'u': // 4 strings to match.
			if (NameR[10] != '.')
			break;
			switch (NameR[11]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_subs_u_b; // "ips.subs.u.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_subs_u_d; // "ips.subs.u.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_subs_u_h; // "ips.subs.u.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_subs_u_w; // "ips.subs.u.w"
			}
			break;
			}
			break;
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+8, "h.qb", 4))
			break;
			return Intrinsic::mips_subuh_qb; // "ips.subuh.qb"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 13: // 10 strings to match.		case 13: // 46 strings to match.
	if (memcmp(NameR.data()+0, "vvm.", 4))		if (memcmp(NameR.data()+0, "ips.", 4))
	break;		break;
	switch (NameR[4]) {		switch (NameR[4]) {
	default: break;		default: break;
	case 'm': // 2 strings to match.		case 'a': // 6 strings to match.
	switch (NameR[5]) {		switch (NameR[5]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'b': // 2 strings to match.
	if (memcmp(NameR.data()+6, "mbar.gl", 7))		if (memcmp(NameR.data()+6, "sq.s.", 5))
	break;
	return Intrinsic::nvvm_membar_gl; // "vvm.membar.gl"
	case 'u': // 1 string to match.
	if (memcmp(NameR.data()+6, "lhi.ull", 7))
	break;
	return Intrinsic::nvvm_mulhi_ull; // "vvm.mulhi.ull"
	}
	break;
	case 's': // 8 strings to match.
	if (memcmp(NameR.data()+5, "qrt.r", 5))
	break;
	switch (NameR[10]) {
	default: break;
	case 'm': // 2 strings to match.
	if (NameR[11] != '.')
	break;		break;
	switch (NameR[12]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'p': // 1 string to match.
	return Intrinsic::nvvm_sqrt_rm_d; // "vvm.sqrt.rm.d"		if (NameR[12] != 'h')
	case 'f': // 1 string to match.		break;
	return Intrinsic::nvvm_sqrt_rm_f; // "vvm.sqrt.rm.f"		return Intrinsic::mips_absq_s_ph; // "ips.absq.s.ph"
			case 'q': // 1 string to match.
			if (NameR[12] != 'b')
			break;
			return Intrinsic::mips_absq_s_qb; // "ips.absq.s.qb"
	}		}
	break;		break;
	case 'n': // 2 strings to match.		case 'd': // 4 strings to match.
	if (NameR[11] != '.')		if (NameR[6] != 'd')
	break;		break;
	switch (NameR[12]) {		switch (NameR[7]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'q': // 2 strings to match.
	return Intrinsic::nvvm_sqrt_rn_d; // "vvm.sqrt.rn.d"		switch (NameR[8]) {
	case 'f': // 1 string to match.		default: break;
	return Intrinsic::nvvm_sqrt_rn_f; // "vvm.sqrt.rn.f"		case '.': // 1 string to match.
	}		if (memcmp(NameR.data()+9, "s.ph", 4))
	break;		break;
	case 'p': // 2 strings to match.		return Intrinsic::mips_addq_s_ph; // "ips.addq.s.ph"
	if (NameR[11] != '.')		case 'h': // 1 string to match.
			if (memcmp(NameR.data()+9, ".r.w", 4))
			break;
			return Intrinsic::mips_addqh_r_w; // "ips.addqh.r.w"
			}
	break;		break;
	switch (NameR[12]) {		case 'u': // 2 strings to match.
	default: break;		if (memcmp(NameR.data()+8, ".s.", 3))
	case 'd': // 1 string to match.		break;
	return Intrinsic::nvvm_sqrt_rp_d; // "vvm.sqrt.rp.d"		switch (NameR[11]) {
	case 'f': // 1 string to match.		default: break;
	return Intrinsic::nvvm_sqrt_rp_f; // "vvm.sqrt.rp.f"		case 'p': // 1 string to match.
	}		if (NameR[12] != 'h')
	break;		break;
	case 'z': // 2 strings to match.		return Intrinsic::mips_addu_s_ph; // "ips.addu.s.ph"
	if (NameR[11] != '.')		case 'q': // 1 string to match.
			if (NameR[12] != 'b')
			break;
			return Intrinsic::mips_addu_s_qb; // "ips.addu.s.qb"
			}
	break;		break;
	switch (NameR[12]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_sqrt_rz_d; // "vvm.sqrt.rz.d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_sqrt_rz_f; // "vvm.sqrt.rz.f"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'c': // 3 strings to match.
	break;		if (memcmp(NameR.data()+5, "mp.", 3))
	case 14: // 18 strings to match.
	if (memcmp(NameR.data()+0, "vvm.", 4))
	break;
	switch (NameR[4]) {
	default: break;
	case 'c': // 1 string to match.
	if (memcmp(NameR.data()+5, "eil.ftz.f", 9))
	break;
	return Intrinsic::nvvm_ceil_ftz_f; // "vvm.ceil.ftz.f"
	case 'd': // 4 strings to match.
	if (memcmp(NameR.data()+5, "2f.r", 4))
	break;		break;
	switch (NameR[9]) {		switch (NameR[8]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'e': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz", 4))		if (memcmp(NameR.data()+9, "q.ph", 4))
	break;
	return Intrinsic::nvvm_d2f_rm_ftz; // "vvm.d2f.rm.ftz"
	case 'n': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz", 4))
	break;
	return Intrinsic::nvvm_d2f_rn_ftz; // "vvm.d2f.rn.ftz"
	case 'p': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz", 4))
	break;
	return Intrinsic::nvvm_d2f_rp_ftz; // "vvm.d2f.rp.ftz"
	case 'z': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz", 4))
	break;		break;
	return Intrinsic::nvvm_d2f_rz_ftz; // "vvm.d2f.rz.ftz"		return Intrinsic::mips_cmp_eq_ph; // "ips.cmp.eq.ph"
			case 'l': // 2 strings to match.
			switch (NameR[9]) {
			default: break;
			case 'e': // 1 string to match.
			if (memcmp(NameR.data()+10, ".ph", 3))
			break;
			return Intrinsic::mips_cmp_le_ph; // "ips.cmp.le.ph"
			case 't': // 1 string to match.
			if (memcmp(NameR.data()+10, ".ph", 3))
			break;
			return Intrinsic::mips_cmp_lt_ph; // "ips.cmp.lt.ph"
			}
			break;
	}		}
	break;		break;
	case 'f': // 8 strings to match.		case 'd': // 14 strings to match.
	switch (NameR[5]) {		if (NameR[5] != 'p')
			break;
			switch (NameR[6]) {
	default: break;		default: break;
	case '2': // 5 strings to match.		case 'a': // 7 strings to match.
	switch (NameR[6]) {		switch (NameR[7]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'd': // 6 strings to match.
	if (memcmp(NameR.data()+7, ".rn.ftz", 7))		if (memcmp(NameR.data()+8, "d.", 2))
	break;
	return Intrinsic::nvvm_f2h_rn_ftz; // "vvm.f2h.rn.ftz"
	case 'i': // 4 strings to match.
	if (memcmp(NameR.data()+7, ".r", 2))
	break;		break;
	switch (NameR[9]) {		switch (NameR[10]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 's': // 3 strings to match.
	if (memcmp(NameR.data()+10, ".ftz", 4))		if (NameR[11] != '.')
	break;
	return Intrinsic::nvvm_f2i_rm_ftz; // "vvm.f2i.rm.ftz"
	case 'n': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz", 4))
	break;
	return Intrinsic::nvvm_f2i_rn_ftz; // "vvm.f2i.rn.ftz"
	case 'p': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz", 4))
	break;		break;
	return Intrinsic::nvvm_f2i_rp_ftz; // "vvm.f2i.rp.ftz"		switch (NameR[12]) {
	case 'z': // 1 string to match.		default: break;
	if (memcmp(NameR.data()+10, ".ftz", 4))		case 'd': // 1 string to match.
			return Intrinsic::mips_dpadd_s_d; // "ips.dpadd.s.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_dpadd_s_h; // "ips.dpadd.s.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_dpadd_s_w; // "ips.dpadd.s.w"
			}
			break;
			case 'u': // 3 strings to match.
			if (NameR[11] != '.')
	break;		break;
	return Intrinsic::nvvm_f2i_rz_ftz; // "vvm.f2i.rz.ftz"		switch (NameR[12]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_dpadd_u_d; // "ips.dpadd.u.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_dpadd_u_h; // "ips.dpadd.u.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_dpadd_u_w; // "ips.dpadd.u.w"
			}
			break;
	}		}
	break;		break;
			case 'x': // 1 string to match.
			if (memcmp(NameR.data()+8, ".w.ph", 5))
			break;
			return Intrinsic::mips_dpax_w_ph; // "ips.dpax.w.ph"
	}		}
	break;		break;
	case 'a': // 1 string to match.		case 's': // 7 strings to match.
	if (memcmp(NameR.data()+6, "bs.ftz.f", 8))		switch (NameR[7]) {
	break;
	return Intrinsic::nvvm_fabs_ftz_f; // "vvm.fabs.ftz.f"
	case 'm': // 2 strings to match.
	switch (NameR[6]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'u': // 6 strings to match.
	if (memcmp(NameR.data()+7, "x.ftz.f", 7))		if (memcmp(NameR.data()+8, "b.", 2))
	break;		break;
	return Intrinsic::nvvm_fmax_ftz_f; // "vvm.fmax.ftz.f"		switch (NameR[10]) {
	case 'i': // 1 string to match.		default: break;
	if (memcmp(NameR.data()+7, "n.ftz.f", 7))		case 's': // 3 strings to match.
			if (NameR[11] != '.')
			break;
			switch (NameR[12]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_dpsub_s_d; // "ips.dpsub.s.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_dpsub_s_h; // "ips.dpsub.s.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_dpsub_s_w; // "ips.dpsub.s.w"
			}
	break;		break;
	return Intrinsic::nvvm_fmin_ftz_f; // "vvm.fmin.ftz.f"		case 'u': // 3 strings to match.
			if (NameR[11] != '.')
			break;
			switch (NameR[12]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_dpsub_u_d; // "ips.dpsub.u.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_dpsub_u_h; // "ips.dpsub.u.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_dpsub_u_w; // "ips.dpsub.u.w"
			}
			break;
			}
			break;
			case 'x': // 1 string to match.
			if (memcmp(NameR.data()+8, ".w.ph", 5))
			break;
			return Intrinsic::mips_dpsx_w_ph; // "ips.dpsx.w.ph"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'm': // 3 strings to match.		case 'e': // 1 string to match.
			if (memcmp(NameR.data()+5, "xtr.rs.w", 8))
			break;
			return Intrinsic::mips_extr_rs_w; // "ips.extr.rs.w"
			case 'f': // 8 strings to match.
	switch (NameR[5]) {		switch (NameR[5]) {
	default: break;		default: break;
	case 'e': // 2 strings to match.		case 'f': // 4 strings to match.
	if (memcmp(NameR.data()+6, "mbar.", 5))		if (memcmp(NameR.data()+6, "int.", 4))
	break;		break;
	switch (NameR[11]) {		switch (NameR[10]) {
	default: break;		default: break;
	case 'c': // 1 string to match.		case 's': // 2 strings to match.
	if (memcmp(NameR.data()+12, "ta", 2))		if (NameR[11] != '.')
	break;		break;
	return Intrinsic::nvvm_membar_cta; // "vvm.membar.cta"		switch (NameR[12]) {
	case 's': // 1 string to match.		default: break;
	if (memcmp(NameR.data()+12, "ys", 2))		case 'd': // 1 string to match.
			return Intrinsic::mips_ffint_s_d; // "ips.ffint.s.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ffint_s_w; // "ips.ffint.s.w"
			}
			break;
			case 'u': // 2 strings to match.
			if (NameR[11] != '.')
	break;		break;
	return Intrinsic::nvvm_membar_sys; // "vvm.membar.sys"		switch (NameR[12]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_ffint_u_d; // "ips.ffint.u.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ffint_u_w; // "ips.ffint.u.w"
			}
			break;
	}		}
	break;		break;
	case 'o': // 1 string to match.		case 't': // 4 strings to match.
	if (memcmp(NameR.data()+6, "ve.float", 8))		if (memcmp(NameR.data()+6, "int.", 4))
	break;		break;
	return Intrinsic::nvvm_move_float; // "vvm.move.float"		switch (NameR[10]) {
	}		default: break;
	break;		case 's': // 2 strings to match.
	case 's': // 2 strings to match.		if (NameR[11] != '.')
	if (memcmp(NameR.data()+5, "aturate.", 8))		break;
			switch (NameR[12]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_ftint_s_d; // "ips.ftint.s.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ftint_s_w; // "ips.ftint.s.w"
			}
			break;
			case 'u': // 2 strings to match.
			if (NameR[11] != '.')
			break;
			switch (NameR[12]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_ftint_u_d; // "ips.ftint.u.d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ftint_u_w; // "ips.ftint.u.w"
			}
			break;
			}
	break;		break;
	switch (NameR[13]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_saturate_d; // "vvm.saturate.d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_saturate_f; // "vvm.saturate.f"
	}		}
	break;		break;
	}		case 'm': // 6 strings to match.
	break;
	case 15: // 15 strings to match.
	if (memcmp(NameR.data()+0, "vvm.", 4))
	break;
	switch (NameR[4]) {
	default: break;
	case 'b': // 3 strings to match.
	switch (NameR[5]) {		switch (NameR[5]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'a': // 2 strings to match.
	if (memcmp(NameR.data()+6, "rrier0.or", 9))		if (memcmp(NameR.data()+6, "ddr.q.", 6))
	break;
	return Intrinsic::nvvm_barrier0_or; // "vvm.barrier0.or"
	case 'i': // 2 strings to match.
	if (memcmp(NameR.data()+6, "tcast.", 6))
	break;		break;
	switch (NameR[12]) {		switch (NameR[12]) {
	default: break;		default: break;
	case 'f': // 1 string to match.		case 'h': // 1 string to match.
	if (memcmp(NameR.data()+13, "2i", 2))		return Intrinsic::mips_maddr_q_h; // "ips.maddr.q.h"
	break;		case 'w': // 1 string to match.
	return Intrinsic::nvvm_bitcast_f2i; // "vvm.bitcast.f2i		return Intrinsic::mips_maddr_q_w; // "ips.maddr.q.w"
	"
	case 'i': // 1 string to match.
	if (memcmp(NameR.data()+13, "2f", 2))
	break;
	return Intrinsic::nvvm_bitcast_i2f; // "vvm.bitcast.i2f
	"
	}		}
	break;		break;
	}		case 's': // 2 strings to match.
			if (memcmp(NameR.data()+6, "ubr.q.", 6))
			break;
			switch (NameR[12]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::mips_msubr_q_h; // "ips.msubr.q.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_msubr_q_w; // "ips.msubr.q.w"
			}
			break;
			case 'u': // 2 strings to match.
			if (memcmp(NameR.data()+6, "lq.", 3))
			break;
			switch (NameR[9]) {
			default: break;
			case 'r': // 1 string to match.
			if (memcmp(NameR.data()+10, "s.w", 3))
			break;
			return Intrinsic::mips_mulq_rs_w; // "ips.mulq.rs.w"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+10, ".ph", 3))
			break;
			return Intrinsic::mips_mulq_s_ph; // "ips.mulq.s.ph"
			}
			break;
			}
	break;		break;
	case 'f': // 9 strings to match.		case 'p': // 1 string to match.
			if (memcmp(NameR.data()+5, "ackrl.ph", 8))
			break;
			return Intrinsic::mips_packrl_ph; // "ips.packrl.ph"
			case 's': // 7 strings to match.
	switch (NameR[5]) {		switch (NameR[5]) {
	default: break;		default: break;
	case '2': // 8 strings to match.		case 'h': // 3 strings to match.
	switch (NameR[6]) {		switch (NameR[6]) {
	default: break;		default: break;
	case 'l': // 4 strings to match.		case 'l': // 1 string to match.
	if (memcmp(NameR.data()+7, "l.r", 3))		if (memcmp(NameR.data()+7, "l.s.ph", 6))
	break;		break;
	switch (NameR[10]) {		return Intrinsic::mips_shll_s_ph; // "ips.shll.s.ph"
			case 'r': // 2 strings to match.
			if (memcmp(NameR.data()+7, "a.r.", 4))
			break;
			switch (NameR[11]) {
	default: break;		default: break;
	case 'm': // 1 string to match.
	if (memcmp(NameR.data()+11, ".ftz", 4))
	break;
	return Intrinsic::nvvm_f2ll_rm_ftz; // "vvm.f2ll.rm.ftz
	"
	case 'n': // 1 string to match.
	if (memcmp(NameR.data()+11, ".ftz", 4))
	break;
	return Intrinsic::nvvm_f2ll_rn_ftz; // "vvm.f2ll.rn.ftz
	"
	case 'p': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(NameR.data()+11, ".ftz", 4))		if (NameR[12] != 'h')
	break;		break;
	return Intrinsic::nvvm_f2ll_rp_ftz; // "vvm.f2ll.rp.ftz		return Intrinsic::mips_shra_r_ph; // "ips.shra.r.ph"
	"		case 'q': // 1 string to match.
	case 'z': // 1 string to match.		if (NameR[12] != 'b')
	if (memcmp(NameR.data()+11, ".ftz", 4))
	break;		break;
	return Intrinsic::nvvm_f2ll_rz_ftz; // "vvm.f2ll.rz.ftz "		return Intrinsic::mips_shra_r_qb; // "ips.shra.r.qb"
	}		}
	break;		break;
	case 'u': // 4 strings to match.		}
	if (memcmp(NameR.data()+7, "i.r", 3))		break;
	break;		case 'u': // 4 strings to match.
	switch (NameR[10]) {		if (NameR[6] != 'b')
			break;
			switch (NameR[7]) {
			default: break;
			case 'q': // 2 strings to match.
			switch (NameR[8]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case '.': // 1 string to match.
	if (memcmp(NameR.data()+11, ".ftz", 4))		if (memcmp(NameR.data()+9, "s.ph", 4))
	break;		break;
	return Intrinsic::nvvm_f2ui_rm_ftz; // "vvm.f2ui.rm.ftz		return Intrinsic::mips_subq_s_ph; // "ips.subq.s.ph"
	"		case 'h': // 1 string to match.
	case 'n': // 1 string to match.		if (memcmp(NameR.data()+9, ".r.w", 4))
	if (memcmp(NameR.data()+11, ".ftz", 4))
	break;		break;
	return Intrinsic::nvvm_f2ui_rn_ftz; // "vvm.f2ui.rn.ftz		return Intrinsic::mips_subqh_r_w; // "ips.subqh.r.w"
	"		}
			break;
			case 'u': // 2 strings to match.
			if (memcmp(NameR.data()+8, ".s.", 3))
			break;
			switch (NameR[11]) {
			default: break;
	case 'p': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(NameR.data()+11, ".ftz", 4))		if (NameR[12] != 'h')
	break;		break;
	return Intrinsic::nvvm_f2ui_rp_ftz; // "vvm.f2ui.rp.ftz		return Intrinsic::mips_subu_s_ph; // "ips.subu.s.ph"
	"		case 'q': // 1 string to match.
	case 'z': // 1 string to match.		if (NameR[12] != 'b')
	if (memcmp(NameR.data()+11, ".ftz", 4))
	break;		break;
	return Intrinsic::nvvm_f2ui_rz_ftz; // "vvm.f2ui.rz.ftz "		return Intrinsic::mips_subu_s_qb; // "ips.subu.s.qb"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'l': // 1 string to match.
	if (memcmp(NameR.data()+6, "oor.ftz.f", 9))
	break;
	return Intrinsic::nvvm_floor_ftz_f; // "vvm.floor.ftz.f"
	}		}
	break;		break;
	case 'm': // 1 string to match.
	if (memcmp(NameR.data()+5, "ove.double", 10))
	break;
	return Intrinsic::nvvm_move_double; // "vvm.move.double"
	case 'r': // 1 string to match.
	if (memcmp(NameR.data()+5, "ound.ftz.f", 10))
	break;
	return Intrinsic::nvvm_round_ftz_f; // "vvm.round.ftz.f"
	case 't': // 1 string to match.
	if (memcmp(NameR.data()+5, "runc.ftz.f", 10))
	break;
	return Intrinsic::nvvm_trunc_ftz_f; // "vvm.trunc.ftz.f"
	}		}
	break;		break;
	case 16: // 34 strings to match.		case 14: // 26 strings to match.
	if (memcmp(NameR.data()+0, "vvm.", 4))		if (memcmp(NameR.data()+0, "ips.", 4))
	break;		break;
	switch (NameR[4]) {		switch (NameR[4]) {
	default: break;		default: break;
	case 'a': // 4 strings to match.		case 'a': // 2 strings to match.
	if (memcmp(NameR.data()+5, "dd.r", 4))		if (memcmp(NameR.data()+5, "dd", 2))
	break;		break;
	switch (NameR[9]) {		switch (NameR[7]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'q': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz.f", 6))		if (memcmp(NameR.data()+8, "h.r.ph", 6))
	break;
	return Intrinsic::nvvm_add_rm_ftz_f; // "vvm.add.rm.ftz.f"
	case 'n': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz.f", 6))
	break;
	return Intrinsic::nvvm_add_rn_ftz_f; // "vvm.add.rn.ftz.f"
	case 'p': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz.f", 6))
	break;		break;
	return Intrinsic::nvvm_add_rp_ftz_f; // "vvm.add.rp.ftz.f"		return Intrinsic::mips_addqh_r_ph; // "ips.addqh.r.ph"
	case 'z': // 1 string to match.		case 'u': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz.f", 6))		if (memcmp(NameR.data()+8, "h.r.qb", 6))
	break;		break;
	return Intrinsic::nvvm_add_rz_ftz_f; // "vvm.add.rz.ftz.f"		return Intrinsic::mips_adduh_r_qb; // "ips.adduh.r.qb"
	}		}
	break;		break;
	case 'b': // 3 strings to match.		case 'c': // 3 strings to match.
	switch (NameR[5]) {		if (memcmp(NameR.data()+5, "mpu.", 4))
			break;
			switch (NameR[9]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'e': // 1 string to match.
	if (memcmp(NameR.data()+6, "rrier0.and", 10))		if (memcmp(NameR.data()+10, "q.qb", 4))
	break;
	return Intrinsic::nvvm_barrier0_and; // "vvm.barrier0.and"
	case 'i': // 2 strings to match.
	if (memcmp(NameR.data()+6, "tcast.", 6))
	break;		break;
	switch (NameR[12]) {		return Intrinsic::mips_cmpu_eq_qb; // "ips.cmpu.eq.qb"
			case 'l': // 2 strings to match.
			switch (NameR[10]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'e': // 1 string to match.
	if (memcmp(NameR.data()+13, "2ll", 3))		if (memcmp(NameR.data()+11, ".qb", 3))
	break;		break;
	return Intrinsic::nvvm_bitcast_d2ll; // "vvm.bitcast.d2l		return Intrinsic::mips_cmpu_le_qb; // "ips.cmpu.le.qb"
	l"		case 't': // 1 string to match.
	case 'l': // 1 string to match.		if (memcmp(NameR.data()+11, ".qb", 3))
	if (memcmp(NameR.data()+13, "l2d", 3))
	break;		break;
	return Intrinsic::nvvm_bitcast_ll2d; // "vvm.bitcast.ll2 d"		return Intrinsic::mips_cmpu_lt_qb; // "ips.cmpu.lt.qb"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'c': // 1 string to match.		case 'd': // 4 strings to match.
	if (memcmp(NameR.data()+5, "os.approx.f", 11))		if (NameR[5] != 'p')
	break;
	return Intrinsic::nvvm_cos_approx_f; // "vvm.cos.approx.f"
	case 'd': // 5 strings to match.
	if (memcmp(NameR.data()+5, "iv.", 3))
	break;		break;
	switch (NameR[8]) {		switch (NameR[6]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'a': // 2 strings to match.
	if (memcmp(NameR.data()+9, "pprox.f", 7))		if (memcmp(NameR.data()+7, "u.h.qb", 6))
	break;		break;
	return Intrinsic::nvvm_div_approx_f; // "vvm.div.approx.f"		switch (NameR[13]) {
	case 'r': // 4 strings to match.
	switch (NameR[9]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'l': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz.f", 6))		return Intrinsic::mips_dpau_h_qbl; // "ips.dpau.h.qbl"
	break;		case 'r': // 1 string to match.
	return Intrinsic::nvvm_div_rm_ftz_f; // "vvm.div.rm.ftz.		return Intrinsic::mips_dpau_h_qbr; // "ips.dpau.h.qbr"
	f"
	case 'n': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz.f", 6))
	break;
	return Intrinsic::nvvm_div_rn_ftz_f; // "vvm.div.rn.ftz.
	f"
	case 'p': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz.f", 6))
	break;
	return Intrinsic::nvvm_div_rp_ftz_f; // "vvm.div.rp.ftz.
	f"
	case 'z': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz.f", 6))
	break;
	return Intrinsic::nvvm_div_rz_ftz_f; // "vvm.div.rz.ftz.
	f"
	}		}
	break;		break;
	}		case 's': // 2 strings to match.
	break;		if (memcmp(NameR.data()+7, "u.h.qb", 6))
	case 'e': // 2 strings to match.		break;
	if (memcmp(NameR.data()+5, "x2.approx.", 10))		switch (NameR[13]) {
			default: break;
			case 'l': // 1 string to match.
			return Intrinsic::mips_dpsu_h_qbl; // "ips.dpsu.h.qbl"
			case 'r': // 1 string to match.
			return Intrinsic::mips_dpsu_h_qbr; // "ips.dpsu.h.qbr"
			}
	break;		break;
	switch (NameR[15]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_ex2_approx_d; // "vvm.ex2.approx.d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_ex2_approx_f; // "vvm.ex2.approx.f"
	}		}
	break;		break;
	case 'f': // 8 strings to match.		case 'f': // 4 strings to match.
	switch (NameR[5]) {		if (memcmp(NameR.data()+5, "trunc.", 6))
			break;
			switch (NameR[11]) {
	default: break;		default: break;
	case '2': // 4 strings to match.		case 's': // 2 strings to match.
	if (memcmp(NameR.data()+6, "ull.r", 5))		if (NameR[12] != '.')
	break;		break;
	switch (NameR[11]) {		switch (NameR[13]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+12, ".ftz", 4))		return Intrinsic::mips_ftrunc_s_d; // "ips.ftrunc.s.d"
	break;		case 'w': // 1 string to match.
	return Intrinsic::nvvm_f2ull_rm_ftz; // "vvm.f2ull.rm.ft		return Intrinsic::mips_ftrunc_s_w; // "ips.ftrunc.s.w"
	z"
	case 'n': // 1 string to match.
	if (memcmp(NameR.data()+12, ".ftz", 4))
	break;
	return Intrinsic::nvvm_f2ull_rn_ftz; // "vvm.f2ull.rn.ft
	z"
	case 'p': // 1 string to match.
	if (memcmp(NameR.data()+12, ".ftz", 4))
	break;
	return Intrinsic::nvvm_f2ull_rp_ftz; // "vvm.f2ull.rp.ft
	z"
	case 'z': // 1 string to match.
	if (memcmp(NameR.data()+12, ".ftz", 4))
	break;
	return Intrinsic::nvvm_f2ull_rz_ftz; // "vvm.f2ull.rz.ft
	z"
	}		}
	break;		break;
	case 'm': // 4 strings to match.		case 'u': // 2 strings to match.
	if (memcmp(NameR.data()+6, "a.r", 3))		if (NameR[12] != '.')
	break;		break;
	switch (NameR[9]) {		switch (NameR[13]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz.f", 6))		return Intrinsic::mips_ftrunc_u_d; // "ips.ftrunc.u.d"
	break;		case 'w': // 1 string to match.
	return Intrinsic::nvvm_fma_rm_ftz_f; // "vvm.fma.rm.ftz.		return Intrinsic::mips_ftrunc_u_w; // "ips.ftrunc.u.w"
	f"
	case 'n': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz.f", 6))
	break;
	return Intrinsic::nvvm_fma_rn_ftz_f; // "vvm.fma.rn.ftz.
	f"
	case 'p': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz.f", 6))
	break;
	return Intrinsic::nvvm_fma_rp_ftz_f; // "vvm.fma.rp.ftz.
	f"
	case 'z': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz.f", 6))
	break;
	return Intrinsic::nvvm_fma_rz_ftz_f; // "vvm.fma.rz.ftz.
	f"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'm': // 2 strings to match.
	if (memcmp(NameR.data()+5, "g2.approx.", 10))		if (memcmp(NameR.data()+5, "ul", 2))
	break;
	switch (NameR[15]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_lg2_approx_d; // "vvm.lg2.approx.d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_lg2_approx_f; // "vvm.lg2.approx.f"
	}
	break;
	case 'm': // 4 strings to match.
	if (memcmp(NameR.data()+5, "ul.r", 4))
	break;		break;
	switch (NameR[9]) {		switch (NameR[7]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'q': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz.f", 6))		if (memcmp(NameR.data()+8, ".rs.ph", 6))
	break;
	return Intrinsic::nvvm_mul_rm_ftz_f; // "vvm.mul.rm.ftz.f"
	case 'n': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz.f", 6))
	break;
	return Intrinsic::nvvm_mul_rn_ftz_f; // "vvm.mul.rn.ftz.f"
	case 'p': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz.f", 6))
	break;		break;
	return Intrinsic::nvvm_mul_rp_ftz_f; // "vvm.mul.rp.ftz.f"		return Intrinsic::mips_mulq_rs_ph; // "ips.mulq.rs.ph"
	case 'z': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz.f", 6))		if (memcmp(NameR.data()+8, "a.w.ph", 6))
	break;		break;
	return Intrinsic::nvvm_mul_rz_ftz_f; // "vvm.mul.rz.ftz.f"		return Intrinsic::mips_mulsa_w_ph; // "ips.mulsa.w.ph"
	}		}
	break;		break;
	case 'r': // 4 strings to match.		case 'r': // 1 string to match.
	if (memcmp(NameR.data()+5, "cp.r", 4))		if (memcmp(NameR.data()+5, "addu.w.qb", 9))
	break;		break;
	switch (NameR[9]) {		return Intrinsic::mips_raddu_w_qb; // "ips.raddu.w.qb"
			case 's': // 10 strings to match.
			if (memcmp(NameR.data()+5, "ub", 2))
			break;
			switch (NameR[7]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'q': // 1 string to match.
	if (memcmp(NameR.data()+10, ".ftz.f", 6))		if (memcmp(NameR.data()+8, "h.r.ph", 6))
	break;		break;
	return Intrinsic::nvvm_rcp_rm_ftz_f; // "vvm.rcp.rm.ftz.f"		return Intrinsic::mips_subqh_r_ph; // "ips.subqh.r.ph"
	case 'n': // 1 string to match.		case 's': // 8 strings to match.
	if (memcmp(NameR.data()+10, ".ftz.f", 6))		if (NameR[8] != 'u')
	break;		break;
	return Intrinsic::nvvm_rcp_rn_ftz_f; // "vvm.rcp.rn.ftz.f"		switch (NameR[9]) {
	case 'p': // 1 string to match.		default: break;
	if (memcmp(NameR.data()+10, ".ftz.f", 6))		case 's': // 4 strings to match.
			if (memcmp(NameR.data()+10, ".u.", 3))
			break;
			switch (NameR[13]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_subsus_u_b; // "ips.subsus.u.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_subsus_u_d; // "ips.subsus.u.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_subsus_u_h; // "ips.subsus.u.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_subsus_u_w; // "ips.subsus.u.w"
			}
	break;		break;
	return Intrinsic::nvvm_rcp_rp_ftz_f; // "vvm.rcp.rp.ftz.f"		case 'u': // 4 strings to match.
	case 'z': // 1 string to match.		if (memcmp(NameR.data()+10, ".s.", 3))
	if (memcmp(NameR.data()+10, ".ftz.f", 6))		break;
			switch (NameR[13]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_subsuu_s_b; // "ips.subsuu.s.b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_subsuu_s_d; // "ips.subsuu.s.d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_subsuu_s_h; // "ips.subsuu.s.h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_subsuu_s_w; // "ips.subsuu.s.w"
			}
	break;		break;
	return Intrinsic::nvvm_rcp_rz_ftz_f; // "vvm.rcp.rz.ftz.f"		}
			break;
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+8, "h.r.qb", 6))
			break;
			return Intrinsic::mips_subuh_r_qb; // "ips.subuh.r.qb"
	}		}
	break;		break;
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+5, "in.approx.f", 11))
	break;
	return Intrinsic::nvvm_sin_approx_f; // "vvm.sin.approx.f"
	}		}
	break;		break;
	case 17: // 6 strings to match.		case 15: // 11 strings to match.
	if (memcmp(NameR.data()+0, "vvm.", 4))		if (memcmp(NameR.data()+0, "ips.", 4))
	break;		break;
	switch (NameR[4]) {		switch (NameR[4]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'c': // 3 strings to match.
	if (memcmp(NameR.data()+5, "arrier0.popc", 12))		if (memcmp(NameR.data()+5, "mpgu.", 5))
	break;		break;
	return Intrinsic::nvvm_barrier0_popc; // "vvm.barrier0.popc"		switch (NameR[10]) {
	case 's': // 5 strings to match.		default: break;
	if (memcmp(NameR.data()+5, "qrt.", 4))		case 'e': // 1 string to match.
			if (memcmp(NameR.data()+11, "q.qb", 4))
			break;
			return Intrinsic::mips_cmpgu_eq_qb; // "ips.cmpgu.eq.qb"
			case 'l': // 2 strings to match.
			switch (NameR[11]) {
			default: break;
			case 'e': // 1 string to match.
			if (memcmp(NameR.data()+12, ".qb", 3))
			break;
			return Intrinsic::mips_cmpgu_le_qb; // "ips.cmpgu.le.qb
			"
			case 't': // 1 string to match.
			if (memcmp(NameR.data()+12, ".qb", 3))
			break;
			return Intrinsic::mips_cmpgu_lt_qb; // "ips.cmpgu.lt.qb
			"
			}
	break;		break;
	switch (NameR[9]) {		}
			break;
			case 'd': // 4 strings to match.
			if (NameR[5] != 'p')
			break;
			switch (NameR[6]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'a': // 2 strings to match.
	if (memcmp(NameR.data()+10, "pprox.f", 7))		if (memcmp(NameR.data()+7, "q.s", 3))
	break;		break;
	return Intrinsic::nvvm_sqrt_approx_f; // "vvm.sqrt.approx
	.f"
	case 'r': // 4 strings to match.
	switch (NameR[10]) {		switch (NameR[10]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case '.': // 1 string to match.
	if (memcmp(NameR.data()+11, ".ftz.f", 6))		if (memcmp(NameR.data()+11, "w.ph", 4))
	break;		break;
	return Intrinsic::nvvm_sqrt_rm_ftz_f; // "vvm.sqrt.rm.ftz		return Intrinsic::mips_dpaq_s_w_ph; // "ips.dpaq.s.w.ph
	.f"		"
	case 'n': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(NameR.data()+11, ".ftz.f", 6))		if (memcmp(NameR.data()+11, ".l.w", 4))
	break;		break;
	return Intrinsic::nvvm_sqrt_rn_ftz_f; // "vvm.sqrt.rn.ftz		return Intrinsic::mips_dpaq_sa_l_w; // "ips.dpaq.sa.l.w
	.f"		"
	case 'p': // 1 string to match.		}
	if (memcmp(NameR.data()+11, ".ftz.f", 6))		break;
			case 's': // 2 strings to match.
			if (memcmp(NameR.data()+7, "q.s", 3))
			break;
			switch (NameR[10]) {
			default: break;
			case '.': // 1 string to match.
			if (memcmp(NameR.data()+11, "w.ph", 4))
	break;		break;
	return Intrinsic::nvvm_sqrt_rp_ftz_f; // "vvm.sqrt.rp.ftz		return Intrinsic::mips_dpsq_s_w_ph; // "ips.dpsq.s.w.ph
	.f"		"
	case 'z': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(NameR.data()+11, ".ftz.f", 6))		if (memcmp(NameR.data()+11, ".l.w", 4))
	break;		break;
	return Intrinsic::nvvm_sqrt_rz_ftz_f; // "vvm.sqrt.rz.ftz .f"		return Intrinsic::mips_dpsq_sa_l_w; // "ips.dpsq.sa.l.w "
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'm': // 2 strings to match.
	break;		if (memcmp(NameR.data()+5, "aq.s.w.ph", 9))
	case 18: // 3 strings to match.
	if (memcmp(NameR.data()+0, "vvm.", 4))
	break;
	switch (NameR[4]) {
	default: break;
	case 'r': // 2 strings to match.
	if (memcmp(NameR.data()+5, "sqrt.approx.", 12))
	break;		break;
	switch (NameR[17]) {		switch (NameR[14]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'l': // 1 string to match.
	return Intrinsic::nvvm_rsqrt_approx_d; // "vvm.rsqrt.appro		return Intrinsic::mips_maq_s_w_phl; // "ips.maq.s.w.phl"
	x.d"		case 'r': // 1 string to match.
	case 'f': // 1 string to match.		return Intrinsic::mips_maq_s_w_phr; // "ips.maq.s.w.phr"
	return Intrinsic::nvvm_rsqrt_approx_f; // "vvm.rsqrt.appro
	x.f"
	}		}
	break;		break;
	case 's': // 1 string to match.		case 'p': // 2 strings to match.
	if (memcmp(NameR.data()+5, "aturate.ftz.f", 13))		if (memcmp(NameR.data()+5, "recr", 4))
	break;		break;
	return Intrinsic::nvvm_saturate_ftz_f; // "vvm.saturate.ftz.f"		switch (NameR[9]) {
			default: break;
			case '.': // 1 string to match.
			if (memcmp(NameR.data()+10, "qb.ph", 5))
			break;
			return Intrinsic::mips_precr_qb_ph; // "ips.precr.qb.ph"
			case 'q': // 1 string to match.
			if (memcmp(NameR.data()+10, ".ph.w", 5))
			break;
			return Intrinsic::mips_precrq_ph_w; // "ips.precrq.ph.w"
			}
			break;
	}		}
	break;		break;
	case 20: // 6 strings to match.		case 16: // 10 strings to match.
	if (memcmp(NameR.data()+0, "vvm.", 4))		if (memcmp(NameR.data()+0, "ips.", 4))
	break;		break;
	switch (NameR[4]) {		switch (NameR[4]) {
	default: break;		default: break;
	case 'c': // 1 string to match.		case 'c': // 3 strings to match.
	if (memcmp(NameR.data()+5, "os.approx.ftz.f", 15))		if (memcmp(NameR.data()+5, "mpgdu.", 6))
	break;
	return Intrinsic::nvvm_cos_approx_ftz_f; // "vvm.cos.approx.
	ftz.f"
	case 'd': // 1 string to match.
	if (memcmp(NameR.data()+5, "iv.approx.ftz.f", 15))
	break;
	return Intrinsic::nvvm_div_approx_ftz_f; // "vvm.div.approx.
	ftz.f"
	case 'e': // 1 string to match.
	if (memcmp(NameR.data()+5, "x2.approx.ftz.f", 15))
	break;
	return Intrinsic::nvvm_ex2_approx_ftz_f; // "vvm.ex2.approx.
	ftz.f"
	case 'l': // 1 string to match.
	if (memcmp(NameR.data()+5, "g2.approx.ftz.f", 15))
	break;
	return Intrinsic::nvvm_lg2_approx_ftz_f; // "vvm.lg2.approx.
	ftz.f"
	case 'r': // 1 string to match.
	if (memcmp(NameR.data()+5, "cp.approx.ftz.d", 15))
	break;		break;
	return Intrinsic::nvvm_rcp_approx_ftz_d; // "vvm.rcp.approx.		switch (NameR[11]) {
	ftz.d"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+5, "in.approx.ftz.f", 15))
	break;
	return Intrinsic::nvvm_sin_approx_ftz_f; // "vvm.sin.approx.
	ftz.f"
	}
	break;
	case 21: // 1 string to match.
	if (memcmp(NameR.data()+0, "vvm.sqrt.approx.ftz.f", 21))
	break;
	return Intrinsic::nvvm_sqrt_approx_ftz_f; // "vvm.sqrt.approx
	.ftz.f"
	case 22: // 1 string to match.
	if (memcmp(NameR.data()+0, "vvm.rsqrt.approx.ftz.f", 22))
	break;
	return Intrinsic::nvvm_rsqrt_approx_ftz_f; // "vvm.rsqrt.appro
	x.ftz.f"
	case 23: // 3 strings to match.
	if (memcmp(NameR.data()+0, "vvm.read.ptx.sreg.tid.", 22))
	break;
	switch (NameR[22]) {
	default: break;
	case 'x': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_tid_x; // "vvm.read.ptx.sr
	eg.tid.x"
	case 'y': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_tid_y; // "vvm.read.ptx.sr
	eg.tid.y"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_tid_z; // "vvm.read.ptx.sr
	eg.tid.z"
	}
	break;
	case 24: // 3 strings to match.
	if (memcmp(NameR.data()+0, "vvm.read.ptx.sreg.ntid.", 23))
	break;
	switch (NameR[23]) {
	default: break;
	case 'x': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_ntid_x; // "vvm.read.ptx.sr
	eg.ntid.x"
	case 'y': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_ntid_y; // "vvm.read.ptx.sr
	eg.ntid.y"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_ntid_z; // "vvm.read.ptx.sr
	eg.ntid.z"
	}
	break;
	case 25: // 3 strings to match.
	if (memcmp(NameR.data()+0, "vvm.read.ptx.sreg.ctaid.", 24))
	break;
	switch (NameR[24]) {
	default: break;
	case 'x': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_ctaid_x; // "vvm.read.ptx.sr
	eg.ctaid.x"
	case 'y': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_ctaid_y; // "vvm.read.ptx.sr
	eg.ctaid.y"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_ctaid_z; // "vvm.read.ptx.sr
	eg.ctaid.z"
	}
	break;
	case 26: // 4 strings to match.
	if (memcmp(NameR.data()+0, "vvm.read.ptx.sreg.", 18))
	break;
	switch (NameR[18]) {
	default: break;
	case 'n': // 3 strings to match.
	if (memcmp(NameR.data()+19, "ctaid.", 6))
	break;
	switch (NameR[25]) {
	default: break;
	case 'x': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_nctaid_x; // "vvm.rea
	d.ptx.sreg.nctaid.x"
	case 'y': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_nctaid_y; // "vvm.rea
	d.ptx.sreg.nctaid.y"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_nctaid_z; // "vvm.rea
	d.ptx.sreg.nctaid.z"
	}
	break;
	case 'w': // 1 string to match.
	if (memcmp(NameR.data()+19, "arpsize", 7))
	break;
	return Intrinsic::nvvm_read_ptx_sreg_warpsize; // "vvm.read.ptx.sr
	eg.warpsize"
	}
	break;
	}
	break; // end of 'n' case.
	case 'o':
	if (NameR.startswith("bjectsize.")) return Intrinsic::objectsize;
	break; // end of 'o' case.
	case 'p':
	if (NameR.startswith("ow.")) return Intrinsic::pow;
	if (NameR.startswith("owi.")) return Intrinsic::powi;
	if (NameR.startswith("tr.annotation.")) return Intrinsic::ptr_annotatio
	n;
	switch (NameR.size()) {
	default: break;
	case 7: // 8 strings to match.
	switch (NameR[0]) {
	default: break;
	case 'c': // 1 string to match.
	if (memcmp(NameR.data()+1, "marker", 6))
	break;
	return Intrinsic::pcmarker; // "cmarker"
	case 'p': // 6 strings to match.
	if (memcmp(NameR.data()+1, "c.", 2))
	break;
	switch (NameR[3]) {
	default: break;		default: break;
	case 'd': // 5 strings to match.		case 'e': // 1 string to match.
	if (memcmp(NameR.data()+4, "cb", 2))		if (memcmp(NameR.data()+12, "q.qb", 4))
	break;		break;
	switch (NameR[6]) {		return Intrinsic::mips_cmpgdu_eq_qb; // "ips.cmpgdu.eq.qb"
			case 'l': // 2 strings to match.
			switch (NameR[12]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'e': // 1 string to match.
	return Intrinsic::ppc_dcba; // "pc.dcba"		if (memcmp(NameR.data()+13, ".qb", 3))
	case 'f': // 1 string to match.		break;
	return Intrinsic::ppc_dcbf; // "pc.dcbf"		return Intrinsic::mips_cmpgdu_le_qb; // "ips.cmpgdu.le.q
	case 'i': // 1 string to match.		b"
	return Intrinsic::ppc_dcbi; // "pc.dcbi"
	case 't': // 1 string to match.		case 't': // 1 string to match.
	return Intrinsic::ppc_dcbt; // "pc.dcbt"		if (memcmp(NameR.data()+13, ".qb", 3))
	case 'z': // 1 string to match.		break;
	return Intrinsic::ppc_dcbz; // "pc.dcbz"		return Intrinsic::mips_cmpgdu_lt_qb; // "ips.cmpgdu.lt.q
			b"
	}		}
	break;		break;
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+4, "ync", 3))
	break;
	return Intrinsic::ppc_sync; // "pc.sync"
	}		}
	break;		break;
	case 'r': // 1 string to match.		case 'd': // 2 strings to match.
	if (memcmp(NameR.data()+1, "efetch", 6))		if (NameR[5] != 'p')
	break;		break;
	return Intrinsic::prefetch; // "refetch"		switch (NameR[6]) {
	}		default: break;
	break;		case 'a': // 1 string to match.
	case 8: // 2 strings to match.		if (memcmp(NameR.data()+7, "qx.s.w.ph", 9))
	if (memcmp(NameR.data()+0, "pc.dcb", 6))		break;
			return Intrinsic::mips_dpaqx_s_w_ph; // "ips.dpaqx.s.w.ph"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+7, "qx.s.w.ph", 9))
			break;
			return Intrinsic::mips_dpsqx_s_w_ph; // "ips.dpsqx.s.w.ph"
			}
	break;		break;
	switch (NameR[6]) {		case 'm': // 2 strings to match.
	default: break;		if (memcmp(NameR.data()+5, "aq.sa.w.ph", 10))
	case 's': // 1 string to match.
	if (NameR[7] != 't')
	break;
	return Intrinsic::ppc_dcbst; // "pc.dcbst"
	case 'z': // 1 string to match.
	if (NameR[7] != 'l')
	break;		break;
	return Intrinsic::ppc_dcbzl; // "pc.dcbzl"		switch (NameR[15]) {
	}		default: break;
	break;		case 'l': // 1 string to match.
	case 9: // 1 string to match.		return Intrinsic::mips_maq_sa_w_phl; // "ips.maq.sa.w.phl"
	if (memcmp(NameR.data()+0, "pc.dcbtst", 9))		case 'r': // 1 string to match.
	break;		return Intrinsic::mips_maq_sa_w_phr; // "ips.maq.sa.w.phr"
	return Intrinsic::ppc_dcbtst; // "pc.dcbtst"		}
	case 11: // 5 strings to match.
	if (memcmp(NameR.data()+0, "tx.", 3))
	break;		break;
	switch (NameR[3]) {		case 'p': // 3 strings to match.
	default: break;		if (memcmp(NameR.data()+5, "rec", 3))
	case 'b': // 1 string to match.
	if (memcmp(NameR.data()+4, "ar.sync", 7))
	break;
	return Intrinsic::ptx_bar_sync; // "tx.bar.sync"
	case 'r': // 4 strings to match.
	if (memcmp(NameR.data()+4, "ead.pm", 6))
	break;		break;
	switch (NameR[10]) {		switch (NameR[8]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'e': // 2 strings to match.
	return Intrinsic::ptx_read_pm0; // "tx.read.pm0"		if (memcmp(NameR.data()+9, "q.w.ph", 6))
	case '1': // 1 string to match.		break;
	return Intrinsic::ptx_read_pm1; // "tx.read.pm1"		switch (NameR[15]) {
	case '2': // 1 string to match.		default: break;
	return Intrinsic::ptx_read_pm2; // "tx.read.pm2"		case 'l': // 1 string to match.
	case '3': // 1 string to match.		return Intrinsic::mips_preceq_w_phl; // "ips.preceq.w.ph
	return Intrinsic::ptx_read_pm3; // "tx.read.pm3"		l"
			case 'r': // 1 string to match.
			return Intrinsic::mips_preceq_w_phr; // "ips.preceq.w.ph
			r"
			}
			break;
			case 'r': // 1 string to match.
			if (memcmp(NameR.data()+9, "q.qb.ph", 7))
			break;
			return Intrinsic::mips_precrq_qb_ph; // "ips.precrq.qb.ph"
	}		}
	break;		break;
	}		}
	break;		break;
	case 12: // 1 string to match.		case 17: // 7 strings to match.
	if (memcmp(NameR.data()+0, "tx.read.smid", 12))		if (memcmp(NameR.data()+0, "ips.", 4))
	break;
	return Intrinsic::ptx_read_smid; // "tx.read.smid"
	case 13: // 6 strings to match.
	if (memcmp(NameR.data()+0, "tx.read.", 8))
	break;		break;
	switch (NameR[8]) {		switch (NameR[4]) {
	default: break;		default: break;
	case 'c': // 1 string to match.		case 'd': // 2 strings to match.
	if (memcmp(NameR.data()+9, "lock", 4))		if (NameR[5] != 'p')
	break;
	return Intrinsic::ptx_read_clock; // "tx.read.clock"
	case 'n': // 1 string to match.
	if (memcmp(NameR.data()+9, "smid", 4))
	break;
	return Intrinsic::ptx_read_nsmid; // "tx.read.nsmid"
	case 't': // 4 strings to match.
	if (memcmp(NameR.data()+9, "id.", 3))
	break;		break;
	switch (NameR[12]) {		switch (NameR[6]) {
	default: break;		default: break;
	case 'w': // 1 string to match.		case 'a': // 1 string to match.
	return Intrinsic::ptx_read_tid_w; // "tx.read.tid.w"		if (memcmp(NameR.data()+7, "qx.sa.w.ph", 10))
	case 'x': // 1 string to match.		break;
	return Intrinsic::ptx_read_tid_x; // "tx.read.tid.x"		return Intrinsic::mips_dpaqx_sa_w_ph; // "ips.dpaqx.sa.w.
	case 'y': // 1 string to match.		ph"
	return Intrinsic::ptx_read_tid_y; // "tx.read.tid.y"		case 's': // 1 string to match.
	case 'z': // 1 string to match.		if (memcmp(NameR.data()+7, "qx.sa.w.ph", 10))
	return Intrinsic::ptx_read_tid_z; // "tx.read.tid.z"		break;
			return Intrinsic::mips_dpsqx_sa_w_ph; // "ips.dpsqx.sa.w.
			ph"
	}		}
	break;		break;
	}		case 'm': // 3 strings to match.
	break;		if (memcmp(NameR.data()+5, "ul", 2))
	case 14: // 12 strings to match.
	switch (NameR[0]) {
	default: break;
	case 'p': // 5 strings to match.
	if (memcmp(NameR.data()+1, "c.altivec.", 10))
	break;		break;
	switch (NameR[11]) {		switch (NameR[7]) {
	default: break;		default: break;
	case 'd': // 2 strings to match.		case 'e': // 2 strings to match.
	if (NameR[12] != 's')		if (memcmp(NameR.data()+8, "q.s.w.ph", 8))
	break;
	switch (NameR[13]) {
	default: break;
	case 's': // 1 string to match.
	return Intrinsic::ppc_altivec_dss; // "pc.altivec.dss"
	case 't': // 1 string to match.
	return Intrinsic::ppc_altivec_dst; // "pc.altivec.dst"
	}
	break;
	case 'l': // 1 string to match.
	if (memcmp(NameR.data()+12, "vx", 2))
	break;
	return Intrinsic::ppc_altivec_lvx; // "pc.altivec.lvx"
	case 'v': // 2 strings to match.
	if (NameR[12] != 's')
	break;		break;
	switch (NameR[13]) {		switch (NameR[16]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'l': // 1 string to match.
	return Intrinsic::ppc_altivec_vsl; // "pc.altivec.vsl"		return Intrinsic::mips_muleq_s_w_phl; // "ips.muleq.s.w.p hl"
	case 'r': // 1 string to match.		case 'r': // 1 string to match.
	return Intrinsic::ppc_altivec_vsr; // "pc.altivec.vsr"		return Intrinsic::mips_muleq_s_w_phr; // "ips.muleq.s.w.p hr"
	}		}
	break;		break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+8, "aq.s.w.ph", 9))
			break;
			return Intrinsic::mips_mulsaq_s_w_ph; // "ips.mulsaq.s.w.
			ph"
	}		}
	break;		break;
	case 't': // 7 strings to match.		case 'p': // 2 strings to match.
	if (memcmp(NameR.data()+1, "x.read.", 7))		if (memcmp(NameR.data()+5, "receu.ph.qb", 11))
	break;		break;
	switch (NameR[8]) {		switch (NameR[16]) {
	default: break;		default: break;
	case 'g': // 1 string to match.
	if (memcmp(NameR.data()+9, "ridid", 5))
	break;
	return Intrinsic::ptx_read_gridid; // "tx.read.gridid"
	case 'l': // 1 string to match.		case 'l': // 1 string to match.
	if (memcmp(NameR.data()+9, "aneid", 5))		return Intrinsic::mips_preceu_ph_qbl; // "ips.preceu.ph.q
	break;		bl"
	return Intrinsic::ptx_read_laneid; // "tx.read.laneid"		case 'r': // 1 string to match.
	case 'n': // 4 strings to match.		return Intrinsic::mips_preceu_ph_qbr; // "ips.preceu.ph.q
	if (memcmp(NameR.data()+9, "tid.", 4))		br"
	break;
	switch (NameR[13]) {
	default: break;
	case 'w': // 1 string to match.
	return Intrinsic::ptx_read_ntid_w; // "tx.read.ntid.w"
	case 'x': // 1 string to match.
	return Intrinsic::ptx_read_ntid_x; // "tx.read.ntid.x"
	case 'y': // 1 string to match.
	return Intrinsic::ptx_read_ntid_y; // "tx.read.ntid.y"
	case 'z': // 1 string to match.
	return Intrinsic::ptx_read_ntid_z; // "tx.read.ntid.z"
	}
	break;
	case 'w': // 1 string to match.
	if (memcmp(NameR.data()+9, "arpid", 5))
	break;
	return Intrinsic::ptx_read_warpid; // "tx.read.warpid"
	}		}
	break;		break;
	}		}
	break;		break;
	case 15: // 23 strings to match.		case 18: // 8 strings to match.
	switch (NameR[0]) {		if (memcmp(NameR.data()+0, "ips.", 4))
			break;
			switch (NameR[4]) {
	default: break;		default: break;
	case 'p': // 17 strings to match.		case 'm': // 2 strings to match.
	if (memcmp(NameR.data()+1, "c.altivec.", 10))		if (memcmp(NameR.data()+5, "uleu.s.ph.qb", 12))
	break;		break;
	switch (NameR[11]) {		switch (NameR[17]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'l': // 1 string to match.
	if (memcmp(NameR.data()+12, "stt", 3))		return Intrinsic::mips_muleu_s_ph_qbl; // "ips.muleu.s.ph.
	break;		qbl"
	return Intrinsic::ppc_altivec_dstt; // "pc.altivec.dstt"		case 'r': // 1 string to match.
	case 'l': // 3 strings to match.		return Intrinsic::mips_muleu_s_ph_qbr; // "ips.muleu.s.ph.
	if (NameR[12] != 'v')		qbr"
	break;		}
	switch (NameR[13]) {		break;
			case 'p': // 6 strings to match.
			if (memcmp(NameR.data()+5, "rec", 3))
			break;
			switch (NameR[8]) {
			default: break;
			case 'e': // 4 strings to match.
			switch (NameR[9]) {
	default: break;		default: break;
	case 's': // 2 strings to match.		case 'q': // 2 strings to match.
	switch (NameR[14]) {		if (memcmp(NameR.data()+10, "u.ph.qb", 7))
			break;
			switch (NameR[17]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'l': // 1 string to match.
	return Intrinsic::ppc_altivec_lvsl; // "pc.altivec.lvsl "		return Intrinsic::mips_precequ_ph_qbl; // "ips.precequ.ph. qbl"
	case 'r': // 1 string to match.		case 'r': // 1 string to match.
	return Intrinsic::ppc_altivec_lvsr; // "pc.altivec.lvsr "		return Intrinsic::mips_precequ_ph_qbr; // "ips.precequ.ph. qbr"
	}		}
	break;		break;
	case 'x': // 1 string to match.		case 'u': // 2 strings to match.
	if (NameR[14] != 'l')		if (memcmp(NameR.data()+10, ".ph.qb", 6))
	break;
	return Intrinsic::ppc_altivec_lvxl; // "pc.altivec.lvxl
	"
	}
	break;
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+12, "tvx", 3))
	break;
	return Intrinsic::ppc_altivec_stvx; // "pc.altivec.stvx"
	case 'v': // 12 strings to match.
	switch (NameR[12]) {
	default: break;
	case 'r': // 3 strings to match.
	if (NameR[13] != 'l')
	break;		break;
	switch (NameR[14]) {		switch (NameR[16]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vrlb; // "pc.altivec.vrlb
	"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vrlh; // "pc.altivec.vrlh
	"
	case 'w': // 1 string to match.
	return Intrinsic::ppc_altivec_vrlw; // "pc.altivec.vrlw
	"
	}
	break;
	case 's': // 9 strings to match.
	switch (NameR[13]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'l': // 1 string to match.
	if (NameR[14] != 'l')		if (NameR[17] != 'a')
	break;		break;
	return Intrinsic::ppc_altivec_vsel; // "pc.altivec.vsel		return Intrinsic::mips_preceu_ph_qbla; // "ips.preceu.ph.q
	"		bla"
	case 'l': // 4 strings to match.		case 'r': // 1 string to match.
	switch (NameR[14]) {		if (NameR[17] != 'a')
	default: break;		break;
	case 'b': // 1 string to match.		return Intrinsic::mips_preceu_ph_qbra; // "ips.preceu.ph.q
	return Intrinsic::ppc_altivec_vslb; // "pc.altivec.vslb		bra"
	"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vslh; // "pc.altivec.vslh
	"
	case 'o': // 1 string to match.
	return Intrinsic::ppc_altivec_vslo; // "pc.altivec.vslo
	"
	case 'w': // 1 string to match.
	return Intrinsic::ppc_altivec_vslw; // "pc.altivec.vslw
	"
	}
	break;
	case 'r': // 4 strings to match.
	switch (NameR[14]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vsrb; // "pc.altivec.vsrb
	"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vsrh; // "pc.altivec.vsrh
	"
	case 'o': // 1 string to match.
	return Intrinsic::ppc_altivec_vsro; // "pc.altivec.vsro
	"
	case 'w': // 1 string to match.
	return Intrinsic::ppc_altivec_vsrw; // "pc.altivec.vsrw
	"
	}
	break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'r': // 2 strings to match.
	break;
	case 't': // 6 strings to match.
	if (memcmp(NameR.data()+1, "x.read.", 7))
	break;
	switch (NameR[8]) {
	default: break;
	case 'c': // 5 strings to match.
	switch (NameR[9]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case '.': // 1 string to match.
	if (memcmp(NameR.data()+10, "ock64", 5))		if (memcmp(NameR.data()+10, "sra.ph.w", 8))
	break;		break;
	return Intrinsic::ptx_read_clock64; // "tx.read.clock64		return Intrinsic::mips_precr_sra_ph_w; // "ips.precr.sra.p
	"		h.w"
	case 't': // 4 strings to match.		case 'q': // 1 string to match.
	if (memcmp(NameR.data()+10, "aid.", 4))		if (memcmp(NameR.data()+10, ".rs.ph.w", 8))
	break;		break;
	switch (NameR[14]) {		return Intrinsic::mips_precrq_rs_ph_w; // "ips.precrq.rs.p
	default: break;		h.w"
	case 'w': // 1 string to match.
	return Intrinsic::ptx_read_ctaid_w; // "tx.read.ctaid.w
	"
	case 'x': // 1 string to match.
	return Intrinsic::ptx_read_ctaid_x; // "tx.read.ctaid.x
	"
	case 'y': // 1 string to match.
	return Intrinsic::ptx_read_ctaid_y; // "tx.read.ctaid.y
	"
	case 'z': // 1 string to match.
	return Intrinsic::ptx_read_ctaid_z; // "tx.read.ctaid.z
	"
	}
	break;
	}		}
	break;		break;
	case 'n': // 1 string to match.
	if (memcmp(NameR.data()+9, "warpid", 6))
	break;
	return Intrinsic::ptx_read_nwarpid; // "tx.read.nwarpid"
	}		}
	break;		break;
	}		}
	break;		break;
	case 16: // 21 strings to match.		case 19: // 3 strings to match.
	switch (NameR[0]) {		if (memcmp(NameR.data()+0, "ips.prec", 8))
			break;
			switch (NameR[8]) {
	default: break;		default: break;
	case 'p': // 17 strings to match.		case 'e': // 2 strings to match.
	if (memcmp(NameR.data()+1, "c.altivec.", 10))		if (memcmp(NameR.data()+9, "qu.ph.qb", 8))
	break;		break;
	switch (NameR[11]) {		switch (NameR[17]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'l': // 1 string to match.
	if (memcmp(NameR.data()+12, "stst", 4))		if (NameR[18] != 'a')
	break;		break;
	return Intrinsic::ppc_altivec_dstst; // "pc.altivec.dstst"		return Intrinsic::mips_precequ_ph_qbla; // "ips.precequ.ph.
	case 'l': // 3 strings to match.		qbla"
	if (memcmp(NameR.data()+12, "ve", 2))		case 'r': // 1 string to match.
			if (NameR[18] != 'a')
	break;		break;
	switch (NameR[14]) {		return Intrinsic::mips_precequ_ph_qbra; // "ips.precequ.ph.
	default: break;		qbra"
	case 'b': // 1 string to match.		}
	if (NameR[15] != 'x')		break;
	break;		case 'r': // 1 string to match.
	return Intrinsic::ppc_altivec_lvebx; // "pc.altivec.lveb		if (memcmp(NameR.data()+9, "qu.s.qb.ph", 10))
	x"
	case 'h': // 1 string to match.
	if (NameR[15] != 'x')
	break;
	return Intrinsic::ppc_altivec_lvehx; // "pc.altivec.lveh
	x"
	case 'w': // 1 string to match.
	if (NameR[15] != 'x')
	break;
	return Intrinsic::ppc_altivec_lvewx; // "pc.altivec.lvew
	x"
	}
	break;		break;
	case 's': // 1 string to match.		return Intrinsic::mips_precrqu_s_qb_ph; // "ips.precrqu.s.q
	if (memcmp(NameR.data()+12, "tvxl", 4))		b.ph"
	break;		}
	return Intrinsic::ppc_altivec_stvxl; // "pc.altivec.stvxl"		break;
	case 'v': // 12 strings to match.		case 20: // 1 string to match.
	switch (NameR[12]) {		if (memcmp(NameR.data()+0, "ips.precr.sra.r.ph.w", 20))
	default: break;
	case 'c': // 2 strings to match.
	if (NameR[13] != 'f')
	break;
	switch (NameR[14]) {
	default: break;
	case 's': // 1 string to match.
	if (NameR[15] != 'x')
	break;
	return Intrinsic::ppc_altivec_vcfsx; // "pc.altivec.vcfs
	x"
	case 'u': // 1 string to match.
	if (NameR[15] != 'x')
	break;
	return Intrinsic::ppc_altivec_vcfux; // "pc.altivec.vcfu
	x"
	}
	break;
	case 'p': // 2 strings to match.
	switch (NameR[13]) {
	default: break;
	case 'e': // 1 string to match.
	if (memcmp(NameR.data()+14, "rm", 2))
	break;
	return Intrinsic::ppc_altivec_vperm; // "pc.altivec.vper
	m"
	case 'k': // 1 string to match.
	if (memcmp(NameR.data()+14, "px", 2))
	break;
	return Intrinsic::ppc_altivec_vpkpx; // "pc.altivec.vpkp
	x"
	}
	break;
	case 'r': // 5 strings to match.
	switch (NameR[13]) {
	default: break;
	case 'e': // 1 string to match.
	if (memcmp(NameR.data()+14, "fp", 2))
	break;
	return Intrinsic::ppc_altivec_vrefp; // "pc.altivec.vref
	p"
	case 'f': // 4 strings to match.
	if (NameR[14] != 'i')
	break;
	switch (NameR[15]) {
	default: break;
	case 'm': // 1 string to match.
	return Intrinsic::ppc_altivec_vrfim; // "pc.altivec.vrfi
	m"
	case 'n': // 1 string to match.
	return Intrinsic::ppc_altivec_vrfin; // "pc.altivec.vrfi
	n"
	case 'p': // 1 string to match.
	return Intrinsic::ppc_altivec_vrfip; // "pc.altivec.vrfi
	p"
	case 'z': // 1 string to match.
	return Intrinsic::ppc_altivec_vrfiz; // "pc.altivec.vrfi
	z"
	}
	break;
	}
	break;
	case 's': // 3 strings to match.
	if (memcmp(NameR.data()+13, "ra", 2))
	break;
	switch (NameR[15]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vsrab; // "pc.altivec.vsra
	b"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vsrah; // "pc.altivec.vsra
	h"
	case 'w': // 1 string to match.
	return Intrinsic::ppc_altivec_vsraw; // "pc.altivec.vsra
	w"
	}
	break;
	}
	break;
	}
	break;		break;
	case 't': // 4 strings to match.		return Intrinsic::mips_precr_sra_r_ph_w; // "ips.precr.sra.r.ph.w"
	if (memcmp(NameR.data()+1, "x.read.nctaid.", 14))		}
			break; // end of 'm' case.
			case 'n':
			if (NameR.startswith("vvm.ptr.shared.to.gen.")) return Intrinsic::nvvm_
			ptr_shared_to_gen;
			if (NameR.startswith("vvm.ptr.local.to.gen.")) return Intrinsic::nvvm_p
			tr_local_to_gen;
			if (NameR.startswith("vvm.ptr.global.to.gen.")) return Intrinsic::nvvm_
			ptr_global_to_gen;
			if (NameR.startswith("vvm.ptr.gen.to.shared.")) return Intrinsic::nvvm_
			ptr_gen_to_shared;
			if (NameR.startswith("vvm.ptr.gen.to.param.")) return Intrinsic::nvvm_p
			tr_gen_to_param;
			if (NameR.startswith("vvm.ptr.gen.to.local.")) return Intrinsic::nvvm_p
			tr_gen_to_local;
			if (NameR.startswith("vvm.ptr.gen.to.global.")) return Intrinsic::nvvm_
			ptr_gen_to_global;
			if (NameR.startswith("vvm.ptr.gen.to.constant.")) return Intrinsic::nvv
			m_ptr_gen_to_constant;
			if (NameR.startswith("vvm.ptr.constant.to.gen.")) return Intrinsic::nvv
			m_ptr_constant_to_gen;
			if (NameR.startswith("vvm.move.ptr.")) return Intrinsic::nvvm_move_ptr;
			if (NameR.startswith("vvm.ldu.global.p.")) return Intrinsic::nvvm_ldu_g
			lobal_p;
			if (NameR.startswith("vvm.ldu.global.i.")) return Intrinsic::nvvm_ldu_g
			lobal_i;
			if (NameR.startswith("vvm.ldu.global.f.")) return Intrinsic::nvvm_ldu_g
			lobal_f;
			if (NameR.startswith("vvm.ldg.global.p.")) return Intrinsic::nvvm_ldg_g
			lobal_p;
			if (NameR.startswith("vvm.ldg.global.i.")) return Intrinsic::nvvm_ldg_g
			lobal_i;
			if (NameR.startswith("vvm.ldg.global.f.")) return Intrinsic::nvvm_ldg_g
			lobal_f;
			if (NameR.startswith("vvm.compiler.warn.")) return Intrinsic::nvvm_comp
			iler_warn;
			if (NameR.startswith("vvm.compiler.error.")) return Intrinsic::nvvm_com
			piler_error;
			if (NameR.startswith("vvm.atomic.load.inc.32.")) return Intrinsic::nvvm
			_atomic_load_inc_32;
			if (NameR.startswith("vvm.atomic.load.dec.32.")) return Intrinsic::nvvm
			_atomic_load_dec_32;
			if (NameR.startswith("vvm.atomic.load.add.f32.")) return Intrinsic::nvv
			m_atomic_load_add_f32;
			if (NameR.startswith("earbyint.")) return Intrinsic::nearbyint;
			switch (NameR.size()) {
			default: break;
			case 7: // 1 string to match.
			if (memcmp(NameR.data()+0, "vvm.h2f", 7))
			break;
			return Intrinsic::nvvm_h2f; // "vvm.h2f"
			case 8: // 1 string to match.
			if (memcmp(NameR.data()+0, "vvm.prmt", 8))
			break;
			return Intrinsic::nvvm_prmt; // "vvm.prmt"
			case 9: // 5 strings to match.
			if (memcmp(NameR.data()+0, "vvm.", 4))
			break;
			switch (NameR[4]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(NameR.data()+5, "bs.i", 4))
	break;		break;
	switch (NameR[15]) {		return Intrinsic::nvvm_abs_i; // "vvm.abs.i"
			case 'c': // 1 string to match.
			if (memcmp(NameR.data()+5, "lz.i", 4))
			break;
			return Intrinsic::nvvm_clz_i; // "vvm.clz.i"
			case 'm': // 2 strings to match.
			switch (NameR[5]) {
	default: break;		default: break;
	case 'w': // 1 string to match.		case 'a': // 1 string to match.
	return Intrinsic::ptx_read_nctaid_w; // "tx.read.nctaid.w"		if (memcmp(NameR.data()+6, "x.i", 3))
	case 'x': // 1 string to match.		break;
	return Intrinsic::ptx_read_nctaid_x; // "tx.read.nctaid.x"		return Intrinsic::nvvm_max_i; // "vvm.max.i"
	case 'y': // 1 string to match.		case 'i': // 1 string to match.
	return Intrinsic::ptx_read_nctaid_y; // "tx.read.nctaid.y"		if (memcmp(NameR.data()+6, "n.i", 3))
	case 'z': // 1 string to match.		break;
	return Intrinsic::ptx_read_nctaid_z; // "tx.read.nctaid.z"		return Intrinsic::nvvm_min_i; // "vvm.min.i"
	}		}
	break;		break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+5, "ad.i", 4))
			break;
			return Intrinsic::nvvm_sad_i; // "vvm.sad.i"
	}		}
	break;		break;
	case 17: // 29 strings to match.		case 10: // 42 strings to match.
	if (memcmp(NameR.data()+0, "pc.altivec.", 11))		if (memcmp(NameR.data()+0, "vvm.", 4))
	break;		break;
	switch (NameR[11]) {		switch (NameR[4]) {
	default: break;		default: break;
	case 'd': // 2 strings to match.		case 'a': // 1 string to match.
	if (NameR[12] != 's')		if (memcmp(NameR.data()+5, "bs.ll", 5))
	break;		break;
	switch (NameR[13]) {		return Intrinsic::nvvm_abs_ll; // "vvm.abs.ll"
			case 'b': // 2 strings to match.
			if (memcmp(NameR.data()+5, "rev", 3))
			break;
			switch (NameR[8]) {
	default: break;		default: break;
	case 's': // 1 string to match.		case '3': // 1 string to match.
	if (memcmp(NameR.data()+14, "all", 3))		if (NameR[9] != '2')
	break;		break;
	return Intrinsic::ppc_altivec_dssall; // "pc.altivec.dssa		return Intrinsic::nvvm_brev32; // "vvm.brev32"
	ll"		case '6': // 1 string to match.
	case 't': // 1 string to match.		if (NameR[9] != '4')
	if (memcmp(NameR.data()+14, "stt", 3))
	break;		break;
	return Intrinsic::ppc_altivec_dststt; // "pc.altivec.dsts tt"		return Intrinsic::nvvm_brev64; // "vvm.brev64"
	}		}
	break;		break;
	case 'm': // 2 strings to match.		case 'c': // 3 strings to match.
	switch (NameR[12]) {		switch (NameR[5]) {
	default: break;		default: break;
	case 'f': // 1 string to match.		case 'e': // 2 strings to match.
	if (memcmp(NameR.data()+13, "vscr", 4))		if (memcmp(NameR.data()+6, "il.", 3))
	break;		break;
	return Intrinsic::ppc_altivec_mfvscr; // "pc.altivec.mfvs		switch (NameR[9]) {
	cr"		default: break;
	case 't': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+13, "vscr", 4))		return Intrinsic::nvvm_ceil_d; // "vvm.ceil.d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_ceil_f; // "vvm.ceil.f"
			}
			break;
			case 'l': // 1 string to match.
			if (memcmp(NameR.data()+6, "z.ll", 4))
	break;		break;
	return Intrinsic::ppc_altivec_mtvscr; // "pc.altivec.mtvs cr"		return Intrinsic::nvvm_clz_ll; // "vvm.clz.ll"
	}		}
	break;		break;
	case 's': // 3 strings to match.		case 'd': // 10 strings to match.
	if (memcmp(NameR.data()+12, "tve", 3))		if (NameR[5] != '2')
	break;		break;
	switch (NameR[15]) {		switch (NameR[6]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'f': // 4 strings to match.
	if (NameR[16] != 'x')		if (memcmp(NameR.data()+7, ".r", 2))
	break;		break;
	return Intrinsic::ppc_altivec_stvebx; // "pc.altivec.stve		switch (NameR[9]) {
	bx"		default: break;
	case 'h': // 1 string to match.		case 'm': // 1 string to match.
	if (NameR[16] != 'x')		return Intrinsic::nvvm_d2f_rm; // "vvm.d2f.rm"
			case 'n': // 1 string to match.
			return Intrinsic::nvvm_d2f_rn; // "vvm.d2f.rn"
			case 'p': // 1 string to match.
			return Intrinsic::nvvm_d2f_rp; // "vvm.d2f.rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_d2f_rz; // "vvm.d2f.rz"
			}
			break;
			case 'i': // 6 strings to match.
			if (NameR[7] != '.')
	break;		break;
	return Intrinsic::ppc_altivec_stvehx; // "pc.altivec.stve		switch (NameR[8]) {
	hx"		default: break;
	case 'w': // 1 string to match.		case 'h': // 1 string to match.
	if (NameR[16] != 'x')		if (NameR[9] != 'i')
			break;
			return Intrinsic::nvvm_d2i_hi; // "vvm.d2i.hi"
			case 'l': // 1 string to match.
			if (NameR[9] != 'o')
			break;
			return Intrinsic::nvvm_d2i_lo; // "vvm.d2i.lo"
			case 'r': // 4 strings to match.
			switch (NameR[9]) {
			default: break;
			case 'm': // 1 string to match.
			return Intrinsic::nvvm_d2i_rm; // "vvm.d2i.rm"
			case 'n': // 1 string to match.
			return Intrinsic::nvvm_d2i_rn; // "vvm.d2i.rn"
			case 'p': // 1 string to match.
			return Intrinsic::nvvm_d2i_rp; // "vvm.d2i.rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_d2i_rz; // "vvm.d2i.rz"
			}
	break;		break;
	return Intrinsic::ppc_altivec_stvewx; // "pc.altivec.stve		}
	wx"		break;
	}		}
	break;		break;
	case 'v': // 22 strings to match.		case 'f': // 11 strings to match.
	switch (NameR[12]) {		switch (NameR[5]) {
	default: break;		default: break;
	case 'a': // 6 strings to match.		case '2': // 5 strings to match.
	if (memcmp(NameR.data()+13, "vg", 2))		switch (NameR[6]) {
	break;
	switch (NameR[15]) {
	default: break;		default: break;
	case 's': // 3 strings to match.		case 'h': // 1 string to match.
	switch (NameR[16]) {		if (memcmp(NameR.data()+7, ".rn", 3))
	default: break;		break;
	case 'b': // 1 string to match.		return Intrinsic::nvvm_f2h_rn; // "vvm.f2h.rn"
	return Intrinsic::ppc_altivec_vavgsb; // "pc.altivec.vavg		case 'i': // 4 strings to match.
	sb"		if (memcmp(NameR.data()+7, ".r", 2))
	case 'h': // 1 string to match.		break;
	return Intrinsic::ppc_altivec_vavgsh; // "pc.altivec.vavg		switch (NameR[9]) {
	sh"
	case 'w': // 1 string to match.
	return Intrinsic::ppc_altivec_vavgsw; // "pc.altivec.vavg
	sw"
	}
	break;
	case 'u': // 3 strings to match.
	switch (NameR[16]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'm': // 1 string to match.
	return Intrinsic::ppc_altivec_vavgub; // "pc.altivec.vavg		return Intrinsic::nvvm_f2i_rm; // "vvm.f2i.rm"
	ub"		case 'n': // 1 string to match.
	case 'h': // 1 string to match.		return Intrinsic::nvvm_f2i_rn; // "vvm.f2i.rn"
	return Intrinsic::ppc_altivec_vavguh; // "pc.altivec.vavg		case 'p': // 1 string to match.
	uh"		return Intrinsic::nvvm_f2i_rp; // "vvm.f2i.rp"
	case 'w': // 1 string to match.		case 'z': // 1 string to match.
	return Intrinsic::ppc_altivec_vavguw; // "pc.altivec.vavg		return Intrinsic::nvvm_f2i_rz; // "vvm.f2i.rz"
	uw"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'c': // 2 strings to match.		case 'a': // 2 strings to match.
	if (NameR[13] != 't')		if (memcmp(NameR.data()+6, "bs.", 3))
	break;		break;
	switch (NameR[14]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 's': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+15, "xs", 2))		return Intrinsic::nvvm_fabs_d; // "vvm.fabs.d"
	break;		case 'f': // 1 string to match.
	return Intrinsic::ppc_altivec_vctsxs; // "pc.altivec.vcts		return Intrinsic::nvvm_fabs_f; // "vvm.fabs.f"
	xs"
	case 'u': // 1 string to match.
	if (memcmp(NameR.data()+15, "xs", 2))
	break;
	return Intrinsic::ppc_altivec_vctuxs; // "pc.altivec.vctu
	xs"
	}		}
	break;		break;
	case 'm': // 14 strings to match.		case 'm': // 4 strings to match.
	switch (NameR[13]) {		switch (NameR[6]) {
	default: break;		default: break;
	case 'a': // 7 strings to match.		case 'a': // 2 strings to match.
	if (NameR[14] != 'x')		if (memcmp(NameR.data()+7, "x.", 2))
	break;		break;
	switch (NameR[15]) {		switch (NameR[9]) {
	default: break;		default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_fmax_d; // "vvm.fmax.d"
	case 'f': // 1 string to match.		case 'f': // 1 string to match.
	if (NameR[16] != 'p')		return Intrinsic::nvvm_fmax_f; // "vvm.fmax.f"
	break;
	return Intrinsic::ppc_altivec_vmaxfp; // "pc.altivec.vmax
	fp"
	case 's': // 3 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vmaxsb; // "pc.altivec.vmax
	sb"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vmaxsh; // "pc.altivec.vmax
	sh"
	case 'w': // 1 string to match.
	return Intrinsic::ppc_altivec_vmaxsw; // "pc.altivec.vmax
	sw"
	}
	break;
	case 'u': // 3 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vmaxub; // "pc.altivec.vmax
	ub"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vmaxuh; // "pc.altivec.vmax
	uh"
	case 'w': // 1 string to match.
	return Intrinsic::ppc_altivec_vmaxuw; // "pc.altivec.vmax
	uw"
	}
	break;
	}		}
	break;		break;
	case 'i': // 7 strings to match.		case 'i': // 2 strings to match.
	if (NameR[14] != 'n')		if (memcmp(NameR.data()+7, "n.", 2))
	break;		break;
	switch (NameR[15]) {		switch (NameR[9]) {
	default: break;		default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_fmin_d; // "vvm.fmin.d"
	case 'f': // 1 string to match.		case 'f': // 1 string to match.
	if (NameR[16] != 'p')		return Intrinsic::nvvm_fmin_f; // "vvm.fmin.f"
	break;
	return Intrinsic::ppc_altivec_vminfp; // "pc.altivec.vmin
	fp"
	case 's': // 3 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vminsb; // "pc.altivec.vmin
	sb"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vminsh; // "pc.altivec.vmin
	sh"
	case 'w': // 1 string to match.
	return Intrinsic::ppc_altivec_vminsw; // "pc.altivec.vmin
	sw"
	}
	break;
	case 'u': // 3 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vminub; // "pc.altivec.vmin
	ub"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vminuh; // "pc.altivec.vmin
	uh"
	case 'w': // 1 string to match.
	return Intrinsic::ppc_altivec_vminuw; // "pc.altivec.vmin
	uw"
	}
	break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'i': // 8 strings to match.
	break;		if (NameR[5] != '2')
	case 18: // 38 strings to match.
	if (memcmp(NameR.data()+0, "pc.altivec.v", 12))
	break;
	switch (NameR[12]) {
	default: break;
	case 'a': // 7 strings to match.
	if (memcmp(NameR.data()+13, "dd", 2))
	break;		break;
	switch (NameR[15]) {		switch (NameR[6]) {
	default: break;		default: break;
	case 'c': // 1 string to match.		case 'd': // 4 strings to match.
	if (memcmp(NameR.data()+16, "uw", 2))		if (memcmp(NameR.data()+7, ".r", 2))
	break;		break;
	return Intrinsic::ppc_altivec_vaddcuw; // "pc.altivec.vadd		switch (NameR[9]) {
	cuw"
	case 's': // 3 strings to match.
	switch (NameR[16]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'm': // 1 string to match.
	if (NameR[17] != 's')		return Intrinsic::nvvm_i2d_rm; // "vvm.i2d.rm"
	break;		case 'n': // 1 string to match.
	return Intrinsic::ppc_altivec_vaddsbs; // "pc.altivec.vadd		return Intrinsic::nvvm_i2d_rn; // "vvm.i2d.rn"
	sbs"		case 'p': // 1 string to match.
	case 'h': // 1 string to match.		return Intrinsic::nvvm_i2d_rp; // "vvm.i2d.rp"
	if (NameR[17] != 's')		case 'z': // 1 string to match.
			return Intrinsic::nvvm_i2d_rz; // "vvm.i2d.rz"
			}
			break;
			case 'f': // 4 strings to match.
			if (memcmp(NameR.data()+7, ".r", 2))
			break;
			switch (NameR[9]) {
			default: break;
			case 'm': // 1 string to match.
			return Intrinsic::nvvm_i2f_rm; // "vvm.i2f.rm"
			case 'n': // 1 string to match.
			return Intrinsic::nvvm_i2f_rn; // "vvm.i2f.rn"
			case 'p': // 1 string to match.
			return Intrinsic::nvvm_i2f_rp; // "vvm.i2f.rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_i2f_rz; // "vvm.i2f.rz"
			}
			break;
			}
			break;
			case 'm': // 4 strings to match.
			switch (NameR[5]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(NameR.data()+6, "x.", 2))
			break;
			switch (NameR[8]) {
			default: break;
			case 'l': // 1 string to match.
			if (NameR[9] != 'l')
	break;		break;
	return Intrinsic::ppc_altivec_vaddshs; // "pc.altivec.vadd		return Intrinsic::nvvm_max_ll; // "vvm.max.ll"
	shs"		case 'u': // 1 string to match.
	case 'w': // 1 string to match.		if (NameR[9] != 'i')
	if (NameR[17] != 's')
	break;		break;
	return Intrinsic::ppc_altivec_vaddsws; // "pc.altivec.vadd sws"		return Intrinsic::nvvm_max_ui; // "vvm.max.ui"
	}		}
	break;		break;
	case 'u': // 3 strings to match.		case 'i': // 2 strings to match.
	switch (NameR[16]) {		if (memcmp(NameR.data()+6, "n.", 2))
			break;
			switch (NameR[8]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'l': // 1 string to match.
	if (NameR[17] != 's')		if (NameR[9] != 'l')
	break;
	return Intrinsic::ppc_altivec_vaddubs; // "pc.altivec.vadd
	ubs"
	case 'h': // 1 string to match.
	if (NameR[17] != 's')
	break;		break;
	return Intrinsic::ppc_altivec_vadduhs; // "pc.altivec.vadd		return Intrinsic::nvvm_min_ll; // "vvm.min.ll"
	uhs"		case 'u': // 1 string to match.
	case 'w': // 1 string to match.		if (NameR[9] != 'i')
	if (NameR[17] != 's')
	break;		break;
	return Intrinsic::ppc_altivec_vadduws; // "pc.altivec.vadd uws"		return Intrinsic::nvvm_min_ui; // "vvm.min.ui"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'c': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(NameR.data()+13, "mpbfp", 5))		if (memcmp(NameR.data()+5, "opc.i", 5))
	break;
	return Intrinsic::ppc_altivec_vcmpbfp; // "pc.altivec.vcmpbfp"
	case 'l': // 1 string to match.
	if (memcmp(NameR.data()+13, "ogefp", 5))
	break;		break;
	return Intrinsic::ppc_altivec_vlogefp; // "pc.altivec.vlogefp"		return Intrinsic::nvvm_popc_i; // "vvm.popc.i"
	case 'm': // 9 strings to match.		case 's': // 2 strings to match.
	switch (NameR[13]) {		switch (NameR[5]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(NameR.data()+14, "ddfp", 4))		if (memcmp(NameR.data()+6, "d.ui", 4))
	break;		break;
	return Intrinsic::ppc_altivec_vmaddfp; // "pc.altivec.vmad		return Intrinsic::nvvm_sad_ui; // "vvm.sad.ui"
	dfp"		case 'q': // 1 string to match.
	case 'u': // 8 strings to match.		if (memcmp(NameR.data()+6, "rt.f", 4))
	if (NameR[14] != 'l')
	break;		break;
	switch (NameR[15]) {		return Intrinsic::nvvm_sqrt_f; // "vvm.sqrt.f"
	default: break;
	case 'e': // 4 strings to match.
	switch (NameR[16]) {
	default: break;
	case 's': // 2 strings to match.
	switch (NameR[17]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vmulesb; // "pc.altivec.vmul
	esb"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vmulesh; // "pc.altivec.vmul
	esh"
	}
	break;
	case 'u': // 2 strings to match.
	switch (NameR[17]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vmuleub; // "pc.altivec.vmul
	eub"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vmuleuh; // "pc.altivec.vmul
	euh"
	}
	break;
	}
	break;
	case 'o': // 4 strings to match.
	switch (NameR[16]) {
	default: break;
	case 's': // 2 strings to match.
	switch (NameR[17]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vmulosb; // "pc.altivec.vmul
	osb"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vmulosh; // "pc.altivec.vmul
	osh"
	}
	break;
	case 'u': // 2 strings to match.
	switch (NameR[17]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vmuloub; // "pc.altivec.vmul
	oub"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vmulouh; // "pc.altivec.vmul
	ouh"
	}
	break;
	}
	break;
	}
	break;
	}		}
	break;		break;
	case 'p': // 6 strings to match.		}
	if (NameR[13] != 'k')		break;
			case 11: // 43 strings to match.
			if (memcmp(NameR.data()+0, "vvm.", 4))
			break;
			switch (NameR[4]) {
			default: break;
			case 'd': // 8 strings to match.
			if (NameR[5] != '2')
	break;		break;
	switch (NameR[14]) {		switch (NameR[6]) {
	default: break;		default: break;
	case 's': // 4 strings to match.		case 'l': // 4 strings to match.
	switch (NameR[15]) {		if (memcmp(NameR.data()+7, "l.r", 3))
	default: break;
	case 'h': // 2 strings to match.
	switch (NameR[16]) {
	default: break;
	case 's': // 1 string to match.
	if (NameR[17] != 's')
	break;
	return Intrinsic::ppc_altivec_vpkshss; // "pc.altivec.vpks
	hss"
	case 'u': // 1 string to match.
	if (NameR[17] != 's')
	break;
	return Intrinsic::ppc_altivec_vpkshus; // "pc.altivec.vpks
	hus"
	}
	break;
	case 'w': // 2 strings to match.
	switch (NameR[16]) {
	default: break;
	case 's': // 1 string to match.
	if (NameR[17] != 's')
	break;
	return Intrinsic::ppc_altivec_vpkswss; // "pc.altivec.vpks
	wss"
	case 'u': // 1 string to match.
	if (NameR[17] != 's')
	break;
	return Intrinsic::ppc_altivec_vpkswus; // "pc.altivec.vpks
	wus"
	}
	break;		break;
			switch (NameR[10]) {
			default: break;
			case 'm': // 1 string to match.
			return Intrinsic::nvvm_d2ll_rm; // "vvm.d2ll.rm"
			case 'n': // 1 string to match.
			return Intrinsic::nvvm_d2ll_rn; // "vvm.d2ll.rn"
			case 'p': // 1 string to match.
			return Intrinsic::nvvm_d2ll_rp; // "vvm.d2ll.rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_d2ll_rz; // "vvm.d2ll.rz"
	}		}
	break;		break;
	case 'u': // 2 strings to match.		case 'u': // 4 strings to match.
	switch (NameR[15]) {		if (memcmp(NameR.data()+7, "i.r", 3))
			break;
			switch (NameR[10]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'm': // 1 string to match.
	if (memcmp(NameR.data()+16, "us", 2))		return Intrinsic::nvvm_d2ui_rm; // "vvm.d2ui.rm"
	break;		case 'n': // 1 string to match.
	return Intrinsic::ppc_altivec_vpkuhus; // "pc.altivec.vpku		return Intrinsic::nvvm_d2ui_rn; // "vvm.d2ui.rn"
	hus"		case 'p': // 1 string to match.
	case 'w': // 1 string to match.		return Intrinsic::nvvm_d2ui_rp; // "vvm.d2ui.rp"
	if (memcmp(NameR.data()+16, "us", 2))		case 'z': // 1 string to match.
	break;		return Intrinsic::nvvm_d2ui_rz; // "vvm.d2ui.rz"
	return Intrinsic::ppc_altivec_vpkuwus; // "pc.altivec.vpku
	wus"
	}		}
	break;		break;
	}		}
	break;		break;
	case 's': // 8 strings to match.		case 'f': // 10 strings to match.
	if (NameR[13] != 'u')		switch (NameR[5]) {
	break;
	switch (NameR[14]) {
	default: break;		default: break;
	case 'b': // 7 strings to match.		case '2': // 8 strings to match.
	switch (NameR[15]) {		switch (NameR[6]) {
	default: break;		default: break;
	case 'c': // 1 string to match.		case 'l': // 4 strings to match.
	if (memcmp(NameR.data()+16, "uw", 2))		if (memcmp(NameR.data()+7, "l.r", 3))
	break;		break;
	return Intrinsic::ppc_altivec_vsubcuw; // "pc.altivec.vsub		switch (NameR[10]) {
	cuw"
	case 's': // 3 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'b': // 1 string to match.
	if (NameR[17] != 's')
	break;
	return Intrinsic::ppc_altivec_vsubsbs; // "pc.altivec.vsub
	sbs"
	case 'h': // 1 string to match.
	if (NameR[17] != 's')
	break;
	return Intrinsic::ppc_altivec_vsubshs; // "pc.altivec.vsub
	shs"
	case 'w': // 1 string to match.
	if (NameR[17] != 's')
	break;
	return Intrinsic::ppc_altivec_vsubsws; // "pc.altivec.vsub
	sws"
	}
	break;
	case 'u': // 3 strings to match.
	switch (NameR[16]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'm': // 1 string to match.
	if (NameR[17] != 's')		return Intrinsic::nvvm_f2ll_rm; // "vvm.f2ll.rm"
	break;		case 'n': // 1 string to match.
	return Intrinsic::ppc_altivec_vsububs; // "pc.altivec.vsub		return Intrinsic::nvvm_f2ll_rn; // "vvm.f2ll.rn"
	ubs"		case 'p': // 1 string to match.
	case 'h': // 1 string to match.		return Intrinsic::nvvm_f2ll_rp; // "vvm.f2ll.rp"
	if (NameR[17] != 's')		case 'z': // 1 string to match.
	break;		return Intrinsic::nvvm_f2ll_rz; // "vvm.f2ll.rz"
	return Intrinsic::ppc_altivec_vsubuhs; // "pc.altivec.vsub
	uhs"
	case 'w': // 1 string to match.
	if (NameR[17] != 's')
	break;
	return Intrinsic::ppc_altivec_vsubuws; // "pc.altivec.vsub
	uws"
	}		}
	break;		break;
	}		case 'u': // 4 strings to match.
	break;		if (memcmp(NameR.data()+7, "i.r", 3))
	case 'm': // 1 string to match.
	if (memcmp(NameR.data()+15, "sws", 3))
	break;
	return Intrinsic::ppc_altivec_vsumsws; // "pc.altivec.vsum
	sws"
	}
	break;
	case 'u': // 6 strings to match.
	if (memcmp(NameR.data()+13, "pk", 2))
	break;
	switch (NameR[15]) {
	default: break;
	case 'h': // 3 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'p': // 1 string to match.
	if (NameR[17] != 'x')
	break;		break;
	return Intrinsic::ppc_altivec_vupkhpx; // "pc.altivec.vupk		switch (NameR[10]) {
	hpx"
	case 's': // 2 strings to match.
	switch (NameR[17]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'm': // 1 string to match.
	return Intrinsic::ppc_altivec_vupkhsb; // "pc.altivec.vupk		return Intrinsic::nvvm_f2ui_rm; // "vvm.f2ui.rm"
	hsb"		case 'n': // 1 string to match.
	case 'h': // 1 string to match.		return Intrinsic::nvvm_f2ui_rn; // "vvm.f2ui.rn"
	return Intrinsic::ppc_altivec_vupkhsh; // "pc.altivec.vupk		case 'p': // 1 string to match.
	hsh"		return Intrinsic::nvvm_f2ui_rp; // "vvm.f2ui.rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_f2ui_rz; // "vvm.f2ui.rz"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'l': // 3 strings to match.		case 'l': // 2 strings to match.
	switch (NameR[16]) {		if (memcmp(NameR.data()+6, "oor.", 4))
	default: break;
	case 'p': // 1 string to match.
	if (NameR[17] != 'x')
	break;
	return Intrinsic::ppc_altivec_vupklpx; // "pc.altivec.vupk
	lpx"
	case 's': // 2 strings to match.
	switch (NameR[17]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vupklsb; // "pc.altivec.vupk
	lsb"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vupklsh; // "pc.altivec.vupk
	lsh"
	}
	break;		break;
			switch (NameR[10]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_floor_d; // "vvm.floor.d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_floor_f; // "vvm.floor.f"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'l': // 8 strings to match.
	break;		if (memcmp(NameR.data()+5, "l2", 2))
	case 19: // 29 strings to match.
	switch (NameR[0]) {
	default: break;
	case 'p': // 24 strings to match.
	if (memcmp(NameR.data()+1, "c.altivec.v", 11))
	break;		break;
	switch (NameR[12]) {		switch (NameR[7]) {
	default: break;		default: break;
	case 'c': // 12 strings to match.		case 'd': // 4 strings to match.
	if (memcmp(NameR.data()+13, "mp", 2))		if (memcmp(NameR.data()+8, ".r", 2))
	break;		break;
	switch (NameR[15]) {		switch (NameR[10]) {
	default: break;		default: break;
	case 'e': // 4 strings to match.		case 'm': // 1 string to match.
	if (NameR[16] != 'q')		return Intrinsic::nvvm_ll2d_rm; // "vvm.ll2d.rm"
	break;		case 'n': // 1 string to match.
	switch (NameR[17]) {		return Intrinsic::nvvm_ll2d_rn; // "vvm.ll2d.rn"
	default: break;		case 'p': // 1 string to match.
	case 'f': // 1 string to match.		return Intrinsic::nvvm_ll2d_rp; // "vvm.ll2d.rp"
	if (NameR[18] != 'p')		case 'z': // 1 string to match.
	break;		return Intrinsic::nvvm_ll2d_rz; // "vvm.ll2d.rz"
	return Intrinsic::ppc_altivec_vcmpeqfp; // "pc.altivec.vcmp
	eqfp"
	case 'u': // 3 strings to match.
	switch (NameR[18]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vcmpequb; // "pc.alti
	vec.vcmpequb"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vcmpequh; // "pc.alti
	vec.vcmpequh"
	case 'w': // 1 string to match.
	return Intrinsic::ppc_altivec_vcmpequw; // "pc.alti
	vec.vcmpequw"
	}
	break;
	}
	break;
	case 'g': // 8 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'e': // 1 string to match.
	if (memcmp(NameR.data()+17, "fp", 2))
	break;
	return Intrinsic::ppc_altivec_vcmpgefp; // "pc.altivec.vcmp
	gefp"
	case 't': // 7 strings to match.
	switch (NameR[17]) {
	default: break;
	case 'f': // 1 string to match.
	if (NameR[18] != 'p')
	break;
	return Intrinsic::ppc_altivec_vcmpgtfp; // "pc.alti
	vec.vcmpgtfp"
	case 's': // 3 strings to match.
	switch (NameR[18]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vcmpgtsb; // "pc.alti
	vec.vcmpgtsb"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vcmpgtsh; // "pc.alti
	vec.vcmpgtsh"
	case 'w': // 1 string to match.
	return Intrinsic::ppc_altivec_vcmpgtsw; // "pc.alti
	vec.vcmpgtsw"
	}
	break;
	case 'u': // 3 strings to match.
	switch (NameR[18]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::ppc_altivec_vcmpgtub; // "pc.alti
	vec.vcmpgtub"
	case 'h': // 1 string to match.
	return Intrinsic::ppc_altivec_vcmpgtuh; // "pc.alti
	vec.vcmpgtuh"
	case 'w': // 1 string to match.
	return Intrinsic::ppc_altivec_vcmpgtuw; // "pc.alti
	vec.vcmpgtuw"
	}
	break;
	}
	break;
	}
	break;
	}		}
	break;		break;
	case 'e': // 1 string to match.		case 'f': // 4 strings to match.
	if (memcmp(NameR.data()+13, "xptefp", 6))		if (memcmp(NameR.data()+8, ".r", 2))
	break;
	return Intrinsic::ppc_altivec_vexptefp; // "pc.altivec.vexp
	tefp"
	case 'm': // 6 strings to match.
	if (memcmp(NameR.data()+13, "sum", 3))
	break;		break;
	switch (NameR[16]) {		switch (NameR[10]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'm': // 1 string to match.
	if (memcmp(NameR.data()+17, "bm", 2))		return Intrinsic::nvvm_ll2f_rm; // "vvm.ll2f.rm"
	break;		case 'n': // 1 string to match.
	return Intrinsic::ppc_altivec_vmsummbm; // "pc.altivec.vmsu		return Intrinsic::nvvm_ll2f_rn; // "vvm.ll2f.rn"
	mmbm"		case 'p': // 1 string to match.
	case 's': // 2 strings to match.		return Intrinsic::nvvm_ll2f_rp; // "vvm.ll2f.rp"
	if (NameR[17] != 'h')		case 'z': // 1 string to match.
	break;		return Intrinsic::nvvm_ll2f_rz; // "vvm.ll2f.rz"
	switch (NameR[18]) {
	default: break;
	case 'm': // 1 string to match.
	return Intrinsic::ppc_altivec_vmsumshm; // "pc.altivec.vmsu
	mshm"
	case 's': // 1 string to match.
	return Intrinsic::ppc_altivec_vmsumshs; // "pc.altivec.vmsu
	mshs"
	}
	break;
	case 'u': // 3 strings to match.
	switch (NameR[17]) {
	default: break;
	case 'b': // 1 string to match.
	if (NameR[18] != 'm')
	break;
	return Intrinsic::ppc_altivec_vmsumubm; // "pc.altivec.vmsu
	mubm"
	case 'h': // 2 strings to match.
	switch (NameR[18]) {
	default: break;
	case 'm': // 1 string to match.
	return Intrinsic::ppc_altivec_vmsumuhm; // "pc.alti
	vec.vmsumuhm"
	case 's': // 1 string to match.
	return Intrinsic::ppc_altivec_vmsumuhs; // "pc.alti
	vec.vmsumuhs"
	}
	break;
	}
	break;
	}		}
	break;		break;
	case 'n': // 1 string to match.		}
	if (memcmp(NameR.data()+13, "msubfp", 6))		break;
			case 'm': // 4 strings to match.
			switch (NameR[5]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(NameR.data()+6, "x.ull", 5))
	break;		break;
	return Intrinsic::ppc_altivec_vnmsubfp; // "pc.altivec.vnms		return Intrinsic::nvvm_max_ull; // "vvm.max.ull"
	ubfp"		case 'i': // 1 string to match.
	case 's': // 4 strings to match.		if (memcmp(NameR.data()+6, "n.ull", 5))
	if (memcmp(NameR.data()+13, "um", 2))
	break;		break;
	switch (NameR[15]) {		return Intrinsic::nvvm_min_ull; // "vvm.min.ull"
			case 'u': // 2 strings to match.
			if (NameR[6] != 'l')
			break;
			switch (NameR[7]) {
	default: break;		default: break;
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(NameR.data()+16, "sws", 3))		if (memcmp(NameR.data()+8, "4.i", 3))
	break;		break;
	return Intrinsic::ppc_altivec_vsum2sws; // "pc.altivec.vsum		return Intrinsic::nvvm_mul24_i; // "vvm.mul24.i"
	2sws"		case 'h': // 1 string to match.
	case '4': // 3 strings to match.		if (memcmp(NameR.data()+8, "i.i", 3))
	switch (NameR[16]) {
	default: break;
	case 's': // 2 strings to match.
	switch (NameR[17]) {
	default: break;
	case 'b': // 1 string to match.
	if (NameR[18] != 's')
	break;
	return Intrinsic::ppc_altivec_vsum4sbs; // "pc.alti
	vec.vsum4sbs"
	case 'h': // 1 string to match.
	if (NameR[18] != 's')
	break;
	return Intrinsic::ppc_altivec_vsum4shs; // "pc.alti
	vec.vsum4shs"
	}
	break;		break;
	case 'u': // 1 string to match.		return Intrinsic::nvvm_mulhi_i; // "vvm.mulhi.i"
	if (memcmp(NameR.data()+17, "bs", 2))
	break;
	return Intrinsic::ppc_altivec_vsum4ubs; // "pc.altivec.vsum
	4ubs"
	}
	break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 't': // 5 strings to match.		case 'p': // 1 string to match.
	if (memcmp(NameR.data()+1, "x.read.lanemask.", 16))		if (memcmp(NameR.data()+5, "opc.ll", 6))
	break;		break;
	switch (NameR[17]) {		return Intrinsic::nvvm_popc_ll; // "vvm.popc.ll"
			case 'r': // 2 strings to match.
			if (memcmp(NameR.data()+5, "ound.", 5))
			break;
			switch (NameR[10]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'd': // 1 string to match.
	if (NameR[18] != 'q')		return Intrinsic::nvvm_round_d; // "vvm.round.d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_round_f; // "vvm.round.f"
			}
			break;
			case 't': // 2 strings to match.
			if (memcmp(NameR.data()+5, "runc.", 5))
			break;
			switch (NameR[10]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_trunc_d; // "vvm.trunc.d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_trunc_f; // "vvm.trunc.f"
			}
			break;
			case 'u': // 8 strings to match.
			if (memcmp(NameR.data()+5, "i2", 2))
			break;
			switch (NameR[7]) {
			default: break;
			case 'd': // 4 strings to match.
			if (memcmp(NameR.data()+8, ".r", 2))
	break;		break;
	return Intrinsic::ptx_read_lanemask_eq; // "tx.read.lanemas		switch (NameR[10]) {
	k.eq"
	case 'g': // 2 strings to match.
	switch (NameR[18]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'm': // 1 string to match.
	return Intrinsic::ptx_read_lanemask_ge; // "tx.read.lanemas		return Intrinsic::nvvm_ui2d_rm; // "vvm.ui2d.rm"
	k.ge"		case 'n': // 1 string to match.
	case 't': // 1 string to match.		return Intrinsic::nvvm_ui2d_rn; // "vvm.ui2d.rn"
	return Intrinsic::ptx_read_lanemask_gt; // "tx.read.lanemas		case 'p': // 1 string to match.
	k.gt"		return Intrinsic::nvvm_ui2d_rp; // "vvm.ui2d.rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_ui2d_rz; // "vvm.ui2d.rz"
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'f': // 4 strings to match.
	switch (NameR[18]) {		if (memcmp(NameR.data()+8, ".r", 2))
			break;
			switch (NameR[10]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'm': // 1 string to match.
	return Intrinsic::ptx_read_lanemask_le; // "tx.read.lanemas		return Intrinsic::nvvm_ui2f_rm; // "vvm.ui2f.rm"
	k.le"		case 'n': // 1 string to match.
	case 't': // 1 string to match.		return Intrinsic::nvvm_ui2f_rn; // "vvm.ui2f.rn"
	return Intrinsic::ptx_read_lanemask_lt; // "tx.read.lanemas		case 'p': // 1 string to match.
	k.lt"		return Intrinsic::nvvm_ui2f_rp; // "vvm.ui2f.rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_ui2f_rz; // "vvm.ui2f.rz"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 20: // 4 strings to match.		case 12: // 64 strings to match.
	if (memcmp(NameR.data()+0, "pc.altivec.v", 12))		if (memcmp(NameR.data()+0, "vvm.", 4))
	break;		break;
	switch (NameR[12]) {		switch (NameR[4]) {
	default: break;		default: break;
	case 'c': // 1 string to match.		case 'a': // 8 strings to match.
	if (memcmp(NameR.data()+13, "mpbfp.p", 7))		if (memcmp(NameR.data()+5, "dd.r", 4))
	break;		break;
	return Intrinsic::ppc_altivec_vcmpbfp_p; // "pc.altivec.vcmp		switch (NameR[9]) {
	bfp.p"
	case 'm': // 2 strings to match.
	switch (NameR[13]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'm': // 2 strings to match.
	if (memcmp(NameR.data()+14, "addshs", 6))		if (NameR[10] != '.')
	break;
	return Intrinsic::ppc_altivec_vmhaddshs; // "pc.altivec.vmha
	ddshs"
	case 'l': // 1 string to match.
	if (memcmp(NameR.data()+14, "adduhm", 6))
	break;		break;
	return Intrinsic::ppc_altivec_vmladduhm; // "pc.altivec.vmla		switch (NameR[11]) {
	dduhm"		default: break;
	}		case 'd': // 1 string to match.
	break;		return Intrinsic::nvvm_add_rm_d; // "vvm.add.rm.d"
	case 'r': // 1 string to match.		case 'f': // 1 string to match.
	if (memcmp(NameR.data()+13, "sqrtefp", 7))		return Intrinsic::nvvm_add_rm_f; // "vvm.add.rm.f"
	break;		}
	return Intrinsic::ppc_altivec_vrsqrtefp; // "pc.altivec.vrsq
	rtefp"
	}
	break;
	case 21: // 13 strings to match.
	if (memcmp(NameR.data()+0, "pc.altivec.v", 12))
	break;
	switch (NameR[12]) {
	default: break;
	case 'c': // 12 strings to match.
	if (memcmp(NameR.data()+13, "mp", 2))
	break;		break;
	switch (NameR[15]) {		case 'n': // 2 strings to match.
	default: break;		if (NameR[10] != '.')
	case 'e': // 4 strings to match.
	if (NameR[16] != 'q')
	break;		break;
	switch (NameR[17]) {		switch (NameR[11]) {
	default: break;		default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_add_rn_d; // "vvm.add.rn.d"
	case 'f': // 1 string to match.		case 'f': // 1 string to match.
	if (memcmp(NameR.data()+18, "p.p", 3))		return Intrinsic::nvvm_add_rn_f; // "vvm.add.rn.f"
	break;
	return Intrinsic::ppc_altivec_vcmpeqfp_p; // "pc.altivec.vcmp
	eqfp.p"
	case 'u': // 3 strings to match.
	switch (NameR[18]) {
	default: break;
	case 'b': // 1 string to match.
	if (memcmp(NameR.data()+19, ".p", 2))
	break;
	return Intrinsic::ppc_altivec_vcmpequb_p; // "pc.alti
	vec.vcmpequb.p"
	case 'h': // 1 string to match.
	if (memcmp(NameR.data()+19, ".p", 2))
	break;
	return Intrinsic::ppc_altivec_vcmpequh_p; // "pc.alti
	vec.vcmpequh.p"
	case 'w': // 1 string to match.
	if (memcmp(NameR.data()+19, ".p", 2))
	break;
	return Intrinsic::ppc_altivec_vcmpequw_p; // "pc.alti
	vec.vcmpequw.p"
	}
	break;
	}		}
	break;		break;
	case 'g': // 8 strings to match.		case 'p': // 2 strings to match.
	switch (NameR[16]) {		if (NameR[10] != '.')
	default: break;
	case 'e': // 1 string to match.
	if (memcmp(NameR.data()+17, "fp.p", 4))
	break;
	return Intrinsic::ppc_altivec_vcmpgefp_p; // "pc.altivec.vcmp
	gefp.p"
	case 't': // 7 strings to match.
	switch (NameR[17]) {
	default: break;
	case 'f': // 1 string to match.
	if (memcmp(NameR.data()+18, "p.p", 3))
	break;
	return Intrinsic::ppc_altivec_vcmpgtfp_p; // "pc.alti
	vec.vcmpgtfp.p"
	case 's': // 3 strings to match.
	switch (NameR[18]) {
	default: break;
	case 'b': // 1 string to match.
	if (memcmp(NameR.data()+19, ".p", 2))
	break;
	return Intrinsic::ppc_altivec_vcmpgtsb_p; // "pc.alti
	vec.vcmpgtsb.p"
	case 'h': // 1 string to match.
	if (memcmp(NameR.data()+19, ".p", 2))
	break;
	return Intrinsic::ppc_altivec_vcmpgtsh_p; // "pc.alti
	vec.vcmpgtsh.p"
	case 'w': // 1 string to match.
	if (memcmp(NameR.data()+19, ".p", 2))
	break;
	return Intrinsic::ppc_altivec_vcmpgtsw_p; // "pc.alti
	vec.vcmpgtsw.p"
	}
	break;
	case 'u': // 3 strings to match.
	switch (NameR[18]) {
	default: break;
	case 'b': // 1 string to match.
	if (memcmp(NameR.data()+19, ".p", 2))
	break;
	return Intrinsic::ppc_altivec_vcmpgtub_p; // "pc.alti
	vec.vcmpgtub.p"
	case 'h': // 1 string to match.
	if (memcmp(NameR.data()+19, ".p", 2))
	break;
	return Intrinsic::ppc_altivec_vcmpgtuh_p; // "pc.alti
	vec.vcmpgtuh.p"
	case 'w': // 1 string to match.
	if (memcmp(NameR.data()+19, ".p", 2))
	break;
	return Intrinsic::ppc_altivec_vcmpgtuw_p; // "pc.alti
	vec.vcmpgtuw.p"
	}
	break;
	}
	break;		break;
			switch (NameR[11]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_add_rp_d; // "vvm.add.rp.d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_add_rp_f; // "vvm.add.rp.f"
	}		}
	break;		break;
	}		case 'z': // 2 strings to match.
	break;		if (NameR[10] != '.')
	case 'm': // 1 string to match.
	if (memcmp(NameR.data()+13, "hraddshs", 8))
	break;
	return Intrinsic::ppc_altivec_vmhraddshs; // "pc.altivec.vmhr
	addshs"
	}
	break;
	}
	break; // end of 'p' case.
	case 'r':
	if (NameR.startswith("int.")) return Intrinsic::rint;
	switch (NameR.size()) {
	default: break;
	case 12: // 1 string to match.
	if (memcmp(NameR.data()+0, "eturnaddress", 12))
	break;
	return Intrinsic::returnaddress; // "eturnaddress"
	case 15: // 4 strings to match.
	switch (NameR[0]) {
	default: break;
	case '6': // 3 strings to match.
	if (memcmp(NameR.data()+1, "00.read.tgid.", 13))
	break;
	switch (NameR[14]) {
	default: break;
	case 'x': // 1 string to match.
	return Intrinsic::r600_read_tgid_x; // "600.read.tgid.x"
	case 'y': // 1 string to match.
	return Intrinsic::r600_read_tgid_y; // "600.read.tgid.y"
	case 'z': // 1 string to match.
	return Intrinsic::r600_read_tgid_z; // "600.read.tgid.z"
	}
	break;
	case 'e': // 1 string to match.
	if (memcmp(NameR.data()+1, "adcyclecounter", 14))
	break;
	return Intrinsic::readcyclecounter; // "eadcyclecounter"
	}
	break;
	case 16: // 3 strings to match.
	if (memcmp(NameR.data()+0, "600.read.tidig.", 15))
	break;
	switch (NameR[15]) {
	default: break;
	case 'x': // 1 string to match.
	return Intrinsic::r600_read_tidig_x; // "600.read.tidig.x"
	case 'y': // 1 string to match.
	return Intrinsic::r600_read_tidig_y; // "600.read.tidig.y"
	case 'z': // 1 string to match.
	return Intrinsic::r600_read_tidig_z; // "600.read.tidig.z"
	}
	break;
	case 18: // 3 strings to match.
	if (memcmp(NameR.data()+0, "600.read.ngroups.", 17))
	break;
	switch (NameR[17]) {
	default: break;
	case 'x': // 1 string to match.
	return Intrinsic::r600_read_ngroups_x; // "600.read.ngroups.x"
	case 'y': // 1 string to match.
	return Intrinsic::r600_read_ngroups_y; // "600.read.ngroups.y"
	case 'z': // 1 string to match.
	return Intrinsic::r600_read_ngroups_z; // "600.read.ngroups.z"
	}
	break;
	case 21: // 3 strings to match.
	if (memcmp(NameR.data()+0, "600.read.local.size.", 20))
	break;
	switch (NameR[20]) {
	default: break;
	case 'x': // 1 string to match.
	return Intrinsic::r600_read_local_size_x; // "600.read.local.
	size.x"
	case 'y': // 1 string to match.
	return Intrinsic::r600_read_local_size_y; // "600.read.local.
	size.y"
	case 'z': // 1 string to match.
	return Intrinsic::r600_read_local_size_z; // "600.read.local.
	size.z"
	}
	break;
	case 22: // 3 strings to match.
	if (memcmp(NameR.data()+0, "600.read.global.size.", 21))
	break;
	switch (NameR[21]) {
	default: break;
	case 'x': // 1 string to match.
	return Intrinsic::r600_read_global_size_x; // "600.read.global
	.size.x"
	case 'y': // 1 string to match.
	return Intrinsic::r600_read_global_size_y; // "600.read.global
	.size.y"
	case 'z': // 1 string to match.
	return Intrinsic::r600_read_global_size_z; // "600.read.global
	.size.z"
	}
	break;
	}
	break; // end of 'r' case.
	case 's':
	if (NameR.startswith("add.with.overflow.")) return Intrinsic::sadd_with
	_overflow;
	if (NameR.startswith("in.")) return Intrinsic::sin;
	if (NameR.startswith("mul.with.overflow.")) return Intrinsic::smul_with
	_overflow;
	if (NameR.startswith("qrt.")) return Intrinsic::sqrt;
	if (NameR.startswith("sub.with.overflow.")) return Intrinsic::ssub_with
	_overflow;
	switch (NameR.size()) {
	default: break;
	case 5: // 1 string to match.
	if (memcmp(NameR.data()+0, "etjmp", 5))
	break;
	return Intrinsic::setjmp; // "etjmp"
	case 8: // 2 strings to match.
	switch (NameR[0]) {
	default: break;
	case 'i': // 1 string to match.
	if (memcmp(NameR.data()+1, "gsetjmp", 7))
	break;
	return Intrinsic::sigsetjmp; // "igsetjmp"
	case 't': // 1 string to match.
	if (memcmp(NameR.data()+1, "acksave", 7))
	break;
	return Intrinsic::stacksave; // "tacksave"
	}
	break;
	case 9: // 1 string to match.
	if (memcmp(NameR.data()+0, "iglongjmp", 9))
	break;
	return Intrinsic::siglongjmp; // "iglongjmp"
	case 11: // 1 string to match.
	if (memcmp(NameR.data()+0, "tackrestore", 11))
	break;
	return Intrinsic::stackrestore; // "tackrestore"
	case 13: // 1 string to match.
	if (memcmp(NameR.data()+0, "tackprotector", 13))
	break;
	return Intrinsic::stackprotector; // "tackprotector"
	}
	break; // end of 's' case.
	case 't':
	if (NameR.startswith("runc.")) return Intrinsic::trunc;
	switch (NameR.size()) {
	default: break;
	case 3: // 1 string to match.
	if (memcmp(NameR.data()+0, "rap", 3))
	break;
	return Intrinsic::trap; // "rap"
	}
	break; // end of 't' case.
	case 'u':
	if (NameR.startswith("add.with.overflow.")) return Intrinsic::uadd_with
	_overflow;
	if (NameR.startswith("mul.with.overflow.")) return Intrinsic::umul_with
	_overflow;
	if (NameR.startswith("sub.with.overflow.")) return Intrinsic::usub_with
	_overflow;
	break; // end of 'u' case.
	case 'v':
	switch (NameR.size()) {
	default: break;
	case 5: // 1 string to match.
	if (memcmp(NameR.data()+0, "a_end", 5))
	break;
	return Intrinsic::vaend; // "a_end"
	case 6: // 1 string to match.
	if (memcmp(NameR.data()+0, "a_copy", 6))
	break;
	return Intrinsic::vacopy; // "a_copy"
	case 7: // 1 string to match.
	if (memcmp(NameR.data()+0, "a_start", 7))
	break;
	return Intrinsic::vastart; // "a_start"
	case 13: // 1 string to match.
	if (memcmp(NameR.data()+0, "ar.annotation", 13))
	break;
	return Intrinsic::var_annotation; // "ar.annotation"
	}
	break; // end of 'v' case.
	case 'x':
	if (NameR.startswith("core.chkct.")) return Intrinsic::xcore_chkct;
	if (NameR.startswith("core.eeu.")) return Intrinsic::xcore_eeu;
	if (NameR.startswith("core.endin.")) return Intrinsic::xcore_endin;
	if (NameR.startswith("core.freer.")) return Intrinsic::xcore_freer;
	if (NameR.startswith("core.getr.")) return Intrinsic::xcore_getr;
	if (NameR.startswith("core.getst.")) return Intrinsic::xcore_getst;
	if (NameR.startswith("core.getts.")) return Intrinsic::xcore_getts;
	if (NameR.startswith("core.in.")) return Intrinsic::xcore_in;
	if (NameR.startswith("core.inct.")) return Intrinsic::xcore_inct;
	if (NameR.startswith("core.initcp.")) return Intrinsic::xcore_initcp;
	if (NameR.startswith("core.initdp.")) return Intrinsic::xcore_initdp;
	if (NameR.startswith("core.initlr.")) return Intrinsic::xcore_initlr;
	if (NameR.startswith("core.initpc.")) return Intrinsic::xcore_initpc;
	if (NameR.startswith("core.initsp.")) return Intrinsic::xcore_initsp;
	if (NameR.startswith("core.inshr.")) return Intrinsic::xcore_inshr;
	if (NameR.startswith("core.int.")) return Intrinsic::xcore_int;
	if (NameR.startswith("core.mjoin.")) return Intrinsic::xcore_mjoin;
	if (NameR.startswith("core.msync.")) return Intrinsic::xcore_msync;
	if (NameR.startswith("core.out.")) return Intrinsic::xcore_out;
	if (NameR.startswith("core.outct.")) return Intrinsic::xcore_outct;
	if (NameR.startswith("core.outshr.")) return Intrinsic::xcore_outshr;
	if (NameR.startswith("core.outt.")) return Intrinsic::xcore_outt;
	if (NameR.startswith("core.peek.")) return Intrinsic::xcore_peek;
	if (NameR.startswith("core.setc.")) return Intrinsic::xcore_setc;
	if (NameR.startswith("core.setclk.")) return Intrinsic::xcore_setclk;
	if (NameR.startswith("core.setd.")) return Intrinsic::xcore_setd;
	if (NameR.startswith("core.setev.")) return Intrinsic::xcore_setev;
	if (NameR.startswith("core.setpsc.")) return Intrinsic::xcore_setpsc;
	if (NameR.startswith("core.setpt.")) return Intrinsic::xcore_setpt;
	if (NameR.startswith("core.setrdy.")) return Intrinsic::xcore_setrdy;
	if (NameR.startswith("core.settw.")) return Intrinsic::xcore_settw;
	if (NameR.startswith("core.setv.")) return Intrinsic::xcore_setv;
	if (NameR.startswith("core.syncr.")) return Intrinsic::xcore_syncr;
	if (NameR.startswith("core.testct.")) return Intrinsic::xcore_testct;
	if (NameR.startswith("core.testwct.")) return Intrinsic::xcore_testwct;
	switch (NameR.size()) {
	default: break;
	case 6: // 1 string to match.
	if (memcmp(NameR.data()+0, "86.int", 6))
	break;
	return Intrinsic::x86_int; // "86.int"
	case 7: // 1 string to match.
	if (memcmp(NameR.data()+0, "86.xend", 7))
	break;
	return Intrinsic::x86_xend; // "86.xend"
	case 8: // 1 string to match.
	if (memcmp(NameR.data()+0, "86.xtest", 8))
	break;
	return Intrinsic::x86_xtest; // "86.xtest"
	case 9: // 6 strings to match.
	switch (NameR[0]) {
	default: break;
	case '8': // 2 strings to match.
	if (memcmp(NameR.data()+1, "6.x", 3))
	break;
	switch (NameR[4]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(NameR.data()+5, "bort", 4))
	break;
	return Intrinsic::x86_xabort; // "86.xabort"
	case 'b': // 1 string to match.
	if (memcmp(NameR.data()+5, "egin", 4))
	break;		break;
	return Intrinsic::x86_xbegin; // "86.xbegin"		switch (NameR[11]) {
	}
	break;
	case 'c': // 4 strings to match.
	if (memcmp(NameR.data()+1, "ore.", 4))
	break;
	switch (NameR[5]) {
	default: break;
	case 'c': // 2 strings to match.
	switch (NameR[6]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+7, "re", 2))		return Intrinsic::nvvm_add_rz_d; // "vvm.add.rz.d"
	break;		case 'f': // 1 string to match.
	return Intrinsic::xcore_clre; // "core.clre"		return Intrinsic::nvvm_add_rz_f; // "vvm.add.rz.f"
	case 'r': // 1 string to match.
	if (memcmp(NameR.data()+7, "c8", 2))
	break;
	return Intrinsic::xcore_crc8; // "core.crc8"
	}		}
	break;		break;
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+6, "ext", 3))
	break;
	return Intrinsic::xcore_sext; // "core.sext"
	case 'z': // 1 string to match.
	if (memcmp(NameR.data()+6, "ext", 3))
	break;
	return Intrinsic::xcore_zext; // "core.zext"
	}		}
	break;		break;
	}		case 'b': // 1 string to match.
	break;		if (memcmp(NameR.data()+5, "arrier0", 7))
	case 10: // 10 strings to match.
	switch (NameR[0]) {
	default: break;
	case '8': // 1 string to match.
	if (memcmp(NameR.data()+1, "6.mmx.por", 9))
	break;
	return Intrinsic::x86_mmx_por; // "86.mmx.por"
	case 'c': // 9 strings to match.
	if (memcmp(NameR.data()+1, "ore.", 4))
	break;		break;
			return Intrinsic::nvvm_barrier0; // "vvm.barrier0"
			case 'd': // 12 strings to match.
	switch (NameR[5]) {		switch (NameR[5]) {
	default: break;		default: break;
	case 'c': // 2 strings to match.		case '2': // 4 strings to match.
	switch (NameR[6]) {		if (memcmp(NameR.data()+6, "ull.r", 5))
			break;
			switch (NameR[11]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'm': // 1 string to match.
	if (memcmp(NameR.data()+7, "rsr", 3))		return Intrinsic::nvvm_d2ull_rm; // "vvm.d2ull.rm"
	break;		case 'n': // 1 string to match.
	return Intrinsic::xcore_clrsr; // "core.clrsr"		return Intrinsic::nvvm_d2ull_rn; // "vvm.d2ull.rn"
	case 'r': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(NameR.data()+7, "c32", 3))		return Intrinsic::nvvm_d2ull_rp; // "vvm.d2ull.rp"
	break;		case 'z': // 1 string to match.
	return Intrinsic::xcore_crc32; // "core.crc32"		return Intrinsic::nvvm_d2ull_rz; // "vvm.d2ull.rz"
	}		}
	break;		break;
	case 'g': // 4 strings to match.		case 'i': // 8 strings to match.
	if (memcmp(NameR.data()+6, "et", 2))		if (memcmp(NameR.data()+6, "v.r", 3))
	break;		break;
	switch (NameR[8]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'e': // 2 strings to match.		case 'm': // 2 strings to match.
	switch (NameR[9]) {		if (NameR[10] != '.')
			break;
			switch (NameR[11]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::xcore_geted; // "core.geted"		return Intrinsic::nvvm_div_rm_d; // "vvm.div.rm.d"
	case 't': // 1 string to match.		case 'f': // 1 string to match.
	return Intrinsic::xcore_getet; // "core.getet"		return Intrinsic::nvvm_div_rm_f; // "vvm.div.rm.f"
	}		}
	break;		break;
	case 'i': // 1 string to match.		case 'n': // 2 strings to match.
	if (NameR[9] != 'd')		if (NameR[10] != '.')
	break;
	return Intrinsic::xcore_getid; // "core.getid"
	case 'p': // 1 string to match.
	if (NameR[9] != 's')
	break;		break;
	return Intrinsic::xcore_getps; // "core.getps"		switch (NameR[11]) {
	}		default: break;
	break;		case 'd': // 1 string to match.
	case 's': // 3 strings to match.		return Intrinsic::nvvm_div_rn_d; // "vvm.div.rn.d"
	switch (NameR[6]) {		case 'f': // 1 string to match.
	default: break;		return Intrinsic::nvvm_div_rn_f; // "vvm.div.rn.f"
	case 'e': // 2 strings to match.		}
	if (NameR[7] != 't')		break;
			case 'p': // 2 strings to match.
			if (NameR[10] != '.')
	break;		break;
	switch (NameR[8]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'd': // 1 string to match.
	if (NameR[9] != 's')		return Intrinsic::nvvm_div_rp_d; // "vvm.div.rp.d"
	break;		case 'f': // 1 string to match.
	return Intrinsic::xcore_setps; // "core.setps"		return Intrinsic::nvvm_div_rp_f; // "vvm.div.rp.f"
	case 's': // 1 string to match.
	if (NameR[9] != 'r')
	break;
	return Intrinsic::xcore_setsr; // "core.setsr"
	}		}
	break;		break;
	case 's': // 1 string to match.		case 'z': // 2 strings to match.
	if (memcmp(NameR.data()+7, "ync", 3))		if (NameR[10] != '.')
	break;		break;
	return Intrinsic::xcore_ssync; // "core.ssync"		switch (NameR[11]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_div_rz_d; // "vvm.div.rz.d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_div_rz_f; // "vvm.div.rz.f"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'f': // 12 strings to match.
	break;		switch (NameR[5]) {
	case 11: // 4 strings to match.
	switch (NameR[0]) {
	default: break;
	case '8': // 3 strings to match.
	if (memcmp(NameR.data()+1, "6.mmx.", 6))
	break;
	switch (NameR[7]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case '2': // 4 strings to match.
	if (memcmp(NameR.data()+8, "mms", 3))		if (memcmp(NameR.data()+6, "ull.r", 5))
	break;		break;
	return Intrinsic::x86_mmx_emms; // "86.mmx.emms"		switch (NameR[11]) {
	case 'p': // 2 strings to match.
	switch (NameR[8]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'm': // 1 string to match.
	if (memcmp(NameR.data()+9, "nd", 2))		return Intrinsic::nvvm_f2ull_rm; // "vvm.f2ull.rm"
	break;		case 'n': // 1 string to match.
	return Intrinsic::x86_mmx_pand; // "86.mmx.pand"		return Intrinsic::nvvm_f2ull_rn; // "vvm.f2ull.rn"
	case 'x': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(NameR.data()+9, "or", 2))		return Intrinsic::nvvm_f2ull_rp; // "vvm.f2ull.rp"
	break;		case 'z': // 1 string to match.
	return Intrinsic::x86_mmx_pxor; // "86.mmx.pxor"		return Intrinsic::nvvm_f2ull_rz; // "vvm.f2ull.rz"
	}		}
	break;		break;
	}		case 'm': // 8 strings to match.
	break;		if (memcmp(NameR.data()+6, "a.r", 3))
	case 'c': // 1 string to match.
	if (memcmp(NameR.data()+1, "ore.bitrev", 10))
	break;
	return Intrinsic::xcore_bitrev; // "core.bitrev"
	}
	break;
	case 12: // 9 strings to match.
	if (memcmp(NameR.data()+0, "86.", 3))
	break;
	switch (NameR[3]) {
	default: break;
	case 'm': // 2 strings to match.
	if (memcmp(NameR.data()+4, "mx.", 3))
	break;
	switch (NameR[7]) {
	default: break;
	case 'f': // 1 string to match.
	if (memcmp(NameR.data()+8, "emms", 4))
	break;
	return Intrinsic::x86_mmx_femms; // "86.mmx.femms"
	case 'p': // 1 string to match.
	if (memcmp(NameR.data()+8, "andn", 4))
	break;
	return Intrinsic::x86_mmx_pandn; // "86.mmx.pandn"
	}
	break;
	case 'p': // 1 string to match.
	if (memcmp(NameR.data()+4, "clmulqdq", 8))
	break;
	return Intrinsic::x86_pclmulqdq; // "86.pclmulqdq"
	case 'r': // 6 strings to match.
	if (NameR[4] != 'd')
	break;
	switch (NameR[5]) {
	default: break;
	case 'r': // 3 strings to match.
	if (memcmp(NameR.data()+6, "and.", 4))
	break;
	switch (NameR[10]) {
	default: break;
	case '1': // 1 string to match.
	if (NameR[11] != '6')
	break;
	return Intrinsic::x86_rdrand_16; // "86.rdrand.16"
	case '3': // 1 string to match.
	if (NameR[11] != '2')
	break;
	return Intrinsic::x86_rdrand_32; // "86.rdrand.32"
	case '6': // 1 string to match.
	if (NameR[11] != '4')
	break;
	return Intrinsic::x86_rdrand_64; // "86.rdrand.64"
	}
	break;
	case 's': // 3 strings to match.
	if (memcmp(NameR.data()+6, "eed.", 4))
	break;		break;
	switch (NameR[10]) {
	default: break;
	case '1': // 1 string to match.
	if (NameR[11] != '6')
	break;
	return Intrinsic::x86_rdseed_16; // "86.rdseed.16"
	case '3': // 1 string to match.
	if (NameR[11] != '2')
	break;
	return Intrinsic::x86_rdseed_32; // "86.rdseed.32"
	case '6': // 1 string to match.
	if (NameR[11] != '4')
	break;
	return Intrinsic::x86_rdseed_64; // "86.rdseed.64"
	}
	break;
	}
	break;
	}
	break;
	case 13: // 53 strings to match.
	if (memcmp(NameR.data()+0, "86.", 3))
	break;
	switch (NameR[3]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(NameR.data()+4, "vx2.permd", 9))
	break;
	return Intrinsic::x86_avx2_permd; // "86.avx2.permd"
	case 'm': // 18 strings to match.
	if (memcmp(NameR.data()+4, "mx.p", 4))
	break;
	switch (NameR[8]) {
	default: break;
	case 'a': // 6 strings to match.
	switch (NameR[9]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'd': // 4 strings to match.		case 'm': // 2 strings to match.
	if (memcmp(NameR.data()+10, "d.", 2))		if (NameR[10] != '.')
	break;		break;
	switch (NameR[12]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'b': // 1 string to match.
	return Intrinsic::x86_mmx_padd_b; // "86.mmx.padd.b"
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::x86_mmx_padd_d; // "86.mmx.padd.d"		return Intrinsic::nvvm_fma_rm_d; // "vvm.fma.rm.d"
	case 'q': // 1 string to match.		case 'f': // 1 string to match.
	return Intrinsic::x86_mmx_padd_q; // "86.mmx.padd.q"		return Intrinsic::nvvm_fma_rm_f; // "vvm.fma.rm.f"
	case 'w': // 1 string to match.
	return Intrinsic::x86_mmx_padd_w; // "86.mmx.padd.w"
	}		}
	break;		break;
	case 'v': // 2 strings to match.		case 'n': // 2 strings to match.
	if (memcmp(NameR.data()+10, "g.", 2))		if (NameR[10] != '.')
	break;		break;
	switch (NameR[12]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::x86_mmx_pavg_b; // "86.mmx.pavg.b"		return Intrinsic::nvvm_fma_rn_d; // "vvm.fma.rn.d"
	case 'w': // 1 string to match.		case 'f': // 1 string to match.
	return Intrinsic::x86_mmx_pavg_w; // "86.mmx.pavg.w"		return Intrinsic::nvvm_fma_rn_f; // "vvm.fma.rn.f"
	}		}
	break;		break;
	}		case 'p': // 2 strings to match.
	break;		if (NameR[10] != '.')
	case 's': // 12 strings to match.
	switch (NameR[9]) {
	default: break;
	case 'l': // 3 strings to match.
	if (memcmp(NameR.data()+10, "l.", 2))
	break;		break;
	switch (NameR[12]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::x86_mmx_psll_d; // "86.mmx.psll.d"		return Intrinsic::nvvm_fma_rp_d; // "vvm.fma.rp.d"
	case 'q': // 1 string to match.		case 'f': // 1 string to match.
	return Intrinsic::x86_mmx_psll_q; // "86.mmx.psll.q"		return Intrinsic::nvvm_fma_rp_f; // "vvm.fma.rp.f"
	case 'w': // 1 string to match.
	return Intrinsic::x86_mmx_psll_w; // "86.mmx.psll.w"
	}
	break;
	case 'r': // 5 strings to match.
	switch (NameR[10]) {
	default: break;
	case 'a': // 2 strings to match.
	if (NameR[11] != '.')
	break;
	switch (NameR[12]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_mmx_psra_d; // "86.mmx.psra.d"
	case 'w': // 1 string to match.
	return Intrinsic::x86_mmx_psra_w; // "86.mmx.psra.w"
	}
	break;
	case 'l': // 3 strings to match.
	if (NameR[11] != '.')
	break;
	switch (NameR[12]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_mmx_psrl_d; // "86.mmx.psrl.d"
	case 'q': // 1 string to match.
	return Intrinsic::x86_mmx_psrl_q; // "86.mmx.psrl.q"
	case 'w': // 1 string to match.
	return Intrinsic::x86_mmx_psrl_w; // "86.mmx.psrl.w"
	}
	break;
	}		}
	break;		break;
	case 'u': // 4 strings to match.		case 'z': // 2 strings to match.
	if (memcmp(NameR.data()+10, "b.", 2))		if (NameR[10] != '.')
	break;		break;
	switch (NameR[12]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'b': // 1 string to match.
	return Intrinsic::x86_mmx_psub_b; // "86.mmx.psub.b"
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::x86_mmx_psub_d; // "86.mmx.psub.d"		return Intrinsic::nvvm_fma_rz_d; // "vvm.fma.rz.d"
	case 'q': // 1 string to match.		case 'f': // 1 string to match.
	return Intrinsic::x86_mmx_psub_q; // "86.mmx.psub.q"		return Intrinsic::nvvm_fma_rz_f; // "vvm.fma.rz.f"
	case 'w': // 1 string to match.
	return Intrinsic::x86_mmx_psub_w; // "86.mmx.psub.w"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 's': // 16 strings to match.		case 'l': // 1 string to match.
	if (memcmp(NameR.data()+4, "se", 2))		if (memcmp(NameR.data()+5, "ohi.i2d", 7))
	break;		break;
	switch (NameR[6]) {		return Intrinsic::nvvm_lohi_i2d; // "vvm.lohi.i2d"
			case 'm': // 14 strings to match.
			switch (NameR[5]) {
	default: break;		default: break;
	case '.': // 13 strings to match.		case 'o': // 3 strings to match.
	switch (NameR[7]) {		if (memcmp(NameR.data()+6, "ve.i", 4))
			break;
			switch (NameR[10]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(NameR.data()+8, "dd.ss", 5))		if (NameR[11] != '6')
	break;		break;
	return Intrinsic::x86_sse_add_ss; // "86.sse.add.ss"		return Intrinsic::nvvm_move_i16; // "vvm.move.i16"
	case 'c': // 2 strings to match.		case '3': // 1 string to match.
	if (memcmp(NameR.data()+8, "mp.", 3))		if (NameR[11] != '2')
	break;		break;
	switch (NameR[11]) {		return Intrinsic::nvvm_move_i32; // "vvm.move.i32"
	default: break;		case '6': // 1 string to match.
	case 'p': // 1 string to match.		if (NameR[11] != '4')
	if (NameR[12] != 's')		break;
	break;		return Intrinsic::nvvm_move_i64; // "vvm.move.i64"
	return Intrinsic::x86_sse_cmp_ps; // "86.sse.cmp.ps"		}
	case 's': // 1 string to match.		break;
	if (NameR[12] != 's')		case 'u': // 11 strings to match.
	break;		if (NameR[6] != 'l')
	return Intrinsic::x86_sse_cmp_ss; // "86.sse.cmp.ss"
	}
	break;		break;
	case 'd': // 1 string to match.		switch (NameR[7]) {
	if (memcmp(NameR.data()+8, "iv.ss", 5))		default: break;
			case '.': // 8 strings to match.
			if (NameR[8] != 'r')
	break;		break;
	return Intrinsic::x86_sse_div_ss; // "86.sse.div.ss"		switch (NameR[9]) {
	case 'm': // 5 strings to match.
	switch (NameR[8]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'm': // 2 strings to match.
	if (memcmp(NameR.data()+9, "x.", 2))		if (NameR[10] != '.')
	break;		break;
	switch (NameR[11]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'd': // 1 string to match.
	if (NameR[12] != 's')		return Intrinsic::nvvm_mul_rm_d; // "vvm.mul.rm.d"
	break;		case 'f': // 1 string to match.
	return Intrinsic::x86_sse_max_ps; // "86.sse.max.ps"		return Intrinsic::nvvm_mul_rm_f; // "vvm.mul.rm.f"
	case 's': // 1 string to match.
	if (NameR[12] != 's')
	break;
	return Intrinsic::x86_sse_max_ss; // "86.sse.max.ss"
	}		}
	break;		break;
	case 'i': // 2 strings to match.		case 'n': // 2 strings to match.
	if (memcmp(NameR.data()+9, "n.", 2))		if (NameR[10] != '.')
	break;		break;
	switch (NameR[11]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'd': // 1 string to match.
	if (NameR[12] != 's')		return Intrinsic::nvvm_mul_rn_d; // "vvm.mul.rn.d"
	break;		case 'f': // 1 string to match.
	return Intrinsic::x86_sse_min_ps; // "86.sse.min.ps"		return Intrinsic::nvvm_mul_rn_f; // "vvm.mul.rn.f"
	case 's': // 1 string to match.
	if (NameR[12] != 's')
	break;
	return Intrinsic::x86_sse_min_ss; // "86.sse.min.ss"
	}		}
	break;		break;
	case 'u': // 1 string to match.		case 'p': // 2 strings to match.
	if (memcmp(NameR.data()+9, "l.ss", 4))		if (NameR[10] != '.')
	break;		break;
	return Intrinsic::x86_sse_mul_ss; // "86.sse.mul.ss"		switch (NameR[11]) {
	}		default: break;
	break;		case 'd': // 1 string to match.
	case 'r': // 2 strings to match.		return Intrinsic::nvvm_mul_rp_d; // "vvm.mul.rp.d"
	if (memcmp(NameR.data()+8, "cp.", 3))		case 'f': // 1 string to match.
			return Intrinsic::nvvm_mul_rp_f; // "vvm.mul.rp.f"
			}
	break;		break;
	switch (NameR[11]) {		case 'z': // 2 strings to match.
	default: break;		if (NameR[10] != '.')
	case 'p': // 1 string to match.
	if (NameR[12] != 's')
	break;
	return Intrinsic::x86_sse_rcp_ps; // "86.sse.rcp.ps"
	case 's': // 1 string to match.
	if (NameR[12] != 's')
	break;		break;
	return Intrinsic::x86_sse_rcp_ss; // "86.sse.rcp.ss"		switch (NameR[11]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_mul_rz_d; // "vvm.mul.rz.d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_mul_rz_f; // "vvm.mul.rz.f"
			}
			break;
	}		}
	break;		break;
	case 's': // 2 strings to match.		case '2': // 1 string to match.
	switch (NameR[8]) {		if (memcmp(NameR.data()+8, "4.ui", 4))
			break;
			return Intrinsic::nvvm_mul24_ui; // "vvm.mul24.ui"
			case 'h': // 2 strings to match.
			if (memcmp(NameR.data()+8, "i.", 2))
			break;
			switch (NameR[10]) {
	default: break;		default: break;
	case 'f': // 1 string to match.		case 'l': // 1 string to match.
	if (memcmp(NameR.data()+9, "ence", 4))		if (NameR[11] != 'l')
	break;		break;
	return Intrinsic::x86_sse_sfence; // "86.sse.sfence"		return Intrinsic::nvvm_mulhi_ll; // "vvm.mulhi.ll"
	case 'u': // 1 string to match.		case 'u': // 1 string to match.
	if (memcmp(NameR.data()+9, "b.ss", 4))		if (NameR[11] != 'i')
	break;		break;
	return Intrinsic::x86_sse_sub_ss; // "86.sse.sub.ss"		return Intrinsic::nvvm_mulhi_ui; // "vvm.mulhi.ui"
	}		}
	break;		break;
	}		}
	break;		break;
	case '3': // 1 string to match.		}
	if (memcmp(NameR.data()+7, ".mwait", 6))		break;
			case 'r': // 8 strings to match.
			if (memcmp(NameR.data()+5, "cp.r", 4))
			break;
			switch (NameR[9]) {
			default: break;
			case 'm': // 2 strings to match.
			if (NameR[10] != '.')
	break;		break;
	return Intrinsic::x86_sse3_mwait; // "86.sse3.mwait"		switch (NameR[11]) {
	case '4': // 2 strings to match.		default: break;
	if (memcmp(NameR.data()+7, "1.dpp", 5))		case 'd': // 1 string to match.
			return Intrinsic::nvvm_rcp_rm_d; // "vvm.rcp.rm.d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_rcp_rm_f; // "vvm.rcp.rm.f"
			}
			break;
			case 'n': // 2 strings to match.
			if (NameR[10] != '.')
	break;		break;
	switch (NameR[12]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_dppd; // "86.sse41.dppd"		return Intrinsic::nvvm_rcp_rn_d; // "vvm.rcp.rn.d"
	case 's': // 1 string to match.		case 'f': // 1 string to match.
	return Intrinsic::x86_sse41_dpps; // "86.sse41.dpps"		return Intrinsic::nvvm_rcp_rn_f; // "vvm.rcp.rn.f"
			}
			break;
			case 'p': // 2 strings to match.
			if (NameR[10] != '.')
			break;
			switch (NameR[11]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_rcp_rp_d; // "vvm.rcp.rp.d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_rcp_rp_f; // "vvm.rcp.rp.f"
			}
			break;
			case 'z': // 2 strings to match.
			if (NameR[10] != '.')
			break;
			switch (NameR[11]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_rcp_rz_d; // "vvm.rcp.rz.d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_rcp_rz_f; // "vvm.rcp.rz.f"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'x': // 18 strings to match.		case 'u': // 8 strings to match.
	if (memcmp(NameR.data()+4, "op.vp", 5))		if (memcmp(NameR.data()+5, "ll2", 3))
	break;		break;
	switch (NameR[9]) {		switch (NameR[8]) {
	default: break;		default: break;
	case 'c': // 5 strings to match.		case 'd': // 4 strings to match.
	switch (NameR[10]) {		if (memcmp(NameR.data()+9, ".r", 2))
			break;
			switch (NameR[11]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'm': // 1 string to match.
	if (memcmp(NameR.data()+11, "ov", 2))		return Intrinsic::nvvm_ull2d_rm; // "vvm.ull2d.rm"
	break;		case 'n': // 1 string to match.
	return Intrinsic::x86_xop_vpcmov; // "86.xop.vpcmov"		return Intrinsic::nvvm_ull2d_rn; // "vvm.ull2d.rn"
	case 'o': // 4 strings to match.		case 'p': // 1 string to match.
	if (NameR[11] != 'm')		return Intrinsic::nvvm_ull2d_rp; // "vvm.ull2d.rp"
	break;		case 'z': // 1 string to match.
	switch (NameR[12]) {		return Intrinsic::nvvm_ull2d_rz; // "vvm.ull2d.rz"
	default: break;		}
	case 'b': // 1 string to match.		break;
	return Intrinsic::x86_xop_vpcomb; // "86.xop.vpcomb"		case 'f': // 4 strings to match.
	case 'd': // 1 string to match.		if (memcmp(NameR.data()+9, ".r", 2))
	return Intrinsic::x86_xop_vpcomd; // "86.xop.vpcomd"
	case 'q': // 1 string to match.
	return Intrinsic::x86_xop_vpcomq; // "86.xop.vpcomq"
	case 'w': // 1 string to match.
	return Intrinsic::x86_xop_vpcomw; // "86.xop.vpcomw"
	}
	break;		break;
			switch (NameR[11]) {
			default: break;
			case 'm': // 1 string to match.
			return Intrinsic::nvvm_ull2f_rm; // "vvm.ull2f.rm"
			case 'n': // 1 string to match.
			return Intrinsic::nvvm_ull2f_rn; // "vvm.ull2f.rn"
			case 'p': // 1 string to match.
			return Intrinsic::nvvm_ull2f_rp; // "vvm.ull2f.rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_ull2f_rz; // "vvm.ull2f.rz"
	}		}
	break;		break;
	case 'p': // 1 string to match.		}
	if (memcmp(NameR.data()+10, "erm", 3))		break;
			}
			break;
			case 13: // 10 strings to match.
			if (memcmp(NameR.data()+0, "vvm.", 4))
			break;
			switch (NameR[4]) {
			default: break;
			case 'm': // 2 strings to match.
			switch (NameR[5]) {
			default: break;
			case 'e': // 1 string to match.
			if (memcmp(NameR.data()+6, "mbar.gl", 7))
	break;		break;
	return Intrinsic::x86_xop_vpperm; // "86.xop.vpperm"		return Intrinsic::nvvm_membar_gl; // "vvm.membar.gl"
	case 'r': // 4 strings to match.		case 'u': // 1 string to match.
	if (memcmp(NameR.data()+10, "ot", 2))		if (memcmp(NameR.data()+6, "lhi.ull", 7))
			break;
			return Intrinsic::nvvm_mulhi_ull; // "vvm.mulhi.ull"
			}
			break;
			case 's': // 8 strings to match.
			if (memcmp(NameR.data()+5, "qrt.r", 5))
			break;
			switch (NameR[10]) {
			default: break;
			case 'm': // 2 strings to match.
			if (NameR[11] != '.')
	break;		break;
	switch (NameR[12]) {		switch (NameR[12]) {
	default: break;		default: break;
	case 'b': // 1 string to match.
	return Intrinsic::x86_xop_vprotb; // "86.xop.vprotb"
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::x86_xop_vprotd; // "86.xop.vprotd"		return Intrinsic::nvvm_sqrt_rm_d; // "vvm.sqrt.rm.d"
	case 'q': // 1 string to match.		case 'f': // 1 string to match.
	return Intrinsic::x86_xop_vprotq; // "86.xop.vprotq"		return Intrinsic::nvvm_sqrt_rm_f; // "vvm.sqrt.rm.f"
	case 'w': // 1 string to match.
	return Intrinsic::x86_xop_vprotw; // "86.xop.vprotw"
	}		}
	break;		break;
	case 's': // 8 strings to match.		case 'n': // 2 strings to match.
	if (NameR[10] != 'h')		if (NameR[11] != '.')
	break;		break;
	switch (NameR[11]) {		switch (NameR[12]) {
	default: break;		default: break;
	case 'a': // 4 strings to match.		case 'd': // 1 string to match.
	switch (NameR[12]) {		return Intrinsic::nvvm_sqrt_rn_d; // "vvm.sqrt.rn.d"
	default: break;		case 'f': // 1 string to match.
	case 'b': // 1 string to match.		return Intrinsic::nvvm_sqrt_rn_f; // "vvm.sqrt.rn.f"
	return Intrinsic::x86_xop_vpshab; // "86.xop.vpshab"		}
	case 'd': // 1 string to match.		break;
	return Intrinsic::x86_xop_vpshad; // "86.xop.vpshad"		case 'p': // 2 strings to match.
	case 'q': // 1 string to match.		if (NameR[11] != '.')
	return Intrinsic::x86_xop_vpshaq; // "86.xop.vpshaq"
	case 'w': // 1 string to match.
	return Intrinsic::x86_xop_vpshaw; // "86.xop.vpshaw"
	}
	break;		break;
	case 'l': // 4 strings to match.		switch (NameR[12]) {
	switch (NameR[12]) {		default: break;
	default: break;		case 'd': // 1 string to match.
	case 'b': // 1 string to match.		return Intrinsic::nvvm_sqrt_rp_d; // "vvm.sqrt.rp.d"
	return Intrinsic::x86_xop_vpshlb; // "86.xop.vpshlb"		case 'f': // 1 string to match.
	case 'd': // 1 string to match.		return Intrinsic::nvvm_sqrt_rp_f; // "vvm.sqrt.rp.f"
	return Intrinsic::x86_xop_vpshld; // "86.xop.vpshld"		}
	case 'q': // 1 string to match.		break;
	return Intrinsic::x86_xop_vpshlq; // "86.xop.vpshlq"		case 'z': // 2 strings to match.
	case 'w': // 1 string to match.		if (NameR[11] != '.')
	return Intrinsic::x86_xop_vpshlw; // "86.xop.vpshlw"
	}
	break;		break;
			switch (NameR[12]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_sqrt_rz_d; // "vvm.sqrt.rz.d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_sqrt_rz_f; // "vvm.sqrt.rz.f"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 14: // 96 strings to match.		case 14: // 18 strings to match.
	switch (NameR[0]) {		if (memcmp(NameR.data()+0, "vvm.", 4))
			break;
			switch (NameR[4]) {
	default: break;		default: break;
	case '8': // 95 strings to match.		case 'c': // 1 string to match.
	if (memcmp(NameR.data()+1, "6.", 2))		if (memcmp(NameR.data()+5, "eil.ftz.f", 9))
	break;		break;
	switch (NameR[3]) {		return Intrinsic::nvvm_ceil_ftz_f; // "vvm.ceil.ftz.f"
	default: break;		case 'd': // 4 strings to match.
	case '3': // 9 strings to match.		if (memcmp(NameR.data()+5, "2f.r", 4))
	if (memcmp(NameR.data()+4, "dnow.p", 6))		break;
			switch (NameR[9]) {
			default: break;
			case 'm': // 1 string to match.
			if (memcmp(NameR.data()+10, ".ftz", 4))
	break;		break;
	switch (NameR[10]) {		return Intrinsic::nvvm_d2f_rm_ftz; // "vvm.d2f.rm.ftz"
	default: break;		case 'n': // 1 string to match.
	case 'f': // 8 strings to match.		if (memcmp(NameR.data()+10, ".ftz", 4))
	switch (NameR[11]) {
	default: break;
	case '2': // 1 string to match.
	if (memcmp(NameR.data()+12, "id", 2))
	break;
	return Intrinsic::x86_3dnow_pf2id; // "86.3dnow.pf2id"
	case 'a': // 2 strings to match.
	switch (NameR[12]) {
	default: break;
	case 'c': // 1 string to match.
	if (NameR[13] != 'c')
	break;
	return Intrinsic::x86_3dnow_pfacc; // "86.3dnow.pfacc"
	case 'd': // 1 string to match.
	if (NameR[13] != 'd')
	break;
	return Intrinsic::x86_3dnow_pfadd; // "86.3dnow.pfadd"
	}
	break;
	case 'm': // 3 strings to match.
	switch (NameR[12]) {
	default: break;
	case 'a': // 1 string to match.
	if (NameR[13] != 'x')
	break;
	return Intrinsic::x86_3dnow_pfmax; // "86.3dnow.pfmax"
	case 'i': // 1 string to match.
	if (NameR[13] != 'n')
	break;
	return Intrinsic::x86_3dnow_pfmin; // "86.3dnow.pfmin"
	case 'u': // 1 string to match.
	if (NameR[13] != 'l')
	break;
	return Intrinsic::x86_3dnow_pfmul; // "86.3dnow.pfmul"
	}
	break;
	case 'r': // 1 string to match.
	if (memcmp(NameR.data()+12, "cp", 2))
	break;
	return Intrinsic::x86_3dnow_pfrcp; // "86.3dnow.pfrcp"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+12, "ub", 2))
	break;
	return Intrinsic::x86_3dnow_pfsub; // "86.3dnow.pfsub"
	}
	break;		break;
	case 'i': // 1 string to match.		return Intrinsic::nvvm_d2f_rn_ftz; // "vvm.d2f.rn.ftz"
	if (memcmp(NameR.data()+11, "2fd", 3))		case 'p': // 1 string to match.
	break;		if (memcmp(NameR.data()+10, ".ftz", 4))
	return Intrinsic::x86_3dnow_pi2fd; // "86.3dnow.pi2fd"
	}
	break;
	case 'a': // 14 strings to match.
	if (memcmp(NameR.data()+4, "vx2.p", 5))
	break;		break;
	switch (NameR[9]) {		return Intrinsic::nvvm_d2f_rp_ftz; // "vvm.d2f.rp.ftz"
			case 'z': // 1 string to match.
			if (memcmp(NameR.data()+10, ".ftz", 4))
			break;
			return Intrinsic::nvvm_d2f_rz_ftz; // "vvm.d2f.rz.ftz"
			}
			break;
			case 'f': // 8 strings to match.
			switch (NameR[5]) {
			default: break;
			case '2': // 5 strings to match.
			switch (NameR[6]) {
	default: break;		default: break;
	case 'a': // 5 strings to match.		case 'h': // 1 string to match.
	switch (NameR[10]) {		if (memcmp(NameR.data()+7, ".rn.ftz", 7))
	default: break;
	case 'b': // 3 strings to match.
	if (memcmp(NameR.data()+11, "s.", 2))
	break;
	switch (NameR[13]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::x86_avx2_pabs_b; // "86.avx2.pabs.b"
	case 'd': // 1 string to match.
	return Intrinsic::x86_avx2_pabs_d; // "86.avx2.pabs.d"
	case 'w': // 1 string to match.
	return Intrinsic::x86_avx2_pabs_w; // "86.avx2.pabs.w"
	}
	break;
	case 'v': // 2 strings to match.
	if (memcmp(NameR.data()+11, "g.", 2))
	break;
	switch (NameR[13]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::x86_avx2_pavg_b; // "86.avx2.pavg.b"
	case 'w': // 1 string to match.
	return Intrinsic::x86_avx2_pavg_w; // "86.avx2.pavg.w"
	}
	break;		break;
	}		return Intrinsic::nvvm_f2h_rn_ftz; // "vvm.f2h.rn.ftz"
	break;		case 'i': // 4 strings to match.
	case 'e': // 1 string to match.		if (memcmp(NameR.data()+7, ".r", 2))
	if (memcmp(NameR.data()+10, "rmps", 4))
	break;		break;
	return Intrinsic::x86_avx2_permps; // "86.avx2.permps"		switch (NameR[9]) {
	case 's': // 8 strings to match.
	switch (NameR[10]) {
	default: break;		default: break;
	case 'l': // 3 strings to match.		case 'm': // 1 string to match.
	if (memcmp(NameR.data()+11, "l.", 2))		if (memcmp(NameR.data()+10, ".ftz", 4))
	break;		break;
	switch (NameR[13]) {		return Intrinsic::nvvm_f2i_rm_ftz; // "vvm.f2i.rm.ftz"
	default: break;		case 'n': // 1 string to match.
	case 'd': // 1 string to match.		if (memcmp(NameR.data()+10, ".ftz", 4))
	return Intrinsic::x86_avx2_psll_d; // "86.avx2.psll.d"
	case 'q': // 1 string to match.
	return Intrinsic::x86_avx2_psll_q; // "86.avx2.psll.q"
	case 'w': // 1 string to match.
	return Intrinsic::x86_avx2_psll_w; // "86.avx2.psll.w"
	}
	break;
	case 'r': // 5 strings to match.
	switch (NameR[11]) {
	default: break;
	case 'a': // 2 strings to match.
	if (NameR[12] != '.')
	break;
	switch (NameR[13]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_avx2_psra_d; // "86.avx2.psra.d"
	case 'w': // 1 string to match.
	return Intrinsic::x86_avx2_psra_w; // "86.avx2.psra.w"
	}
	break;		break;
	case 'l': // 3 strings to match.		return Intrinsic::nvvm_f2i_rn_ftz; // "vvm.f2i.rn.ftz"
	if (NameR[12] != '.')		case 'p': // 1 string to match.
	break;		if (memcmp(NameR.data()+10, ".ftz", 4))
	switch (NameR[13]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_avx2_psrl_d; // "86.avx2.psrl.d"
	case 'q': // 1 string to match.
	return Intrinsic::x86_avx2_psrl_q; // "86.avx2.psrl.q"
	case 'w': // 1 string to match.
	return Intrinsic::x86_avx2_psrl_w; // "86.avx2.psrl.w"
	}
	break;		break;
	}		return Intrinsic::nvvm_f2i_rp_ftz; // "vvm.f2i.rp.ftz"
	break;		case 'z': // 1 string to match.
			if (memcmp(NameR.data()+10, ".ftz", 4))
			break;
			return Intrinsic::nvvm_f2i_rz_ftz; // "vvm.f2i.rz.ftz"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'b': // 6 strings to match.		case 'a': // 1 string to match.
	if (memcmp(NameR.data()+4, "mi.", 3))		if (memcmp(NameR.data()+6, "bs.ftz.f", 8))
	break;		break;
	switch (NameR[7]) {		return Intrinsic::nvvm_fabs_ftz_f; // "vvm.fabs.ftz.f"
			case 'm': // 2 strings to match.
			switch (NameR[6]) {
	default: break;		default: break;
	case 'b': // 2 strings to match.		case 'a': // 1 string to match.
	if (memcmp(NameR.data()+8, "zhi.", 4))		if (memcmp(NameR.data()+7, "x.ftz.f", 7))
	break;
	switch (NameR[12]) {
	default: break;
	case '3': // 1 string to match.
	if (NameR[13] != '2')
	break;
	return Intrinsic::x86_bmi_bzhi_32; // "86.bmi.bzhi.32"
	case '6': // 1 string to match.
	if (NameR[13] != '4')
	break;
	return Intrinsic::x86_bmi_bzhi_64; // "86.bmi.bzhi.64"
	}
	break;
	case 'p': // 4 strings to match.
	switch (NameR[8]) {
	default: break;
	case 'd': // 2 strings to match.
	if (memcmp(NameR.data()+9, "ep.", 3))
	break;
	switch (NameR[12]) {
	default: break;
	case '3': // 1 string to match.
	if (NameR[13] != '2')
	break;
	return Intrinsic::x86_bmi_pdep_32; // "86.bmi.pdep.32"
	case '6': // 1 string to match.
	if (NameR[13] != '4')
	break;
	return Intrinsic::x86_bmi_pdep_64; // "86.bmi.pdep.64"
	}
	break;		break;
	case 'e': // 2 strings to match.		return Intrinsic::nvvm_fmax_ftz_f; // "vvm.fmax.ftz.f"
	if (memcmp(NameR.data()+9, "xt.", 3))		case 'i': // 1 string to match.
	break;		if (memcmp(NameR.data()+7, "n.ftz.f", 7))
	switch (NameR[12]) {
	default: break;
	case '3': // 1 string to match.
	if (NameR[13] != '2')
	break;
	return Intrinsic::x86_bmi_pext_32; // "86.bmi.pext.32"
	case '6': // 1 string to match.
	if (NameR[13] != '4')
	break;
	return Intrinsic::x86_bmi_pext_64; // "86.bmi.pext.64"
	}
	break;		break;
	}		return Intrinsic::nvvm_fmin_ftz_f; // "vvm.fmin.ftz.f"
	break;
	}		}
	break;		break;
	case 'm': // 21 strings to match.		}
	if (memcmp(NameR.data()+4, "mx.p", 4))		break;
			case 'm': // 3 strings to match.
			switch (NameR[5]) {
			default: break;
			case 'e': // 2 strings to match.
			if (memcmp(NameR.data()+6, "mbar.", 5))
	break;		break;
	switch (NameR[8]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'c': // 1 string to match.
	if (memcmp(NameR.data()+9, "dds.", 4))		if (memcmp(NameR.data()+12, "ta", 2))
	break;		break;
	switch (NameR[13]) {		return Intrinsic::nvvm_membar_cta; // "vvm.membar.cta"
	default: break;		case 's': // 1 string to match.
	case 'b': // 1 string to match.		if (memcmp(NameR.data()+12, "ys", 2))
	return Intrinsic::x86_mmx_padds_b; // "86.mmx.padds.b"		break;
	case 'w': // 1 string to match.		return Intrinsic::nvvm_membar_sys; // "vvm.membar.sys"
	return Intrinsic::x86_mmx_padds_w; // "86.mmx.padds.w"		}
	}		break;
			case 'o': // 1 string to match.
			if (memcmp(NameR.data()+6, "ve.float", 8))
	break;		break;
	case 'e': // 1 string to match.		return Intrinsic::nvvm_move_float; // "vvm.move.float"
	if (memcmp(NameR.data()+9, "xtr.w", 5))		}
			break;
			case 's': // 2 strings to match.
			if (memcmp(NameR.data()+5, "aturate.", 8))
			break;
			switch (NameR[13]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_saturate_d; // "vvm.saturate.d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_saturate_f; // "vvm.saturate.f"
			}
			break;
			}
			break;
			case 15: // 15 strings to match.
			if (memcmp(NameR.data()+0, "vvm.", 4))
			break;
			switch (NameR[4]) {
			default: break;
			case 'b': // 3 strings to match.
			switch (NameR[5]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(NameR.data()+6, "rrier0.or", 9))
			break;
			return Intrinsic::nvvm_barrier0_or; // "vvm.barrier0.or"
			case 'i': // 2 strings to match.
			if (memcmp(NameR.data()+6, "tcast.", 6))
			break;
			switch (NameR[12]) {
			default: break;
			case 'f': // 1 string to match.
			if (memcmp(NameR.data()+13, "2i", 2))
	break;		break;
	return Intrinsic::x86_mmx_pextr_w; // "86.mmx.pextr.w"		return Intrinsic::nvvm_bitcast_f2i; // "vvm.bitcast.f2i "
	case 'i': // 1 string to match.		case 'i': // 1 string to match.
	if (memcmp(NameR.data()+9, "nsr.w", 5))		if (memcmp(NameR.data()+13, "2f", 2))
	break;
	return Intrinsic::x86_mmx_pinsr_w; // "86.mmx.pinsr.w"
	case 'm': // 6 strings to match.
	switch (NameR[9]) {
	default: break;
	case 'a': // 2 strings to match.
	if (NameR[10] != 'x')
	break;
	switch (NameR[11]) {
	default: break;
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+12, ".w", 2))
	break;
	return Intrinsic::x86_mmx_pmaxs_w; // "86.mmx.pmaxs.w"
	case 'u': // 1 string to match.
	if (memcmp(NameR.data()+12, ".b", 2))
	break;
	return Intrinsic::x86_mmx_pmaxu_b; // "86.mmx.pmaxu.b"
	}
	break;
	case 'i': // 2 strings to match.
	if (NameR[10] != 'n')
	break;
	switch (NameR[11]) {
	default: break;
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+12, ".w", 2))
	break;
	return Intrinsic::x86_mmx_pmins_w; // "86.mmx.pmins.w"
	case 'u': // 1 string to match.
	if (memcmp(NameR.data()+12, ".b", 2))
	break;
	return Intrinsic::x86_mmx_pminu_b; // "86.mmx.pminu.b"
	}
	break;		break;
	case 'u': // 2 strings to match.		return Intrinsic::nvvm_bitcast_i2f; // "vvm.bitcast.i2f
	if (NameR[10] != 'l')		"
	break;		}
	switch (NameR[11]) {		break;
	default: break;		}
	case 'h': // 1 string to match.		break;
	if (memcmp(NameR.data()+12, ".w", 2))		case 'f': // 9 strings to match.
	break;		switch (NameR[5]) {
	return Intrinsic::x86_mmx_pmulh_w; // "86.mmx.pmulh.w"		default: break;
	case 'l': // 1 string to match.		case '2': // 8 strings to match.
	if (memcmp(NameR.data()+12, ".w", 2))		switch (NameR[6]) {
	break;		default: break;
	return Intrinsic::x86_mmx_pmull_w; // "86.mmx.pmull.w"		case 'l': // 4 strings to match.
	}		if (memcmp(NameR.data()+7, "l.r", 3))
	break;		break;
	}		switch (NameR[10]) {
	break;
	case 's': // 11 strings to match.
	switch (NameR[9]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'm': // 1 string to match.
	if (memcmp(NameR.data()+10, "d.bw", 4))		if (memcmp(NameR.data()+11, ".ftz", 4))
	break;
	return Intrinsic::x86_mmx_psad_bw; // "86.mmx.psad.bw"
	case 'l': // 3 strings to match.
	if (memcmp(NameR.data()+10, "li.", 3))
	break;		break;
	switch (NameR[13]) {		return Intrinsic::nvvm_f2ll_rm_ftz; // "vvm.f2ll.rm.ftz
	default: break;		"
	case 'd': // 1 string to match.		case 'n': // 1 string to match.
	return Intrinsic::x86_mmx_pslli_d; // "86.mmx.pslli.d"		if (memcmp(NameR.data()+11, ".ftz", 4))
	case 'q': // 1 string to match.
	return Intrinsic::x86_mmx_pslli_q; // "86.mmx.pslli.q"
	case 'w': // 1 string to match.
	return Intrinsic::x86_mmx_pslli_w; // "86.mmx.pslli.w"
	}
	break;
	case 'r': // 5 strings to match.
	switch (NameR[10]) {
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(NameR.data()+11, "i.", 2))
	break;
	switch (NameR[13]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_mmx_psrai_d; // "86.mmx.psrai.d"
	case 'w': // 1 string to match.
	return Intrinsic::x86_mmx_psrai_w; // "86.mmx.psrai.w"
	}
	break;		break;
	case 'l': // 3 strings to match.		return Intrinsic::nvvm_f2ll_rn_ftz; // "vvm.f2ll.rn.ftz
	if (memcmp(NameR.data()+11, "i.", 2))		"
	break;		case 'p': // 1 string to match.
	switch (NameR[13]) {		if (memcmp(NameR.data()+11, ".ftz", 4))
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_mmx_psrli_d; // "86.mmx.psrli.d"
	case 'q': // 1 string to match.
	return Intrinsic::x86_mmx_psrli_q; // "86.mmx.psrli.q"
	case 'w': // 1 string to match.
	return Intrinsic::x86_mmx_psrli_w; // "86.mmx.psrli.w"
	}
	break;		break;
	}		return Intrinsic::nvvm_f2ll_rp_ftz; // "vvm.f2ll.rp.ftz
	break;		"
	case 'u': // 2 strings to match.		case 'z': // 1 string to match.
	if (memcmp(NameR.data()+10, "bs.", 3))		if (memcmp(NameR.data()+11, ".ftz", 4))
	break;		break;
	switch (NameR[13]) {		return Intrinsic::nvvm_f2ll_rz_ftz; // "vvm.f2ll.rz.ftz
	default: break;		"
	case 'b': // 1 string to match.
	return Intrinsic::x86_mmx_psubs_b; // "86.mmx.psubs.b"
	case 'w': // 1 string to match.
	return Intrinsic::x86_mmx_psubs_w; // "86.mmx.psubs.w"
	}
	break;
	}		}
	break;		break;
	}		case 'u': // 4 strings to match.
	break;		if (memcmp(NameR.data()+7, "i.r", 3))
	case 'r': // 4 strings to match.
	if (NameR[4] != 'd')
	break;
	switch (NameR[5]) {
	default: break;
	case 'f': // 2 strings to match.
	if (memcmp(NameR.data()+6, "sbase.", 6))
	break;		break;
	switch (NameR[12]) {		switch (NameR[10]) {
	default: break;		default: break;
	case '3': // 1 string to match.		case 'm': // 1 string to match.
	if (NameR[13] != '2')		if (memcmp(NameR.data()+11, ".ftz", 4))
	break;		break;
	return Intrinsic::x86_rdfsbase_32; // "86.rdfsbase.32"		return Intrinsic::nvvm_f2ui_rm_ftz; // "vvm.f2ui.rm.ftz
	case '6': // 1 string to match.		"
	if (NameR[13] != '4')		case 'n': // 1 string to match.
			if (memcmp(NameR.data()+11, ".ftz", 4))
	break;		break;
	return Intrinsic::x86_rdfsbase_64; // "86.rdfsbase.64"		return Intrinsic::nvvm_f2ui_rn_ftz; // "vvm.f2ui.rn.ftz
	}		"
	break;		case 'p': // 1 string to match.
	case 'g': // 2 strings to match.		if (memcmp(NameR.data()+11, ".ftz", 4))
	if (memcmp(NameR.data()+6, "sbase.", 6))
	break;
	switch (NameR[12]) {
	default: break;
	case '3': // 1 string to match.
	if (NameR[13] != '2')
	break;		break;
	return Intrinsic::x86_rdgsbase_32; // "86.rdgsbase.32"		return Intrinsic::nvvm_f2ui_rp_ftz; // "vvm.f2ui.rp.ftz
	case '6': // 1 string to match.		"
	if (NameR[13] != '4')		case 'z': // 1 string to match.
			if (memcmp(NameR.data()+11, ".ftz", 4))
	break;		break;
	return Intrinsic::x86_rdgsbase_64; // "86.rdgsbase.64"		return Intrinsic::nvvm_f2ui_rz_ftz; // "vvm.f2ui.rz.ftz "
	}		}
	break;		break;
	}		}
	break;		break;
	case 's': // 29 strings to match.		case 'l': // 1 string to match.
	if (memcmp(NameR.data()+4, "se", 2))		if (memcmp(NameR.data()+6, "oor.ftz.f", 9))
	break;		break;
	switch (NameR[6]) {		return Intrinsic::nvvm_floor_ftz_f; // "vvm.floor.ftz.f"
	default: break;		}
	case '.': // 5 strings to match.		break;
	switch (NameR[7]) {		case 'm': // 1 string to match.
	default: break;		if (memcmp(NameR.data()+5, "ove.double", 10))
	case 'l': // 1 string to match.		break;
	if (memcmp(NameR.data()+8, "dmxcsr", 6))		return Intrinsic::nvvm_move_double; // "vvm.move.double"
	break;		case 'r': // 1 string to match.
	return Intrinsic::x86_sse_ldmxcsr; // "86.sse.ldmxcsr"		if (memcmp(NameR.data()+5, "ound.ftz.f", 10))
	case 'p': // 1 string to match.		break;
	if (memcmp(NameR.data()+8, "shuf.w", 6))		return Intrinsic::nvvm_round_ftz_f; // "vvm.round.ftz.f"
	break;		case 't': // 1 string to match.
	return Intrinsic::x86_sse_pshuf_w; // "86.sse.pshuf.w"		if (memcmp(NameR.data()+5, "runc.ftz.f", 10))
	case 's': // 3 strings to match.		break;
	switch (NameR[8]) {		return Intrinsic::nvvm_trunc_ftz_f; // "vvm.trunc.ftz.f"
	default: break;		}
	case 'q': // 2 strings to match.		break;
	if (memcmp(NameR.data()+9, "rt.", 3))		case 16: // 34 strings to match.
	break;		if (memcmp(NameR.data()+0, "vvm.", 4))
	switch (NameR[12]) {		break;
	default: break;		switch (NameR[4]) {
	case 'p': // 1 string to match.		default: break;
	if (NameR[13] != 's')		case 'a': // 4 strings to match.
	break;		if (memcmp(NameR.data()+5, "dd.r", 4))
	return Intrinsic::x86_sse_sqrt_ps; // "86.sse.sqrt.ps"		break;
	case 's': // 1 string to match.		switch (NameR[9]) {
	if (NameR[13] != 's')		default: break;
	break;		case 'm': // 1 string to match.
	return Intrinsic::x86_sse_sqrt_ss; // "86.sse.sqrt.ss"		if (memcmp(NameR.data()+10, ".ftz.f", 6))
	}
	break;
	case 't': // 1 string to match.
	if (memcmp(NameR.data()+9, "mxcsr", 5))
	break;
	return Intrinsic::x86_sse_stmxcsr; // "86.sse.stmxcsr"
	}
	break;
	}
	break;		break;
	case '2': // 22 strings to match.		return Intrinsic::nvvm_add_rm_ftz_f; // "vvm.add.rm.ftz.f"
	if (NameR[7] != '.')		case 'n': // 1 string to match.
			if (memcmp(NameR.data()+10, ".ftz.f", 6))
			break;
			return Intrinsic::nvvm_add_rn_ftz_f; // "vvm.add.rn.ftz.f"
			case 'p': // 1 string to match.
			if (memcmp(NameR.data()+10, ".ftz.f", 6))
			break;
			return Intrinsic::nvvm_add_rp_ftz_f; // "vvm.add.rp.ftz.f"
			case 'z': // 1 string to match.
			if (memcmp(NameR.data()+10, ".ftz.f", 6))
			break;
			return Intrinsic::nvvm_add_rz_ftz_f; // "vvm.add.rz.ftz.f"
			}
			break;
			case 'b': // 3 strings to match.
			switch (NameR[5]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(NameR.data()+6, "rrier0.and", 10))
			break;
			return Intrinsic::nvvm_barrier0_and; // "vvm.barrier0.and"
			case 'i': // 2 strings to match.
			if (memcmp(NameR.data()+6, "tcast.", 6))
			break;
			switch (NameR[12]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+13, "2ll", 3))
	break;		break;
	switch (NameR[8]) {		return Intrinsic::nvvm_bitcast_d2ll; // "vvm.bitcast.d2l
	default: break;		l"
	case 'a': // 1 string to match.		case 'l': // 1 string to match.
	if (memcmp(NameR.data()+9, "dd.sd", 5))		if (memcmp(NameR.data()+13, "l2d", 3))
	break;
	return Intrinsic::x86_sse2_add_sd; // "86.sse2.add.sd"
	case 'c': // 2 strings to match.
	if (memcmp(NameR.data()+9, "mp.", 3))
	break;
	switch (NameR[12]) {
	default: break;
	case 'p': // 1 string to match.
	if (NameR[13] != 'd')
	break;
	return Intrinsic::x86_sse2_cmp_pd; // "86.sse2.cmp.pd"
	case 's': // 1 string to match.
	if (NameR[13] != 'd')
	break;
	return Intrinsic::x86_sse2_cmp_sd; // "86.sse2.cmp.sd"
	}
	break;		break;
	case 'd': // 1 string to match.		return Intrinsic::nvvm_bitcast_ll2d; // "vvm.bitcast.ll2
	if (memcmp(NameR.data()+9, "iv.sd", 5))		d"
	break;		}
	return Intrinsic::x86_sse2_div_sd; // "86.sse2.div.sd"		break;
	case 'l': // 1 string to match.		}
	if (memcmp(NameR.data()+9, "fence", 5))		break;
	break;		case 'c': // 1 string to match.
	return Intrinsic::x86_sse2_lfence; // "86.sse2.lfence"		if (memcmp(NameR.data()+5, "os.approx.f", 11))
	case 'm': // 6 strings to match.		break;
	switch (NameR[9]) {		return Intrinsic::nvvm_cos_approx_f; // "vvm.cos.approx.f"
	default: break;		case 'd': // 5 strings to match.
	case 'a': // 2 strings to match.		if (memcmp(NameR.data()+5, "iv.", 3))
	if (memcmp(NameR.data()+10, "x.", 2))		break;
	break;		switch (NameR[8]) {
	switch (NameR[12]) {		default: break;
	default: break;		case 'a': // 1 string to match.
	case 'p': // 1 string to match.		if (memcmp(NameR.data()+9, "pprox.f", 7))
	if (NameR[13] != 'd')		break;
	break;		return Intrinsic::nvvm_div_approx_f; // "vvm.div.approx.f"
	return Intrinsic::x86_sse2_max_pd; // "86.sse2.max.pd"		case 'r': // 4 strings to match.
	case 's': // 1 string to match.		switch (NameR[9]) {
	if (NameR[13] != 'd')		default: break;
	break;		case 'm': // 1 string to match.
	return Intrinsic::x86_sse2_max_sd; // "86.sse2.max.sd"		if (memcmp(NameR.data()+10, ".ftz.f", 6))
	}
	break;
	case 'f': // 1 string to match.
	if (memcmp(NameR.data()+10, "ence", 4))
	break;
	return Intrinsic::x86_sse2_mfence; // "86.sse2.mfence"
	case 'i': // 2 strings to match.
	if (memcmp(NameR.data()+10, "n.", 2))
	break;
	switch (NameR[12]) {
	default: break;
	case 'p': // 1 string to match.
	if (NameR[13] != 'd')
	break;
	return Intrinsic::x86_sse2_min_pd; // "86.sse2.min.pd"
	case 's': // 1 string to match.
	if (NameR[13] != 'd')
	break;
	return Intrinsic::x86_sse2_min_sd; // "86.sse2.min.sd"
	}
	break;
	case 'u': // 1 string to match.
	if (memcmp(NameR.data()+10, "l.sd", 4))
	break;
	return Intrinsic::x86_sse2_mul_sd; // "86.sse2.mul.sd"
	}
	break;		break;
	case 'p': // 10 strings to match.		return Intrinsic::nvvm_div_rm_ftz_f; // "vvm.div.rm.ftz.
	switch (NameR[9]) {		f"
	default: break;		case 'n': // 1 string to match.
	case 'a': // 2 strings to match.		if (memcmp(NameR.data()+10, ".ftz.f", 6))
	if (memcmp(NameR.data()+10, "vg.", 3))
	break;
	switch (NameR[13]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::x86_sse2_pavg_b; // "86.sse2.pavg.b"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse2_pavg_w; // "86.sse2.pavg.w"
	}
	break;
	case 's': // 8 strings to match.
	switch (NameR[10]) {
	default: break;
	case 'l': // 3 strings to match.
	if (memcmp(NameR.data()+11, "l.", 2))
	break;
	switch (NameR[13]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse2_psll_d; // "86.sse2.psll.d"
	case 'q': // 1 string to match.
	return Intrinsic::x86_sse2_psll_q; // "86.sse2.psll.q"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse2_psll_w; // "86.sse2.psll.w"
	}
	break;
	case 'r': // 5 strings to match.
	switch (NameR[11]) {
	default: break;
	case 'a': // 2 strings to match.
	if (NameR[12] != '.')
	break;
	switch (NameR[13]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse2_psra_d; // "86.sse2
	.psra.d"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse2_psra_w; // "86.sse2
	.psra.w"
	}
	break;
	case 'l': // 3 strings to match.
	if (NameR[12] != '.')
	break;
	switch (NameR[13]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse2_psrl_d; // "86.sse2
	.psrl.d"
	case 'q': // 1 string to match.
	return Intrinsic::x86_sse2_psrl_q; // "86.sse2
	.psrl.q"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse2_psrl_w; // "86.sse2
	.psrl.w"
	}
	break;
	}
	break;
	}
	break;
	}
	break;		break;
	case 's': // 1 string to match.		return Intrinsic::nvvm_div_rn_ftz_f; // "vvm.div.rn.ftz.
	if (memcmp(NameR.data()+9, "ub.sd", 5))		f"
	break;		case 'p': // 1 string to match.
	return Intrinsic::x86_sse2_sub_sd; // "86.sse2.sub.sd"		if (memcmp(NameR.data()+10, ".ftz.f", 6))
	}
	break;
	case '3': // 1 string to match.
	if (memcmp(NameR.data()+7, ".ldu.dq", 7))
	break;		break;
	return Intrinsic::x86_sse3_ldu_dq; // "86.sse3.ldu.dq"		return Intrinsic::nvvm_div_rp_ftz_f; // "vvm.div.rp.ftz.
	case '4': // 1 string to match.		f"
	if (memcmp(NameR.data()+7, "a.extrq", 7))		case 'z': // 1 string to match.
			if (memcmp(NameR.data()+10, ".ftz.f", 6))
	break;		break;
	return Intrinsic::x86_sse4a_extrq; // "86.sse4a.extrq"		return Intrinsic::nvvm_div_rz_ftz_f; // "vvm.div.rz.ftz. f"
	}		}
	break;		break;
	case 'w': // 4 strings to match.		}
	if (NameR[4] != 'r')		break;
			case 'e': // 2 strings to match.
			if (memcmp(NameR.data()+5, "x2.approx.", 10))
			break;
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_ex2_approx_d; // "vvm.ex2.approx.d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_ex2_approx_f; // "vvm.ex2.approx.f"
			}
			break;
			case 'f': // 8 strings to match.
			switch (NameR[5]) {
			default: break;
			case '2': // 4 strings to match.
			if (memcmp(NameR.data()+6, "ull.r", 5))
	break;		break;
	switch (NameR[5]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'f': // 2 strings to match.		case 'm': // 1 string to match.
	if (memcmp(NameR.data()+6, "sbase.", 6))		if (memcmp(NameR.data()+12, ".ftz", 4))
	break;		break;
	switch (NameR[12]) {		return Intrinsic::nvvm_f2ull_rm_ftz; // "vvm.f2ull.rm.ft
	default: break;		z"
	case '3': // 1 string to match.		case 'n': // 1 string to match.
	if (NameR[13] != '2')		if (memcmp(NameR.data()+12, ".ftz", 4))
	break;
	return Intrinsic::x86_wrfsbase_32; // "86.wrfsbase.32"
	case '6': // 1 string to match.
	if (NameR[13] != '4')
	break;
	return Intrinsic::x86_wrfsbase_64; // "86.wrfsbase.64"
	}
	break;
	case 'g': // 2 strings to match.
	if (memcmp(NameR.data()+6, "sbase.", 6))
	break;		break;
	switch (NameR[12]) {		return Intrinsic::nvvm_f2ull_rn_ftz; // "vvm.f2ull.rn.ft
	default: break;		z"
	case '3': // 1 string to match.		case 'p': // 1 string to match.
	if (NameR[13] != '2')		if (memcmp(NameR.data()+12, ".ftz", 4))
	break;		break;
	return Intrinsic::x86_wrgsbase_32; // "86.wrgsbase.32"		return Intrinsic::nvvm_f2ull_rp_ftz; // "vvm.f2ull.rp.ft
	case '6': // 1 string to match.		z"
	if (NameR[13] != '4')		case 'z': // 1 string to match.
	break;		if (memcmp(NameR.data()+12, ".ftz", 4))
	return Intrinsic::x86_wrgsbase_64; // "86.wrgsbase.64"		break;
	}		return Intrinsic::nvvm_f2ull_rz_ftz; // "vvm.f2ull.rz.ft
	break;		z"
	}		}
	break;		break;
	case 'x': // 8 strings to match.		case 'm': // 4 strings to match.
	if (memcmp(NameR.data()+4, "op.vp", 5))		if (memcmp(NameR.data()+6, "a.r", 3))
	break;		break;
	switch (NameR[9]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'c': // 4 strings to match.		case 'm': // 1 string to match.
	if (memcmp(NameR.data()+10, "omu", 3))		if (memcmp(NameR.data()+10, ".ftz.f", 6))
	break;		break;
	switch (NameR[13]) {		return Intrinsic::nvvm_fma_rm_ftz_f; // "vvm.fma.rm.ftz.
	default: break;		f"
	case 'b': // 1 string to match.		case 'n': // 1 string to match.
	return Intrinsic::x86_xop_vpcomub; // "86.xop.vpcomub"		if (memcmp(NameR.data()+10, ".ftz.f", 6))
	case 'd': // 1 string to match.
	return Intrinsic::x86_xop_vpcomud; // "86.xop.vpcomud"
	case 'q': // 1 string to match.
	return Intrinsic::x86_xop_vpcomuq; // "86.xop.vpcomuq"
	case 'w': // 1 string to match.
	return Intrinsic::x86_xop_vpcomuw; // "86.xop.vpcomuw"
	}
	break;
	case 'r': // 4 strings to match.
	if (memcmp(NameR.data()+10, "ot", 2))
	break;		break;
	switch (NameR[12]) {		return Intrinsic::nvvm_fma_rn_ftz_f; // "vvm.fma.rn.ftz.
	default: break;		f"
	case 'b': // 1 string to match.		case 'p': // 1 string to match.
	if (NameR[13] != 'i')		if (memcmp(NameR.data()+10, ".ftz.f", 6))
	break;		break;
	return Intrinsic::x86_xop_vprotbi; // "86.xop.vprotbi"		return Intrinsic::nvvm_fma_rp_ftz_f; // "vvm.fma.rp.ftz.
	case 'd': // 1 string to match.		f"
	if (NameR[13] != 'i')		case 'z': // 1 string to match.
	break;		if (memcmp(NameR.data()+10, ".ftz.f", 6))
	return Intrinsic::x86_xop_vprotdi; // "86.xop.vprotdi"		break;
	case 'q': // 1 string to match.		return Intrinsic::nvvm_fma_rz_ftz_f; // "vvm.fma.rz.ftz.
	if (NameR[13] != 'i')		f"
	break;
	return Intrinsic::x86_xop_vprotqi; // "86.xop.vprotqi"
	case 'w': // 1 string to match.
	if (NameR[13] != 'i')
	break;
	return Intrinsic::x86_xop_vprotwi; // "86.xop.vprotwi"
	}
	break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'c': // 1 string to match.		case 'l': // 2 strings to match.
	if (memcmp(NameR.data()+1, "ore.waitevent", 13))		if (memcmp(NameR.data()+5, "g2.approx.", 10))
	break;		break;
	return Intrinsic::xcore_waitevent; // "core.waitevent"		switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_lg2_approx_d; // "vvm.lg2.approx.d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_lg2_approx_f; // "vvm.lg2.approx.f"
			}
			break;
			case 'm': // 4 strings to match.
			if (memcmp(NameR.data()+5, "ul.r", 4))
			break;
			switch (NameR[9]) {
			default: break;
			case 'm': // 1 string to match.
			if (memcmp(NameR.data()+10, ".ftz.f", 6))
			break;
			return Intrinsic::nvvm_mul_rm_ftz_f; // "vvm.mul.rm.ftz.f"
			case 'n': // 1 string to match.
			if (memcmp(NameR.data()+10, ".ftz.f", 6))
			break;
			return Intrinsic::nvvm_mul_rn_ftz_f; // "vvm.mul.rn.ftz.f"
			case 'p': // 1 string to match.
			if (memcmp(NameR.data()+10, ".ftz.f", 6))
			break;
			return Intrinsic::nvvm_mul_rp_ftz_f; // "vvm.mul.rp.ftz.f"
			case 'z': // 1 string to match.
			if (memcmp(NameR.data()+10, ".ftz.f", 6))
			break;
			return Intrinsic::nvvm_mul_rz_ftz_f; // "vvm.mul.rz.ftz.f"
			}
			break;
			case 'r': // 4 strings to match.
			if (memcmp(NameR.data()+5, "cp.r", 4))
			break;
			switch (NameR[9]) {
			default: break;
			case 'm': // 1 string to match.
			if (memcmp(NameR.data()+10, ".ftz.f", 6))
			break;
			return Intrinsic::nvvm_rcp_rm_ftz_f; // "vvm.rcp.rm.ftz.f"
			case 'n': // 1 string to match.
			if (memcmp(NameR.data()+10, ".ftz.f", 6))
			break;
			return Intrinsic::nvvm_rcp_rn_ftz_f; // "vvm.rcp.rn.ftz.f"
			case 'p': // 1 string to match.
			if (memcmp(NameR.data()+10, ".ftz.f", 6))
			break;
			return Intrinsic::nvvm_rcp_rp_ftz_f; // "vvm.rcp.rp.ftz.f"
			case 'z': // 1 string to match.
			if (memcmp(NameR.data()+10, ".ftz.f", 6))
			break;
			return Intrinsic::nvvm_rcp_rz_ftz_f; // "vvm.rcp.rz.ftz.f"
			}
			break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+5, "in.approx.f", 11))
			break;
			return Intrinsic::nvvm_sin_approx_f; // "vvm.sin.approx.f"
	}		}
	break;		break;
	case 15: // 143 strings to match.		case 17: // 6 strings to match.
	switch (NameR[0]) {		if (memcmp(NameR.data()+0, "vvm.", 4))
			break;
			switch (NameR[4]) {
	default: break;		default: break;
	case '8': // 142 strings to match.		case 'b': // 1 string to match.
	if (memcmp(NameR.data()+1, "6.", 2))		if (memcmp(NameR.data()+5, "arrier0.popc", 12))
	break;		break;
	switch (NameR[3]) {		return Intrinsic::nvvm_barrier0_popc; // "vvm.barrier0.popc"
			case 's': // 5 strings to match.
			if (memcmp(NameR.data()+5, "qrt.", 4))
			break;
			switch (NameR[9]) {
	default: break;		default: break;
	case '3': // 3 strings to match.		case 'a': // 1 string to match.
	if (memcmp(NameR.data()+4, "dnow", 4))		if (memcmp(NameR.data()+10, "pprox.f", 7))
	break;		break;
	switch (NameR[8]) {		return Intrinsic::nvvm_sqrt_approx_f; // "vvm.sqrt.approx
			.f"
			case 'r': // 4 strings to match.
			switch (NameR[10]) {
	default: break;		default: break;
	case '.': // 1 string to match.		case 'm': // 1 string to match.
	if (memcmp(NameR.data()+9, "pfsubr", 6))		if (memcmp(NameR.data()+11, ".ftz.f", 6))
	break;		break;
	return Intrinsic::x86_3dnow_pfsubr; // "86.3dnow.pfsubr		return Intrinsic::nvvm_sqrt_rm_ftz_f; // "vvm.sqrt.rm.ftz
	"		.f"
	case 'a': // 2 strings to match.		case 'n': // 1 string to match.
	if (memcmp(NameR.data()+9, ".p", 2))		if (memcmp(NameR.data()+11, ".ftz.f", 6))
	break;		break;
	switch (NameR[11]) {		return Intrinsic::nvvm_sqrt_rn_ftz_f; // "vvm.sqrt.rn.ftz
	default: break;		.f"
	case 'f': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(NameR.data()+12, "2iw", 3))		if (memcmp(NameR.data()+11, ".ftz.f", 6))
	break;
	return Intrinsic::x86_3dnowa_pf2iw; // "86.3dnowa.pf2iw
	"
	case 'i': // 1 string to match.
	if (memcmp(NameR.data()+12, "2fw", 3))
	break;
	return Intrinsic::x86_3dnowa_pi2fw; // "86.3dnowa.pi2fw
	"
	}
	break;
	}
	break;
	case 'a': // 48 strings to match.
	switch (NameR[4]) {
	default: break;
	case 'e': // 3 strings to match.
	if (memcmp(NameR.data()+5, "sni.aes", 7))
	break;		break;
	switch (NameR[12]) {		return Intrinsic::nvvm_sqrt_rp_ftz_f; // "vvm.sqrt.rp.ftz
	default: break;		.f"
	case 'd': // 1 string to match.		case 'z': // 1 string to match.
	if (memcmp(NameR.data()+13, "ec", 2))		if (memcmp(NameR.data()+11, ".ftz.f", 6))
	break;
	return Intrinsic::x86_aesni_aesdec; // "86.aesni.aesdec
	"
	case 'e': // 1 string to match.
	if (memcmp(NameR.data()+13, "nc", 2))
	break;
	return Intrinsic::x86_aesni_aesenc; // "86.aesni.aesenc
	"
	case 'i': // 1 string to match.
	if (memcmp(NameR.data()+13, "mc", 2))
	break;
	return Intrinsic::x86_aesni_aesimc; // "86.aesni.aesimc
	"
	}
	break;
	case 'v': // 45 strings to match.
	if (NameR[5] != 'x')
	break;		break;
	switch (NameR[6]) {		return Intrinsic::nvvm_sqrt_rz_ftz_f; // "vvm.sqrt.rz.ftz
	default: break;		.f"
	case '.': // 1 string to match.		}
	if (memcmp(NameR.data()+7, "vzeroall", 8))		break;
	break;		}
	return Intrinsic::x86_avx_vzeroall; // "86.avx.vzeroall		break;
	"		}
	case '2': // 44 strings to match.		break;
	if (NameR[7] != '.')		case 18: // 3 strings to match.
	break;		if (memcmp(NameR.data()+0, "vvm.", 4))
	switch (NameR[8]) {		break;
	default: break;		switch (NameR[4]) {
	case 'm': // 1 string to match.		default: break;
	if (memcmp(NameR.data()+9, "psadbw", 6))		case 'r': // 2 strings to match.
	break;		if (memcmp(NameR.data()+5, "sqrt.approx.", 12))
	return Intrinsic::x86_avx2_mpsadbw; // "86.avx2.mpsadbw		break;
	"		switch (NameR[17]) {
	case 'p': // 43 strings to match.		default: break;
	switch (NameR[9]) {		case 'd': // 1 string to match.
	default: break;		return Intrinsic::nvvm_rsqrt_approx_d; // "vvm.rsqrt.appro
	case 'a': // 2 strings to match.		x.d"
	if (memcmp(NameR.data()+10, "dds.", 4))		case 'f': // 1 string to match.
	break;		return Intrinsic::nvvm_rsqrt_approx_f; // "vvm.rsqrt.appro
	switch (NameR[14]) {		x.f"
	default: break;		}
	case 'b': // 1 string to match.		break;
	return Intrinsic::x86_avx2_padds_b; // "86.avx2		case 's': // 1 string to match.
	.padds.b"		if (memcmp(NameR.data()+5, "aturate.ftz.f", 13))
	case 'w': // 1 string to match.		break;
	return Intrinsic::x86_avx2_padds_w; // "86.avx2		return Intrinsic::nvvm_saturate_ftz_f; // "vvm.saturate.ftz.f"
	.padds.w"		}
	}		break;
	break;		case 20: // 6 strings to match.
	case 'b': // 1 string to match.		if (memcmp(NameR.data()+0, "vvm.", 4))
	if (memcmp(NameR.data()+10, "lendw", 5))		break;
	break;		switch (NameR[4]) {
	return Intrinsic::x86_avx2_pblendw; // "86.avx2.pblendw		default: break;
	"		case 'c': // 1 string to match.
	case 'h': // 4 strings to match.		if (memcmp(NameR.data()+5, "os.approx.ftz.f", 15))
	switch (NameR[10]) {		break;
	default: break;		return Intrinsic::nvvm_cos_approx_ftz_f; // "vvm.cos.approx.
	case 'a': // 2 strings to match.		ftz.f"
	if (memcmp(NameR.data()+11, "dd.", 3))		case 'd': // 1 string to match.
	break;		if (memcmp(NameR.data()+5, "iv.approx.ftz.f", 15))
	switch (NameR[14]) {		break;
	default: break;		return Intrinsic::nvvm_div_approx_ftz_f; // "vvm.div.approx.
	case 'd': // 1 string to match.		ftz.f"
	return Intrinsic::x86_avx2_phadd_d; // "86.avx2		case 'e': // 1 string to match.
	.phadd.d"		if (memcmp(NameR.data()+5, "x2.approx.ftz.f", 15))
	case 'w': // 1 string to match.		break;
	return Intrinsic::x86_avx2_phadd_w; // "86.avx2		return Intrinsic::nvvm_ex2_approx_ftz_f; // "vvm.ex2.approx.
	.phadd.w"		ftz.f"
	}		case 'l': // 1 string to match.
	break;		if (memcmp(NameR.data()+5, "g2.approx.ftz.f", 15))
	case 's': // 2 strings to match.		break;
	if (memcmp(NameR.data()+11, "ub.", 3))		return Intrinsic::nvvm_lg2_approx_ftz_f; // "vvm.lg2.approx.
	break;		ftz.f"
	switch (NameR[14]) {		case 'r': // 1 string to match.
	default: break;		if (memcmp(NameR.data()+5, "cp.approx.ftz.d", 15))
	case 'd': // 1 string to match.		break;
	return Intrinsic::x86_avx2_phsub_d; // "86.avx2		return Intrinsic::nvvm_rcp_approx_ftz_d; // "vvm.rcp.approx.
	.phsub.d"		ftz.d"
	case 'w': // 1 string to match.		case 's': // 1 string to match.
	return Intrinsic::x86_avx2_phsub_w; // "86.avx2		if (memcmp(NameR.data()+5, "in.approx.ftz.f", 15))
	.phsub.w"		break;
	}		return Intrinsic::nvvm_sin_approx_ftz_f; // "vvm.sin.approx.
	break;		ftz.f"
	}		}
	break;		break;
	case 'm': // 14 strings to match.		case 21: // 1 string to match.
	switch (NameR[10]) {		if (memcmp(NameR.data()+0, "vvm.sqrt.approx.ftz.f", 21))
	default: break;		break;
	case 'a': // 6 strings to match.		return Intrinsic::nvvm_sqrt_approx_ftz_f; // "vvm.sqrt.approx
	if (NameR[11] != 'x')		.ftz.f"
	break;		case 22: // 1 string to match.
	switch (NameR[12]) {		if (memcmp(NameR.data()+0, "vvm.rsqrt.approx.ftz.f", 22))
	default: break;		break;
	case 's': // 3 strings to match.		return Intrinsic::nvvm_rsqrt_approx_ftz_f; // "vvm.rsqrt.appro
	if (NameR[13] != '.')		x.ftz.f"
	break;		case 23: // 3 strings to match.
	switch (NameR[14]) {		if (memcmp(NameR.data()+0, "vvm.read.ptx.sreg.tid.", 22))
	default: break;		break;
	case 'b': // 1 string to match.		switch (NameR[22]) {
	return Intrinsic::x86_avx2_pmaxs_b; // "86.avx2		default: break;
	.pmaxs.b"		case 'x': // 1 string to match.
	case 'd': // 1 string to match.		return Intrinsic::nvvm_read_ptx_sreg_tid_x; // "vvm.read.ptx.sr
	return Intrinsic::x86_avx2_pmaxs_d; // "86.avx2		eg.tid.x"
	.pmaxs.d"		case 'y': // 1 string to match.
	case 'w': // 1 string to match.		return Intrinsic::nvvm_read_ptx_sreg_tid_y; // "vvm.read.ptx.sr
	return Intrinsic::x86_avx2_pmaxs_w; // "86.avx2		eg.tid.y"
	.pmaxs.w"		case 'z': // 1 string to match.
	}		return Intrinsic::nvvm_read_ptx_sreg_tid_z; // "vvm.read.ptx.sr
	break;		eg.tid.z"
	case 'u': // 3 strings to match.		}
	if (NameR[13] != '.')		break;
	break;		case 24: // 3 strings to match.
	switch (NameR[14]) {		if (memcmp(NameR.data()+0, "vvm.read.ptx.sreg.ntid.", 23))
	default: break;		break;
	case 'b': // 1 string to match.		switch (NameR[23]) {
	return Intrinsic::x86_avx2_pmaxu_b; // "86.avx2		default: break;
	.pmaxu.b"		case 'x': // 1 string to match.
	case 'd': // 1 string to match.		return Intrinsic::nvvm_read_ptx_sreg_ntid_x; // "vvm.read.ptx.sr
	return Intrinsic::x86_avx2_pmaxu_d; // "86.avx2		eg.ntid.x"
	.pmaxu.d"		case 'y': // 1 string to match.
	case 'w': // 1 string to match.		return Intrinsic::nvvm_read_ptx_sreg_ntid_y; // "vvm.read.ptx.sr
	return Intrinsic::x86_avx2_pmaxu_w; // "86.avx2		eg.ntid.y"
	.pmaxu.w"		case 'z': // 1 string to match.
	}		return Intrinsic::nvvm_read_ptx_sreg_ntid_z; // "vvm.read.ptx.sr
	break;		eg.ntid.z"
	}		}
	break;		break;
	case 'i': // 6 strings to match.		case 25: // 3 strings to match.
	if (NameR[11] != 'n')		if (memcmp(NameR.data()+0, "vvm.read.ptx.sreg.ctaid.", 24))
	break;		break;
	switch (NameR[12]) {		switch (NameR[24]) {
	default: break;		default: break;
	case 's': // 3 strings to match.		case 'x': // 1 string to match.
	if (NameR[13] != '.')		return Intrinsic::nvvm_read_ptx_sreg_ctaid_x; // "vvm.read.ptx.sr
	break;		eg.ctaid.x"
	switch (NameR[14]) {		case 'y': // 1 string to match.
	default: break;		return Intrinsic::nvvm_read_ptx_sreg_ctaid_y; // "vvm.read.ptx.sr
	case 'b': // 1 string to match.		eg.ctaid.y"
	return Intrinsic::x86_avx2_pmins_b; // "86.avx2		case 'z': // 1 string to match.
	.pmins.b"		return Intrinsic::nvvm_read_ptx_sreg_ctaid_z; // "vvm.read.ptx.sr
	case 'd': // 1 string to match.		eg.ctaid.z"
	return Intrinsic::x86_avx2_pmins_d; // "86.avx2		}
	.pmins.d"		break;
	case 'w': // 1 string to match.		case 26: // 4 strings to match.
	return Intrinsic::x86_avx2_pmins_w; // "86.avx2		if (memcmp(NameR.data()+0, "vvm.read.ptx.sreg.", 18))
	.pmins.w"		break;
	}		switch (NameR[18]) {
	break;		default: break;
	case 'u': // 3 strings to match.		case 'n': // 3 strings to match.
	if (NameR[13] != '.')		if (memcmp(NameR.data()+19, "ctaid.", 6))
	break;		break;
	switch (NameR[14]) {		switch (NameR[25]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'x': // 1 string to match.
	return Intrinsic::x86_avx2_pminu_b; // "86.avx2		return Intrinsic::nvvm_read_ptx_sreg_nctaid_x; // "vvm.rea
	.pminu.b"		d.ptx.sreg.nctaid.x"
	case 'd': // 1 string to match.		case 'y': // 1 string to match.
	return Intrinsic::x86_avx2_pminu_d; // "86.avx2		return Intrinsic::nvvm_read_ptx_sreg_nctaid_y; // "vvm.rea
	.pminu.d"		d.ptx.sreg.nctaid.y"
	case 'w': // 1 string to match.		case 'z': // 1 string to match.
	return Intrinsic::x86_avx2_pminu_w; // "86.avx2		return Intrinsic::nvvm_read_ptx_sreg_nctaid_z; // "vvm.rea
	.pminu.w"		d.ptx.sreg.nctaid.z"
	}		}
	break;		break;
	}		case 'w': // 1 string to match.
	break;		if (memcmp(NameR.data()+19, "arpsize", 7))
	case 'u': // 2 strings to match.		break;
	if (NameR[11] != 'l')		return Intrinsic::nvvm_read_ptx_sreg_warpsize; // "vvm.read.ptx.sr
	break;		eg.warpsize"
	switch (NameR[12]) {		}
	default: break;		break;
	case '.': // 1 string to match.		}
	if (memcmp(NameR.data()+13, "dq", 2))		break; // end of 'n' case.
	break;		case 'o':
	return Intrinsic::x86_avx2_pmul_dq; // "86.avx2		if (NameR.startswith("bjectsize.")) return Intrinsic::objectsize;
	.pmul.dq"		break; // end of 'o' case.
	case 'h': // 1 string to match.		case 'p':
	if (memcmp(NameR.data()+13, ".w", 2))		if (NameR.startswith("tr.annotation.")) return Intrinsic::ptr_annotatio
	break;		n;
	return Intrinsic::x86_avx2_pmulh_w; // "86.avx2		if (NameR.startswith("pc.mtctr.")) return Intrinsic::ppc_mtctr;
	.pmulh.w"		if (NameR.startswith("owi.")) return Intrinsic::powi;
	}		if (NameR.startswith("ow.")) return Intrinsic::pow;
	break;		switch (NameR.size()) {
	}		default: break;
	break;		case 7: // 8 strings to match.
	case 's': // 22 strings to match.		switch (NameR[0]) {
	switch (NameR[10]) {		default: break;
	default: break;		case 'c': // 1 string to match.
	case 'a': // 1 string to match.		if (memcmp(NameR.data()+1, "marker", 6))
	if (memcmp(NameR.data()+11, "d.bw", 4))		break;
	break;		return Intrinsic::pcmarker; // "cmarker"
	return Intrinsic::x86_avx2_psad_bw; // "86.avx2		case 'p': // 6 strings to match.
	.psad.bw"		if (memcmp(NameR.data()+1, "c.", 2))
	case 'h': // 1 string to match.		break;
	if (memcmp(NameR.data()+11, "uf.b", 4))		switch (NameR[3]) {
	break;		default: break;
	return Intrinsic::x86_avx2_pshuf_b; // "86.avx2		case 'd': // 5 strings to match.
	.pshuf.b"		if (memcmp(NameR.data()+4, "cb", 2))
	case 'i': // 3 strings to match.
	if (memcmp(NameR.data()+11, "gn.", 3))
	break;
	switch (NameR[14]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::x86_avx2_psign_b; // "86.avx2
	.psign.b"
	case 'd': // 1 string to match.
	return Intrinsic::x86_avx2_psign_d; // "86.avx2
	.psign.d"
	case 'w': // 1 string to match.
	return Intrinsic::x86_avx2_psign_w; // "86.avx2
	.psign.w"
	}
	break;
	case 'l': // 6 strings to match.
	if (NameR[11] != 'l')
	break;
	switch (NameR[12]) {
	default: break;
	case '.': // 1 string to match.
	if (memcmp(NameR.data()+13, "dq", 2))
	break;
	return Intrinsic::x86_avx2_psll_dq; // "86.avx2
	.psll.dq"
	case 'i': // 3 strings to match.
	if (NameR[13] != '.')
	break;
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_avx2_pslli_d; // "86.avx2
	.pslli.d"
	case 'q': // 1 string to match.
	return Intrinsic::x86_avx2_pslli_q; // "86.avx2
	.pslli.q"
	case 'w': // 1 string to match.
	return Intrinsic::x86_avx2_pslli_w; // "86.avx2
	.pslli.w"
	}
	break;
	case 'v': // 2 strings to match.
	if (NameR[13] != '.')
	break;
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_avx2_psllv_d; // "86.avx2
	.psllv.d"
	case 'q': // 1 string to match.
	return Intrinsic::x86_avx2_psllv_q; // "86.avx2
	.psllv.q"
	}
	break;
	}
	break;
	case 'r': // 9 strings to match.
	switch (NameR[11]) {
	default: break;
	case 'a': // 3 strings to match.
	switch (NameR[12]) {
	default: break;
	case 'i': // 2 strings to match.
	if (NameR[13] != '.')
	break;
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_avx2_psrai_d; // "86.avx2
	.psrai.d"
	case 'w': // 1 string to match.
	return Intrinsic::x86_avx2_psrai_w; // "86.avx2
	.psrai.w"
	}
	break;
	case 'v': // 1 string to match.
	if (memcmp(NameR.data()+13, ".d", 2))
	break;
	return Intrinsic::x86_avx2_psrav_d; // "86.avx2
	.psrav.d"
	}
	break;
	case 'l': // 6 strings to match.
	switch (NameR[12]) {
	default: break;
	case '.': // 1 string to match.
	if (memcmp(NameR.data()+13, "dq", 2))
	break;
	return Intrinsic::x86_avx2_psrl_dq; // "86.avx2
	.psrl.dq"
	case 'i': // 3 strings to match.
	if (NameR[13] != '.')
	break;
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_avx2_psrli_d; // "86.avx2
	.psrli.d"
	case 'q': // 1 string to match.
	return Intrinsic::x86_avx2_psrli_q; // "86.avx2
	.psrli.q"
	case 'w': // 1 string to match.
	return Intrinsic::x86_avx2_psrli_w; // "86.avx2
	.psrli.w"
	}
	break;
	case 'v': // 2 strings to match.
	if (NameR[13] != '.')
	break;
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_avx2_psrlv_d; // "86.avx2
	.psrlv.d"
	case 'q': // 1 string to match.
	return Intrinsic::x86_avx2_psrlv_q; // "86.avx2
	.psrlv.q"
	}
	break;
	}
	break;
	}
	break;
	case 'u': // 2 strings to match.
	if (memcmp(NameR.data()+11, "bs.", 3))
	break;
	switch (NameR[14]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::x86_avx2_psubs_b; // "86.avx2
	.psubs.b"
	case 'w': // 1 string to match.
	return Intrinsic::x86_avx2_psubs_w; // "86.avx2
	.psubs.w"
	}
	break;
	}
	break;
	}
	break;
	}
	break;
	}
	break;		break;
			switch (NameR[6]) {
			default: break;
			case 'a': // 1 string to match.
			return Intrinsic::ppc_dcba; // "pc.dcba"
			case 'f': // 1 string to match.
			return Intrinsic::ppc_dcbf; // "pc.dcbf"
			case 'i': // 1 string to match.
			return Intrinsic::ppc_dcbi; // "pc.dcbi"
			case 't': // 1 string to match.
			return Intrinsic::ppc_dcbt; // "pc.dcbt"
			case 'z': // 1 string to match.
			return Intrinsic::ppc_dcbz; // "pc.dcbz"
	}		}
	break;		break;
	case 'b': // 2 strings to match.		case 's': // 1 string to match.
	if (memcmp(NameR.data()+4, "mi.bextr.", 9))		if (memcmp(NameR.data()+4, "ync", 3))
			break;
			return Intrinsic::ppc_sync; // "pc.sync"
			}
			break;
			case 'r': // 1 string to match.
			if (memcmp(NameR.data()+1, "efetch", 6))
			break;
			return Intrinsic::prefetch; // "refetch"
			}
			break;
			case 8: // 2 strings to match.
			if (memcmp(NameR.data()+0, "pc.dcb", 6))
			break;
			switch (NameR[6]) {
			default: break;
			case 's': // 1 string to match.
			if (NameR[7] != 't')
			break;
			return Intrinsic::ppc_dcbst; // "pc.dcbst"
			case 'z': // 1 string to match.
			if (NameR[7] != 'l')
			break;
			return Intrinsic::ppc_dcbzl; // "pc.dcbzl"
			}
			break;
			case 9: // 1 string to match.
			if (memcmp(NameR.data()+0, "pc.dcbtst", 9))
			break;
			return Intrinsic::ppc_dcbtst; // "pc.dcbtst"
			case 11: // 5 strings to match.
			if (memcmp(NameR.data()+0, "tx.", 3))
			break;
			switch (NameR[3]) {
			default: break;
			case 'b': // 1 string to match.
			if (memcmp(NameR.data()+4, "ar.sync", 7))
			break;
			return Intrinsic::ptx_bar_sync; // "tx.bar.sync"
			case 'r': // 4 strings to match.
			if (memcmp(NameR.data()+4, "ead.pm", 6))
			break;
			switch (NameR[10]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::ptx_read_pm0; // "tx.read.pm0"
			case '1': // 1 string to match.
			return Intrinsic::ptx_read_pm1; // "tx.read.pm1"
			case '2': // 1 string to match.
			return Intrinsic::ptx_read_pm2; // "tx.read.pm2"
			case '3': // 1 string to match.
			return Intrinsic::ptx_read_pm3; // "tx.read.pm3"
			}
			break;
			}
			break;
			case 12: // 1 string to match.
			if (memcmp(NameR.data()+0, "tx.read.smid", 12))
			break;
			return Intrinsic::ptx_read_smid; // "tx.read.smid"
			case 13: // 6 strings to match.
			if (memcmp(NameR.data()+0, "tx.read.", 8))
			break;
			switch (NameR[8]) {
			default: break;
			case 'c': // 1 string to match.
			if (memcmp(NameR.data()+9, "lock", 4))
			break;
			return Intrinsic::ptx_read_clock; // "tx.read.clock"
			case 'n': // 1 string to match.
			if (memcmp(NameR.data()+9, "smid", 4))
			break;
			return Intrinsic::ptx_read_nsmid; // "tx.read.nsmid"
			case 't': // 4 strings to match.
			if (memcmp(NameR.data()+9, "id.", 3))
			break;
			switch (NameR[12]) {
			default: break;
			case 'w': // 1 string to match.
			return Intrinsic::ptx_read_tid_w; // "tx.read.tid.w"
			case 'x': // 1 string to match.
			return Intrinsic::ptx_read_tid_x; // "tx.read.tid.x"
			case 'y': // 1 string to match.
			return Intrinsic::ptx_read_tid_y; // "tx.read.tid.y"
			case 'z': // 1 string to match.
			return Intrinsic::ptx_read_tid_z; // "tx.read.tid.z"
			}
			break;
			}
			break;
			case 14: // 12 strings to match.
			switch (NameR[0]) {
			default: break;
			case 'p': // 5 strings to match.
			if (memcmp(NameR.data()+1, "c.altivec.", 10))
			break;
			switch (NameR[11]) {
			default: break;
			case 'd': // 2 strings to match.
			if (NameR[12] != 's')
	break;		break;
	switch (NameR[13]) {		switch (NameR[13]) {
	default: break;		default: break;
	case '3': // 1 string to match.		case 's': // 1 string to match.
	if (NameR[14] != '2')		return Intrinsic::ppc_altivec_dss; // "pc.altivec.dss"
	break;		case 't': // 1 string to match.
	return Intrinsic::x86_bmi_bextr_32; // "86.bmi.bextr.32		return Intrinsic::ppc_altivec_dst; // "pc.altivec.dst"
	"
	case '6': // 1 string to match.
	if (NameR[14] != '4')
	break;
	return Intrinsic::x86_bmi_bextr_64; // "86.bmi.bextr.64
	"
	}		}
	break;		break;
	case 'm': // 19 strings to match.		case 'l': // 1 string to match.
	if (memcmp(NameR.data()+4, "mx.", 3))		if (memcmp(NameR.data()+12, "vx", 2))
	break;		break;
	switch (NameR[7]) {		return Intrinsic::ppc_altivec_lvx; // "pc.altivec.lvx"
	default: break;		case 'v': // 2 strings to match.
	case 'm': // 2 strings to match.		if (NameR[12] != 's')
	switch (NameR[8]) {		break;
			switch (NameR[13]) {
			default: break;
			case 'l': // 1 string to match.
			return Intrinsic::ppc_altivec_vsl; // "pc.altivec.vsl"
			case 'r': // 1 string to match.
			return Intrinsic::ppc_altivec_vsr; // "pc.altivec.vsr"
			}
			break;
			}
			break;
			case 't': // 7 strings to match.
			if (memcmp(NameR.data()+1, "x.read.", 7))
			break;
			switch (NameR[8]) {
			default: break;
			case 'g': // 1 string to match.
			if (memcmp(NameR.data()+9, "ridid", 5))
			break;
			return Intrinsic::ptx_read_gridid; // "tx.read.gridid"
			case 'l': // 1 string to match.
			if (memcmp(NameR.data()+9, "aneid", 5))
			break;
			return Intrinsic::ptx_read_laneid; // "tx.read.laneid"
			case 'n': // 4 strings to match.
			if (memcmp(NameR.data()+9, "tid.", 4))
			break;
			switch (NameR[13]) {
			default: break;
			case 'w': // 1 string to match.
			return Intrinsic::ptx_read_ntid_w; // "tx.read.ntid.w"
			case 'x': // 1 string to match.
			return Intrinsic::ptx_read_ntid_x; // "tx.read.ntid.x"
			case 'y': // 1 string to match.
			return Intrinsic::ptx_read_ntid_y; // "tx.read.ntid.y"
			case 'z': // 1 string to match.
			return Intrinsic::ptx_read_ntid_z; // "tx.read.ntid.z"
			}
			break;
			case 'w': // 1 string to match.
			if (memcmp(NameR.data()+9, "arpid", 5))
			break;
			return Intrinsic::ptx_read_warpid; // "tx.read.warpid"
			}
			break;
			}
			break;
			case 15: // 23 strings to match.
			switch (NameR[0]) {
			default: break;
			case 'p': // 17 strings to match.
			if (memcmp(NameR.data()+1, "c.altivec.", 10))
			break;
			switch (NameR[11]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+12, "stt", 3))
			break;
			return Intrinsic::ppc_altivec_dstt; // "pc.altivec.dstt"
			case 'l': // 3 strings to match.
			if (NameR[12] != 'v')
			break;
			switch (NameR[13]) {
			default: break;
			case 's': // 2 strings to match.
			switch (NameR[14]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'l': // 1 string to match.
	if (memcmp(NameR.data()+9, "skmovq", 6))		return Intrinsic::ppc_altivec_lvsl; // "pc.altivec.lvsl
	break;		"
	return Intrinsic::x86_mmx_maskmovq; // "86.mmx.maskmovq		case 'r': // 1 string to match.
	"		return Intrinsic::ppc_altivec_lvsr; // "pc.altivec.lvsr
	case 'o': // 1 string to match.		"
	if (memcmp(NameR.data()+9, "vnt.dq", 6))
	break;
	return Intrinsic::x86_mmx_movnt_dq; // "86.mmx.movnt.dq
	"
	}		}
	break;		break;
	case 'p': // 17 strings to match.		case 'x': // 1 string to match.
	switch (NameR[8]) {		if (NameR[14] != 'l')
	default: break;
	case 'a': // 5 strings to match.
	switch (NameR[9]) {
	default: break;
	case 'c': // 3 strings to match.
	if (NameR[10] != 'k')
	break;
	switch (NameR[11]) {
	default: break;
	case 's': // 2 strings to match.
	if (NameR[12] != 's')
	break;
	switch (NameR[13]) {
	default: break;
	case 'd': // 1 string to match.
	if (NameR[14] != 'w')
	break;
	return Intrinsic::x86_mmx_packssdw; // "86.mmx.
	packssdw"
	case 'w': // 1 string to match.
	if (NameR[14] != 'b')
	break;
	return Intrinsic::x86_mmx_packsswb; // "86.mmx.
	packsswb"
	}
	break;
	case 'u': // 1 string to match.
	if (memcmp(NameR.data()+12, "swb", 3))
	break;
	return Intrinsic::x86_mmx_packuswb; // "86.mmx.packuswb
	"
	}
	break;
	case 'd': // 2 strings to match.
	if (memcmp(NameR.data()+10, "dus.", 4))
	break;
	switch (NameR[14]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::x86_mmx_paddus_b; // "86.mmx.paddus.b
	"
	case 'w': // 1 string to match.
	return Intrinsic::x86_mmx_paddus_w; // "86.mmx.paddus.w
	"
	}
	break;
	}
	break;		break;
	case 'c': // 6 strings to match.		return Intrinsic::ppc_altivec_lvxl; // "pc.altivec.lvxl
	if (memcmp(NameR.data()+9, "mp", 2))		"
	break;		}
	switch (NameR[11]) {		break;
	default: break;		case 's': // 1 string to match.
	case 'e': // 3 strings to match.		if (memcmp(NameR.data()+12, "tvx", 3))
	if (memcmp(NameR.data()+12, "q.", 2))		break;
	break;		return Intrinsic::ppc_altivec_stvx; // "pc.altivec.stvx"
	switch (NameR[14]) {		case 'v': // 12 strings to match.
	default: break;		switch (NameR[12]) {
	case 'b': // 1 string to match.		default: break;
	return Intrinsic::x86_mmx_pcmpeq_b; // "86.mmx.pcmpeq.b		case 'r': // 3 strings to match.
	"		if (NameR[13] != 'l')
	case 'd': // 1 string to match.
	return Intrinsic::x86_mmx_pcmpeq_d; // "86.mmx.pcmpeq.d
	"
	case 'w': // 1 string to match.
	return Intrinsic::x86_mmx_pcmpeq_w; // "86.mmx.pcmpeq.w
	"
	}
	break;
	case 'g': // 3 strings to match.
	if (memcmp(NameR.data()+12, "t.", 2))
	break;
	switch (NameR[14]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::x86_mmx_pcmpgt_b; // "86.mmx.pcmpgt.b
	"
	case 'd': // 1 string to match.
	return Intrinsic::x86_mmx_pcmpgt_d; // "86.mmx.pcmpgt.d
	"
	case 'w': // 1 string to match.
	return Intrinsic::x86_mmx_pcmpgt_w; // "86.mmx.pcmpgt.w
	"
	}
	break;
	}
	break;		break;
	case 'm': // 4 strings to match.		switch (NameR[14]) {
	switch (NameR[9]) {		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::ppc_altivec_vrlb; // "pc.altivec.vrlb
			"
			case 'h': // 1 string to match.
			return Intrinsic::ppc_altivec_vrlh; // "pc.altivec.vrlh
			"
			case 'w': // 1 string to match.
			return Intrinsic::ppc_altivec_vrlw; // "pc.altivec.vrlw
			"
			}
			break;
			case 's': // 9 strings to match.
			switch (NameR[13]) {
			default: break;
			case 'e': // 1 string to match.
			if (NameR[14] != 'l')
			break;
			return Intrinsic::ppc_altivec_vsel; // "pc.altivec.vsel
			"
			case 'l': // 4 strings to match.
			switch (NameR[14]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(NameR.data()+10, "dd.wd", 5))		return Intrinsic::ppc_altivec_vslb; // "pc.altivec.vslb
	break;		"
	return Intrinsic::x86_mmx_pmadd_wd; // "86.mmx.pmadd.wd		case 'h': // 1 string to match.
	"		return Intrinsic::ppc_altivec_vslh; // "pc.altivec.vslh
			"
	case 'o': // 1 string to match.		case 'o': // 1 string to match.
	if (memcmp(NameR.data()+10, "vmskb", 5))		return Intrinsic::ppc_altivec_vslo; // "pc.altivec.vslo
	break;		"
	return Intrinsic::x86_mmx_pmovmskb; // "86.mmx.pmovmskb		case 'w': // 1 string to match.
	"		return Intrinsic::ppc_altivec_vslw; // "pc.altivec.vslw
	case 'u': // 2 strings to match.		"
	if (NameR[10] != 'l')
	break;
	switch (NameR[11]) {
	default: break;
	case 'h': // 1 string to match.
	if (memcmp(NameR.data()+12, "u.w", 3))
	break;
	return Intrinsic::x86_mmx_pmulhu_w; // "86.mmx.pmulhu.w
	"
	case 'u': // 1 string to match.
	if (memcmp(NameR.data()+12, ".dq", 3))
	break;
	return Intrinsic::x86_mmx_pmulu_dq; // "86.mmx.pmulu.dq
	"
	}
	break;
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 'r': // 4 strings to match.
	if (memcmp(NameR.data()+9, "ubus.", 5))
	break;
	switch (NameR[14]) {		switch (NameR[14]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::x86_mmx_psubus_b; // "86.mmx.psubus.b		return Intrinsic::ppc_altivec_vsrb; // "pc.altivec.vsrb
	"		"
			case 'h': // 1 string to match.
			return Intrinsic::ppc_altivec_vsrh; // "pc.altivec.vsrh
			"
			case 'o': // 1 string to match.
			return Intrinsic::ppc_altivec_vsro; // "pc.altivec.vsro
			"
	case 'w': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::x86_mmx_psubus_w; // "86.mmx.psubus.w "		return Intrinsic::ppc_altivec_vsrw; // "pc.altivec.vsrw "
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 's': // 54 strings to match.		}
	if (NameR[4] != 's')		break;
			case 't': // 6 strings to match.
			if (memcmp(NameR.data()+1, "x.read.", 7))
			break;
			switch (NameR[8]) {
			default: break;
			case 'c': // 5 strings to match.
			switch (NameR[9]) {
			default: break;
			case 'l': // 1 string to match.
			if (memcmp(NameR.data()+10, "ock64", 5))
			break;
			return Intrinsic::ptx_read_clock64; // "tx.read.clock64
			"
			case 't': // 4 strings to match.
			if (memcmp(NameR.data()+10, "aid.", 4))
			break;
			switch (NameR[14]) {
			default: break;
			case 'w': // 1 string to match.
			return Intrinsic::ptx_read_ctaid_w; // "tx.read.ctaid.w
			"
			case 'x': // 1 string to match.
			return Intrinsic::ptx_read_ctaid_x; // "tx.read.ctaid.x
			"
			case 'y': // 1 string to match.
			return Intrinsic::ptx_read_ctaid_y; // "tx.read.ctaid.y
			"
			case 'z': // 1 string to match.
			return Intrinsic::ptx_read_ctaid_z; // "tx.read.ctaid.z
			"
			}
	break;		break;
	switch (NameR[5]) {		}
			break;
			case 'n': // 1 string to match.
			if (memcmp(NameR.data()+9, "warpid", 6))
			break;
			return Intrinsic::ptx_read_nwarpid; // "tx.read.nwarpid"
			}
			break;
			}
			break;
			case 16: // 21 strings to match.
			switch (NameR[0]) {
			default: break;
			case 'p': // 17 strings to match.
			if (memcmp(NameR.data()+1, "c.altivec.", 10))
			break;
			switch (NameR[11]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+12, "stst", 4))
			break;
			return Intrinsic::ppc_altivec_dstst; // "pc.altivec.dstst"
			case 'l': // 3 strings to match.
			if (memcmp(NameR.data()+12, "ve", 2))
			break;
			switch (NameR[14]) {
	default: break;		default: break;
	case 'e': // 51 strings to match.		case 'b': // 1 string to match.
	switch (NameR[6]) {		if (NameR[15] != 'x')
			break;
			return Intrinsic::ppc_altivec_lvebx; // "pc.altivec.lveb
			x"
			case 'h': // 1 string to match.
			if (NameR[15] != 'x')
			break;
			return Intrinsic::ppc_altivec_lvehx; // "pc.altivec.lveh
			x"
			case 'w': // 1 string to match.
			if (NameR[15] != 'x')
			break;
			return Intrinsic::ppc_altivec_lvewx; // "pc.altivec.lvew
			x"
			}
			break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+12, "tvxl", 4))
			break;
			return Intrinsic::ppc_altivec_stvxl; // "pc.altivec.stvxl"
			case 'v': // 12 strings to match.
			switch (NameR[12]) {
			default: break;
			case 'c': // 2 strings to match.
			if (NameR[13] != 'f')
			break;
			switch (NameR[14]) {
	default: break;		default: break;
	case '.': // 8 strings to match.		case 's': // 1 string to match.
	switch (NameR[7]) {		if (NameR[15] != 'x')
	default: break;
	case 'c': // 6 strings to match.
	if (memcmp(NameR.data()+8, "vt", 2))
	break;
	switch (NameR[10]) {
	default: break;
	case 'p': // 4 strings to match.
	switch (NameR[11]) {
	default: break;
	case 'd': // 1 string to match.
	if (memcmp(NameR.data()+12, "2pi", 3))
	break;
	return Intrinsic::x86_sse_cvtpd2pi; // "86.sse.
	cvtpd2pi"
	case 'i': // 2 strings to match.
	if (memcmp(NameR.data()+12, "2p", 2))
	break;
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse_cvtpi2pd; // "86.sse.
	cvtpi2pd"
	case 's': // 1 string to match.
	return Intrinsic::x86_sse_cvtpi2ps; // "86.sse.
	cvtpi2ps"
	}
	break;
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+12, "2pi", 3))
	break;
	return Intrinsic::x86_sse_cvtps2pi; // "86.sse.
	cvtps2pi"
	}
	break;
	case 's': // 2 strings to match.
	switch (NameR[11]) {
	default: break;
	case 'i': // 1 string to match.
	if (memcmp(NameR.data()+12, "2ss", 3))
	break;
	return Intrinsic::x86_sse_cvtsi2ss; // "86.sse.
	cvtsi2ss"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+12, "2si", 3))
	break;
	return Intrinsic::x86_sse_cvtss2si; // "86.sse.
	cvtss2si"
	}
	break;
	}
	break;		break;
	case 'r': // 2 strings to match.		return Intrinsic::ppc_altivec_vcfsx; // "pc.altivec.vcfs
	if (memcmp(NameR.data()+8, "sqrt.", 5))		x"
	break;		case 'u': // 1 string to match.
	switch (NameR[13]) {		if (NameR[15] != 'x')
	default: break;
	case 'p': // 1 string to match.
	if (NameR[14] != 's')
	break;
	return Intrinsic::x86_sse_rsqrt_ps; // "86.sse.rsqrt.ps
	"
	case 's': // 1 string to match.
	if (NameR[14] != 's')
	break;
	return Intrinsic::x86_sse_rsqrt_ss; // "86.sse.rsqrt.ss
	"
	}
	break;		break;
	}		return Intrinsic::ppc_altivec_vcfux; // "pc.altivec.vcfu
	break;		x"
	case '2': // 23 strings to match.		}
	if (NameR[7] != '.')		break;
			case 'p': // 2 strings to match.
			switch (NameR[13]) {
			default: break;
			case 'e': // 1 string to match.
			if (memcmp(NameR.data()+14, "rm", 2))
	break;		break;
	switch (NameR[8]) {		return Intrinsic::ppc_altivec_vperm; // "pc.altivec.vper
			m"
			case 'k': // 1 string to match.
			if (memcmp(NameR.data()+14, "px", 2))
			break;
			return Intrinsic::ppc_altivec_vpkpx; // "pc.altivec.vpkp
			x"
			}
			break;
			case 'r': // 5 strings to match.
			switch (NameR[13]) {
			default: break;
			case 'e': // 1 string to match.
			if (memcmp(NameR.data()+14, "fp", 2))
			break;
			return Intrinsic::ppc_altivec_vrefp; // "pc.altivec.vref
			p"
			case 'f': // 4 strings to match.
			if (NameR[14] != 'i')
			break;
			switch (NameR[15]) {
	default: break;		default: break;
	case 'c': // 1 string to match.
	if (memcmp(NameR.data()+9, "lflush", 6))
	break;
	return Intrinsic::x86_sse2_clflush; // "86.sse2.clflush
	"
	case 'p': // 20 strings to match.
	switch (NameR[9]) {
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(NameR.data()+10, "dds.", 4))
	break;
	switch (NameR[14]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::x86_sse2_padds_b; // "86.sse2
	.padds.b"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse2_padds_w; // "86.sse2
	.padds.w"
	}
	break;
	case 'm': // 5 strings to match.
	switch (NameR[10]) {
	default: break;
	case 'a': // 2 strings to match.
	if (NameR[11] != 'x')
	break;
	switch (NameR[12]) {
	default: break;
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+13, ".w", 2))
	break;
	return Intrinsic::x86_sse2_pmaxs_w; // "86.sse2
	.pmaxs.w"
	case 'u': // 1 string to match.
	if (memcmp(NameR.data()+13, ".b", 2))
	break;
	return Intrinsic::x86_sse2_pmaxu_b; // "86.sse2
	.pmaxu.b"
	}
	break;
	case 'i': // 2 strings to match.
	if (NameR[11] != 'n')
	break;
	switch (NameR[12]) {
	default: break;
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+13, ".w", 2))
	break;
	return Intrinsic::x86_sse2_pmins_w; // "86.sse2
	.pmins.w"
	case 'u': // 1 string to match.
	if (memcmp(NameR.data()+13, ".b", 2))
	break;
	return Intrinsic::x86_sse2_pminu_b; // "86.sse2
	.pminu.b"
	}
	break;
	case 'u': // 1 string to match.
	if (memcmp(NameR.data()+11, "lh.w", 4))
	break;
	return Intrinsic::x86_sse2_pmulh_w; // "86.sse2
	.pmulh.w"
	}
	break;
	case 's': // 13 strings to match.
	switch (NameR[10]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(NameR.data()+11, "d.bw", 4))
	break;
	return Intrinsic::x86_sse2_psad_bw; // "86.sse2
	.psad.bw"
	case 'l': // 4 strings to match.
	if (NameR[11] != 'l')
	break;
	switch (NameR[12]) {
	default: break;
	case '.': // 1 string to match.
	if (memcmp(NameR.data()+13, "dq", 2))
	break;
	return Intrinsic::x86_sse2_psll_dq; // "86.sse2
	.psll.dq"
	case 'i': // 3 strings to match.
	if (NameR[13] != '.')
	break;
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse2_pslli_d; // "86.sse2
	.pslli.d"
	case 'q': // 1 string to match.
	return Intrinsic::x86_sse2_pslli_q; // "86.sse2
	.pslli.q"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse2_pslli_w; // "86.sse2
	.pslli.w"
	}
	break;
	}
	break;
	case 'r': // 6 strings to match.
	switch (NameR[11]) {
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(NameR.data()+12, "i.", 2))
	break;
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse2_psrai_d; // "86.sse2
	.psrai.d"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse2_psrai_w; // "86.sse2
	.psrai.w"
	}
	break;
	case 'l': // 4 strings to match.
	switch (NameR[12]) {
	default: break;
	case '.': // 1 string to match.
	if (memcmp(NameR.data()+13, "dq", 2))
	break;
	return Intrinsic::x86_sse2_psrl_dq; // "86.sse2
	.psrl.dq"
	case 'i': // 3 strings to match.
	if (NameR[13] != '.')
	break;
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse2_psrli_d; // "86.sse2
	.psrli.d"
	case 'q': // 1 string to match.
	return Intrinsic::x86_sse2_psrli_q; // "86.sse2
	.psrli.q"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse2_psrli_w; // "86.sse2
	.psrli.w"
	}
	break;
	}
	break;
	}
	break;
	case 'u': // 2 strings to match.
	if (memcmp(NameR.data()+11, "bs.", 3))
	break;
	switch (NameR[14]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::x86_sse2_psubs_b; // "86.sse2
	.psubs.b"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse2_psubs_w; // "86.sse2
	.psubs.w"
	}
	break;
	}
	break;
	}
	break;
	case 's': // 2 strings to match.
	if (memcmp(NameR.data()+9, "qrt.", 4))
	break;
	switch (NameR[13]) {
	default: break;
	case 'p': // 1 string to match.
	if (NameR[14] != 'd')
	break;
	return Intrinsic::x86_sse2_sqrt_pd; // "86.sse2.sqrt.pd
	"
	case 's': // 1 string to match.
	if (NameR[14] != 'd')
	break;
	return Intrinsic::x86_sse2_sqrt_sd; // "86.sse2.sqrt.sd
	"
	}
	break;
	}
	break;
	case '3': // 5 strings to match.
	if (NameR[7] != '.')
	break;
	switch (NameR[8]) {
	default: break;
	case 'h': // 4 strings to match.
	switch (NameR[9]) {
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(NameR.data()+10, "dd.p", 4))
	break;
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse3_hadd_pd; // "86.sse3
	.hadd.pd"
	case 's': // 1 string to match.
	return Intrinsic::x86_sse3_hadd_ps; // "86.sse3
	.hadd.ps"
	}
	break;
	case 's': // 2 strings to match.
	if (memcmp(NameR.data()+10, "ub.p", 4))
	break;
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse3_hsub_pd; // "86.sse3
	.hsub.pd"
	case 's': // 1 string to match.
	return Intrinsic::x86_sse3_hsub_ps; // "86.sse3
	.hsub.ps"
	}
	break;
	}
	break;
	case 'm': // 1 string to match.		case 'm': // 1 string to match.
	if (memcmp(NameR.data()+9, "onitor", 6))		return Intrinsic::ppc_altivec_vrfim; // "pc.altivec.vrfi
	break;		m"
	return Intrinsic::x86_sse3_monitor; // "86.sse3.monitor		case 'n': // 1 string to match.
	"		return Intrinsic::ppc_altivec_vrfin; // "pc.altivec.vrfi
	}		n"
	break;		case 'p': // 1 string to match.
	case '4': // 15 strings to match.		return Intrinsic::ppc_altivec_vrfip; // "pc.altivec.vrfi
	switch (NameR[7]) {		p"
	default: break;		case 'z': // 1 string to match.
	case '1': // 14 strings to match.		return Intrinsic::ppc_altivec_vrfiz; // "pc.altivec.vrfi
	if (memcmp(NameR.data()+8, ".p", 2))		z"
	break;
	switch (NameR[10]) {
	default: break;
	case 'e': // 3 strings to match.
	if (memcmp(NameR.data()+11, "xtr", 3))
	break;
	switch (NameR[14]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::x86_sse41_pextrb; // "86.sse4
	1.pextrb"
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_pextrd; // "86.sse4
	1.pextrd"
	case 'q': // 1 string to match.
	return Intrinsic::x86_sse41_pextrq; // "86.sse4
	1.pextrq"
	}
	break;
	case 'm': // 9 strings to match.
	switch (NameR[11]) {
	default: break;
	case 'a': // 4 strings to match.
	if (NameR[12] != 'x')
	break;
	switch (NameR[13]) {
	default: break;
	case 's': // 2 strings to match.
	switch (NameR[14]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::x86_sse41_pmaxsb; // "86.sse4
	1.pmaxsb"
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_pmaxsd; // "86.sse4
	1.pmaxsd"
	}
	break;
	case 'u': // 2 strings to match.
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_pmaxud; // "86.sse4
	1.pmaxud"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse41_pmaxuw; // "86.sse4
	1.pmaxuw"
	}
	break;
	}
	break;
	case 'i': // 4 strings to match.
	if (NameR[12] != 'n')
	break;
	switch (NameR[13]) {
	default: break;
	case 's': // 2 strings to match.
	switch (NameR[14]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::x86_sse41_pminsb; // "86.sse4
	1.pminsb"
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_pminsd; // "86.sse4
	1.pminsd"
	}
	break;
	case 'u': // 2 strings to match.
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_pminud; // "86.sse4
	1.pminud"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse41_pminuw; // "86.sse4
	1.pminuw"
	}
	break;
	}
	break;
	case 'u': // 1 string to match.
	if (memcmp(NameR.data()+12, "ldq", 3))
	break;
	return Intrinsic::x86_sse41_pmuldq; // "86.sse4
	1.pmuldq"
	}
	break;
	case 't': // 2 strings to match.
	if (memcmp(NameR.data()+11, "est", 3))
	break;
	switch (NameR[14]) {
	default: break;
	case 'c': // 1 string to match.
	return Intrinsic::x86_sse41_ptestc; // "86.sse4
	1.ptestc"
	case 'z': // 1 string to match.
	return Intrinsic::x86_sse41_ptestz; // "86.sse4
	1.ptestz"
	}
	break;
	}
	break;
	case 'a': // 1 string to match.
	if (memcmp(NameR.data()+8, ".extrqi", 7))
	break;
	return Intrinsic::x86_sse4a_extrqi; // "86.sse4a.extrqi
	"
	}		}
	break;		break;
	}		}
	break;		break;
	case 's': // 3 strings to match.		case 's': // 3 strings to match.
	if (memcmp(NameR.data()+6, "e3.pabs.", 8))		if (memcmp(NameR.data()+13, "ra", 2))
	break;		break;
	switch (NameR[14]) {		switch (NameR[15]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::x86_ssse3_pabs_b; // "86.ssse3.pabs.b		return Intrinsic::ppc_altivec_vsrab; // "pc.altivec.vsra
	"		b"
	case 'd': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::x86_ssse3_pabs_d; // "86.ssse3.pabs.d		return Intrinsic::ppc_altivec_vsrah; // "pc.altivec.vsra
	"		h"
	case 'w': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::x86_ssse3_pabs_w; // "86.ssse3.pabs.w "		return Intrinsic::ppc_altivec_vsraw; // "pc.altivec.vsra w"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'x': // 16 strings to match.		}
	if (memcmp(NameR.data()+4, "op.v", 4))		break;
			case 't': // 4 strings to match.
			if (memcmp(NameR.data()+1, "x.read.nctaid.", 14))
			break;
			switch (NameR[15]) {
			default: break;
			case 'w': // 1 string to match.
			return Intrinsic::ptx_read_nctaid_w; // "tx.read.nctaid.w"
			case 'x': // 1 string to match.
			return Intrinsic::ptx_read_nctaid_x; // "tx.read.nctaid.x"
			case 'y': // 1 string to match.
			return Intrinsic::ptx_read_nctaid_y; // "tx.read.nctaid.y"
			case 'z': // 1 string to match.
			return Intrinsic::ptx_read_nctaid_z; // "tx.read.nctaid.z"
			}
			break;
			}
			break;
			case 17: // 29 strings to match.
			if (memcmp(NameR.data()+0, "pc.altivec.", 11))
			break;
			switch (NameR[11]) {
			default: break;
			case 'd': // 2 strings to match.
			if (NameR[12] != 's')
			break;
			switch (NameR[13]) {
			default: break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+14, "all", 3))
	break;		break;
	switch (NameR[8]) {		return Intrinsic::ppc_altivec_dssall; // "pc.altivec.dssa
			ll"
			case 't': // 1 string to match.
			if (memcmp(NameR.data()+14, "stt", 3))
			break;
			return Intrinsic::ppc_altivec_dststt; // "pc.altivec.dsts
			tt"
			}
			break;
			case 'm': // 2 strings to match.
			switch (NameR[12]) {
			default: break;
			case 'f': // 1 string to match.
			if (memcmp(NameR.data()+13, "vscr", 4))
			break;
			return Intrinsic::ppc_altivec_mfvscr; // "pc.altivec.mfvs
			cr"
			case 't': // 1 string to match.
			if (memcmp(NameR.data()+13, "vscr", 4))
			break;
			return Intrinsic::ppc_altivec_mtvscr; // "pc.altivec.mtvs
			cr"
			}
			break;
			case 's': // 3 strings to match.
			if (memcmp(NameR.data()+12, "tve", 3))
			break;
			switch (NameR[15]) {
			default: break;
			case 'b': // 1 string to match.
			if (NameR[16] != 'x')
			break;
			return Intrinsic::ppc_altivec_stvebx; // "pc.altivec.stve
			bx"
			case 'h': // 1 string to match.
			if (NameR[16] != 'x')
			break;
			return Intrinsic::ppc_altivec_stvehx; // "pc.altivec.stve
			hx"
			case 'w': // 1 string to match.
			if (NameR[16] != 'x')
			break;
			return Intrinsic::ppc_altivec_stvewx; // "pc.altivec.stve
			wx"
			}
			break;
			case 'v': // 22 strings to match.
			switch (NameR[12]) {
			default: break;
			case 'a': // 6 strings to match.
			if (memcmp(NameR.data()+13, "vg", 2))
			break;
			switch (NameR[15]) {
	default: break;		default: break;
	case 'f': // 4 strings to match.		case 's': // 3 strings to match.
	if (memcmp(NameR.data()+9, "rcz.", 4))		switch (NameR[16]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::ppc_altivec_vavgsb; // "pc.altivec.vavg
			sb"
			case 'h': // 1 string to match.
			return Intrinsic::ppc_altivec_vavgsh; // "pc.altivec.vavg
			sh"
			case 'w': // 1 string to match.
			return Intrinsic::ppc_altivec_vavgsw; // "pc.altivec.vavg
			sw"
			}
			break;
			case 'u': // 3 strings to match.
			switch (NameR[16]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::ppc_altivec_vavgub; // "pc.altivec.vavg
			ub"
			case 'h': // 1 string to match.
			return Intrinsic::ppc_altivec_vavguh; // "pc.altivec.vavg
			uh"
			case 'w': // 1 string to match.
			return Intrinsic::ppc_altivec_vavguw; // "pc.altivec.vavg
			uw"
			}
			break;
			}
			break;
			case 'c': // 2 strings to match.
			if (NameR[13] != 't')
			break;
			switch (NameR[14]) {
			default: break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+15, "xs", 2))
	break;		break;
	switch (NameR[13]) {		return Intrinsic::ppc_altivec_vctsxs; // "pc.altivec.vcts
			xs"
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+15, "xs", 2))
			break;
			return Intrinsic::ppc_altivec_vctuxs; // "pc.altivec.vctu
			xs"
			}
			break;
			case 'm': // 14 strings to match.
			switch (NameR[13]) {
			default: break;
			case 'a': // 7 strings to match.
			if (NameR[14] != 'x')
			break;
			switch (NameR[15]) {
	default: break;		default: break;
	case 'p': // 2 strings to match.		case 'f': // 1 string to match.
	switch (NameR[14]) {		if (NameR[16] != 'p')
			break;
			return Intrinsic::ppc_altivec_vmaxfp; // "pc.altivec.vmax
			fp"
			case 's': // 3 strings to match.
			switch (NameR[16]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::x86_xop_vfrcz_pd; // "86.xop.vfrcz.pd		return Intrinsic::ppc_altivec_vmaxsb; // "pc.altivec.vmax
	"		sb"
	case 's': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::x86_xop_vfrcz_ps; // "86.xop.vfrcz.ps		return Intrinsic::ppc_altivec_vmaxsh; // "pc.altivec.vmax
	"		sh"
			case 'w': // 1 string to match.
			return Intrinsic::ppc_altivec_vmaxsw; // "pc.altivec.vmax
			sw"
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 'u': // 3 strings to match.
	switch (NameR[14]) {		switch (NameR[16]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::x86_xop_vfrcz_sd; // "86.xop.vfrcz.sd		return Intrinsic::ppc_altivec_vmaxub; // "pc.altivec.vmax
	"		ub"
	case 's': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::x86_xop_vfrcz_ss; // "86.xop.vfrcz.ss		return Intrinsic::ppc_altivec_vmaxuh; // "pc.altivec.vmax
	"		uh"
			case 'w': // 1 string to match.
			return Intrinsic::ppc_altivec_vmaxuw; // "pc.altivec.vmax
			uw"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'p': // 12 strings to match.		case 'i': // 7 strings to match.
	switch (NameR[9]) {		if (NameR[14] != 'n')
			break;
			switch (NameR[15]) {
	default: break;		default: break;
	case 'h': // 9 strings to match.		case 'f': // 1 string to match.
	switch (NameR[10]) {		if (NameR[16] != 'p')
	default: break;
	case 'a': // 6 strings to match.
	if (memcmp(NameR.data()+11, "dd", 2))
	break;
	switch (NameR[13]) {
	default: break;
	case 'b': // 3 strings to match.
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_xop_vphaddbd; // "86.xop.
	vphaddbd"
	case 'q': // 1 string to match.
	return Intrinsic::x86_xop_vphaddbq; // "86.xop.
	vphaddbq"
	case 'w': // 1 string to match.
	return Intrinsic::x86_xop_vphaddbw; // "86.xop.
	vphaddbw"
	}
	break;
	case 'd': // 1 string to match.
	if (NameR[14] != 'q')
	break;
	return Intrinsic::x86_xop_vphadddq; // "86.xop.vphadddq
	"
	case 'w': // 2 strings to match.
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_xop_vphaddwd; // "86.xop.
	vphaddwd"
	case 'q': // 1 string to match.
	return Intrinsic::x86_xop_vphaddwq; // "86.xop.
	vphaddwq"
	}
	break;
	}
	break;
	case 's': // 3 strings to match.
	if (memcmp(NameR.data()+11, "ub", 2))
	break;
	switch (NameR[13]) {
	default: break;
	case 'b': // 1 string to match.
	if (NameR[14] != 'w')
	break;
	return Intrinsic::x86_xop_vphsubbw; // "86.xop.vphsubbw
	"
	case 'd': // 1 string to match.
	if (NameR[14] != 'q')
	break;
	return Intrinsic::x86_xop_vphsubdq; // "86.xop.vphsubdq
	"
	case 'w': // 1 string to match.
	if (NameR[14] != 'd')
	break;
	return Intrinsic::x86_xop_vphsubwd; // "86.xop.vphsubwd
	"
	}
	break;		break;
			return Intrinsic::ppc_altivec_vminfp; // "pc.altivec.vmin
			fp"
			case 's': // 3 strings to match.
			switch (NameR[16]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::ppc_altivec_vminsb; // "pc.altivec.vmin
			sb"
			case 'h': // 1 string to match.
			return Intrinsic::ppc_altivec_vminsh; // "pc.altivec.vmin
			sh"
			case 'w': // 1 string to match.
			return Intrinsic::ppc_altivec_vminsw; // "pc.altivec.vmin
			sw"
	}		}
	break;		break;
	case 'm': // 3 strings to match.		case 'u': // 3 strings to match.
	if (memcmp(NameR.data()+10, "acs", 3))		switch (NameR[16]) {
	break;
	switch (NameR[13]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'b': // 1 string to match.
	if (NameR[14] != 'd')		return Intrinsic::ppc_altivec_vminub; // "pc.altivec.vmin
	break;		ub"
	return Intrinsic::x86_xop_vpmacsdd; // "86.xop.vpmacsdd		case 'h': // 1 string to match.
	"		return Intrinsic::ppc_altivec_vminuh; // "pc.altivec.vmin
	case 'w': // 2 strings to match.		uh"
	switch (NameR[14]) {		case 'w': // 1 string to match.
	default: break;		return Intrinsic::ppc_altivec_vminuw; // "pc.altivec.vmin
	case 'd': // 1 string to match.		uw"
	return Intrinsic::x86_xop_vpmacswd; // "86.xop.vpmacswd
	"
	case 'w': // 1 string to match.
	return Intrinsic::x86_xop_vpmacsww; // "86.xop.vpmacsww
	"
	}
	break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'c': // 1 string to match.
	if (memcmp(NameR.data()+1, "ore.checkevent", 14))
	break;
	return Intrinsic::xcore_checkevent; // "core.checkevent"
	}		}
	break;		break;
	case 16: // 112 strings to match.		case 18: // 38 strings to match.
	if (memcmp(NameR.data()+0, "86.", 3))		if (memcmp(NameR.data()+0, "pc.altivec.v", 12))
	break;		break;
	switch (NameR[3]) {		switch (NameR[12]) {
	default: break;		default: break;
	case '3': // 8 strings to match.		case 'a': // 7 strings to match.
	if (memcmp(NameR.data()+4, "dnow", 4))		if (memcmp(NameR.data()+13, "dd", 2))
	break;		break;
	switch (NameR[8]) {		switch (NameR[15]) {
	default: break;		default: break;
	case '.': // 6 strings to match.		case 'c': // 1 string to match.
	if (NameR[9] != 'p')		if (memcmp(NameR.data()+16, "uw", 2))
	break;		break;
	switch (NameR[10]) {		return Intrinsic::ppc_altivec_vaddcuw; // "pc.altivec.vadd
			cuw"
			case 's': // 3 strings to match.
			switch (NameR[16]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(NameR.data()+11, "vgusb", 5))		if (NameR[17] != 's')
	break;		break;
	return Intrinsic::x86_3dnow_pavgusb; // "86.3dnow.pavgus		return Intrinsic::ppc_altivec_vaddsbs; // "pc.altivec.vadd
	b"		sbs"
	case 'f': // 4 strings to match.		case 'h': // 1 string to match.
	switch (NameR[11]) {		if (NameR[17] != 's')
	default: break;
	case 'c': // 3 strings to match.
	if (memcmp(NameR.data()+12, "mp", 2))
	break;
	switch (NameR[14]) {
	default: break;
	case 'e': // 1 string to match.
	if (NameR[15] != 'q')
	break;
	return Intrinsic::x86_3dnow_pfcmpeq; // "86.3dnow.pfcmpe
	q"
	case 'g': // 2 strings to match.
	switch (NameR[15]) {
	default: break;
	case 'e': // 1 string to match.
	return Intrinsic::x86_3dnow_pfcmpge; // "86.3dnow.pfcmpg
	e"
	case 't': // 1 string to match.
	return Intrinsic::x86_3dnow_pfcmpgt; // "86.3dnow.pfcmpg
	t"
	}
	break;
	}
	break;		break;
	case 'r': // 1 string to match.		return Intrinsic::ppc_altivec_vaddshs; // "pc.altivec.vadd
	if (memcmp(NameR.data()+12, "sqrt", 4))		shs"
	break;		case 'w': // 1 string to match.
	return Intrinsic::x86_3dnow_pfrsqrt; // "86.3dnow.pfrsqr		if (NameR[17] != 's')
	t"
	}
	break;
	case 'm': // 1 string to match.
	if (memcmp(NameR.data()+11, "ulhrw", 5))
	break;		break;
	return Intrinsic::x86_3dnow_pmulhrw; // "86.3dnow.pmulhr w"		return Intrinsic::ppc_altivec_vaddsws; // "pc.altivec.vadd sws"
	}		}
	break;		break;
	case 'a': // 2 strings to match.		case 'u': // 3 strings to match.
	if (memcmp(NameR.data()+9, ".p", 2))		switch (NameR[16]) {
	break;
	switch (NameR[11]) {
	default: break;		default: break;
	case 'f': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(NameR.data()+12, "nacc", 4))		if (NameR[17] != 's')
	break;		break;
	return Intrinsic::x86_3dnowa_pfnacc; // "86.3dnowa.pfnac		return Intrinsic::ppc_altivec_vaddubs; // "pc.altivec.vadd
	c"		ubs"
	case 's': // 1 string to match.		case 'h': // 1 string to match.
	if (memcmp(NameR.data()+12, "wapd", 4))		if (NameR[17] != 's')
	break;		break;
	return Intrinsic::x86_3dnowa_pswapd; // "86.3dnowa.pswap		return Intrinsic::ppc_altivec_vadduhs; // "pc.altivec.vadd
	d"		uhs"
			case 'w': // 1 string to match.
			if (NameR[17] != 's')
			break;
			return Intrinsic::ppc_altivec_vadduws; // "pc.altivec.vadd
			uws"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'a': // 33 strings to match.		case 'c': // 1 string to match.
	if (memcmp(NameR.data()+4, "vx", 2))		if (memcmp(NameR.data()+13, "mpbfp", 5))
	break;		break;
	switch (NameR[6]) {		return Intrinsic::ppc_altivec_vcmpbfp; // "pc.altivec.vcmpbfp"
			case 'l': // 1 string to match.
			if (memcmp(NameR.data()+13, "ogefp", 5))
			break;
			return Intrinsic::ppc_altivec_vlogefp; // "pc.altivec.vlogefp"
			case 'm': // 9 strings to match.
			switch (NameR[13]) {
	default: break;		default: break;
	case '.': // 5 strings to match.		case 'a': // 1 string to match.
	switch (NameR[7]) {		if (memcmp(NameR.data()+14, "ddfp", 4))
			break;
			return Intrinsic::ppc_altivec_vmaddfp; // "pc.altivec.vmad
			dfp"
			case 'u': // 8 strings to match.
			if (NameR[14] != 'l')
			break;
			switch (NameR[15]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'e': // 4 strings to match.
	if (memcmp(NameR.data()+8, "p.ps.256", 8))		switch (NameR[16]) {
	break;
	return Intrinsic::x86_avx_dp_ps_256; // "86.avx.dp.ps.25
	6"
	case 'v': // 4 strings to match.
	if (memcmp(NameR.data()+8, "test", 4))
	break;
	switch (NameR[12]) {
	default: break;		default: break;
	case 'c': // 2 strings to match.		case 's': // 2 strings to match.
	if (memcmp(NameR.data()+13, ".p", 2))		switch (NameR[17]) {
	break;
	switch (NameR[15]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::x86_avx_vtestc_pd; // "86.avx.vtestc.p		return Intrinsic::ppc_altivec_vmulesb; // "pc.altivec.vmul
	d"		esb"
	case 's': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::x86_avx_vtestc_ps; // "86.avx.vtestc.p		return Intrinsic::ppc_altivec_vmulesh; // "pc.altivec.vmul
	s"		esh"
	}		}
	break;		break;
	case 'z': // 2 strings to match.		case 'u': // 2 strings to match.
	if (memcmp(NameR.data()+13, ".p", 2))		switch (NameR[17]) {
	break;
	switch (NameR[15]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::x86_avx_vtestz_pd; // "86.avx.vtestz.p		return Intrinsic::ppc_altivec_vmuleub; // "pc.altivec.vmul
	d"		eub"
	case 's': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::x86_avx_vtestz_ps; // "86.avx.vtestz.p		return Intrinsic::ppc_altivec_vmuleuh; // "pc.altivec.vmul
	s"		euh"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'o': // 4 strings to match.
	break;		switch (NameR[16]) {
	case '2': // 28 strings to match.
	if (NameR[7] != '.')
	break;
	switch (NameR[8]) {
	default: break;
	case 'm': // 1 string to match.
	if (memcmp(NameR.data()+9, "ovntdqa", 7))
	break;
	return Intrinsic::x86_avx2_movntdqa; // "86.avx2.movntdq
	a"
	case 'p': // 27 strings to match.
	switch (NameR[9]) {
	default: break;		default: break;
	case 'a': // 6 strings to match.		case 's': // 2 strings to match.
	switch (NameR[10]) {		switch (NameR[17]) {
	default: break;
	case 'c': // 4 strings to match.
	if (NameR[11] != 'k')
	break;
	switch (NameR[12]) {
	default: break;
	case 's': // 2 strings to match.
	if (NameR[13] != 's')
	break;
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	if (NameR[15] != 'w')
	break;
	return Intrinsic::x86_avx2_packssdw; // "86.avx2
	.packssdw"
	case 'w': // 1 string to match.
	if (NameR[15] != 'b')
	break;
	return Intrinsic::x86_avx2_packsswb; // "86.avx2
	.packsswb"
	}
	break;
	case 'u': // 2 strings to match.
	if (NameR[13] != 's')
	break;
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	if (NameR[15] != 'w')
	break;
	return Intrinsic::x86_avx2_packusdw; // "86.avx2
	.packusdw"
	case 'w': // 1 string to match.
	if (NameR[15] != 'b')
	break;
	return Intrinsic::x86_avx2_packuswb; // "86.avx2
	.packuswb"
	}
	break;
	}
	break;
	case 'd': // 2 strings to match.
	if (memcmp(NameR.data()+11, "dus.", 4))
	break;
	switch (NameR[15]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::x86_avx2_paddus_b; // "86.avx2.paddus.
	b"
	case 'w': // 1 string to match.
	return Intrinsic::x86_avx2_paddus_w; // "86.avx2.paddus.
	w"
	}
	break;
	}
	break;
	case 'b': // 1 string to match.
	if (memcmp(NameR.data()+10, "lendvb", 6))
	break;
	return Intrinsic::x86_avx2_pblendvb; // "86.avx2.pblendv
	b"
	case 'h': // 2 strings to match.
	switch (NameR[10]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(NameR.data()+11, "dd.sw", 5))
	break;
	return Intrinsic::x86_avx2_phadd_sw; // "86.avx2.phadd.s
	w"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+11, "ub.sw", 5))
	break;
	return Intrinsic::x86_avx2_phsub_sw; // "86.avx2.phsub.s
	w"
	}
	break;
	case 'm': // 16 strings to match.
	switch (NameR[10]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(NameR.data()+11, "dd.wd", 5))		return Intrinsic::ppc_altivec_vmulosb; // "pc.altivec.vmul
	break;		osb"
	return Intrinsic::x86_avx2_pmadd_wd; // "86.avx2.pmadd.w		case 'h': // 1 string to match.
	d"		return Intrinsic::ppc_altivec_vmulosh; // "pc.altivec.vmul
	case 'o': // 13 strings to match.		osh"
	if (NameR[11] != 'v')
	break;
	switch (NameR[12]) {
	default: break;
	case 'm': // 1 string to match.
	if (memcmp(NameR.data()+13, "skb", 3))
	break;
	return Intrinsic::x86_avx2_pmovmskb; // "86.avx2.pmovmsk
	b"
	case 's': // 6 strings to match.
	if (NameR[13] != 'x')
	break;
	switch (NameR[14]) {
	default: break;
	case 'b': // 3 strings to match.
	switch (NameR[15]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_avx2_pmovsxbd; // "86.avx2
	.pmovsxbd"
	case 'q': // 1 string to match.
	return Intrinsic::x86_avx2_pmovsxbq; // "86.avx2
	.pmovsxbq"
	case 'w': // 1 string to match.
	return Intrinsic::x86_avx2_pmovsxbw; // "86.avx2
	.pmovsxbw"
	}
	break;
	case 'd': // 1 string to match.
	if (NameR[15] != 'q')
	break;
	return Intrinsic::x86_avx2_pmovsxdq; // "86.avx2
	.pmovsxdq"
	case 'w': // 2 strings to match.
	switch (NameR[15]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_avx2_pmovsxwd; // "86.avx2
	.pmovsxwd"
	case 'q': // 1 string to match.
	return Intrinsic::x86_avx2_pmovsxwq; // "86.avx2
	.pmovsxwq"
	}
	break;
	}
	break;
	case 'z': // 6 strings to match.
	if (NameR[13] != 'x')
	break;
	switch (NameR[14]) {
	default: break;
	case 'b': // 3 strings to match.
	switch (NameR[15]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_avx2_pmovzxbd; // "86.avx2
	.pmovzxbd"
	case 'q': // 1 string to match.
	return Intrinsic::x86_avx2_pmovzxbq; // "86.avx2
	.pmovzxbq"
	case 'w': // 1 string to match.
	return Intrinsic::x86_avx2_pmovzxbw; // "86.avx2
	.pmovzxbw"
	}
	break;
	case 'd': // 1 string to match.
	if (NameR[15] != 'q')
	break;
	return Intrinsic::x86_avx2_pmovzxdq; // "86.avx2
	.pmovzxdq"
	case 'w': // 2 strings to match.
	switch (NameR[15]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_avx2_pmovzxwd; // "86.avx2
	.pmovzxwd"
	case 'q': // 1 string to match.
	return Intrinsic::x86_avx2_pmovzxwq; // "86.avx2
	.pmovzxwq"
	}
	break;
	}
	break;
	}
	break;
	case 'u': // 2 strings to match.
	if (NameR[11] != 'l')
	break;
	switch (NameR[12]) {
	default: break;
	case 'h': // 1 string to match.
	if (memcmp(NameR.data()+13, "u.w", 3))
	break;
	return Intrinsic::x86_avx2_pmulhu_w; // "86.avx2.pmulhu.
	w"
	case 'u': // 1 string to match.
	if (memcmp(NameR.data()+13, ".dq", 3))
	break;
	return Intrinsic::x86_avx2_pmulu_dq; // "86.avx2.pmulu.d
	q"
	}
	break;
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 'u': // 2 strings to match.
	if (memcmp(NameR.data()+10, "ubus.", 5))		switch (NameR[17]) {
	break;
	switch (NameR[15]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::x86_avx2_psubus_b; // "86.avx2.psubus.		return Intrinsic::ppc_altivec_vmuloub; // "pc.altivec.vmul
	b"		oub"
	case 'w': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::x86_avx2_psubus_w; // "86.avx2.psubus.		return Intrinsic::ppc_altivec_vmulouh; // "pc.altivec.vmul
	w"		ouh"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'f': // 8 strings to match.		case 'p': // 6 strings to match.
	if (memcmp(NameR.data()+4, "ma.vfm", 6))		if (NameR[13] != 'k')
	break;		break;
	switch (NameR[10]) {		switch (NameR[14]) {
	default: break;		default: break;
	case 'a': // 4 strings to match.		case 's': // 4 strings to match.
	if (memcmp(NameR.data()+11, "dd.", 3))		switch (NameR[15]) {
	break;
	switch (NameR[14]) {
	default: break;		default: break;
	case 'p': // 2 strings to match.		case 'h': // 2 strings to match.
	switch (NameR[15]) {		switch (NameR[16]) {
	default: break;		default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_fma_vfmadd_pd; // "86.fma.vfmadd.p
	d"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	return Intrinsic::x86_fma_vfmadd_ps; // "86.fma.vfmadd.p		if (NameR[17] != 's')
	s"		break;
			return Intrinsic::ppc_altivec_vpkshss; // "pc.altivec.vpks
			hss"
			case 'u': // 1 string to match.
			if (NameR[17] != 's')
			break;
			return Intrinsic::ppc_altivec_vpkshus; // "pc.altivec.vpks
			hus"
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 'w': // 2 strings to match.
	switch (NameR[15]) {		switch (NameR[16]) {
	default: break;		default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_fma_vfmadd_sd; // "86.fma.vfmadd.s
	d"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	return Intrinsic::x86_fma_vfmadd_ss; // "86.fma.vfmadd.s		if (NameR[17] != 's')
	s"		break;
			return Intrinsic::ppc_altivec_vpkswss; // "pc.altivec.vpks
			wss"
			case 'u': // 1 string to match.
			if (NameR[17] != 's')
			break;
			return Intrinsic::ppc_altivec_vpkswus; // "pc.altivec.vpks
			wus"
	}		}
	break;		break;
	}		}
	break;		break;
	case 's': // 4 strings to match.		case 'u': // 2 strings to match.
	if (memcmp(NameR.data()+11, "ub.", 3))		switch (NameR[15]) {
	break;
	switch (NameR[14]) {
	default: break;		default: break;
	case 'p': // 2 strings to match.		case 'h': // 1 string to match.
	switch (NameR[15]) {		if (memcmp(NameR.data()+16, "us", 2))
	default: break;		break;
	case 'd': // 1 string to match.		return Intrinsic::ppc_altivec_vpkuhus; // "pc.altivec.vpku
	return Intrinsic::x86_fma_vfmsub_pd; // "86.fma.vfmsub.p		hus"
	d"		case 'w': // 1 string to match.
	case 's': // 1 string to match.		if (memcmp(NameR.data()+16, "us", 2))
	return Intrinsic::x86_fma_vfmsub_ps; // "86.fma.vfmsub.p		break;
	s"		return Intrinsic::ppc_altivec_vpkuwus; // "pc.altivec.vpku
	}		wus"
	break;
	case 's': // 2 strings to match.
	switch (NameR[15]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_fma_vfmsub_sd; // "86.fma.vfmsub.s
	d"
	case 's': // 1 string to match.
	return Intrinsic::x86_fma_vfmsub_ss; // "86.fma.vfmsub.s
	s"
	}
	break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'm': // 7 strings to match.		case 's': // 8 strings to match.
	if (memcmp(NameR.data()+4, "mx.p", 4))		if (NameR[13] != 'u')
	break;		break;
	switch (NameR[8]) {		switch (NameR[14]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'b': // 7 strings to match.
	if (memcmp(NameR.data()+9, "lignr.b", 7))		switch (NameR[15]) {
	break;
	return Intrinsic::x86_mmx_palignr_b; // "86.mmx.palignr.b"
	case 'u': // 6 strings to match.
	if (memcmp(NameR.data()+9, "npck", 4))
	break;
	switch (NameR[13]) {
	default: break;		default: break;
	case 'h': // 3 strings to match.		case 'c': // 1 string to match.
	switch (NameR[14]) {		if (memcmp(NameR.data()+16, "uw", 2))
			break;
			return Intrinsic::ppc_altivec_vsubcuw; // "pc.altivec.vsub
			cuw"
			case 's': // 3 strings to match.
			switch (NameR[16]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'b': // 1 string to match.
	if (NameR[15] != 'w')		if (NameR[17] != 's')
	break;		break;
	return Intrinsic::x86_mmx_punpckhbw; // "86.mmx.punpckhb		return Intrinsic::ppc_altivec_vsubsbs; // "pc.altivec.vsub
	w"		sbs"
	case 'd': // 1 string to match.		case 'h': // 1 string to match.
	if (NameR[15] != 'q')		if (NameR[17] != 's')
	break;		break;
	return Intrinsic::x86_mmx_punpckhdq; // "86.mmx.punpckhd q"		return Intrinsic::ppc_altivec_vsubshs; // "pc.altivec.vsub shs"
	case 'w': // 1 string to match.		case 'w': // 1 string to match.
	if (NameR[15] != 'd')		if (NameR[17] != 's')
	break;		break;
	return Intrinsic::x86_mmx_punpckhwd; // "86.mmx.punpckhw d"		return Intrinsic::ppc_altivec_vsubsws; // "pc.altivec.vsub sws"
	}		}
	break;		break;
	case 'l': // 3 strings to match.		case 'u': // 3 strings to match.
	switch (NameR[14]) {		switch (NameR[16]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'b': // 1 string to match.
	if (NameR[15] != 'w')		if (NameR[17] != 's')
	break;		break;
	return Intrinsic::x86_mmx_punpcklbw; // "86.mmx.punpcklb		return Intrinsic::ppc_altivec_vsububs; // "pc.altivec.vsub
	w"		ubs"
	case 'd': // 1 string to match.		case 'h': // 1 string to match.
	if (NameR[15] != 'q')		if (NameR[17] != 's')
	break;		break;
	return Intrinsic::x86_mmx_punpckldq; // "86.mmx.punpckld q"		return Intrinsic::ppc_altivec_vsubuhs; // "pc.altivec.vsub uhs"
	case 'w': // 1 string to match.		case 'w': // 1 string to match.
	if (NameR[15] != 'd')		if (NameR[17] != 's')
	break;		break;
	return Intrinsic::x86_mmx_punpcklwd; // "86.mmx.punpcklw d"		return Intrinsic::ppc_altivec_vsubuws; // "pc.altivec.vsub uws"
	}		}
	break;		break;
	}		}
	break;		break;
			case 'm': // 1 string to match.
			if (memcmp(NameR.data()+15, "sws", 3))
			break;
			return Intrinsic::ppc_altivec_vsumsws; // "pc.altivec.vsum
			sws"
	}		}
	break;		break;
	case 's': // 40 strings to match.		case 'u': // 6 strings to match.
	if (NameR[4] != 's')		if (memcmp(NameR.data()+13, "pk", 2))
	break;		break;
	switch (NameR[5]) {		switch (NameR[15]) {
	default: break;		default: break;
	case 'e': // 32 strings to match.		case 'h': // 3 strings to match.
	switch (NameR[6]) {		switch (NameR[16]) {
	default: break;		default: break;
	case '.': // 10 strings to match.		case 'p': // 1 string to match.
	switch (NameR[7]) {		if (NameR[17] != 'x')
			break;
			return Intrinsic::ppc_altivec_vupkhpx; // "pc.altivec.vupk
			hpx"
			case 's': // 2 strings to match.
			switch (NameR[17]) {
	default: break;		default: break;
	case 'c': // 8 strings to match.		case 'b': // 1 string to match.
	switch (NameR[8]) {		return Intrinsic::ppc_altivec_vupkhsb; // "pc.altivec.vupk
			hsb"
			case 'h': // 1 string to match.
			return Intrinsic::ppc_altivec_vupkhsh; // "pc.altivec.vupk
			hsh"
			}
			break;
			}
			break;
			case 'l': // 3 strings to match.
			switch (NameR[16]) {
			default: break;
			case 'p': // 1 string to match.
			if (NameR[17] != 'x')
			break;
			return Intrinsic::ppc_altivec_vupklpx; // "pc.altivec.vupk
			lpx"
			case 's': // 2 strings to match.
			switch (NameR[17]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::ppc_altivec_vupklsb; // "pc.altivec.vupk
			lsb"
			case 'h': // 1 string to match.
			return Intrinsic::ppc_altivec_vupklsh; // "pc.altivec.vupk
			lsh"
			}
			break;
			}
			break;
			}
			break;
			}
			break;
			case 19: // 29 strings to match.
			switch (NameR[0]) {
			default: break;
			case 'p': // 24 strings to match.
			if (memcmp(NameR.data()+1, "c.altivec.v", 11))
			break;
			switch (NameR[12]) {
			default: break;
			case 'c': // 12 strings to match.
			if (memcmp(NameR.data()+13, "mp", 2))
			break;
			switch (NameR[15]) {
			default: break;
			case 'e': // 4 strings to match.
			if (NameR[16] != 'q')
			break;
			switch (NameR[17]) {
			default: break;
			case 'f': // 1 string to match.
			if (NameR[18] != 'p')
			break;
			return Intrinsic::ppc_altivec_vcmpeqfp; // "pc.altivec.vcmp
			eqfp"
			case 'u': // 3 strings to match.
			switch (NameR[18]) {
	default: break;		default: break;
	case 'o': // 5 strings to match.		case 'b': // 1 string to match.
	if (memcmp(NameR.data()+9, "mi", 2))		return Intrinsic::ppc_altivec_vcmpequb; // "pc.alti
	break;		vec.vcmpequb"
	switch (NameR[11]) {		case 'h': // 1 string to match.
	default: break;		return Intrinsic::ppc_altivec_vcmpequh; // "pc.alti
	case 'e': // 1 string to match.		vec.vcmpequh"
	if (memcmp(NameR.data()+12, "q.ss", 4))		case 'w': // 1 string to match.
	break;		return Intrinsic::ppc_altivec_vcmpequw; // "pc.alti
	return Intrinsic::x86_sse_comieq_ss; // "86.sse.comieq.s		vec.vcmpequw"
	s"
	case 'g': // 2 strings to match.
	switch (NameR[12]) {
	default: break;
	case 'e': // 1 string to match.
	if (memcmp(NameR.data()+13, ".ss", 3))
	break;
	return Intrinsic::x86_sse_comige_ss; // "86.sse.
	comige.ss"
	case 't': // 1 string to match.
	if (memcmp(NameR.data()+13, ".ss", 3))
	break;
	return Intrinsic::x86_sse_comigt_ss; // "86.sse.
	comigt.ss"
	}
	break;
	case 'l': // 2 strings to match.
	switch (NameR[12]) {
	default: break;
	case 'e': // 1 string to match.
	if (memcmp(NameR.data()+13, ".ss", 3))
	break;
	return Intrinsic::x86_sse_comile_ss; // "86.sse.
	comile.ss"
	case 't': // 1 string to match.
	if (memcmp(NameR.data()+13, ".ss", 3))
	break;
	return Intrinsic::x86_sse_comilt_ss; // "86.sse.
	comilt.ss"
	}
	break;
	}
	break;
	case 'v': // 3 strings to match.
	if (memcmp(NameR.data()+9, "tt", 2))
	break;
	switch (NameR[11]) {
	default: break;
	case 'p': // 2 strings to match.
	switch (NameR[12]) {
	default: break;
	case 'd': // 1 string to match.
	if (memcmp(NameR.data()+13, "2pi", 3))
	break;
	return Intrinsic::x86_sse_cvttpd2pi; // "86.sse.
	cvttpd2pi"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+13, "2pi", 3))
	break;
	return Intrinsic::x86_sse_cvttps2pi; // "86.sse.
	cvttps2pi"
	}
	break;
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+12, "s2si", 4))
	break;
	return Intrinsic::x86_sse_cvttss2si; // "86.sse.cvttss2s
	i"
	}
	break;
	}		}
	break;		break;
	case 'm': // 1 string to match.
	if (memcmp(NameR.data()+8, "ovmsk.ps", 8))
	break;
	return Intrinsic::x86_sse_movmsk_ps; // "86.sse.movmsk.p
	s"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+8, "toreu.ps", 8))
	break;
	return Intrinsic::x86_sse_storeu_ps; // "86.sse.storeu.p
	s"
	}		}
	break;		break;
	case '2': // 17 strings to match.		case 'g': // 8 strings to match.
	if (NameR[7] != '.')		switch (NameR[16]) {
	break;
	switch (NameR[8]) {
	default: break;		default: break;
	case 'c': // 10 strings to match.		case 'e': // 1 string to match.
	if (memcmp(NameR.data()+9, "vt", 2))		if (memcmp(NameR.data()+17, "fp", 2))
	break;
	switch (NameR[11]) {
	default: break;
	case 'd': // 2 strings to match.
	if (memcmp(NameR.data()+12, "q2p", 3))
	break;
	switch (NameR[15]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse2_cvtdq2pd; // "86.sse2.cvtdq2p
	d"
	case 's': // 1 string to match.
	return Intrinsic::x86_sse2_cvtdq2ps; // "86.sse2.cvtdq2p
	s"
	}
	break;
	case 'p': // 4 strings to match.
	switch (NameR[12]) {
	default: break;
	case 'd': // 2 strings to match.
	if (NameR[13] != '2')
	break;
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	if (NameR[15] != 'q')
	break;
	return Intrinsic::x86_sse2_cvtpd2dq; // "86.sse2
	.cvtpd2dq"
	case 'p': // 1 string to match.
	if (NameR[15] != 's')
	break;
	return Intrinsic::x86_sse2_cvtpd2ps; // "86.sse2
	.cvtpd2ps"
	}
	break;
	case 's': // 2 strings to match.
	if (NameR[13] != '2')
	break;
	switch (NameR[14]) {
	default: break;
	case 'd': // 1 string to match.
	if (NameR[15] != 'q')
	break;
	return Intrinsic::x86_sse2_cvtps2dq; // "86.sse2
	.cvtps2dq"
	case 'p': // 1 string to match.
	if (NameR[15] != 'd')
	break;
	return Intrinsic::x86_sse2_cvtps2pd; // "86.sse2
	.cvtps2pd"
	}
	break;
	}
	break;
	case 's': // 4 strings to match.
	switch (NameR[12]) {
	default: break;
	case 'd': // 2 strings to match.
	if (memcmp(NameR.data()+13, "2s", 2))
	break;
	switch (NameR[15]) {
	default: break;
	case 'i': // 1 string to match.
	return Intrinsic::x86_sse2_cvtsd2si; // "86.sse2
	.cvtsd2si"
	case 's': // 1 string to match.
	return Intrinsic::x86_sse2_cvtsd2ss; // "86.sse2
	.cvtsd2ss"
	}
	break;
	case 'i': // 1 string to match.
	if (memcmp(NameR.data()+13, "2sd", 3))
	break;
	return Intrinsic::x86_sse2_cvtsi2sd; // "86.sse2.cvtsi2s
	d"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+13, "2sd", 3))
	break;
	return Intrinsic::x86_sse2_cvtss2sd; // "86.sse2.cvtss2s
	d"
	}
	break;		break;
	}		return Intrinsic::ppc_altivec_vcmpgefp; // "pc.altivec.vcmp
	break;		gefp"
	case 'p': // 7 strings to match.		case 't': // 7 strings to match.
	switch (NameR[9]) {		switch (NameR[17]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'f': // 1 string to match.
	if (memcmp(NameR.data()+10, "ddus.", 5))		if (NameR[18] != 'p')
	break;		break;
	switch (NameR[15]) {		return Intrinsic::ppc_altivec_vcmpgtfp; // "pc.alti
			vec.vcmpgtfp"
			case 's': // 3 strings to match.
			switch (NameR[18]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::x86_sse2_paddus_b; // "86.sse2.paddus.		return Intrinsic::ppc_altivec_vcmpgtsb; // "pc.alti
	b"		vec.vcmpgtsb"
			case 'h': // 1 string to match.
			return Intrinsic::ppc_altivec_vcmpgtsh; // "pc.alti
			vec.vcmpgtsh"
	case 'w': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::x86_sse2_paddus_w; // "86.sse2.paddus.		return Intrinsic::ppc_altivec_vcmpgtsw; // "pc.alti
	w"		vec.vcmpgtsw"
	}
	break;
	case 'm': // 3 strings to match.
	switch (NameR[10]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(NameR.data()+11, "dd.wd", 5))
	break;
	return Intrinsic::x86_sse2_pmadd_wd; // "86.sse2.pmadd.w
	d"
	case 'u': // 2 strings to match.
	if (NameR[11] != 'l')
	break;
	switch (NameR[12]) {
	default: break;
	case 'h': // 1 string to match.
	if (memcmp(NameR.data()+13, "u.w", 3))
	break;
	return Intrinsic::x86_sse2_pmulhu_w; // "86.sse2
	.pmulhu.w"
	case 'u': // 1 string to match.
	if (memcmp(NameR.data()+13, ".dq", 3))
	break;
	return Intrinsic::x86_sse2_pmulu_dq; // "86.sse2
	.pmulu.dq"
	}
	break;
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 'u': // 3 strings to match.
	if (memcmp(NameR.data()+10, "ubus.", 5))		switch (NameR[18]) {
	break;
	switch (NameR[15]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::x86_sse2_psubus_b; // "86.sse2.psubus.		return Intrinsic::ppc_altivec_vcmpgtub; // "pc.alti
	b"		vec.vcmpgtub"
			case 'h': // 1 string to match.
			return Intrinsic::ppc_altivec_vcmpgtuh; // "pc.alti
			vec.vcmpgtuh"
	case 'w': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::x86_sse2_psubus_w; // "86.sse2.psubus. w"		return Intrinsic::ppc_altivec_vcmpgtuw; // "pc.alti vec.vcmpgtuw"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case '4': // 5 strings to match.		}
	switch (NameR[7]) {		break;
			case 'e': // 1 string to match.
			if (memcmp(NameR.data()+13, "xptefp", 6))
			break;
			return Intrinsic::ppc_altivec_vexptefp; // "pc.altivec.vexp
			tefp"
			case 'm': // 6 strings to match.
			if (memcmp(NameR.data()+13, "sum", 3))
			break;
			switch (NameR[16]) {
			default: break;
			case 'm': // 1 string to match.
			if (memcmp(NameR.data()+17, "bm", 2))
			break;
			return Intrinsic::ppc_altivec_vmsummbm; // "pc.altivec.vmsu
			mmbm"
			case 's': // 2 strings to match.
			if (NameR[17] != 'h')
			break;
			switch (NameR[18]) {
	default: break;		default: break;
	case '1': // 4 strings to match.		case 'm': // 1 string to match.
	if (NameR[8] != '.')		return Intrinsic::ppc_altivec_vmsumshm; // "pc.altivec.vmsu
			mshm"
			case 's': // 1 string to match.
			return Intrinsic::ppc_altivec_vmsumshs; // "pc.altivec.vmsu
			mshs"
			}
			break;
			case 'u': // 3 strings to match.
			switch (NameR[17]) {
			default: break;
			case 'b': // 1 string to match.
			if (NameR[18] != 'm')
	break;		break;
	switch (NameR[9]) {		return Intrinsic::ppc_altivec_vmsumubm; // "pc.altivec.vmsu
			mubm"
			case 'h': // 2 strings to match.
			switch (NameR[18]) {
	default: break;		default: break;
	case 'b': // 2 strings to match.
	if (memcmp(NameR.data()+10, "lendp", 5))
	break;
	switch (NameR[15]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_blendpd; // "86.sse41.blendp
	d"
	case 's': // 1 string to match.
	return Intrinsic::x86_sse41_blendps; // "86.sse41.blendp
	s"
	}
	break;
	case 'm': // 1 string to match.		case 'm': // 1 string to match.
	if (memcmp(NameR.data()+10, "psadbw", 6))		return Intrinsic::ppc_altivec_vmsumuhm; // "pc.alti
	break;		vec.vmsumuhm"
	return Intrinsic::x86_sse41_mpsadbw; // "86.sse41.mpsadb		case 's': // 1 string to match.
	w"		return Intrinsic::ppc_altivec_vmsumuhs; // "pc.alti
	case 'p': // 1 string to match.		vec.vmsumuhs"
	if (memcmp(NameR.data()+10, "blendw", 6))
	break;
	return Intrinsic::x86_sse41_pblendw; // "86.sse41.pblend
	w"
	}		}
	break;		break;
	case 'a': // 1 string to match.
	if (memcmp(NameR.data()+8, ".insertq", 8))
	break;
	return Intrinsic::x86_sse4a_insertq; // "86.sse4a.insert
	q"
	}		}
	break;		break;
	}		}
	break;		break;
	case 's': // 8 strings to match.		case 'n': // 1 string to match.
	if (memcmp(NameR.data()+6, "e3.p", 4))		if (memcmp(NameR.data()+13, "msubfp", 6))
	break;		break;
	switch (NameR[10]) {		return Intrinsic::ppc_altivec_vnmsubfp; // "pc.altivec.vnms
			ubfp"
			case 's': // 4 strings to match.
			if (memcmp(NameR.data()+13, "um", 2))
			break;
			switch (NameR[15]) {
	default: break;		default: break;
	case 'h': // 4 strings to match.		case '2': // 1 string to match.
	switch (NameR[11]) {		if (memcmp(NameR.data()+16, "sws", 3))
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(NameR.data()+12, "dd.", 3))
	break;
	switch (NameR[15]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_ssse3_phadd_d; // "86.ssse3.phadd.
	d"
	case 'w': // 1 string to match.
	return Intrinsic::x86_ssse3_phadd_w; // "86.ssse3.phadd.
	w"
	}
	break;
	case 's': // 2 strings to match.
	if (memcmp(NameR.data()+12, "ub.", 3))
	break;
	switch (NameR[15]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_ssse3_phsub_d; // "86.ssse3.phsub.
	d"
	case 'w': // 1 string to match.
	return Intrinsic::x86_ssse3_phsub_w; // "86.ssse3.phsub.
	w"
	}
	break;		break;
	}		return Intrinsic::ppc_altivec_vsum2sws; // "pc.altivec.vsum
	break;		2sws"
	case 's': // 4 strings to match.		case '4': // 3 strings to match.
	switch (NameR[11]) {		switch (NameR[16]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 's': // 2 strings to match.
	if (memcmp(NameR.data()+12, "uf.b", 4))		switch (NameR[17]) {
	break;
	return Intrinsic::x86_ssse3_pshuf_b; // "86.ssse3.pshuf.
	b"
	case 'i': // 3 strings to match.
	if (memcmp(NameR.data()+12, "gn.", 3))
	break;
	switch (NameR[15]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::x86_ssse3_psign_b; // "86.ssse3.psign.		if (NameR[18] != 's')
	b"		break;
	case 'd': // 1 string to match.		return Intrinsic::ppc_altivec_vsum4sbs; // "pc.alti
	return Intrinsic::x86_ssse3_psign_d; // "86.ssse3.psign.		vec.vsum4sbs"
	d"		case 'h': // 1 string to match.
	case 'w': // 1 string to match.		if (NameR[18] != 's')
	return Intrinsic::x86_ssse3_psign_w; // "86.ssse3.psign.		break;
	w"		return Intrinsic::ppc_altivec_vsum4shs; // "pc.alti
			vec.vsum4shs"
	}		}
	break;		break;
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+17, "bs", 2))
			break;
			return Intrinsic::ppc_altivec_vsum4ubs; // "pc.altivec.vsum
			4ubs"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'v': // 4 strings to match.		case 't': // 5 strings to match.
	if (memcmp(NameR.data()+4, "cvtp", 4))		if (memcmp(NameR.data()+1, "x.read.lanemask.", 16))
	break;		break;
	switch (NameR[8]) {		switch (NameR[17]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'e': // 1 string to match.
	if (memcmp(NameR.data()+9, "2ps.", 4))		if (NameR[18] != 'q')
	break;		break;
	switch (NameR[13]) {		return Intrinsic::ptx_read_lanemask_eq; // "tx.read.lanemas
			k.eq"
			case 'g': // 2 strings to match.
			switch (NameR[18]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case 'e': // 1 string to match.
	if (memcmp(NameR.data()+14, "28", 2))		return Intrinsic::ptx_read_lanemask_ge; // "tx.read.lanemas
	break;		k.ge"
	return Intrinsic::x86_vcvtph2ps_128; // "86.vcvtph2ps.12		case 't': // 1 string to match.
	8"		return Intrinsic::ptx_read_lanemask_gt; // "tx.read.lanemas
	case '2': // 1 string to match.		k.gt"
	if (memcmp(NameR.data()+14, "56", 2))
	break;
	return Intrinsic::x86_vcvtph2ps_256; // "86.vcvtph2ps.25
	6"
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 'l': // 2 strings to match.
	if (memcmp(NameR.data()+9, "2ph.", 4))		switch (NameR[18]) {
	break;
	switch (NameR[13]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case 'e': // 1 string to match.
	if (memcmp(NameR.data()+14, "28", 2))		return Intrinsic::ptx_read_lanemask_le; // "tx.read.lanemas
	break;		k.le"
	return Intrinsic::x86_vcvtps2ph_128; // "86.vcvtps2ph.12		case 't': // 1 string to match.
	8"		return Intrinsic::ptx_read_lanemask_lt; // "tx.read.lanemas
	case '2': // 1 string to match.		k.lt"
	if (memcmp(NameR.data()+14, "56", 2))
	break;
	return Intrinsic::x86_vcvtps2ph_256; // "86.vcvtps2ph.25
	6"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'x': // 12 strings to match.		}
	if (memcmp(NameR.data()+4, "op.vp", 5))		break;
			case 20: // 4 strings to match.
			if (memcmp(NameR.data()+0, "pc.altivec.v", 12))
			break;
			switch (NameR[12]) {
			default: break;
			case 'c': // 1 string to match.
			if (memcmp(NameR.data()+13, "mpbfp.p", 7))
	break;		break;
	switch (NameR[9]) {		return Intrinsic::ppc_altivec_vcmpbfp_p; // "pc.altivec.vcmp
			bfp.p"
			case 'm': // 2 strings to match.
			switch (NameR[13]) {
	default: break;		default: break;
	case 'h': // 6 strings to match.		case 'h': // 1 string to match.
	if (memcmp(NameR.data()+10, "addu", 4))		if (memcmp(NameR.data()+14, "addshs", 6))
	break;		break;
	switch (NameR[14]) {		return Intrinsic::ppc_altivec_vmhaddshs; // "pc.altivec.vmha
	default: break;		ddshs"
	case 'b': // 3 strings to match.		case 'l': // 1 string to match.
	switch (NameR[15]) {		if (memcmp(NameR.data()+14, "adduhm", 6))
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_xop_vphaddubd; // "86.xop.vphaddub
	d"
	case 'q': // 1 string to match.
	return Intrinsic::x86_xop_vphaddubq; // "86.xop.vphaddub
	q"
	case 'w': // 1 string to match.
	return Intrinsic::x86_xop_vphaddubw; // "86.xop.vphaddub
	w"
	}
	break;		break;
	case 'd': // 1 string to match.		return Intrinsic::ppc_altivec_vmladduhm; // "pc.altivec.vmla
	if (NameR[15] != 'q')		dduhm"
			}
			break;
			case 'r': // 1 string to match.
			if (memcmp(NameR.data()+13, "sqrtefp", 7))
			break;
			return Intrinsic::ppc_altivec_vrsqrtefp; // "pc.altivec.vrsq
			rtefp"
			}
			break;
			case 21: // 13 strings to match.
			if (memcmp(NameR.data()+0, "pc.altivec.v", 12))
			break;
			switch (NameR[12]) {
			default: break;
			case 'c': // 12 strings to match.
			if (memcmp(NameR.data()+13, "mp", 2))
			break;
			switch (NameR[15]) {
			default: break;
			case 'e': // 4 strings to match.
			if (NameR[16] != 'q')
			break;
			switch (NameR[17]) {
			default: break;
			case 'f': // 1 string to match.
			if (memcmp(NameR.data()+18, "p.p", 3))
	break;		break;
	return Intrinsic::x86_xop_vphaddudq; // "86.xop.vphaddud		return Intrinsic::ppc_altivec_vcmpeqfp_p; // "pc.altivec.vcmp
	q"		eqfp.p"
	case 'w': // 2 strings to match.		case 'u': // 3 strings to match.
	switch (NameR[15]) {		switch (NameR[18]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::x86_xop_vphadduwd; // "86.xop.vphadduw		if (memcmp(NameR.data()+19, ".p", 2))
	d"		break;
	case 'q': // 1 string to match.		return Intrinsic::ppc_altivec_vcmpequb_p; // "pc.alti
	return Intrinsic::x86_xop_vphadduwq; // "86.xop.vphadduw		vec.vcmpequb.p"
	q"		case 'h': // 1 string to match.
			if (memcmp(NameR.data()+19, ".p", 2))
			break;
			return Intrinsic::ppc_altivec_vcmpequh_p; // "pc.alti
			vec.vcmpequh.p"
			case 'w': // 1 string to match.
			if (memcmp(NameR.data()+19, ".p", 2))
			break;
			return Intrinsic::ppc_altivec_vcmpequw_p; // "pc.alti
			vec.vcmpequw.p"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'm': // 6 strings to match.		case 'g': // 8 strings to match.
	if (NameR[10] != 'a')		switch (NameR[16]) {
	break;
	switch (NameR[11]) {
	default: break;		default: break;
	case 'c': // 5 strings to match.		case 'e': // 1 string to match.
	if (NameR[12] != 's')		if (memcmp(NameR.data()+17, "fp.p", 4))
	break;		break;
	switch (NameR[13]) {		return Intrinsic::ppc_altivec_vcmpgefp_p; // "pc.altivec.vcmp
			gefp.p"
			case 't': // 7 strings to match.
			switch (NameR[17]) {
	default: break;		default: break;
	case 'd': // 2 strings to match.		case 'f': // 1 string to match.
	if (NameR[14] != 'q')		if (memcmp(NameR.data()+18, "p.p", 3))
	break;		break;
	switch (NameR[15]) {		return Intrinsic::ppc_altivec_vcmpgtfp_p; // "pc.alti
			vec.vcmpgtfp.p"
			case 's': // 3 strings to match.
			switch (NameR[18]) {
	default: break;		default: break;
			case 'b': // 1 string to match.
			if (memcmp(NameR.data()+19, ".p", 2))
			break;
			return Intrinsic::ppc_altivec_vcmpgtsb_p; // "pc.alti
			vec.vcmpgtsb.p"
	case 'h': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::x86_xop_vpmacsdqh; // "86.xop.vpmacsdq		if (memcmp(NameR.data()+19, ".p", 2))
	h"		break;
	case 'l': // 1 string to match.		return Intrinsic::ppc_altivec_vcmpgtsh_p; // "pc.alti
	return Intrinsic::x86_xop_vpmacsdql; // "86.xop.vpmacsdq		vec.vcmpgtsh.p"
	l"		case 'w': // 1 string to match.
			if (memcmp(NameR.data()+19, ".p", 2))
			break;
			return Intrinsic::ppc_altivec_vcmpgtsw_p; // "pc.alti
			vec.vcmpgtsw.p"
	}		}
	break;		break;
	case 's': // 3 strings to match.		case 'u': // 3 strings to match.
	switch (NameR[14]) {		switch (NameR[18]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'b': // 1 string to match.
	if (NameR[15] != 'd')		if (memcmp(NameR.data()+19, ".p", 2))
	break;		break;
	return Intrinsic::x86_xop_vpmacssdd; // "86.xop.vpmacssd		return Intrinsic::ppc_altivec_vcmpgtub_p; // "pc.alti
	d"		vec.vcmpgtub.p"
	case 'w': // 2 strings to match.		case 'h': // 1 string to match.
	switch (NameR[15]) {		if (memcmp(NameR.data()+19, ".p", 2))
	default: break;		break;
	case 'd': // 1 string to match.		return Intrinsic::ppc_altivec_vcmpgtuh_p; // "pc.alti
	return Intrinsic::x86_xop_vpmacsswd; // "86.xop.vpmacssw		vec.vcmpgtuh.p"
	d"		case 'w': // 1 string to match.
	case 'w': // 1 string to match.		if (memcmp(NameR.data()+19, ".p", 2))
	return Intrinsic::x86_xop_vpmacssww; // "86.xop.vpmacssw		break;
	w"		return Intrinsic::ppc_altivec_vcmpgtuw_p; // "pc.alti
	}		vec.vcmpgtuw.p"
	break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'd': // 1 string to match.
	if (memcmp(NameR.data()+12, "cswd", 4))
	break;
	return Intrinsic::x86_xop_vpmadcswd; // "86.xop.vpmadcsw
	d"
	}		}
	break;		break;
	}		}
	break;		break;
			case 'm': // 1 string to match.
			if (memcmp(NameR.data()+13, "hraddshs", 8))
			break;
			return Intrinsic::ppc_altivec_vmhraddshs; // "pc.altivec.vmhr
			addshs"
	}		}
	break;		break;
	case 17: // 79 strings to match.		case 29: // 1 string to match.
	if (memcmp(NameR.data()+0, "86.", 3))		if (memcmp(NameR.data()+0, "pc.is.decremented.ctr.nonzero", 29))
	break;		break;
	switch (NameR[3]) {		return Intrinsic::ppc_is_decremented_ctr_nonzero; // "pc.is.d
			ecremented.ctr.nonzero"
			}
			break; // end of 'p' case.
			case 'r':
			if (NameR.startswith("ound.")) return Intrinsic::round;
			if (NameR.startswith("int.")) return Intrinsic::rint;
			switch (NameR.size()) {
			default: break;
			case 12: // 1 string to match.
			if (memcmp(NameR.data()+0, "eturnaddress", 12))
			break;
			return Intrinsic::returnaddress; // "eturnaddress"
			case 15: // 4 strings to match.
			switch (NameR[0]) {
	default: break;		default: break;
	case '3': // 4 strings to match.		case '6': // 3 strings to match.
	if (memcmp(NameR.data()+4, "dnow", 4))		if (memcmp(NameR.data()+1, "00.read.tgid.", 13))
	break;		break;
	switch (NameR[8]) {		switch (NameR[14]) {
	default: break;		default: break;
	case '.': // 3 strings to match.		case 'x': // 1 string to match.
	if (memcmp(NameR.data()+9, "pfr", 3))		return Intrinsic::r600_read_tgid_x; // "600.read.tgid.x"
			case 'y': // 1 string to match.
			return Intrinsic::r600_read_tgid_y; // "600.read.tgid.y"
			case 'z': // 1 string to match.
			return Intrinsic::r600_read_tgid_z; // "600.read.tgid.z"
			}
			break;
			case 'e': // 1 string to match.
			if (memcmp(NameR.data()+1, "adcyclecounter", 14))
			break;
			return Intrinsic::readcyclecounter; // "eadcyclecounter"
			}
			break;
			case 16: // 3 strings to match.
			if (memcmp(NameR.data()+0, "600.read.tidig.", 15))
			break;
			switch (NameR[15]) {
			default: break;
			case 'x': // 1 string to match.
			return Intrinsic::r600_read_tidig_x; // "600.read.tidig.x"
			case 'y': // 1 string to match.
			return Intrinsic::r600_read_tidig_y; // "600.read.tidig.y"
			case 'z': // 1 string to match.
			return Intrinsic::r600_read_tidig_z; // "600.read.tidig.z"
			}
			break;
			case 18: // 3 strings to match.
			if (memcmp(NameR.data()+0, "600.read.ngroups.", 17))
			break;
			switch (NameR[17]) {
			default: break;
			case 'x': // 1 string to match.
			return Intrinsic::r600_read_ngroups_x; // "600.read.ngroups.x"
			case 'y': // 1 string to match.
			return Intrinsic::r600_read_ngroups_y; // "600.read.ngroups.y"
			case 'z': // 1 string to match.
			return Intrinsic::r600_read_ngroups_z; // "600.read.ngroups.z"
			}
			break;
			case 21: // 3 strings to match.
			if (memcmp(NameR.data()+0, "600.read.local.size.", 20))
			break;
			switch (NameR[20]) {
			default: break;
			case 'x': // 1 string to match.
			return Intrinsic::r600_read_local_size_x; // "600.read.local.
			size.x"
			case 'y': // 1 string to match.
			return Intrinsic::r600_read_local_size_y; // "600.read.local.
			size.y"
			case 'z': // 1 string to match.
			return Intrinsic::r600_read_local_size_z; // "600.read.local.
			size.z"
			}
			break;
			case 22: // 3 strings to match.
			if (memcmp(NameR.data()+0, "600.read.global.size.", 21))
			break;
			switch (NameR[21]) {
			default: break;
			case 'x': // 1 string to match.
			return Intrinsic::r600_read_global_size_x; // "600.read.global
			.size.x"
			case 'y': // 1 string to match.
			return Intrinsic::r600_read_global_size_y; // "600.read.global
			.size.y"
			case 'z': // 1 string to match.
			return Intrinsic::r600_read_global_size_z; // "600.read.global
			.size.z"
			}
			break;
			}
			break; // end of 'r' case.
			case 's':
			if (NameR.startswith("sub.with.overflow.")) return Intrinsic::ssub_with
			_overflow;
			if (NameR.startswith("qrt.")) return Intrinsic::sqrt;
			if (NameR.startswith("mul.with.overflow.")) return Intrinsic::smul_with
			_overflow;
			if (NameR.startswith("in.")) return Intrinsic::sin;
			if (NameR.startswith("add.with.overflow.")) return Intrinsic::sadd_with
			_overflow;
			switch (NameR.size()) {
			default: break;
			case 5: // 1 string to match.
			if (memcmp(NameR.data()+0, "etjmp", 5))
			break;
			return Intrinsic::setjmp; // "etjmp"
			case 8: // 2 strings to match.
			switch (NameR[0]) {
			default: break;
			case 'i': // 1 string to match.
			if (memcmp(NameR.data()+1, "gsetjmp", 7))
			break;
			return Intrinsic::sigsetjmp; // "igsetjmp"
			case 't': // 1 string to match.
			if (memcmp(NameR.data()+1, "acksave", 7))
			break;
			return Intrinsic::stacksave; // "tacksave"
			}
			break;
			case 9: // 1 string to match.
			if (memcmp(NameR.data()+0, "iglongjmp", 9))
			break;
			return Intrinsic::siglongjmp; // "iglongjmp"
			case 11: // 1 string to match.
			if (memcmp(NameR.data()+0, "tackrestore", 11))
			break;
			return Intrinsic::stackrestore; // "tackrestore"
			case 13: // 1 string to match.
			if (memcmp(NameR.data()+0, "tackprotector", 13))
			break;
			return Intrinsic::stackprotector; // "tackprotector"
			case 18: // 1 string to match.
			if (memcmp(NameR.data()+0, "tackprotectorcheck", 18))
			break;
			return Intrinsic::stackprotectorcheck; // "tackprotectorcheck"
			}
			break; // end of 's' case.
			case 't':
			if (NameR.startswith("runc.")) return Intrinsic::trunc;
			switch (NameR.size()) {
			default: break;
			case 3: // 1 string to match.
			if (memcmp(NameR.data()+0, "rap", 3))
			break;
			return Intrinsic::trap; // "rap"
			}
			break; // end of 't' case.
			case 'u':
			if (NameR.startswith("sub.with.overflow.")) return Intrinsic::usub_with
			_overflow;
			if (NameR.startswith("mul.with.overflow.")) return Intrinsic::umul_with
			_overflow;
			if (NameR.startswith("add.with.overflow.")) return Intrinsic::uadd_with
			_overflow;
			break; // end of 'u' case.
			case 'v':
			switch (NameR.size()) {
			default: break;
			case 5: // 1 string to match.
			if (memcmp(NameR.data()+0, "a_end", 5))
			break;
			return Intrinsic::vaend; // "a_end"
			case 6: // 1 string to match.
			if (memcmp(NameR.data()+0, "a_copy", 6))
			break;
			return Intrinsic::vacopy; // "a_copy"
			case 7: // 1 string to match.
			if (memcmp(NameR.data()+0, "a_start", 7))
			break;
			return Intrinsic::vastart; // "a_start"
			case 13: // 1 string to match.
			if (memcmp(NameR.data()+0, "ar.annotation", 13))
			break;
			return Intrinsic::var_annotation; // "ar.annotation"
			}
			break; // end of 'v' case.
			case 'x':
			if (NameR.startswith("core.testwct.")) return Intrinsic::xcore_testwct;
			if (NameR.startswith("core.testct.")) return Intrinsic::xcore_testct;
			if (NameR.startswith("core.syncr.")) return Intrinsic::xcore_syncr;
			if (NameR.startswith("core.setv.")) return Intrinsic::xcore_setv;
			if (NameR.startswith("core.settw.")) return Intrinsic::xcore_settw;
			if (NameR.startswith("core.setrdy.")) return Intrinsic::xcore_setrdy;
			if (NameR.startswith("core.setpt.")) return Intrinsic::xcore_setpt;
			if (NameR.startswith("core.setpsc.")) return Intrinsic::xcore_setpsc;
			if (NameR.startswith("core.setev.")) return Intrinsic::xcore_setev;
			if (NameR.startswith("core.setd.")) return Intrinsic::xcore_setd;
			if (NameR.startswith("core.setclk.")) return Intrinsic::xcore_setclk;
			if (NameR.startswith("core.setc.")) return Intrinsic::xcore_setc;
			if (NameR.startswith("core.peek.")) return Intrinsic::xcore_peek;
			if (NameR.startswith("core.outt.")) return Intrinsic::xcore_outt;
			if (NameR.startswith("core.outshr.")) return Intrinsic::xcore_outshr;
			if (NameR.startswith("core.outct.")) return Intrinsic::xcore_outct;
			if (NameR.startswith("core.out.")) return Intrinsic::xcore_out;
			if (NameR.startswith("core.msync.")) return Intrinsic::xcore_msync;
			if (NameR.startswith("core.mjoin.")) return Intrinsic::xcore_mjoin;
			if (NameR.startswith("core.int.")) return Intrinsic::xcore_int;
			if (NameR.startswith("core.inshr.")) return Intrinsic::xcore_inshr;
			if (NameR.startswith("core.initsp.")) return Intrinsic::xcore_initsp;
			if (NameR.startswith("core.initpc.")) return Intrinsic::xcore_initpc;
			if (NameR.startswith("core.initlr.")) return Intrinsic::xcore_initlr;
			if (NameR.startswith("core.initdp.")) return Intrinsic::xcore_initdp;
			if (NameR.startswith("core.initcp.")) return Intrinsic::xcore_initcp;
			if (NameR.startswith("core.inct.")) return Intrinsic::xcore_inct;
			if (NameR.startswith("core.in.")) return Intrinsic::xcore_in;
			if (NameR.startswith("core.getts.")) return Intrinsic::xcore_getts;
			if (NameR.startswith("core.getst.")) return Intrinsic::xcore_getst;
			if (NameR.startswith("core.getr.")) return Intrinsic::xcore_getr;
			if (NameR.startswith("core.freer.")) return Intrinsic::xcore_freer;
			if (NameR.startswith("core.endin.")) return Intrinsic::xcore_endin;
			if (NameR.startswith("core.eeu.")) return Intrinsic::xcore_eeu;
			if (NameR.startswith("core.chkct.")) return Intrinsic::xcore_chkct;
			switch (NameR.size()) {
			default: break;
			case 6: // 1 string to match.
			if (memcmp(NameR.data()+0, "86.int", 6))
			break;
			return Intrinsic::x86_int; // "86.int"
			case 7: // 1 string to match.
			if (memcmp(NameR.data()+0, "86.xend", 7))
			break;
			return Intrinsic::x86_xend; // "86.xend"
			case 8: // 1 string to match.
			if (memcmp(NameR.data()+0, "86.xtest", 8))
			break;
			return Intrinsic::x86_xtest; // "86.xtest"
			case 9: // 6 strings to match.
			switch (NameR[0]) {
			default: break;
			case '8': // 2 strings to match.
			if (memcmp(NameR.data()+1, "6.x", 3))
			break;
			switch (NameR[4]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(NameR.data()+5, "bort", 4))
	break;		break;
	switch (NameR[12]) {		return Intrinsic::x86_xabort; // "86.xabort"
			case 'b': // 1 string to match.
			if (memcmp(NameR.data()+5, "egin", 4))
			break;
			return Intrinsic::x86_xbegin; // "86.xbegin"
			}
			break;
			case 'c': // 4 strings to match.
			if (memcmp(NameR.data()+1, "ore.", 4))
			break;
			switch (NameR[5]) {
			default: break;
			case 'c': // 2 strings to match.
			switch (NameR[6]) {
	default: break;		default: break;
	case 'c': // 2 strings to match.		case 'l': // 1 string to match.
	if (memcmp(NameR.data()+13, "pit", 3))		if (memcmp(NameR.data()+7, "re", 2))
	break;		break;
	switch (NameR[16]) {		return Intrinsic::xcore_clre; // "core.clre"
	default: break;		case 'r': // 1 string to match.
	case '1': // 1 string to match.		if (memcmp(NameR.data()+7, "c8", 2))
	return Intrinsic::x86_3dnow_pfrcpit1; // "86.3dnow.pfrcpi
	t1"
	case '2': // 1 string to match.
	return Intrinsic::x86_3dnow_pfrcpit2; // "86.3dnow.pfrcpi
	t2"
	}
	break;
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+13, "qit1", 4))
	break;		break;
	return Intrinsic::x86_3dnow_pfrsqit1; // "86.3dnow.pfrsqi t1"		return Intrinsic::xcore_crc8; // "core.crc8"
	}		}
	break;		break;
	case 'a': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(NameR.data()+9, ".pfpnacc", 8))		if (memcmp(NameR.data()+6, "ext", 3))
	break;		break;
	return Intrinsic::x86_3dnowa_pfpnacc; // "86.3dnowa.pfpna		return Intrinsic::xcore_sext; // "core.sext"
	cc"		case 'z': // 1 string to match.
			if (memcmp(NameR.data()+6, "ext", 3))
			break;
			return Intrinsic::xcore_zext; // "core.zext"
	}		}
	break;		break;
	case 'a': // 11 strings to match.		}
	if (memcmp(NameR.data()+4, "vx.", 3))		break;
			case 10: // 10 strings to match.
			switch (NameR[0]) {
			default: break;
			case '8': // 1 string to match.
			if (memcmp(NameR.data()+1, "6.mmx.por", 9))
	break;		break;
	switch (NameR[7]) {		return Intrinsic::x86_mmx_por; // "86.mmx.por"
			case 'c': // 9 strings to match.
			if (memcmp(NameR.data()+1, "ore.", 4))
			break;
			switch (NameR[5]) {
	default: break;		default: break;
	case 'c': // 2 strings to match.		case 'c': // 2 strings to match.
	if (memcmp(NameR.data()+8, "mp.p", 4))		switch (NameR[6]) {
	break;
	switch (NameR[12]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'l': // 1 string to match.
	if (memcmp(NameR.data()+13, ".256", 4))		if (memcmp(NameR.data()+7, "rsr", 3))
	break;		break;
	return Intrinsic::x86_avx_cmp_pd_256; // "86.avx.cmp.pd.2		return Intrinsic::xcore_clrsr; // "core.clrsr"
	56"		case 'r': // 1 string to match.
	case 's': // 1 string to match.		if (memcmp(NameR.data()+7, "c32", 3))
	if (memcmp(NameR.data()+13, ".256", 4))
	break;		break;
	return Intrinsic::x86_avx_cmp_ps_256; // "86.avx.cmp.ps.2 56"		return Intrinsic::xcore_crc32; // "core.crc32"
	}		}
	break;		break;
	case 'l': // 1 string to match.		case 'g': // 4 strings to match.
	if (memcmp(NameR.data()+8, "du.dq.256", 9))		if (memcmp(NameR.data()+6, "et", 2))
	break;		break;
	return Intrinsic::x86_avx_ldu_dq_256; // "86.avx.ldu.dq.2
	56"
	case 'm': // 4 strings to match.
	switch (NameR[8]) {		switch (NameR[8]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'e': // 2 strings to match.
	if (memcmp(NameR.data()+9, "x.p", 3))		switch (NameR[9]) {
	break;
	switch (NameR[12]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+13, ".256", 4))		return Intrinsic::xcore_geted; // "core.geted"
	break;		case 't': // 1 string to match.
	return Intrinsic::x86_avx_max_pd_256; // "86.avx.max.pd.2		return Intrinsic::xcore_getet; // "core.getet"
	56"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+13, ".256", 4))
	break;
	return Intrinsic::x86_avx_max_ps_256; // "86.avx.max.ps.2
	56"
	}		}
	break;		break;
	case 'i': // 2 strings to match.		case 'i': // 1 string to match.
	if (memcmp(NameR.data()+9, "n.p", 3))		if (NameR[9] != 'd')
	break;		break;
	switch (NameR[12]) {		return Intrinsic::xcore_getid; // "core.getid"
			case 'p': // 1 string to match.
			if (NameR[9] != 's')
			break;
			return Intrinsic::xcore_getps; // "core.getps"
			}
			break;
			case 's': // 3 strings to match.
			switch (NameR[6]) {
			default: break;
			case 'e': // 2 strings to match.
			if (NameR[7] != 't')
			break;
			switch (NameR[8]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(NameR.data()+13, ".256", 4))		if (NameR[9] != 's')
	break;		break;
	return Intrinsic::x86_avx_min_pd_256; // "86.avx.min.pd.2 56"		return Intrinsic::xcore_setps; // "core.setps"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(NameR.data()+13, ".256", 4))		if (NameR[9] != 'r')
	break;		break;
	return Intrinsic::x86_avx_min_ps_256; // "86.avx.min.ps.2 56"		return Intrinsic::xcore_setsr; // "core.setsr"
	}		}
	break;		break;
	}		case 's': // 1 string to match.
	break;		if (memcmp(NameR.data()+7, "ync", 3))
	case 'p': // 2 strings to match.
	if (memcmp(NameR.data()+8, "test", 4))
	break;
	switch (NameR[12]) {
	default: break;
	case 'c': // 1 string to match.
	if (memcmp(NameR.data()+13, ".256", 4))
	break;
	return Intrinsic::x86_avx_ptestc_256; // "86.avx.ptestc.2
	56"
	case 'z': // 1 string to match.
	if (memcmp(NameR.data()+13, ".256", 4))
	break;		break;
	return Intrinsic::x86_avx_ptestz_256; // "86.avx.ptestz.2 56"		return Intrinsic::xcore_ssync; // "core.ssync"
	}		}
	break;		break;
	case 'r': // 1 string to match.
	if (memcmp(NameR.data()+8, "cp.ps.256", 9))
	break;
	return Intrinsic::x86_avx_rcp_ps_256; // "86.avx.rcp.ps.2
	56"
	case 'v': // 1 string to match.
	if (memcmp(NameR.data()+8, "zeroupper", 9))
	break;
	return Intrinsic::x86_avx_vzeroupper; // "86.avx.vzeroupp
	er"
	}		}
	break;		break;
	case 'f': // 8 strings to match.		}
	if (memcmp(NameR.data()+4, "ma.vfnm", 7))		break;
			case 11: // 6 strings to match.
			switch (NameR[0]) {
			default: break;
			case '8': // 5 strings to match.
			if (memcmp(NameR.data()+1, "6.", 2))
	break;		break;
	switch (NameR[11]) {		switch (NameR[3]) {
	default: break;		default: break;
	case 'a': // 4 strings to match.		case 'm': // 3 strings to match.
	if (memcmp(NameR.data()+12, "dd.", 3))		if (memcmp(NameR.data()+4, "mx.", 3))
	break;		break;
	switch (NameR[15]) {		switch (NameR[7]) {
	default: break;		default: break;
			case 'e': // 1 string to match.
			if (memcmp(NameR.data()+8, "mms", 3))
			break;
			return Intrinsic::x86_mmx_emms; // "86.mmx.emms"
	case 'p': // 2 strings to match.		case 'p': // 2 strings to match.
	switch (NameR[16]) {		switch (NameR[8]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_fma_vfnmadd_pd; // "86.fma.vfnmadd.
	pd"
	case 's': // 1 string to match.
	return Intrinsic::x86_fma_vfnmadd_ps; // "86.fma.vfnmadd.
	ps"
	}
	break;
	case 's': // 2 strings to match.
	switch (NameR[16]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'a': // 1 string to match.
	return Intrinsic::x86_fma_vfnmadd_sd; // "86.fma.vfnmadd.		if (memcmp(NameR.data()+9, "nd", 2))
	sd"		break;
	case 's': // 1 string to match.		return Intrinsic::x86_mmx_pand; // "86.mmx.pand"
	return Intrinsic::x86_fma_vfnmadd_ss; // "86.fma.vfnmadd.		case 'x': // 1 string to match.
	ss"		if (memcmp(NameR.data()+9, "or", 2))
			break;
			return Intrinsic::x86_mmx_pxor; // "86.mmx.pxor"
	}		}
	break;		break;
	}		}
	break;		break;
	case 's': // 4 strings to match.		case 's': // 2 strings to match.
	if (memcmp(NameR.data()+12, "ub.", 3))		if (memcmp(NameR.data()+4, "ha1msg", 6))
	break;		break;
	switch (NameR[15]) {		switch (NameR[10]) {
	default: break;		default: break;
	case 'p': // 2 strings to match.		case '1': // 1 string to match.
	switch (NameR[16]) {		return Intrinsic::x86_sha1msg1; // "86.sha1msg1"
	default: break;		case '2': // 1 string to match.
	case 'd': // 1 string to match.		return Intrinsic::x86_sha1msg2; // "86.sha1msg2"
	return Intrinsic::x86_fma_vfnmsub_pd; // "86.fma.vfnmsub.
	pd"
	case 's': // 1 string to match.
	return Intrinsic::x86_fma_vfnmsub_ps; // "86.fma.vfnmsub.
	ps"
	}
	break;
	case 's': // 2 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_fma_vfnmsub_sd; // "86.fma.vfnmsub.
	sd"
	case 's': // 1 string to match.
	return Intrinsic::x86_fma_vfnmsub_ss; // "86.fma.vfnmsub.
	ss"
	}
	break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 's': // 50 strings to match.		case 'c': // 1 string to match.
	if (NameR[4] != 's')		if (memcmp(NameR.data()+1, "ore.bitrev", 10))
			break;
			return Intrinsic::xcore_bitrev; // "core.bitrev"
			}
			break;
			case 12: // 12 strings to match.
			if (memcmp(NameR.data()+0, "86.", 3))
			break;
			switch (NameR[3]) {
			default: break;
			case 'k': // 1 string to match.
			if (memcmp(NameR.data()+4, "or.v16i1", 8))
			break;
			return Intrinsic::x86_kor_v16i1; // "86.kor.v16i1"
			case 'm': // 2 strings to match.
			if (memcmp(NameR.data()+4, "mx.", 3))
			break;
			switch (NameR[7]) {
			default: break;
			case 'f': // 1 string to match.
			if (memcmp(NameR.data()+8, "emms", 4))
			break;
			return Intrinsic::x86_mmx_femms; // "86.mmx.femms"
			case 'p': // 1 string to match.
			if (memcmp(NameR.data()+8, "andn", 4))
			break;
			return Intrinsic::x86_mmx_pandn; // "86.mmx.pandn"
			}
			break;
			case 'p': // 1 string to match.
			if (memcmp(NameR.data()+4, "clmulqdq", 8))
			break;
			return Intrinsic::x86_pclmulqdq; // "86.pclmulqdq"
			case 'r': // 6 strings to match.
			if (NameR[4] != 'd')
	break;		break;
	switch (NameR[5]) {		switch (NameR[5]) {
	default: break;		default: break;
	case 'e': // 48 strings to match.		case 'r': // 3 strings to match.
	switch (NameR[6]) {		if (memcmp(NameR.data()+6, "and.", 4))
			break;
			switch (NameR[10]) {
	default: break;		default: break;
	case '.': // 8 strings to match.		case '1': // 1 string to match.
	switch (NameR[7]) {		if (NameR[11] != '6')
	default: break;
	case 'c': // 3 strings to match.
	switch (NameR[8]) {
	default: break;
	case 'o': // 1 string to match.
	if (memcmp(NameR.data()+9, "mineq.ss", 8))
	break;
	return Intrinsic::x86_sse_comineq_ss; // "86.sse.comineq.
	ss"
	case 'v': // 2 strings to match.
	if (memcmp(NameR.data()+9, "ts", 2))
	break;
	switch (NameR[11]) {
	default: break;
	case 'i': // 1 string to match.
	if (memcmp(NameR.data()+12, "642ss", 5))
	break;
	return Intrinsic::x86_sse_cvtsi642ss; // "86.sse.
	cvtsi642ss"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+12, "2si64", 5))
	break;
	return Intrinsic::x86_sse_cvtss2si64; // "86.sse.
	cvtss2si64"
	}
	break;
	}
	break;		break;
	case 'u': // 5 strings to match.		return Intrinsic::x86_rdrand_16; // "86.rdrand.16"
	if (memcmp(NameR.data()+8, "comi", 4))		case '3': // 1 string to match.
	break;		if (NameR[11] != '2')
	switch (NameR[12]) {		break;
	default: break;		return Intrinsic::x86_rdrand_32; // "86.rdrand.32"
	case 'e': // 1 string to match.		case '6': // 1 string to match.
	if (memcmp(NameR.data()+13, "q.ss", 4))		if (NameR[11] != '4')
	break;		break;
	return Intrinsic::x86_sse_ucomieq_ss; // "86.sse.ucomieq.		return Intrinsic::x86_rdrand_64; // "86.rdrand.64"
	ss"		}
	case 'g': // 2 strings to match.		break;
	switch (NameR[13]) {		case 's': // 3 strings to match.
	default: break;		if (memcmp(NameR.data()+6, "eed.", 4))
	case 'e': // 1 string to match.		break;
	if (memcmp(NameR.data()+14, ".ss", 3))		switch (NameR[10]) {
	break;		default: break;
	return Intrinsic::x86_sse_ucomige_ss; // "86.sse.		case '1': // 1 string to match.
	ucomige.ss"		if (NameR[11] != '6')
	case 't': // 1 string to match.		break;
	if (memcmp(NameR.data()+14, ".ss", 3))		return Intrinsic::x86_rdseed_16; // "86.rdseed.16"
	break;		case '3': // 1 string to match.
	return Intrinsic::x86_sse_ucomigt_ss; // "86.sse.		if (NameR[11] != '2')
	ucomigt.ss"		break;
	}		return Intrinsic::x86_rdseed_32; // "86.rdseed.32"
	break;		case '6': // 1 string to match.
	case 'l': // 2 strings to match.		if (NameR[11] != '4')
	switch (NameR[13]) {		break;
	default: break;		return Intrinsic::x86_rdseed_64; // "86.rdseed.64"
	case 'e': // 1 string to match.		}
	if (memcmp(NameR.data()+14, ".ss", 3))		break;
	break;		}
	return Intrinsic::x86_sse_ucomile_ss; // "86.sse.		break;
	ucomile.ss"		case 's': // 2 strings to match.
	case 't': // 1 string to match.		if (memcmp(NameR.data()+4, "ha1", 3))
	if (memcmp(NameR.data()+14, ".ss", 3))		break;
	break;		switch (NameR[7]) {
	return Intrinsic::x86_sse_ucomilt_ss; // "86.sse.		default: break;
	ucomilt.ss"		case 'n': // 1 string to match.
	}		if (memcmp(NameR.data()+8, "exte", 4))
	break;		break;
	}		return Intrinsic::x86_sha1nexte; // "86.sha1nexte"
			case 'r': // 1 string to match.
			if (memcmp(NameR.data()+8, "nds4", 4))
			break;
			return Intrinsic::x86_sha1rnds4; // "86.sha1rnds4"
			}
			break;
			}
			break;
			case 13: // 59 strings to match.
			if (memcmp(NameR.data()+0, "86.", 3))
			break;
			switch (NameR[3]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(NameR.data()+4, "vx2.permd", 9))
			break;
			return Intrinsic::x86_avx2_permd; // "86.avx2.permd"
			case 'k': // 4 strings to match.
			switch (NameR[4]) {
			default: break;
			case 'a': // 2 strings to match.
			switch (NameR[5]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+6, "d.v16i1", 7))
			break;
			return Intrinsic::x86_kadd_v16i1; // "86.kadd.v16i1"
			case 'n': // 1 string to match.
			if (memcmp(NameR.data()+6, "d.v16i1", 7))
			break;
			return Intrinsic::x86_kand_v16i1; // "86.kand.v16i1"
			}
			break;
			case 'n': // 1 string to match.
			if (memcmp(NameR.data()+5, "ot.v16i1", 8))
			break;
			return Intrinsic::x86_knot_v16i1; // "86.knot.v16i1"
			case 'x': // 1 string to match.
			if (memcmp(NameR.data()+5, "or.v16i1", 8))
			break;
			return Intrinsic::x86_kxor_v16i1; // "86.kxor.v16i1"
			}
			break;
			case 'm': // 18 strings to match.
			if (memcmp(NameR.data()+4, "mx.p", 4))
			break;
			switch (NameR[8]) {
			default: break;
			case 'a': // 6 strings to match.
			switch (NameR[9]) {
			default: break;
			case 'd': // 4 strings to match.
			if (memcmp(NameR.data()+10, "d.", 2))
	break;		break;
			switch (NameR[12]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_mmx_padd_b; // "86.mmx.padd.b"
			case 'd': // 1 string to match.
			return Intrinsic::x86_mmx_padd_d; // "86.mmx.padd.d"
			case 'q': // 1 string to match.
			return Intrinsic::x86_mmx_padd_q; // "86.mmx.padd.q"
			case 'w': // 1 string to match.
			return Intrinsic::x86_mmx_padd_w; // "86.mmx.padd.w"
	}		}
	break;		break;
	case '2': // 12 strings to match.		case 'v': // 2 strings to match.
	if (NameR[7] != '.')		if (memcmp(NameR.data()+10, "g.", 2))
	break;		break;
	switch (NameR[8]) {		switch (NameR[12]) {
	default: break;		default: break;
	case 'c': // 8 strings to match.		case 'b': // 1 string to match.
	switch (NameR[9]) {		return Intrinsic::x86_mmx_pavg_b; // "86.mmx.pavg.b"
	default: break;		case 'w': // 1 string to match.
	case 'o': // 5 strings to match.		return Intrinsic::x86_mmx_pavg_w; // "86.mmx.pavg.w"
	if (memcmp(NameR.data()+10, "mi", 2))		}
	break;		break;
	switch (NameR[12]) {		}
	default: break;		break;
	case 'e': // 1 string to match.		case 's': // 12 strings to match.
	if (memcmp(NameR.data()+13, "q.sd", 4))		switch (NameR[9]) {
	break;		default: break;
	return Intrinsic::x86_sse2_comieq_sd; // "86.sse2		case 'l': // 3 strings to match.
	.comieq.sd"		if (memcmp(NameR.data()+10, "l.", 2))
	case 'g': // 2 strings to match.		break;
	switch (NameR[13]) {		switch (NameR[12]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+14, ".sd", 3))		return Intrinsic::x86_mmx_psll_d; // "86.mmx.psll.d"
	break;		case 'q': // 1 string to match.
	return Intrinsic::x86_sse2_comige_sd; // "86.sse2		return Intrinsic::x86_mmx_psll_q; // "86.mmx.psll.q"
	.comige.sd"		case 'w': // 1 string to match.
	case 't': // 1 string to match.		return Intrinsic::x86_mmx_psll_w; // "86.mmx.psll.w"
	if (memcmp(NameR.data()+14, ".sd", 3))		}
	break;		break;
	return Intrinsic::x86_sse2_comigt_sd; // "86.sse2		case 'r': // 5 strings to match.
	.comigt.sd"		switch (NameR[10]) {
	}		default: break;
	break;		case 'a': // 2 strings to match.
	case 'l': // 2 strings to match.		if (NameR[11] != '.')
	switch (NameR[13]) {
	default: break;
	case 'e': // 1 string to match.
	if (memcmp(NameR.data()+14, ".sd", 3))
	break;
	return Intrinsic::x86_sse2_comile_sd; // "86.sse2
	.comile.sd"
	case 't': // 1 string to match.
	if (memcmp(NameR.data()+14, ".sd", 3))
	break;
	return Intrinsic::x86_sse2_comilt_sd; // "86.sse2
	.comilt.sd"
	}
	break;
	}
	break;
	case 'v': // 3 strings to match.
	if (memcmp(NameR.data()+10, "tt", 2))
	break;
	switch (NameR[12]) {
	default: break;
	case 'p': // 2 strings to match.
	switch (NameR[13]) {
	default: break;
	case 'd': // 1 string to match.
	if (memcmp(NameR.data()+14, "2dq", 3))
	break;
	return Intrinsic::x86_sse2_cvttpd2dq; // "86.sse2
	.cvttpd2dq"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+14, "2dq", 3))
	break;
	return Intrinsic::x86_sse2_cvttps2dq; // "86.sse2
	.cvttps2dq"
	}
	break;
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+13, "d2si", 4))
	break;
	return Intrinsic::x86_sse2_cvttsd2si; // "86.sse2
	.cvttsd2si"
	}
	break;		break;
			switch (NameR[12]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_mmx_psra_d; // "86.mmx.psra.d"
			case 'w': // 1 string to match.
			return Intrinsic::x86_mmx_psra_w; // "86.mmx.psra.w"
	}		}
	break;		break;
	case 'm': // 1 string to match.		case 'l': // 3 strings to match.
	if (memcmp(NameR.data()+9, "ovmsk.pd", 8))		if (NameR[11] != '.')
	break;
	return Intrinsic::x86_sse2_movmsk_pd; // "86.sse2.movmsk.
	pd"
	case 's': // 3 strings to match.
	if (memcmp(NameR.data()+9, "tore", 4))
	break;		break;
	switch (NameR[13]) {		switch (NameR[12]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+14, ".dq", 3))		return Intrinsic::x86_mmx_psrl_d; // "86.mmx.psrl.d"
	break;		case 'q': // 1 string to match.
	return Intrinsic::x86_sse2_storel_dq; // "86.sse2.storel.		return Intrinsic::x86_mmx_psrl_q; // "86.mmx.psrl.q"
	dq"		case 'w': // 1 string to match.
	case 'u': // 2 strings to match.		return Intrinsic::x86_mmx_psrl_w; // "86.mmx.psrl.w"
	if (NameR[14] != '.')
	break;
	switch (NameR[15]) {
	default: break;
	case 'd': // 1 string to match.
	if (NameR[16] != 'q')
	break;
	return Intrinsic::x86_sse2_storeu_dq; // "86.sse2
	.storeu.dq"
	case 'p': // 1 string to match.
	if (NameR[16] != 'd')
	break;
	return Intrinsic::x86_sse2_storeu_pd; // "86.sse2
	.storeu.pd"
	}
	break;
	}		}
	break;		break;
	}		}
	break;		break;
	case '3': // 2 strings to match.		case 'u': // 4 strings to match.
	if (memcmp(NameR.data()+7, ".addsub.p", 9))		if (memcmp(NameR.data()+10, "b.", 2))
	break;		break;
	switch (NameR[16]) {		switch (NameR[12]) {
	default: break;		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_mmx_psub_b; // "86.mmx.psub.b"
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::x86_sse3_addsub_pd; // "86.sse3.addsub.		return Intrinsic::x86_mmx_psub_d; // "86.mmx.psub.d"
	pd"		case 'q': // 1 string to match.
	case 's': // 1 string to match.		return Intrinsic::x86_mmx_psub_q; // "86.mmx.psub.q"
	return Intrinsic::x86_sse3_addsub_ps; // "86.sse3.addsub.		case 'w': // 1 string to match.
	ps"		return Intrinsic::x86_mmx_psub_w; // "86.mmx.psub.w"
	}		}
	break;		break;
	case '4': // 26 strings to match.		}
			break;
			}
			break;
			case 's': // 18 strings to match.
			switch (NameR[4]) {
			default: break;
			case 'h': // 2 strings to match.
			if (memcmp(NameR.data()+5, "a256msg", 7))
			break;
			switch (NameR[12]) {
			default: break;
			case '1': // 1 string to match.
			return Intrinsic::x86_sha256msg1; // "86.sha256msg1"
			case '2': // 1 string to match.
			return Intrinsic::x86_sha256msg2; // "86.sha256msg2"
			}
			break;
			case 's': // 16 strings to match.
			if (NameR[5] != 'e')
			break;
			switch (NameR[6]) {
			default: break;
			case '.': // 13 strings to match.
	switch (NameR[7]) {		switch (NameR[7]) {
	default: break;		default: break;
	case '1': // 23 strings to match.		case 'a': // 1 string to match.
	if (NameR[8] != '.')		if (memcmp(NameR.data()+8, "dd.ss", 5))
	break;		break;
	switch (NameR[9]) {		return Intrinsic::x86_sse_add_ss; // "86.sse.add.ss"
			case 'c': // 2 strings to match.
			if (memcmp(NameR.data()+8, "mp.", 3))
			break;
			switch (NameR[11]) {
	default: break;		default: break;
	case 'b': // 2 strings to match.		case 'p': // 1 string to match.
	if (memcmp(NameR.data()+10, "lendvp", 6))		if (NameR[12] != 's')
	break;		break;
	switch (NameR[16]) {		return Intrinsic::x86_sse_cmp_ps; // "86.sse.cmp.ps"
			case 's': // 1 string to match.
			if (NameR[12] != 's')
			break;
			return Intrinsic::x86_sse_cmp_ss; // "86.sse.cmp.ss"
			}
			break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+8, "iv.ss", 5))
			break;
			return Intrinsic::x86_sse_div_ss; // "86.sse.div.ss"
			case 'm': // 5 strings to match.
			switch (NameR[8]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(NameR.data()+9, "x.", 2))
			break;
			switch (NameR[11]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'p': // 1 string to match.
	return Intrinsic::x86_sse41_blendvpd; // "86.sse4		if (NameR[12] != 's')
	1.blendvpd"		break;
			return Intrinsic::x86_sse_max_ps; // "86.sse.max.ps"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	return Intrinsic::x86_sse41_blendvps; // "86.sse4		if (NameR[12] != 's')
	1.blendvps"		break;
			return Intrinsic::x86_sse_max_ss; // "86.sse.max.ss"
	}		}
	break;		break;
	case 'i': // 1 string to match.		case 'i': // 2 strings to match.
	if (memcmp(NameR.data()+10, "nsertps", 7))		if (memcmp(NameR.data()+9, "n.", 2))
	break;
	return Intrinsic::x86_sse41_insertps; // "86.sse41.insert
	ps"
	case 'm': // 1 string to match.
	if (memcmp(NameR.data()+10, "ovntdqa", 7))
	break;		break;
	return Intrinsic::x86_sse41_movntdqa; // "86.sse41.movntd		switch (NameR[11]) {
	qa"
	case 'p': // 15 strings to match.
	switch (NameR[10]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(NameR.data()+11, "ckusdw", 6))		if (NameR[12] != 's')
	break;
	return Intrinsic::x86_sse41_packusdw; // "86.sse4
	1.packusdw"
	case 'b': // 1 string to match.
	if (memcmp(NameR.data()+11, "lendvb", 6))
	break;
	return Intrinsic::x86_sse41_pblendvb; // "86.sse4
	1.pblendvb"
	case 'm': // 12 strings to match.
	if (memcmp(NameR.data()+11, "ov", 2))
	break;
	switch (NameR[13]) {
	default: break;
	case 's': // 6 strings to match.
	if (NameR[14] != 'x')
	break;
	switch (NameR[15]) {
	default: break;
	case 'b': // 3 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_pmovsxbd; // "86.sse4
	1.pmovsxbd"
	case 'q': // 1 string to match.
	return Intrinsic::x86_sse41_pmovsxbq; // "86.sse4
	1.pmovsxbq"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse41_pmovsxbw; // "86.sse4
	1.pmovsxbw"
	}
	break;
	case 'd': // 1 string to match.
	if (NameR[16] != 'q')
	break;
	return Intrinsic::x86_sse41_pmovsxdq; // "86.sse4
	1.pmovsxdq"
	case 'w': // 2 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_pmovsxwd; // "86.sse4
	1.pmovsxwd"
	case 'q': // 1 string to match.
	return Intrinsic::x86_sse41_pmovsxwq; // "86.sse4
	1.pmovsxwq"
	}
	break;
	}
	break;
	case 'z': // 6 strings to match.
	if (NameR[14] != 'x')
	break;
	switch (NameR[15]) {
	default: break;
	case 'b': // 3 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_pmovzxbd; // "86.sse4
	1.pmovzxbd"
	case 'q': // 1 string to match.
	return Intrinsic::x86_sse41_pmovzxbq; // "86.sse4
	1.pmovzxbq"
	case 'w': // 1 string to match.
	return Intrinsic::x86_sse41_pmovzxbw; // "86.sse4
	1.pmovzxbw"
	}
	break;
	case 'd': // 1 string to match.
	if (NameR[16] != 'q')
	break;
	return Intrinsic::x86_sse41_pmovzxdq; // "86.sse4
	1.pmovzxdq"
	case 'w': // 2 strings to match.
	switch (NameR[16]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_pmovzxwd; // "86.sse4
	1.pmovzxwd"
	case 'q': // 1 string to match.
	return Intrinsic::x86_sse41_pmovzxwq; // "86.sse4
	1.pmovzxwq"
	}
	break;
	}
	break;		break;
	}		return Intrinsic::x86_sse_min_ps; // "86.sse.min.ps"
	break;		case 's': // 1 string to match.
	case 't': // 1 string to match.		if (NameR[12] != 's')
	if (memcmp(NameR.data()+11, "estnzc", 6))
	break;		break;
	return Intrinsic::x86_sse41_ptestnzc; // "86.sse4 1.ptestnzc"		return Intrinsic::x86_sse_min_ss; // "86.sse.min.ss"
	}		}
	break;		break;
	case 'r': // 4 strings to match.		case 'u': // 1 string to match.
	if (memcmp(NameR.data()+10, "ound.", 5))		if (memcmp(NameR.data()+9, "l.ss", 4))
	break;		break;
	switch (NameR[15]) {		return Intrinsic::x86_sse_mul_ss; // "86.sse.mul.ss"
	default: break;		}
	case 'p': // 2 strings to match.		break;
	switch (NameR[16]) {		case 'r': // 2 strings to match.
	default: break;		if (memcmp(NameR.data()+8, "cp.", 3))
	case 'd': // 1 string to match.		break;
	return Intrinsic::x86_sse41_round_pd; // "86.sse4		switch (NameR[11]) {
	1.round.pd"		default: break;
	case 's': // 1 string to match.		case 'p': // 1 string to match.
	return Intrinsic::x86_sse41_round_ps; // "86.sse4		if (NameR[12] != 's')
	1.round.ps"
	}
	break;		break;
	case 's': // 2 strings to match.		return Intrinsic::x86_sse_rcp_ps; // "86.sse.rcp.ps"
	switch (NameR[16]) {		case 's': // 1 string to match.
	default: break;		if (NameR[12] != 's')
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_round_sd; // "86.sse4
	1.round.sd"
	case 's': // 1 string to match.
	return Intrinsic::x86_sse41_round_ss; // "86.sse4
	1.round.ss"
	}
	break;		break;
	}		return Intrinsic::x86_sse_rcp_ss; // "86.sse.rcp.ss"
	break;
	}		}
	break;		break;
	case 'a': // 3 strings to match.		case 's': // 2 strings to match.
	if (NameR[8] != '.')		switch (NameR[8]) {
	break;
	switch (NameR[9]) {
	default: break;		default: break;
	case 'i': // 1 string to match.		case 'f': // 1 string to match.
	if (memcmp(NameR.data()+10, "nsertqi", 7))		if (memcmp(NameR.data()+9, "ence", 4))
	break;		break;
	return Intrinsic::x86_sse4a_insertqi; // "86.sse4a.insert		return Intrinsic::x86_sse_sfence; // "86.sse.sfence"
	qi"		case 'u': // 1 string to match.
	case 'm': // 2 strings to match.		if (memcmp(NameR.data()+9, "b.ss", 4))
	if (memcmp(NameR.data()+10, "ovnt.s", 6))
	break;		break;
	switch (NameR[16]) {		return Intrinsic::x86_sse_sub_ss; // "86.sse.sub.ss"
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_sse4a_movnt_sd; // "86.sse4
	a.movnt.sd"
	case 's': // 1 string to match.
	return Intrinsic::x86_sse4a_movnt_ss; // "86.sse4
	a.movnt.ss"
	}
	break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		case '3': // 1 string to match.
	break;		if (memcmp(NameR.data()+7, ".mwait", 6))
	case 's': // 2 strings to match.
	if (memcmp(NameR.data()+6, "e3.ph", 5))
	break;
	switch (NameR[11]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(NameR.data()+12, "dd.sw", 5))
	break;		break;
	return Intrinsic::x86_ssse3_phadd_sw; // "86.ssse3.phadd.		return Intrinsic::x86_sse3_mwait; // "86.sse3.mwait"
	sw"		case '4': // 2 strings to match.
	case 's': // 1 string to match.		if (memcmp(NameR.data()+7, "1.dpp", 5))
	if (memcmp(NameR.data()+12, "ub.sw", 5))
	break;		break;
	return Intrinsic::x86_ssse3_phsub_sw; // "86.ssse3.phsub.		switch (NameR[12]) {
	sw"		default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_sse41_dppd; // "86.sse41.dppd"
			case 's': // 1 string to match.
			return Intrinsic::x86_sse41_dpps; // "86.sse41.dpps"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'x': // 6 strings to match.		case 'x': // 18 strings to match.
	if (memcmp(NameR.data()+4, "op.vp", 5))		if (memcmp(NameR.data()+4, "op.vp", 5))
	break;		break;
	switch (NameR[9]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'c': // 1 string to match.		case 'c': // 5 strings to match.
	if (memcmp(NameR.data()+10, "mov.256", 7))		switch (NameR[10]) {
	break;
	return Intrinsic::x86_xop_vpcmov_256; // "86.xop.vpcmov.2
	56"
	case 'e': // 2 strings to match.
	if (memcmp(NameR.data()+10, "rmil2p", 6))
	break;
	switch (NameR[16]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'm': // 1 string to match.
	return Intrinsic::x86_xop_vpermil2pd; // "86.xop.vpermil2		if (memcmp(NameR.data()+11, "ov", 2))
	pd"		break;
	case 's': // 1 string to match.		return Intrinsic::x86_xop_vpcmov; // "86.xop.vpcmov"
	return Intrinsic::x86_xop_vpermil2ps; // "86.xop.vpermil2		case 'o': // 4 strings to match.
	ps"		if (NameR[11] != 'm')
			break;
			switch (NameR[12]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_xop_vpcomb; // "86.xop.vpcomb"
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vpcomd; // "86.xop.vpcomd"
			case 'q': // 1 string to match.
			return Intrinsic::x86_xop_vpcomq; // "86.xop.vpcomq"
			case 'w': // 1 string to match.
			return Intrinsic::x86_xop_vpcomw; // "86.xop.vpcomw"
			}
			break;
	}		}
	break;		break;
	case 'm': // 3 strings to match.		case 'p': // 1 string to match.
	if (NameR[10] != 'a')		if (memcmp(NameR.data()+10, "erm", 3))
			break;
			return Intrinsic::x86_xop_vpperm; // "86.xop.vpperm"
			case 'r': // 4 strings to match.
			if (memcmp(NameR.data()+10, "ot", 2))
			break;
			switch (NameR[12]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_xop_vprotb; // "86.xop.vprotb"
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vprotd; // "86.xop.vprotd"
			case 'q': // 1 string to match.
			return Intrinsic::x86_xop_vprotq; // "86.xop.vprotq"
			case 'w': // 1 string to match.
			return Intrinsic::x86_xop_vprotw; // "86.xop.vprotw"
			}
			break;
			case 's': // 8 strings to match.
			if (NameR[10] != 'h')
	break;		break;
	switch (NameR[11]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'c': // 2 strings to match.		case 'a': // 4 strings to match.
	if (memcmp(NameR.data()+12, "ssdq", 4))		switch (NameR[12]) {
	break;
	switch (NameR[16]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::x86_xop_vpmacssdqh; // "86.xop.vpmacssd		return Intrinsic::x86_xop_vpshab; // "86.xop.vpshab"
	qh"		case 'd': // 1 string to match.
	case 'l': // 1 string to match.		return Intrinsic::x86_xop_vpshad; // "86.xop.vpshad"
	return Intrinsic::x86_xop_vpmacssdql; // "86.xop.vpmacssd		case 'q': // 1 string to match.
	ql"		return Intrinsic::x86_xop_vpshaq; // "86.xop.vpshaq"
			case 'w': // 1 string to match.
			return Intrinsic::x86_xop_vpshaw; // "86.xop.vpshaw"
			}
			break;
			case 'l': // 4 strings to match.
			switch (NameR[12]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_xop_vpshlb; // "86.xop.vpshlb"
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vpshld; // "86.xop.vpshld"
			case 'q': // 1 string to match.
			return Intrinsic::x86_xop_vpshlq; // "86.xop.vpshlq"
			case 'w': // 1 string to match.
			return Intrinsic::x86_xop_vpshlw; // "86.xop.vpshlw"
	}		}
	break;		break;
	case 'd': // 1 string to match.
	if (memcmp(NameR.data()+12, "csswd", 5))
	break;
	return Intrinsic::x86_xop_vpmadcsswd; // "86.xop.vpmadcss
	wd"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 18: // 33 strings to match.		case 14: // 99 strings to match.
	if (memcmp(NameR.data()+0, "86.", 3))		switch (NameR[0]) {
	break;
	switch (NameR[3]) {
	default: break;		default: break;
	case 'a': // 20 strings to match.		case '8': // 98 strings to match.
	if (memcmp(NameR.data()+4, "vx", 2))		if (memcmp(NameR.data()+1, "6.", 2))
	break;		break;
	switch (NameR[6]) {		switch (NameR[3]) {
	default: break;		default: break;
	case '.': // 10 strings to match.		case '3': // 9 strings to match.
	switch (NameR[7]) {		if (memcmp(NameR.data()+4, "dnow.p", 6))
			break;
			switch (NameR[10]) {
	default: break;		default: break;
	case 'h': // 4 strings to match.		case 'f': // 8 strings to match.
	switch (NameR[8]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case '2': // 1 string to match.
	if (memcmp(NameR.data()+9, "dd.p", 4))		if (memcmp(NameR.data()+12, "id", 2))
	break;		break;
	switch (NameR[13]) {		return Intrinsic::x86_3dnow_pf2id; // "86.3dnow.pf2id"
			case 'a': // 2 strings to match.
			switch (NameR[12]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'c': // 1 string to match.
	if (memcmp(NameR.data()+14, ".256", 4))		if (NameR[13] != 'c')
	break;		break;
	return Intrinsic::x86_avx_hadd_pd_256; // "86.avx.hadd.pd.		return Intrinsic::x86_3dnow_pfacc; // "86.3dnow.pfacc"
	256"		case 'd': // 1 string to match.
	case 's': // 1 string to match.		if (NameR[13] != 'd')
	if (memcmp(NameR.data()+14, ".256", 4))
	break;		break;
	return Intrinsic::x86_avx_hadd_ps_256; // "86.avx.hadd.ps. 256"		return Intrinsic::x86_3dnow_pfadd; // "86.3dnow.pfadd"
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 'm': // 3 strings to match.
	if (memcmp(NameR.data()+9, "ub.p", 4))		switch (NameR[12]) {
	break;
	switch (NameR[13]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(NameR.data()+14, ".256", 4))		if (NameR[13] != 'x')
	break;		break;
	return Intrinsic::x86_avx_hsub_pd_256; // "86.avx.hsub.pd.		return Intrinsic::x86_3dnow_pfmax; // "86.3dnow.pfmax"
	256"		case 'i': // 1 string to match.
	case 's': // 1 string to match.		if (NameR[13] != 'n')
	if (memcmp(NameR.data()+14, ".256", 4))
	break;		break;
	return Intrinsic::x86_avx_hsub_ps_256; // "86.avx.hsub.ps.		return Intrinsic::x86_3dnow_pfmin; // "86.3dnow.pfmin"
	256"		case 'u': // 1 string to match.
			if (NameR[13] != 'l')
			break;
			return Intrinsic::x86_3dnow_pfmul; // "86.3dnow.pfmul"
	}		}
	break;		break;
	}		case 'r': // 1 string to match.
	break;		if (memcmp(NameR.data()+12, "cp", 2))
	case 'm': // 2 strings to match.
	if (memcmp(NameR.data()+8, "askload.p", 9))
	break;
	switch (NameR[17]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_avx_maskload_pd; // "86.avx.maskload
	.pd"
	case 's': // 1 string to match.
	return Intrinsic::x86_avx_maskload_ps; // "86.avx.maskload
	.ps"
	}
	break;
	case 's': // 2 strings to match.
	if (memcmp(NameR.data()+8, "qrt.p", 5))
	break;
	switch (NameR[13]) {
	default: break;
	case 'd': // 1 string to match.
	if (memcmp(NameR.data()+14, ".256", 4))
	break;		break;
	return Intrinsic::x86_avx_sqrt_pd_256; // "86.avx.sqrt.pd. 256"		return Intrinsic::x86_3dnow_pfrcp; // "86.3dnow.pfrcp"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(NameR.data()+14, ".256", 4))		if (memcmp(NameR.data()+12, "ub", 2))
	break;		break;
	return Intrinsic::x86_avx_sqrt_ps_256; // "86.avx.sqrt.ps. 256"		return Intrinsic::x86_3dnow_pfsub; // "86.3dnow.pfsub"
	}		}
	break;		break;
	case 'v': // 2 strings to match.		case 'i': // 1 string to match.
	if (memcmp(NameR.data()+8, "testnzc.p", 9))		if (memcmp(NameR.data()+11, "2fd", 3))
	break;		break;
	switch (NameR[17]) {		return Intrinsic::x86_3dnow_pi2fd; // "86.3dnow.pi2fd"
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_avx_vtestnzc_pd; // "86.avx.vtestnzc
	.pd"
	case 's': // 1 string to match.
	return Intrinsic::x86_avx_vtestnzc_ps; // "86.avx.vtestnzc
	.ps"
	}
	break;
	}		}
	break;		break;
	case '2': // 10 strings to match.		case 'a': // 14 strings to match.
	if (NameR[7] != '.')		if (memcmp(NameR.data()+4, "vx2.p", 5))
	break;		break;
	switch (NameR[8]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'g': // 4 strings to match.		case 'a': // 5 strings to match.
	if (memcmp(NameR.data()+9, "ather.", 6))		switch (NameR[10]) {
	break;
	switch (NameR[15]) {
	default: break;		default: break;
	case 'd': // 2 strings to match.		case 'b': // 3 strings to match.
	if (NameR[16] != '.')		if (memcmp(NameR.data()+11, "s.", 2))
	break;		break;
	switch (NameR[17]) {		switch (NameR[13]) {
	default: break;		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_avx2_pabs_b; // "86.avx2.pabs.b"
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::x86_avx2_gather_d_d; // "86.avx2.gather.		return Intrinsic::x86_avx2_pabs_d; // "86.avx2.pabs.d"
	d.d"		case 'w': // 1 string to match.
	case 'q': // 1 string to match.		return Intrinsic::x86_avx2_pabs_w; // "86.avx2.pabs.w"
	return Intrinsic::x86_avx2_gather_d_q; // "86.avx2.gather.
	d.q"
	}		}
	break;		break;
	case 'q': // 2 strings to match.		case 'v': // 2 strings to match.
	if (NameR[16] != '.')		if (memcmp(NameR.data()+11, "g.", 2))
	break;		break;
	switch (NameR[17]) {		switch (NameR[13]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::x86_avx2_gather_q_d; // "86.avx2.gather.		return Intrinsic::x86_avx2_pavg_b; // "86.avx2.pavg.b"
	q.d"		case 'w': // 1 string to match.
	case 'q': // 1 string to match.		return Intrinsic::x86_avx2_pavg_w; // "86.avx2.pavg.w"
	return Intrinsic::x86_avx2_gather_q_q; // "86.avx2.gather.
	q.q"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'm': // 2 strings to match.		case 'e': // 1 string to match.
	if (memcmp(NameR.data()+9, "askload.", 8))		if (memcmp(NameR.data()+10, "rmps", 4))
	break;		break;
	switch (NameR[17]) {		return Intrinsic::x86_avx2_permps; // "86.avx2.permps"
	default: break;		case 's': // 8 strings to match.
	case 'd': // 1 string to match.		switch (NameR[10]) {
	return Intrinsic::x86_avx2_maskload_d; // "86.avx2.maskloa
	d.d"
	case 'q': // 1 string to match.
	return Intrinsic::x86_avx2_maskload_q; // "86.avx2.maskloa
	d.q"
	}
	break;
	case 'p': // 3 strings to match.
	switch (NameR[9]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'l': // 3 strings to match.
	if (memcmp(NameR.data()+10, "ul.hr.sw", 8))		if (memcmp(NameR.data()+11, "l.", 2))
	break;		break;
	return Intrinsic::x86_avx2_pmul_hr_sw; // "86.avx2.pmul.hr		switch (NameR[13]) {
	.sw"
	case 's': // 2 strings to match.
	switch (NameR[10]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+11, "l.dq.bs", 7))		return Intrinsic::x86_avx2_psll_d; // "86.avx2.psll.d"
			case 'q': // 1 string to match.
			return Intrinsic::x86_avx2_psll_q; // "86.avx2.psll.q"
			case 'w': // 1 string to match.
			return Intrinsic::x86_avx2_psll_w; // "86.avx2.psll.w"
			}
			break;
			case 'r': // 5 strings to match.
			switch (NameR[11]) {
			default: break;
			case 'a': // 2 strings to match.
			if (NameR[12] != '.')
	break;		break;
	return Intrinsic::x86_avx2_psll_dq_bs; // "86.avx2.psll.dq		switch (NameR[13]) {
	.bs"		default: break;
	case 'r': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+11, "l.dq.bs", 7))		return Intrinsic::x86_avx2_psra_d; // "86.avx2.psra.d"
			case 'w': // 1 string to match.
			return Intrinsic::x86_avx2_psra_w; // "86.avx2.psra.w"
			}
			break;
			case 'l': // 3 strings to match.
			if (NameR[12] != '.')
	break;		break;
	return Intrinsic::x86_avx2_psrl_dq_bs; // "86.avx2.psrl.dq		switch (NameR[13]) {
	.bs"		default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx2_psrl_d; // "86.avx2.psrl.d"
			case 'q': // 1 string to match.
			return Intrinsic::x86_avx2_psrl_q; // "86.avx2.psrl.q"
			case 'w': // 1 string to match.
			return Intrinsic::x86_avx2_psrl_w; // "86.avx2.psrl.w"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'v': // 1 string to match.
	if (memcmp(NameR.data()+9, "perm2i128", 9))
	break;
	return Intrinsic::x86_avx2_vperm2i128; // "86.avx2.vperm2i
	128"
	}
	break;
	}
	break;
	case 's': // 13 strings to match.
	if (memcmp(NameR.data()+4, "se", 2))
	break;
	switch (NameR[6]) {
	default: break;
	case '.': // 2 strings to match.
	switch (NameR[7]) {
	default: break;
	case 'c': // 1 string to match.
	if (memcmp(NameR.data()+8, "vttss2si64", 10))
	break;
	return Intrinsic::x86_sse_cvttss2si64; // "86.sse.cvttss2s
	i64"
	case 'u': // 1 string to match.
	if (memcmp(NameR.data()+8, "comineq.ss", 10))
	break;
	return Intrinsic::x86_sse_ucomineq_ss; // "86.sse.ucomineq
	.ss"
	}		}
	break;		break;
	case '2': // 10 strings to match.		case 'b': // 6 strings to match.
	if (NameR[7] != '.')		if (memcmp(NameR.data()+4, "mi.", 3))
	break;		break;
	switch (NameR[8]) {		switch (NameR[7]) {
	default: break;		default: break;
	case 'c': // 3 strings to match.		case 'b': // 2 strings to match.
	switch (NameR[9]) {		if (memcmp(NameR.data()+8, "zhi.", 4))
	default: break;
	case 'o': // 1 string to match.
	if (memcmp(NameR.data()+10, "mineq.sd", 8))
	break;
	return Intrinsic::x86_sse2_comineq_sd; // "86.sse2.comineq
	.sd"
	case 'v': // 2 strings to match.
	if (memcmp(NameR.data()+10, "ts", 2))
	break;
	switch (NameR[12]) {
	default: break;
	case 'd': // 1 string to match.
	if (memcmp(NameR.data()+13, "2si64", 5))
	break;
	return Intrinsic::x86_sse2_cvtsd2si64; // "86.sse2.cvtsd2s
	i64"
	case 'i': // 1 string to match.
	if (memcmp(NameR.data()+13, "642sd", 5))
	break;
	return Intrinsic::x86_sse2_cvtsi642sd; // "86.sse2.cvtsi64
	2sd"
	}
	break;
	}
	break;
	case 'p': // 2 strings to match.
	if (NameR[9] != 's')
	break;		break;
	switch (NameR[10]) {		switch (NameR[12]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case '3': // 1 string to match.
	if (memcmp(NameR.data()+11, "l.dq.bs", 7))		if (NameR[13] != '2')
	break;		break;
	return Intrinsic::x86_sse2_psll_dq_bs; // "86.sse2.psll.dq		return Intrinsic::x86_bmi_bzhi_32; // "86.bmi.bzhi.32"
	.bs"		case '6': // 1 string to match.
	case 'r': // 1 string to match.		if (NameR[13] != '4')
	if (memcmp(NameR.data()+11, "l.dq.bs", 7))
	break;		break;
	return Intrinsic::x86_sse2_psrl_dq_bs; // "86.sse2.psrl.dq .bs"		return Intrinsic::x86_bmi_bzhi_64; // "86.bmi.bzhi.64"
	}		}
	break;		break;
	case 'u': // 5 strings to match.		case 'p': // 4 strings to match.
	if (memcmp(NameR.data()+9, "comi", 4))		switch (NameR[8]) {
	break;
	switch (NameR[13]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'd': // 2 strings to match.
	if (memcmp(NameR.data()+14, "q.sd", 4))		if (memcmp(NameR.data()+9, "ep.", 3))
	break;		break;
	return Intrinsic::x86_sse2_ucomieq_sd; // "86.sse2.ucomieq		switch (NameR[12]) {
	.sd"
	case 'g': // 2 strings to match.
	switch (NameR[14]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case '3': // 1 string to match.
	if (memcmp(NameR.data()+15, ".sd", 3))		if (NameR[13] != '2')
	break;		break;
	return Intrinsic::x86_sse2_ucomige_sd; // "86.sse2.ucomige		return Intrinsic::x86_bmi_pdep_32; // "86.bmi.pdep.32"
	.sd"		case '6': // 1 string to match.
	case 't': // 1 string to match.		if (NameR[13] != '4')
	if (memcmp(NameR.data()+15, ".sd", 3))
	break;		break;
	return Intrinsic::x86_sse2_ucomigt_sd; // "86.sse2.ucomigt .sd"		return Intrinsic::x86_bmi_pdep_64; // "86.bmi.pdep.64"
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'e': // 2 strings to match.
	switch (NameR[14]) {		if (memcmp(NameR.data()+9, "xt.", 3))
			break;
			switch (NameR[12]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case '3': // 1 string to match.
	if (memcmp(NameR.data()+15, ".sd", 3))		if (NameR[13] != '2')
	break;		break;
	return Intrinsic::x86_sse2_ucomile_sd; // "86.sse2.ucomile		return Intrinsic::x86_bmi_pext_32; // "86.bmi.pext.32"
	.sd"		case '6': // 1 string to match.
	case 't': // 1 string to match.		if (NameR[13] != '4')
	if (memcmp(NameR.data()+15, ".sd", 3))
	break;		break;
	return Intrinsic::x86_sse2_ucomilt_sd; // "86.sse2.ucomilt .sd"		return Intrinsic::x86_bmi_pext_64; // "86.bmi.pext.64"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case '4': // 1 string to match.		case 'k': // 2 strings to match.
	if (memcmp(NameR.data()+7, "1.extractps", 11))		switch (NameR[4]) {
	break;
	return Intrinsic::x86_sse41_extractps; // "86.sse41.extrac
	tps"
	}
	break;
	}
	break;
	case 19: // 41 strings to match.
	if (memcmp(NameR.data()+0, "86.", 3))
	break;
	switch (NameR[3]) {
	default: break;
	case 'a': // 25 strings to match.
	switch (NameR[4]) {
	default: break;
	case 'e': // 2 strings to match.
	if (memcmp(NameR.data()+5, "sni.aes", 7))
	break;
	switch (NameR[12]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(NameR.data()+13, "eclast", 6))		if (memcmp(NameR.data()+5, "ndn.v16i1", 9))
	break;		break;
	return Intrinsic::x86_aesni_aesdeclast; // "86.aesni.aesdec		return Intrinsic::x86_kandn_v16i1; // "86.kandn.v16i1"
	last"		case 'x': // 1 string to match.
	case 'e': // 1 string to match.		if (memcmp(NameR.data()+5, "nor.v16i1", 9))
	if (memcmp(NameR.data()+13, "nclast", 6))
	break;		break;
	return Intrinsic::x86_aesni_aesenclast; // "86.aesni.aesenc last"		return Intrinsic::x86_kxnor_v16i1; // "86.kxnor.v16i1"
	}		}
	break;		break;
	case 'v': // 23 strings to match.		case 'm': // 21 strings to match.
	if (NameR[5] != 'x')		if (memcmp(NameR.data()+4, "mx.p", 4))
	break;		break;
	switch (NameR[6]) {		switch (NameR[8]) {
	default: break;		default: break;
	case '.': // 8 strings to match.		case 'a': // 2 strings to match.
	switch (NameR[7]) {		if (memcmp(NameR.data()+9, "dds.", 4))
			break;
			switch (NameR[13]) {
	default: break;		default: break;
	case 'b': // 2 strings to match.		case 'b': // 1 string to match.
	if (memcmp(NameR.data()+8, "lend.p", 6))		return Intrinsic::x86_mmx_padds_b; // "86.mmx.padds.b"
			case 'w': // 1 string to match.
			return Intrinsic::x86_mmx_padds_w; // "86.mmx.padds.w"
			}
			break;
			case 'e': // 1 string to match.
			if (memcmp(NameR.data()+9, "xtr.w", 5))
			break;
			return Intrinsic::x86_mmx_pextr_w; // "86.mmx.pextr.w"
			case 'i': // 1 string to match.
			if (memcmp(NameR.data()+9, "nsr.w", 5))
			break;
			return Intrinsic::x86_mmx_pinsr_w; // "86.mmx.pinsr.w"
			case 'm': // 6 strings to match.
			switch (NameR[9]) {
			default: break;
			case 'a': // 2 strings to match.
			if (NameR[10] != 'x')
	break;		break;
	switch (NameR[14]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'd': // 1 string to match.
	if (memcmp(NameR.data()+15, ".256", 4))
	break;
	return Intrinsic::x86_avx_blend_pd_256; // "86.avx.
	blend.pd.256"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(NameR.data()+15, ".256", 4))		if (memcmp(NameR.data()+12, ".w", 2))
	break;		break;
	return Intrinsic::x86_avx_blend_ps_256; // "86.avx.		return Intrinsic::x86_mmx_pmaxs_w; // "86.mmx.pmaxs.w"
	blend.ps.256"		case 'u': // 1 string to match.
			if (memcmp(NameR.data()+12, ".b", 2))
			break;
			return Intrinsic::x86_mmx_pmaxu_b; // "86.mmx.pmaxu.b"
	}		}
	break;		break;
	case 'm': // 2 strings to match.		case 'i': // 2 strings to match.
	if (memcmp(NameR.data()+8, "askstore.p", 10))		if (NameR[10] != 'n')
	break;		break;
	switch (NameR[18]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_avx_maskstore_pd; // "86.avx.
	maskstore.pd"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	return Intrinsic::x86_avx_maskstore_ps; // "86.avx.		if (memcmp(NameR.data()+12, ".w", 2))
	maskstore.ps"		break;
			return Intrinsic::x86_mmx_pmins_w; // "86.mmx.pmins.w"
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+12, ".b", 2))
			break;
			return Intrinsic::x86_mmx_pminu_b; // "86.mmx.pminu.b"
	}		}
	break;		break;
	case 'p': // 1 string to match.		case 'u': // 2 strings to match.
	if (memcmp(NameR.data()+8, "testnzc.256", 11))		if (NameR[10] != 'l')
	break;		break;
	return Intrinsic::x86_avx_ptestnzc_256; // "86.avx.ptestnzc		switch (NameR[11]) {
	.256"
	case 'r': // 3 strings to match.
	switch (NameR[8]) {
	default: break;		default: break;
	case 'o': // 2 strings to match.		case 'h': // 1 string to match.
	if (memcmp(NameR.data()+9, "und.p", 5))		if (memcmp(NameR.data()+12, ".w", 2))
	break;		break;
	switch (NameR[14]) {		return Intrinsic::x86_mmx_pmulh_w; // "86.mmx.pmulh.w"
	default: break;		case 'l': // 1 string to match.
	case 'd': // 1 string to match.		if (memcmp(NameR.data()+12, ".w", 2))
	if (memcmp(NameR.data()+15, ".256", 4))
	break;
	return Intrinsic::x86_avx_round_pd_256; // "86.avx.
	round.pd.256"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+15, ".256", 4))
	break;
	return Intrinsic::x86_avx_round_ps_256; // "86.avx.
	round.ps.256"
	}
	break;
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+9, "qrt.ps.256", 10))
	break;		break;
	return Intrinsic::x86_avx_rsqrt_ps_256; // "86.avx. rsqrt.ps.256"		return Intrinsic::x86_mmx_pmull_w; // "86.mmx.pmull.w"
	}		}
	break;		break;
	}		}
	break;		break;
	case '2': // 15 strings to match.		case 's': // 11 strings to match.
	if (NameR[7] != '.')		switch (NameR[9]) {
	break;
	switch (NameR[8]) {
	default: break;		default: break;
	case 'g': // 4 strings to match.		case 'a': // 1 string to match.
	if (memcmp(NameR.data()+9, "ather.", 6))		if (memcmp(NameR.data()+10, "d.bw", 4))
	break;		break;
	switch (NameR[15]) {		return Intrinsic::x86_mmx_psad_bw; // "86.mmx.psad.bw"
			case 'l': // 3 strings to match.
			if (memcmp(NameR.data()+10, "li.", 3))
			break;
			switch (NameR[13]) {
	default: break;		default: break;
	case 'd': // 2 strings to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+16, ".p", 2))		return Intrinsic::x86_mmx_pslli_d; // "86.mmx.pslli.d"
			case 'q': // 1 string to match.
			return Intrinsic::x86_mmx_pslli_q; // "86.mmx.pslli.q"
			case 'w': // 1 string to match.
			return Intrinsic::x86_mmx_pslli_w; // "86.mmx.pslli.w"
			}
			break;
			case 'r': // 5 strings to match.
			switch (NameR[10]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(NameR.data()+11, "i.", 2))
	break;		break;
	switch (NameR[18]) {		switch (NameR[13]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::x86_avx2_gather_d_pd; // "86.avx2		return Intrinsic::x86_mmx_psrai_d; // "86.mmx.psrai.d"
	.gather.d.pd"		case 'w': // 1 string to match.
	case 's': // 1 string to match.		return Intrinsic::x86_mmx_psrai_w; // "86.mmx.psrai.w"
	return Intrinsic::x86_avx2_gather_d_ps; // "86.avx2
	.gather.d.ps"
	}		}
	break;		break;
	case 'q': // 2 strings to match.		case 'l': // 3 strings to match.
	if (memcmp(NameR.data()+16, ".p", 2))		if (memcmp(NameR.data()+11, "i.", 2))
	break;		break;
	switch (NameR[18]) {		switch (NameR[13]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::x86_avx2_gather_q_pd; // "86.avx2		return Intrinsic::x86_mmx_psrli_d; // "86.mmx.psrli.d"
	.gather.q.pd"		case 'q': // 1 string to match.
	case 's': // 1 string to match.		return Intrinsic::x86_mmx_psrli_q; // "86.mmx.psrli.q"
	return Intrinsic::x86_avx2_gather_q_ps; // "86.avx2		case 'w': // 1 string to match.
	.gather.q.ps"		return Intrinsic::x86_mmx_psrli_w; // "86.mmx.psrli.w"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'm': // 2 strings to match.		case 'u': // 2 strings to match.
	if (memcmp(NameR.data()+9, "askstore.", 9))		if (memcmp(NameR.data()+10, "bs.", 3))
	break;		break;
	switch (NameR[18]) {		switch (NameR[13]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::x86_avx2_maskstore_d; // "86.avx2		return Intrinsic::x86_mmx_psubs_b; // "86.mmx.psubs.b"
	.maskstore.d"		case 'w': // 1 string to match.
	case 'q': // 1 string to match.		return Intrinsic::x86_mmx_psubs_w; // "86.mmx.psubs.w"
	return Intrinsic::x86_avx2_maskstore_q; // "86.avx2
	.maskstore.q"
	}		}
	break;		break;
	case 'p': // 8 strings to match.		}
	switch (NameR[9]) {		break;
			}
			break;
			case 'r': // 4 strings to match.
			if (NameR[4] != 'd')
			break;
			switch (NameR[5]) {
			default: break;
			case 'f': // 2 strings to match.
			if (memcmp(NameR.data()+6, "sbase.", 6))
			break;
			switch (NameR[12]) {
			default: break;
			case '3': // 1 string to match.
			if (NameR[13] != '2')
			break;
			return Intrinsic::x86_rdfsbase_32; // "86.rdfsbase.32"
			case '6': // 1 string to match.
			if (NameR[13] != '4')
			break;
			return Intrinsic::x86_rdfsbase_64; // "86.rdfsbase.64"
			}
			break;
			case 'g': // 2 strings to match.
			if (memcmp(NameR.data()+6, "sbase.", 6))
			break;
			switch (NameR[12]) {
			default: break;
			case '3': // 1 string to match.
			if (NameR[13] != '2')
			break;
			return Intrinsic::x86_rdgsbase_32; // "86.rdgsbase.32"
			case '6': // 1 string to match.
			if (NameR[13] != '4')
			break;
			return Intrinsic::x86_rdgsbase_64; // "86.rdgsbase.64"
			}
			break;
			}
			break;
			case 's': // 30 strings to match.
			switch (NameR[4]) {
			default: break;
			case 'h': // 1 string to match.
			if (memcmp(NameR.data()+5, "a256rnds2", 9))
			break;
			return Intrinsic::x86_sha256rnds2; // "86.sha256rnds2"
			case 's': // 29 strings to match.
			if (NameR[5] != 'e')
			break;
			switch (NameR[6]) {
			default: break;
			case '.': // 5 strings to match.
			switch (NameR[7]) {
	default: break;		default: break;
	case 'b': // 2 strings to match.		case 'l': // 1 string to match.
	if (memcmp(NameR.data()+10, "lendd.", 6))		if (memcmp(NameR.data()+8, "dmxcsr", 6))
	break;		break;
	switch (NameR[16]) {		return Intrinsic::x86_sse_ldmxcsr; // "86.sse.ldmxcsr"
			case 'p': // 1 string to match.
			if (memcmp(NameR.data()+8, "shuf.w", 6))
			break;
			return Intrinsic::x86_sse_pshuf_w; // "86.sse.pshuf.w"
			case 's': // 3 strings to match.
			switch (NameR[8]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case 'q': // 2 strings to match.
	if (memcmp(NameR.data()+17, "28", 2))		if (memcmp(NameR.data()+9, "rt.", 3))
	break;		break;
	return Intrinsic::x86_avx2_pblendd_128; // "86.avx2		switch (NameR[12]) {
	.pblendd.128"		default: break;
	case '2': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(NameR.data()+17, "56", 2))		if (NameR[13] != 's')
			break;
			return Intrinsic::x86_sse_sqrt_ps; // "86.sse.sqrt.ps"
			case 's': // 1 string to match.
			if (NameR[13] != 's')
			break;
			return Intrinsic::x86_sse_sqrt_ss; // "86.sse.sqrt.ss"
			}
			break;
			case 't': // 1 string to match.
			if (memcmp(NameR.data()+9, "mxcsr", 5))
	break;		break;
	return Intrinsic::x86_avx2_pblendd_256; // "86.avx2 .pblendd.256"		return Intrinsic::x86_sse_stmxcsr; // "86.sse.stmxcsr"
	}		}
	break;		break;
	case 'm': // 1 string to match.		}
	if (memcmp(NameR.data()+10, "add.ub.sw", 9))		break;
			case '2': // 22 strings to match.
			if (NameR[7] != '.')
			break;
			switch (NameR[8]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(NameR.data()+9, "dd.sd", 5))
	break;		break;
	return Intrinsic::x86_avx2_pmadd_ub_sw; // "86.avx2		return Intrinsic::x86_sse2_add_sd; // "86.sse2.add.sd"
	.pmadd.ub.sw"		case 'c': // 2 strings to match.
	case 's': // 5 strings to match.		if (memcmp(NameR.data()+9, "mp.", 3))
	switch (NameR[10]) {		break;
			switch (NameR[12]) {
	default: break;		default: break;
	case 'l': // 2 strings to match.		case 'p': // 1 string to match.
	if (memcmp(NameR.data()+11, "lv.", 3))		if (NameR[13] != 'd')
	break;		break;
	switch (NameR[14]) {		return Intrinsic::x86_sse2_cmp_pd; // "86.sse2.cmp.pd"
			case 's': // 1 string to match.
			if (NameR[13] != 'd')
			break;
			return Intrinsic::x86_sse2_cmp_sd; // "86.sse2.cmp.sd"
			}
			break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+9, "iv.sd", 5))
			break;
			return Intrinsic::x86_sse2_div_sd; // "86.sse2.div.sd"
			case 'l': // 1 string to match.
			if (memcmp(NameR.data()+9, "fence", 5))
			break;
			return Intrinsic::x86_sse2_lfence; // "86.sse2.lfence"
			case 'm': // 6 strings to match.
			switch (NameR[9]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(NameR.data()+10, "x.", 2))
			break;
			switch (NameR[12]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(NameR.data()+15, ".256", 4))		if (NameR[13] != 'd')
	break;		break;
	return Intrinsic::x86_avx2_psllv_d_256; // "86.avx2		return Intrinsic::x86_sse2_max_pd; // "86.sse2.max.pd"
	.psllv.d.256"		case 's': // 1 string to match.
	case 'q': // 1 string to match.		if (NameR[13] != 'd')
	if (memcmp(NameR.data()+15, ".256", 4))
	break;		break;
	return Intrinsic::x86_avx2_psllv_q_256; // "86.avx2 .psllv.q.256"		return Intrinsic::x86_sse2_max_sd; // "86.sse2.max.sd"
	}		}
	break;		break;
	case 'r': // 3 strings to match.		case 'f': // 1 string to match.
	switch (NameR[11]) {		if (memcmp(NameR.data()+10, "ence", 4))
			break;
			return Intrinsic::x86_sse2_mfence; // "86.sse2.mfence"
			case 'i': // 2 strings to match.
			if (memcmp(NameR.data()+10, "n.", 2))
			break;
			switch (NameR[12]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(NameR.data()+12, "v.d.256", 7))		if (NameR[13] != 'd')
	break;		break;
	return Intrinsic::x86_avx2_psrav_d_256; // "86.avx2		return Intrinsic::x86_sse2_min_pd; // "86.sse2.min.pd"
	.psrav.d.256"		case 's': // 1 string to match.
	case 'l': // 2 strings to match.		if (NameR[13] != 'd')
	if (memcmp(NameR.data()+12, "v.", 2))
	break;		break;
	switch (NameR[14]) {		return Intrinsic::x86_sse2_min_sd; // "86.sse2.min.sd"
			}
			break;
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+10, "l.sd", 4))
			break;
			return Intrinsic::x86_sse2_mul_sd; // "86.sse2.mul.sd"
			}
			break;
			case 'p': // 10 strings to match.
			switch (NameR[9]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(NameR.data()+10, "vg.", 3))
			break;
			switch (NameR[13]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_sse2_pavg_b; // "86.sse2.pavg.b"
			case 'w': // 1 string to match.
			return Intrinsic::x86_sse2_pavg_w; // "86.sse2.pavg.w"
			}
			break;
			case 's': // 8 strings to match.
			switch (NameR[10]) {
			default: break;
			case 'l': // 3 strings to match.
			if (memcmp(NameR.data()+11, "l.", 2))
			break;
			switch (NameR[13]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+15, ".256", 4))		return Intrinsic::x86_sse2_psll_d; // "86.sse2
	break;		.psll.d"
	return Intrinsic::x86_avx2_psrlv_d_256; // "86.avx2
	.psrlv.d.256"
	case 'q': // 1 string to match.		case 'q': // 1 string to match.
	if (memcmp(NameR.data()+15, ".256", 4))		return Intrinsic::x86_sse2_psll_q; // "86.sse2
			.psll.q"
			case 'w': // 1 string to match.
			return Intrinsic::x86_sse2_psll_w; // "86.sse2
			.psll.w"
			}
			break;
			case 'r': // 5 strings to match.
			switch (NameR[11]) {
			default: break;
			case 'a': // 2 strings to match.
			if (NameR[12] != '.')
	break;		break;
	return Intrinsic::x86_avx2_psrlv_q_256; // "86.avx2		switch (NameR[13]) {
	.psrlv.q.256"		default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_sse2_psra_d; // "86.sse2
			.psra.d"
			case 'w': // 1 string to match.
			return Intrinsic::x86_sse2_psra_w; // "86.sse2
			.psra.w"
			}
			break;
			case 'l': // 3 strings to match.
			if (NameR[12] != '.')
			break;
			switch (NameR[13]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_sse2_psrl_d; // "86.sse2
			.psrl.d"
			case 'q': // 1 string to match.
			return Intrinsic::x86_sse2_psrl_q; // "86.sse2
			.psrl.q"
			case 'w': // 1 string to match.
			return Intrinsic::x86_sse2_psrl_w; // "86.sse2
			.psrl.w"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+9, "ub.sd", 5))
			break;
			return Intrinsic::x86_sse2_sub_sd; // "86.sse2.sub.sd"
	}		}
	break;		break;
	case 'v': // 1 string to match.		case '3': // 1 string to match.
	if (memcmp(NameR.data()+9, "inserti128", 10))		if (memcmp(NameR.data()+7, ".ldu.dq", 7))
	break;		break;
	return Intrinsic::x86_avx2_vinserti128; // "86.avx2.vinsert		return Intrinsic::x86_sse3_ldu_dq; // "86.sse3.ldu.dq"
	i128"		case '4': // 1 string to match.
			if (memcmp(NameR.data()+7, "a.extrq", 7))
			break;
			return Intrinsic::x86_sse4a_extrq; // "86.sse4a.extrq"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'w': // 4 strings to match.
	break;		if (NameR[4] != 'r')
	case 'f': // 4 strings to match.
	if (memcmp(NameR.data()+4, "ma.vfm", 6))
	break;
	switch (NameR[10]) {
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(NameR.data()+11, "ddsub.p", 7))
	break;
	switch (NameR[18]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_fma_vfmaddsub_pd; // "86.fma.vfmaddsu
	b.pd"
	case 's': // 1 string to match.
	return Intrinsic::x86_fma_vfmaddsub_ps; // "86.fma.vfmaddsu
	b.ps"
	}
	break;
	case 's': // 2 strings to match.
	if (memcmp(NameR.data()+11, "ubadd.p", 7))
	break;		break;
	switch (NameR[18]) {		switch (NameR[5]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_fma_vfmsubadd_pd; // "86.fma.vfmsubad
	d.pd"
	case 's': // 1 string to match.
	return Intrinsic::x86_fma_vfmsubadd_ps; // "86.fma.vfmsubad
	d.ps"
	}
	break;
	}
	break;
	case 's': // 10 strings to match.
	if (NameR[4] != 's')
	break;
	switch (NameR[5]) {
	default: break;
	case 'e': // 6 strings to match.
	switch (NameR[6]) {
	default: break;		default: break;
	case '2': // 3 strings to match.		case 'f': // 2 strings to match.
	if (NameR[7] != '.')		if (memcmp(NameR.data()+6, "sbase.", 6))
	break;		break;
	switch (NameR[8]) {		switch (NameR[12]) {
	default: break;		default: break;
	case 'c': // 1 string to match.		case '3': // 1 string to match.
	if (memcmp(NameR.data()+9, "vttsd2si64", 10))		if (NameR[13] != '2')
	break;
	return Intrinsic::x86_sse2_cvttsd2si64; // "86.sse2.cvttsd2
	si64"
	case 'm': // 1 string to match.
	if (memcmp(NameR.data()+9, "askmov.dqu", 10))
	break;		break;
	return Intrinsic::x86_sse2_maskmov_dqu; // "86.sse2.maskmov		return Intrinsic::x86_wrfsbase_32; // "86.wrfsbase.32"
	.dqu"		case '6': // 1 string to match.
	case 'u': // 1 string to match.		if (NameR[13] != '4')
	if (memcmp(NameR.data()+9, "comineq.sd", 10))
	break;		break;
	return Intrinsic::x86_sse2_ucomineq_sd; // "86.sse2.ucomine q.sd"		return Intrinsic::x86_wrfsbase_64; // "86.wrfsbase.64"
	}		}
	break;		break;
	case '4': // 3 strings to match.		case 'g': // 2 strings to match.
	switch (NameR[7]) {		if (memcmp(NameR.data()+6, "sbase.", 6))
			break;
			switch (NameR[12]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '3': // 1 string to match.
	if (memcmp(NameR.data()+8, ".phminposuw", 11))		if (NameR[13] != '2')
	break;		break;
	return Intrinsic::x86_sse41_phminposuw; // "86.sse41.phminp		return Intrinsic::x86_wrgsbase_32; // "86.wrgsbase.32"
	osuw"		case '6': // 1 string to match.
	case '2': // 2 strings to match.		if (NameR[13] != '4')
	if (memcmp(NameR.data()+8, ".crc32.", 7))
	break;		break;
	switch (NameR[15]) {		return Intrinsic::x86_wrgsbase_64; // "86.wrgsbase.64"
	default: break;
	case '3': // 1 string to match.
	if (memcmp(NameR.data()+16, "2.8", 3))
	break;
	return Intrinsic::x86_sse42_crc32_32_8; // "86.sse4
	2.crc32.32.8"
	case '6': // 1 string to match.
	if (memcmp(NameR.data()+16, "4.8", 3))
	break;
	return Intrinsic::x86_sse42_crc32_64_8; // "86.sse4
	2.crc32.64.8"
	}
	break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 's': // 4 strings to match.		case 'x': // 8 strings to match.
	if (memcmp(NameR.data()+6, "e3.p", 4))		if (memcmp(NameR.data()+4, "op.vp", 5))
	break;		break;
	switch (NameR[10]) {		switch (NameR[9]) {
	default: break;		default: break;
	case 'a': // 3 strings to match.		case 'c': // 4 strings to match.
	if (memcmp(NameR.data()+11, "bs.", 3))		if (memcmp(NameR.data()+10, "omu", 3))
	break;		break;
	switch (NameR[14]) {		switch (NameR[13]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(NameR.data()+15, ".128", 4))		return Intrinsic::x86_xop_vpcomub; // "86.xop.vpcomub"
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vpcomud; // "86.xop.vpcomud"
			case 'q': // 1 string to match.
			return Intrinsic::x86_xop_vpcomuq; // "86.xop.vpcomuq"
			case 'w': // 1 string to match.
			return Intrinsic::x86_xop_vpcomuw; // "86.xop.vpcomuw"
			}
			break;
			case 'r': // 4 strings to match.
			if (memcmp(NameR.data()+10, "ot", 2))
			break;
			switch (NameR[12]) {
			default: break;
			case 'b': // 1 string to match.
			if (NameR[13] != 'i')
	break;		break;
	return Intrinsic::x86_ssse3_pabs_b_128; // "86.ssse3.pabs.b .128"		return Intrinsic::x86_xop_vprotbi; // "86.xop.vprotbi"
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+15, ".128", 4))		if (NameR[13] != 'i')
	break;		break;
	return Intrinsic::x86_ssse3_pabs_d_128; // "86.ssse3.pabs.d		return Intrinsic::x86_xop_vprotdi; // "86.xop.vprotdi"
	.128"		case 'q': // 1 string to match.
			if (NameR[13] != 'i')
			break;
			return Intrinsic::x86_xop_vprotqi; // "86.xop.vprotqi"
	case 'w': // 1 string to match.		case 'w': // 1 string to match.
	if (memcmp(NameR.data()+15, ".128", 4))		if (NameR[13] != 'i')
	break;		break;
	return Intrinsic::x86_ssse3_pabs_w_128; // "86.ssse3.pabs.w .128"		return Intrinsic::x86_xop_vprotwi; // "86.xop.vprotwi"
	}		}
	break;		break;
	case 'm': // 1 string to match.
	if (memcmp(NameR.data()+11, "ul.hr.sw", 8))
	break;
	return Intrinsic::x86_ssse3_pmul_hr_sw; // "86.ssse3.pmul.h
	r.sw"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'x': // 2 strings to match.		case 'c': // 1 string to match.
	if (memcmp(NameR.data()+4, "op.vfrcz.p", 10))		if (memcmp(NameR.data()+1, "ore.waitevent", 13))
	break;		break;
	switch (NameR[14]) {		return Intrinsic::xcore_waitevent; // "core.waitevent"
	default: break;
	case 'd': // 1 string to match.
	if (memcmp(NameR.data()+15, ".256", 4))
	break;
	return Intrinsic::x86_xop_vfrcz_pd_256; // "86.xop.vfrcz.pd
	.256"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+15, ".256", 4))
	break;
	return Intrinsic::x86_xop_vfrcz_ps_256; // "86.xop.vfrcz.ps
	.256"
	}
	break;
	}		}
	break;		break;
	case 20: // 41 strings to match.		case 15: // 144 strings to match.
	if (memcmp(NameR.data()+0, "86.", 3))		switch (NameR[0]) {
	break;
	switch (NameR[3]) {
	default: break;		default: break;
	case 'a': // 21 strings to match.		case '8': // 143 strings to match.
	if (memcmp(NameR.data()+4, "vx", 2))		if (memcmp(NameR.data()+1, "6.", 2))
	break;		break;
	switch (NameR[6]) {		switch (NameR[3]) {
	default: break;		default: break;
	case '.': // 20 strings to match.		case '3': // 3 strings to match.
	switch (NameR[7]) {		if (memcmp(NameR.data()+4, "dnow", 4))
			break;
			switch (NameR[8]) {
	default: break;		default: break;
			case '.': // 1 string to match.
			if (memcmp(NameR.data()+9, "pfsubr", 6))
			break;
			return Intrinsic::x86_3dnow_pfsubr; // "86.3dnow.pfsubr
			"
	case 'a': // 2 strings to match.		case 'a': // 2 strings to match.
	if (memcmp(NameR.data()+8, "ddsub.p", 7))		if (memcmp(NameR.data()+9, ".p", 2))
	break;		break;
	switch (NameR[15]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'f': // 1 string to match.
	if (memcmp(NameR.data()+16, ".256", 4))		if (memcmp(NameR.data()+12, "2iw", 3))
	break;		break;
	return Intrinsic::x86_avx_addsub_pd_256; // "86.avx.addsub.p		return Intrinsic::x86_3dnowa_pf2iw; // "86.3dnowa.pf2iw
	d.256"		"
	case 's': // 1 string to match.		case 'i': // 1 string to match.
	if (memcmp(NameR.data()+16, ".256", 4))		if (memcmp(NameR.data()+12, "2fw", 3))
	break;		break;
	return Intrinsic::x86_avx_addsub_ps_256; // "86.avx.addsub.p s.256"		return Intrinsic::x86_3dnowa_pi2fw; // "86.3dnowa.pi2fw "
	}		}
	break;		break;
	case 'b': // 2 strings to match.		}
	if (memcmp(NameR.data()+8, "lendv.p", 7))		break;
			case 'a': // 48 strings to match.
			switch (NameR[4]) {
			default: break;
			case 'e': // 3 strings to match.
			if (memcmp(NameR.data()+5, "sni.aes", 7))
	break;		break;
	switch (NameR[15]) {		switch (NameR[12]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+16, ".256", 4))		if (memcmp(NameR.data()+13, "ec", 2))
	break;		break;
	return Intrinsic::x86_avx_blendv_pd_256; // "86.avx.blendv.p		return Intrinsic::x86_aesni_aesdec; // "86.aesni.aesdec
	d.256"		"
	case 's': // 1 string to match.		case 'e': // 1 string to match.
	if (memcmp(NameR.data()+16, ".256", 4))		if (memcmp(NameR.data()+13, "nc", 2))
	break;		break;
	return Intrinsic::x86_avx_blendv_ps_256; // "86.avx.blendv.p		return Intrinsic::x86_aesni_aesenc; // "86.aesni.aesenc
	s.256"		"
			case 'i': // 1 string to match.
			if (memcmp(NameR.data()+13, "mc", 2))
			break;
			return Intrinsic::x86_aesni_aesimc; // "86.aesni.aesimc
			"
	}		}
	break;		break;
	case 'c': // 4 strings to match.		case 'v': // 45 strings to match.
	if (memcmp(NameR.data()+8, "vt", 2))		if (NameR[5] != 'x')
	break;		break;
	switch (NameR[10]) {		switch (NameR[6]) {
	default: break;		default: break;
	case '.': // 2 strings to match.		case '.': // 1 string to match.
	if (NameR[11] != 'p')		if (memcmp(NameR.data()+7, "vzeroall", 8))
	break;		break;
	switch (NameR[12]) {		return Intrinsic::x86_avx_vzeroall; // "86.avx.vzeroall
	default: break;		"
	case 'd': // 1 string to match.		case '2': // 44 strings to match.
	if (memcmp(NameR.data()+13, "2dq.256", 7))		if (NameR[7] != '.')
	break;
	return Intrinsic::x86_avx_cvt_pd2dq_256; // "86.avx.
	cvt.pd2dq.256"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+13, "2dq.256", 7))
	break;
	return Intrinsic::x86_avx_cvt_ps2dq_256; // "86.avx.
	cvt.ps2dq.256"
	}
	break;
	case 'd': // 2 strings to match.
	if (memcmp(NameR.data()+11, "q2.p", 4))
	break;		break;
	switch (NameR[15]) {		switch (NameR[8]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'm': // 1 string to match.
	if (memcmp(NameR.data()+16, ".256", 4))		if (memcmp(NameR.data()+9, "psadbw", 6))
	break;		break;
	return Intrinsic::x86_avx_cvtdq2_pd_256; // "86.avx.		return Intrinsic::x86_avx2_mpsadbw; // "86.avx2.mpsadbw
	cvtdq2.pd.256"		"
	case 's': // 1 string to match.		case 'p': // 43 strings to match.
	if (memcmp(NameR.data()+16, ".256", 4))		switch (NameR[9]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(NameR.data()+10, "dds.", 4))
			break;
			switch (NameR[14]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_avx2_padds_b; // "86.avx2
			.padds.b"
			case 'w': // 1 string to match.
			return Intrinsic::x86_avx2_padds_w; // "86.avx2
			.padds.w"
			}
	break;		break;
	return Intrinsic::x86_avx_cvtdq2_ps_256; // "86.avx.		case 'b': // 1 string to match.
	cvtdq2.ps.256"		if (memcmp(NameR.data()+10, "lendw", 5))
			break;
			return Intrinsic::x86_avx2_pblendw; // "86.avx2.pblendw
			"
			case 'h': // 4 strings to match.
			switch (NameR[10]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(NameR.data()+11, "dd.", 3))
			break;
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx2_phadd_d; // "86.avx2
			.phadd.d"
			case 'w': // 1 string to match.
			return Intrinsic::x86_avx2_phadd_w; // "86.avx2
			.phadd.w"
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(NameR.data()+11, "ub.", 3))
			break;
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx2_phsub_d; // "86.avx2
			.phsub.d"
			case 'w': // 1 string to match.
			return Intrinsic::x86_avx2_phsub_w; // "86.avx2
			.phsub.w"
			}
			break;
			}
			break;
			case 'm': // 14 strings to match.
			switch (NameR[10]) {
			default: break;
			case 'a': // 6 strings to match.
			if (NameR[11] != 'x')
			break;
			switch (NameR[12]) {
			default: break;
			case 's': // 3 strings to match.
			if (NameR[13] != '.')
			break;
			switch (NameR[14]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_avx2_pmaxs_b; // "86.avx2
			.pmaxs.b"
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx2_pmaxs_d; // "86.avx2
			.pmaxs.d"
			case 'w': // 1 string to match.
			return Intrinsic::x86_avx2_pmaxs_w; // "86.avx2
			.pmaxs.w"
			}
			break;
			case 'u': // 3 strings to match.
			if (NameR[13] != '.')
			break;
			switch (NameR[14]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_avx2_pmaxu_b; // "86.avx2
			.pmaxu.b"
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx2_pmaxu_d; // "86.avx2
			.pmaxu.d"
			case 'w': // 1 string to match.
			return Intrinsic::x86_avx2_pmaxu_w; // "86.avx2
			.pmaxu.w"
			}
			break;
			}
			break;
			case 'i': // 6 strings to match.
			if (NameR[11] != 'n')
			break;
			switch (NameR[12]) {
			default: break;
			case 's': // 3 strings to match.
			if (NameR[13] != '.')
			break;
			switch (NameR[14]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_avx2_pmins_b; // "86.avx2
			.pmins.b"
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx2_pmins_d; // "86.avx2
			.pmins.d"
			case 'w': // 1 string to match.
			return Intrinsic::x86_avx2_pmins_w; // "86.avx2
			.pmins.w"
			}
			break;
			case 'u': // 3 strings to match.
			if (NameR[13] != '.')
			break;
			switch (NameR[14]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_avx2_pminu_b; // "86.avx2
			.pminu.b"
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx2_pminu_d; // "86.avx2
			.pminu.d"
			case 'w': // 1 string to match.
			return Intrinsic::x86_avx2_pminu_w; // "86.avx2
			.pminu.w"
			}
			break;
			}
			break;
			case 'u': // 2 strings to match.
			if (NameR[11] != 'l')
			break;
			switch (NameR[12]) {
			default: break;
			case '.': // 1 string to match.
			if (memcmp(NameR.data()+13, "dq", 2))
			break;
			return Intrinsic::x86_avx2_pmul_dq; // "86.avx2
			.pmul.dq"
			case 'h': // 1 string to match.
			if (memcmp(NameR.data()+13, ".w", 2))
			break;
			return Intrinsic::x86_avx2_pmulh_w; // "86.avx2
			.pmulh.w"
			}
			break;
			}
			break;
			case 's': // 22 strings to match.
			switch (NameR[10]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(NameR.data()+11, "d.bw", 4))
			break;
			return Intrinsic::x86_avx2_psad_bw; // "86.avx2
			.psad.bw"
			case 'h': // 1 string to match.
			if (memcmp(NameR.data()+11, "uf.b", 4))
			break;
			return Intrinsic::x86_avx2_pshuf_b; // "86.avx2
			.pshuf.b"
			case 'i': // 3 strings to match.
			if (memcmp(NameR.data()+11, "gn.", 3))
			break;
			switch (NameR[14]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_avx2_psign_b; // "86.avx2
			.psign.b"
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx2_psign_d; // "86.avx2
			.psign.d"
			case 'w': // 1 string to match.
			return Intrinsic::x86_avx2_psign_w; // "86.avx2
			.psign.w"
			}
			break;
			case 'l': // 6 strings to match.
			if (NameR[11] != 'l')
			break;
			switch (NameR[12]) {
			default: break;
			case '.': // 1 string to match.
			if (memcmp(NameR.data()+13, "dq", 2))
			break;
			return Intrinsic::x86_avx2_psll_dq; // "86.avx2
			.psll.dq"
			case 'i': // 3 strings to match.
			if (NameR[13] != '.')
			break;
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx2_pslli_d; // "86.avx2
			.pslli.d"
			case 'q': // 1 string to match.
			return Intrinsic::x86_avx2_pslli_q; // "86.avx2
			.pslli.q"
			case 'w': // 1 string to match.
			return Intrinsic::x86_avx2_pslli_w; // "86.avx2
			.pslli.w"
			}
			break;
			case 'v': // 2 strings to match.
			if (NameR[13] != '.')
			break;
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx2_psllv_d; // "86.avx2
			.psllv.d"
			case 'q': // 1 string to match.
			return Intrinsic::x86_avx2_psllv_q; // "86.avx2
			.psllv.q"
			}
			break;
			}
			break;
			case 'r': // 9 strings to match.
			switch (NameR[11]) {
			default: break;
			case 'a': // 3 strings to match.
			switch (NameR[12]) {
			default: break;
			case 'i': // 2 strings to match.
			if (NameR[13] != '.')
			break;
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx2_psrai_d; // "86.avx2
			.psrai.d"
			case 'w': // 1 string to match.
			return Intrinsic::x86_avx2_psrai_w; // "86.avx2
			.psrai.w"
			}
			break;
			case 'v': // 1 string to match.
			if (memcmp(NameR.data()+13, ".d", 2))
			break;
			return Intrinsic::x86_avx2_psrav_d; // "86.avx2
			.psrav.d"
			}
			break;
			case 'l': // 6 strings to match.
			switch (NameR[12]) {
			default: break;
			case '.': // 1 string to match.
			if (memcmp(NameR.data()+13, "dq", 2))
			break;
			return Intrinsic::x86_avx2_psrl_dq; // "86.avx2
			.psrl.dq"
			case 'i': // 3 strings to match.
			if (NameR[13] != '.')
			break;
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx2_psrli_d; // "86.avx2
			.psrli.d"
			case 'q': // 1 string to match.
			return Intrinsic::x86_avx2_psrli_q; // "86.avx2
			.psrli.q"
			case 'w': // 1 string to match.
			return Intrinsic::x86_avx2_psrli_w; // "86.avx2
			.psrli.w"
			}
			break;
			case 'v': // 2 strings to match.
			if (NameR[13] != '.')
			break;
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx2_psrlv_d; // "86.avx2
			.psrlv.d"
			case 'q': // 1 string to match.
			return Intrinsic::x86_avx2_psrlv_q; // "86.avx2
			.psrlv.q"
			}
			break;
			}
			break;
			}
			break;
			case 'u': // 2 strings to match.
			if (memcmp(NameR.data()+11, "bs.", 3))
			break;
			switch (NameR[14]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_avx2_psubs_b; // "86.avx2
			.psubs.b"
			case 'w': // 1 string to match.
			return Intrinsic::x86_avx2_psubs_w; // "86.avx2
			.psubs.w"
			}
			break;
			}
			break;
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'm': // 2 strings to match.		}
	if (memcmp(NameR.data()+8, "ovmsk.p", 7))		break;
			case 'b': // 2 strings to match.
			if (memcmp(NameR.data()+4, "mi.bextr.", 9))
			break;
			switch (NameR[13]) {
			default: break;
			case '3': // 1 string to match.
			if (NameR[14] != '2')
	break;		break;
	switch (NameR[15]) {		return Intrinsic::x86_bmi_bextr_32; // "86.bmi.bextr.32
			"
			case '6': // 1 string to match.
			if (NameR[14] != '4')
			break;
			return Intrinsic::x86_bmi_bextr_64; // "86.bmi.bextr.64
			"
			}
			break;
			case 'k': // 1 string to match.
			if (memcmp(NameR.data()+4, "unpck.v16i1", 11))
			break;
			return Intrinsic::x86_kunpck_v16i1; // "86.kunpck.v16i1"
			case 'm': // 19 strings to match.
			if (memcmp(NameR.data()+4, "mx.", 3))
			break;
			switch (NameR[7]) {
			default: break;
			case 'm': // 2 strings to match.
			switch (NameR[8]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(NameR.data()+16, ".256", 4))		if (memcmp(NameR.data()+9, "skmovq", 6))
	break;		break;
	return Intrinsic::x86_avx_movmsk_pd_256; // "86.avx.movmsk.p		return Intrinsic::x86_mmx_maskmovq; // "86.mmx.maskmovq
	d.256"		"
	case 's': // 1 string to match.		case 'o': // 1 string to match.
	if (memcmp(NameR.data()+16, ".256", 4))		if (memcmp(NameR.data()+9, "vnt.dq", 6))
	break;		break;
	return Intrinsic::x86_avx_movmsk_ps_256; // "86.avx.movmsk.p s.256"		return Intrinsic::x86_mmx_movnt_dq; // "86.mmx.movnt.dq "
	}		}
	break;		break;
	case 's': // 3 strings to match.		case 'p': // 17 strings to match.
	if (memcmp(NameR.data()+8, "toreu.", 6))		switch (NameR[8]) {
	break;
	switch (NameR[14]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'a': // 5 strings to match.
	if (memcmp(NameR.data()+15, "q.256", 5))		switch (NameR[9]) {
	break;
	return Intrinsic::x86_avx_storeu_dq_256; // "86.avx.storeu.d
	q.256"
	case 'p': // 2 strings to match.
	switch (NameR[15]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'c': // 3 strings to match.
	if (memcmp(NameR.data()+16, ".256", 4))		if (NameR[10] != 'k')
	break;		break;
	return Intrinsic::x86_avx_storeu_pd_256; // "86.avx.		switch (NameR[11]) {
	storeu.pd.256"		default: break;
	case 's': // 1 string to match.		case 's': // 2 strings to match.
	if (memcmp(NameR.data()+16, ".256", 4))		if (NameR[12] != 's')
			break;
			switch (NameR[13]) {
			default: break;
			case 'd': // 1 string to match.
			if (NameR[14] != 'w')
			break;
			return Intrinsic::x86_mmx_packssdw; // "86.mmx.
			packssdw"
			case 'w': // 1 string to match.
			if (NameR[14] != 'b')
			break;
			return Intrinsic::x86_mmx_packsswb; // "86.mmx.
			packsswb"
			}
	break;		break;
	return Intrinsic::x86_avx_storeu_ps_256; // "86.avx.		case 'u': // 1 string to match.
	storeu.ps.256"		if (memcmp(NameR.data()+12, "swb", 3))
	}		break;
	break;		return Intrinsic::x86_mmx_packuswb; // "86.mmx.packuswb
	}		"
	break;		}
	case 'v': // 7 strings to match.
	switch (NameR[8]) {
	default: break;
	case 'b': // 1 string to match.
	if (memcmp(NameR.data()+9, "roadcast.ss", 11))
	break;		break;
	return Intrinsic::x86_avx_vbroadcast_ss; // "86.avx.vbroadca		case 'd': // 2 strings to match.
	st.ss"		if (memcmp(NameR.data()+10, "dus.", 4))
	case 'p': // 2 strings to match.		break;
	if (memcmp(NameR.data()+9, "ermilvar.p", 10))		switch (NameR[14]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_mmx_paddus_b; // "86.mmx.paddus.b
			"
			case 'w': // 1 string to match.
			return Intrinsic::x86_mmx_paddus_w; // "86.mmx.paddus.w
			"
			}
	break;		break;
	switch (NameR[19]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_avx_vpermilvar_pd; // "86.avx.
	vpermilvar.pd"
	case 's': // 1 string to match.
	return Intrinsic::x86_avx_vpermilvar_ps; // "86.avx.
	vpermilvar.ps"
	}		}
	break;		break;
	case 't': // 4 strings to match.		case 'c': // 6 strings to match.
	if (memcmp(NameR.data()+9, "est", 3))		if (memcmp(NameR.data()+9, "mp", 2))
	break;		break;
	switch (NameR[12]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'c': // 2 strings to match.		case 'e': // 3 strings to match.
	if (memcmp(NameR.data()+13, ".p", 2))		if (memcmp(NameR.data()+12, "q.", 2))
	break;		break;
	switch (NameR[15]) {		switch (NameR[14]) {
	default: break;		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_mmx_pcmpeq_b; // "86.mmx.pcmpeq.b
			"
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+16, ".256", 4))		return Intrinsic::x86_mmx_pcmpeq_d; // "86.mmx.pcmpeq.d
	break;		"
	return Intrinsic::x86_avx_vtestc_pd_256; // "86.avx.		case 'w': // 1 string to match.
	vtestc.pd.256"		return Intrinsic::x86_mmx_pcmpeq_w; // "86.mmx.pcmpeq.w
	case 's': // 1 string to match.		"
	if (memcmp(NameR.data()+16, ".256", 4))
	break;
	return Intrinsic::x86_avx_vtestc_ps_256; // "86.avx.
	vtestc.ps.256"
	}		}
	break;		break;
	case 'z': // 2 strings to match.		case 'g': // 3 strings to match.
	if (memcmp(NameR.data()+13, ".p", 2))		if (memcmp(NameR.data()+12, "t.", 2))
	break;		break;
	switch (NameR[15]) {		switch (NameR[14]) {
	default: break;		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_mmx_pcmpgt_b; // "86.mmx.pcmpgt.b
			"
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+16, ".256", 4))		return Intrinsic::x86_mmx_pcmpgt_d; // "86.mmx.pcmpgt.d
	break;		"
	return Intrinsic::x86_avx_vtestz_pd_256; // "86.avx.		case 'w': // 1 string to match.
	vtestz.pd.256"		return Intrinsic::x86_mmx_pcmpgt_w; // "86.mmx.pcmpgt.w
	case 's': // 1 string to match.		"
	if (memcmp(NameR.data()+16, ".256", 4))
	break;
	return Intrinsic::x86_avx_vtestz_ps_256; // "86.avx.
	vtestz.ps.256"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'm': // 4 strings to match.
	break;		switch (NameR[9]) {
	}
	break;
	case '2': // 1 string to match.
	if (memcmp(NameR.data()+7, ".vextracti128", 13))
	break;
	return Intrinsic::x86_avx2_vextracti128; // "86.avx2.vextrac
	ti128"
	}
	break;
	case 'f': // 4 strings to match.
	if (memcmp(NameR.data()+4, "ma.vfm", 6))
	break;
	switch (NameR[10]) {
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(NameR.data()+11, "dd.p", 4))
	break;
	switch (NameR[15]) {
	default: break;
	case 'd': // 1 string to match.
	if (memcmp(NameR.data()+16, ".256", 4))
	break;
	return Intrinsic::x86_fma_vfmadd_pd_256; // "86.fma.vfmadd.p
	d.256"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+16, ".256", 4))
	break;
	return Intrinsic::x86_fma_vfmadd_ps_256; // "86.fma.vfmadd.p
	s.256"
	}
	break;
	case 's': // 2 strings to match.
	if (memcmp(NameR.data()+11, "ub.p", 4))
	break;
	switch (NameR[15]) {
	default: break;
	case 'd': // 1 string to match.
	if (memcmp(NameR.data()+16, ".256", 4))
	break;
	return Intrinsic::x86_fma_vfmsub_pd_256; // "86.fma.vfmsub.p
	d.256"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+16, ".256", 4))
	break;
	return Intrinsic::x86_fma_vfmsub_ps_256; // "86.fma.vfmsub.p
	s.256"
	}
	break;
	}
	break;
	case 's': // 16 strings to match.
	if (NameR[4] != 's')
	break;
	switch (NameR[5]) {
	default: break;
	case 'e': // 7 strings to match.
	switch (NameR[6]) {
	default: break;
	case '2': // 4 strings to match.
	if (memcmp(NameR.data()+7, ".p", 2))
	break;
	switch (NameR[9]) {
	default: break;
	case 'a': // 3 strings to match.
	if (memcmp(NameR.data()+10, "ck", 2))
	break;
	switch (NameR[12]) {
	default: break;		default: break;
	case 's': // 2 strings to match.		case 'a': // 1 string to match.
	if (NameR[13] != 's')		if (memcmp(NameR.data()+10, "dd.wd", 5))
	break;		break;
	switch (NameR[14]) {		return Intrinsic::x86_mmx_pmadd_wd; // "86.mmx.pmadd.wd
			"
			case 'o': // 1 string to match.
			if (memcmp(NameR.data()+10, "vmskb", 5))
			break;
			return Intrinsic::x86_mmx_pmovmskb; // "86.mmx.pmovmskb
			"
			case 'u': // 2 strings to match.
			if (NameR[10] != 'l')
			break;
			switch (NameR[11]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'h': // 1 string to match.
	if (memcmp(NameR.data()+15, "w.128", 5))		if (memcmp(NameR.data()+12, "u.w", 3))
	break;		break;
	return Intrinsic::x86_sse2_packssdw_128; // "86.sse2		return Intrinsic::x86_mmx_pmulhu_w; // "86.mmx.pmulhu.w
	.packssdw.128"		"
	case 'w': // 1 string to match.		case 'u': // 1 string to match.
	if (memcmp(NameR.data()+15, "b.128", 5))		if (memcmp(NameR.data()+12, ".dq", 3))
	break;		break;
	return Intrinsic::x86_sse2_packsswb_128; // "86.sse2 .packsswb.128"		return Intrinsic::x86_mmx_pmulu_dq; // "86.mmx.pmulu.dq "
	}		}
	break;		break;
	case 'u': // 1 string to match.
	if (memcmp(NameR.data()+13, "swb.128", 7))
	break;
	return Intrinsic::x86_sse2_packuswb_128; // "86.sse2
	.packuswb.128"
	}		}
	break;		break;
	case 'm': // 1 string to match.		case 's': // 2 strings to match.
	if (memcmp(NameR.data()+10, "ovmskb.128", 10))		if (memcmp(NameR.data()+9, "ubus.", 5))
	break;		break;
	return Intrinsic::x86_sse2_pmovmskb_128; // "86.sse2.pmovmsk		switch (NameR[14]) {
	b.128"		default: break;
	}		case 'b': // 1 string to match.
	break;		return Intrinsic::x86_mmx_psubus_b; // "86.mmx.psubus.b
	case '4': // 3 strings to match.		"
	if (memcmp(NameR.data()+7, "2.crc32.", 8))		case 'w': // 1 string to match.
	break;		return Intrinsic::x86_mmx_psubus_w; // "86.mmx.psubus.w
	switch (NameR[15]) {		"
	default: break;		}
	case '3': // 2 strings to match.		break;
	if (memcmp(NameR.data()+16, "2.", 2))
	break;
	switch (NameR[18]) {
	default: break;
	case '1': // 1 string to match.
	if (NameR[19] != '6')
	break;
	return Intrinsic::x86_sse42_crc32_32_16; // "86.sse4
	2.crc32.32.16"
	case '3': // 1 string to match.
	if (NameR[19] != '2')
	break;
	return Intrinsic::x86_sse42_crc32_32_32; // "86.sse4
	2.crc32.32.32"
	}
	break;
	case '6': // 1 string to match.
	if (memcmp(NameR.data()+16, "4.64", 4))
	break;
	return Intrinsic::x86_sse42_crc32_64_64; // "86.sse42.crc32.
	64.64"
	}		}
	break;		break;
	}		}
	break;		break;
	case 's': // 9 strings to match.		case 's': // 54 strings to match.
	if (memcmp(NameR.data()+6, "e3.p", 4))		if (NameR[4] != 's')
	break;		break;
	switch (NameR[10]) {		switch (NameR[5]) {
	default: break;		default: break;
	case 'h': // 4 strings to match.		case 'e': // 51 strings to match.
	switch (NameR[11]) {		switch (NameR[6]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case '.': // 8 strings to match.
	if (memcmp(NameR.data()+12, "dd.", 3))		switch (NameR[7]) {
	break;
	switch (NameR[15]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'c': // 6 strings to match.
	if (memcmp(NameR.data()+16, ".128", 4))		if (memcmp(NameR.data()+8, "vt", 2))
	break;		break;
	return Intrinsic::x86_ssse3_phadd_d_128; // "86.ssse		switch (NameR[10]) {
	3.phadd.d.128"		default: break;
	case 'w': // 1 string to match.		case 'p': // 4 strings to match.
	if (memcmp(NameR.data()+16, ".128", 4))		switch (NameR[11]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+12, "2pi", 3))
			break;
			return Intrinsic::x86_sse_cvtpd2pi; // "86.sse.
			cvtpd2pi"
			case 'i': // 2 strings to match.
			if (memcmp(NameR.data()+12, "2p", 2))
			break;
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_sse_cvtpi2pd; // "86.sse.
			cvtpi2pd"
			case 's': // 1 string to match.
			return Intrinsic::x86_sse_cvtpi2ps; // "86.sse.
			cvtpi2ps"
			}
			break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+12, "2pi", 3))
			break;
			return Intrinsic::x86_sse_cvtps2pi; // "86.sse.
			cvtps2pi"
			}
	break;		break;
	return Intrinsic::x86_ssse3_phadd_w_128; // "86.ssse		case 's': // 2 strings to match.
	3.phadd.w.128"		switch (NameR[11]) {
			default: break;
			case 'i': // 1 string to match.
			if (memcmp(NameR.data()+12, "2ss", 3))
			break;
			return Intrinsic::x86_sse_cvtsi2ss; // "86.sse.
			cvtsi2ss"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+12, "2si", 3))
			break;
			return Intrinsic::x86_sse_cvtss2si; // "86.sse.
			cvtss2si"
			}
			break;
			}
			break;
			case 'r': // 2 strings to match.
			if (memcmp(NameR.data()+8, "sqrt.", 5))
			break;
			switch (NameR[13]) {
			default: break;
			case 'p': // 1 string to match.
			if (NameR[14] != 's')
			break;
			return Intrinsic::x86_sse_rsqrt_ps; // "86.sse.rsqrt.ps
			"
			case 's': // 1 string to match.
			if (NameR[14] != 's')
			break;
			return Intrinsic::x86_sse_rsqrt_ss; // "86.sse.rsqrt.ss
			"
			}
			break;
	}		}
	break;		break;
	case 's': // 2 strings to match.		case '2': // 23 strings to match.
	if (memcmp(NameR.data()+12, "ub.", 3))		if (NameR[7] != '.')
	break;		break;
	switch (NameR[15]) {		switch (NameR[8]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'c': // 1 string to match.
	if (memcmp(NameR.data()+16, ".128", 4))		if (memcmp(NameR.data()+9, "lflush", 6))
	break;		break;
	return Intrinsic::x86_ssse3_phsub_d_128; // "86.ssse		return Intrinsic::x86_sse2_clflush; // "86.sse2.clflush
	3.phsub.d.128"		"
	case 'w': // 1 string to match.		case 'p': // 20 strings to match.
	if (memcmp(NameR.data()+16, ".128", 4))		switch (NameR[9]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(NameR.data()+10, "dds.", 4))
			break;
			switch (NameR[14]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_sse2_padds_b; // "86.sse2
			.padds.b"
			case 'w': // 1 string to match.
			return Intrinsic::x86_sse2_padds_w; // "86.sse2
			.padds.w"
			}
	break;		break;
	return Intrinsic::x86_ssse3_phsub_w_128; // "86.ssse		case 'm': // 5 strings to match.
	3.phsub.w.128"		switch (NameR[10]) {
			default: break;
			case 'a': // 2 strings to match.
			if (NameR[11] != 'x')
			break;
			switch (NameR[12]) {
			default: break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+13, ".w", 2))
			break;
			return Intrinsic::x86_sse2_pmaxs_w; // "86.sse2
			.pmaxs.w"
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+13, ".b", 2))
			break;
			return Intrinsic::x86_sse2_pmaxu_b; // "86.sse2
			.pmaxu.b"
			}
			break;
			case 'i': // 2 strings to match.
			if (NameR[11] != 'n')
			break;
			switch (NameR[12]) {
			default: break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+13, ".w", 2))
			break;
			return Intrinsic::x86_sse2_pmins_w; // "86.sse2
			.pmins.w"
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+13, ".b", 2))
			break;
			return Intrinsic::x86_sse2_pminu_b; // "86.sse2
			.pminu.b"
			}
			break;
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+11, "lh.w", 4))
			break;
			return Intrinsic::x86_sse2_pmulh_w; // "86.sse2
			.pmulh.w"
			}
			break;
			case 's': // 13 strings to match.
			switch (NameR[10]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(NameR.data()+11, "d.bw", 4))
			break;
			return Intrinsic::x86_sse2_psad_bw; // "86.sse2
			.psad.bw"
			case 'l': // 4 strings to match.
			if (NameR[11] != 'l')
			break;
			switch (NameR[12]) {
			default: break;
			case '.': // 1 string to match.
			if (memcmp(NameR.data()+13, "dq", 2))
			break;
			return Intrinsic::x86_sse2_psll_dq; // "86.sse2
			.psll.dq"
			case 'i': // 3 strings to match.
			if (NameR[13] != '.')
			break;
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_sse2_pslli_d; // "86.sse2
			.pslli.d"
			case 'q': // 1 string to match.
			return Intrinsic::x86_sse2_pslli_q; // "86.sse2
			.pslli.q"
			case 'w': // 1 string to match.
			return Intrinsic::x86_sse2_pslli_w; // "86.sse2
			.pslli.w"
			}
			break;
			}
			break;
			case 'r': // 6 strings to match.
			switch (NameR[11]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(NameR.data()+12, "i.", 2))
			break;
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_sse2_psrai_d; // "86.sse2
			.psrai.d"
			case 'w': // 1 string to match.
			return Intrinsic::x86_sse2_psrai_w; // "86.sse2
			.psrai.w"
			}
			break;
			case 'l': // 4 strings to match.
			switch (NameR[12]) {
			default: break;
			case '.': // 1 string to match.
			if (memcmp(NameR.data()+13, "dq", 2))
			break;
			return Intrinsic::x86_sse2_psrl_dq; // "86.sse2
			.psrl.dq"
			case 'i': // 3 strings to match.
			if (NameR[13] != '.')
			break;
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_sse2_psrli_d; // "86.sse2
			.psrli.d"
			case 'q': // 1 string to match.
			return Intrinsic::x86_sse2_psrli_q; // "86.sse2
			.psrli.q"
			case 'w': // 1 string to match.
			return Intrinsic::x86_sse2_psrli_w; // "86.sse2
			.psrli.w"
			}
			break;
			}
			break;
			}
			break;
			case 'u': // 2 strings to match.
			if (memcmp(NameR.data()+11, "bs.", 3))
			break;
			switch (NameR[14]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_sse2_psubs_b; // "86.sse2
			.psubs.b"
			case 'w': // 1 string to match.
			return Intrinsic::x86_sse2_psubs_w; // "86.sse2
			.psubs.w"
			}
			break;
			}
			break;
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(NameR.data()+9, "qrt.", 4))
			break;
			switch (NameR[13]) {
			default: break;
			case 'p': // 1 string to match.
			if (NameR[14] != 'd')
			break;
			return Intrinsic::x86_sse2_sqrt_pd; // "86.sse2.sqrt.pd
			"
			case 's': // 1 string to match.
			if (NameR[14] != 'd')
			break;
			return Intrinsic::x86_sse2_sqrt_sd; // "86.sse2.sqrt.sd
			"
			}
			break;
	}		}
	break;		break;
	}		case '3': // 5 strings to match.
	break;		if (NameR[7] != '.')
	case 'm': // 1 string to match.
	if (memcmp(NameR.data()+11, "add.ub.sw", 9))
	break;
	return Intrinsic::x86_ssse3_pmadd_ub_sw; // "86.ssse3.pmadd.
	ub.sw"
	case 's': // 4 strings to match.
	switch (NameR[11]) {
	default: break;
	case 'h': // 1 string to match.
	if (memcmp(NameR.data()+12, "uf.b.128", 8))
	break;		break;
	return Intrinsic::x86_ssse3_pshuf_b_128; // "86.ssse3.pshuf.		switch (NameR[8]) {
	b.128"		default: break;
	case 'i': // 3 strings to match.		case 'h': // 4 strings to match.
	if (memcmp(NameR.data()+12, "gn.", 3))		switch (NameR[9]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(NameR.data()+10, "dd.p", 4))
			break;
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_sse3_hadd_pd; // "86.sse3
			.hadd.pd"
			case 's': // 1 string to match.
			return Intrinsic::x86_sse3_hadd_ps; // "86.sse3
			.hadd.ps"
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(NameR.data()+10, "ub.p", 4))
			break;
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_sse3_hsub_pd; // "86.sse3
			.hsub.pd"
			case 's': // 1 string to match.
			return Intrinsic::x86_sse3_hsub_ps; // "86.sse3
			.hsub.ps"
			}
			break;
			}
	break;		break;
	switch (NameR[15]) {		case 'm': // 1 string to match.
			if (memcmp(NameR.data()+9, "onitor", 6))
			break;
			return Intrinsic::x86_sse3_monitor; // "86.sse3.monitor
			"
			}
			break;
			case '4': // 15 strings to match.
			switch (NameR[7]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case '1': // 14 strings to match.
	if (memcmp(NameR.data()+16, ".128", 4))		if (memcmp(NameR.data()+8, ".p", 2))
	break;		break;
	return Intrinsic::x86_ssse3_psign_b_128; // "86.ssse		switch (NameR[10]) {
	3.psign.b.128"		default: break;
	case 'd': // 1 string to match.		case 'e': // 3 strings to match.
	if (memcmp(NameR.data()+16, ".128", 4))		if (memcmp(NameR.data()+11, "xtr", 3))
			break;
			switch (NameR[14]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_sse41_pextrb; // "86.sse4
			1.pextrb"
			case 'd': // 1 string to match.
			return Intrinsic::x86_sse41_pextrd; // "86.sse4
			1.pextrd"
			case 'q': // 1 string to match.
			return Intrinsic::x86_sse41_pextrq; // "86.sse4
			1.pextrq"
			}
	break;		break;
	return Intrinsic::x86_ssse3_psign_d_128; // "86.ssse		case 'm': // 9 strings to match.
	3.psign.d.128"		switch (NameR[11]) {
	case 'w': // 1 string to match.		default: break;
	if (memcmp(NameR.data()+16, ".128", 4))		case 'a': // 4 strings to match.
			if (NameR[12] != 'x')
			break;
			switch (NameR[13]) {
			default: break;
			case 's': // 2 strings to match.
			switch (NameR[14]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_sse41_pmaxsb; // "86.sse4
			1.pmaxsb"
			case 'd': // 1 string to match.
			return Intrinsic::x86_sse41_pmaxsd; // "86.sse4
			1.pmaxsd"
			}
			break;
			case 'u': // 2 strings to match.
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_sse41_pmaxud; // "86.sse4
			1.pmaxud"
			case 'w': // 1 string to match.
			return Intrinsic::x86_sse41_pmaxuw; // "86.sse4
			1.pmaxuw"
			}
			break;
			}
			break;
			case 'i': // 4 strings to match.
			if (NameR[12] != 'n')
			break;
			switch (NameR[13]) {
			default: break;
			case 's': // 2 strings to match.
			switch (NameR[14]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_sse41_pminsb; // "86.sse4
			1.pminsb"
			case 'd': // 1 string to match.
			return Intrinsic::x86_sse41_pminsd; // "86.sse4
			1.pminsd"
			}
			break;
			case 'u': // 2 strings to match.
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_sse41_pminud; // "86.sse4
			1.pminud"
			case 'w': // 1 string to match.
			return Intrinsic::x86_sse41_pminuw; // "86.sse4
			1.pminuw"
			}
			break;
			}
			break;
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+12, "ldq", 3))
			break;
			return Intrinsic::x86_sse41_pmuldq; // "86.sse4
			1.pmuldq"
			}
	break;		break;
	return Intrinsic::x86_ssse3_psign_w_128; // "86.ssse		case 't': // 2 strings to match.
	3.psign.w.128"		if (memcmp(NameR.data()+11, "est", 3))
			break;
			switch (NameR[14]) {
			default: break;
			case 'c': // 1 string to match.
			return Intrinsic::x86_sse41_ptestc; // "86.sse4
			1.ptestc"
			case 'z': // 1 string to match.
			return Intrinsic::x86_sse41_ptestz; // "86.sse4
			1.ptestz"
			}
			break;
			}
			break;
			case 'a': // 1 string to match.
			if (memcmp(NameR.data()+8, ".extrqi", 7))
			break;
			return Intrinsic::x86_sse4a_extrqi; // "86.sse4a.extrqi
			"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 's': // 3 strings to match.
	break;		if (memcmp(NameR.data()+6, "e3.pabs.", 8))
	}
	break;
	}
	break;
	case 21: // 16 strings to match.
	if (memcmp(NameR.data()+0, "86.", 3))
	break;
	switch (NameR[3]) {
	default: break;
	case 'a': // 4 strings to match.
	if (memcmp(NameR.data()+4, "vx.cvt", 6))
	break;
	switch (NameR[10]) {
	default: break;
	case '.': // 2 strings to match.
	if (NameR[11] != 'p')
	break;
	switch (NameR[12]) {
	default: break;
	case 'd': // 1 string to match.
	if (memcmp(NameR.data()+13, "2.ps.256", 8))
	break;
	return Intrinsic::x86_avx_cvt_pd2_ps_256; // "86.avx.cvt.pd2.
	ps.256"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+13, "2.pd.256", 8))
	break;		break;
	return Intrinsic::x86_avx_cvt_ps2_pd_256; // "86.avx.cvt.ps2.		switch (NameR[14]) {
	pd.256"		default: break;
	}		case 'b': // 1 string to match.
	break;		return Intrinsic::x86_ssse3_pabs_b; // "86.ssse3.pabs.b
	case 't': // 2 strings to match.		"
	if (memcmp(NameR.data()+11, ".p", 2))		case 'd': // 1 string to match.
			return Intrinsic::x86_ssse3_pabs_d; // "86.ssse3.pabs.d
			"
			case 'w': // 1 string to match.
			return Intrinsic::x86_ssse3_pabs_w; // "86.ssse3.pabs.w
			"
			}
	break;		break;
	switch (NameR[13]) {
	default: break;
	case 'd': // 1 string to match.
	if (memcmp(NameR.data()+14, "2dq.256", 7))
	break;
	return Intrinsic::x86_avx_cvtt_pd2dq_256; // "86.avx.cvtt.pd2
	dq.256"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+14, "2dq.256", 7))
	break;
	return Intrinsic::x86_avx_cvtt_ps2dq_256; // "86.avx.cvtt.ps2
	dq.256"
	}		}
	break;		break;
	}		case 'x': // 16 strings to match.
	break;		if (memcmp(NameR.data()+4, "op.v", 4))
	case 'f': // 4 strings to match.
	if (memcmp(NameR.data()+4, "ma.vfnm", 7))
	break;
	switch (NameR[11]) {
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(NameR.data()+12, "dd.p", 4))
	break;		break;
	switch (NameR[16]) {		switch (NameR[8]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'f': // 4 strings to match.
	if (memcmp(NameR.data()+17, ".256", 4))		if (memcmp(NameR.data()+9, "rcz.", 4))
	break;
	return Intrinsic::x86_fma_vfnmadd_pd_256; // "86.fma.vfnmadd.
	pd.256"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+17, ".256", 4))
	break;		break;
	return Intrinsic::x86_fma_vfnmadd_ps_256; // "86.fma.vfnmadd.		switch (NameR[13]) {
	ps.256"		default: break;
	}		case 'p': // 2 strings to match.
	break;		switch (NameR[14]) {
	case 's': // 2 strings to match.		default: break;
	if (memcmp(NameR.data()+12, "ub.p", 4))		case 'd': // 1 string to match.
	break;		return Intrinsic::x86_xop_vfrcz_pd; // "86.xop.vfrcz.pd
	switch (NameR[16]) {		"
	default: break;		case 's': // 1 string to match.
	case 'd': // 1 string to match.		return Intrinsic::x86_xop_vfrcz_ps; // "86.xop.vfrcz.ps
	if (memcmp(NameR.data()+17, ".256", 4))		"
			}
	break;		break;
	return Intrinsic::x86_fma_vfnmsub_pd_256; // "86.fma.vfnmsub.		case 's': // 2 strings to match.
	pd.256"		switch (NameR[14]) {
	case 's': // 1 string to match.		default: break;
	if (memcmp(NameR.data()+17, ".256", 4))		case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vfrcz_sd; // "86.xop.vfrcz.sd
			"
			case 's': // 1 string to match.
			return Intrinsic::x86_xop_vfrcz_ss; // "86.xop.vfrcz.ss
			"
			}
	break;		break;
	return Intrinsic::x86_fma_vfnmsub_ps_256; // "86.fma.vfnmsub.		}
	ps.256"
	}
	break;
	}
	break;
	case 's': // 6 strings to match.
	if (NameR[4] != 's')
	break;
	switch (NameR[5]) {
	default: break;
	case 'e': // 4 strings to match.
	if (memcmp(NameR.data()+6, "42.pcmp", 7))
	break;		break;
	switch (NameR[13]) {		case 'p': // 12 strings to match.
	default: break;		switch (NameR[9]) {
	case 'e': // 2 strings to match.
	if (memcmp(NameR.data()+14, "str", 3))
	break;
	switch (NameR[17]) {
	default: break;		default: break;
	case 'i': // 1 string to match.		case 'h': // 9 strings to match.
	if (memcmp(NameR.data()+18, "128", 3))		switch (NameR[10]) {
			default: break;
			case 'a': // 6 strings to match.
			if (memcmp(NameR.data()+11, "dd", 2))
			break;
			switch (NameR[13]) {
			default: break;
			case 'b': // 3 strings to match.
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vphaddbd; // "86.xop.
			vphaddbd"
			case 'q': // 1 string to match.
			return Intrinsic::x86_xop_vphaddbq; // "86.xop.
			vphaddbq"
			case 'w': // 1 string to match.
			return Intrinsic::x86_xop_vphaddbw; // "86.xop.
			vphaddbw"
			}
			break;
			case 'd': // 1 string to match.
			if (NameR[14] != 'q')
			break;
			return Intrinsic::x86_xop_vphadddq; // "86.xop.vphadddq
			"
			case 'w': // 2 strings to match.
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vphaddwd; // "86.xop.
			vphaddwd"
			case 'q': // 1 string to match.
			return Intrinsic::x86_xop_vphaddwq; // "86.xop.
			vphaddwq"
			}
			break;
			}
	break;		break;
	return Intrinsic::x86_sse42_pcmpestri128; // "86.sse4		case 's': // 3 strings to match.
	2.pcmpestri128"		if (memcmp(NameR.data()+11, "ub", 2))
	case 'm': // 1 string to match.		break;
	if (memcmp(NameR.data()+18, "128", 3))		switch (NameR[13]) {
			default: break;
			case 'b': // 1 string to match.
			if (NameR[14] != 'w')
			break;
			return Intrinsic::x86_xop_vphsubbw; // "86.xop.vphsubbw
			"
			case 'd': // 1 string to match.
			if (NameR[14] != 'q')
			break;
			return Intrinsic::x86_xop_vphsubdq; // "86.xop.vphsubdq
			"
			case 'w': // 1 string to match.
			if (NameR[14] != 'd')
			break;
			return Intrinsic::x86_xop_vphsubwd; // "86.xop.vphsubwd
			"
			}
	break;		break;
	return Intrinsic::x86_sse42_pcmpestrm128; // "86.sse4		}
	2.pcmpestrm128"
	}
	break;
	case 'i': // 2 strings to match.
	if (memcmp(NameR.data()+14, "str", 3))
	break;		break;
	switch (NameR[17]) {		case 'm': // 3 strings to match.
	default: break;		if (memcmp(NameR.data()+10, "acs", 3))
	case 'i': // 1 string to match.
	if (memcmp(NameR.data()+18, "128", 3))
	break;		break;
	return Intrinsic::x86_sse42_pcmpistri128; // "86.sse4		switch (NameR[13]) {
	2.pcmpistri128"		default: break;
	case 'm': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+18, "128", 3))		if (NameR[14] != 'd')
			break;
			return Intrinsic::x86_xop_vpmacsdd; // "86.xop.vpmacsdd
			"
			case 'w': // 2 strings to match.
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vpmacswd; // "86.xop.vpmacswd
			"
			case 'w': // 1 string to match.
			return Intrinsic::x86_xop_vpmacsww; // "86.xop.vpmacsww
			"
			}
	break;		break;
	return Intrinsic::x86_sse42_pcmpistrm128; // "86.sse4		}
	2.pcmpistrm128"		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 's': // 2 strings to match.
	if (memcmp(NameR.data()+6, "e3.ph", 5))
	break;
	switch (NameR[11]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(NameR.data()+12, "dd.sw.128", 9))
	break;
	return Intrinsic::x86_ssse3_phadd_sw_128; // "86.ssse3.phadd.
	sw.128"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+12, "ub.sw.128", 9))
	break;
	return Intrinsic::x86_ssse3_phsub_sw_128; // "86.ssse3.phsub.
	sw.128"
	}
	break;
	}		}
	break;		break;
	case 'x': // 2 strings to match.		case 'c': // 1 string to match.
	if (memcmp(NameR.data()+4, "op.vpermil2p", 12))		if (memcmp(NameR.data()+1, "ore.checkevent", 14))
	break;		break;
	switch (NameR[16]) {		return Intrinsic::xcore_checkevent; // "core.checkevent"
	default: break;
	case 'd': // 1 string to match.
	if (memcmp(NameR.data()+17, ".256", 4))
	break;
	return Intrinsic::x86_xop_vpermil2pd_256; // "86.xop.vpermil2
	pd.256"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+17, ".256", 4))
	break;
	return Intrinsic::x86_xop_vpermil2ps_256; // "86.xop.vpermil2
	ps.256"
	}
	break;
	}		}
	break;		break;
	case 22: // 21 strings to match.		case 16: // 113 strings to match.
	if (memcmp(NameR.data()+0, "86.", 3))		if (memcmp(NameR.data()+0, "86.", 3))
	break;		break;
	switch (NameR[3]) {		switch (NameR[3]) {
	default: break;		default: break;
	case 'a': // 11 strings to match.		case '3': // 8 strings to match.
	if (memcmp(NameR.data()+4, "vx", 2))		if (memcmp(NameR.data()+4, "dnow", 4))
	break;		break;
	switch (NameR[6]) {		switch (NameR[8]) {
	default: break;		default: break;
	case '.': // 4 strings to match.		case '.': // 6 strings to match.
	switch (NameR[7]) {		if (NameR[9] != 'p')
	default: break;
	case 'm': // 2 strings to match.
	if (memcmp(NameR.data()+8, "askload.p", 9))
	break;
	switch (NameR[17]) {
	default: break;
	case 'd': // 1 string to match.
	if (memcmp(NameR.data()+18, ".256", 4))
	break;
	return Intrinsic::x86_avx_maskload_pd_256; // "86.avx.
	maskload.pd.256"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+18, ".256", 4))
	break;
	return Intrinsic::x86_avx_maskload_ps_256; // "86.avx.
	maskload.ps.256"
	}
	break;
	case 'v': // 2 strings to match.
	if (memcmp(NameR.data()+8, "testnzc.p", 9))
	break;
	switch (NameR[17]) {
	default: break;
	case 'd': // 1 string to match.
	if (memcmp(NameR.data()+18, ".256", 4))
	break;
	return Intrinsic::x86_avx_vtestnzc_pd_256; // "86.avx.
	vtestnzc.pd.256"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+18, ".256", 4))
	break;
	return Intrinsic::x86_avx_vtestnzc_ps_256; // "86.avx.
	vtestnzc.ps.256"
	}
	break;
	}
	break;
	case '2': // 7 strings to match.
	if (NameR[7] != '.')
	break;		break;
	switch (NameR[8]) {		switch (NameR[10]) {
	default: break;		default: break;
	case 'g': // 4 strings to match.		case 'a': // 1 string to match.
	if (memcmp(NameR.data()+9, "ather.", 6))		if (memcmp(NameR.data()+11, "vgusb", 5))
	break;		break;
	switch (NameR[15]) {		return Intrinsic::x86_3dnow_pavgusb; // "86.3dnow.pavgus
			b"
			case 'f': // 4 strings to match.
			switch (NameR[11]) {
	default: break;		default: break;
	case 'd': // 2 strings to match.		case 'c': // 3 strings to match.
	if (NameR[16] != '.')		if (memcmp(NameR.data()+12, "mp", 2))
	break;		break;
	switch (NameR[17]) {		switch (NameR[14]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'e': // 1 string to match.
	if (memcmp(NameR.data()+18, ".256", 4))		if (NameR[15] != 'q')
	break;
	return Intrinsic::x86_avx2_gather_d_d_256; // "86.avx2
	.gather.d.d.256"
	case 'q': // 1 string to match.
	if (memcmp(NameR.data()+18, ".256", 4))
	break;		break;
	return Intrinsic::x86_avx2_gather_d_q_256; // "86.avx2		return Intrinsic::x86_3dnow_pfcmpeq; // "86.3dnow.pfcmpe
	.gather.d.q.256"		q"
	}		case 'g': // 2 strings to match.
	break;		switch (NameR[15]) {
	case 'q': // 2 strings to match.		default: break;
	if (NameR[16] != '.')		case 'e': // 1 string to match.
			return Intrinsic::x86_3dnow_pfcmpge; // "86.3dnow.pfcmpg
			e"
			case 't': // 1 string to match.
			return Intrinsic::x86_3dnow_pfcmpgt; // "86.3dnow.pfcmpg
			t"
			}
	break;		break;
	switch (NameR[17]) {
	default: break;
	case 'd': // 1 string to match.
	if (memcmp(NameR.data()+18, ".256", 4))
	break;
	return Intrinsic::x86_avx2_gather_q_d_256; // "86.avx2
	.gather.q.d.256"
	case 'q': // 1 string to match.
	if (memcmp(NameR.data()+18, ".256", 4))
	break;
	return Intrinsic::x86_avx2_gather_q_q_256; // "86.avx2
	.gather.q.q.256"
	}		}
	break;		break;
	}		case 'r': // 1 string to match.
	break;		if (memcmp(NameR.data()+12, "sqrt", 4))
	case 'm': // 2 strings to match.
	if (memcmp(NameR.data()+9, "askload.", 8))
	break;
	switch (NameR[17]) {
	default: break;
	case 'd': // 1 string to match.
	if (memcmp(NameR.data()+18, ".256", 4))
	break;
	return Intrinsic::x86_avx2_maskload_d_256; // "86.avx2
	.maskload.d.256"
	case 'q': // 1 string to match.
	if (memcmp(NameR.data()+18, ".256", 4))
	break;		break;
	return Intrinsic::x86_avx2_maskload_q_256; // "86.avx2 .maskload.q.256"		return Intrinsic::x86_3dnow_pfrsqrt; // "86.3dnow.pfrsqr t"
	}		}
	break;		break;
	case 'v': // 1 string to match.		case 'm': // 1 string to match.
	if (memcmp(NameR.data()+9, "broadcasti128", 13))		if (memcmp(NameR.data()+11, "ulhrw", 5))
	break;
	return Intrinsic::x86_avx2_vbroadcasti128; // "86.avx2.vbroadc
	asti128"
	}
	break;
	}
	break;
	case 's': // 10 strings to match.
	if (memcmp(NameR.data()+4, "se42.pcmp", 9))
	break;
	switch (NameR[13]) {
	default: break;
	case 'e': // 5 strings to match.
	if (memcmp(NameR.data()+14, "stri", 4))
	break;
	switch (NameR[18]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(NameR.data()+19, "128", 3))
	break;
	return Intrinsic::x86_sse42_pcmpestria128; // "86.sse42.pcmpes
	tria128"
	case 'c': // 1 string to match.
	if (memcmp(NameR.data()+19, "128", 3))
	break;
	return Intrinsic::x86_sse42_pcmpestric128; // "86.sse42.pcmpes
	tric128"
	case 'o': // 1 string to match.
	if (memcmp(NameR.data()+19, "128", 3))
	break;
	return Intrinsic::x86_sse42_pcmpestrio128; // "86.sse42.pcmpes
	trio128"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+19, "128", 3))
	break;
	return Intrinsic::x86_sse42_pcmpestris128; // "86.sse42.pcmpes
	tris128"
	case 'z': // 1 string to match.
	if (memcmp(NameR.data()+19, "128", 3))
	break;		break;
	return Intrinsic::x86_sse42_pcmpestriz128; // "86.sse42.pcmpes triz128"		return Intrinsic::x86_3dnow_pmulhrw; // "86.3dnow.pmulhr w"
	}		}
	break;		break;
	case 'i': // 5 strings to match.		case 'a': // 2 strings to match.
	if (memcmp(NameR.data()+14, "stri", 4))		if (memcmp(NameR.data()+9, ".p", 2))
	break;		break;
	switch (NameR[18]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'f': // 1 string to match.
	if (memcmp(NameR.data()+19, "128", 3))		if (memcmp(NameR.data()+12, "nacc", 4))
	break;
	return Intrinsic::x86_sse42_pcmpistria128; // "86.sse42.pcmpis
	tria128"
	case 'c': // 1 string to match.
	if (memcmp(NameR.data()+19, "128", 3))
	break;
	return Intrinsic::x86_sse42_pcmpistric128; // "86.sse42.pcmpis
	tric128"
	case 'o': // 1 string to match.
	if (memcmp(NameR.data()+19, "128", 3))
	break;		break;
	return Intrinsic::x86_sse42_pcmpistrio128; // "86.sse42.pcmpis trio128"		return Intrinsic::x86_3dnowa_pfnacc; // "86.3dnowa.pfnac c"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(NameR.data()+19, "128", 3))		if (memcmp(NameR.data()+12, "wapd", 4))
	break;
	return Intrinsic::x86_sse42_pcmpistris128; // "86.sse42.pcmpis
	tris128"
	case 'z': // 1 string to match.
	if (memcmp(NameR.data()+19, "128", 3))
	break;		break;
	return Intrinsic::x86_sse42_pcmpistriz128; // "86.sse42.pcmpis triz128"		return Intrinsic::x86_3dnowa_pswapd; // "86.3dnowa.pswap d"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'a': // 34 strings to match.
	break;
	case 23: // 21 strings to match.
	if (memcmp(NameR.data()+0, "86.", 3))
	break;
	switch (NameR[3]) {
	default: break;
	case 'a': // 16 strings to match.
	if (memcmp(NameR.data()+4, "vx", 2))		if (memcmp(NameR.data()+4, "vx", 2))
	break;		break;
	switch (NameR[6]) {		switch (NameR[6]) {
	default: break;		default: break;
	case '.': // 2 strings to match.		case '.': // 5 strings to match.
	if (memcmp(NameR.data()+7, "maskstore.p", 11))		switch (NameR[7]) {
	break;
	switch (NameR[18]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+19, ".256", 4))		if (memcmp(NameR.data()+8, "p.ps.256", 8))
	break;
	return Intrinsic::x86_avx_maskstore_pd_256; // "86.avx.
	maskstore.pd.256"
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+19, ".256", 4))
	break;		break;
	return Intrinsic::x86_avx_maskstore_ps_256; // "86.avx.		return Intrinsic::x86_avx_dp_ps_256; // "86.avx.dp.ps.25
	maskstore.ps.256"		6"
	}		case 'v': // 4 strings to match.
	break;		if (memcmp(NameR.data()+8, "test", 4))
	case '2': // 14 strings to match.
	if (NameR[7] != '.')
	break;
	switch (NameR[8]) {
	default: break;
	case 'g': // 4 strings to match.
	if (memcmp(NameR.data()+9, "ather.", 6))
	break;		break;
	switch (NameR[15]) {		switch (NameR[12]) {
	default: break;		default: break;
	case 'd': // 2 strings to match.		case 'c': // 2 strings to match.
	if (memcmp(NameR.data()+16, ".p", 2))		if (memcmp(NameR.data()+13, ".p", 2))
	break;		break;
	switch (NameR[18]) {		switch (NameR[15]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+19, ".256", 4))		return Intrinsic::x86_avx_vtestc_pd; // "86.avx.vtestc.p
	break;		d"
	return Intrinsic::x86_avx2_gather_d_pd_256; // "86.avx2
	.gather.d.pd.256"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(NameR.data()+19, ".256", 4))		return Intrinsic::x86_avx_vtestc_ps; // "86.avx.vtestc.p
	break;		s"
	return Intrinsic::x86_avx2_gather_d_ps_256; // "86.avx2
	.gather.d.ps.256"
	}		}
	break;		break;
	case 'q': // 2 strings to match.		case 'z': // 2 strings to match.
	if (memcmp(NameR.data()+16, ".p", 2))		if (memcmp(NameR.data()+13, ".p", 2))
	break;		break;
	switch (NameR[18]) {		switch (NameR[15]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+19, ".256", 4))		return Intrinsic::x86_avx_vtestz_pd; // "86.avx.vtestz.p
	break;		d"
	return Intrinsic::x86_avx2_gather_q_pd_256; // "86.avx2
	.gather.q.pd.256"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(NameR.data()+19, ".256", 4))		return Intrinsic::x86_avx_vtestz_ps; // "86.avx.vtestz.p
	break;		s"
	return Intrinsic::x86_avx2_gather_q_ps_256; // "86.avx2
	.gather.q.ps.256"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'm': // 2 strings to match.		}
	if (memcmp(NameR.data()+9, "askstore.", 9))		break;
	break;		case '2': // 28 strings to match.
	switch (NameR[18]) {		if (NameR[7] != '.')
	default: break;
	case 'd': // 1 string to match.
	if (memcmp(NameR.data()+19, ".256", 4))
	break;
	return Intrinsic::x86_avx2_maskstore_d_256; // "86.avx2
	.maskstore.d.256"
	case 'q': // 1 string to match.
	if (memcmp(NameR.data()+19, ".256", 4))
	break;
	return Intrinsic::x86_avx2_maskstore_q_256; // "86.avx2
	.maskstore.q.256"
	}
	break;		break;
	case 'p': // 8 strings to match.		switch (NameR[8]) {
	if (memcmp(NameR.data()+9, "broadcast", 9))		default: break;
			case 'm': // 1 string to match.
			if (memcmp(NameR.data()+9, "ovntdqa", 7))
	break;		break;
	switch (NameR[18]) {		return Intrinsic::x86_avx2_movntdqa; // "86.avx2.movntdq
			a"
			case 'p': // 27 strings to match.
			switch (NameR[9]) {
	default: break;		default: break;
	case 'b': // 2 strings to match.		case 'a': // 6 strings to match.
	if (NameR[19] != '.')		switch (NameR[10]) {
	break;
	switch (NameR[20]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case 'c': // 4 strings to match.
	if (memcmp(NameR.data()+21, "28", 2))		if (NameR[11] != 'k')
	break;		break;
	return Intrinsic::x86_avx2_pbroadcastb_128; // "86.avx2		switch (NameR[12]) {
	.pbroadcastb.128"		default: break;
	case '2': // 1 string to match.		case 's': // 2 strings to match.
	if (memcmp(NameR.data()+21, "56", 2))		if (NameR[13] != 's')
			break;
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			if (NameR[15] != 'w')
			break;
			return Intrinsic::x86_avx2_packssdw; // "86.avx2
			.packssdw"
			case 'w': // 1 string to match.
			if (NameR[15] != 'b')
			break;
			return Intrinsic::x86_avx2_packsswb; // "86.avx2
			.packsswb"
			}
	break;		break;
	return Intrinsic::x86_avx2_pbroadcastb_256; // "86.avx2		case 'u': // 2 strings to match.
	.pbroadcastb.256"		if (NameR[13] != 's')
	}		break;
	break;		switch (NameR[14]) {
	case 'd': // 2 strings to match.		default: break;
	if (NameR[19] != '.')		case 'd': // 1 string to match.
	break;		if (NameR[15] != 'w')
	switch (NameR[20]) {		break;
	default: break;		return Intrinsic::x86_avx2_packusdw; // "86.avx2
	case '1': // 1 string to match.		.packusdw"
	if (memcmp(NameR.data()+21, "28", 2))		case 'w': // 1 string to match.
			if (NameR[15] != 'b')
			break;
			return Intrinsic::x86_avx2_packuswb; // "86.avx2
			.packuswb"
			}
	break;		break;
	return Intrinsic::x86_avx2_pbroadcastd_128; // "86.avx2		}
	.pbroadcastd.128"		break;
	case '2': // 1 string to match.		case 'd': // 2 strings to match.
	if (memcmp(NameR.data()+21, "56", 2))		if (memcmp(NameR.data()+11, "dus.", 4))
	break;		break;
	return Intrinsic::x86_avx2_pbroadcastd_256; // "86.avx2		switch (NameR[15]) {
	.pbroadcastd.256"		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_avx2_paddus_b; // "86.avx2.paddus.
			b"
			case 'w': // 1 string to match.
			return Intrinsic::x86_avx2_paddus_w; // "86.avx2.paddus.
			w"
			}
			break;
	}		}
	break;		break;
	case 'q': // 2 strings to match.		case 'b': // 1 string to match.
	if (NameR[19] != '.')		if (memcmp(NameR.data()+10, "lendvb", 6))
	break;		break;
	switch (NameR[20]) {		return Intrinsic::x86_avx2_pblendvb; // "86.avx2.pblendv
			b"
			case 'h': // 2 strings to match.
			switch (NameR[10]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(NameR.data()+21, "28", 2))		if (memcmp(NameR.data()+11, "dd.sw", 5))
	break;		break;
	return Intrinsic::x86_avx2_pbroadcastq_128; // "86.avx2		return Intrinsic::x86_avx2_phadd_sw; // "86.avx2.phadd.s
	.pbroadcastq.128"		w"
	case '2': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(NameR.data()+21, "56", 2))		if (memcmp(NameR.data()+11, "ub.sw", 5))
	break;		break;
	return Intrinsic::x86_avx2_pbroadcastq_256; // "86.avx2 .pbroadcastq.256"		return Intrinsic::x86_avx2_phsub_sw; // "86.avx2.phsub.s w"
	}		}
	break;		break;
	case 'w': // 2 strings to match.		case 'm': // 16 strings to match.
	if (NameR[19] != '.')		switch (NameR[10]) {
	break;
	switch (NameR[20]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(NameR.data()+21, "28", 2))		if (memcmp(NameR.data()+11, "dd.wd", 5))
	break;		break;
	return Intrinsic::x86_avx2_pbroadcastw_128; // "86.avx2		return Intrinsic::x86_avx2_pmadd_wd; // "86.avx2.pmadd.w
	.pbroadcastw.128"		d"
	case '2': // 1 string to match.		case 'o': // 13 strings to match.
	if (memcmp(NameR.data()+21, "56", 2))		if (NameR[11] != 'v')
	break;		break;
	return Intrinsic::x86_avx2_pbroadcastw_256; // "86.avx2		switch (NameR[12]) {
	.pbroadcastw.256"		default: break;
	}		case 'm': // 1 string to match.
	break;		if (memcmp(NameR.data()+13, "skb", 3))
	}		break;
	break;		return Intrinsic::x86_avx2_pmovmskb; // "86.avx2.pmovmsk
	}		b"
	break;		case 's': // 6 strings to match.
	}		if (NameR[13] != 'x')
	break;		break;
	case 'f': // 4 strings to match.		switch (NameR[14]) {
	if (memcmp(NameR.data()+4, "ma.vfm", 6))		default: break;
			case 'b': // 3 strings to match.
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx2_pmovsxbd; // "86.avx2
			.pmovsxbd"
			case 'q': // 1 string to match.
			return Intrinsic::x86_avx2_pmovsxbq; // "86.avx2
			.pmovsxbq"
			case 'w': // 1 string to match.
			return Intrinsic::x86_avx2_pmovsxbw; // "86.avx2
			.pmovsxbw"
			}
			break;
			case 'd': // 1 string to match.
			if (NameR[15] != 'q')
			break;
			return Intrinsic::x86_avx2_pmovsxdq; // "86.avx2
			.pmovsxdq"
			case 'w': // 2 strings to match.
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx2_pmovsxwd; // "86.avx2
			.pmovsxwd"
			case 'q': // 1 string to match.
			return Intrinsic::x86_avx2_pmovsxwq; // "86.avx2
			.pmovsxwq"
			}
			break;
			}
			break;
			case 'z': // 6 strings to match.
			if (NameR[13] != 'x')
			break;
			switch (NameR[14]) {
			default: break;
			case 'b': // 3 strings to match.
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx2_pmovzxbd; // "86.avx2
			.pmovzxbd"
			case 'q': // 1 string to match.
			return Intrinsic::x86_avx2_pmovzxbq; // "86.avx2
			.pmovzxbq"
			case 'w': // 1 string to match.
			return Intrinsic::x86_avx2_pmovzxbw; // "86.avx2
			.pmovzxbw"
			}
			break;
			case 'd': // 1 string to match.
			if (NameR[15] != 'q')
			break;
			return Intrinsic::x86_avx2_pmovzxdq; // "86.avx2
			.pmovzxdq"
			case 'w': // 2 strings to match.
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx2_pmovzxwd; // "86.avx2
			.pmovzxwd"
			case 'q': // 1 string to match.
			return Intrinsic::x86_avx2_pmovzxwq; // "86.avx2
			.pmovzxwq"
			}
			break;
			}
			break;
			}
			break;
			case 'u': // 2 strings to match.
			if (NameR[11] != 'l')
			break;
			switch (NameR[12]) {
			default: break;
			case 'h': // 1 string to match.
			if (memcmp(NameR.data()+13, "u.w", 3))
			break;
			return Intrinsic::x86_avx2_pmulhu_w; // "86.avx2.pmulhu.
			w"
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+13, ".dq", 3))
			break;
			return Intrinsic::x86_avx2_pmulu_dq; // "86.avx2.pmulu.d
			q"
			}
			break;
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(NameR.data()+10, "ubus.", 5))
			break;
			switch (NameR[15]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_avx2_psubus_b; // "86.avx2.psubus.
			b"
			case 'w': // 1 string to match.
			return Intrinsic::x86_avx2_psubus_w; // "86.avx2.psubus.
			w"
			}
			break;
			}
			break;
			}
			break;
			case '5': // 1 string to match.
			if (memcmp(NameR.data()+7, "12.and.pi", 9))
			break;
			return Intrinsic::x86_avx512_and_pi; // "86.avx512.and.pi"
			}
			break;
			case 'f': // 8 strings to match.
			if (memcmp(NameR.data()+4, "ma.vfm", 6))
	break;		break;
	switch (NameR[10]) {		switch (NameR[10]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'a': // 4 strings to match.
	if (memcmp(NameR.data()+11, "ddsub.p", 7))		if (memcmp(NameR.data()+11, "dd.", 3))
	break;		break;
	switch (NameR[18]) {		switch (NameR[14]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'p': // 2 strings to match.
	if (memcmp(NameR.data()+19, ".256", 4))		switch (NameR[15]) {
	break;		default: break;
	return Intrinsic::x86_fma_vfmaddsub_pd_256; // "86.fma.		case 'd': // 1 string to match.
	vfmaddsub.pd.256"		return Intrinsic::x86_fma_vfmadd_pd; // "86.fma.vfmadd.p
	case 's': // 1 string to match.		d"
	if (memcmp(NameR.data()+19, ".256", 4))		case 's': // 1 string to match.
	break;		return Intrinsic::x86_fma_vfmadd_ps; // "86.fma.vfmadd.p
	return Intrinsic::x86_fma_vfmaddsub_ps_256; // "86.fma.		s"
	vfmaddsub.ps.256"		}
			break;
			case 's': // 2 strings to match.
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_fma_vfmadd_sd; // "86.fma.vfmadd.s
			d"
			case 's': // 1 string to match.
			return Intrinsic::x86_fma_vfmadd_ss; // "86.fma.vfmadd.s
			s"
			}
			break;
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 's': // 4 strings to match.
	if (memcmp(NameR.data()+11, "ubadd.p", 7))		if (memcmp(NameR.data()+11, "ub.", 3))
	break;		break;
	switch (NameR[18]) {		switch (NameR[14]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'p': // 2 strings to match.
	if (memcmp(NameR.data()+19, ".256", 4))		switch (NameR[15]) {
	break;		default: break;
	return Intrinsic::x86_fma_vfmsubadd_pd_256; // "86.fma.		case 'd': // 1 string to match.
	vfmsubadd.pd.256"		return Intrinsic::x86_fma_vfmsub_pd; // "86.fma.vfmsub.p
	case 's': // 1 string to match.		d"
	if (memcmp(NameR.data()+19, ".256", 4))		case 's': // 1 string to match.
	break;		return Intrinsic::x86_fma_vfmsub_ps; // "86.fma.vfmsub.p
	return Intrinsic::x86_fma_vfmsubadd_ps_256; // "86.fma.		s"
	vfmsubadd.ps.256"		}
			break;
			case 's': // 2 strings to match.
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_fma_vfmsub_sd; // "86.fma.vfmsub.s
			d"
			case 's': // 1 string to match.
			return Intrinsic::x86_fma_vfmsub_ss; // "86.fma.vfmsub.s
			s"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 's': // 1 string to match.		case 'm': // 7 strings to match.
	if (memcmp(NameR.data()+4, "sse3.pmul.hr.sw.128", 19))		if (memcmp(NameR.data()+4, "mx.p", 4))
	break;		break;
	return Intrinsic::x86_ssse3_pmul_hr_sw_128; // "86.ssse3.pmul.h		switch (NameR[8]) {
	r.sw.128"
	}
	break;
	case 24: // 10 strings to match.
	if (memcmp(NameR.data()+0, "86.", 3))
	break;
	switch (NameR[3]) {
	default: break;
	case 'a': // 9 strings to match.
	switch (NameR[4]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(NameR.data()+5, "sni.aeskeygenassist", 19))		if (memcmp(NameR.data()+9, "lignr.b", 7))
	break;		break;
	return Intrinsic::x86_aesni_aeskeygenassist; // "86.aesni.aeskey		return Intrinsic::x86_mmx_palignr_b; // "86.mmx.palignr.b"
	genassist"		case 'u': // 6 strings to match.
	case 'v': // 8 strings to match.		if (memcmp(NameR.data()+9, "npck", 4))
	if (NameR[5] != 'x')
	break;		break;
	switch (NameR[6]) {		switch (NameR[13]) {
	default: break;		default: break;
	case '.': // 7 strings to match.		case 'h': // 3 strings to match.
	if (NameR[7] != 'v')		switch (NameR[14]) {
	break;
	switch (NameR[8]) {
	default: break;		default: break;
	case 'b': // 2 strings to match.		case 'b': // 1 string to match.
	if (memcmp(NameR.data()+9, "roadcast.s", 10))		if (NameR[15] != 'w')
	break;		break;
	switch (NameR[19]) {		return Intrinsic::x86_mmx_punpckhbw; // "86.mmx.punpckhb
			w"
			case 'd': // 1 string to match.
			if (NameR[15] != 'q')
			break;
			return Intrinsic::x86_mmx_punpckhdq; // "86.mmx.punpckhd
			q"
			case 'w': // 1 string to match.
			if (NameR[15] != 'd')
			break;
			return Intrinsic::x86_mmx_punpckhwd; // "86.mmx.punpckhw
			d"
			}
			break;
			case 'l': // 3 strings to match.
			switch (NameR[14]) {
			default: break;
			case 'b': // 1 string to match.
			if (NameR[15] != 'w')
			break;
			return Intrinsic::x86_mmx_punpcklbw; // "86.mmx.punpcklb
			w"
			case 'd': // 1 string to match.
			if (NameR[15] != 'q')
			break;
			return Intrinsic::x86_mmx_punpckldq; // "86.mmx.punpckld
			q"
			case 'w': // 1 string to match.
			if (NameR[15] != 'd')
			break;
			return Intrinsic::x86_mmx_punpcklwd; // "86.mmx.punpcklw
			d"
			}
			break;
			}
			break;
			}
			break;
			case 's': // 40 strings to match.
			if (NameR[4] != 's')
			break;
			switch (NameR[5]) {
			default: break;
			case 'e': // 32 strings to match.
			switch (NameR[6]) {
			default: break;
			case '.': // 10 strings to match.
			switch (NameR[7]) {
			default: break;
			case 'c': // 8 strings to match.
			switch (NameR[8]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'o': // 5 strings to match.
	if (memcmp(NameR.data()+20, ".256", 4))		if (memcmp(NameR.data()+9, "mi", 2))
	break;		break;
	return Intrinsic::x86_avx_vbroadcast_sd_256; // "86.avx.		switch (NameR[11]) {
	vbroadcast.sd.256"		default: break;
	case 's': // 1 string to match.		case 'e': // 1 string to match.
	if (memcmp(NameR.data()+20, ".256", 4))		if (memcmp(NameR.data()+12, "q.ss", 4))
			break;
			return Intrinsic::x86_sse_comieq_ss; // "86.sse.comieq.s
			s"
			case 'g': // 2 strings to match.
			switch (NameR[12]) {
			default: break;
			case 'e': // 1 string to match.
			if (memcmp(NameR.data()+13, ".ss", 3))
			break;
			return Intrinsic::x86_sse_comige_ss; // "86.sse.
			comige.ss"
			case 't': // 1 string to match.
			if (memcmp(NameR.data()+13, ".ss", 3))
			break;
			return Intrinsic::x86_sse_comigt_ss; // "86.sse.
			comigt.ss"
			}
	break;		break;
	return Intrinsic::x86_avx_vbroadcast_ss_256; // "86.avx.		case 'l': // 2 strings to match.
	vbroadcast.ss.256"		switch (NameR[12]) {
	}		default: break;
	break;		case 'e': // 1 string to match.
	case 'p': // 5 strings to match.		if (memcmp(NameR.data()+13, ".ss", 3))
	if (memcmp(NameR.data()+9, "erm", 3))		break;
			return Intrinsic::x86_sse_comile_ss; // "86.sse.
			comile.ss"
			case 't': // 1 string to match.
			if (memcmp(NameR.data()+13, ".ss", 3))
			break;
			return Intrinsic::x86_sse_comilt_ss; // "86.sse.
			comilt.ss"
			}
			break;
			}
	break;		break;
	switch (NameR[12]) {		case 'v': // 3 strings to match.
	default: break;		if (memcmp(NameR.data()+9, "tt", 2))
	case '2': // 3 strings to match.
	if (memcmp(NameR.data()+13, "f128.", 5))
	break;		break;
	switch (NameR[18]) {		switch (NameR[11]) {
	default: break;		default: break;
	case 'p': // 2 strings to match.		case 'p': // 2 strings to match.
	switch (NameR[19]) {		switch (NameR[12]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+20, ".256", 4))		if (memcmp(NameR.data()+13, "2pi", 3))
	break;		break;
	return Intrinsic::x86_avx_vperm2f128_pd_256; // "86.avx.vperm2f128.pd.256"		return Intrinsic::x86_sse_cvttpd2pi; // "86.sse. cvttpd2pi"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(NameR.data()+20, ".256", 4))		if (memcmp(NameR.data()+13, "2pi", 3))
	break;		break;
	return Intrinsic::x86_avx_vperm2f128_ps_256; // "86.avx.vperm2f128.ps.256"		return Intrinsic::x86_sse_cvttps2pi; // "86.sse. cvttps2pi"
	}		}
	break;		break;
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(NameR.data()+19, "i.256", 5))		if (memcmp(NameR.data()+12, "s2si", 4))
	break;		break;
	return Intrinsic::x86_avx_vperm2f128_si_256; // "86.avx. vperm2f128.si.256"		return Intrinsic::x86_sse_cvttss2si; // "86.sse.cvttss2s i"
	}		}
	break;		break;
	case 'i': // 2 strings to match.		}
	if (memcmp(NameR.data()+13, "lvar.p", 6))		break;
			case 'm': // 1 string to match.
			if (memcmp(NameR.data()+8, "ovmsk.ps", 8))
			break;
			return Intrinsic::x86_sse_movmsk_ps; // "86.sse.movmsk.p
			s"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+8, "toreu.ps", 8))
			break;
			return Intrinsic::x86_sse_storeu_ps; // "86.sse.storeu.p
			s"
			}
			break;
			case '2': // 17 strings to match.
			if (NameR[7] != '.')
			break;
			switch (NameR[8]) {
			default: break;
			case 'c': // 10 strings to match.
			if (memcmp(NameR.data()+9, "vt", 2))
			break;
			switch (NameR[11]) {
			default: break;
			case 'd': // 2 strings to match.
			if (memcmp(NameR.data()+12, "q2p", 3))
	break;		break;
	switch (NameR[19]) {		switch (NameR[15]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(NameR.data()+20, ".256", 4))		return Intrinsic::x86_sse2_cvtdq2pd; // "86.sse2.cvtdq2p
			d"
			case 's': // 1 string to match.
			return Intrinsic::x86_sse2_cvtdq2ps; // "86.sse2.cvtdq2p
			s"
			}
			break;
			case 'p': // 4 strings to match.
			switch (NameR[12]) {
			default: break;
			case 'd': // 2 strings to match.
			if (NameR[13] != '2')
	break;		break;
	return Intrinsic::x86_avx_vpermilvar_pd_256; // "86.avx.		switch (NameR[14]) {
	vpermilvar.pd.256"		default: break;
			case 'd': // 1 string to match.
			if (NameR[15] != 'q')
			break;
			return Intrinsic::x86_sse2_cvtpd2dq; // "86.sse2
			.cvtpd2dq"
			case 'p': // 1 string to match.
			if (NameR[15] != 's')
			break;
			return Intrinsic::x86_sse2_cvtpd2ps; // "86.sse2
			.cvtpd2ps"
			}
			break;
			case 's': // 2 strings to match.
			if (NameR[13] != '2')
			break;
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			if (NameR[15] != 'q')
			break;
			return Intrinsic::x86_sse2_cvtps2dq; // "86.sse2
			.cvtps2dq"
			case 'p': // 1 string to match.
			if (NameR[15] != 'd')
			break;
			return Intrinsic::x86_sse2_cvtps2pd; // "86.sse2
			.cvtps2pd"
			}
			break;
			}
			break;
			case 's': // 4 strings to match.
			switch (NameR[12]) {
			default: break;
			case 'd': // 2 strings to match.
			if (memcmp(NameR.data()+13, "2s", 2))
			break;
			switch (NameR[15]) {
			default: break;
			case 'i': // 1 string to match.
			return Intrinsic::x86_sse2_cvtsd2si; // "86.sse2
			.cvtsd2si"
			case 's': // 1 string to match.
			return Intrinsic::x86_sse2_cvtsd2ss; // "86.sse2
			.cvtsd2ss"
			}
			break;
			case 'i': // 1 string to match.
			if (memcmp(NameR.data()+13, "2sd", 3))
			break;
			return Intrinsic::x86_sse2_cvtsi2sd; // "86.sse2.cvtsi2s
			d"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(NameR.data()+20, ".256", 4))		if (memcmp(NameR.data()+13, "2sd", 3))
	break;		break;
	return Intrinsic::x86_avx_vpermilvar_ps_256; // "86.avx.		return Intrinsic::x86_sse2_cvtss2sd; // "86.sse2.cvtss2s
	vpermilvar.ps.256"		d"
			}
			break;
			}
			break;
			case 'p': // 7 strings to match.
			switch (NameR[9]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(NameR.data()+10, "ddus.", 5))
			break;
			switch (NameR[15]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_sse2_paddus_b; // "86.sse2.paddus.
			b"
			case 'w': // 1 string to match.
			return Intrinsic::x86_sse2_paddus_w; // "86.sse2.paddus.
			w"
			}
			break;
			case 'm': // 3 strings to match.
			switch (NameR[10]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(NameR.data()+11, "dd.wd", 5))
			break;
			return Intrinsic::x86_sse2_pmadd_wd; // "86.sse2.pmadd.w
			d"
			case 'u': // 2 strings to match.
			if (NameR[11] != 'l')
			break;
			switch (NameR[12]) {
			default: break;
			case 'h': // 1 string to match.
			if (memcmp(NameR.data()+13, "u.w", 3))
			break;
			return Intrinsic::x86_sse2_pmulhu_w; // "86.sse2
			.pmulhu.w"
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+13, ".dq", 3))
			break;
			return Intrinsic::x86_sse2_pmulu_dq; // "86.sse2
			.pmulu.dq"
			}
			break;
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(NameR.data()+10, "ubus.", 5))
			break;
			switch (NameR[15]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_sse2_psubus_b; // "86.sse2.psubus.
			b"
			case 'w': // 1 string to match.
			return Intrinsic::x86_sse2_psubus_w; // "86.sse2.psubus.
			w"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case '2': // 1 string to match.		case '4': // 5 strings to match.
	if (memcmp(NameR.data()+7, ".vbroadcast.ss.ps", 17))		switch (NameR[7]) {
			default: break;
			case '1': // 4 strings to match.
			if (NameR[8] != '.')
			break;
			switch (NameR[9]) {
			default: break;
			case 'b': // 2 strings to match.
			if (memcmp(NameR.data()+10, "lendp", 5))
			break;
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_sse41_blendpd; // "86.sse41.blendp
			d"
			case 's': // 1 string to match.
			return Intrinsic::x86_sse41_blendps; // "86.sse41.blendp
			s"
			}
			break;
			case 'm': // 1 string to match.
			if (memcmp(NameR.data()+10, "psadbw", 6))
			break;
			return Intrinsic::x86_sse41_mpsadbw; // "86.sse41.mpsadb
			w"
			case 'p': // 1 string to match.
			if (memcmp(NameR.data()+10, "blendw", 6))
			break;
			return Intrinsic::x86_sse41_pblendw; // "86.sse41.pblend
			w"
			}
	break;		break;
	return Intrinsic::x86_avx2_vbroadcast_ss_ps; // "86.avx2		case 'a': // 1 string to match.
	.vbroadcast.ss.ps"		if (memcmp(NameR.data()+8, ".insertq", 8))
			break;
			return Intrinsic::x86_sse4a_insertq; // "86.sse4a.insert
			q"
			}
			break;
	}		}
	break;		break;
	}		case 's': // 8 strings to match.
	break;		if (memcmp(NameR.data()+6, "e3.p", 4))
	case 's': // 1 string to match.
	if (memcmp(NameR.data()+4, "sse3.pmadd.ub.sw.128", 20))
	break;
	return Intrinsic::x86_ssse3_pmadd_ub_sw_128; // "86.ssse3.pmadd.
	ub.sw.128"
	}
	break;
	case 25: // 3 strings to match.
	if (memcmp(NameR.data()+0, "86.avx.vinsertf128.", 19))
	break;
	switch (NameR[19]) {
	default: break;
	case 'p': // 2 strings to match.
	switch (NameR[20]) {
	default: break;
	case 'd': // 1 string to match.
	if (memcmp(NameR.data()+21, ".256", 4))
	break;		break;
	return Intrinsic::x86_avx_vinsertf128_pd_256; // "86.avx.		switch (NameR[10]) {
	vinsertf128.pd.256"		default: break;
	case 's': // 1 string to match.		case 'h': // 4 strings to match.
	if (memcmp(NameR.data()+21, ".256", 4))		switch (NameR[11]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(NameR.data()+12, "dd.", 3))
			break;
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_ssse3_phadd_d; // "86.ssse3.phadd.
			d"
			case 'w': // 1 string to match.
			return Intrinsic::x86_ssse3_phadd_w; // "86.ssse3.phadd.
			w"
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(NameR.data()+12, "ub.", 3))
			break;
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_ssse3_phsub_d; // "86.ssse3.phsub.
			d"
			case 'w': // 1 string to match.
			return Intrinsic::x86_ssse3_phsub_w; // "86.ssse3.phsub.
			w"
			}
			break;
			}
			break;
			case 's': // 4 strings to match.
			switch (NameR[11]) {
			default: break;
			case 'h': // 1 string to match.
			if (memcmp(NameR.data()+12, "uf.b", 4))
			break;
			return Intrinsic::x86_ssse3_pshuf_b; // "86.ssse3.pshuf.
			b"
			case 'i': // 3 strings to match.
			if (memcmp(NameR.data()+12, "gn.", 3))
			break;
			switch (NameR[15]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_ssse3_psign_b; // "86.ssse3.psign.
			b"
			case 'd': // 1 string to match.
			return Intrinsic::x86_ssse3_psign_d; // "86.ssse3.psign.
			d"
			case 'w': // 1 string to match.
			return Intrinsic::x86_ssse3_psign_w; // "86.ssse3.psign.
			w"
			}
			break;
			}
	break;		break;
	return Intrinsic::x86_avx_vinsertf128_ps_256; // "86.avx.		}
	vinsertf128.ps.256"		break;
	}		}
	break;		break;
	case 's': // 1 string to match.		case 'v': // 4 strings to match.
	if (memcmp(NameR.data()+20, "i.256", 5))		if (memcmp(NameR.data()+4, "cvtp", 4))
	break;		break;
	return Intrinsic::x86_avx_vinsertf128_si_256; // "86.avx.vinsertf		switch (NameR[8]) {
	128.si.256"
	}
	break;
	case 26: // 3 strings to match.
	if (memcmp(NameR.data()+0, "86.avx.vextractf128.", 20))
	break;
	switch (NameR[20]) {
	default: break;
	case 'p': // 2 strings to match.
	switch (NameR[21]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'h': // 2 strings to match.
	if (memcmp(NameR.data()+22, ".256", 4))		if (memcmp(NameR.data()+9, "2ps.", 4))
	break;		break;
	return Intrinsic::x86_avx_vextractf128_pd_256; // "86.avx.		switch (NameR[13]) {
	vextractf128.pd.256"		default: break;
	case 's': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(NameR.data()+22, ".256", 4))		if (memcmp(NameR.data()+14, "28", 2))
			break;
			return Intrinsic::x86_vcvtph2ps_128; // "86.vcvtph2ps.12
			8"
			case '2': // 1 string to match.
			if (memcmp(NameR.data()+14, "56", 2))
			break;
			return Intrinsic::x86_vcvtph2ps_256; // "86.vcvtph2ps.25
			6"
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(NameR.data()+9, "2ph.", 4))
	break;		break;
	return Intrinsic::x86_avx_vextractf128_ps_256; // "86.avx.		switch (NameR[13]) {
	vextractf128.ps.256"		default: break;
			case '1': // 1 string to match.
			if (memcmp(NameR.data()+14, "28", 2))
			break;
			return Intrinsic::x86_vcvtps2ph_128; // "86.vcvtps2ph.12
			8"
			case '2': // 1 string to match.
			if (memcmp(NameR.data()+14, "56", 2))
			break;
			return Intrinsic::x86_vcvtps2ph_256; // "86.vcvtps2ph.25
			6"
			}
			break;
	}		}
	break;		break;
	case 's': // 1 string to match.		case 'x': // 12 strings to match.
	if (memcmp(NameR.data()+21, "i.256", 5))		if (memcmp(NameR.data()+4, "op.vp", 5))
	break;		break;
	return Intrinsic::x86_avx_vextractf128_si_256; // "86.avx.vextract		switch (NameR[9]) {
	f128.si.256"		default: break;
			case 'h': // 6 strings to match.
			if (memcmp(NameR.data()+10, "addu", 4))
			break;
			switch (NameR[14]) {
			default: break;
			case 'b': // 3 strings to match.
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vphaddubd; // "86.xop.vphaddub
			d"
			case 'q': // 1 string to match.
			return Intrinsic::x86_xop_vphaddubq; // "86.xop.vphaddub
			q"
			case 'w': // 1 string to match.
			return Intrinsic::x86_xop_vphaddubw; // "86.xop.vphaddub
			w"
			}
			break;
			case 'd': // 1 string to match.
			if (NameR[15] != 'q')
			break;
			return Intrinsic::x86_xop_vphaddudq; // "86.xop.vphaddud
			q"
			case 'w': // 2 strings to match.
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vphadduwd; // "86.xop.vphadduw
			d"
			case 'q': // 1 string to match.
			return Intrinsic::x86_xop_vphadduwq; // "86.xop.vphadduw
			q"
			}
			break;
			}
			break;
			case 'm': // 6 strings to match.
			if (NameR[10] != 'a')
			break;
			switch (NameR[11]) {
			default: break;
			case 'c': // 5 strings to match.
			if (NameR[12] != 's')
			break;
			switch (NameR[13]) {
			default: break;
			case 'd': // 2 strings to match.
			if (NameR[14] != 'q')
			break;
			switch (NameR[15]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::x86_xop_vpmacsdqh; // "86.xop.vpmacsdq
			h"
			case 'l': // 1 string to match.
			return Intrinsic::x86_xop_vpmacsdql; // "86.xop.vpmacsdq
			l"
			}
			break;
			case 's': // 3 strings to match.
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			if (NameR[15] != 'd')
			break;
			return Intrinsic::x86_xop_vpmacssdd; // "86.xop.vpmacssd
			d"
			case 'w': // 2 strings to match.
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vpmacsswd; // "86.xop.vpmacssw
			d"
			case 'w': // 1 string to match.
			return Intrinsic::x86_xop_vpmacssww; // "86.xop.vpmacssw
			w"
			}
			break;
			}
			break;
			}
			break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+12, "cswd", 4))
			break;
			return Intrinsic::x86_xop_vpmadcswd; // "86.xop.vpmadcsw
			d"
			}
			break;
			}
			break;
	}		}
	break;		break;
	case 28: // 4 strings to match.		case 17: // 95 strings to match.
	if (memcmp(NameR.data()+0, "86.avx", 6))		if (memcmp(NameR.data()+0, "86.", 3))
	break;		break;
	switch (NameR[6]) {		switch (NameR[3]) {
	default: break;		default: break;
	case '.': // 2 strings to match.		case '3': // 4 strings to match.
	if (memcmp(NameR.data()+7, "vbroadcastf128.p", 16))		if (memcmp(NameR.data()+4, "dnow", 4))
	break;		break;
	switch (NameR[23]) {		switch (NameR[8]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case '.': // 3 strings to match.
	if (memcmp(NameR.data()+24, ".256", 4))		if (memcmp(NameR.data()+9, "pfr", 3))
	break;		break;
	return Intrinsic::x86_avx_vbroadcastf128_pd_256; // "86.avx.		switch (NameR[12]) {
	vbroadcastf128.pd.256"		default: break;
	case 's': // 1 string to match.		case 'c': // 2 strings to match.
	if (memcmp(NameR.data()+24, ".256", 4))		if (memcmp(NameR.data()+13, "pit", 3))
			break;
			switch (NameR[16]) {
			default: break;
			case '1': // 1 string to match.
			return Intrinsic::x86_3dnow_pfrcpit1; // "86.3dnow.pfrcpi
			t1"
			case '2': // 1 string to match.
			return Intrinsic::x86_3dnow_pfrcpit2; // "86.3dnow.pfrcpi
			t2"
			}
	break;		break;
	return Intrinsic::x86_avx_vbroadcastf128_ps_256; // "86.avx.		case 's': // 1 string to match.
	vbroadcastf128.ps.256"		if (memcmp(NameR.data()+13, "qit1", 4))
			break;
			return Intrinsic::x86_3dnow_pfrsqit1; // "86.3dnow.pfrsqi
			t1"
			}
			break;
			case 'a': // 1 string to match.
			if (memcmp(NameR.data()+9, ".pfpnacc", 8))
			break;
			return Intrinsic::x86_3dnowa_pfpnacc; // "86.3dnowa.pfpna
			cc"
	}		}
	break;		break;
	case '2': // 2 strings to match.		case 'a': // 23 strings to match.
	if (memcmp(NameR.data()+7, ".vbroadcast.s", 13))		if (memcmp(NameR.data()+4, "vx", 2))
	break;		break;
	switch (NameR[20]) {		switch (NameR[6]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case '.': // 11 strings to match.
	if (memcmp(NameR.data()+21, ".pd.256", 7))		switch (NameR[7]) {
			default: break;
			case 'c': // 2 strings to match.
			if (memcmp(NameR.data()+8, "mp.p", 4))
			break;
			switch (NameR[12]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+13, ".256", 4))
			break;
			return Intrinsic::x86_avx_cmp_pd_256; // "86.avx.cmp.pd.2
			56"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+13, ".256", 4))
			break;
			return Intrinsic::x86_avx_cmp_ps_256; // "86.avx.cmp.ps.2
			56"
			}
	break;		break;
	return Intrinsic::x86_avx2_vbroadcast_sd_pd_256; // "86.avx2		case 'l': // 1 string to match.
	.vbroadcast.sd.pd.256"		if (memcmp(NameR.data()+8, "du.dq.256", 9))
	case 's': // 1 string to match.		break;
	if (memcmp(NameR.data()+21, ".ps.256", 7))		return Intrinsic::x86_avx_ldu_dq_256; // "86.avx.ldu.dq.2
			56"
			case 'm': // 4 strings to match.
			switch (NameR[8]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(NameR.data()+9, "x.p", 3))
			break;
			switch (NameR[12]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+13, ".256", 4))
			break;
			return Intrinsic::x86_avx_max_pd_256; // "86.avx.max.pd.2
			56"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+13, ".256", 4))
			break;
			return Intrinsic::x86_avx_max_ps_256; // "86.avx.max.ps.2
			56"
			}
			break;
			case 'i': // 2 strings to match.
			if (memcmp(NameR.data()+9, "n.p", 3))
			break;
			switch (NameR[12]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+13, ".256", 4))
			break;
			return Intrinsic::x86_avx_min_pd_256; // "86.avx.min.pd.2
			56"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+13, ".256", 4))
			break;
			return Intrinsic::x86_avx_min_ps_256; // "86.avx.min.ps.2
			56"
			}
			break;
			}
	break;		break;
	return Intrinsic::x86_avx2_vbroadcast_ss_ps_256; // "86.avx2		case 'p': // 2 strings to match.
	.vbroadcast.ss.ps.256"		if (memcmp(NameR.data()+8, "test", 4))
			break;
			switch (NameR[12]) {
			default: break;
			case 'c': // 1 string to match.
			if (memcmp(NameR.data()+13, ".256", 4))
			break;
			return Intrinsic::x86_avx_ptestc_256; // "86.avx.ptestc.2
			56"
			case 'z': // 1 string to match.
			if (memcmp(NameR.data()+13, ".256", 4))
			break;
			return Intrinsic::x86_avx_ptestz_256; // "86.avx.ptestz.2
			56"
			}
			break;
			case 'r': // 1 string to match.
			if (memcmp(NameR.data()+8, "cp.ps.256", 9))
			break;
			return Intrinsic::x86_avx_rcp_ps_256; // "86.avx.rcp.ps.2
			56"
			case 'v': // 1 string to match.
			if (memcmp(NameR.data()+8, "zeroupper", 9))
			break;
			return Intrinsic::x86_avx_vzeroupper; // "86.avx.vzeroupp
			er"
			}
			break;
			case '5': // 12 strings to match.
			if (memcmp(NameR.data()+7, "12.", 3))
			break;
			switch (NameR[10]) {
			default: break;
			case 'p': // 10 strings to match.
			switch (NameR[11]) {
			default: break;
			case 'm': // 8 strings to match.
			switch (NameR[12]) {
			default: break;
			case 'a': // 4 strings to match.
			if (NameR[13] != 'x')
			break;
			switch (NameR[14]) {
			default: break;
			case 's': // 2 strings to match.
			if (NameR[15] != '.')
			break;
			switch (NameR[16]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx512_pmaxs_d; // "86.avx5
			12.pmaxs.d"
			case 'q': // 1 string to match.
			return Intrinsic::x86_avx512_pmaxs_q; // "86.avx5
			12.pmaxs.q"
			}
			break;
			case 'u': // 2 strings to match.
			if (NameR[15] != '.')
			break;
			switch (NameR[16]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx512_pmaxu_d; // "86.avx5
			12.pmaxu.d"
			case 'q': // 1 string to match.
			return Intrinsic::x86_avx512_pmaxu_q; // "86.avx5
			12.pmaxu.q"
			}
			break;
			}
			break;
			case 'i': // 4 strings to match.
			if (NameR[13] != 'n')
			break;
			switch (NameR[14]) {
			default: break;
			case 's': // 2 strings to match.
			if (NameR[15] != '.')
			break;
			switch (NameR[16]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx512_pmins_d; // "86.avx5
			12.pmins.d"
			case 'q': // 1 string to match.
			return Intrinsic::x86_avx512_pmins_q; // "86.avx5
			12.pmins.q"
			}
			break;
			case 'u': // 2 strings to match.
			if (NameR[15] != '.')
			break;
			switch (NameR[16]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx512_pminu_d; // "86.avx5
			12.pminu.d"
			case 'q': // 1 string to match.
			return Intrinsic::x86_avx512_pminu_q; // "86.avx5
			12.pminu.q"
			}
			break;
			}
			break;
			}
			break;
			case 's': // 2 strings to match.
			switch (NameR[12]) {
			default: break;
			case 'l': // 1 string to match.
			if (memcmp(NameR.data()+13, "l.dq", 4))
			break;
			return Intrinsic::x86_avx512_psll_dq; // "86.avx512.psll.
			dq"
			case 'r': // 1 string to match.
			if (memcmp(NameR.data()+13, "l.dq", 4))
			break;
			return Intrinsic::x86_avx512_psrl_dq; // "86.avx512.psrl.
			dq"
			}
			break;
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(NameR.data()+11, "qrt.s", 5))
			break;
			switch (NameR[16]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx512_sqrt_sd; // "86.avx512.sqrt.
			sd"
			case 's': // 1 string to match.
			return Intrinsic::x86_avx512_sqrt_ss; // "86.avx512.sqrt.
			ss"
			}
			break;
			}
			break;
	}		}
	break;		break;
	}		case 'f': // 8 strings to match.
	break;		if (memcmp(NameR.data()+4, "ma.vfnm", 7))
	}		break;
	break; // end of 'x' case.		switch (NameR[11]) {
	}		default: break;
	#endif		case 'a': // 4 strings to match.
			if (memcmp(NameR.data()+12, "dd.", 3))
	// Global intrinsic function declaration type table.		break;
	#ifdef GET_INTRINSIC_GENERATOR_GLOBAL		switch (NameR[15]) {
	static const unsigned IIT_Table[] = {		default: break;
	0x2E2E, (1U<<31) | 321, 0x4444440, 0x4444440, 0x4, (1U<<31) | 276, 0x4444		case 'p': // 2 strings to match.
	440,		switch (NameR[16]) {
	0x4444440, 0x444440, 0x444440, 0x444444, 0x444444, 0x2F2F2F, 0x2F2F2F, 0x		default: break;
	2F2F,		case 'd': // 1 string to match.
	0x797949, 0x7A7A4A, 0x797949, 0x7A7A4A, (1U<<31) | 305, 0x2F2F2F2F, 0x2F2		return Intrinsic::x86_fma_vfnmadd_pd; // "86.fma.vfnmadd.
	F, 0x2F2F,		pd"
	0x2F2F, 0x45F0F, 0x45F0F, 0x7A3A, 0x44F1F, 0x44F1F, 0x3A7A, 0x2F2F2F,		case 's': // 1 string to match.
	0x2F2F2F, 0x2F2F2F, 0x2F2F2F, 0x42E2F, (1U<<31) | 365, (1U<<31) | 412, (1		return Intrinsic::x86_fma_vfnmadd_ps; // "86.fma.vfnmadd.
	U<<31) | 354, (1U<<31) | 438,		ps"
	(1U<<31) | 341, (1U<<31) | 470, 0x2F2F2F, 0x2F2F2F, 0x2F2F2F, 0x2F2F2F, (		}
	1U<<31) | 314, (1U<<31) | 314,		break;
	(1U<<31) | 314, 0x2F2F2F, 0x6F2F2F, 0x6F2F2F, 0x2F2F2F, 0x6F2F, 0x6F2F, 0		case 's': // 2 strings to match.
	x2F2F2F,		switch (NameR[16]) {
	0x2F2F2F, 0x2F2F2F, 0x2F2F2F, 0x2F2F, 0x2F2F2F, 0x2F2F2F, (1U<<31) | 312,		default: break;
	(1U<<31) | 312,		case 'd': // 1 string to match.
	0x2F2F2F, (1U<<31) | 314, (1U<<31) | 300, (1U<<31) | 300, (1U<<31) | 300,		return Intrinsic::x86_fma_vfnmadd_sd; // "86.fma.vfnmadd.
	0x2F2F, 0x2F2F2F, (1U<<31) | 305,		sd"
	(1U<<31) | 305, (1U<<31) | 305, 0x2F2F2F, 0x2F2F2F, (1U<<31) | 305, (1U<<		case 's': // 1 string to match.
	31) | 305, (1U<<31) | 305, 0x2F2F2F,		return Intrinsic::x86_fma_vfnmadd_ss; // "86.fma.vfnmadd.
	0x2F2F2F, 0x2F2F2F, 0x2F2F2F, 0x2F2F2F, (1U<<31) | 305, 0x2F2F, 0x2F2F2F,		ss"
	0x2F2F2F,		}
	0x2F2F2F, (1U<<31) | 305, 0x2F2F2F, 0x2F2F2F, 0x2F2F, 0x2F2F2F, (1U<<31)		break;
	| 305, 0x2F2F2F2F,		}
	(1U<<31) | 314, (1U<<31) | 314, (1U<<31) | 305, 0x2F2F2F, 0x2F2F2F, 0x42F		break;
	2E0, 0x42F2F2E0, (1U<<31) | 402,		case 's': // 4 strings to match.
	(1U<<31) | 374, (1U<<31) | 426, (1U<<31) | 385, (1U<<31) | 456, (1U<<31)		if (memcmp(NameR.data()+12, "ub.", 3))
	| 305, 0x2B2B2B, 0x2B2B2B2B, (1U<<31) | 265,		break;
	(1U<<31) | 263, 0x2B2B2B2B, (1U<<31) | 265, (1U<<31) | 263, (1U<<31) | 26		switch (NameR[15]) {
	1, 0x444, 0x444, 0x40,		default: break;
	0x444, 0x2E444, 0x2E, 0x444, 0x1F7, 0x1F7, 0xF0F, 0x1F1F,		case 'p': // 2 strings to match.
	0x37, 0x73, 0x445F1F, 0x444F1F, 0x444F1F, 0x445F0F, 0x444F0F, 0x444F0F,		switch (NameR[16]) {
	0x445F0F, 0x444F0F, 0x444F0F, 0x1F1F, 0x10F0F, 0xF0F, 0x10F0F, 0x0,		default: break;
	(1U<<31) | 573, (1U<<31) | 568, 0x0, 0x0, 0x42E, 0x2E40, 0x2E50, 0x40,		case 'd': // 1 string to match.
	0x2E0, 0x2E0, 0x2E, 0x2E4, 0x2E4, 0x0, 0x1F1F, 0x1F1F,		return Intrinsic::x86_fma_vfnmsub_pd; // "86.fma.vfnmsub.
	0xF0F0F, 0x1F1F, 0x1F1F, 0x4, 0x1F1F1F1F, 0x1F1F1F1F, 0x42E, 0x2EE2E2E,		pd"
	0x2E2EE0, 0x2EE2E2E0, 0x44, 0x55, 0x44, 0x444, 0x444, 0x444,		case 's': // 1 string to match.
	0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444,		return Intrinsic::x86_fma_vfnmsub_ps; // "86.fma.vfnmsub.
	0x444, 0x444, 0x444, 0x555, 0x555, 0x444, 0x545, 0x444,		ps"
	0x444, 0x555, 0x44, 0x44, 0x444, 0x444, 0x444, 0x444,		}
	0x445, 0x445, 0x444, 0x555, 0x444, 0x555, 0x444, 0x555,		break;
	0x444, 0x555, 0x44, 0x55, 0x44, 0x44, 0x55, 0x444,		case 's': // 2 strings to match.
	0x444, 0x555, 0x54, 0x54, 0x44, 0x44, 0x44, 0x44,		switch (NameR[16]) {
	0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444,		default: break;
	0x444, 0x444, 0x444, 0x444, 0x444, 0x555, 0x444, 0x444,		case 'd': // 1 string to match.
	0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444,		return Intrinsic::x86_fma_vfnmsub_sd; // "86.fma.vfnmsub.
	0x444, 0x44, 0x44, 0x44, 0x45, 0x44, 0x444, 0x444,		sd"
	0x55, 0x45, 0x44, 0x55, 0x55, 0x55, 0x55, 0x555,		case 's': // 1 string to match.
	0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555,		return Intrinsic::x86_fma_vfnmsub_ss; // "86.fma.vfnmsub.
	0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555,		ss"
	0x555, 0x555, 0x555, 0x551, 0x551, 0x551, 0x551, 0x551,		}
	0x551, 0x551, 0x551, 0x55, 0x555, 0x555, 0x555, 0x555,		break;
	0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555,		}
	0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x5555,		break;
	0x555, 0x5555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555,		}
	0x555, 0x555, 0x444, 0x555, 0x44, 0x44, 0x444, 0x555,		break;
	0x445, 0x445, 0x541, 0x441, 0x441, 0x441, 0x441, 0x441,		case 'i': // 1 string to match.
	0x441, 0x441, 0x441, 0x441, 0x441, 0x441, 0x441, 0x445,		if (memcmp(NameR.data()+4, "nt2mask.v16i1", 13))
	0x445, 0x444, 0x444, 0x444, 0x444, 0x555, 0x444, 0x444,		break;
	0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x451, 0x551,		return Intrinsic::x86_int2mask_v16i1; // "86.int2mask.v16i1"
	0x451, 0x551, 0x451, 0x451, 0x451, 0x451, 0x451, 0x451,		case 'm': // 1 string to match.
	0x451, 0x451, 0x4555, 0x4555, 0x4555, 0x4555, 0x4555, 0x4555,		if (memcmp(NameR.data()+4, "ask2int.v16i1", 13))
	0x4555, 0x4555, 0x554, 0x41, 0x441, 0x441, 0x41, 0x441,		break;
	0x441, 0x441, 0x441, 0x441, 0x551, 0x441, 0x441, 0x441,		return Intrinsic::x86_mask2int_v16i1; // "86.mask2int.v16i1"
	0x441, 0x551, 0x441, 0x441, 0x551, 0x441, 0x441, 0x45,		case 's': // 50 strings to match.
	0x4444, 0x4444, 0x4444, 0x4444, 0x41, 0x441, 0x441, 0x41,		if (NameR[4] != 's')
	0x44, 0x41, 0x444, 0x5545, 0x441, 0x4441, 0x4441, 0x4441,		break;
	0x4441, 0x441, 0x441, 0x441, 0x441, 0x441, 0x441, 0x441,		switch (NameR[5]) {
	0x441, 0x441, 0x441, 0x441, 0x4441, 0x4441, 0x4441, 0x4441,		default: break;
	0x58, 0x57, 0x85, 0x85, 0x87, 0x85, 0x85, 0x84,		case 'e': // 48 strings to match.
	0x84, 0x84, 0x84, 0x75, 0x75, 0x78, 0x75, 0x75,		switch (NameR[6]) {
	0x74, 0x74, 0x74, 0x74, 0x58, 0x57, 0x48, 0x47,		default: break;
	0x48, 0x47, 0x888, 0x481, 0x881, 0x881, 0x881, 0x881,		case '.': // 8 strings to match.
	0x888, 0x888, 0x88, 0x8888, 0x8888, 0x48888, 0x8888, 0x8888,		switch (NameR[7]) {
	0x48, 0x48, 0x888, 0x888, 0x888, 0x888, 0x777, 0x471,		default: break;
	0x771, 0x771, 0x771, 0x771, 0x777, 0x777, 0x77, 0x7777,		case 'c': // 3 strings to match.
	0x7777, 0x47777, 0x7777, 0x7777, 0x47, 0x47, 0x777, 0x777,		switch (NameR[8]) {
	0x777, 0x777, 0x4444, 0x4444, 0x4455, 0x4455, 0x4455, 0x4455,		default: break;
	0x4455, 0x4455, 0x445, 0x445, 0x444, 0x444, 0x444, 0x444,		case 'o': // 1 string to match.
	0x445, 0x445, 0x445, 0x445, 0x4455, 0x4455, 0x4455, 0x4455,		if (memcmp(NameR.data()+9, "mineq.ss", 8))
	0x4455, 0x4455, 0x444, 0x445, 0x4455, 0x4455, 0x445, 0x444,		break;
	0x444, 0x444, 0x444, 0x4444, 0x4444, 0x4444, 0x5555, 0x5555,		return Intrinsic::x86_sse_comineq_ss; // "86.sse.comineq.
	0x5555, 0x5555, 0x5555, 0x5555, 0x5555, 0x5555, 0x5555, 0x5555,		ss"
	0x5555, 0x5555, 0x5555, 0x5555, 0x5555, 0x5555, 0x555, 0x555,		case 'v': // 2 strings to match.
	0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555,		if (memcmp(NameR.data()+9, "ts", 2))
	0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x4444, 0x4444,		break;
	0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444,		switch (NameR[11]) {
	0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x444, 0x444,		default: break;
	0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x4444, 0x4444,		case 'i': // 1 string to match.
	0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444,		if (memcmp(NameR.data()+12, "642ss", 5))
	0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x444, 0x444,		break;
	0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444,		return Intrinsic::x86_sse_cvtsi642ss; // "86.sse.
	0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444,		cvtsi642ss"
	0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444,		case 's': // 1 string to match.
	0x444, 0x4455, 0x4455, 0x4455, 0x4455, 0x4455, 0x4455, 0x4455,		if (memcmp(NameR.data()+12, "2si64", 5))
	0x4455, 0x445, 0x445, 0x445, 0x445, 0x445, 0x445, 0x445,		break;
	0x445, 0x4455, 0x4455, 0x4455, 0x4455, 0x4455, 0x4455, 0x4455,		return Intrinsic::x86_sse_cvtss2si64; // "86.sse.
	0x4455, 0x445, 0x445, 0x445, 0x445, 0x445, 0x445, 0x445,		cvtss2si64"
	0x445, 0x444, 0x444, 0x444, 0x4444, 0x4444, 0x4444, 0x4444,		}
	0x4444, 0x4444, 0x4444, 0x4444, 0x444, 0x444, 0x444, 0x444,		break;
	0x444, 0x444, 0x444, 0x444, 0x4444, 0x4444, 0x4444, 0x4444,		}
	0x4444, 0x4444, 0x4444, 0x4444, 0x444, 0x4455, 0x4455, 0x4455,		break;
	0x4455, 0x4455, 0x4455, 0x4455, 0x4455, 0x445, 0x445, 0x445,		case 'u': // 5 strings to match.
	0x445, 0x445, 0x445, 0x445, 0x445, 0x4455, 0x4455, 0x4455,		if (memcmp(NameR.data()+8, "comi", 4))
	0x4455, 0x4455, 0x4455, 0x4455, 0x4455, 0x444, 0x4444, 0x4444,		break;
	0x4444, 0x555, 0x555, 0x5555, 0x5555, 0x555, 0x555, 0x555,		switch (NameR[12]) {
	0x555, 0x5555, 0x5555, 0x554, 0x554, 0x555, 0x555, 0x4455,		default: break;
	0x5555, 0x5555, 0x5555, 0x4455, 0x4455, 0x4455, 0x4455, 0x555,		case 'e': // 1 string to match.
	0x555, 0x445, 0x444, 0x445, 0x444, 0x445, 0x445, 0x554,		if (memcmp(NameR.data()+13, "q.ss", 4))
	0x554, 0x5555, 0x5555, 0x5555, 0x5555, 0x555, 0x555, 0x555,		break;
	0x555, 0x4555, 0x455, 0x454, 0x5555, 0x555, 0x4444, 0x4444,		return Intrinsic::x86_sse_ucomieq_ss; // "86.sse.ucomieq.
	0x4444, 0x4444, 0x4444, 0x454, 0x454, 0x454, 0x454, 0x4444,		ss"
	0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444,		case 'g': // 2 strings to match.
	0x4444, 0x4444, 0x445, 0x4455, 0x445, 0x4455, 0x5555, 0x5555,		switch (NameR[13]) {
	0x555, 0x555, 0x5555, 0x5555, 0x555, 0x555, 0x4444, 0x4444,		default: break;
	0x4444, 0x5555, 0x5555, 0x555, 0x4455, 0x4455, 0x445, 0x445,		case 'e': // 1 string to match.
	0x5555, 0x5555, 0x555, 0x555, 0x4444, 0x455, 0x4555, 0x4555,		if (memcmp(NameR.data()+14, ".ss", 3))
	0x4555, 0x4555, 0x4555, 0x444, 0x4444, 0x4444, 0x4444, 0x4444,		break;
	0x444, 0x4444, 0x455, 0x455, 0x455, 0x4555, 0x4555, 0x4555,		return Intrinsic::x86_sse_ucomige_ss; // "86.sse.
	0x4555, 0x4555, 0x444, 0x4444, 0x4444, 0x4444, 0x4444, 0x444,		ucomige.ss"
	0x455, 0x455, 0x455, 0x4555, 0x4555, 0x4555, 0x4555, 0x455,		case 't': // 1 string to match.
	0x455, 0x444, 0x4444, 0x4444, 0x4444, 0x4444, 0x444, 0x444,		if (memcmp(NameR.data()+14, ".ss", 3))
	0x454, 0x455, 0x455, 0x455, 0x4555, 0x4555, 0x4555, 0x4555,		break;
	0x4555, 0x444, 0x4444, 0x4444, 0x4444, 0x4444, 0x444, 0x454,		return Intrinsic::x86_sse_ucomigt_ss; // "86.sse.
	0x455, 0x455, 0x44, 0x55, 0x44, 0x54, 0x44, 0x54,		ucomigt.ss"
	0x44, 0x44, 0x54, 0x444, 0x444, 0x44, 0x54, 0x44,		}
	0x54, 0x55, 0x4444, 0x544, 0x4455, 0x555, 0x44444, 0x5444,		break;
	0x44555, 0x5555, 0x55, 0x555, 0x455, 0x4555, 0x4555, 0x4555,		case 'l': // 2 strings to match.
	0x4555, 0x4555, 0x444, 0x4444, 0x4444, 0x4444, 0x4444, 0x455,		switch (NameR[13]) {
	0x455, 0x455, 0x4555, 0x4555, 0x4555, 0x4555, 0x4555, 0x444,		default: break;
	0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x455, 0x455, 0x455,		case 'e': // 1 string to match.
	0x4555, 0x4555, 0x4555, 0x4555, 0x4555, 0x444, 0x4444, 0x4444,		if (memcmp(NameR.data()+14, ".ss", 3))
	0x4444, 0x4444, 0x455, 0x455, 0x445, 0x554, 0x444, 0x444,		break;
	0x555, 0x555, 0x555, 0x555, 0x44, 0x44, 0x44444, 0x44444,		return Intrinsic::x86_sse_ucomile_ss; // "86.sse.
	0x44444, 0x44444, 0x444, 0x444, 0x441, 0x441, 0x4555, 0x4555,		ucomile.ss"
	0x455, 0x455, 0x4555, 0x54, 0x54, 0x54, 0x55, 0x54,		case 't': // 1 string to match.
	0x55, 0x54, 0x55, 0x54, 0x55, 0x44, 0x45, 0x4555,		if (memcmp(NameR.data()+14, ".ss", 3))
	0x4555, 0x45, 0x45, 0x54, 0x555, 0x54, 0x555, 0x45,		break;
	0x45, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x444, 0x454,		return Intrinsic::x86_sse_ucomilt_ss; // "86.sse.
	0x54, 0x4444, 0x544, 0x4455, 0x555, 0x444, 0x441, 0x441,		ucomilt.ss"
	0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x444, 0x4444, 0x4444,		}
	0x4444, 0x4455, 0x44555, 0x555, 0x555, 0x555, 0x555, 0x555,		break;
	0x555, 0x454, 0x454, 0x54, 0x455, 0x44, 0x442E2E2E, 0x2E2E2E0,		}
	(1U<<31) | 282, (1U<<31) | 283, 0x2E50, 0x2E50, 0x1F1F, 0x1F1F, 0x1F1F, 0		break;
	x42E0,		}
	(1U<<31) | 9, (1U<<31) | 9, 0x144F23F0, 0x3939, 0x2A2A, 0x44, 0x393939, 0		break;
	x393939,		case '2': // 12 strings to match.
	0x444, 0x393939, 0x393939, 0x444, 0x444, 0x444, 0x393939, 0x2A2A2A,		if (NameR[7] != '.')
	0x393939, 0x2A2A2A, 0x2A2A2A, 0x2A2A2A, 0x444, 0x4444, 0x4444, 0x44,		break;
	0x4, 0x39390, 0x39390, 0x39390, 0x2A2A4, 0x2A2A4, 0x2A2A4, 0x2A2A4,		switch (NameR[8]) {
	0x2A2A4, 0x2A2A4, 0x2A2A0, 0x2A2A0, 0x2A2A0, 0x393955, 0x393955, 0x4455,		default: break;
	0x393955, 0x393955, 0x2A2A55, 0x2A2A55, 0x393955, 0x393955, 0x393955, 0x4		case 'c': // 8 strings to match.
	455,		switch (NameR[9]) {
	0x393955, 0x393955, 0x2A2A55, 0x2A2A55, 0x393955, 0x454, 0x454, 0x454,		default: break;
	0x454, 0x454, 0x454, 0x444, 0x42E4, 0x42E4, 0x42E4, 0x4455,		case 'o': // 5 strings to match.
	0x4455, 0x393955, 0x393955, 0x393955, 0x393955, 0x444, 0x4455, 0x4455,		if (memcmp(NameR.data()+10, "mi", 2))
	0x455, 0x393939, 0x393939, 0x39394, 0x39394, 0x392A39, 0x392A39, 0x393939		break;
	,		switch (NameR[12]) {
	0x444, 0x393939, 0x444, 0x393955, 0x393955, 0x445, 0x445, 0x393939,		default: break;
	0x393939, 0x2A2A2A, 0x394, 0x394, 0x2A39, 0x2A39, 0x2A39, 0x2A39,		case 'e': // 1 string to match.
	0x2A39, 0x2A39, 0x2A39, 0x2A39, 0x39392A, 0x44439, 0x44439, 0x4439,		if (memcmp(NameR.data()+13, "q.sd", 4))
	0x39392A, 0x4439, 0x39392A, 0x4444, 0x2A4, 0x44, 0x439, 0x42A,		break;
	0x455, 0x43939, 0x42A2A, 0x43939, 0x444, 0x43939, 0x42A2A, 0x43939,		return Intrinsic::x86_sse2_comieq_sd; // "86.sse2
	0x42A2A, 0x444, 0x43939, 0x42A2A, 0x393939, 0x393939, 0x444, 0x393939,		.comieq.sd"
	0x393939, 0x444, 0x444, 0x393939, 0x2A2A2A, 0x393939, 0x2A2A2A, 0x2A2A2A,		case 'g': // 2 strings to match.
	0x2A2A2A, 0x440, 0x1F1F, 0x44, 0x55, 0x888, 0x777, 0x777,		switch (NameR[13]) {
	0x888, 0x777, 0x777, 0x888, 0x777, 0x777, 0x888, 0x777,		default: break;
	0x777, 0x73F7, 0x43F4, 0x43F4, 0x0, 0x44, 0x44, 0x44,		case 'e': // 1 string to match.
	0x85, 0x74, 0x47, 0x58, 0x44, 0x55, 0x88, 0x77,		if (memcmp(NameR.data()+14, ".sd", 3))
	0x77, 0x44, 0x54, 0x3F0, 0x3F0, 0x77, 0x77, 0x87,		break;
	0x87, 0x87, 0x87, 0x87, 0x87, 0x87, 0x87, 0x84,		return Intrinsic::x86_sse2_comige_sd; // "86.sse2
	0x84, 0x84, 0x84, 0x84, 0x84, 0x85, 0x85, 0x85,		.comige.sd"
	0x85, 0x84, 0x84, 0x84, 0x84, 0x85, 0x85, 0x85,		case 't': // 1 string to match.
	0x85, 0x777, 0x777, 0x888, 0x777, 0x777, 0x888, 0x777,		if (memcmp(NameR.data()+14, ".sd", 3))
	0x777, 0x888, 0x777, 0x777, 0x888, 0x777, 0x777, 0x88,		break;
	0x77, 0x77, 0x73, 0x73, 0x74, 0x74, 0x74, 0x74,		return Intrinsic::x86_sse2_comigt_sd; // "86.sse2
	0x74, 0x74, 0x74, 0x74, 0x75, 0x75, 0x75, 0x75,		.comigt.sd"
	0x75, 0x75, 0x75, 0x75, 0x74, 0x74, 0x74, 0x74,		}
	0x74, 0x74, 0x74, 0x74, 0x75, 0x75, 0x75, 0x75,		break;
	0x75, 0x75, 0x75, 0x75, 0x88, 0x77, 0x77, 0x88,		case 'l': // 2 strings to match.
	0x77, 0x77, 0x8888, 0x7777, 0x7777, 0x8888, 0x7777, 0x7777,		switch (NameR[13]) {
	0x8888, 0x7777, 0x7777, 0x8888, 0x7777, 0x7777, 0x888, 0x777,		default: break;
	0x777, 0x888, 0x777, 0x777, 0x37, 0x48, 0x48, 0x48,		case 'e': // 1 string to match.
	0x48, 0x47, 0x47, 0x47, 0x47, 0x1FE1F, 0xFE0F, 0x3FE3F,		if (memcmp(NameR.data()+14, ".sd", 3))
	0x1FE1F, 0xFE0F, 0x3FE3F, 0x88, 0x77, 0x77, 0x58, 0x58,		break;
	0x58, 0x58, 0x57, 0x57, 0x57, 0x57, 0x448, 0x444,		return Intrinsic::x86_sse2_comile_sd; // "86.sse2
	0x555, 0x444, 0x555, 0x0, 0x0, 0x0, 0x444, 0x555,		.comile.sd"
	0x444, 0x555, 0x88, 0x77, 0x33, 0x44, 0x55, 0x22,		case 't': // 1 string to match.
	0x7F3F, 0x444, 0x444, 0x888, 0x777, 0x777, 0x888, 0x777,		if (memcmp(NameR.data()+14, ".sd", 3))
	0x777, 0x888, 0x777, 0x777, 0x888, 0x777, 0x777, 0x444,		break;
	0x555, 0x444, 0x555, 0x44, 0x54, 0x4444, 0x7F3F, 0x7F3F,		return Intrinsic::x86_sse2_comilt_sd; // "86.sse2
	0x7F3F, 0x7F3F, 0x7F3F, 0x7F3F, 0x7F3F, 0x7F3F, 0x7F3F, 0x88,		.comilt.sd"
	0x88, 0x77, 0x77, 0x88, 0x77, 0x77, 0x88, 0x77,		}
	0x77, 0x88, 0x77, 0x77, 0x4, 0x4, 0x4, 0x4,		break;
	0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4,		}
	0x4, 0x88, 0x77, 0x77, 0x88, 0x77, 0x77, 0x4444,		break;
	0x4444, 0x88, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77,		case 'v': // 3 strings to match.
	0x77, 0x88, 0x77, 0x77, 0x88, 0x77, 0x77, 0x88,		if (memcmp(NameR.data()+10, "tt", 2))
	0x77, 0x77, 0x88, 0x77, 0x77, 0x88, 0x77, 0x77,		break;
	0x48, 0x48, 0x48, 0x48, 0x47, 0x47, 0x47, 0x47,		switch (NameR[12]) {
	0x58, 0x58, 0x58, 0x58, 0x57, 0x57, 0x57, 0x57,		default: break;
	0x12E0F, 0x40, 0x1F1F1F, 0x41F1F, 0x40, 0x0, 0x442E0, 0x442E0,		case 'p': // 2 strings to match.
	0x442E0, 0x442E0, 0x2E2C, 0x2E3B, 0x2E4A, 0x2E2C, 0x2E2C, 0x2E4A,		switch (NameR[13]) {
	0x2E4A, 0x3B, 0x4A0, 0x2E2C0, 0x2E3B0, 0x2E4A0, 0x2E4A0, 0x2E4A0,		default: break;
	0x4A4A4A, 0x2C2C2C, 0x3B3B3B, 0x4A4A4A, 0x2C2C2C, 0x3B3B3B, 0x4A4A4A, 0x2		case 'd': // 1 string to match.
	C2C2C,		if (memcmp(NameR.data()+14, "2dq", 3))
	0x3B3B3B, 0x4A4A4A, 0x2C2C2C, 0x3B3B3B, 0x4A4A4A, 0x44A7A, 0x44A7A, 0x7A7		break;
	A4A,		return Intrinsic::x86_sse2_cvttpd2dq; // "86.sse2
	0x7A7A44, 0x7A7A4A, 0x7A7A44, 0x2C2C2C, 0x2C2C44, 0x3B3B3B, 0x3B3B44, 0x4		.cvttpd2dq"
	A4A4A,		case 's': // 1 string to match.
	0x4A4A44, 0x7A7A4A, 0x7A7A44, 0x7A7A4A, 0x7A7A44, 0x2C2C2C, 0x2C2C44, 0x3		if (memcmp(NameR.data()+14, "2dq", 3))
	B3B3B,		break;
	0x3B3B44, 0x4A4A4A, 0x4A4A44, 0x2C2C2C, 0x2C2C44, 0x3B3B3B, 0x3B3B44, 0x4		return Intrinsic::x86_sse2_cvttps2dq; // "86.sse2
	A4A4A,		.cvttps2dq"
	0x4A4A44, 0x47A4A, 0x47A4A, 0x7A7A, 0x7A7A, 0x7A7A7A7A, 0x7A7A7A, 0x2C2C2		}
	C,		break;
	0x3B3B3B, 0x4A4A4A, 0x2C2C2C, 0x3B3B3B, 0x4A4A4A, 0x3B3B3B3B, 0x3B3B3B3B,		case 's': // 1 string to match.
	0x7A7A7A,		if (memcmp(NameR.data()+13, "d2si", 4))
	0x2C2C2C, 0x3B3B3B, 0x4A4A4A, 0x2C2C2C, 0x3B3B3B, 0x4A4A4A, 0x3B3B3B3B, 0		break;
	x4A2C2C4A,		return Intrinsic::x86_sse2_cvttsd2si; // "86.sse2
	0x4A3B3B4A, 0x4A3B3B4A, 0x4A2C2C4A, 0x4A3B3B4A, 0x4A3B3B4A, 0x2C2C3B, 0x3		.cvttsd2si"
	B3B4A, 0x2C2C3B,		}
	0x3B3B4A, 0x2C2C3B, 0x3B3B4A, 0x2C2C3B, 0x3B3B4A, 0x7A7A7A7A, 0x2C4A4A4A,		break;
	0x4A4A3B,		}
	0x3B3B2C, 0x3B3B2C, 0x4A4A2C, 0x4A4A3B, 0x3B3B2C, 0x4A4A3B, 0x7A7A, 0x7A7		break;
	A,		case 'm': // 1 string to match.
	0x7A7A, 0x7A7A, 0x7A7A, 0x2C2C2C, 0x3B3B3B, 0x4A4A4A, 0x7A7A, 0x4A4A4A4A,		if (memcmp(NameR.data()+9, "ovmsk.pd", 8))
	0x4A4A4A, 0x2C2C2C, 0x3B3B3B, 0x4A4A4A, 0x4A4A4A, 0x4A4A4A, 0x2C2C2C, 0x3		break;
	B3B3B,		return Intrinsic::x86_sse2_movmsk_pd; // "86.sse2.movmsk.
	0x4A4A4A, 0x2C2C2C, 0x3B3B3B, 0x4A4A4A, 0x4A4A4A, 0x4A4A4A, 0x2C2C2C, 0x3		pd"
	B3B3B,		case 's': // 3 strings to match.
	0x4A4A4A, 0x2C2C2C, 0x3B3B3B, 0x4A4A4A, 0x4A4A4A, 0x4A2C4A, 0x4A3B4A, 0x4		if (memcmp(NameR.data()+9, "tore", 4))
	A2C4A,		break;
	0x4A4A4A, 0x3B4A, 0x2C3B, 0x3B4A, 0x3B4A, 0x2C3B, 0x3B4A, 0x2E0,		switch (NameR[13]) {
	0x2E0, 0x2E0, 0x2E0, 0x2E0, 0x2E0, 0x2E0, 0x2E0, 0x0,		default: break;
	0x4442E0, (1U<<31) | 331, 0x40, 0x4, 0x5, 0x4, 0x4, 0x4,		case 'l': // 1 string to match.
	0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4,		if (memcmp(NameR.data()+14, ".dq", 3))
	0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4,		break;
	0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4,		return Intrinsic::x86_sse2_storel_dq; // "86.sse2.storel.
	0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4,		dq"
	0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4,		case 'u': // 2 strings to match.
	0x4, 0x4, 0x4, 0x5, 0x42E, 0x1F1F, (1U<<31) | 0, 0x2E4,		if (NameR[14] != '.')
	0x42E0, 0x42E4, 0x1F1F, (1U<<31) | 0, 0x1F1F, (1U<<31) | 0, 0x2EE2E0, 0x2		break;
	E0,		switch (NameR[15]) {
	0x2E, 0x0, 0x1F1F, (1U<<31) | 0, (1U<<31) | 0, (1U<<31) | 0, 0x2E2E0, 0x2		default: break;
	E0,		case 'd': // 1 string to match.
	0x42E2E2E0, 0x2E0, (1U<<31) | 564, (1U<<31) | 561, (1U<<31) | 564, (1U<<3		if (NameR[16] != 'q')
	1) | 564, (1U<<31) | 564, (1U<<31) | 564,		break;
	(1U<<31) | 564, (1U<<31) | 564, (1U<<31) | 564, (1U<<31) | 564, (1U<<31)		return Intrinsic::x86_sse2_storeu_dq; // "86.sse2
	| 561, (1U<<31) | 564, (1U<<31) | 564, (1U<<31) | 564,		.storeu.dq"
	(1U<<31) | 561, (1U<<31) | 564, (1U<<31) | 564, (1U<<31) | 561, (1U<<31)		case 'p': // 1 string to match.
	| 564, (1U<<31) | 561, (1U<<31) | 564, (1U<<31) | 564,		if (NameR[16] != 'd')
	(1U<<31) | 561, (1U<<31) | 561, 0x595959, 0x595959, 0x595959, 0x595959, 0		break;
	x5959, 0x25959,		return Intrinsic::x86_sse2_storeu_pd; // "86.sse2
	(1U<<31) | 29, (1U<<31) | 65, (1U<<31) | 193, (1U<<31) | 227, (1U<<31) |		.storeu.pd"
	125, (1U<<31) | 171, (1U<<31) | 77, (1U<<31) | 101,		}
	(1U<<31) | 41, (1U<<31) | 53, (1U<<31) | 205, (1U<<31) | 239, (1U<<31) |		break;
	137, (1U<<31) | 149, (1U<<31) | 89, (1U<<31) | 113,		}
	0x4A2E4A, 0x4B2E4B, 0x592E59, 0x5A2E5A, 0x4A4A2E0, 0x4B4B2E0, 0x59592E0,		break;
	0x5A5A2E0,		}
	0x2E5A, 0x42D2D3C, 0x2D2D, 0x4B4B, 0x3C3C, 0x4B4B3C, 0x3C3C2D, 0x4B4B3C,		break;
	0x3C3C2D, 0x2D2D2D, 0x3C3C3C, 0x2D2D2D, 0x3C3C3C, 0x2D2D2D, 0x3C3C3C, 0x4		case '3': // 2 strings to match.
	4A4A4A,		if (memcmp(NameR.data()+7, ".addsub.p", 9))
	0x44B4B4B, 0x2D2D2D2D, 0x43C3C3C, 0x2C2C, 0x2C2D, 0x4A4A, 0x4A4B, 0x5959,		break;
	0x595A, 0x3B3B, 0x3B3C, 0x4B4B4B, 0x7B7B7B, 0x4B4B4B, 0x3C3C3C, 0x3C3C3C,		switch (NameR[16]) {
	0x4B4B4B, 0x3C3C3C, 0x3C3C3C, 0x2D2D3C, 0x3C3C4B, 0x2D2D2D, 0x4B4B4B, 0x3		default: break;
	C3C3C,		case 'd': // 1 string to match.
	0x2D2D2D, 0x4B4B4B, 0x3C3C3C, 0x2D2D2D, 0x4B4B4B, 0x3C3C3C, 0x2D2D2D, 0x4		return Intrinsic::x86_sse3_addsub_pd; // "86.sse3.addsub.
	B4B4B,		pd"
	0x3C3C3C, 0x2D4, 0x2C4B, 0x2C5A, 0x2C3C, 0x4A5A, 0x3B4B, 0x3B5A,		case 's': // 1 string to match.
	0x2C4B, 0x2C5A, 0x2C3C, 0x4A5A, 0x3B4B, 0x3B5A, 0x4B4B5A, 0x3C3C3C,		return Intrinsic::x86_sse3_addsub_ps; // "86.sse3.addsub.
	0x3C3C3C, 0x3C3C3C, 0x4B4B5A, 0x2D2D5A, 0x2D2D2D, 0x2D2D2D, 0x4B4B4B, 0x3		ps"
	C3C3C,		}
	0x4A4B4B, 0x45A5A, 0x45A5A, 0x595A5A, 0x3B3C3C, 0x44B4B, 0x45A5A, 0x43C3C		break;
	,		case '4': // 26 strings to match.
	0x4A4A4A, 0x4B4B4B, 0x595959, 0x5A5A5A, 0x4A4B4B, 0x3B3C3C, 0x44B4B, 0x43		switch (NameR[7]) {
	C3C,		default: break;
	0x4A4A4A, 0x4B4B4B, 0x4A4B4B, 0x45A5A, 0x45A5A, 0x595A5A, 0x3B3C3C, 0x44B		case '1': // 23 strings to match.
	4B,		if (NameR[8] != '.')
	0x45A5A, 0x43C3C, 0x4A4A4A, 0x4B4B4B, 0x595959, 0x5A5A5A, 0x2D2D2D, 0x3C3		break;
	C3C,		switch (NameR[9]) {
	0x2D2D2D, 0x3C3C3C, 0x898A, 0x7A7A, 0x7A7B, 0x2E5A, 0x25A59, 0x2595A5A,		default: break;
	0x25A5A5A, 0x8A8A8A, 0x7B7B7B, 0x48A8A8A, 0x47B7B7B, (1U<<31) | 537, 0x7B		case 'b': // 2 strings to match.
	7B7B7B, 0x28A8A8A,		if (memcmp(NameR.data()+10, "lendvp", 6))
	0x27B7B7B, 0x8A7A, 0x8A4A, 0x7A8A, 0x7B4B, 0x4A8A, 0x4B7B, 0x8A4A,		break;
	0x7B4B, 0x47B7B7B, 0x8A8A8A, 0x7B7B7B, 0x8A8A8A, 0x7B7B7B, 0x2E2D, 0x892E		switch (NameR[16]) {
	89,		default: break;
	0x8A2E8A, 0x7A2E7A, 0x7B2E7B, 0x89892E0, 0x8A8A2E0, 0x7A7A2E0, 0x7B7B2E0,		case 'd': // 1 string to match.
	0x8A8A8A,		return Intrinsic::x86_sse41_blendvpd; // "86.sse4
	0x7B7B7B, 0x8A8A8A, 0x7B7B7B, 0x8A4, 0x7B4, 0x5A5A4, 0x5A5A4, 0x5A5A4,		1.blendvpd"
	0x7B7B, 0x48A8A, 0x47B7B, 0x7B7B, 0x8A8A, 0x7B7B, 0x2D2E0, 0x8A2E0,		case 's': // 1 string to match.
	0x7B2E0, 0x2E8A, 0x2E7A, 0x2E7B, 0x2E8A, 0x2E7B, 0x28A89, 0x27B7A,		return Intrinsic::x86_sse41_blendvps; // "86.sse4
	0x24B4A, 0x2898A8A, 0x27A7B7B, 0x24A4B4B, 0x28A8A8A, 0x27B7B7B, 0x24B4B4B		1.blendvps"
	, 0x598989,		}
	0x5A8A8A, 0x4A7A7A, 0x4B7B7B, 0x89894, 0x8A8A4, 0x7A7A4, 0x7B7B4, 0x89894		break;
	,		case 'i': // 1 string to match.
	0x8A8A4, 0x7A7A4, 0x7B7B4, 0x89894, 0x8A8A4, 0x7A7A4, 0x7B7B4, 0x0,		if (memcmp(NameR.data()+10, "nsertps", 7))
	0x0, 0x444, 0x555, 0x444, 0x555, 0x444, 0x555, 0x444,		break;
	0x555, (1U<<31) | 524, (1U<<31) | 537, 0x7A7A7A7A, 0x7B7B7B7B, (1U<<31) |		return Intrinsic::x86_sse41_insertps; // "86.sse41.insert
	524, 0x7A7A7A7A, (1U<<31) | 524,		ps"
	(1U<<31) | 537, 0x7A7A7A7A, 0x7B7B7B7B, (1U<<31) | 524, (1U<<31) | 537, 0		case 'm': // 1 string to match.
	x7A7A7A7A, 0x7B7B7B7B, (1U<<31) | 524,		if (memcmp(NameR.data()+10, "ovntdqa", 7))
	0x7A7A7A7A, (1U<<31) | 524, (1U<<31) | 537, 0x7A7A7A7A, 0x7B7B7B7B, (1U<<		break;
	31) | 524, (1U<<31) | 537, 0x7A7A7A7A,		return Intrinsic::x86_sse41_movntdqa; // "86.sse41.movntd
	0x7B7B7B7B, (1U<<31) | 524, 0x7A7A7A7A, (1U<<31) | 524, (1U<<31) | 537, 0		qa"
	x7A7A7A7A, 0x7B7B7B7B, (1U<<31) | 524,		case 'p': // 15 strings to match.
	0x7A7A7A7A, 0x20, 0x0, 0x0, (1U<<31) | 289, (1U<<31) | 559, (1U<<31) | 56		switch (NameR[10]) {
	4, (1U<<31) | 564,		default: break;
	(1U<<31) | 564, (1U<<31) | 564, (1U<<31) | 564, (1U<<31) | 564, (1U<<31)		case 'a': // 1 string to match.
	| 564, (1U<<31) | 564, (1U<<31) | 564, (1U<<31) | 564,		if (memcmp(NameR.data()+11, "ckusdw", 6))
	(1U<<31) | 564, (1U<<31) | 295, (1U<<31) | 564, (1U<<31) | 564, (1U<<31)		break;
	| 564, (1U<<31) | 564, (1U<<31) | 564, (1U<<31) | 564,		return Intrinsic::x86_sse41_packusdw; // "86.sse4
	(1U<<31) | 564, (1U<<31) | 564, (1U<<31) | 564, (1U<<31) | 564, (1U<<31)		1.packusdw"
	| 512, (1U<<31) | 499, (1U<<31) | 564, (1U<<31) | 564,		case 'b': // 1 string to match.
	(1U<<31) | 564, (1U<<31) | 564, (1U<<31) | 564, (1U<<31) | 546, (1U<<31)		if (memcmp(NameR.data()+11, "lendvb", 6))
	| 564, (1U<<31) | 564, (1U<<31) | 564, (1U<<31) | 564,		break;
	(1U<<31) | 564, (1U<<31) | 564, (1U<<31) | 564, (1U<<31) | 564, (1U<<31)		return Intrinsic::x86_sse41_pblendvb; // "86.sse4
	| 564, (1U<<31) | 516, (1U<<31) | 516, (1U<<31) | 516,		1.pblendvb"
	(1U<<31) | 564, (1U<<31) | 564, (1U<<31) | 516, (1U<<31) | 516, (1U<<31)		case 'm': // 12 strings to match.
	| 564, (1U<<31) | 564, (1U<<31) | 564, (1U<<31) | 516,		if (memcmp(NameR.data()+11, "ov", 2))
	(1U<<31) | 516, (1U<<31) | 516, (1U<<31) | 564, (1U<<31) | 564, (1U<<31)		break;
	| 564, (1U<<31) | 564, (1U<<31) | 564, (1U<<31) | 564,		switch (NameR[13]) {
	(1U<<31) | 564, (1U<<31) | 564, (1U<<31) | 564, (1U<<31) | 564, (1U<<31)		default: break;
	| 564, (1U<<31) | 564, (1U<<31) | 564, (1U<<31) | 564,		case 's': // 6 strings to match.
	(1U<<31) | 564, 0x2595959, 0x4, 0x5, 0x4, 0x5, (1U<<31) | 398, (1U<<31) |		if (NameR[14] != 'x')
	504,		break;
	(1U<<31) | 508, (1U<<31) | 398, (1U<<31) | 504, (1U<<31) | 508, 0x898989,		switch (NameR[15]) {
	0x2E0, 0x2898989, 0x2898989,		default: break;
	0x89894, 0x89894, 0x89894, 0x89894, 0x89894, 0x89894, 0x4A89, 0x4A7A,		case 'b': // 3 strings to match.
	0x894A, 0x897A, 0x7A4A, 0x7A89, 0x894, 0x895, 0x897A7A, 0x48989,		switch (NameR[16]) {
	0x58989, 0x7A8989, 0x894A, 0x7A4A, 0x894, 0x895, 0x898989, 0x0,		default: break;
	0x2E2C2C0, 0x898989, 0x898989, 0x0, 0x898989, 0x898989, 0x894, 0x898989,		case 'd': // 1 string to match.
	0x4A4A3B, 0x3B3B2C, 0x3B3B2C, 0x2C2C2C, 0x3B3B3B, 0x2C2C2C, 0x3B3B3B, 0x2		return Intrinsic::x86_sse41_pmovsxbd; // "86.sse4
	C2C2C,		1.pmovsxbd"
	0x3B3B3B, 0x3B3B4A, 0x3B3B3B, 0x2C2C2C, 0x3B3B3B, 0x2C2C2C, 0x2C4, 0x3B3B		case 'q': // 1 string to match.
	3B,		return Intrinsic::x86_sse41_pmovsxbq; // "86.sse4
	0x3B3B3B, 0x4A4A59, 0x2C2C59, 0x4A4A4A, 0x45959, 0x45959, 0x595959, 0x3B3		1.pmovsxbq"
	B3B,		case 'w': // 1 string to match.
	0x44A4A, 0x45959, 0x43B3B, 0x4A4A4A, 0x3B3B3B, 0x44A4A, 0x43B3B, 0x4A4A4A		return Intrinsic::x86_sse41_pmovsxbw; // "86.sse4
	,		1.pmovsxbw"
	0x45959, 0x45959, 0x595959, 0x3B3B3B, 0x44A4A, 0x45959, 0x43B3B, 0x2C2C2C		}
	,		break;
	0x3B3B3B, 0x2C2C2C, 0x3B3B3B, 0x8989, 0x8989, 0x4A2E0, 0x2C2E0, 0x892E0,		case 'd': // 1 string to match.
	0x898989, 0x89894, 0x89894, 0x89894, 0x89894, 0x89894, 0x89894, 0x898989,		if (NameR[16] != 'q')
	0x7A7A7A, 0x898989, 0x7A7A7A, 0x898989, 0x7A7A7A, 0x2E2C, 0x442E0, 0x440,		break;
	0x4898989, 0x47A7A7A, (1U<<31) | 524, 0x7A7A7A7A, 0x4898989, 0x47A7A7A, 0		return Intrinsic::x86_sse41_pmovsxdq; // "86.sse4
	x47A4, 0x47A7A7A,		1.pmovsxdq"
	0x2E59, 0x42C2C3B, 0x4A4A3B, 0x2C2C2C2C, 0x43B3B3B, 0x42C4, 0x44A4, 0x459		case 'w': // 2 strings to match.
	5,		switch (NameR[16]) {
	0x3B3B, 0x2C2C2C, 0x4A4A4A, 0x4A4A4A, 0x3B3B3B, 0x2C2C2C, 0x4A4A4A, 0x4A4		default: break;
	A4A,		case 'd': // 1 string to match.
	0x3B3B3B, 0x2C4A, 0x2C59, 0x2C3B, 0x4A59, 0x3B4A, 0x3B59, 0x2C4A,		return Intrinsic::x86_sse41_pmovsxwd; // "86.sse4
	0x2C59, 0x2C3B, 0x4A59, 0x3B4A, 0x3B59, 0x4A4A59, 0x59594, 0x59594,		1.pmovsxwd"
	0x59594, 0x48989, 0x47A7A, 0x4898989, 0x47A7A7A, 0x344, 0x444, 0x244,		case 'q': // 1 string to match.
	0x555, 0x255, 0x242C42C4, 0x242C42C4, 0x242C42C4, 0x242C42C4, 0x242C42C4,		return Intrinsic::x86_sse41_pmovsxwq; // "86.sse4
	0x242C42C4,		1.pmovsxwq"
	(1U<<31) | 19, 0x22C2C4, 0x22C2C4, 0x22C2C4, 0x22C2C4, 0x22C2C4, 0x22C2C4		}
	, 0x22C2C2C,		break;
	0x2C5959, 0x225959, 0x595959, 0x22595959, 0x892E0, 0x7A2E0, 0x7A7A7A, 0x2		}
	7A7A7A,		break;
	0x27A7A7A, 0x7A7A4, 0x7A7A4, 0x7A7A4, 0x7A7A4, 0x7A7A4, 0x7A7A4, (1U<<31)		case 'z': // 6 strings to match.
	| 533,		if (NameR[14] != 'x')
	(1U<<31) | 555, (1U<<31) | 549, (1U<<31) | 520, 0x47A7A, 0x57A7A, 0x7A4,		break;
	0x7A5, (1U<<31) | 533,		switch (NameR[15]) {
	(1U<<31) | 520, 0x7A4, 0x7A5, 0x7A7A7A, 0x2E0, 0x7A7A7A, 0x7A7A7A, 0x7A7A		default: break;
	7A,		case 'b': // 3 strings to match.
	0x7A7A7A, 0x7A4, 0x7A7A7A, (1U<<31) | 296, 0x7A7A, 0x7A7A, 0x7A7A, 0x7A7A		switch (NameR[16]) {
	,		default: break;
	0x0, 0x7A7A, 0x7A7A, 0x2E0, 0x7A2E0, 0x7A7A7A, 0x7A7A4, 0x7A7A4,		case 'd': // 1 string to match.
	0x7A7A4, 0x7A7A4, 0x7A7A4, 0x7A7A4, (1U<<31) | 561, 0x2C2C, (1U<<31) | 56		return Intrinsic::x86_sse41_pmovzxbd; // "86.sse4
	1, 0x4A4A,		1.pmovzxbd"
	(1U<<31) | 561, 0x3B3B, (1U<<31) | 564, 0x4A4A4A, (1U<<31) | 564, 0x3B3B3		case 'q': // 1 string to match.
	B, (1U<<31) | 564, 0x3B3B3B,		return Intrinsic::x86_sse41_pmovzxbq; // "86.sse4
	(1U<<31) | 564, 0x4A4A4A, (1U<<31) | 564, 0x3B3B3B, (1U<<31) | 564, 0x3B3		1.pmovzxbq"
	B3B, (1U<<31) | 564, 0x2C2C3B,		case 'w': // 1 string to match.
	(1U<<31) | 564, 0x3B3B3B, (1U<<31) | 564, 0x2C2C2C, (1U<<31) | 564, 0x2C2		return Intrinsic::x86_sse41_pmovzxbw; // "86.sse4
	C2C, (1U<<31) | 564, 0x4A4A4A,		1.pmovzxbw"
	(1U<<31) | 564, 0x3B3B3B, 0x3B7A, 0x3B7B, 0x47A3B, 0x47B3B, 0x40, 0x50,		}
	0x40, 0x50, 0x20, 0x4, 0x0, 0x8989, 0x8A8A, 0x7A7A,		break;
	0x7B7B, 0x8989, 0x7A7A, 0x59595959, 0x5A5A5A5A, 0x22C2C2C, 0x24A4A4A, 0x2		case 'd': // 1 string to match.
	595959,		if (NameR[16] != 'q')
	0x22C2C2C, 0x24A4A4A, 0x2595959, 0x23B3B3B, 0x23B3B3B, (1U<<31) | 217, (1		break;
	U<<31) | 251, (1U<<31) | 161,		return Intrinsic::x86_sse41_pmovzxdq; // "86.sse4
	(1U<<31) | 183, 0x2C4A, 0x2C59, 0x2C3B, 0x4A59, 0x2C4A, 0x2C59, 0x2C3B,		1.pmovzxdq"
	0x4A59, 0x3B4A, 0x3B59, 0x3B4A, 0x3B59, 0x2C3B, 0x4A59, 0x3B4A,		case 'w': // 2 strings to match.
	0x4A4A4A4A, 0x594A4A59, 0x594A4A59, 0x4A4A4A4A, 0x594A4A59, 0x594A4A59, 0		switch (NameR[16]) {
	x4A3B3B4A, 0x3B3B3B3B,		default: break;
	0x4A3B3B4A, 0x3B3B3B3B, 0x4A3B3B4A, 0x4A3B3B4A, 0x2C2C2C2C, 0x2C2C2C, 0x2		case 'd': // 1 string to match.
	2C2C, 0x4A4A4A,		return Intrinsic::x86_sse41_pmovzxwd; // "86.sse4
	0x24A4A, 0x595959, 0x25959, 0x3B3B3B, 0x23B3B, 0x2C2C2C, 0x4A4A4A, 0x5959		1.pmovzxwd"
	59,		case 'q': // 1 string to match.
	0x3B3B3B, 0x2C2C2C, 0x4A4A4A, 0x595959, 0x3B3B3B, 0x4, 0x44, 0x2E2E,		return Intrinsic::x86_sse41_pmovzxwq; // "86.sse4
	0x43F0, 0x0, 0x40, 0x4444, (1U<<31) | 492, 0x3F0, 0x3F4, 0x3F0,		1.pmovzxwq"
	0x4, 0x4, 0x4, 0x44, 0x43F, 0x7F3F, 0x3F4, 0x3F4,		}
	0x3F4, 0x2E3F0, 0x2E3F0, 0x2E3F0, 0x2E3F0, 0x2E3F0, 0x43F4, 0x3F4,		break;
	0x3F0, 0x3F0, 0x43F0, 0x43F0, 0x43F4, 0x43F0, 0x3F4, 0x43F0,		}
	0x7F3F0, 0x43F0, 0x2E3F0, 0x440, 0x43F0, 0x43F0, 0x7F3F0, 0x40,		break;
	0x43F0, 0x2E3F0, 0x444, 0x0, 0x3F0, 0x3F4, 0x3F4, 0x2E,		}
	0x444, 0		break;
	};		case 't': // 1 string to match.
			if (memcmp(NameR.data()+11, "estnzc", 6))
	static const unsigned char IIT_LongEncodingTable[] = {		break;
	/* 0 */ 19, 15, 0, 1, 15, 0, 15, 0, 0,		return Intrinsic::x86_sse41_ptestnzc; // "86.sse4
	/* 9 */ 0, 15, 3, 15, 7, 15, 8, 4, 1, 0,		1.ptestnzc"
	/* 19 */ 12, 2, 12, 2, 4, 12, 2, 4, 2, 0,		}
	/* 29 */ 10, 4, 10, 4, 14, 2, 10, 4, 10, 4, 2, 0,		break;
	/* 41 */ 10, 4, 10, 4, 14, 2, 9, 5, 10, 4, 2, 0,		case 'r': // 4 strings to match.
	/* 53 */ 10, 4, 10, 4, 14, 2, 10, 5, 10, 4, 2, 0,		if (memcmp(NameR.data()+10, "ound.", 5))
	/* 65 */ 11, 4, 11, 4, 14, 2, 11, 4, 11, 4, 2, 0,		break;
	/* 77 */ 9, 5, 9, 5, 14, 2, 10, 4, 9, 5, 2, 0,		switch (NameR[15]) {
	/* 89 */ 9, 5, 9, 5, 14, 2, 9, 5, 9, 5, 2, 0,		default: break;
	/* 101 */ 10, 5, 10, 5, 14, 2, 10, 4, 10, 5, 2, 0,		case 'p': // 2 strings to match.
	/* 113 */ 10, 5, 10, 5, 14, 2, 10, 5, 10, 5, 2, 0,		switch (NameR[16]) {
	/* 125 */ 10, 7, 10, 7, 14, 2, 10, 4, 10, 7, 2, 0,		default: break;
	/* 137 */ 10, 7, 10, 7, 14, 2, 9, 5, 10, 7, 2, 0,		case 'd': // 1 string to match.
	/* 149 */ 10, 7, 10, 7, 14, 2, 10, 5, 10, 7, 2, 0,		return Intrinsic::x86_sse41_round_pd; // "86.sse4
	/* 161 */ 10, 7, 10, 7, 10, 7, 10, 7, 2, 0,		1.round.pd"
	/* 171 */ 11, 7, 11, 7, 14, 2, 11, 4, 11, 7, 2, 0,		case 's': // 1 string to match.
	/* 183 */ 11, 7, 11, 7, 11, 7, 11, 7, 2, 0,		return Intrinsic::x86_sse41_round_ps; // "86.sse4
	/* 193 */ 9, 8, 9, 8, 14, 2, 10, 4, 9, 8, 2, 0,		1.round.ps"
	/* 205 */ 9, 8, 9, 8, 14, 2, 9, 5, 9, 8, 2, 0,		}
	/* 217 */ 9, 8, 9, 8, 9, 8, 9, 8, 2, 0,		break;
	/* 227 */ 10, 8, 10, 8, 14, 2, 10, 4, 10, 8, 2, 0,		case 's': // 2 strings to match.
	/* 239 */ 10, 8, 10, 8, 14, 2, 10, 5, 10, 8, 2, 0,		switch (NameR[16]) {
	/* 251 */ 10, 8, 10, 8, 10, 8, 10, 8, 2, 0,		default: break;
	/* 261 */ 11, 2, 11, 2, 11, 2, 11, 2, 11, 2, 11, 2, 11, 2, 0,		case 'd': // 1 string to match.
	/* 276 */ 19, 4, 4, 14, 2, 0,		return Intrinsic::x86_sse41_round_sd; // "86.sse4
	/* 282 */ 0, 14, 18, 5, 14, 2, 0,		1.round.sd"
	/* 289 */ 0, 16, 16, 14, 2, 0,		case 's': // 1 string to match.
	/* 295 */ 16, 16, 16, 2, 0,		return Intrinsic::x86_sse41_round_ss; // "86.sse4
	/* 300 */ 15, 2, 23, 2, 0,		1.round.ss"
	/* 305 */ 15, 2, 23, 2, 23, 2, 0,		}
	/* 312 */ 15, 2, 15, 2, 24, 2, 24, 2, 0,		break;
	/* 321 */ 15, 0, 15, 0, 14, 2, 14, 2, 4, 0,		}
	/* 331 */ 15, 3, 15, 3, 14, 2, 14, 2, 4, 0,		break;
	/* 341 */ 21, 15, 2, 15, 2, 15, 2, 15, 2, 14, 2, 4, 0,		}
	/* 354 */ 20, 15, 2, 15, 2, 15, 2, 14, 2, 4, 0,		break;
	/* 365 */ 19, 15, 2, 15, 2, 14, 2, 4, 0,		case 'a': // 3 strings to match.
	/* 374 */ 0, 14, 2, 15, 2, 15, 2, 15, 2, 4, 0,		if (NameR[8] != '.')
	/* 385 */ 0, 14, 2, 15, 2, 15, 2, 15, 2, 15, 2, 4, 0,		break;
	/* 398 */ 19, 3, 4, 0,		switch (NameR[9]) {
	/* 402 */ 0, 14, 2, 15, 2, 15, 2, 4, 4, 0,		default: break;
	/* 412 */ 19, 15, 2, 15, 2, 14, 2, 15, 2, 15, 2, 4, 4, 0,		case 'i': // 1 string to match.
	/* 426 */ 0, 14, 2, 15, 2, 15, 2, 15, 2, 4, 4, 0,		if (memcmp(NameR.data()+10, "nsertqi", 7))
	/* 438 */ 20, 15, 2, 15, 2, 15, 2, 14, 2, 15, 2, 15, 2, 15, 2, 4, 4, 0,		break;
	/* 456 */ 0, 14, 2, 15, 2, 15, 2, 15, 2, 15, 2, 4, 4, 0,		return Intrinsic::x86_sse4a_insertqi; // "86.sse4a.insert
	/* 470 */ 21, 15, 2, 15, 2, 15, 2, 15, 2, 14, 2, 15, 2, 15, 2, 15, 2, 15,		qi"
	2, 4, 4, 0,		case 'm': // 2 strings to match.
	/* 492 */ 19, 4, 4, 4, 4, 4, 0,		if (memcmp(NameR.data()+10, "ovnt.s", 6))
	/* 499 */ 16, 16, 4, 4, 0,		break;
	/* 504 */ 19, 4, 4, 0,		switch (NameR[16]) {
	/* 508 */ 19, 5, 4, 0,		default: break;
	/* 512 */ 4, 16, 4, 0,		case 'd': // 1 string to match.
	/* 516 */ 16, 16, 4, 0,		return Intrinsic::x86_sse4a_movnt_sd; // "86.sse4
	/* 520 */ 16, 10, 7, 0,		a.movnt.sd"
	/* 524 */ 9, 8, 9, 8, 9, 8, 9, 8, 0,		case 's': // 1 string to match.
	/* 533 */ 16, 9, 8, 0,		return Intrinsic::x86_sse4a_movnt_ss; // "86.sse4
	/* 537 */ 10, 8, 10, 8, 10, 8, 10, 8, 0,		a.movnt.ss"
	/* 546 */ 4, 16, 0,		}
	/* 549 */ 10, 7, 10, 7, 16, 0,		break;
	/* 555 */ 9, 8, 16, 0,		}
	/* 559 */ 0, 14, 16, 16, 0,		break;
	/* 564 */ 16, 16, 16, 0,		}
	/* 568 */ 0, 17, 5, 17, 0,		break;
	/* 573 */ 0, 17, 17, 0,		}
	255		break;
	};		case 's': // 2 strings to match.
			if (memcmp(NameR.data()+6, "e3.ph", 5))
	#endif		break;
			switch (NameR[11]) {
	// Add parameter attributes that are not common to all intrinsics.		default: break;
	#ifdef GET_INTRINSIC_ATTRIBUTES		case 'a': // 1 string to match.
	AttributeSet Intrinsic::getAttributes(LLVMContext &C, ID id) {		if (memcmp(NameR.data()+12, "dd.sw", 5))
	static const uint8_t IntrinsicsToAttributesMap[] = {		break;
	1, // llvm.adjust.trampoline		return Intrinsic::x86_ssse3_phadd_sw; // "86.ssse3.phadd.
	2, // llvm.annotation		sw"
	2, // llvm.arm.cdp		case 's': // 1 string to match.
	2, // llvm.arm.cdp2		if (memcmp(NameR.data()+12, "ub.sw", 5))
	3, // llvm.arm.get.fpscr		break;
	1, // llvm.arm.ldrexd		return Intrinsic::x86_ssse3_phsub_sw; // "86.ssse3.phsub.
	2, // llvm.arm.mcr		sw"
	2, // llvm.arm.mcr2		}
	2, // llvm.arm.mcrr		break;
	2, // llvm.arm.mcrr2		}
	2, // llvm.arm.mrc		break;
	2, // llvm.arm.mrc2		case 't': // 2 strings to match.
	3, // llvm.arm.neon.vabds		if (memcmp(NameR.data()+4, "bm.bextri.u", 11))
	3, // llvm.arm.neon.vabdu		break;
	3, // llvm.arm.neon.vabs		switch (NameR[15]) {
	3, // llvm.arm.neon.vacged		default: break;
	3, // llvm.arm.neon.vacgeq		case '3': // 1 string to match.
	3, // llvm.arm.neon.vacgtd		if (NameR[16] != '2')
	3, // llvm.arm.neon.vacgtq		break;
	3, // llvm.arm.neon.vaddhn		return Intrinsic::x86_tbm_bextri_u32; // "86.tbm.bextri.u
	3, // llvm.arm.neon.vbsl		32"
	3, // llvm.arm.neon.vcls		case '6': // 1 string to match.
	3, // llvm.arm.neon.vclz		if (NameR[16] != '4')
	3, // llvm.arm.neon.vcnt		break;
	3, // llvm.arm.neon.vcvtfp2fxs		return Intrinsic::x86_tbm_bextri_u64; // "86.tbm.bextri.u
	3, // llvm.arm.neon.vcvtfp2fxu		64"
	3, // llvm.arm.neon.vcvtfp2hf		}
	3, // llvm.arm.neon.vcvtfxs2fp		break;
	3, // llvm.arm.neon.vcvtfxu2fp		case 'x': // 6 strings to match.
	3, // llvm.arm.neon.vcvthf2fp		if (memcmp(NameR.data()+4, "op.vp", 5))
	3, // llvm.arm.neon.vhadds		break;
	3, // llvm.arm.neon.vhaddu		switch (NameR[9]) {
	3, // llvm.arm.neon.vhsubs		default: break;
	3, // llvm.arm.neon.vhsubu		case 'c': // 1 string to match.
	1, // llvm.arm.neon.vld1		if (memcmp(NameR.data()+10, "mov.256", 7))
	1, // llvm.arm.neon.vld2		break;
	1, // llvm.arm.neon.vld2lane		return Intrinsic::x86_xop_vpcmov_256; // "86.xop.vpcmov.2
	1, // llvm.arm.neon.vld3		56"
	1, // llvm.arm.neon.vld3lane		case 'e': // 2 strings to match.
	1, // llvm.arm.neon.vld4		if (memcmp(NameR.data()+10, "rmil2p", 6))
	1, // llvm.arm.neon.vld4lane		break;
	3, // llvm.arm.neon.vmaxs		switch (NameR[16]) {
	3, // llvm.arm.neon.vmaxu		default: break;
	3, // llvm.arm.neon.vmins		case 'd': // 1 string to match.
	3, // llvm.arm.neon.vminu		return Intrinsic::x86_xop_vpermil2pd; // "86.xop.vpermil2
	3, // llvm.arm.neon.vmullp		pd"
	3, // llvm.arm.neon.vmulls		case 's': // 1 string to match.
	3, // llvm.arm.neon.vmullu		return Intrinsic::x86_xop_vpermil2ps; // "86.xop.vpermil2
	3, // llvm.arm.neon.vmulp		ps"
	3, // llvm.arm.neon.vpadals		}
	3, // llvm.arm.neon.vpadalu		break;
	3, // llvm.arm.neon.vpadd		case 'm': // 3 strings to match.
	3, // llvm.arm.neon.vpaddls		if (NameR[10] != 'a')
	3, // llvm.arm.neon.vpaddlu		break;
	3, // llvm.arm.neon.vpmaxs		switch (NameR[11]) {
	3, // llvm.arm.neon.vpmaxu		default: break;
	3, // llvm.arm.neon.vpmins		case 'c': // 2 strings to match.
	3, // llvm.arm.neon.vpminu		if (memcmp(NameR.data()+12, "ssdq", 4))
	3, // llvm.arm.neon.vqabs		break;
	3, // llvm.arm.neon.vqadds		switch (NameR[16]) {
	3, // llvm.arm.neon.vqaddu		default: break;
	3, // llvm.arm.neon.vqdmlal		case 'h': // 1 string to match.
	3, // llvm.arm.neon.vqdmlsl		return Intrinsic::x86_xop_vpmacssdqh; // "86.xop.vpmacssd
	3, // llvm.arm.neon.vqdmulh		qh"
	3, // llvm.arm.neon.vqdmull		case 'l': // 1 string to match.
	3, // llvm.arm.neon.vqmovns		return Intrinsic::x86_xop_vpmacssdql; // "86.xop.vpmacssd
	3, // llvm.arm.neon.vqmovnsu		ql"
	3, // llvm.arm.neon.vqmovnu		}
	3, // llvm.arm.neon.vqneg		break;
	3, // llvm.arm.neon.vqrdmulh		case 'd': // 1 string to match.
	3, // llvm.arm.neon.vqrshiftns		if (memcmp(NameR.data()+12, "csswd", 5))
	3, // llvm.arm.neon.vqrshiftnsu		break;
	3, // llvm.arm.neon.vqrshiftnu		return Intrinsic::x86_xop_vpmadcsswd; // "86.xop.vpmadcss
	3, // llvm.arm.neon.vqrshifts		wd"
	3, // llvm.arm.neon.vqrshiftu		}
	3, // llvm.arm.neon.vqshiftns		break;
	3, // llvm.arm.neon.vqshiftnsu		}
	3, // llvm.arm.neon.vqshiftnu		break;
	3, // llvm.arm.neon.vqshifts		}
	3, // llvm.arm.neon.vqshiftsu
	3, // llvm.arm.neon.vqshiftu
	3, // llvm.arm.neon.vqsubs
	3, // llvm.arm.neon.vqsubu
	3, // llvm.arm.neon.vraddhn
	3, // llvm.arm.neon.vrecpe
	3, // llvm.arm.neon.vrecps
	3, // llvm.arm.neon.vrhadds
	3, // llvm.arm.neon.vrhaddu
	3, // llvm.arm.neon.vrshiftn
	3, // llvm.arm.neon.vrshifts
	3, // llvm.arm.neon.vrshiftu
	3, // llvm.arm.neon.vrsqrte
	3, // llvm.arm.neon.vrsqrts
	3, // llvm.arm.neon.vrsubhn
	3, // llvm.arm.neon.vshiftins
	3, // llvm.arm.neon.vshiftls
	3, // llvm.arm.neon.vshiftlu
	3, // llvm.arm.neon.vshiftn
	3, // llvm.arm.neon.vshifts
	3, // llvm.arm.neon.vshiftu
	2, // llvm.arm.neon.vst1
	2, // llvm.arm.neon.vst2
	2, // llvm.arm.neon.vst2lane
	2, // llvm.arm.neon.vst3
	2, // llvm.arm.neon.vst3lane
	2, // llvm.arm.neon.vst4
	2, // llvm.arm.neon.vst4lane
	3, // llvm.arm.neon.vsubhn
	3, // llvm.arm.neon.vtbl1
	3, // llvm.arm.neon.vtbl2
	3, // llvm.arm.neon.vtbl3
	3, // llvm.arm.neon.vtbl4
	3, // llvm.arm.neon.vtbx1
	3, // llvm.arm.neon.vtbx2
	3, // llvm.arm.neon.vtbx3
	3, // llvm.arm.neon.vtbx4
	3, // llvm.arm.qadd
	3, // llvm.arm.qsub
	2, // llvm.arm.set.fpscr
	3, // llvm.arm.ssat
	2, // llvm.arm.strexd
	3, // llvm.arm.thread.pointer
	3, // llvm.arm.usat
	3, // llvm.arm.vcvtr
	3, // llvm.arm.vcvtru
	3, // llvm.bswap
	1, // llvm.ceil
	3, // llvm.convert.from.fp16
	3, // llvm.convert.to.fp16
	2, // llvm.convertff
	2, // llvm.convertfsi
	2, // llvm.convertfui
	2, // llvm.convertsif
	2, // llvm.convertss
	2, // llvm.convertsu
	2, // llvm.convertuif
	2, // llvm.convertus
	2, // llvm.convertuu
	1, // llvm.cos
	3, // llvm.ctlz
	3, // llvm.ctpop
	3, // llvm.cttz
	2, // llvm.cuda.syncthreads
	3, // llvm.dbg.declare
	3, // llvm.dbg.value
	2, // llvm.debugtrap
	3, // llvm.donothing
	2, // llvm.eh.dwarf.cfa
	2, // llvm.eh.return.i32
	2, // llvm.eh.return.i64
	3, // llvm.eh.sjlj.callsite
	2, // llvm.eh.sjlj.functioncontext
	4, // llvm.eh.sjlj.longjmp
	3, // llvm.eh.sjlj.lsda
	2, // llvm.eh.sjlj.setjmp
	3, // llvm.eh.typeid.for
	2, // llvm.eh.unwind.init
	1, // llvm.exp
	1, // llvm.exp2
	3, // llvm.expect
	1, // llvm.fabs
	1, // llvm.floor
	2, // llvm.flt.rounds
	3, // llvm.fma
	3, // llvm.fmuladd
	3, // llvm.frameaddress
	1, // llvm.gcread
	2, // llvm.gcroot
	5, // llvm.gcwrite
	3, // llvm.hexagon.A2.abs
	3, // llvm.hexagon.A2.absp
	3, // llvm.hexagon.A2.abssat
	3, // llvm.hexagon.A2.add
	3, // llvm.hexagon.A2.addh.h16.hh
	3, // llvm.hexagon.A2.addh.h16.hl
	3, // llvm.hexagon.A2.addh.h16.lh
	3, // llvm.hexagon.A2.addh.h16.ll
	3, // llvm.hexagon.A2.addh.h16.sat.hh
	3, // llvm.hexagon.A2.addh.h16.sat.hl
	3, // llvm.hexagon.A2.addh.h16.sat.lh
	3, // llvm.hexagon.A2.addh.h16.sat.ll
	3, // llvm.hexagon.A2.addh.l16.hl
	3, // llvm.hexagon.A2.addh.l16.ll
	3, // llvm.hexagon.A2.addh.l16.sat.hl
	3, // llvm.hexagon.A2.addh.l16.sat.ll
	3, // llvm.hexagon.A2.addi
	3, // llvm.hexagon.A2.addp
	3, // llvm.hexagon.A2.addpsat
	3, // llvm.hexagon.A2.addsat
	3, // llvm.hexagon.A2.addsp
	3, // llvm.hexagon.A2.and
	3, // llvm.hexagon.A2.andir
	3, // llvm.hexagon.A2.andp
	3, // llvm.hexagon.A2.aslh
	3, // llvm.hexagon.A2.asrh
	3, // llvm.hexagon.A2.combine.hh
	3, // llvm.hexagon.A2.combine.hl
	3, // llvm.hexagon.A2.combine.lh
	3, // llvm.hexagon.A2.combine.ll
	3, // llvm.hexagon.A2.combineii
	3, // llvm.hexagon.A2.combinew
	3, // llvm.hexagon.A2.max
	3, // llvm.hexagon.A2.maxp
	3, // llvm.hexagon.A2.maxu
	3, // llvm.hexagon.A2.maxup
	3, // llvm.hexagon.A2.min
	3, // llvm.hexagon.A2.minp
	3, // llvm.hexagon.A2.minu
	3, // llvm.hexagon.A2.minup
	3, // llvm.hexagon.A2.neg
	3, // llvm.hexagon.A2.negp
	3, // llvm.hexagon.A2.negsat
	3, // llvm.hexagon.A2.not
	3, // llvm.hexagon.A2.notp
	3, // llvm.hexagon.A2.or
	3, // llvm.hexagon.A2.orir
	3, // llvm.hexagon.A2.orp
	3, // llvm.hexagon.A2.roundsat
	3, // llvm.hexagon.A2.sat
	3, // llvm.hexagon.A2.satb
	3, // llvm.hexagon.A2.sath
	3, // llvm.hexagon.A2.satub
	3, // llvm.hexagon.A2.satuh
	3, // llvm.hexagon.A2.sub
	3, // llvm.hexagon.A2.subh.h16.hh
	3, // llvm.hexagon.A2.subh.h16.hl
	3, // llvm.hexagon.A2.subh.h16.lh
	3, // llvm.hexagon.A2.subh.h16.ll
	3, // llvm.hexagon.A2.subh.h16.sat.hh
	3, // llvm.hexagon.A2.subh.h16.sat.hl
	3, // llvm.hexagon.A2.subh.h16.sat.lh
	3, // llvm.hexagon.A2.subh.h16.sat.ll
	3, // llvm.hexagon.A2.subh.l16.hl
	3, // llvm.hexagon.A2.subh.l16.ll
	3, // llvm.hexagon.A2.subh.l16.sat.hl
	3, // llvm.hexagon.A2.subh.l16.sat.ll
	3, // llvm.hexagon.A2.subp
	3, // llvm.hexagon.A2.subri
	3, // llvm.hexagon.A2.subsat
	3, // llvm.hexagon.A2.svaddh
	3, // llvm.hexagon.A2.svaddhs
	3, // llvm.hexagon.A2.svadduhs
	3, // llvm.hexagon.A2.svavgh
	3, // llvm.hexagon.A2.svavghs
	3, // llvm.hexagon.A2.svnavgh
	3, // llvm.hexagon.A2.svsubh
	3, // llvm.hexagon.A2.svsubhs
	3, // llvm.hexagon.A2.svsubuhs
	3, // llvm.hexagon.A2.swiz
	3, // llvm.hexagon.A2.sxtb
	3, // llvm.hexagon.A2.sxth
	3, // llvm.hexagon.A2.sxtw
	3, // llvm.hexagon.A2.tfr
	3, // llvm.hexagon.A2.tfrih
	3, // llvm.hexagon.A2.tfril
	3, // llvm.hexagon.A2.tfrp
	3, // llvm.hexagon.A2.tfrpi
	3, // llvm.hexagon.A2.tfrsi
	3, // llvm.hexagon.A2.vabsh
	3, // llvm.hexagon.A2.vabshsat
	3, // llvm.hexagon.A2.vabsw
	3, // llvm.hexagon.A2.vabswsat
	3, // llvm.hexagon.A2.vaddb.map
	3, // llvm.hexagon.A2.vaddh
	3, // llvm.hexagon.A2.vaddhs
	3, // llvm.hexagon.A2.vaddub
	3, // llvm.hexagon.A2.vaddubs
	3, // llvm.hexagon.A2.vadduhs
	3, // llvm.hexagon.A2.vaddw
	3, // llvm.hexagon.A2.vaddws
	3, // llvm.hexagon.A2.vavgh
	3, // llvm.hexagon.A2.vavghcr
	3, // llvm.hexagon.A2.vavghr
	3, // llvm.hexagon.A2.vavgub
	3, // llvm.hexagon.A2.vavgubr
	3, // llvm.hexagon.A2.vavguh
	3, // llvm.hexagon.A2.vavguhr
	3, // llvm.hexagon.A2.vavguw
	3, // llvm.hexagon.A2.vavguwr
	3, // llvm.hexagon.A2.vavgw
	3, // llvm.hexagon.A2.vavgwcr
	3, // llvm.hexagon.A2.vavgwr
	3, // llvm.hexagon.A2.vcmpbeq
	3, // llvm.hexagon.A2.vcmpbgtu
	3, // llvm.hexagon.A2.vcmpheq
	3, // llvm.hexagon.A2.vcmphgt
	3, // llvm.hexagon.A2.vcmphgtu
	3, // llvm.hexagon.A2.vcmpweq
	3, // llvm.hexagon.A2.vcmpwgt
	3, // llvm.hexagon.A2.vcmpwgtu
	3, // llvm.hexagon.A2.vconj
	3, // llvm.hexagon.A2.vmaxb
	3, // llvm.hexagon.A2.vmaxh
	3, // llvm.hexagon.A2.vmaxub
	3, // llvm.hexagon.A2.vmaxuh
	3, // llvm.hexagon.A2.vmaxuw
	3, // llvm.hexagon.A2.vmaxw
	3, // llvm.hexagon.A2.vminb
	3, // llvm.hexagon.A2.vminh
	3, // llvm.hexagon.A2.vminub
	3, // llvm.hexagon.A2.vminuh
	3, // llvm.hexagon.A2.vminuw
	3, // llvm.hexagon.A2.vminw
	3, // llvm.hexagon.A2.vnavgh
	3, // llvm.hexagon.A2.vnavghcr
	3, // llvm.hexagon.A2.vnavghr
	3, // llvm.hexagon.A2.vnavgw
	3, // llvm.hexagon.A2.vnavgwcr
	3, // llvm.hexagon.A2.vnavgwr
	3, // llvm.hexagon.A2.vraddub
	3, // llvm.hexagon.A2.vraddub.acc
	3, // llvm.hexagon.A2.vrsadub
	3, // llvm.hexagon.A2.vrsadub.acc
	3, // llvm.hexagon.A2.vsubb.map
	3, // llvm.hexagon.A2.vsubh
	3, // llvm.hexagon.A2.vsubhs
	3, // llvm.hexagon.A2.vsubub
	3, // llvm.hexagon.A2.vsububs
	3, // llvm.hexagon.A2.vsubuhs
	3, // llvm.hexagon.A2.vsubw
	3, // llvm.hexagon.A2.vsubws
	3, // llvm.hexagon.A2.xor
	3, // llvm.hexagon.A2.xorp
	3, // llvm.hexagon.A2.zxtb
	3, // llvm.hexagon.A2.zxth
	3, // llvm.hexagon.A4.andn
	3, // llvm.hexagon.A4.andnp
	3, // llvm.hexagon.A4.bitsplit
	3, // llvm.hexagon.A4.bitspliti
	3, // llvm.hexagon.A4.boundscheck
	3, // llvm.hexagon.A4.cmpbeq
	3, // llvm.hexagon.A4.cmpbeqi
	3, // llvm.hexagon.A4.cmpbgt
	3, // llvm.hexagon.A4.cmpbgti
	3, // llvm.hexagon.A4.cmpbgtu
	3, // llvm.hexagon.A4.cmpbgtui
	3, // llvm.hexagon.A4.cmpheq
	3, // llvm.hexagon.A4.cmpheqi
	3, // llvm.hexagon.A4.cmphgt
	3, // llvm.hexagon.A4.cmphgti
	3, // llvm.hexagon.A4.cmphgtu
	3, // llvm.hexagon.A4.cmphgtui
	3, // llvm.hexagon.A4.combineir
	3, // llvm.hexagon.A4.combineri
	3, // llvm.hexagon.A4.cround.ri
	3, // llvm.hexagon.A4.cround.rr
	3, // llvm.hexagon.A4.modwrapu
	3, // llvm.hexagon.A4.orn
	3, // llvm.hexagon.A4.ornp
	3, // llvm.hexagon.A4.rcmpeq
	3, // llvm.hexagon.A4.rcmpeqi
	3, // llvm.hexagon.A4.rcmpneq
	3, // llvm.hexagon.A4.rcmpneqi
	3, // llvm.hexagon.A4.round.ri
	3, // llvm.hexagon.A4.round.ri.sat
	3, // llvm.hexagon.A4.round.rr
	3, // llvm.hexagon.A4.round.rr.sat
	3, // llvm.hexagon.A4.tlbmatch
	3, // llvm.hexagon.A4.vcmpbeq.any
	3, // llvm.hexagon.A4.vcmpbeqi
	3, // llvm.hexagon.A4.vcmpbgt
	3, // llvm.hexagon.A4.vcmpbgti
	3, // llvm.hexagon.A4.vcmpbgtui
	3, // llvm.hexagon.A4.vcmpheqi
	3, // llvm.hexagon.A4.vcmphgti
	3, // llvm.hexagon.A4.vcmphgtui
	3, // llvm.hexagon.A4.vcmpweqi
	3, // llvm.hexagon.A4.vcmpwgti
	3, // llvm.hexagon.A4.vcmpwgtui
	3, // llvm.hexagon.A4.vrmaxh
	3, // llvm.hexagon.A4.vrmaxuh
	3, // llvm.hexagon.A4.vrmaxuw
	3, // llvm.hexagon.A4.vrmaxw
	3, // llvm.hexagon.A4.vrminh
	3, // llvm.hexagon.A4.vrminuh
	3, // llvm.hexagon.A4.vrminuw
	3, // llvm.hexagon.A4.vrminw
	3, // llvm.hexagon.A5.vaddhubs
	3, // llvm.hexagon.C2.all8
	3, // llvm.hexagon.C2.and
	3, // llvm.hexagon.C2.andn
	3, // llvm.hexagon.C2.any8
	3, // llvm.hexagon.C2.bitsclr
	3, // llvm.hexagon.C2.bitsclri
	3, // llvm.hexagon.C2.bitsset
	3, // llvm.hexagon.C2.cmpeq
	3, // llvm.hexagon.C2.cmpeqi
	3, // llvm.hexagon.C2.cmpeqp
	3, // llvm.hexagon.C2.cmpgei
	3, // llvm.hexagon.C2.cmpgeui
	3, // llvm.hexagon.C2.cmpgt
	3, // llvm.hexagon.C2.cmpgti
	3, // llvm.hexagon.C2.cmpgtp
	3, // llvm.hexagon.C2.cmpgtu
	3, // llvm.hexagon.C2.cmpgtui
	3, // llvm.hexagon.C2.cmpgtup
	3, // llvm.hexagon.C2.cmplt
	3, // llvm.hexagon.C2.cmpltu
	3, // llvm.hexagon.C2.mask
	3, // llvm.hexagon.C2.mux
	3, // llvm.hexagon.C2.muxii
	3, // llvm.hexagon.C2.muxir
	3, // llvm.hexagon.C2.muxri
	3, // llvm.hexagon.C2.not
	3, // llvm.hexagon.C2.or
	3, // llvm.hexagon.C2.orn
	3, // llvm.hexagon.C2.pxfer.map
	3, // llvm.hexagon.C2.tfrpr
	3, // llvm.hexagon.C2.tfrrp
	3, // llvm.hexagon.C2.vitpack
	3, // llvm.hexagon.C2.vmux
	3, // llvm.hexagon.C2.xor
	3, // llvm.hexagon.C4.and.and
	3, // llvm.hexagon.C4.and.andn
	3, // llvm.hexagon.C4.and.or
	3, // llvm.hexagon.C4.and.orn
	3, // llvm.hexagon.C4.cmplte
	3, // llvm.hexagon.C4.cmpltei
	3, // llvm.hexagon.C4.cmplteu
	3, // llvm.hexagon.C4.cmplteui
	3, // llvm.hexagon.C4.cmpneq
	3, // llvm.hexagon.C4.cmpneqi
	3, // llvm.hexagon.C4.fastcorner9
	3, // llvm.hexagon.C4.fastcorner9.not
	3, // llvm.hexagon.C4.nbitsclr
	3, // llvm.hexagon.C4.nbitsclri
	3, // llvm.hexagon.C4.nbitsset
	3, // llvm.hexagon.C4.or.and
	3, // llvm.hexagon.C4.or.andn
	3, // llvm.hexagon.C4.or.or
	3, // llvm.hexagon.C4.or.orn
	3, // llvm.hexagon.F2.conv.d2df
	3, // llvm.hexagon.F2.conv.d2sf
	3, // llvm.hexagon.F2.conv.df2d
	3, // llvm.hexagon.F2.conv.df2d.chop
	3, // llvm.hexagon.F2.conv.df2sf
	3, // llvm.hexagon.F2.conv.df2ud
	3, // llvm.hexagon.F2.conv.df2ud.chop
	3, // llvm.hexagon.F2.conv.df2uw
	3, // llvm.hexagon.F2.conv.df2uw.chop
	3, // llvm.hexagon.F2.conv.df2w
	3, // llvm.hexagon.F2.conv.df2w.chop
	3, // llvm.hexagon.F2.conv.sf2d
	3, // llvm.hexagon.F2.conv.sf2d.chop
	3, // llvm.hexagon.F2.conv.sf2df
	3, // llvm.hexagon.F2.conv.sf2ud
	3, // llvm.hexagon.F2.conv.sf2ud.chop
	3, // llvm.hexagon.F2.conv.sf2uw
	3, // llvm.hexagon.F2.conv.sf2uw.chop
	3, // llvm.hexagon.F2.conv.sf2w
	3, // llvm.hexagon.F2.conv.sf2w.chop
	3, // llvm.hexagon.F2.conv.ud2df
	3, // llvm.hexagon.F2.conv.ud2sf
	3, // llvm.hexagon.F2.conv.uw2df
	3, // llvm.hexagon.F2.conv.uw2sf
	3, // llvm.hexagon.F2.conv.w2df
	3, // llvm.hexagon.F2.conv.w2sf
	3, // llvm.hexagon.F2.dfadd
	3, // llvm.hexagon.F2.dfclass
	3, // llvm.hexagon.F2.dfcmpeq
	3, // llvm.hexagon.F2.dfcmpge
	3, // llvm.hexagon.F2.dfcmpgt
	3, // llvm.hexagon.F2.dfcmpuo
	3, // llvm.hexagon.F2.dffixupd
	3, // llvm.hexagon.F2.dffixupn
	3, // llvm.hexagon.F2.dffixupr
	3, // llvm.hexagon.F2.dffma
	3, // llvm.hexagon.F2.dffma.lib
	3, // llvm.hexagon.F2.dffma.sc
	3, // llvm.hexagon.F2.dffms
	3, // llvm.hexagon.F2.dffms.lib
	3, // llvm.hexagon.F2.dfimm.n
	3, // llvm.hexagon.F2.dfimm.p
	3, // llvm.hexagon.F2.dfmax
	3, // llvm.hexagon.F2.dfmin
	3, // llvm.hexagon.F2.dfmpy
	3, // llvm.hexagon.F2.dfsub
	3, // llvm.hexagon.F2.sfadd
	3, // llvm.hexagon.F2.sfclass
	3, // llvm.hexagon.F2.sfcmpeq
	3, // llvm.hexagon.F2.sfcmpge
	3, // llvm.hexagon.F2.sfcmpgt
	3, // llvm.hexagon.F2.sfcmpuo
	3, // llvm.hexagon.F2.sffixupd
	3, // llvm.hexagon.F2.sffixupn
	3, // llvm.hexagon.F2.sffixupr
	3, // llvm.hexagon.F2.sffma
	3, // llvm.hexagon.F2.sffma.lib
	3, // llvm.hexagon.F2.sffma.sc
	3, // llvm.hexagon.F2.sffms
	3, // llvm.hexagon.F2.sffms.lib
	3, // llvm.hexagon.F2.sfimm.n
	3, // llvm.hexagon.F2.sfimm.p
	3, // llvm.hexagon.F2.sfmax
	3, // llvm.hexagon.F2.sfmin
	3, // llvm.hexagon.F2.sfmpy
	3, // llvm.hexagon.F2.sfsub
	3, // llvm.hexagon.M2.acci
	3, // llvm.hexagon.M2.accii
	3, // llvm.hexagon.M2.cmaci.s0
	3, // llvm.hexagon.M2.cmacr.s0
	3, // llvm.hexagon.M2.cmacs.s0
	3, // llvm.hexagon.M2.cmacs.s1
	3, // llvm.hexagon.M2.cmacsc.s0
	3, // llvm.hexagon.M2.cmacsc.s1
	3, // llvm.hexagon.M2.cmpyi.s0
	3, // llvm.hexagon.M2.cmpyr.s0
	3, // llvm.hexagon.M2.cmpyrs.s0
	3, // llvm.hexagon.M2.cmpyrs.s1
	3, // llvm.hexagon.M2.cmpyrsc.s0
	3, // llvm.hexagon.M2.cmpyrsc.s1
	3, // llvm.hexagon.M2.cmpys.s0
	3, // llvm.hexagon.M2.cmpys.s1
	3, // llvm.hexagon.M2.cmpysc.s0
	3, // llvm.hexagon.M2.cmpysc.s1
	3, // llvm.hexagon.M2.cnacs.s0
	3, // llvm.hexagon.M2.cnacs.s1
	3, // llvm.hexagon.M2.cnacsc.s0
	3, // llvm.hexagon.M2.cnacsc.s1
	3, // llvm.hexagon.M2.dpmpyss.acc.s0
	3, // llvm.hexagon.M2.dpmpyss.nac.s0
	3, // llvm.hexagon.M2.dpmpyss.rnd.s0
	3, // llvm.hexagon.M2.dpmpyss.s0
	3, // llvm.hexagon.M2.dpmpyuu.acc.s0
	3, // llvm.hexagon.M2.dpmpyuu.nac.s0
	3, // llvm.hexagon.M2.dpmpyuu.s0
	3, // llvm.hexagon.M2.hmmpyh.rs1
	3, // llvm.hexagon.M2.hmmpyh.s1
	3, // llvm.hexagon.M2.hmmpyl.rs1
	3, // llvm.hexagon.M2.hmmpyl.s1
	3, // llvm.hexagon.M2.maci
	3, // llvm.hexagon.M2.macsin
	3, // llvm.hexagon.M2.macsip
	3, // llvm.hexagon.M2.mmachs.rs0
	3, // llvm.hexagon.M2.mmachs.rs1
	3, // llvm.hexagon.M2.mmachs.s0
	3, // llvm.hexagon.M2.mmachs.s1
	3, // llvm.hexagon.M2.mmacls.rs0
	3, // llvm.hexagon.M2.mmacls.rs1
	3, // llvm.hexagon.M2.mmacls.s0
	3, // llvm.hexagon.M2.mmacls.s1
	3, // llvm.hexagon.M2.mmacuhs.rs0
	3, // llvm.hexagon.M2.mmacuhs.rs1
	3, // llvm.hexagon.M2.mmacuhs.s0
	3, // llvm.hexagon.M2.mmacuhs.s1
	3, // llvm.hexagon.M2.mmaculs.rs0
	3, // llvm.hexagon.M2.mmaculs.rs1
	3, // llvm.hexagon.M2.mmaculs.s0
	3, // llvm.hexagon.M2.mmaculs.s1
	3, // llvm.hexagon.M2.mmpyh.rs0
	3, // llvm.hexagon.M2.mmpyh.rs1
	3, // llvm.hexagon.M2.mmpyh.s0
	3, // llvm.hexagon.M2.mmpyh.s1
	3, // llvm.hexagon.M2.mmpyl.rs0
	3, // llvm.hexagon.M2.mmpyl.rs1
	3, // llvm.hexagon.M2.mmpyl.s0
	3, // llvm.hexagon.M2.mmpyl.s1
	3, // llvm.hexagon.M2.mmpyuh.rs0
	3, // llvm.hexagon.M2.mmpyuh.rs1
	3, // llvm.hexagon.M2.mmpyuh.s0
	3, // llvm.hexagon.M2.mmpyuh.s1
	3, // llvm.hexagon.M2.mmpyul.rs0
	3, // llvm.hexagon.M2.mmpyul.rs1
	3, // llvm.hexagon.M2.mmpyul.s0
	3, // llvm.hexagon.M2.mmpyul.s1
	3, // llvm.hexagon.M2.mpy.acc.hh.s0
	3, // llvm.hexagon.M2.mpy.acc.hh.s1
	3, // llvm.hexagon.M2.mpy.acc.hl.s0
	3, // llvm.hexagon.M2.mpy.acc.hl.s1
	3, // llvm.hexagon.M2.mpy.acc.lh.s0
	3, // llvm.hexagon.M2.mpy.acc.lh.s1
	3, // llvm.hexagon.M2.mpy.acc.ll.s0
	3, // llvm.hexagon.M2.mpy.acc.ll.s1
	3, // llvm.hexagon.M2.mpy.acc.sat.hh.s0
	3, // llvm.hexagon.M2.mpy.acc.sat.hh.s1
	3, // llvm.hexagon.M2.mpy.acc.sat.hl.s0
	3, // llvm.hexagon.M2.mpy.acc.sat.hl.s1
	3, // llvm.hexagon.M2.mpy.acc.sat.lh.s0
	3, // llvm.hexagon.M2.mpy.acc.sat.lh.s1
	3, // llvm.hexagon.M2.mpy.acc.sat.ll.s0
	3, // llvm.hexagon.M2.mpy.acc.sat.ll.s1
	3, // llvm.hexagon.M2.mpy.hh.s0
	3, // llvm.hexagon.M2.mpy.hh.s1
	3, // llvm.hexagon.M2.mpy.hl.s0
	3, // llvm.hexagon.M2.mpy.hl.s1
	3, // llvm.hexagon.M2.mpy.lh.s0
	3, // llvm.hexagon.M2.mpy.lh.s1
	3, // llvm.hexagon.M2.mpy.ll.s0
	3, // llvm.hexagon.M2.mpy.ll.s1
	3, // llvm.hexagon.M2.mpy.nac.hh.s0
	3, // llvm.hexagon.M2.mpy.nac.hh.s1
	3, // llvm.hexagon.M2.mpy.nac.hl.s0
	3, // llvm.hexagon.M2.mpy.nac.hl.s1
	3, // llvm.hexagon.M2.mpy.nac.lh.s0
	3, // llvm.hexagon.M2.mpy.nac.lh.s1
	3, // llvm.hexagon.M2.mpy.nac.ll.s0
	3, // llvm.hexagon.M2.mpy.nac.ll.s1
	3, // llvm.hexagon.M2.mpy.nac.sat.hh.s0
	3, // llvm.hexagon.M2.mpy.nac.sat.hh.s1
	3, // llvm.hexagon.M2.mpy.nac.sat.hl.s0
	3, // llvm.hexagon.M2.mpy.nac.sat.hl.s1
	3, // llvm.hexagon.M2.mpy.nac.sat.lh.s0
	3, // llvm.hexagon.M2.mpy.nac.sat.lh.s1
	3, // llvm.hexagon.M2.mpy.nac.sat.ll.s0
	3, // llvm.hexagon.M2.mpy.nac.sat.ll.s1
	3, // llvm.hexagon.M2.mpy.rnd.hh.s0
	3, // llvm.hexagon.M2.mpy.rnd.hh.s1
	3, // llvm.hexagon.M2.mpy.rnd.hl.s0
	3, // llvm.hexagon.M2.mpy.rnd.hl.s1
	3, // llvm.hexagon.M2.mpy.rnd.lh.s0
	3, // llvm.hexagon.M2.mpy.rnd.lh.s1
	3, // llvm.hexagon.M2.mpy.rnd.ll.s0
	3, // llvm.hexagon.M2.mpy.rnd.ll.s1
	3, // llvm.hexagon.M2.mpy.sat.hh.s0
	3, // llvm.hexagon.M2.mpy.sat.hh.s1
	3, // llvm.hexagon.M2.mpy.sat.hl.s0
	3, // llvm.hexagon.M2.mpy.sat.hl.s1
	3, // llvm.hexagon.M2.mpy.sat.lh.s0
	3, // llvm.hexagon.M2.mpy.sat.lh.s1
	3, // llvm.hexagon.M2.mpy.sat.ll.s0
	3, // llvm.hexagon.M2.mpy.sat.ll.s1
	3, // llvm.hexagon.M2.mpy.sat.rnd.hh.s0
	3, // llvm.hexagon.M2.mpy.sat.rnd.hh.s1
	3, // llvm.hexagon.M2.mpy.sat.rnd.hl.s0
	3, // llvm.hexagon.M2.mpy.sat.rnd.hl.s1
	3, // llvm.hexagon.M2.mpy.sat.rnd.lh.s0
	3, // llvm.hexagon.M2.mpy.sat.rnd.lh.s1
	3, // llvm.hexagon.M2.mpy.sat.rnd.ll.s0
	3, // llvm.hexagon.M2.mpy.sat.rnd.ll.s1
	3, // llvm.hexagon.M2.mpy.up
	3, // llvm.hexagon.M2.mpy.up.s1
	3, // llvm.hexagon.M2.mpy.up.s1.sat
	3, // llvm.hexagon.M2.mpyd.acc.hh.s0
	3, // llvm.hexagon.M2.mpyd.acc.hh.s1
	3, // llvm.hexagon.M2.mpyd.acc.hl.s0
	3, // llvm.hexagon.M2.mpyd.acc.hl.s1
	3, // llvm.hexagon.M2.mpyd.acc.lh.s0
	3, // llvm.hexagon.M2.mpyd.acc.lh.s1
	3, // llvm.hexagon.M2.mpyd.acc.ll.s0
	3, // llvm.hexagon.M2.mpyd.acc.ll.s1
	3, // llvm.hexagon.M2.mpyd.hh.s0
	3, // llvm.hexagon.M2.mpyd.hh.s1
	3, // llvm.hexagon.M2.mpyd.hl.s0
	3, // llvm.hexagon.M2.mpyd.hl.s1
	3, // llvm.hexagon.M2.mpyd.lh.s0
	3, // llvm.hexagon.M2.mpyd.lh.s1
	3, // llvm.hexagon.M2.mpyd.ll.s0
	3, // llvm.hexagon.M2.mpyd.ll.s1
	3, // llvm.hexagon.M2.mpyd.nac.hh.s0
	3, // llvm.hexagon.M2.mpyd.nac.hh.s1
	3, // llvm.hexagon.M2.mpyd.nac.hl.s0
	3, // llvm.hexagon.M2.mpyd.nac.hl.s1
	3, // llvm.hexagon.M2.mpyd.nac.lh.s0
	3, // llvm.hexagon.M2.mpyd.nac.lh.s1
	3, // llvm.hexagon.M2.mpyd.nac.ll.s0
	3, // llvm.hexagon.M2.mpyd.nac.ll.s1
	3, // llvm.hexagon.M2.mpyd.rnd.hh.s0
	3, // llvm.hexagon.M2.mpyd.rnd.hh.s1
	3, // llvm.hexagon.M2.mpyd.rnd.hl.s0
	3, // llvm.hexagon.M2.mpyd.rnd.hl.s1
	3, // llvm.hexagon.M2.mpyd.rnd.lh.s0
	3, // llvm.hexagon.M2.mpyd.rnd.lh.s1
	3, // llvm.hexagon.M2.mpyd.rnd.ll.s0
	3, // llvm.hexagon.M2.mpyd.rnd.ll.s1
	3, // llvm.hexagon.M2.mpyi
	3, // llvm.hexagon.M2.mpysmi
	3, // llvm.hexagon.M2.mpysu.up
	3, // llvm.hexagon.M2.mpyu.acc.hh.s0
	3, // llvm.hexagon.M2.mpyu.acc.hh.s1
	3, // llvm.hexagon.M2.mpyu.acc.hl.s0
	3, // llvm.hexagon.M2.mpyu.acc.hl.s1
	3, // llvm.hexagon.M2.mpyu.acc.lh.s0
	3, // llvm.hexagon.M2.mpyu.acc.lh.s1
	3, // llvm.hexagon.M2.mpyu.acc.ll.s0
	3, // llvm.hexagon.M2.mpyu.acc.ll.s1
	3, // llvm.hexagon.M2.mpyu.hh.s0
	3, // llvm.hexagon.M2.mpyu.hh.s1
	3, // llvm.hexagon.M2.mpyu.hl.s0
	3, // llvm.hexagon.M2.mpyu.hl.s1
	3, // llvm.hexagon.M2.mpyu.lh.s0
	3, // llvm.hexagon.M2.mpyu.lh.s1
	3, // llvm.hexagon.M2.mpyu.ll.s0
	3, // llvm.hexagon.M2.mpyu.ll.s1
	3, // llvm.hexagon.M2.mpyu.nac.hh.s0
	3, // llvm.hexagon.M2.mpyu.nac.hh.s1
	3, // llvm.hexagon.M2.mpyu.nac.hl.s0
	3, // llvm.hexagon.M2.mpyu.nac.hl.s1
	3, // llvm.hexagon.M2.mpyu.nac.lh.s0
	3, // llvm.hexagon.M2.mpyu.nac.lh.s1
	3, // llvm.hexagon.M2.mpyu.nac.ll.s0
	3, // llvm.hexagon.M2.mpyu.nac.ll.s1
	3, // llvm.hexagon.M2.mpyu.up
	3, // llvm.hexagon.M2.mpyud.acc.hh.s0
	3, // llvm.hexagon.M2.mpyud.acc.hh.s1
	3, // llvm.hexagon.M2.mpyud.acc.hl.s0
	3, // llvm.hexagon.M2.mpyud.acc.hl.s1
	3, // llvm.hexagon.M2.mpyud.acc.lh.s0
	3, // llvm.hexagon.M2.mpyud.acc.lh.s1
	3, // llvm.hexagon.M2.mpyud.acc.ll.s0
	3, // llvm.hexagon.M2.mpyud.acc.ll.s1
	3, // llvm.hexagon.M2.mpyud.hh.s0
	3, // llvm.hexagon.M2.mpyud.hh.s1
	3, // llvm.hexagon.M2.mpyud.hl.s0
	3, // llvm.hexagon.M2.mpyud.hl.s1
	3, // llvm.hexagon.M2.mpyud.lh.s0
	3, // llvm.hexagon.M2.mpyud.lh.s1
	3, // llvm.hexagon.M2.mpyud.ll.s0
	3, // llvm.hexagon.M2.mpyud.ll.s1
	3, // llvm.hexagon.M2.mpyud.nac.hh.s0
	3, // llvm.hexagon.M2.mpyud.nac.hh.s1
	3, // llvm.hexagon.M2.mpyud.nac.hl.s0
	3, // llvm.hexagon.M2.mpyud.nac.hl.s1
	3, // llvm.hexagon.M2.mpyud.nac.lh.s0
	3, // llvm.hexagon.M2.mpyud.nac.lh.s1
	3, // llvm.hexagon.M2.mpyud.nac.ll.s0
	3, // llvm.hexagon.M2.mpyud.nac.ll.s1
	3, // llvm.hexagon.M2.mpyui
	3, // llvm.hexagon.M2.nacci
	3, // llvm.hexagon.M2.naccii
	3, // llvm.hexagon.M2.subacc
	3, // llvm.hexagon.M2.vabsdiffh
	3, // llvm.hexagon.M2.vabsdiffw
	3, // llvm.hexagon.M2.vcmac.s0.sat.i
	3, // llvm.hexagon.M2.vcmac.s0.sat.r
	3, // llvm.hexagon.M2.vcmpy.s0.sat.i
	3, // llvm.hexagon.M2.vcmpy.s0.sat.r
	3, // llvm.hexagon.M2.vcmpy.s1.sat.i
	3, // llvm.hexagon.M2.vcmpy.s1.sat.r
	3, // llvm.hexagon.M2.vdmacs.s0
	3, // llvm.hexagon.M2.vdmacs.s1
	3, // llvm.hexagon.M2.vdmpyrs.s0
	3, // llvm.hexagon.M2.vdmpyrs.s1
	3, // llvm.hexagon.M2.vdmpys.s0
	3, // llvm.hexagon.M2.vdmpys.s1
	3, // llvm.hexagon.M2.vmac2
	3, // llvm.hexagon.M2.vmac2es
	3, // llvm.hexagon.M2.vmac2es.s0
	3, // llvm.hexagon.M2.vmac2es.s1
	3, // llvm.hexagon.M2.vmac2s.s0
	3, // llvm.hexagon.M2.vmac2s.s1
	3, // llvm.hexagon.M2.vmac2su.s0
	3, // llvm.hexagon.M2.vmac2su.s1
	3, // llvm.hexagon.M2.vmpy2es.s0
	3, // llvm.hexagon.M2.vmpy2es.s1
	3, // llvm.hexagon.M2.vmpy2s.s0
	3, // llvm.hexagon.M2.vmpy2s.s0pack
	3, // llvm.hexagon.M2.vmpy2s.s1
	3, // llvm.hexagon.M2.vmpy2s.s1pack
	3, // llvm.hexagon.M2.vmpy2su.s0
	3, // llvm.hexagon.M2.vmpy2su.s1
	3, // llvm.hexagon.M2.vraddh
	3, // llvm.hexagon.M2.vradduh
	3, // llvm.hexagon.M2.vrcmaci.s0
	3, // llvm.hexagon.M2.vrcmaci.s0c
	3, // llvm.hexagon.M2.vrcmacr.s0
	3, // llvm.hexagon.M2.vrcmacr.s0c
	3, // llvm.hexagon.M2.vrcmpyi.s0
	3, // llvm.hexagon.M2.vrcmpyi.s0c
	3, // llvm.hexagon.M2.vrcmpyr.s0
	3, // llvm.hexagon.M2.vrcmpyr.s0c
	3, // llvm.hexagon.M2.vrcmpys.acc.s1
	3, // llvm.hexagon.M2.vrcmpys.s1
	3, // llvm.hexagon.M2.vrcmpys.s1rp
	3, // llvm.hexagon.M2.vrmac.s0
	3, // llvm.hexagon.M2.vrmpy.s0
	3, // llvm.hexagon.M2.xor.xacc
	3, // llvm.hexagon.M4.and.and
	3, // llvm.hexagon.M4.and.andn
	3, // llvm.hexagon.M4.and.or
	3, // llvm.hexagon.M4.and.xor
	3, // llvm.hexagon.M4.cmpyi.wh
	3, // llvm.hexagon.M4.cmpyi.whc
	3, // llvm.hexagon.M4.cmpyr.wh
	3, // llvm.hexagon.M4.cmpyr.whc
	3, // llvm.hexagon.M4.mac.up.s1.sat
	3, // llvm.hexagon.M4.mpyri.addi
	3, // llvm.hexagon.M4.mpyri.addr
	3, // llvm.hexagon.M4.mpyri.addr.u2
	3, // llvm.hexagon.M4.mpyrr.addi
	3, // llvm.hexagon.M4.mpyrr.addr
	3, // llvm.hexagon.M4.nac.up.s1.sat
	3, // llvm.hexagon.M4.or.and
	3, // llvm.hexagon.M4.or.andn
	3, // llvm.hexagon.M4.or.or
	3, // llvm.hexagon.M4.or.xor
	3, // llvm.hexagon.M4.pmpyw
	3, // llvm.hexagon.M4.pmpyw.acc
	3, // llvm.hexagon.M4.vpmpyh
	3, // llvm.hexagon.M4.vpmpyh.acc
	3, // llvm.hexagon.M4.vrmpyeh.acc.s0
	3, // llvm.hexagon.M4.vrmpyeh.acc.s1
	3, // llvm.hexagon.M4.vrmpyeh.s0
	3, // llvm.hexagon.M4.vrmpyeh.s1
	3, // llvm.hexagon.M4.vrmpyoh.acc.s0
	3, // llvm.hexagon.M4.vrmpyoh.acc.s1
	3, // llvm.hexagon.M4.vrmpyoh.s0
	3, // llvm.hexagon.M4.vrmpyoh.s1
	3, // llvm.hexagon.M4.xor.and
	3, // llvm.hexagon.M4.xor.andn
	3, // llvm.hexagon.M4.xor.or
	3, // llvm.hexagon.M4.xor.xacc
	3, // llvm.hexagon.M5.vdmacbsu
	3, // llvm.hexagon.M5.vdmpybsu
	3, // llvm.hexagon.M5.vmacbsu
	3, // llvm.hexagon.M5.vmacbuu
	3, // llvm.hexagon.M5.vmpybsu
	3, // llvm.hexagon.M5.vmpybuu
	3, // llvm.hexagon.M5.vrmacbsu
	3, // llvm.hexagon.M5.vrmacbuu
	3, // llvm.hexagon.M5.vrmpybsu
	3, // llvm.hexagon.M5.vrmpybuu
	3, // llvm.hexagon.S2.addasl.rrri
	3, // llvm.hexagon.S2.asl.i.p
	3, // llvm.hexagon.S2.asl.i.p.acc
	3, // llvm.hexagon.S2.asl.i.p.and
	3, // llvm.hexagon.S2.asl.i.p.nac
	3, // llvm.hexagon.S2.asl.i.p.or
	3, // llvm.hexagon.S2.asl.i.p.xacc
	3, // llvm.hexagon.S2.asl.i.r
	3, // llvm.hexagon.S2.asl.i.r.acc
	3, // llvm.hexagon.S2.asl.i.r.and
	3, // llvm.hexagon.S2.asl.i.r.nac
	3, // llvm.hexagon.S2.asl.i.r.or
	3, // llvm.hexagon.S2.asl.i.r.sat
	3, // llvm.hexagon.S2.asl.i.r.xacc
	3, // llvm.hexagon.S2.asl.i.vh
	3, // llvm.hexagon.S2.asl.i.vw
	3, // llvm.hexagon.S2.asl.r.p
	3, // llvm.hexagon.S2.asl.r.p.acc
	3, // llvm.hexagon.S2.asl.r.p.and
	3, // llvm.hexagon.S2.asl.r.p.nac
	3, // llvm.hexagon.S2.asl.r.p.or
	3, // llvm.hexagon.S2.asl.r.p.xor
	3, // llvm.hexagon.S2.asl.r.r
	3, // llvm.hexagon.S2.asl.r.r.acc
	3, // llvm.hexagon.S2.asl.r.r.and
	3, // llvm.hexagon.S2.asl.r.r.nac
	3, // llvm.hexagon.S2.asl.r.r.or
	3, // llvm.hexagon.S2.asl.r.r.sat
	3, // llvm.hexagon.S2.asl.r.vh
	3, // llvm.hexagon.S2.asl.r.vw
	3, // llvm.hexagon.S2.asr.i.p
	3, // llvm.hexagon.S2.asr.i.p.acc
	3, // llvm.hexagon.S2.asr.i.p.and
	3, // llvm.hexagon.S2.asr.i.p.nac
	3, // llvm.hexagon.S2.asr.i.p.or
	3, // llvm.hexagon.S2.asr.i.p.rnd
	3, // llvm.hexagon.S2.asr.i.p.rnd.goodsyntax
	3, // llvm.hexagon.S2.asr.i.r
	3, // llvm.hexagon.S2.asr.i.r.acc
	3, // llvm.hexagon.S2.asr.i.r.and
	3, // llvm.hexagon.S2.asr.i.r.nac
	3, // llvm.hexagon.S2.asr.i.r.or
	3, // llvm.hexagon.S2.asr.i.r.rnd
	3, // llvm.hexagon.S2.asr.i.r.rnd.goodsyntax
	3, // llvm.hexagon.S2.asr.i.svw.trun
	3, // llvm.hexagon.S2.asr.i.vh
	3, // llvm.hexagon.S2.asr.i.vw
	3, // llvm.hexagon.S2.asr.r.p
	3, // llvm.hexagon.S2.asr.r.p.acc
	3, // llvm.hexagon.S2.asr.r.p.and
	3, // llvm.hexagon.S2.asr.r.p.nac
	3, // llvm.hexagon.S2.asr.r.p.or
	3, // llvm.hexagon.S2.asr.r.p.xor
	3, // llvm.hexagon.S2.asr.r.r
	3, // llvm.hexagon.S2.asr.r.r.acc
	3, // llvm.hexagon.S2.asr.r.r.and
	3, // llvm.hexagon.S2.asr.r.r.nac
	3, // llvm.hexagon.S2.asr.r.r.or
	3, // llvm.hexagon.S2.asr.r.r.sat
	3, // llvm.hexagon.S2.asr.r.svw.trun
	3, // llvm.hexagon.S2.asr.r.vh
	3, // llvm.hexagon.S2.asr.r.vw
	3, // llvm.hexagon.S2.brev
	3, // llvm.hexagon.S2.brevp
	3, // llvm.hexagon.S2.cl0
	3, // llvm.hexagon.S2.cl0p
	3, // llvm.hexagon.S2.cl1
	3, // llvm.hexagon.S2.cl1p
	3, // llvm.hexagon.S2.clb
	3, // llvm.hexagon.S2.clbnorm
	3, // llvm.hexagon.S2.clbp
	3, // llvm.hexagon.S2.clrbit.i
	3, // llvm.hexagon.S2.clrbit.r
	3, // llvm.hexagon.S2.ct0
	3, // llvm.hexagon.S2.ct0p
	3, // llvm.hexagon.S2.ct1
	3, // llvm.hexagon.S2.ct1p
	3, // llvm.hexagon.S2.deinterleave
	3, // llvm.hexagon.S2.extractu
	3, // llvm.hexagon.S2.extractu.rp
	3, // llvm.hexagon.S2.extractup
	3, // llvm.hexagon.S2.extractup.rp
	3, // llvm.hexagon.S2.insert
	3, // llvm.hexagon.S2.insert.rp
	3, // llvm.hexagon.S2.insertp
	3, // llvm.hexagon.S2.insertp.rp
	3, // llvm.hexagon.S2.interleave
	3, // llvm.hexagon.S2.lfsp
	3, // llvm.hexagon.S2.lsl.r.p
	3, // llvm.hexagon.S2.lsl.r.p.acc
	3, // llvm.hexagon.S2.lsl.r.p.and
	3, // llvm.hexagon.S2.lsl.r.p.nac
	3, // llvm.hexagon.S2.lsl.r.p.or
	3, // llvm.hexagon.S2.lsl.r.p.xor
	3, // llvm.hexagon.S2.lsl.r.r
	3, // llvm.hexagon.S2.lsl.r.r.acc
	3, // llvm.hexagon.S2.lsl.r.r.and
	3, // llvm.hexagon.S2.lsl.r.r.nac
	3, // llvm.hexagon.S2.lsl.r.r.or
	3, // llvm.hexagon.S2.lsl.r.vh
	3, // llvm.hexagon.S2.lsl.r.vw
	3, // llvm.hexagon.S2.lsr.i.p
	3, // llvm.hexagon.S2.lsr.i.p.acc
	3, // llvm.hexagon.S2.lsr.i.p.and
	3, // llvm.hexagon.S2.lsr.i.p.nac
	3, // llvm.hexagon.S2.lsr.i.p.or
	3, // llvm.hexagon.S2.lsr.i.p.xacc
	3, // llvm.hexagon.S2.lsr.i.r
	3, // llvm.hexagon.S2.lsr.i.r.acc
	3, // llvm.hexagon.S2.lsr.i.r.and
	3, // llvm.hexagon.S2.lsr.i.r.nac
	3, // llvm.hexagon.S2.lsr.i.r.or
	3, // llvm.hexagon.S2.lsr.i.r.xacc
	3, // llvm.hexagon.S2.lsr.i.vh
	3, // llvm.hexagon.S2.lsr.i.vw
	3, // llvm.hexagon.S2.lsr.r.p
	3, // llvm.hexagon.S2.lsr.r.p.acc
	3, // llvm.hexagon.S2.lsr.r.p.and
	3, // llvm.hexagon.S2.lsr.r.p.nac
	3, // llvm.hexagon.S2.lsr.r.p.or
	3, // llvm.hexagon.S2.lsr.r.p.xor
	3, // llvm.hexagon.S2.lsr.r.r
	3, // llvm.hexagon.S2.lsr.r.r.acc
	3, // llvm.hexagon.S2.lsr.r.r.and
	3, // llvm.hexagon.S2.lsr.r.r.nac
	3, // llvm.hexagon.S2.lsr.r.r.or
	3, // llvm.hexagon.S2.lsr.r.vh
	3, // llvm.hexagon.S2.lsr.r.vw
	3, // llvm.hexagon.S2.packhl
	3, // llvm.hexagon.S2.parityp
	3, // llvm.hexagon.S2.setbit.i
	3, // llvm.hexagon.S2.setbit.r
	3, // llvm.hexagon.S2.shuffeb
	3, // llvm.hexagon.S2.shuffeh
	3, // llvm.hexagon.S2.shuffob
	3, // llvm.hexagon.S2.shuffoh
	3, // llvm.hexagon.S2.svsathb
	3, // llvm.hexagon.S2.svsathub
	3, // llvm.hexagon.S2.tableidxb.goodsyntax
	3, // llvm.hexagon.S2.tableidxd.goodsyntax
	3, // llvm.hexagon.S2.tableidxh.goodsyntax
	3, // llvm.hexagon.S2.tableidxw.goodsyntax
	3, // llvm.hexagon.S2.togglebit.i
	3, // llvm.hexagon.S2.togglebit.r
	3, // llvm.hexagon.S2.tstbit.i
	3, // llvm.hexagon.S2.tstbit.r
	3, // llvm.hexagon.S2.valignib
	3, // llvm.hexagon.S2.valignrb
	3, // llvm.hexagon.S2.vcnegh
	3, // llvm.hexagon.S2.vcrotate
	3, // llvm.hexagon.S2.vrcnegh
	3, // llvm.hexagon.S2.vrndpackwh
	3, // llvm.hexagon.S2.vrndpackwhs
	3, // llvm.hexagon.S2.vsathb
	3, // llvm.hexagon.S2.vsathb.nopack
	3, // llvm.hexagon.S2.vsathub
	3, // llvm.hexagon.S2.vsathub.nopack
	3, // llvm.hexagon.S2.vsatwh
	3, // llvm.hexagon.S2.vsatwh.nopack
	3, // llvm.hexagon.S2.vsatwuh
	3, // llvm.hexagon.S2.vsatwuh.nopack
	3, // llvm.hexagon.S2.vsplatrb
	3, // llvm.hexagon.S2.vsplatrh
	3, // llvm.hexagon.S2.vspliceib
	3, // llvm.hexagon.S2.vsplicerb
	3, // llvm.hexagon.S2.vsxtbh
	3, // llvm.hexagon.S2.vsxthw
	3, // llvm.hexagon.S2.vtrunehb
	3, // llvm.hexagon.S2.vtrunewh
	3, // llvm.hexagon.S2.vtrunohb
	3, // llvm.hexagon.S2.vtrunowh
	3, // llvm.hexagon.S2.vzxtbh
	3, // llvm.hexagon.S2.vzxthw
	3, // llvm.hexagon.S4.addaddi
	3, // llvm.hexagon.S4.addi.asl.ri
	3, // llvm.hexagon.S4.addi.lsr.ri
	3, // llvm.hexagon.S4.andi.asl.ri
	3, // llvm.hexagon.S4.andi.lsr.ri
	3, // llvm.hexagon.S4.clbaddi
	3, // llvm.hexagon.S4.clbpaddi
	3, // llvm.hexagon.S4.clbpnorm
	3, // llvm.hexagon.S4.extract
	3, // llvm.hexagon.S4.extract.rp
	3, // llvm.hexagon.S4.extractp
	3, // llvm.hexagon.S4.extractp.rp
	3, // llvm.hexagon.S4.lsli
	3, // llvm.hexagon.S4.ntstbit.i
	3, // llvm.hexagon.S4.ntstbit.r
	3, // llvm.hexagon.S4.or.andi
	3, // llvm.hexagon.S4.or.andix
	3, // llvm.hexagon.S4.or.ori
	3, // llvm.hexagon.S4.ori.asl.ri
	3, // llvm.hexagon.S4.ori.lsr.ri
	3, // llvm.hexagon.S4.parity
	3, // llvm.hexagon.S4.subaddi
	3, // llvm.hexagon.S4.subi.asl.ri
	3, // llvm.hexagon.S4.subi.lsr.ri
	3, // llvm.hexagon.S4.vrcrotate
	3, // llvm.hexagon.S4.vrcrotate.acc
	3, // llvm.hexagon.S4.vxaddsubh
	3, // llvm.hexagon.S4.vxaddsubhr
	3, // llvm.hexagon.S4.vxaddsubw
	3, // llvm.hexagon.S4.vxsubaddh
	3, // llvm.hexagon.S4.vxsubaddhr
	3, // llvm.hexagon.S4.vxsubaddw
	3, // llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax
	3, // llvm.hexagon.S5.asrhub.sat
	3, // llvm.hexagon.S5.popcountp
	3, // llvm.hexagon.S5.vasrhrnd.goodsyntax
	3, // llvm.hexagon.SI.to.SXTHI.asrh
	2, // llvm.hexagon.circ.ldd
	6, // llvm.init.trampoline
	7, // llvm.invariant.end
	8, // llvm.invariant.start
	8, // llvm.lifetime.end
	8, // llvm.lifetime.start
	1, // llvm.log
	1, // llvm.log10
	1, // llvm.log2
	4, // llvm.longjmp
	9, // llvm.memcpy
	9, // llvm.memmove
	6, // llvm.memset
	2, // llvm.mips.absq.s.ph
	2, // llvm.mips.absq.s.qb
	2, // llvm.mips.absq.s.w
	2, // llvm.mips.addq.ph
	2, // llvm.mips.addq.s.ph
	2, // llvm.mips.addq.s.w
	3, // llvm.mips.addqh.ph
	3, // llvm.mips.addqh.r.ph
	3, // llvm.mips.addqh.r.w
	3, // llvm.mips.addqh.w
	2, // llvm.mips.addsc
	2, // llvm.mips.addu.ph
	2, // llvm.mips.addu.qb
	2, // llvm.mips.addu.s.ph
	2, // llvm.mips.addu.s.qb
	3, // llvm.mips.adduh.qb
	3, // llvm.mips.adduh.r.qb
	2, // llvm.mips.addwc
	3, // llvm.mips.append
	3, // llvm.mips.balign
	3, // llvm.mips.bitrev
	1, // llvm.mips.bposge32
	2, // llvm.mips.cmp.eq.ph
	2, // llvm.mips.cmp.le.ph
	2, // llvm.mips.cmp.lt.ph
	2, // llvm.mips.cmpgdu.eq.qb
	2, // llvm.mips.cmpgdu.le.qb
	2, // llvm.mips.cmpgdu.lt.qb
	2, // llvm.mips.cmpgu.eq.qb
	2, // llvm.mips.cmpgu.le.qb
	2, // llvm.mips.cmpgu.lt.qb
	2, // llvm.mips.cmpu.eq.qb
	2, // llvm.mips.cmpu.le.qb
	2, // llvm.mips.cmpu.lt.qb
	3, // llvm.mips.dpa.w.ph
	2, // llvm.mips.dpaq.s.w.ph
	2, // llvm.mips.dpaq.sa.l.w
	2, // llvm.mips.dpaqx.s.w.ph
	2, // llvm.mips.dpaqx.sa.w.ph
	3, // llvm.mips.dpau.h.qbl
	3, // llvm.mips.dpau.h.qbr
	3, // llvm.mips.dpax.w.ph
	3, // llvm.mips.dps.w.ph
	2, // llvm.mips.dpsq.s.w.ph
	2, // llvm.mips.dpsq.sa.l.w
	2, // llvm.mips.dpsqx.s.w.ph
	2, // llvm.mips.dpsqx.sa.w.ph
	3, // llvm.mips.dpsu.h.qbl
	3, // llvm.mips.dpsu.h.qbr
	3, // llvm.mips.dpsx.w.ph
	2, // llvm.mips.extp
	2, // llvm.mips.extpdp
	2, // llvm.mips.extr.r.w
	2, // llvm.mips.extr.rs.w
	2, // llvm.mips.extr.s.h
	2, // llvm.mips.extr.w
	1, // llvm.mips.insv
	1, // llvm.mips.lbux
	1, // llvm.mips.lhx
	1, // llvm.mips.lwx
	3, // llvm.mips.madd
	3, // llvm.mips.maddu
	2, // llvm.mips.maq.s.w.phl
	2, // llvm.mips.maq.s.w.phr
	2, // llvm.mips.maq.sa.w.phl
	2, // llvm.mips.maq.sa.w.phr
	3, // llvm.mips.modsub
	3, // llvm.mips.msub
	3, // llvm.mips.msubu
	2, // llvm.mips.mthlip
	2, // llvm.mips.mul.ph
	2, // llvm.mips.mul.s.ph
	2, // llvm.mips.muleq.s.w.phl
	2, // llvm.mips.muleq.s.w.phr
	2, // llvm.mips.muleu.s.ph.qbl
	2, // llvm.mips.muleu.s.ph.qbr
	2, // llvm.mips.mulq.rs.ph
	2, // llvm.mips.mulq.rs.w
	2, // llvm.mips.mulq.s.ph
	2, // llvm.mips.mulq.s.w
	3, // llvm.mips.mulsa.w.ph
	2, // llvm.mips.mulsaq.s.w.ph
	3, // llvm.mips.mult
	3, // llvm.mips.multu
	3, // llvm.mips.packrl.ph
	1, // llvm.mips.pick.ph
	1, // llvm.mips.pick.qb
	3, // llvm.mips.preceq.w.phl
	3, // llvm.mips.preceq.w.phr
	3, // llvm.mips.precequ.ph.qbl
	3, // llvm.mips.precequ.ph.qbla
	3, // llvm.mips.precequ.ph.qbr
	3, // llvm.mips.precequ.ph.qbra
	3, // llvm.mips.preceu.ph.qbl
	3, // llvm.mips.preceu.ph.qbla
	3, // llvm.mips.preceu.ph.qbr
	3, // llvm.mips.preceu.ph.qbra
	2, // llvm.mips.precr.qb.ph
	3, // llvm.mips.precr.sra.ph.w
	3, // llvm.mips.precr.sra.r.ph.w
	3, // llvm.mips.precrq.ph.w
	3, // llvm.mips.precrq.qb.ph
	2, // llvm.mips.precrq.rs.ph.w
	2, // llvm.mips.precrqu.s.qb.ph
	3, // llvm.mips.prepend
	3, // llvm.mips.raddu.w.qb
	1, // llvm.mips.rddsp
	3, // llvm.mips.repl.ph
	3, // llvm.mips.repl.qb
	3, // llvm.mips.shilo
	2, // llvm.mips.shll.ph
	2, // llvm.mips.shll.qb
	2, // llvm.mips.shll.s.ph
	2, // llvm.mips.shll.s.w
	3, // llvm.mips.shra.ph
	3, // llvm.mips.shra.qb
	3, // llvm.mips.shra.r.ph
	3, // llvm.mips.shra.r.qb
	3, // llvm.mips.shra.r.w
	3, // llvm.mips.shrl.ph
	3, // llvm.mips.shrl.qb
	2, // llvm.mips.subq.ph
	2, // llvm.mips.subq.s.ph
	2, // llvm.mips.subq.s.w
	3, // llvm.mips.subqh.ph
	3, // llvm.mips.subqh.r.ph
	3, // llvm.mips.subqh.r.w
	3, // llvm.mips.subqh.w
	2, // llvm.mips.subu.ph
	2, // llvm.mips.subu.qb
	2, // llvm.mips.subu.s.ph
	2, // llvm.mips.subu.s.qb
	3, // llvm.mips.subuh.qb
	3, // llvm.mips.subuh.r.qb
	2, // llvm.mips.wrdsp
	1, // llvm.nearbyint
	3, // llvm.nvvm.abs.i
	3, // llvm.nvvm.abs.ll
	3, // llvm.nvvm.add.rm.d
	3, // llvm.nvvm.add.rm.f
	3, // llvm.nvvm.add.rm.ftz.f
	3, // llvm.nvvm.add.rn.d
	3, // llvm.nvvm.add.rn.f
	3, // llvm.nvvm.add.rn.ftz.f
	3, // llvm.nvvm.add.rp.d
	3, // llvm.nvvm.add.rp.f
	3, // llvm.nvvm.add.rp.ftz.f
	3, // llvm.nvvm.add.rz.d
	3, // llvm.nvvm.add.rz.f
	3, // llvm.nvvm.add.rz.ftz.f
	6, // llvm.nvvm.atomic.load.add.f32
	6, // llvm.nvvm.atomic.load.dec.32
	6, // llvm.nvvm.atomic.load.inc.32
	2, // llvm.nvvm.barrier0
	2, // llvm.nvvm.barrier0.and
	2, // llvm.nvvm.barrier0.or
	2, // llvm.nvvm.barrier0.popc
	3, // llvm.nvvm.bitcast.d2ll
	3, // llvm.nvvm.bitcast.f2i
	3, // llvm.nvvm.bitcast.i2f
	3, // llvm.nvvm.bitcast.ll2d
	3, // llvm.nvvm.brev32
	3, // llvm.nvvm.brev64
	3, // llvm.nvvm.ceil.d
	3, // llvm.nvvm.ceil.f
	3, // llvm.nvvm.ceil.ftz.f
	3, // llvm.nvvm.clz.i
	3, // llvm.nvvm.clz.ll
	2, // llvm.nvvm.compiler.error
	2, // llvm.nvvm.compiler.warn
	3, // llvm.nvvm.cos.approx.f
	3, // llvm.nvvm.cos.approx.ftz.f
	3, // llvm.nvvm.d2f.rm
	3, // llvm.nvvm.d2f.rm.ftz
	3, // llvm.nvvm.d2f.rn
	3, // llvm.nvvm.d2f.rn.ftz
	3, // llvm.nvvm.d2f.rp
	3, // llvm.nvvm.d2f.rp.ftz
	3, // llvm.nvvm.d2f.rz
	3, // llvm.nvvm.d2f.rz.ftz
	3, // llvm.nvvm.d2i.hi
	3, // llvm.nvvm.d2i.lo
	3, // llvm.nvvm.d2i.rm
	3, // llvm.nvvm.d2i.rn
	3, // llvm.nvvm.d2i.rp
	3, // llvm.nvvm.d2i.rz
	3, // llvm.nvvm.d2ll.rm
	3, // llvm.nvvm.d2ll.rn
	3, // llvm.nvvm.d2ll.rp
	3, // llvm.nvvm.d2ll.rz
	3, // llvm.nvvm.d2ui.rm
	3, // llvm.nvvm.d2ui.rn
	3, // llvm.nvvm.d2ui.rp
	3, // llvm.nvvm.d2ui.rz
	3, // llvm.nvvm.d2ull.rm
	3, // llvm.nvvm.d2ull.rn
	3, // llvm.nvvm.d2ull.rp
	3, // llvm.nvvm.d2ull.rz
	3, // llvm.nvvm.div.approx.f
	3, // llvm.nvvm.div.approx.ftz.f
	3, // llvm.nvvm.div.rm.d
	3, // llvm.nvvm.div.rm.f
	3, // llvm.nvvm.div.rm.ftz.f
	3, // llvm.nvvm.div.rn.d
	3, // llvm.nvvm.div.rn.f
	3, // llvm.nvvm.div.rn.ftz.f
	3, // llvm.nvvm.div.rp.d
	3, // llvm.nvvm.div.rp.f
	3, // llvm.nvvm.div.rp.ftz.f
	3, // llvm.nvvm.div.rz.d
	3, // llvm.nvvm.div.rz.f
	3, // llvm.nvvm.div.rz.ftz.f
	3, // llvm.nvvm.ex2.approx.d
	3, // llvm.nvvm.ex2.approx.f
	3, // llvm.nvvm.ex2.approx.ftz.f
	3, // llvm.nvvm.f2h.rn
	3, // llvm.nvvm.f2h.rn.ftz
	3, // llvm.nvvm.f2i.rm
	3, // llvm.nvvm.f2i.rm.ftz
	3, // llvm.nvvm.f2i.rn
	3, // llvm.nvvm.f2i.rn.ftz
	3, // llvm.nvvm.f2i.rp
	3, // llvm.nvvm.f2i.rp.ftz
	3, // llvm.nvvm.f2i.rz
	3, // llvm.nvvm.f2i.rz.ftz
	3, // llvm.nvvm.f2ll.rm
	3, // llvm.nvvm.f2ll.rm.ftz
	3, // llvm.nvvm.f2ll.rn
	3, // llvm.nvvm.f2ll.rn.ftz
	3, // llvm.nvvm.f2ll.rp
	3, // llvm.nvvm.f2ll.rp.ftz
	3, // llvm.nvvm.f2ll.rz
	3, // llvm.nvvm.f2ll.rz.ftz
	3, // llvm.nvvm.f2ui.rm
	3, // llvm.nvvm.f2ui.rm.ftz
	3, // llvm.nvvm.f2ui.rn
	3, // llvm.nvvm.f2ui.rn.ftz
	3, // llvm.nvvm.f2ui.rp
	3, // llvm.nvvm.f2ui.rp.ftz
	3, // llvm.nvvm.f2ui.rz
	3, // llvm.nvvm.f2ui.rz.ftz
	3, // llvm.nvvm.f2ull.rm
	3, // llvm.nvvm.f2ull.rm.ftz
	3, // llvm.nvvm.f2ull.rn
	3, // llvm.nvvm.f2ull.rn.ftz
	3, // llvm.nvvm.f2ull.rp
	3, // llvm.nvvm.f2ull.rp.ftz
	3, // llvm.nvvm.f2ull.rz
	3, // llvm.nvvm.f2ull.rz.ftz
	3, // llvm.nvvm.fabs.d
	3, // llvm.nvvm.fabs.f
	3, // llvm.nvvm.fabs.ftz.f
	3, // llvm.nvvm.floor.d
	3, // llvm.nvvm.floor.f
	3, // llvm.nvvm.floor.ftz.f
	3, // llvm.nvvm.fma.rm.d
	3, // llvm.nvvm.fma.rm.f
	3, // llvm.nvvm.fma.rm.ftz.f
	3, // llvm.nvvm.fma.rn.d
	3, // llvm.nvvm.fma.rn.f
	3, // llvm.nvvm.fma.rn.ftz.f
	3, // llvm.nvvm.fma.rp.d
	3, // llvm.nvvm.fma.rp.f
	3, // llvm.nvvm.fma.rp.ftz.f
	3, // llvm.nvvm.fma.rz.d
	3, // llvm.nvvm.fma.rz.f
	3, // llvm.nvvm.fma.rz.ftz.f
	3, // llvm.nvvm.fmax.d
	3, // llvm.nvvm.fmax.f
	3, // llvm.nvvm.fmax.ftz.f
	3, // llvm.nvvm.fmin.d
	3, // llvm.nvvm.fmin.f
	3, // llvm.nvvm.fmin.ftz.f
	3, // llvm.nvvm.h2f
	3, // llvm.nvvm.i2d.rm
	3, // llvm.nvvm.i2d.rn
	3, // llvm.nvvm.i2d.rp
	3, // llvm.nvvm.i2d.rz
	3, // llvm.nvvm.i2f.rm
	3, // llvm.nvvm.i2f.rn
	3, // llvm.nvvm.i2f.rp
	3, // llvm.nvvm.i2f.rz
	10, // llvm.nvvm.ldg.global.f
	10, // llvm.nvvm.ldg.global.i
	10, // llvm.nvvm.ldg.global.p
	10, // llvm.nvvm.ldu.global.f
	10, // llvm.nvvm.ldu.global.i
	10, // llvm.nvvm.ldu.global.p
	3, // llvm.nvvm.lg2.approx.d
	3, // llvm.nvvm.lg2.approx.f
	3, // llvm.nvvm.lg2.approx.ftz.f
	3, // llvm.nvvm.ll2d.rm
	3, // llvm.nvvm.ll2d.rn
	3, // llvm.nvvm.ll2d.rp
	3, // llvm.nvvm.ll2d.rz
	3, // llvm.nvvm.ll2f.rm
	3, // llvm.nvvm.ll2f.rn
	3, // llvm.nvvm.ll2f.rp
	3, // llvm.nvvm.ll2f.rz
	3, // llvm.nvvm.lohi.i2d
	3, // llvm.nvvm.max.i
	3, // llvm.nvvm.max.ll
	3, // llvm.nvvm.max.ui
	3, // llvm.nvvm.max.ull
	2, // llvm.nvvm.membar.cta
	2, // llvm.nvvm.membar.gl
	2, // llvm.nvvm.membar.sys
	3, // llvm.nvvm.min.i
	3, // llvm.nvvm.min.ll
	3, // llvm.nvvm.min.ui
	3, // llvm.nvvm.min.ull
	3, // llvm.nvvm.move.double
	3, // llvm.nvvm.move.float
	3, // llvm.nvvm.move.i16
	3, // llvm.nvvm.move.i32
	3, // llvm.nvvm.move.i64
	3, // llvm.nvvm.move.i8
	11, // llvm.nvvm.move.ptr
	3, // llvm.nvvm.mul24.i
	3, // llvm.nvvm.mul24.ui
	3, // llvm.nvvm.mul.rm.d
	3, // llvm.nvvm.mul.rm.f
	3, // llvm.nvvm.mul.rm.ftz.f
	3, // llvm.nvvm.mul.rn.d
	3, // llvm.nvvm.mul.rn.f
	3, // llvm.nvvm.mul.rn.ftz.f
	3, // llvm.nvvm.mul.rp.d
	3, // llvm.nvvm.mul.rp.f
	3, // llvm.nvvm.mul.rp.ftz.f
	3, // llvm.nvvm.mul.rz.d
	3, // llvm.nvvm.mul.rz.f
	3, // llvm.nvvm.mul.rz.ftz.f
	3, // llvm.nvvm.mulhi.i
	3, // llvm.nvvm.mulhi.ll
	3, // llvm.nvvm.mulhi.ui
	3, // llvm.nvvm.mulhi.ull
	3, // llvm.nvvm.popc.i
	3, // llvm.nvvm.popc.ll
	3, // llvm.nvvm.prmt
	3, // llvm.nvvm.ptr.constant.to.gen
	3, // llvm.nvvm.ptr.gen.to.constant
	3, // llvm.nvvm.ptr.gen.to.global
	3, // llvm.nvvm.ptr.gen.to.local
	3, // llvm.nvvm.ptr.gen.to.param
	3, // llvm.nvvm.ptr.gen.to.shared
	3, // llvm.nvvm.ptr.global.to.gen
	3, // llvm.nvvm.ptr.local.to.gen
	3, // llvm.nvvm.ptr.shared.to.gen
	3, // llvm.nvvm.rcp.approx.ftz.d
	3, // llvm.nvvm.rcp.rm.d
	3, // llvm.nvvm.rcp.rm.f
	3, // llvm.nvvm.rcp.rm.ftz.f
	3, // llvm.nvvm.rcp.rn.d
	3, // llvm.nvvm.rcp.rn.f
	3, // llvm.nvvm.rcp.rn.ftz.f
	3, // llvm.nvvm.rcp.rp.d
	3, // llvm.nvvm.rcp.rp.f
	3, // llvm.nvvm.rcp.rp.ftz.f
	3, // llvm.nvvm.rcp.rz.d
	3, // llvm.nvvm.rcp.rz.f
	3, // llvm.nvvm.rcp.rz.ftz.f
	3, // llvm.nvvm.read.ptx.sreg.ctaid.x
	3, // llvm.nvvm.read.ptx.sreg.ctaid.y
	3, // llvm.nvvm.read.ptx.sreg.ctaid.z
	3, // llvm.nvvm.read.ptx.sreg.nctaid.x
	3, // llvm.nvvm.read.ptx.sreg.nctaid.y
	3, // llvm.nvvm.read.ptx.sreg.nctaid.z
	3, // llvm.nvvm.read.ptx.sreg.ntid.x
	3, // llvm.nvvm.read.ptx.sreg.ntid.y
	3, // llvm.nvvm.read.ptx.sreg.ntid.z
	3, // llvm.nvvm.read.ptx.sreg.tid.x
	3, // llvm.nvvm.read.ptx.sreg.tid.y
	3, // llvm.nvvm.read.ptx.sreg.tid.z
	3, // llvm.nvvm.read.ptx.sreg.warpsize
	3, // llvm.nvvm.round.d
	3, // llvm.nvvm.round.f
	3, // llvm.nvvm.round.ftz.f
	3, // llvm.nvvm.rsqrt.approx.d
	3, // llvm.nvvm.rsqrt.approx.f
	3, // llvm.nvvm.rsqrt.approx.ftz.f
	3, // llvm.nvvm.sad.i
	3, // llvm.nvvm.sad.ui
	3, // llvm.nvvm.saturate.d
	3, // llvm.nvvm.saturate.f
	3, // llvm.nvvm.saturate.ftz.f
	3, // llvm.nvvm.sin.approx.f
	3, // llvm.nvvm.sin.approx.ftz.f
	3, // llvm.nvvm.sqrt.approx.f
	3, // llvm.nvvm.sqrt.approx.ftz.f
	3, // llvm.nvvm.sqrt.f
	3, // llvm.nvvm.sqrt.rm.d
	3, // llvm.nvvm.sqrt.rm.f
	3, // llvm.nvvm.sqrt.rm.ftz.f
	3, // llvm.nvvm.sqrt.rn.d
	3, // llvm.nvvm.sqrt.rn.f
	3, // llvm.nvvm.sqrt.rn.ftz.f
	3, // llvm.nvvm.sqrt.rp.d
	3, // llvm.nvvm.sqrt.rp.f
	3, // llvm.nvvm.sqrt.rp.ftz.f
	3, // llvm.nvvm.sqrt.rz.d
	3, // llvm.nvvm.sqrt.rz.f
	3, // llvm.nvvm.sqrt.rz.ftz.f
	3, // llvm.nvvm.trunc.d
	3, // llvm.nvvm.trunc.f
	3, // llvm.nvvm.trunc.ftz.f
	3, // llvm.nvvm.ui2d.rm
	3, // llvm.nvvm.ui2d.rn
	3, // llvm.nvvm.ui2d.rp
	3, // llvm.nvvm.ui2d.rz
	3, // llvm.nvvm.ui2f.rm
	3, // llvm.nvvm.ui2f.rn
	3, // llvm.nvvm.ui2f.rp
	3, // llvm.nvvm.ui2f.rz
	3, // llvm.nvvm.ull2d.rm
	3, // llvm.nvvm.ull2d.rn
	3, // llvm.nvvm.ull2d.rp
	3, // llvm.nvvm.ull2d.rz
	3, // llvm.nvvm.ull2f.rm
	3, // llvm.nvvm.ull2f.rn
	3, // llvm.nvvm.ull2f.rp
	3, // llvm.nvvm.ull2f.rz
	3, // llvm.objectsize
	2, // llvm.pcmarker
	1, // llvm.pow
	1, // llvm.powi
	2, // llvm.ppc.altivec.dss
	2, // llvm.ppc.altivec.dssall
	2, // llvm.ppc.altivec.dst
	2, // llvm.ppc.altivec.dstst
	2, // llvm.ppc.altivec.dststt
	2, // llvm.ppc.altivec.dstt
	1, // llvm.ppc.altivec.lvebx
	1, // llvm.ppc.altivec.lvehx
	1, // llvm.ppc.altivec.lvewx
	3, // llvm.ppc.altivec.lvsl
	3, // llvm.ppc.altivec.lvsr
	1, // llvm.ppc.altivec.lvx
	1, // llvm.ppc.altivec.lvxl
	1, // llvm.ppc.altivec.mfvscr
	2, // llvm.ppc.altivec.mtvscr
	2, // llvm.ppc.altivec.stvebx
	2, // llvm.ppc.altivec.stvehx
	2, // llvm.ppc.altivec.stvewx
	2, // llvm.ppc.altivec.stvx
	2, // llvm.ppc.altivec.stvxl
	3, // llvm.ppc.altivec.vaddcuw
	3, // llvm.ppc.altivec.vaddsbs
	3, // llvm.ppc.altivec.vaddshs
	3, // llvm.ppc.altivec.vaddsws
	3, // llvm.ppc.altivec.vaddubs
	3, // llvm.ppc.altivec.vadduhs
	3, // llvm.ppc.altivec.vadduws
	3, // llvm.ppc.altivec.vavgsb
	3, // llvm.ppc.altivec.vavgsh
	3, // llvm.ppc.altivec.vavgsw
	3, // llvm.ppc.altivec.vavgub
	3, // llvm.ppc.altivec.vavguh
	3, // llvm.ppc.altivec.vavguw
	3, // llvm.ppc.altivec.vcfsx
	3, // llvm.ppc.altivec.vcfux
	3, // llvm.ppc.altivec.vcmpbfp
	3, // llvm.ppc.altivec.vcmpbfp.p
	3, // llvm.ppc.altivec.vcmpeqfp
	3, // llvm.ppc.altivec.vcmpeqfp.p
	3, // llvm.ppc.altivec.vcmpequb
	3, // llvm.ppc.altivec.vcmpequb.p
	3, // llvm.ppc.altivec.vcmpequh
	3, // llvm.ppc.altivec.vcmpequh.p
	3, // llvm.ppc.altivec.vcmpequw
	3, // llvm.ppc.altivec.vcmpequw.p
	3, // llvm.ppc.altivec.vcmpgefp
	3, // llvm.ppc.altivec.vcmpgefp.p
	3, // llvm.ppc.altivec.vcmpgtfp
	3, // llvm.ppc.altivec.vcmpgtfp.p
	3, // llvm.ppc.altivec.vcmpgtsb
	3, // llvm.ppc.altivec.vcmpgtsb.p
	3, // llvm.ppc.altivec.vcmpgtsh
	3, // llvm.ppc.altivec.vcmpgtsh.p
	3, // llvm.ppc.altivec.vcmpgtsw
	3, // llvm.ppc.altivec.vcmpgtsw.p
	3, // llvm.ppc.altivec.vcmpgtub
	3, // llvm.ppc.altivec.vcmpgtub.p
	3, // llvm.ppc.altivec.vcmpgtuh
	3, // llvm.ppc.altivec.vcmpgtuh.p
	3, // llvm.ppc.altivec.vcmpgtuw
	3, // llvm.ppc.altivec.vcmpgtuw.p
	3, // llvm.ppc.altivec.vctsxs
	3, // llvm.ppc.altivec.vctuxs
	3, // llvm.ppc.altivec.vexptefp
	3, // llvm.ppc.altivec.vlogefp
	3, // llvm.ppc.altivec.vmaddfp
	3, // llvm.ppc.altivec.vmaxfp
	3, // llvm.ppc.altivec.vmaxsb
	3, // llvm.ppc.altivec.vmaxsh
	3, // llvm.ppc.altivec.vmaxsw
	3, // llvm.ppc.altivec.vmaxub
	3, // llvm.ppc.altivec.vmaxuh
	3, // llvm.ppc.altivec.vmaxuw
	3, // llvm.ppc.altivec.vmhaddshs
	3, // llvm.ppc.altivec.vmhraddshs
	3, // llvm.ppc.altivec.vminfp
	3, // llvm.ppc.altivec.vminsb
	3, // llvm.ppc.altivec.vminsh
	3, // llvm.ppc.altivec.vminsw
	3, // llvm.ppc.altivec.vminub
	3, // llvm.ppc.altivec.vminuh
	3, // llvm.ppc.altivec.vminuw
	3, // llvm.ppc.altivec.vmladduhm
	3, // llvm.ppc.altivec.vmsummbm
	3, // llvm.ppc.altivec.vmsumshm
	3, // llvm.ppc.altivec.vmsumshs
	3, // llvm.ppc.altivec.vmsumubm
	3, // llvm.ppc.altivec.vmsumuhm
	3, // llvm.ppc.altivec.vmsumuhs
	3, // llvm.ppc.altivec.vmulesb
	3, // llvm.ppc.altivec.vmulesh
	3, // llvm.ppc.altivec.vmuleub
	3, // llvm.ppc.altivec.vmuleuh
	3, // llvm.ppc.altivec.vmulosb
	3, // llvm.ppc.altivec.vmulosh
	3, // llvm.ppc.altivec.vmuloub
	3, // llvm.ppc.altivec.vmulouh
	3, // llvm.ppc.altivec.vnmsubfp
	3, // llvm.ppc.altivec.vperm
	3, // llvm.ppc.altivec.vpkpx
	3, // llvm.ppc.altivec.vpkshss
	3, // llvm.ppc.altivec.vpkshus
	3, // llvm.ppc.altivec.vpkswss
	3, // llvm.ppc.altivec.vpkswus
	3, // llvm.ppc.altivec.vpkuhus
	3, // llvm.ppc.altivec.vpkuwus
	3, // llvm.ppc.altivec.vrefp
	3, // llvm.ppc.altivec.vrfim
	3, // llvm.ppc.altivec.vrfin
	3, // llvm.ppc.altivec.vrfip
	3, // llvm.ppc.altivec.vrfiz
	3, // llvm.ppc.altivec.vrlb
	3, // llvm.ppc.altivec.vrlh
	3, // llvm.ppc.altivec.vrlw
	3, // llvm.ppc.altivec.vrsqrtefp
	3, // llvm.ppc.altivec.vsel
	3, // llvm.ppc.altivec.vsl
	3, // llvm.ppc.altivec.vslb
	3, // llvm.ppc.altivec.vslh
	3, // llvm.ppc.altivec.vslo
	3, // llvm.ppc.altivec.vslw
	3, // llvm.ppc.altivec.vsr
	3, // llvm.ppc.altivec.vsrab
	3, // llvm.ppc.altivec.vsrah
	3, // llvm.ppc.altivec.vsraw
	3, // llvm.ppc.altivec.vsrb
	3, // llvm.ppc.altivec.vsrh
	3, // llvm.ppc.altivec.vsro
	3, // llvm.ppc.altivec.vsrw
	3, // llvm.ppc.altivec.vsubcuw
	3, // llvm.ppc.altivec.vsubsbs
	3, // llvm.ppc.altivec.vsubshs
	3, // llvm.ppc.altivec.vsubsws
	3, // llvm.ppc.altivec.vsububs
	3, // llvm.ppc.altivec.vsubuhs
	3, // llvm.ppc.altivec.vsubuws
	3, // llvm.ppc.altivec.vsum2sws
	3, // llvm.ppc.altivec.vsum4sbs
	3, // llvm.ppc.altivec.vsum4shs
	3, // llvm.ppc.altivec.vsum4ubs
	3, // llvm.ppc.altivec.vsumsws
	3, // llvm.ppc.altivec.vupkhpx
	3, // llvm.ppc.altivec.vupkhsb
	3, // llvm.ppc.altivec.vupkhsh
	3, // llvm.ppc.altivec.vupklpx
	3, // llvm.ppc.altivec.vupklsb
	3, // llvm.ppc.altivec.vupklsh
	2, // llvm.ppc.dcba
	2, // llvm.ppc.dcbf
	2, // llvm.ppc.dcbi
	2, // llvm.ppc.dcbst
	6, // llvm.ppc.dcbt
	2, // llvm.ppc.dcbtst
	2, // llvm.ppc.dcbz
	2, // llvm.ppc.dcbzl
	2, // llvm.ppc.sync
	6, // llvm.prefetch
	2, // llvm.ptr.annotation
	2, // llvm.ptx.bar.sync
	3, // llvm.ptx.read.clock
	3, // llvm.ptx.read.clock64
	3, // llvm.ptx.read.ctaid.w
	3, // llvm.ptx.read.ctaid.x
	3, // llvm.ptx.read.ctaid.y
	3, // llvm.ptx.read.ctaid.z
	3, // llvm.ptx.read.gridid
	3, // llvm.ptx.read.laneid
	3, // llvm.ptx.read.lanemask.eq
	3, // llvm.ptx.read.lanemask.ge
	3, // llvm.ptx.read.lanemask.gt
	3, // llvm.ptx.read.lanemask.le
	3, // llvm.ptx.read.lanemask.lt
	3, // llvm.ptx.read.nctaid.w
	3, // llvm.ptx.read.nctaid.x
	3, // llvm.ptx.read.nctaid.y
	3, // llvm.ptx.read.nctaid.z
	3, // llvm.ptx.read.nsmid
	3, // llvm.ptx.read.ntid.w
	3, // llvm.ptx.read.ntid.x
	3, // llvm.ptx.read.ntid.y
	3, // llvm.ptx.read.ntid.z
	3, // llvm.ptx.read.nwarpid
	3, // llvm.ptx.read.pm0
	3, // llvm.ptx.read.pm1
	3, // llvm.ptx.read.pm2
	3, // llvm.ptx.read.pm3
	3, // llvm.ptx.read.smid
	3, // llvm.ptx.read.tid.w
	3, // llvm.ptx.read.tid.x
	3, // llvm.ptx.read.tid.y
	3, // llvm.ptx.read.tid.z
	3, // llvm.ptx.read.warpid
	3, // llvm.r600.read.global.size.x
	3, // llvm.r600.read.global.size.y
	3, // llvm.r600.read.global.size.z
	3, // llvm.r600.read.local.size.x
	3, // llvm.r600.read.local.size.y
	3, // llvm.r600.read.local.size.z
	3, // llvm.r600.read.ngroups.x
	3, // llvm.r600.read.ngroups.y
	3, // llvm.r600.read.ngroups.z
	3, // llvm.r600.read.tgid.x
	3, // llvm.r600.read.tgid.y
	3, // llvm.r600.read.tgid.z
	3, // llvm.r600.read.tidig.x
	3, // llvm.r600.read.tidig.y
	3, // llvm.r600.read.tidig.z
	2, // llvm.readcyclecounter
	3, // llvm.returnaddress
	1, // llvm.rint
	3, // llvm.sadd.with.overflow
	2, // llvm.setjmp
	4, // llvm.siglongjmp
	2, // llvm.sigsetjmp
	1, // llvm.sin
	3, // llvm.smul.with.overflow
	1, // llvm.sqrt
	3, // llvm.ssub.with.overflow
	2, // llvm.stackprotector
	2, // llvm.stackrestore
	2, // llvm.stacksave
	4, // llvm.trap
	1, // llvm.trunc
	3, // llvm.uadd.with.overflow
	3, // llvm.umul.with.overflow
	3, // llvm.usub.with.overflow
	2, // llvm.va_copy
	2, // llvm.va_end
	2, // llvm.var.annotation
	2, // llvm.va_start
	3, // llvm.x86.3dnow.pavgusb
	3, // llvm.x86.3dnow.pf2id
	3, // llvm.x86.3dnow.pfacc
	3, // llvm.x86.3dnow.pfadd
	3, // llvm.x86.3dnow.pfcmpeq
	3, // llvm.x86.3dnow.pfcmpge
	3, // llvm.x86.3dnow.pfcmpgt
	3, // llvm.x86.3dnow.pfmax
	3, // llvm.x86.3dnow.pfmin
	3, // llvm.x86.3dnow.pfmul
	3, // llvm.x86.3dnow.pfrcp
	3, // llvm.x86.3dnow.pfrcpit1
	3, // llvm.x86.3dnow.pfrcpit2
	3, // llvm.x86.3dnow.pfrsqit1
	3, // llvm.x86.3dnow.pfrsqrt
	3, // llvm.x86.3dnow.pfsub
	3, // llvm.x86.3dnow.pfsubr
	3, // llvm.x86.3dnow.pi2fd
	3, // llvm.x86.3dnow.pmulhrw
	3, // llvm.x86.3dnowa.pf2iw
	3, // llvm.x86.3dnowa.pfnacc
	3, // llvm.x86.3dnowa.pfpnacc
	3, // llvm.x86.3dnowa.pi2fw
	3, // llvm.x86.3dnowa.pswapd
	3, // llvm.x86.aesni.aesdec
	3, // llvm.x86.aesni.aesdeclast
	3, // llvm.x86.aesni.aesenc
	3, // llvm.x86.aesni.aesenclast
	3, // llvm.x86.aesni.aesimc
	3, // llvm.x86.aesni.aeskeygenassist
	1, // llvm.x86.avx2.gather.d.d
	1, // llvm.x86.avx2.gather.d.d.256
	1, // llvm.x86.avx2.gather.d.pd
	1, // llvm.x86.avx2.gather.d.pd.256
	1, // llvm.x86.avx2.gather.d.ps
	1, // llvm.x86.avx2.gather.d.ps.256
	1, // llvm.x86.avx2.gather.d.q
	1, // llvm.x86.avx2.gather.d.q.256
	1, // llvm.x86.avx2.gather.q.d
	1, // llvm.x86.avx2.gather.q.d.256
	1, // llvm.x86.avx2.gather.q.pd
	1, // llvm.x86.avx2.gather.q.pd.256
	1, // llvm.x86.avx2.gather.q.ps
	1, // llvm.x86.avx2.gather.q.ps.256
	1, // llvm.x86.avx2.gather.q.q
	1, // llvm.x86.avx2.gather.q.q.256
	1, // llvm.x86.avx2.maskload.d
	1, // llvm.x86.avx2.maskload.d.256
	1, // llvm.x86.avx2.maskload.q
	1, // llvm.x86.avx2.maskload.q.256
	2, // llvm.x86.avx2.maskstore.d
	2, // llvm.x86.avx2.maskstore.d.256
	2, // llvm.x86.avx2.maskstore.q
	2, // llvm.x86.avx2.maskstore.q.256
	1, // llvm.x86.avx2.movntdqa
	3, // llvm.x86.avx2.mpsadbw
	3, // llvm.x86.avx2.pabs.b
	3, // llvm.x86.avx2.pabs.d
	3, // llvm.x86.avx2.pabs.w
	3, // llvm.x86.avx2.packssdw
	3, // llvm.x86.avx2.packsswb
	3, // llvm.x86.avx2.packusdw
	3, // llvm.x86.avx2.packuswb
	3, // llvm.x86.avx2.padds.b
	3, // llvm.x86.avx2.padds.w
	3, // llvm.x86.avx2.paddus.b
	3, // llvm.x86.avx2.paddus.w
	3, // llvm.x86.avx2.pavg.b
	3, // llvm.x86.avx2.pavg.w
	3, // llvm.x86.avx2.pblendd.128
	3, // llvm.x86.avx2.pblendd.256
	3, // llvm.x86.avx2.pblendvb
	3, // llvm.x86.avx2.pblendw
	3, // llvm.x86.avx2.pbroadcastb.128
	3, // llvm.x86.avx2.pbroadcastb.256
	3, // llvm.x86.avx2.pbroadcastd.128
	3, // llvm.x86.avx2.pbroadcastd.256
	3, // llvm.x86.avx2.pbroadcastq.128
	3, // llvm.x86.avx2.pbroadcastq.256
	3, // llvm.x86.avx2.pbroadcastw.128
	3, // llvm.x86.avx2.pbroadcastw.256
	3, // llvm.x86.avx2.permd
	3, // llvm.x86.avx2.permps
	3, // llvm.x86.avx2.phadd.d
	3, // llvm.x86.avx2.phadd.sw
	3, // llvm.x86.avx2.phadd.w
	3, // llvm.x86.avx2.phsub.d
	3, // llvm.x86.avx2.phsub.sw
	3, // llvm.x86.avx2.phsub.w
	3, // llvm.x86.avx2.pmadd.ub.sw
	3, // llvm.x86.avx2.pmadd.wd
	3, // llvm.x86.avx2.pmaxs.b
	3, // llvm.x86.avx2.pmaxs.d
	3, // llvm.x86.avx2.pmaxs.w
	3, // llvm.x86.avx2.pmaxu.b
	3, // llvm.x86.avx2.pmaxu.d
	3, // llvm.x86.avx2.pmaxu.w
	3, // llvm.x86.avx2.pmins.b
	3, // llvm.x86.avx2.pmins.d
	3, // llvm.x86.avx2.pmins.w
	3, // llvm.x86.avx2.pminu.b
	3, // llvm.x86.avx2.pminu.d
	3, // llvm.x86.avx2.pminu.w
	3, // llvm.x86.avx2.pmovmskb
	3, // llvm.x86.avx2.pmovsxbd
	3, // llvm.x86.avx2.pmovsxbq
	3, // llvm.x86.avx2.pmovsxbw
	3, // llvm.x86.avx2.pmovsxdq
	3, // llvm.x86.avx2.pmovsxwd
	3, // llvm.x86.avx2.pmovsxwq
	3, // llvm.x86.avx2.pmovzxbd
	3, // llvm.x86.avx2.pmovzxbq
	3, // llvm.x86.avx2.pmovzxbw
	3, // llvm.x86.avx2.pmovzxdq
	3, // llvm.x86.avx2.pmovzxwd
	3, // llvm.x86.avx2.pmovzxwq
	3, // llvm.x86.avx2.pmul.dq
	3, // llvm.x86.avx2.pmul.hr.sw
	3, // llvm.x86.avx2.pmulh.w
	3, // llvm.x86.avx2.pmulhu.w
	3, // llvm.x86.avx2.pmulu.dq
	3, // llvm.x86.avx2.psad.bw
	3, // llvm.x86.avx2.pshuf.b
	3, // llvm.x86.avx2.psign.b
	3, // llvm.x86.avx2.psign.d
	3, // llvm.x86.avx2.psign.w
	3, // llvm.x86.avx2.psll.d
	3, // llvm.x86.avx2.psll.dq
	3, // llvm.x86.avx2.psll.dq.bs
	3, // llvm.x86.avx2.psll.q
	3, // llvm.x86.avx2.psll.w
	3, // llvm.x86.avx2.pslli.d
	3, // llvm.x86.avx2.pslli.q
	3, // llvm.x86.avx2.pslli.w
	3, // llvm.x86.avx2.psllv.d
	3, // llvm.x86.avx2.psllv.d.256
	3, // llvm.x86.avx2.psllv.q
	3, // llvm.x86.avx2.psllv.q.256
	3, // llvm.x86.avx2.psra.d
	3, // llvm.x86.avx2.psra.w
	3, // llvm.x86.avx2.psrai.d
	3, // llvm.x86.avx2.psrai.w
	3, // llvm.x86.avx2.psrav.d
	3, // llvm.x86.avx2.psrav.d.256
	3, // llvm.x86.avx2.psrl.d
	3, // llvm.x86.avx2.psrl.dq
	3, // llvm.x86.avx2.psrl.dq.bs
	3, // llvm.x86.avx2.psrl.q
	3, // llvm.x86.avx2.psrl.w
	3, // llvm.x86.avx2.psrli.d
	3, // llvm.x86.avx2.psrli.q
	3, // llvm.x86.avx2.psrli.w
	3, // llvm.x86.avx2.psrlv.d
	3, // llvm.x86.avx2.psrlv.d.256
	3, // llvm.x86.avx2.psrlv.q
	3, // llvm.x86.avx2.psrlv.q.256
	3, // llvm.x86.avx2.psubs.b
	3, // llvm.x86.avx2.psubs.w
	3, // llvm.x86.avx2.psubus.b
	3, // llvm.x86.avx2.psubus.w
	3, // llvm.x86.avx2.vbroadcast.sd.pd.256
	3, // llvm.x86.avx2.vbroadcast.ss.ps
	3, // llvm.x86.avx2.vbroadcast.ss.ps.256
	1, // llvm.x86.avx2.vbroadcasti128
	3, // llvm.x86.avx2.vextracti128
	3, // llvm.x86.avx2.vinserti128
	3, // llvm.x86.avx2.vperm2i128
	3, // llvm.x86.avx.addsub.pd.256
	3, // llvm.x86.avx.addsub.ps.256
	3, // llvm.x86.avx.blend.pd.256
	3, // llvm.x86.avx.blend.ps.256
	3, // llvm.x86.avx.blendv.pd.256
	3, // llvm.x86.avx.blendv.ps.256
	3, // llvm.x86.avx.cmp.pd.256
	3, // llvm.x86.avx.cmp.ps.256
	3, // llvm.x86.avx.cvt.pd2.ps.256
	3, // llvm.x86.avx.cvt.pd2dq.256
	3, // llvm.x86.avx.cvt.ps2.pd.256
	3, // llvm.x86.avx.cvt.ps2dq.256
	3, // llvm.x86.avx.cvtdq2.pd.256
	3, // llvm.x86.avx.cvtdq2.ps.256
	3, // llvm.x86.avx.cvtt.pd2dq.256
	3, // llvm.x86.avx.cvtt.ps2dq.256
	3, // llvm.x86.avx.dp.ps.256
	3, // llvm.x86.avx.hadd.pd.256
	3, // llvm.x86.avx.hadd.ps.256
	3, // llvm.x86.avx.hsub.pd.256
	3, // llvm.x86.avx.hsub.ps.256
	1, // llvm.x86.avx.ldu.dq.256
	1, // llvm.x86.avx.maskload.pd
	1, // llvm.x86.avx.maskload.pd.256
	1, // llvm.x86.avx.maskload.ps
	1, // llvm.x86.avx.maskload.ps.256
	2, // llvm.x86.avx.maskstore.pd
	2, // llvm.x86.avx.maskstore.pd.256
	2, // llvm.x86.avx.maskstore.ps
	2, // llvm.x86.avx.maskstore.ps.256
	3, // llvm.x86.avx.max.pd.256
	3, // llvm.x86.avx.max.ps.256
	3, // llvm.x86.avx.min.pd.256
	3, // llvm.x86.avx.min.ps.256
	3, // llvm.x86.avx.movmsk.pd.256
	3, // llvm.x86.avx.movmsk.ps.256
	3, // llvm.x86.avx.ptestc.256
	3, // llvm.x86.avx.ptestnzc.256
	3, // llvm.x86.avx.ptestz.256
	3, // llvm.x86.avx.rcp.ps.256
	3, // llvm.x86.avx.round.pd.256
	3, // llvm.x86.avx.round.ps.256
	3, // llvm.x86.avx.rsqrt.ps.256
	3, // llvm.x86.avx.sqrt.pd.256
	3, // llvm.x86.avx.sqrt.ps.256
	2, // llvm.x86.avx.storeu.dq.256
	2, // llvm.x86.avx.storeu.pd.256
	2, // llvm.x86.avx.storeu.ps.256
	1, // llvm.x86.avx.vbroadcast.sd.256
	1, // llvm.x86.avx.vbroadcast.ss
	1, // llvm.x86.avx.vbroadcast.ss.256
	1, // llvm.x86.avx.vbroadcastf128.pd.256
	1, // llvm.x86.avx.vbroadcastf128.ps.256
	3, // llvm.x86.avx.vextractf128.pd.256
	3, // llvm.x86.avx.vextractf128.ps.256
	3, // llvm.x86.avx.vextractf128.si.256
	3, // llvm.x86.avx.vinsertf128.pd.256
	3, // llvm.x86.avx.vinsertf128.ps.256
	3, // llvm.x86.avx.vinsertf128.si.256
	3, // llvm.x86.avx.vperm2f128.pd.256
	3, // llvm.x86.avx.vperm2f128.ps.256
	3, // llvm.x86.avx.vperm2f128.si.256
	3, // llvm.x86.avx.vpermilvar.pd
	3, // llvm.x86.avx.vpermilvar.pd.256
	3, // llvm.x86.avx.vpermilvar.ps
	3, // llvm.x86.avx.vpermilvar.ps.256
	3, // llvm.x86.avx.vtestc.pd
	3, // llvm.x86.avx.vtestc.pd.256
	3, // llvm.x86.avx.vtestc.ps
	3, // llvm.x86.avx.vtestc.ps.256
	3, // llvm.x86.avx.vtestnzc.pd
	3, // llvm.x86.avx.vtestnzc.pd.256
	3, // llvm.x86.avx.vtestnzc.ps
	3, // llvm.x86.avx.vtestnzc.ps.256
	3, // llvm.x86.avx.vtestz.pd
	3, // llvm.x86.avx.vtestz.pd.256
	3, // llvm.x86.avx.vtestz.ps
	3, // llvm.x86.avx.vtestz.ps.256
	2, // llvm.x86.avx.vzeroall
	2, // llvm.x86.avx.vzeroupper
	3, // llvm.x86.bmi.bextr.32
	3, // llvm.x86.bmi.bextr.64
	3, // llvm.x86.bmi.bzhi.32
	3, // llvm.x86.bmi.bzhi.64
	3, // llvm.x86.bmi.pdep.32
	3, // llvm.x86.bmi.pdep.64
	3, // llvm.x86.bmi.pext.32
	3, // llvm.x86.bmi.pext.64
	3, // llvm.x86.fma.vfmadd.pd
	3, // llvm.x86.fma.vfmadd.pd.256
	3, // llvm.x86.fma.vfmadd.ps
	3, // llvm.x86.fma.vfmadd.ps.256
	3, // llvm.x86.fma.vfmadd.sd
	3, // llvm.x86.fma.vfmadd.ss
	3, // llvm.x86.fma.vfmaddsub.pd
	3, // llvm.x86.fma.vfmaddsub.pd.256
	3, // llvm.x86.fma.vfmaddsub.ps
	3, // llvm.x86.fma.vfmaddsub.ps.256
	3, // llvm.x86.fma.vfmsub.pd
	3, // llvm.x86.fma.vfmsub.pd.256
	3, // llvm.x86.fma.vfmsub.ps
	3, // llvm.x86.fma.vfmsub.ps.256
	3, // llvm.x86.fma.vfmsub.sd
	3, // llvm.x86.fma.vfmsub.ss
	3, // llvm.x86.fma.vfmsubadd.pd
	3, // llvm.x86.fma.vfmsubadd.pd.256
	3, // llvm.x86.fma.vfmsubadd.ps
	3, // llvm.x86.fma.vfmsubadd.ps.256
	3, // llvm.x86.fma.vfnmadd.pd
	3, // llvm.x86.fma.vfnmadd.pd.256
	3, // llvm.x86.fma.vfnmadd.ps
	3, // llvm.x86.fma.vfnmadd.ps.256
	3, // llvm.x86.fma.vfnmadd.sd
	3, // llvm.x86.fma.vfnmadd.ss
	3, // llvm.x86.fma.vfnmsub.pd
	3, // llvm.x86.fma.vfnmsub.pd.256
	3, // llvm.x86.fma.vfnmsub.ps
	3, // llvm.x86.fma.vfnmsub.ps.256
	3, // llvm.x86.fma.vfnmsub.sd
	3, // llvm.x86.fma.vfnmsub.ss
	2, // llvm.x86.int
	2, // llvm.x86.mmx.emms
	2, // llvm.x86.mmx.femms
	2, // llvm.x86.mmx.maskmovq
	2, // llvm.x86.mmx.movnt.dq
	3, // llvm.x86.mmx.packssdw
	3, // llvm.x86.mmx.packsswb
	3, // llvm.x86.mmx.packuswb
	3, // llvm.x86.mmx.padd.b
	3, // llvm.x86.mmx.padd.d
	3, // llvm.x86.mmx.padd.q
	3, // llvm.x86.mmx.padd.w
	3, // llvm.x86.mmx.padds.b
	3, // llvm.x86.mmx.padds.w
	3, // llvm.x86.mmx.paddus.b
	3, // llvm.x86.mmx.paddus.w
	3, // llvm.x86.mmx.palignr.b
	3, // llvm.x86.mmx.pand
	3, // llvm.x86.mmx.pandn
	3, // llvm.x86.mmx.pavg.b
	3, // llvm.x86.mmx.pavg.w
	3, // llvm.x86.mmx.pcmpeq.b
	3, // llvm.x86.mmx.pcmpeq.d
	3, // llvm.x86.mmx.pcmpeq.w
	3, // llvm.x86.mmx.pcmpgt.b
	3, // llvm.x86.mmx.pcmpgt.d
	3, // llvm.x86.mmx.pcmpgt.w
	3, // llvm.x86.mmx.pextr.w
	3, // llvm.x86.mmx.pinsr.w
	3, // llvm.x86.mmx.pmadd.wd
	3, // llvm.x86.mmx.pmaxs.w
	3, // llvm.x86.mmx.pmaxu.b
	3, // llvm.x86.mmx.pmins.w
	3, // llvm.x86.mmx.pminu.b
	3, // llvm.x86.mmx.pmovmskb
	3, // llvm.x86.mmx.pmulh.w
	3, // llvm.x86.mmx.pmulhu.w
	3, // llvm.x86.mmx.pmull.w
	3, // llvm.x86.mmx.pmulu.dq
	3, // llvm.x86.mmx.por
	3, // llvm.x86.mmx.psad.bw
	3, // llvm.x86.mmx.psll.d
	3, // llvm.x86.mmx.psll.q
	3, // llvm.x86.mmx.psll.w
	3, // llvm.x86.mmx.pslli.d
	3, // llvm.x86.mmx.pslli.q
	3, // llvm.x86.mmx.pslli.w
	3, // llvm.x86.mmx.psra.d
	3, // llvm.x86.mmx.psra.w
	3, // llvm.x86.mmx.psrai.d
	3, // llvm.x86.mmx.psrai.w
	3, // llvm.x86.mmx.psrl.d
	3, // llvm.x86.mmx.psrl.q
	3, // llvm.x86.mmx.psrl.w
	3, // llvm.x86.mmx.psrli.d
	3, // llvm.x86.mmx.psrli.q
	3, // llvm.x86.mmx.psrli.w
	3, // llvm.x86.mmx.psub.b
	3, // llvm.x86.mmx.psub.d
	3, // llvm.x86.mmx.psub.q
	3, // llvm.x86.mmx.psub.w
	3, // llvm.x86.mmx.psubs.b
	3, // llvm.x86.mmx.psubs.w
	3, // llvm.x86.mmx.psubus.b
	3, // llvm.x86.mmx.psubus.w
	3, // llvm.x86.mmx.punpckhbw
	3, // llvm.x86.mmx.punpckhdq
	3, // llvm.x86.mmx.punpckhwd
	3, // llvm.x86.mmx.punpcklbw
	3, // llvm.x86.mmx.punpckldq
	3, // llvm.x86.mmx.punpcklwd
	3, // llvm.x86.mmx.pxor
	3, // llvm.x86.pclmulqdq
	2, // llvm.x86.rdfsbase.32
	2, // llvm.x86.rdfsbase.64
	2, // llvm.x86.rdgsbase.32
	2, // llvm.x86.rdgsbase.64
	2, // llvm.x86.rdrand.16
	2, // llvm.x86.rdrand.32
	2, // llvm.x86.rdrand.64
	2, // llvm.x86.rdseed.16
	2, // llvm.x86.rdseed.32
	2, // llvm.x86.rdseed.64
	3, // llvm.x86.sse2.add.sd
	2, // llvm.x86.sse2.clflush
	3, // llvm.x86.sse2.cmp.pd
	3, // llvm.x86.sse2.cmp.sd
	3, // llvm.x86.sse2.comieq.sd
	3, // llvm.x86.sse2.comige.sd
	3, // llvm.x86.sse2.comigt.sd
	3, // llvm.x86.sse2.comile.sd
	3, // llvm.x86.sse2.comilt.sd
	3, // llvm.x86.sse2.comineq.sd
	3, // llvm.x86.sse2.cvtdq2pd
	3, // llvm.x86.sse2.cvtdq2ps
	3, // llvm.x86.sse2.cvtpd2dq
	3, // llvm.x86.sse2.cvtpd2ps
	3, // llvm.x86.sse2.cvtps2dq
	3, // llvm.x86.sse2.cvtps2pd
	3, // llvm.x86.sse2.cvtsd2si
	3, // llvm.x86.sse2.cvtsd2si64
	3, // llvm.x86.sse2.cvtsd2ss
	3, // llvm.x86.sse2.cvtsi2sd
	3, // llvm.x86.sse2.cvtsi642sd
	3, // llvm.x86.sse2.cvtss2sd
	3, // llvm.x86.sse2.cvttpd2dq
	3, // llvm.x86.sse2.cvttps2dq
	3, // llvm.x86.sse2.cvttsd2si
	3, // llvm.x86.sse2.cvttsd2si64
	3, // llvm.x86.sse2.div.sd
	2, // llvm.x86.sse2.lfence
	2, // llvm.x86.sse2.maskmov.dqu
	3, // llvm.x86.sse2.max.pd
	3, // llvm.x86.sse2.max.sd
	2, // llvm.x86.sse2.mfence
	3, // llvm.x86.sse2.min.pd
	3, // llvm.x86.sse2.min.sd
	3, // llvm.x86.sse2.movmsk.pd
	3, // llvm.x86.sse2.mul.sd
	3, // llvm.x86.sse2.packssdw.128
	3, // llvm.x86.sse2.packsswb.128
	3, // llvm.x86.sse2.packuswb.128
	3, // llvm.x86.sse2.padds.b
	3, // llvm.x86.sse2.padds.w
	3, // llvm.x86.sse2.paddus.b
	3, // llvm.x86.sse2.paddus.w
	3, // llvm.x86.sse2.pavg.b
	3, // llvm.x86.sse2.pavg.w
	3, // llvm.x86.sse2.pmadd.wd
	3, // llvm.x86.sse2.pmaxs.w
	3, // llvm.x86.sse2.pmaxu.b
	3, // llvm.x86.sse2.pmins.w
	3, // llvm.x86.sse2.pminu.b
	3, // llvm.x86.sse2.pmovmskb.128
	3, // llvm.x86.sse2.pmulh.w
	3, // llvm.x86.sse2.pmulhu.w
	3, // llvm.x86.sse2.pmulu.dq
	3, // llvm.x86.sse2.psad.bw
	3, // llvm.x86.sse2.psll.d
	3, // llvm.x86.sse2.psll.dq
	3, // llvm.x86.sse2.psll.dq.bs
	3, // llvm.x86.sse2.psll.q
	3, // llvm.x86.sse2.psll.w
	3, // llvm.x86.sse2.pslli.d
	3, // llvm.x86.sse2.pslli.q
	3, // llvm.x86.sse2.pslli.w
	3, // llvm.x86.sse2.psra.d
	3, // llvm.x86.sse2.psra.w
	3, // llvm.x86.sse2.psrai.d
	3, // llvm.x86.sse2.psrai.w
	3, // llvm.x86.sse2.psrl.d
	3, // llvm.x86.sse2.psrl.dq
	3, // llvm.x86.sse2.psrl.dq.bs
	3, // llvm.x86.sse2.psrl.q
	3, // llvm.x86.sse2.psrl.w
	3, // llvm.x86.sse2.psrli.d
	3, // llvm.x86.sse2.psrli.q
	3, // llvm.x86.sse2.psrli.w
	3, // llvm.x86.sse2.psubs.b
	3, // llvm.x86.sse2.psubs.w
	3, // llvm.x86.sse2.psubus.b
	3, // llvm.x86.sse2.psubus.w
	3, // llvm.x86.sse2.sqrt.pd
	3, // llvm.x86.sse2.sqrt.sd
	2, // llvm.x86.sse2.storel.dq
	2, // llvm.x86.sse2.storeu.dq
	2, // llvm.x86.sse2.storeu.pd
	3, // llvm.x86.sse2.sub.sd
	3, // llvm.x86.sse2.ucomieq.sd
	3, // llvm.x86.sse2.ucomige.sd
	3, // llvm.x86.sse2.ucomigt.sd
	3, // llvm.x86.sse2.ucomile.sd
	3, // llvm.x86.sse2.ucomilt.sd
	3, // llvm.x86.sse2.ucomineq.sd
	3, // llvm.x86.sse3.addsub.pd
	3, // llvm.x86.sse3.addsub.ps
	3, // llvm.x86.sse3.hadd.pd
	3, // llvm.x86.sse3.hadd.ps
	3, // llvm.x86.sse3.hsub.pd
	3, // llvm.x86.sse3.hsub.ps
	1, // llvm.x86.sse3.ldu.dq
	2, // llvm.x86.sse3.monitor
	2, // llvm.x86.sse3.mwait
	3, // llvm.x86.sse41.blendpd
	3, // llvm.x86.sse41.blendps
	3, // llvm.x86.sse41.blendvpd
	3, // llvm.x86.sse41.blendvps
	3, // llvm.x86.sse41.dppd
	3, // llvm.x86.sse41.dpps
	3, // llvm.x86.sse41.extractps
	3, // llvm.x86.sse41.insertps
	1, // llvm.x86.sse41.movntdqa
	3, // llvm.x86.sse41.mpsadbw
	3, // llvm.x86.sse41.packusdw
	3, // llvm.x86.sse41.pblendvb
	3, // llvm.x86.sse41.pblendw
	3, // llvm.x86.sse41.pextrb
	3, // llvm.x86.sse41.pextrd
	3, // llvm.x86.sse41.pextrq
	3, // llvm.x86.sse41.phminposuw
	3, // llvm.x86.sse41.pmaxsb
	3, // llvm.x86.sse41.pmaxsd
	3, // llvm.x86.sse41.pmaxud
	3, // llvm.x86.sse41.pmaxuw
	3, // llvm.x86.sse41.pminsb
	3, // llvm.x86.sse41.pminsd
	3, // llvm.x86.sse41.pminud
	3, // llvm.x86.sse41.pminuw
	3, // llvm.x86.sse41.pmovsxbd
	3, // llvm.x86.sse41.pmovsxbq
	3, // llvm.x86.sse41.pmovsxbw
	3, // llvm.x86.sse41.pmovsxdq
	3, // llvm.x86.sse41.pmovsxwd
	3, // llvm.x86.sse41.pmovsxwq
	3, // llvm.x86.sse41.pmovzxbd
	3, // llvm.x86.sse41.pmovzxbq
	3, // llvm.x86.sse41.pmovzxbw
	3, // llvm.x86.sse41.pmovzxdq
	3, // llvm.x86.sse41.pmovzxwd
	3, // llvm.x86.sse41.pmovzxwq
	3, // llvm.x86.sse41.pmuldq
	3, // llvm.x86.sse41.ptestc
	3, // llvm.x86.sse41.ptestnzc
	3, // llvm.x86.sse41.ptestz
	3, // llvm.x86.sse41.round.pd
	3, // llvm.x86.sse41.round.ps
	3, // llvm.x86.sse41.round.sd
	3, // llvm.x86.sse41.round.ss
	3, // llvm.x86.sse42.crc32.32.16
	3, // llvm.x86.sse42.crc32.32.32
	3, // llvm.x86.sse42.crc32.32.8
	3, // llvm.x86.sse42.crc32.64.64
	3, // llvm.x86.sse42.crc32.64.8
	3, // llvm.x86.sse42.pcmpestri128
	3, // llvm.x86.sse42.pcmpestria128
	3, // llvm.x86.sse42.pcmpestric128
	3, // llvm.x86.sse42.pcmpestrio128
	3, // llvm.x86.sse42.pcmpestris128
	3, // llvm.x86.sse42.pcmpestriz128
	3, // llvm.x86.sse42.pcmpestrm128
	3, // llvm.x86.sse42.pcmpistri128
	3, // llvm.x86.sse42.pcmpistria128
	3, // llvm.x86.sse42.pcmpistric128
	3, // llvm.x86.sse42.pcmpistrio128
	3, // llvm.x86.sse42.pcmpistris128
	3, // llvm.x86.sse42.pcmpistriz128
	3, // llvm.x86.sse42.pcmpistrm128
	3, // llvm.x86.sse4a.extrq
	3, // llvm.x86.sse4a.extrqi
	3, // llvm.x86.sse4a.insertq
	3, // llvm.x86.sse4a.insertqi
	2, // llvm.x86.sse4a.movnt.sd
	2, // llvm.x86.sse4a.movnt.ss
	3, // llvm.x86.sse.add.ss
	3, // llvm.x86.sse.cmp.ps
	3, // llvm.x86.sse.cmp.ss
	3, // llvm.x86.sse.comieq.ss
	3, // llvm.x86.sse.comige.ss
	3, // llvm.x86.sse.comigt.ss
	3, // llvm.x86.sse.comile.ss
	3, // llvm.x86.sse.comilt.ss
	3, // llvm.x86.sse.comineq.ss
	3, // llvm.x86.sse.cvtpd2pi
	3, // llvm.x86.sse.cvtpi2pd
	3, // llvm.x86.sse.cvtpi2ps
	3, // llvm.x86.sse.cvtps2pi
	3, // llvm.x86.sse.cvtsi2ss
	3, // llvm.x86.sse.cvtsi642ss
	3, // llvm.x86.sse.cvtss2si
	3, // llvm.x86.sse.cvtss2si64
	3, // llvm.x86.sse.cvttpd2pi
	3, // llvm.x86.sse.cvttps2pi
	3, // llvm.x86.sse.cvttss2si
	3, // llvm.x86.sse.cvttss2si64
	3, // llvm.x86.sse.div.ss
	2, // llvm.x86.sse.ldmxcsr
	3, // llvm.x86.sse.max.ps
	3, // llvm.x86.sse.max.ss
	3, // llvm.x86.sse.min.ps
	3, // llvm.x86.sse.min.ss
	3, // llvm.x86.sse.movmsk.ps
	3, // llvm.x86.sse.mul.ss
	3, // llvm.x86.sse.pshuf.w
	3, // llvm.x86.sse.rcp.ps
	3, // llvm.x86.sse.rcp.ss
	3, // llvm.x86.sse.rsqrt.ps
	3, // llvm.x86.sse.rsqrt.ss
	2, // llvm.x86.sse.sfence
	3, // llvm.x86.sse.sqrt.ps
	3, // llvm.x86.sse.sqrt.ss
	2, // llvm.x86.sse.stmxcsr
	2, // llvm.x86.sse.storeu.ps
	3, // llvm.x86.sse.sub.ss
	3, // llvm.x86.sse.ucomieq.ss
	3, // llvm.x86.sse.ucomige.ss
	3, // llvm.x86.sse.ucomigt.ss
	3, // llvm.x86.sse.ucomile.ss
	3, // llvm.x86.sse.ucomilt.ss
	3, // llvm.x86.sse.ucomineq.ss
	3, // llvm.x86.ssse3.pabs.b
	3, // llvm.x86.ssse3.pabs.b.128
	3, // llvm.x86.ssse3.pabs.d
	3, // llvm.x86.ssse3.pabs.d.128
	3, // llvm.x86.ssse3.pabs.w
	3, // llvm.x86.ssse3.pabs.w.128
	3, // llvm.x86.ssse3.phadd.d
	3, // llvm.x86.ssse3.phadd.d.128
	3, // llvm.x86.ssse3.phadd.sw
	3, // llvm.x86.ssse3.phadd.sw.128
	3, // llvm.x86.ssse3.phadd.w
	3, // llvm.x86.ssse3.phadd.w.128
	3, // llvm.x86.ssse3.phsub.d
	3, // llvm.x86.ssse3.phsub.d.128
	3, // llvm.x86.ssse3.phsub.sw
	3, // llvm.x86.ssse3.phsub.sw.128
	3, // llvm.x86.ssse3.phsub.w
	3, // llvm.x86.ssse3.phsub.w.128
	3, // llvm.x86.ssse3.pmadd.ub.sw
	3, // llvm.x86.ssse3.pmadd.ub.sw.128
	3, // llvm.x86.ssse3.pmul.hr.sw
	3, // llvm.x86.ssse3.pmul.hr.sw.128
	3, // llvm.x86.ssse3.pshuf.b
	3, // llvm.x86.ssse3.pshuf.b.128
	3, // llvm.x86.ssse3.psign.b
	3, // llvm.x86.ssse3.psign.b.128
	3, // llvm.x86.ssse3.psign.d
	3, // llvm.x86.ssse3.psign.d.128
	3, // llvm.x86.ssse3.psign.w
	3, // llvm.x86.ssse3.psign.w.128
	3, // llvm.x86.vcvtph2ps.128
	3, // llvm.x86.vcvtph2ps.256
	3, // llvm.x86.vcvtps2ph.128
	3, // llvm.x86.vcvtps2ph.256
	2, // llvm.x86.wrfsbase.32
	2, // llvm.x86.wrfsbase.64
	2, // llvm.x86.wrgsbase.32
	2, // llvm.x86.wrgsbase.64
	4, // llvm.x86.xabort
	2, // llvm.x86.xbegin
	2, // llvm.x86.xend
	3, // llvm.x86.xop.vfrcz.pd
	3, // llvm.x86.xop.vfrcz.pd.256
	3, // llvm.x86.xop.vfrcz.ps
	3, // llvm.x86.xop.vfrcz.ps.256
	3, // llvm.x86.xop.vfrcz.sd
	3, // llvm.x86.xop.vfrcz.ss
	3, // llvm.x86.xop.vpcmov
	3, // llvm.x86.xop.vpcmov.256
	3, // llvm.x86.xop.vpcomb
	3, // llvm.x86.xop.vpcomd
	3, // llvm.x86.xop.vpcomq
	3, // llvm.x86.xop.vpcomub
	3, // llvm.x86.xop.vpcomud
	3, // llvm.x86.xop.vpcomuq
	3, // llvm.x86.xop.vpcomuw
	3, // llvm.x86.xop.vpcomw
	3, // llvm.x86.xop.vpermil2pd
	3, // llvm.x86.xop.vpermil2pd.256
	3, // llvm.x86.xop.vpermil2ps
	3, // llvm.x86.xop.vpermil2ps.256
	3, // llvm.x86.xop.vphaddbd
	3, // llvm.x86.xop.vphaddbq
	3, // llvm.x86.xop.vphaddbw
	3, // llvm.x86.xop.vphadddq
	3, // llvm.x86.xop.vphaddubd
	3, // llvm.x86.xop.vphaddubq
	3, // llvm.x86.xop.vphaddubw
	3, // llvm.x86.xop.vphaddudq
	3, // llvm.x86.xop.vphadduwd
	3, // llvm.x86.xop.vphadduwq
	3, // llvm.x86.xop.vphaddwd
	3, // llvm.x86.xop.vphaddwq
	3, // llvm.x86.xop.vphsubbw
	3, // llvm.x86.xop.vphsubdq
	3, // llvm.x86.xop.vphsubwd
	3, // llvm.x86.xop.vpmacsdd
	3, // llvm.x86.xop.vpmacsdqh
	3, // llvm.x86.xop.vpmacsdql
	3, // llvm.x86.xop.vpmacssdd
	3, // llvm.x86.xop.vpmacssdqh
	3, // llvm.x86.xop.vpmacssdql
	3, // llvm.x86.xop.vpmacsswd
	3, // llvm.x86.xop.vpmacssww
	3, // llvm.x86.xop.vpmacswd
	3, // llvm.x86.xop.vpmacsww
	3, // llvm.x86.xop.vpmadcsswd
	3, // llvm.x86.xop.vpmadcswd
	3, // llvm.x86.xop.vpperm
	3, // llvm.x86.xop.vprotb
	3, // llvm.x86.xop.vprotbi
	3, // llvm.x86.xop.vprotd
	3, // llvm.x86.xop.vprotdi
	3, // llvm.x86.xop.vprotq
	3, // llvm.x86.xop.vprotqi
	3, // llvm.x86.xop.vprotw
	3, // llvm.x86.xop.vprotwi
	3, // llvm.x86.xop.vpshab
	3, // llvm.x86.xop.vpshad
	3, // llvm.x86.xop.vpshaq
	3, // llvm.x86.xop.vpshaw
	3, // llvm.x86.xop.vpshlb
	3, // llvm.x86.xop.vpshld
	3, // llvm.x86.xop.vpshlq
	3, // llvm.x86.xop.vpshlw
	2, // llvm.x86.xtest
	3, // llvm.xcore.bitrev
	2, // llvm.xcore.checkevent
	6, // llvm.xcore.chkct
	2, // llvm.xcore.clre
	2, // llvm.xcore.clrsr
	3, // llvm.xcore.crc32
	3, // llvm.xcore.crc8
	6, // llvm.xcore.eeu
	6, // llvm.xcore.endin
	6, // llvm.xcore.freer
	2, // llvm.xcore.geted
	2, // llvm.xcore.getet
	3, // llvm.xcore.getid
	2, // llvm.xcore.getps
	2, // llvm.xcore.getr
	6, // llvm.xcore.getst
	6, // llvm.xcore.getts
	6, // llvm.xcore.in
	6, // llvm.xcore.inct
	6, // llvm.xcore.initcp
	6, // llvm.xcore.initdp
	6, // llvm.xcore.initlr
	6, // llvm.xcore.initpc
	6, // llvm.xcore.initsp
	6, // llvm.xcore.inshr
	6, // llvm.xcore.int
	6, // llvm.xcore.mjoin
	6, // llvm.xcore.msync
	6, // llvm.xcore.out
	6, // llvm.xcore.outct
	6, // llvm.xcore.outshr
	6, // llvm.xcore.outt
	6, // llvm.xcore.peek
	6, // llvm.xcore.setc
	9, // llvm.xcore.setclk
	6, // llvm.xcore.setd
	6, // llvm.xcore.setev
	2, // llvm.xcore.setps
	6, // llvm.xcore.setpsc
	6, // llvm.xcore.setpt
	9, // llvm.xcore.setrdy
	2, // llvm.xcore.setsr
	6, // llvm.xcore.settw
	6, // llvm.xcore.setv
	3, // llvm.xcore.sext
	2, // llvm.xcore.ssync
	6, // llvm.xcore.syncr
	6, // llvm.xcore.testct
	6, // llvm.xcore.testwct
	1, // llvm.xcore.waitevent
	3, // llvm.xcore.zext
	};
	AttributeSet AS[3];
	unsigned NumAttrs = 0;
	if (id != 0) {
	SmallVector<Attribute::AttrKind, 8> AttrVec;
	switch(IntrinsicsToAttributesMap[id - 1]) {
	default: llvm_unreachable("Invalid attribute number");
	case 3:
	AttrVec.clear();
	AttrVec.push_back(Attribute::NoUnwind);
	AttrVec.push_back(Attribute::ReadNone);
	AS[0] = AttributeSet::get(C, AttributeSet::FunctionIndex, AttrVec);
	NumAttrs = 1;
	break;
	case 11:
	AttrVec.clear();
	AttrVec.push_back(Attribute::NoCapture);
	AS[0] = AttributeSet::get(C, 1, AttrVec);
	AttrVec.clear();
	AttrVec.push_back(Attribute::NoUnwind);
	AttrVec.push_back(Attribute::ReadNone);
	AS[1] = AttributeSet::get(C, AttributeSet::FunctionIndex, AttrVec);
	NumAttrs = 2;
	break;
	case 1:
	AttrVec.clear();
	AttrVec.push_back(Attribute::NoUnwind);
	AttrVec.push_back(Attribute::ReadOnly);
	AS[0] = AttributeSet::get(C, AttributeSet::FunctionIndex, AttrVec);
	NumAttrs = 1;
	break;
	case 10:
	AttrVec.clear();
	AttrVec.push_back(Attribute::NoCapture);
	AS[0] = AttributeSet::get(C, 1, AttrVec);
	AttrVec.clear();
	AttrVec.push_back(Attribute::NoUnwind);
	AttrVec.push_back(Attribute::ReadOnly);
	AS[1] = AttributeSet::get(C, AttributeSet::FunctionIndex, AttrVec);
	NumAttrs = 2;
	break;
	case 2:
	AttrVec.clear();
	AttrVec.push_back(Attribute::NoUnwind);
	AS[0] = AttributeSet::get(C, AttributeSet::FunctionIndex, AttrVec);
	NumAttrs = 1;
	break;		break;
	case 6:		case 18: // 44 strings to match.
	AttrVec.clear();		if (memcmp(NameR.data()+0, "86.", 3))
	AttrVec.push_back(Attribute::NoCapture);		break;
	AS[0] = AttributeSet::get(C, 1, AttrVec);		switch (NameR[3]) {
	AttrVec.clear();		default: break;
	AttrVec.push_back(Attribute::NoUnwind);		case 'a': // 31 strings to match.
	AS[1] = AttributeSet::get(C, AttributeSet::FunctionIndex, AttrVec);		if (memcmp(NameR.data()+4, "vx", 2))
	NumAttrs = 2;		break;
	break;		switch (NameR[6]) {
	case 9:		default: break;
	AttrVec.clear();		case '.': // 10 strings to match.
	AttrVec.push_back(Attribute::NoCapture);		switch (NameR[7]) {
	AS[0] = AttributeSet::get(C, 1, AttrVec);		default: break;
	AttrVec.clear();		case 'h': // 4 strings to match.
	AttrVec.push_back(Attribute::NoCapture);		switch (NameR[8]) {
	AS[1] = AttributeSet::get(C, 2, AttrVec);		default: break;
	AttrVec.clear();		case 'a': // 2 strings to match.
	AttrVec.push_back(Attribute::NoUnwind);		if (memcmp(NameR.data()+9, "dd.p", 4))
	AS[2] = AttributeSet::get(C, AttributeSet::FunctionIndex, AttrVec);		break;
	NumAttrs = 3;		switch (NameR[13]) {
	break;		default: break;
	case 8:		case 'd': // 1 string to match.
	AttrVec.clear();		if (memcmp(NameR.data()+14, ".256", 4))
	AttrVec.push_back(Attribute::NoCapture);		break;
	AS[0] = AttributeSet::get(C, 2, AttrVec);		return Intrinsic::x86_avx_hadd_pd_256; // "86.avx.hadd.pd.
	AttrVec.clear();		256"
	AttrVec.push_back(Attribute::NoUnwind);		case 's': // 1 string to match.
	AS[1] = AttributeSet::get(C, AttributeSet::FunctionIndex, AttrVec);		if (memcmp(NameR.data()+14, ".256", 4))
	NumAttrs = 2;		break;
	break;		return Intrinsic::x86_avx_hadd_ps_256; // "86.avx.hadd.ps.
	case 5:		256"
	AttrVec.clear();		}
	AttrVec.push_back(Attribute::NoCapture);		break;
	AS[0] = AttributeSet::get(C, 2, AttrVec);		case 's': // 2 strings to match.
	AttrVec.clear();		if (memcmp(NameR.data()+9, "ub.p", 4))
	AttrVec.push_back(Attribute::NoCapture);		break;
	AS[1] = AttributeSet::get(C, 3, AttrVec);		switch (NameR[13]) {
	AttrVec.clear();		default: break;
	AttrVec.push_back(Attribute::NoUnwind);		case 'd': // 1 string to match.
	AS[2] = AttributeSet::get(C, AttributeSet::FunctionIndex, AttrVec);		if (memcmp(NameR.data()+14, ".256", 4))
	NumAttrs = 3;		break;
	break;		return Intrinsic::x86_avx_hsub_pd_256; // "86.avx.hsub.pd.
	case 7:		256"
	AttrVec.clear();		case 's': // 1 string to match.
	AttrVec.push_back(Attribute::NoCapture);		if (memcmp(NameR.data()+14, ".256", 4))
	AS[0] = AttributeSet::get(C, 3, AttrVec);		break;
	AttrVec.clear();		return Intrinsic::x86_avx_hsub_ps_256; // "86.avx.hsub.ps.
	AttrVec.push_back(Attribute::NoUnwind);		256"
	AS[1] = AttributeSet::get(C, AttributeSet::FunctionIndex, AttrVec);		}
	NumAttrs = 2;		break;
	break;		}
	case 4:		break;
	AttrVec.clear();		case 'm': // 2 strings to match.
	AttrVec.push_back(Attribute::NoUnwind);		if (memcmp(NameR.data()+8, "askload.p", 9))
	AttrVec.push_back(Attribute::NoReturn);		break;
	AS[0] = AttributeSet::get(C, AttributeSet::FunctionIndex, AttrVec);		switch (NameR[17]) {
	NumAttrs = 1;		default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx_maskload_pd; // "86.avx.maskload
			.pd"
			case 's': // 1 string to match.
			return Intrinsic::x86_avx_maskload_ps; // "86.avx.maskload
			.ps"
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(NameR.data()+8, "qrt.p", 5))
			break;
			switch (NameR[13]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+14, ".256", 4))
			break;
			return Intrinsic::x86_avx_sqrt_pd_256; // "86.avx.sqrt.pd.
			256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+14, ".256", 4))
			break;
			return Intrinsic::x86_avx_sqrt_ps_256; // "86.avx.sqrt.ps.
			256"
			}
			break;
			case 'v': // 2 strings to match.
			if (memcmp(NameR.data()+8, "testnzc.p", 9))
			break;
			switch (NameR[17]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx_vtestnzc_pd; // "86.avx.vtestnzc
			.pd"
			case 's': // 1 string to match.
			return Intrinsic::x86_avx_vtestnzc_ps; // "86.avx.vtestnzc
			.ps"
			}
			break;
			}
			break;
			case '2': // 10 strings to match.
			if (NameR[7] != '.')
			break;
			switch (NameR[8]) {
			default: break;
			case 'g': // 4 strings to match.
			if (memcmp(NameR.data()+9, "ather.", 6))
			break;
			switch (NameR[15]) {
			default: break;
			case 'd': // 2 strings to match.
			if (NameR[16] != '.')
			break;
			switch (NameR[17]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx2_gather_d_d; // "86.avx2.gather.
			d.d"
			case 'q': // 1 string to match.
			return Intrinsic::x86_avx2_gather_d_q; // "86.avx2.gather.
			d.q"
			}
			break;
			case 'q': // 2 strings to match.
			if (NameR[16] != '.')
			break;
			switch (NameR[17]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx2_gather_q_d; // "86.avx2.gather.
			q.d"
			case 'q': // 1 string to match.
			return Intrinsic::x86_avx2_gather_q_q; // "86.avx2.gather.
			q.q"
			}
			break;
			}
			break;
			case 'm': // 2 strings to match.
			if (memcmp(NameR.data()+9, "askload.", 8))
			break;
			switch (NameR[17]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx2_maskload_d; // "86.avx2.maskloa
			d.d"
			case 'q': // 1 string to match.
			return Intrinsic::x86_avx2_maskload_q; // "86.avx2.maskloa
			d.q"
			}
			break;
			case 'p': // 3 strings to match.
			switch (NameR[9]) {
			default: break;
			case 'm': // 1 string to match.
			if (memcmp(NameR.data()+10, "ul.hr.sw", 8))
			break;
			return Intrinsic::x86_avx2_pmul_hr_sw; // "86.avx2.pmul.hr
			.sw"
			case 's': // 2 strings to match.
			switch (NameR[10]) {
			default: break;
			case 'l': // 1 string to match.
			if (memcmp(NameR.data()+11, "l.dq.bs", 7))
			break;
			return Intrinsic::x86_avx2_psll_dq_bs; // "86.avx2.psll.dq
			.bs"
			case 'r': // 1 string to match.
			if (memcmp(NameR.data()+11, "l.dq.bs", 7))
			break;
			return Intrinsic::x86_avx2_psrl_dq_bs; // "86.avx2.psrl.dq
			.bs"
			}
			break;
			}
			break;
			case 'v': // 1 string to match.
			if (memcmp(NameR.data()+9, "perm2i128", 9))
			break;
			return Intrinsic::x86_avx2_vperm2i128; // "86.avx2.vperm2i
			128"
			}
			break;
			case '5': // 11 strings to match.
			if (memcmp(NameR.data()+7, "12.", 3))
			break;
			switch (NameR[10]) {
			default: break;
			case 'k': // 2 strings to match.
			if (memcmp(NameR.data()+11, "ortest", 6))
			break;
			switch (NameR[17]) {
			default: break;
			case 'c': // 1 string to match.
			return Intrinsic::x86_avx512_kortestc; // "86.avx512.korte
			stc"
			case 'z': // 1 string to match.
			return Intrinsic::x86_avx512_kortestz; // "86.avx512.korte
			stz"
			}
			break;
			case 'p': // 5 strings to match.
			if (memcmp(NameR.data()+11, "movzx", 5))
			break;
			switch (NameR[16]) {
			default: break;
			case 'b': // 2 strings to match.
			switch (NameR[17]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx512_pmovzxbd; // "86.avx512.pmovz
			xbd"
			case 'q': // 1 string to match.
			return Intrinsic::x86_avx512_pmovzxbq; // "86.avx512.pmovz
			xbq"
			}
			break;
			case 'd': // 1 string to match.
			if (NameR[17] != 'q')
			break;
			return Intrinsic::x86_avx512_pmovzxdq; // "86.avx512.pmovz
			xdq"
			case 'w': // 2 strings to match.
			switch (NameR[17]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx512_pmovzxwd; // "86.avx512.pmovz
			xwd"
			case 'q': // 1 string to match.
			return Intrinsic::x86_avx512_pmovzxwq; // "86.avx512.pmovz
			xwq"
			}
			break;
			}
			break;
			case 'r': // 4 strings to match.
			if (memcmp(NameR.data()+11, "cp", 2))
			break;
			switch (NameR[13]) {
			default: break;
			case '1': // 2 strings to match.
			if (memcmp(NameR.data()+14, "4.s", 3))
			break;
			switch (NameR[17]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx512_rcp14_sd; // "86.avx512.rcp14
			.sd"
			case 's': // 1 string to match.
			return Intrinsic::x86_avx512_rcp14_ss; // "86.avx512.rcp14
			.ss"
			}
			break;
			case '2': // 2 strings to match.
			if (memcmp(NameR.data()+14, "8.s", 3))
			break;
			switch (NameR[17]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx512_rcp28_sd; // "86.avx512.rcp28
			.sd"
			case 's': // 1 string to match.
			return Intrinsic::x86_avx512_rcp28_ss; // "86.avx512.rcp28
			.ss"
			}
			break;
			}
			break;
			}
			break;
			}
			break;
			case 's': // 13 strings to match.
			if (memcmp(NameR.data()+4, "se", 2))
			break;
			switch (NameR[6]) {
			default: break;
			case '.': // 2 strings to match.
			switch (NameR[7]) {
			default: break;
			case 'c': // 1 string to match.
			if (memcmp(NameR.data()+8, "vttss2si64", 10))
			break;
			return Intrinsic::x86_sse_cvttss2si64; // "86.sse.cvttss2s
			i64"
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+8, "comineq.ss", 10))
			break;
			return Intrinsic::x86_sse_ucomineq_ss; // "86.sse.ucomineq
			.ss"
			}
			break;
			case '2': // 10 strings to match.
			if (NameR[7] != '.')
			break;
			switch (NameR[8]) {
			default: break;
			case 'c': // 3 strings to match.
			switch (NameR[9]) {
			default: break;
			case 'o': // 1 string to match.
			if (memcmp(NameR.data()+10, "mineq.sd", 8))
			break;
			return Intrinsic::x86_sse2_comineq_sd; // "86.sse2.comineq
			.sd"
			case 'v': // 2 strings to match.
			if (memcmp(NameR.data()+10, "ts", 2))
			break;
			switch (NameR[12]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+13, "2si64", 5))
			break;
			return Intrinsic::x86_sse2_cvtsd2si64; // "86.sse2.cvtsd2s
			i64"
			case 'i': // 1 string to match.
			if (memcmp(NameR.data()+13, "642sd", 5))
			break;
			return Intrinsic::x86_sse2_cvtsi642sd; // "86.sse2.cvtsi64
			2sd"
			}
			break;
			}
			break;
			case 'p': // 2 strings to match.
			if (NameR[9] != 's')
			break;
			switch (NameR[10]) {
			default: break;
			case 'l': // 1 string to match.
			if (memcmp(NameR.data()+11, "l.dq.bs", 7))
			break;
			return Intrinsic::x86_sse2_psll_dq_bs; // "86.sse2.psll.dq
			.bs"
			case 'r': // 1 string to match.
			if (memcmp(NameR.data()+11, "l.dq.bs", 7))
			break;
			return Intrinsic::x86_sse2_psrl_dq_bs; // "86.sse2.psrl.dq
			.bs"
			}
			break;
			case 'u': // 5 strings to match.
			if (memcmp(NameR.data()+9, "comi", 4))
			break;
			switch (NameR[13]) {
			default: break;
			case 'e': // 1 string to match.
			if (memcmp(NameR.data()+14, "q.sd", 4))
			break;
			return Intrinsic::x86_sse2_ucomieq_sd; // "86.sse2.ucomieq
			.sd"
			case 'g': // 2 strings to match.
			switch (NameR[14]) {
			default: break;
			case 'e': // 1 string to match.
			if (memcmp(NameR.data()+15, ".sd", 3))
			break;
			return Intrinsic::x86_sse2_ucomige_sd; // "86.sse2.ucomige
			.sd"
			case 't': // 1 string to match.
			if (memcmp(NameR.data()+15, ".sd", 3))
			break;
			return Intrinsic::x86_sse2_ucomigt_sd; // "86.sse2.ucomigt
			.sd"
			}
			break;
			case 'l': // 2 strings to match.
			switch (NameR[14]) {
			default: break;
			case 'e': // 1 string to match.
			if (memcmp(NameR.data()+15, ".sd", 3))
			break;
			return Intrinsic::x86_sse2_ucomile_sd; // "86.sse2.ucomile
			.sd"
			case 't': // 1 string to match.
			if (memcmp(NameR.data()+15, ".sd", 3))
			break;
			return Intrinsic::x86_sse2_ucomilt_sd; // "86.sse2.ucomilt
			.sd"
			}
			break;
			}
			break;
			}
			break;
			case '4': // 1 string to match.
			if (memcmp(NameR.data()+7, "1.extractps", 11))
			break;
			return Intrinsic::x86_sse41_extractps; // "86.sse41.extrac
			tps"
			}
			break;
			}
	break;		break;
	}		case 19: // 44 strings to match.
	}		if (memcmp(NameR.data()+0, "86.", 3))
	return AttributeSet::get(C, ArrayRef<AttributeSet>(AS, NumAttrs));		break;
	}		switch (NameR[3]) {
	#endif // GET_INTRINSIC_ATTRIBUTES		default: break;
			case 'a': // 29 strings to match.
	// Determine intrinsic alias analysis mod/ref behavior.		switch (NameR[4]) {
	#ifdef GET_INTRINSIC_MODREF_BEHAVIOR		default: break;
	assert(iid <= Intrinsic::xcore_zext && "Unknown intrinsic.");		case 'e': // 2 strings to match.
			if (memcmp(NameR.data()+5, "sni.aes", 7))
	static const uint8_t IntrinsicModRefBehavior[] = {		break;
	/* invalid */ UnknownModRefBehavior,		switch (NameR[12]) {
	/* adjust_trampoline */ OnlyReadsArgumentPointees,		default: break;
	/* annotation */ UnknownModRefBehavior,		case 'd': // 1 string to match.
	/* arm_cdp */ UnknownModRefBehavior,		if (memcmp(NameR.data()+13, "eclast", 6))
	/* arm_cdp2 */ UnknownModRefBehavior,		break;
	/* arm_get_fpscr */ DoesNotAccessMemory,		return Intrinsic::x86_aesni_aesdeclast; // "86.aesni.aesdec
	/* arm_ldrexd */ OnlyReadsArgumentPointees,		last"
	/* arm_mcr */ UnknownModRefBehavior,		case 'e': // 1 string to match.
	/* arm_mcr2 */ UnknownModRefBehavior,		if (memcmp(NameR.data()+13, "nclast", 6))
	/* arm_mcrr */ UnknownModRefBehavior,		break;
	/* arm_mcrr2 */ UnknownModRefBehavior,		return Intrinsic::x86_aesni_aesenclast; // "86.aesni.aesenc
	/* arm_mrc */ UnknownModRefBehavior,		last"
	/* arm_mrc2 */ UnknownModRefBehavior,		}
	/* arm_neon_vabds */ DoesNotAccessMemory,		break;
	/* arm_neon_vabdu */ DoesNotAccessMemory,		case 'v': // 27 strings to match.
	/* arm_neon_vabs */ DoesNotAccessMemory,		if (NameR[5] != 'x')
	/* arm_neon_vacged */ DoesNotAccessMemory,		break;
	/* arm_neon_vacgeq */ DoesNotAccessMemory,		switch (NameR[6]) {
	/* arm_neon_vacgtd */ DoesNotAccessMemory,		default: break;
	/* arm_neon_vacgtq */ DoesNotAccessMemory,		case '.': // 8 strings to match.
	/* arm_neon_vaddhn */ DoesNotAccessMemory,		switch (NameR[7]) {
	/* arm_neon_vbsl */ DoesNotAccessMemory,		default: break;
	/* arm_neon_vcls */ DoesNotAccessMemory,		case 'b': // 2 strings to match.
	/* arm_neon_vclz */ DoesNotAccessMemory,		if (memcmp(NameR.data()+8, "lend.p", 6))
	/* arm_neon_vcnt */ DoesNotAccessMemory,		break;
	/* arm_neon_vcvtfp2fxs */ DoesNotAccessMemory,		switch (NameR[14]) {
	/* arm_neon_vcvtfp2fxu */ DoesNotAccessMemory,		default: break;
	/* arm_neon_vcvtfp2hf */ DoesNotAccessMemory,		case 'd': // 1 string to match.
	/* arm_neon_vcvtfxs2fp */ DoesNotAccessMemory,		if (memcmp(NameR.data()+15, ".256", 4))
	/* arm_neon_vcvtfxu2fp */ DoesNotAccessMemory,		break;
	/* arm_neon_vcvthf2fp */ DoesNotAccessMemory,		return Intrinsic::x86_avx_blend_pd_256; // "86.avx.
	/* arm_neon_vhadds */ DoesNotAccessMemory,		blend.pd.256"
	/* arm_neon_vhaddu */ DoesNotAccessMemory,		case 's': // 1 string to match.
	/* arm_neon_vhsubs */ DoesNotAccessMemory,		if (memcmp(NameR.data()+15, ".256", 4))
	/* arm_neon_vhsubu */ DoesNotAccessMemory,		break;
	/* arm_neon_vld1 */ OnlyReadsArgumentPointees,		return Intrinsic::x86_avx_blend_ps_256; // "86.avx.
	/* arm_neon_vld2 */ OnlyReadsArgumentPointees,		blend.ps.256"
	/* arm_neon_vld2lane */ OnlyReadsArgumentPointees,		}
	/* arm_neon_vld3 */ OnlyReadsArgumentPointees,		break;
	/* arm_neon_vld3lane */ OnlyReadsArgumentPointees,		case 'm': // 2 strings to match.
	/* arm_neon_vld4 */ OnlyReadsArgumentPointees,		if (memcmp(NameR.data()+8, "askstore.p", 10))
	/* arm_neon_vld4lane */ OnlyReadsArgumentPointees,		break;
	/* arm_neon_vmaxs */ DoesNotAccessMemory,		switch (NameR[18]) {
	/* arm_neon_vmaxu */ DoesNotAccessMemory,		default: break;
	/* arm_neon_vmins */ DoesNotAccessMemory,		case 'd': // 1 string to match.
	/* arm_neon_vminu */ DoesNotAccessMemory,		return Intrinsic::x86_avx_maskstore_pd; // "86.avx.
	/* arm_neon_vmullp */ DoesNotAccessMemory,		maskstore.pd"
	/* arm_neon_vmulls */ DoesNotAccessMemory,		case 's': // 1 string to match.
	/* arm_neon_vmullu */ DoesNotAccessMemory,		return Intrinsic::x86_avx_maskstore_ps; // "86.avx.
	/* arm_neon_vmulp */ DoesNotAccessMemory,		maskstore.ps"
	/* arm_neon_vpadals */ DoesNotAccessMemory,		}
	/* arm_neon_vpadalu */ DoesNotAccessMemory,		break;
	/* arm_neon_vpadd */ DoesNotAccessMemory,		case 'p': // 1 string to match.
	/* arm_neon_vpaddls */ DoesNotAccessMemory,		if (memcmp(NameR.data()+8, "testnzc.256", 11))
	/* arm_neon_vpaddlu */ DoesNotAccessMemory,		break;
	/* arm_neon_vpmaxs */ DoesNotAccessMemory,		return Intrinsic::x86_avx_ptestnzc_256; // "86.avx.ptestnzc
	/* arm_neon_vpmaxu */ DoesNotAccessMemory,		.256"
	/* arm_neon_vpmins */ DoesNotAccessMemory,		case 'r': // 3 strings to match.
	/* arm_neon_vpminu */ DoesNotAccessMemory,		switch (NameR[8]) {
	/* arm_neon_vqabs */ DoesNotAccessMemory,		default: break;
	/* arm_neon_vqadds */ DoesNotAccessMemory,		case 'o': // 2 strings to match.
	/* arm_neon_vqaddu */ DoesNotAccessMemory,		if (memcmp(NameR.data()+9, "und.p", 5))
	/* arm_neon_vqdmlal */ DoesNotAccessMemory,		break;
	/* arm_neon_vqdmlsl */ DoesNotAccessMemory,		switch (NameR[14]) {
	/* arm_neon_vqdmulh */ DoesNotAccessMemory,		default: break;
	/* arm_neon_vqdmull */ DoesNotAccessMemory,		case 'd': // 1 string to match.
	/* arm_neon_vqmovns */ DoesNotAccessMemory,		if (memcmp(NameR.data()+15, ".256", 4))
	/* arm_neon_vqmovnsu */ DoesNotAccessMemory,		break;
	/* arm_neon_vqmovnu */ DoesNotAccessMemory,		return Intrinsic::x86_avx_round_pd_256; // "86.avx.
	/* arm_neon_vqneg */ DoesNotAccessMemory,		round.pd.256"
	/* arm_neon_vqrdmulh */ DoesNotAccessMemory,		case 's': // 1 string to match.
	/* arm_neon_vqrshiftns */ DoesNotAccessMemory,		if (memcmp(NameR.data()+15, ".256", 4))
	/* arm_neon_vqrshiftnsu */ DoesNotAccessMemory,		break;
	/* arm_neon_vqrshiftnu */ DoesNotAccessMemory,		return Intrinsic::x86_avx_round_ps_256; // "86.avx.
	/* arm_neon_vqrshifts */ DoesNotAccessMemory,		round.ps.256"
	/* arm_neon_vqrshiftu */ DoesNotAccessMemory,		}
	/* arm_neon_vqshiftns */ DoesNotAccessMemory,		break;
	/* arm_neon_vqshiftnsu */ DoesNotAccessMemory,		case 's': // 1 string to match.
	/* arm_neon_vqshiftnu */ DoesNotAccessMemory,		if (memcmp(NameR.data()+9, "qrt.ps.256", 10))
	/* arm_neon_vqshifts */ DoesNotAccessMemory,		break;
	/* arm_neon_vqshiftsu */ DoesNotAccessMemory,		return Intrinsic::x86_avx_rsqrt_ps_256; // "86.avx.
	/* arm_neon_vqshiftu */ DoesNotAccessMemory,		rsqrt.ps.256"
	/* arm_neon_vqsubs */ DoesNotAccessMemory,		}
	/* arm_neon_vqsubu */ DoesNotAccessMemory,		break;
	/* arm_neon_vraddhn */ DoesNotAccessMemory,		}
	/* arm_neon_vrecpe */ DoesNotAccessMemory,		break;
	/* arm_neon_vrecps */ DoesNotAccessMemory,		case '2': // 15 strings to match.
	/* arm_neon_vrhadds */ DoesNotAccessMemory,		if (NameR[7] != '.')
	/* arm_neon_vrhaddu */ DoesNotAccessMemory,		break;
	/* arm_neon_vrshiftn */ DoesNotAccessMemory,		switch (NameR[8]) {
	/* arm_neon_vrshifts */ DoesNotAccessMemory,		default: break;
	/* arm_neon_vrshiftu */ DoesNotAccessMemory,		case 'g': // 4 strings to match.
	/* arm_neon_vrsqrte */ DoesNotAccessMemory,		if (memcmp(NameR.data()+9, "ather.", 6))
	/* arm_neon_vrsqrts */ DoesNotAccessMemory,		break;
	/* arm_neon_vrsubhn */ DoesNotAccessMemory,		switch (NameR[15]) {
	/* arm_neon_vshiftins */ DoesNotAccessMemory,		default: break;
	/* arm_neon_vshiftls */ DoesNotAccessMemory,		case 'd': // 2 strings to match.
	/* arm_neon_vshiftlu */ DoesNotAccessMemory,		if (memcmp(NameR.data()+16, ".p", 2))
	/* arm_neon_vshiftn */ DoesNotAccessMemory,		break;
	/* arm_neon_vshifts */ DoesNotAccessMemory,		switch (NameR[18]) {
	/* arm_neon_vshiftu */ DoesNotAccessMemory,		default: break;
	/* arm_neon_vst1 */ OnlyAccessesArgumentPointees,		case 'd': // 1 string to match.
	/* arm_neon_vst2 */ OnlyAccessesArgumentPointees,		return Intrinsic::x86_avx2_gather_d_pd; // "86.avx2
	/* arm_neon_vst2lane */ OnlyAccessesArgumentPointees,		.gather.d.pd"
	/* arm_neon_vst3 */ OnlyAccessesArgumentPointees,		case 's': // 1 string to match.
	/* arm_neon_vst3lane */ OnlyAccessesArgumentPointees,		return Intrinsic::x86_avx2_gather_d_ps; // "86.avx2
	/* arm_neon_vst4 */ OnlyAccessesArgumentPointees,		.gather.d.ps"
	/* arm_neon_vst4lane */ OnlyAccessesArgumentPointees,		}
	/* arm_neon_vsubhn */ DoesNotAccessMemory,		break;
	/* arm_neon_vtbl1 */ DoesNotAccessMemory,		case 'q': // 2 strings to match.
	/* arm_neon_vtbl2 */ DoesNotAccessMemory,		if (memcmp(NameR.data()+16, ".p", 2))
	/* arm_neon_vtbl3 */ DoesNotAccessMemory,		break;
	/* arm_neon_vtbl4 */ DoesNotAccessMemory,		switch (NameR[18]) {
	/* arm_neon_vtbx1 */ DoesNotAccessMemory,		default: break;
	/* arm_neon_vtbx2 */ DoesNotAccessMemory,		case 'd': // 1 string to match.
	/* arm_neon_vtbx3 */ DoesNotAccessMemory,		return Intrinsic::x86_avx2_gather_q_pd; // "86.avx2
	/* arm_neon_vtbx4 */ DoesNotAccessMemory,		.gather.q.pd"
	/* arm_qadd */ DoesNotAccessMemory,		case 's': // 1 string to match.
	/* arm_qsub */ DoesNotAccessMemory,		return Intrinsic::x86_avx2_gather_q_ps; // "86.avx2
	/* arm_set_fpscr */ UnknownModRefBehavior,		.gather.q.ps"
	/* arm_ssat */ DoesNotAccessMemory,		}
	/* arm_strexd */ OnlyAccessesArgumentPointees,		break;
	/* arm_thread_pointer */ DoesNotAccessMemory,		}
	/* arm_usat */ DoesNotAccessMemory,		break;
	/* arm_vcvtr */ DoesNotAccessMemory,		case 'm': // 2 strings to match.
	/* arm_vcvtru */ DoesNotAccessMemory,		if (memcmp(NameR.data()+9, "askstore.", 9))
	/* bswap */ DoesNotAccessMemory,		break;
	/* ceil */ OnlyReadsMemory,		switch (NameR[18]) {
	/* convert_from_fp16 */ DoesNotAccessMemory,		default: break;
	/* convert_to_fp16 */ DoesNotAccessMemory,		case 'd': // 1 string to match.
	/* convertff */ UnknownModRefBehavior,		return Intrinsic::x86_avx2_maskstore_d; // "86.avx2
	/* convertfsi */ UnknownModRefBehavior,		.maskstore.d"
	/* convertfui */ UnknownModRefBehavior,		case 'q': // 1 string to match.
	/* convertsif */ UnknownModRefBehavior,		return Intrinsic::x86_avx2_maskstore_q; // "86.avx2
	/* convertss */ UnknownModRefBehavior,		.maskstore.q"
	/* convertsu */ UnknownModRefBehavior,		}
	/* convertuif */ UnknownModRefBehavior,		break;
	/* convertus */ UnknownModRefBehavior,		case 'p': // 8 strings to match.
	/* convertuu */ UnknownModRefBehavior,		switch (NameR[9]) {
	/* cos */ OnlyReadsMemory,		default: break;
	/* ctlz */ DoesNotAccessMemory,		case 'b': // 2 strings to match.
	/* ctpop */ DoesNotAccessMemory,		if (memcmp(NameR.data()+10, "lendd.", 6))
	/* cttz */ DoesNotAccessMemory,		break;
	/* cuda_syncthreads */ UnknownModRefBehavior,		switch (NameR[16]) {
	/* dbg_declare */ DoesNotAccessMemory,		default: break;
	/* dbg_value */ DoesNotAccessMemory,		case '1': // 1 string to match.
	/* debugtrap */ UnknownModRefBehavior,		if (memcmp(NameR.data()+17, "28", 2))
	/* donothing */ DoesNotAccessMemory,		break;
	/* eh_dwarf_cfa */ UnknownModRefBehavior,		return Intrinsic::x86_avx2_pblendd_128; // "86.avx2
	/* eh_return_i32 */ UnknownModRefBehavior,		.pblendd.128"
	/* eh_return_i64 */ UnknownModRefBehavior,		case '2': // 1 string to match.
	/* eh_sjlj_callsite */ DoesNotAccessMemory,		if (memcmp(NameR.data()+17, "56", 2))
	/* eh_sjlj_functioncontext */ UnknownModRefBehavior,		break;
	/* eh_sjlj_longjmp */ UnknownModRefBehavior,		return Intrinsic::x86_avx2_pblendd_256; // "86.avx2
	/* eh_sjlj_lsda */ DoesNotAccessMemory,		.pblendd.256"
	/* eh_sjlj_setjmp */ UnknownModRefBehavior,		}
	/* eh_typeid_for */ DoesNotAccessMemory,		break;
	/* eh_unwind_init */ UnknownModRefBehavior,		case 'm': // 1 string to match.
	/* exp */ OnlyReadsMemory,		if (memcmp(NameR.data()+10, "add.ub.sw", 9))
	/* exp2 */ OnlyReadsMemory,		break;
	/* expect */ DoesNotAccessMemory,		return Intrinsic::x86_avx2_pmadd_ub_sw; // "86.avx2
	/* fabs */ OnlyReadsMemory,		.pmadd.ub.sw"
	/* floor */ OnlyReadsMemory,		case 's': // 5 strings to match.
	/* flt_rounds */ UnknownModRefBehavior,		switch (NameR[10]) {
	/* fma */ DoesNotAccessMemory,		default: break;
	/* fmuladd */ DoesNotAccessMemory,		case 'l': // 2 strings to match.
	/* frameaddress */ DoesNotAccessMemory,		if (memcmp(NameR.data()+11, "lv.", 3))
	/* gcread */ OnlyReadsArgumentPointees,		break;
	/* gcroot */ UnknownModRefBehavior,		switch (NameR[14]) {
	/* gcwrite */ OnlyAccessesArgumentPointees,		default: break;
	/* hexagon_A2_abs */ DoesNotAccessMemory,		case 'd': // 1 string to match.
	/* hexagon_A2_absp */ DoesNotAccessMemory,		if (memcmp(NameR.data()+15, ".256", 4))
	/* hexagon_A2_abssat */ DoesNotAccessMemory,		break;
	/* hexagon_A2_add */ DoesNotAccessMemory,		return Intrinsic::x86_avx2_psllv_d_256; // "86.avx2
	/* hexagon_A2_addh_h16_hh */ DoesNotAccessMemory,		.psllv.d.256"
			case 'q': // 1 string to match.
			if (memcmp(NameR.data()+15, ".256", 4))
			break;
			return Intrinsic::x86_avx2_psllv_q_256; // "86.avx2
			.psllv.q.256"
			}
			break;
			case 'r': // 3 strings to match.
			switch (NameR[11]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(NameR.data()+12, "v.d.256", 7))
			break;
			return Intrinsic::x86_avx2_psrav_d_256; // "86.avx2
			.psrav.d.256"
			case 'l': // 2 strings to match.
			if (memcmp(NameR.data()+12, "v.", 2))
			break;
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+15, ".256", 4))
			break;
			return Intrinsic::x86_avx2_psrlv_d_256; // "86.avx2
			.psrlv.d.256"
			case 'q': // 1 string to match.
			if (memcmp(NameR.data()+15, ".256", 4))
			break;
			return Intrinsic::x86_avx2_psrlv_q_256; // "86.avx2
			.psrlv.q.256"
			}
			break;
			}
			break;
			}
			break;
			}
			break;
			case 'v': // 1 string to match.
			if (memcmp(NameR.data()+9, "inserti128", 10))
			break;
			return Intrinsic::x86_avx2_vinserti128; // "86.avx2.vinsert
			i128"
			}
			break;
			case '5': // 4 strings to match.
			if (memcmp(NameR.data()+7, "12.cvt", 6))
			break;
			switch (NameR[13]) {
			default: break;
			case 's': // 2 strings to match.
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+15, "2usi", 4))
			break;
			return Intrinsic::x86_avx512_cvtsd2usi; // "86.avx5
			12.cvtsd2usi"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+15, "2usi", 4))
			break;
			return Intrinsic::x86_avx512_cvtss2usi; // "86.avx5
			12.cvtss2usi"
			}
			break;
			case 'u': // 2 strings to match.
			if (memcmp(NameR.data()+14, "si2s", 4))
			break;
			switch (NameR[18]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx512_cvtusi2sd; // "86.avx5
			12.cvtusi2sd"
			case 's': // 1 string to match.
			return Intrinsic::x86_avx512_cvtusi2ss; // "86.avx5
			12.cvtusi2ss"
			}
			break;
			}
			break;
			}
			break;
			}
			break;
			case 'f': // 4 strings to match.
			if (memcmp(NameR.data()+4, "ma.vfm", 6))
			break;
			switch (NameR[10]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(NameR.data()+11, "ddsub.p", 7))
			break;
			switch (NameR[18]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_fma_vfmaddsub_pd; // "86.fma.vfmaddsu
			b.pd"
			case 's': // 1 string to match.
			return Intrinsic::x86_fma_vfmaddsub_ps; // "86.fma.vfmaddsu
			b.ps"
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(NameR.data()+11, "ubadd.p", 7))
			break;
			switch (NameR[18]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_fma_vfmsubadd_pd; // "86.fma.vfmsubad
			d.pd"
			case 's': // 1 string to match.
			return Intrinsic::x86_fma_vfmsubadd_ps; // "86.fma.vfmsubad
			d.ps"
			}
			break;
			}
			break;
			case 's': // 9 strings to match.
			if (NameR[4] != 's')
			break;
			switch (NameR[5]) {
			default: break;
			case 'e': // 5 strings to match.
			switch (NameR[6]) {
			default: break;
			case '2': // 3 strings to match.
			if (NameR[7] != '.')
			break;
			switch (NameR[8]) {
			default: break;
			case 'c': // 1 string to match.
			if (memcmp(NameR.data()+9, "vttsd2si64", 10))
			break;
			return Intrinsic::x86_sse2_cvttsd2si64; // "86.sse2.cvttsd2
			si64"
			case 'm': // 1 string to match.
			if (memcmp(NameR.data()+9, "askmov.dqu", 10))
			break;
			return Intrinsic::x86_sse2_maskmov_dqu; // "86.sse2.maskmov
			.dqu"
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+9, "comineq.sd", 10))
			break;
			return Intrinsic::x86_sse2_ucomineq_sd; // "86.sse2.ucomine
			q.sd"
			}
			break;
			case '4': // 2 strings to match.
			switch (NameR[7]) {
			default: break;
			case '1': // 1 string to match.
			if (memcmp(NameR.data()+8, ".phminposuw", 11))
			break;
			return Intrinsic::x86_sse41_phminposuw; // "86.sse41.phminp
			osuw"
			case '2': // 1 string to match.
			if (memcmp(NameR.data()+8, ".crc32.32.8", 11))
			break;
			return Intrinsic::x86_sse42_crc32_32_8; // "86.sse42.crc32.
			32.8"
			}
			break;
			}
			break;
			case 's': // 4 strings to match.
			if (memcmp(NameR.data()+6, "e3.p", 4))
			break;
			switch (NameR[10]) {
			default: break;
			case 'a': // 3 strings to match.
			if (memcmp(NameR.data()+11, "bs.", 3))
			break;
			switch (NameR[14]) {
			default: break;
			case 'b': // 1 string to match.
			if (memcmp(NameR.data()+15, ".128", 4))
			break;
			return Intrinsic::x86_ssse3_pabs_b_128; // "86.ssse3.pabs.b
			.128"
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+15, ".128", 4))
			break;
			return Intrinsic::x86_ssse3_pabs_d_128; // "86.ssse3.pabs.d
			.128"
			case 'w': // 1 string to match.
			if (memcmp(NameR.data()+15, ".128", 4))
			break;
			return Intrinsic::x86_ssse3_pabs_w_128; // "86.ssse3.pabs.w
			.128"
			}
			break;
			case 'm': // 1 string to match.
			if (memcmp(NameR.data()+11, "ul.hr.sw", 8))
			break;
			return Intrinsic::x86_ssse3_pmul_hr_sw; // "86.ssse3.pmul.h
			r.sw"
			}
			break;
			}
			break;
			case 'x': // 2 strings to match.
			if (memcmp(NameR.data()+4, "op.vfrcz.p", 10))
			break;
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+15, ".256", 4))
			break;
			return Intrinsic::x86_xop_vfrcz_pd_256; // "86.xop.vfrcz.pd
			.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+15, ".256", 4))
			break;
			return Intrinsic::x86_xop_vfrcz_ps_256; // "86.xop.vfrcz.ps
			.256"
			}
			break;
			}
			break;
			case 20: // 57 strings to match.
			if (memcmp(NameR.data()+0, "86.", 3))
			break;
			switch (NameR[3]) {
			default: break;
			case 'a': // 33 strings to match.
			if (memcmp(NameR.data()+4, "vx", 2))
			break;
			switch (NameR[6]) {
			default: break;
			case '.': // 20 strings to match.
			switch (NameR[7]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(NameR.data()+8, "ddsub.p", 7))
			break;
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+16, ".256", 4))
			break;
			return Intrinsic::x86_avx_addsub_pd_256; // "86.avx.addsub.p
			d.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+16, ".256", 4))
			break;
			return Intrinsic::x86_avx_addsub_ps_256; // "86.avx.addsub.p
			s.256"
			}
			break;
			case 'b': // 2 strings to match.
			if (memcmp(NameR.data()+8, "lendv.p", 7))
			break;
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+16, ".256", 4))
			break;
			return Intrinsic::x86_avx_blendv_pd_256; // "86.avx.blendv.p
			d.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+16, ".256", 4))
			break;
			return Intrinsic::x86_avx_blendv_ps_256; // "86.avx.blendv.p
			s.256"
			}
			break;
			case 'c': // 4 strings to match.
			if (memcmp(NameR.data()+8, "vt", 2))
			break;
			switch (NameR[10]) {
			default: break;
			case '.': // 2 strings to match.
			if (NameR[11] != 'p')
			break;
			switch (NameR[12]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+13, "2dq.256", 7))
			break;
			return Intrinsic::x86_avx_cvt_pd2dq_256; // "86.avx.
			cvt.pd2dq.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+13, "2dq.256", 7))
			break;
			return Intrinsic::x86_avx_cvt_ps2dq_256; // "86.avx.
			cvt.ps2dq.256"
			}
			break;
			case 'd': // 2 strings to match.
			if (memcmp(NameR.data()+11, "q2.p", 4))
			break;
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+16, ".256", 4))
			break;
			return Intrinsic::x86_avx_cvtdq2_pd_256; // "86.avx.
			cvtdq2.pd.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+16, ".256", 4))
			break;
			return Intrinsic::x86_avx_cvtdq2_ps_256; // "86.avx.
			cvtdq2.ps.256"
			}
			break;
			}
			break;
			case 'm': // 2 strings to match.
			if (memcmp(NameR.data()+8, "ovmsk.p", 7))
			break;
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+16, ".256", 4))
			break;
			return Intrinsic::x86_avx_movmsk_pd_256; // "86.avx.movmsk.p
			d.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+16, ".256", 4))
			break;
			return Intrinsic::x86_avx_movmsk_ps_256; // "86.avx.movmsk.p
			s.256"
			}
			break;
			case 's': // 3 strings to match.
			if (memcmp(NameR.data()+8, "toreu.", 6))
			break;
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+15, "q.256", 5))
			break;
			return Intrinsic::x86_avx_storeu_dq_256; // "86.avx.storeu.d
			q.256"
			case 'p': // 2 strings to match.
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+16, ".256", 4))
			break;
			return Intrinsic::x86_avx_storeu_pd_256; // "86.avx.
			storeu.pd.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+16, ".256", 4))
			break;
			return Intrinsic::x86_avx_storeu_ps_256; // "86.avx.
			storeu.ps.256"
			}
			break;
			}
			break;
			case 'v': // 7 strings to match.
			switch (NameR[8]) {
			default: break;
			case 'b': // 1 string to match.
			if (memcmp(NameR.data()+9, "roadcast.ss", 11))
			break;
			return Intrinsic::x86_avx_vbroadcast_ss; // "86.avx.vbroadca
			st.ss"
			case 'p': // 2 strings to match.
			if (memcmp(NameR.data()+9, "ermilvar.p", 10))
			break;
			switch (NameR[19]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx_vpermilvar_pd; // "86.avx.
			vpermilvar.pd"
			case 's': // 1 string to match.
			return Intrinsic::x86_avx_vpermilvar_ps; // "86.avx.
			vpermilvar.ps"
			}
			break;
			case 't': // 4 strings to match.
			if (memcmp(NameR.data()+9, "est", 3))
			break;
			switch (NameR[12]) {
			default: break;
			case 'c': // 2 strings to match.
			if (memcmp(NameR.data()+13, ".p", 2))
			break;
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+16, ".256", 4))
			break;
			return Intrinsic::x86_avx_vtestc_pd_256; // "86.avx.
			vtestc.pd.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+16, ".256", 4))
			break;
			return Intrinsic::x86_avx_vtestc_ps_256; // "86.avx.
			vtestc.ps.256"
			}
			break;
			case 'z': // 2 strings to match.
			if (memcmp(NameR.data()+13, ".p", 2))
			break;
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+16, ".256", 4))
			break;
			return Intrinsic::x86_avx_vtestz_pd_256; // "86.avx.
			vtestz.pd.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+16, ".256", 4))
			break;
			return Intrinsic::x86_avx_vtestz_ps_256; // "86.avx.
			vtestz.ps.256"
			}
			break;
			}
			break;
			}
			break;
			}
			break;
			case '2': // 1 string to match.
			if (memcmp(NameR.data()+7, ".vextracti128", 13))
			break;
			return Intrinsic::x86_avx2_vextracti128; // "86.avx2.vextrac
			ti128"
			case '5': // 12 strings to match.
			if (memcmp(NameR.data()+7, "12.", 3))
			break;
			switch (NameR[10]) {
			default: break;
			case 'c': // 2 strings to match.
			if (memcmp(NameR.data()+11, "vtts", 4))
			break;
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+16, "2usi", 4))
			break;
			return Intrinsic::x86_avx512_cvttsd2usi; // "86.avx512.cvtts
			d2usi"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+16, "2usi", 4))
			break;
			return Intrinsic::x86_avx512_cvttss2usi; // "86.avx512.cvtts
			s2usi"
			}
			break;
			case 'm': // 4 strings to match.
			switch (NameR[11]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(NameR.data()+12, "x.p", 3))
			break;
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+16, ".512", 4))
			break;
			return Intrinsic::x86_avx512_max_pd_512; // "86.avx5
			12.max.pd.512"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+16, ".512", 4))
			break;
			return Intrinsic::x86_avx512_max_ps_512; // "86.avx5
			12.max.ps.512"
			}
			break;
			case 'i': // 2 strings to match.
			if (memcmp(NameR.data()+12, "n.p", 3))
			break;
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+16, ".512", 4))
			break;
			return Intrinsic::x86_avx512_min_pd_512; // "86.avx5
			12.min.pd.512"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+16, ".512", 4))
			break;
			return Intrinsic::x86_avx512_min_ps_512; // "86.avx5
			12.min.ps.512"
			}
			break;
			}
			break;
			case 'p': // 2 strings to match.
			if (NameR[11] != 's')
			break;
			switch (NameR[12]) {
			default: break;
			case 'l': // 1 string to match.
			if (memcmp(NameR.data()+13, "l.dq.bs", 7))
			break;
			return Intrinsic::x86_avx512_psll_dq_bs; // "86.avx512.psll.
			dq.bs"
			case 'r': // 1 string to match.
			if (memcmp(NameR.data()+13, "l.dq.bs", 7))
			break;
			return Intrinsic::x86_avx512_psrl_dq_bs; // "86.avx512.psrl.
			dq.bs"
			}
			break;
			case 'r': // 4 strings to match.
			if (memcmp(NameR.data()+11, "sqrt", 4))
			break;
			switch (NameR[15]) {
			default: break;
			case '1': // 2 strings to match.
			if (memcmp(NameR.data()+16, "4.s", 3))
			break;
			switch (NameR[19]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx512_rsqrt14_sd; // "86.avx5
			12.rsqrt14.sd"
			case 's': // 1 string to match.
			return Intrinsic::x86_avx512_rsqrt14_ss; // "86.avx5
			12.rsqrt14.ss"
			}
			break;
			case '2': // 2 strings to match.
			if (memcmp(NameR.data()+16, "8.s", 3))
			break;
			switch (NameR[19]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx512_rsqrt28_sd; // "86.avx5
			12.rsqrt28.sd"
			case 's': // 1 string to match.
			return Intrinsic::x86_avx512_rsqrt28_ss; // "86.avx5
			12.rsqrt28.ss"
			}
			break;
			}
			break;
			}
			break;
			}
			break;
			case 'f': // 8 strings to match.
			if (memcmp(NameR.data()+4, "ma.vfm", 6))
			break;
			switch (NameR[10]) {
			default: break;
			case 'a': // 4 strings to match.
			if (memcmp(NameR.data()+11, "dd.p", 4))
			break;
			switch (NameR[15]) {
			default: break;
			case 'd': // 2 strings to match.
			if (NameR[16] != '.')
			break;
			switch (NameR[17]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(NameR.data()+18, "56", 2))
			break;
			return Intrinsic::x86_fma_vfmadd_pd_256; // "86.fma.vfmadd.p
			d.256"
			case '5': // 1 string to match.
			if (memcmp(NameR.data()+18, "12", 2))
			break;
			return Intrinsic::x86_fma_vfmadd_pd_512; // "86.fma.vfmadd.p
			d.512"
			}
			break;
			case 's': // 2 strings to match.
			if (NameR[16] != '.')
			break;
			switch (NameR[17]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(NameR.data()+18, "56", 2))
			break;
			return Intrinsic::x86_fma_vfmadd_ps_256; // "86.fma.vfmadd.p
			s.256"
			case '5': // 1 string to match.
			if (memcmp(NameR.data()+18, "12", 2))
			break;
			return Intrinsic::x86_fma_vfmadd_ps_512; // "86.fma.vfmadd.p
			s.512"
			}
			break;
			}
			break;
			case 's': // 4 strings to match.
			if (memcmp(NameR.data()+11, "ub.p", 4))
			break;
			switch (NameR[15]) {
			default: break;
			case 'd': // 2 strings to match.
			if (NameR[16] != '.')
			break;
			switch (NameR[17]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(NameR.data()+18, "56", 2))
			break;
			return Intrinsic::x86_fma_vfmsub_pd_256; // "86.fma.vfmsub.p
			d.256"
			case '5': // 1 string to match.
			if (memcmp(NameR.data()+18, "12", 2))
			break;
			return Intrinsic::x86_fma_vfmsub_pd_512; // "86.fma.vfmsub.p
			d.512"
			}
			break;
			case 's': // 2 strings to match.
			if (NameR[16] != '.')
			break;
			switch (NameR[17]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(NameR.data()+18, "56", 2))
			break;
			return Intrinsic::x86_fma_vfmsub_ps_256; // "86.fma.vfmsub.p
			s.256"
			case '5': // 1 string to match.
			if (memcmp(NameR.data()+18, "12", 2))
			break;
			return Intrinsic::x86_fma_vfmsub_ps_512; // "86.fma.vfmsub.p
			s.512"
			}
			break;
			}
			break;
			}
			break;
			case 's': // 16 strings to match.
			if (NameR[4] != 's')
			break;
			switch (NameR[5]) {
			default: break;
			case 'e': // 7 strings to match.
			switch (NameR[6]) {
			default: break;
			case '2': // 4 strings to match.
			if (memcmp(NameR.data()+7, ".p", 2))
			break;
			switch (NameR[9]) {
			default: break;
			case 'a': // 3 strings to match.
			if (memcmp(NameR.data()+10, "ck", 2))
			break;
			switch (NameR[12]) {
			default: break;
			case 's': // 2 strings to match.
			if (NameR[13] != 's')
			break;
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+15, "w.128", 5))
			break;
			return Intrinsic::x86_sse2_packssdw_128; // "86.sse2
			.packssdw.128"
			case 'w': // 1 string to match.
			if (memcmp(NameR.data()+15, "b.128", 5))
			break;
			return Intrinsic::x86_sse2_packsswb_128; // "86.sse2
			.packsswb.128"
			}
			break;
			case 'u': // 1 string to match.
			if (memcmp(NameR.data()+13, "swb.128", 7))
			break;
			return Intrinsic::x86_sse2_packuswb_128; // "86.sse2
			.packuswb.128"
			}
			break;
			case 'm': // 1 string to match.
			if (memcmp(NameR.data()+10, "ovmskb.128", 10))
			break;
			return Intrinsic::x86_sse2_pmovmskb_128; // "86.sse2.pmovmsk
			b.128"
			}
			break;
			case '4': // 3 strings to match.
			if (memcmp(NameR.data()+7, "2.crc32.", 8))
			break;
			switch (NameR[15]) {
			default: break;
			case '3': // 2 strings to match.
			if (memcmp(NameR.data()+16, "2.", 2))
			break;
			switch (NameR[18]) {
			default: break;
			case '1': // 1 string to match.
			if (NameR[19] != '6')
			break;
			return Intrinsic::x86_sse42_crc32_32_16; // "86.sse4
			2.crc32.32.16"
			case '3': // 1 string to match.
			if (NameR[19] != '2')
			break;
			return Intrinsic::x86_sse42_crc32_32_32; // "86.sse4
			2.crc32.32.32"
			}
			break;
			case '6': // 1 string to match.
			if (memcmp(NameR.data()+16, "4.64", 4))
			break;
			return Intrinsic::x86_sse42_crc32_64_64; // "86.sse42.crc32.
			64.64"
			}
			break;
			}
			break;
			case 's': // 9 strings to match.
			if (memcmp(NameR.data()+6, "e3.p", 4))
			break;
			switch (NameR[10]) {
			default: break;
			case 'h': // 4 strings to match.
			switch (NameR[11]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(NameR.data()+12, "dd.", 3))
			break;
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+16, ".128", 4))
			break;
			return Intrinsic::x86_ssse3_phadd_d_128; // "86.ssse
			3.phadd.d.128"
			case 'w': // 1 string to match.
			if (memcmp(NameR.data()+16, ".128", 4))
			break;
			return Intrinsic::x86_ssse3_phadd_w_128; // "86.ssse
			3.phadd.w.128"
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(NameR.data()+12, "ub.", 3))
			break;
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+16, ".128", 4))
			break;
			return Intrinsic::x86_ssse3_phsub_d_128; // "86.ssse
			3.phsub.d.128"
			case 'w': // 1 string to match.
			if (memcmp(NameR.data()+16, ".128", 4))
			break;
			return Intrinsic::x86_ssse3_phsub_w_128; // "86.ssse
			3.phsub.w.128"
			}
			break;
			}
			break;
			case 'm': // 1 string to match.
			if (memcmp(NameR.data()+11, "add.ub.sw", 9))
			break;
			return Intrinsic::x86_ssse3_pmadd_ub_sw; // "86.ssse3.pmadd.
			ub.sw"
			case 's': // 4 strings to match.
			switch (NameR[11]) {
			default: break;
			case 'h': // 1 string to match.
			if (memcmp(NameR.data()+12, "uf.b.128", 8))
			break;
			return Intrinsic::x86_ssse3_pshuf_b_128; // "86.ssse3.pshuf.
			b.128"
			case 'i': // 3 strings to match.
			if (memcmp(NameR.data()+12, "gn.", 3))
			break;
			switch (NameR[15]) {
			default: break;
			case 'b': // 1 string to match.
			if (memcmp(NameR.data()+16, ".128", 4))
			break;
			return Intrinsic::x86_ssse3_psign_b_128; // "86.ssse
			3.psign.b.128"
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+16, ".128", 4))
			break;
			return Intrinsic::x86_ssse3_psign_d_128; // "86.ssse
			3.psign.d.128"
			case 'w': // 1 string to match.
			if (memcmp(NameR.data()+16, ".128", 4))
			break;
			return Intrinsic::x86_ssse3_psign_w_128; // "86.ssse
			3.psign.w.128"
			}
			break;
			}
			break;
			}
			break;
			}
			break;
			}
			break;
			case 21: // 28 strings to match.
			if (memcmp(NameR.data()+0, "86.", 3))
			break;
			switch (NameR[3]) {
			default: break;
			case 'a': // 12 strings to match.
			if (memcmp(NameR.data()+4, "vx", 2))
			break;
			switch (NameR[6]) {
			default: break;
			case '.': // 4 strings to match.
			if (memcmp(NameR.data()+7, "cvt", 3))
			break;
			switch (NameR[10]) {
			default: break;
			case '.': // 2 strings to match.
			if (NameR[11] != 'p')
			break;
			switch (NameR[12]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+13, "2.ps.256", 8))
			break;
			return Intrinsic::x86_avx_cvt_pd2_ps_256; // "86.avx.
			cvt.pd2.ps.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+13, "2.pd.256", 8))
			break;
			return Intrinsic::x86_avx_cvt_ps2_pd_256; // "86.avx.
			cvt.ps2.pd.256"
			}
			break;
			case 't': // 2 strings to match.
			if (memcmp(NameR.data()+11, ".p", 2))
			break;
			switch (NameR[13]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+14, "2dq.256", 7))
			break;
			return Intrinsic::x86_avx_cvtt_pd2dq_256; // "86.avx.
			cvtt.pd2dq.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+14, "2dq.256", 7))
			break;
			return Intrinsic::x86_avx_cvtt_ps2dq_256; // "86.avx.
			cvtt.ps2dq.256"
			}
			break;
			}
			break;
			case '5': // 8 strings to match.
			if (memcmp(NameR.data()+7, "12.", 3))
			break;
			switch (NameR[10]) {
			default: break;
			case 'c': // 4 strings to match.
			if (memcmp(NameR.data()+11, "vt", 2))
			break;
			switch (NameR[13]) {
			default: break;
			case 's': // 2 strings to match.
			switch (NameR[14]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+15, "2usi64", 6))
			break;
			return Intrinsic::x86_avx512_cvtsd2usi64; // "86.avx5
			12.cvtsd2usi64"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+15, "2usi64", 6))
			break;
			return Intrinsic::x86_avx512_cvtss2usi64; // "86.avx5
			12.cvtss2usi64"
			}
			break;
			case 'u': // 2 strings to match.
			if (memcmp(NameR.data()+14, "si642s", 6))
			break;
			switch (NameR[20]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx512_cvtusi642sd; // "86.avx5
			12.cvtusi642sd"
			case 's': // 1 string to match.
			return Intrinsic::x86_avx512_cvtusi642ss; // "86.avx5
			12.cvtusi642ss"
			}
			break;
			}
			break;
			case 'r': // 2 strings to match.
			if (memcmp(NameR.data()+11, "ndscale.s", 9))
			break;
			switch (NameR[20]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx512_rndscale_sd; // "86.avx5
			12.rndscale.sd"
			case 's': // 1 string to match.
			return Intrinsic::x86_avx512_rndscale_ss; // "86.avx5
			12.rndscale.ss"
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(NameR.data()+11, "qrt.p", 5))
			break;
			switch (NameR[16]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+17, ".512", 4))
			break;
			return Intrinsic::x86_avx512_sqrt_pd_512; // "86.avx5
			12.sqrt.pd.512"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+17, ".512", 4))
			break;
			return Intrinsic::x86_avx512_sqrt_ps_512; // "86.avx5
			12.sqrt.ps.512"
			}
			break;
			}
			break;
			}
			break;
			case 'f': // 8 strings to match.
			if (memcmp(NameR.data()+4, "ma.vfnm", 7))
			break;
			switch (NameR[11]) {
			default: break;
			case 'a': // 4 strings to match.
			if (memcmp(NameR.data()+12, "dd.p", 4))
			break;
			switch (NameR[16]) {
			default: break;
			case 'd': // 2 strings to match.
			if (NameR[17] != '.')
			break;
			switch (NameR[18]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(NameR.data()+19, "56", 2))
			break;
			return Intrinsic::x86_fma_vfnmadd_pd_256; // "86.fma.
			vfnmadd.pd.256"
			case '5': // 1 string to match.
			if (memcmp(NameR.data()+19, "12", 2))
			break;
			return Intrinsic::x86_fma_vfnmadd_pd_512; // "86.fma.
			vfnmadd.pd.512"
			}
			break;
			case 's': // 2 strings to match.
			if (NameR[17] != '.')
			break;
			switch (NameR[18]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(NameR.data()+19, "56", 2))
			break;
			return Intrinsic::x86_fma_vfnmadd_ps_256; // "86.fma.
			vfnmadd.ps.256"
			case '5': // 1 string to match.
			if (memcmp(NameR.data()+19, "12", 2))
			break;
			return Intrinsic::x86_fma_vfnmadd_ps_512; // "86.fma.
			vfnmadd.ps.512"
			}
			break;
			}
			break;
			case 's': // 4 strings to match.
			if (memcmp(NameR.data()+12, "ub.p", 4))
			break;
			switch (NameR[16]) {
			default: break;
			case 'd': // 2 strings to match.
			if (NameR[17] != '.')
			break;
			switch (NameR[18]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(NameR.data()+19, "56", 2))
			break;
			return Intrinsic::x86_fma_vfnmsub_pd_256; // "86.fma.
			vfnmsub.pd.256"
			case '5': // 1 string to match.
			if (memcmp(NameR.data()+19, "12", 2))
			break;
			return Intrinsic::x86_fma_vfnmsub_pd_512; // "86.fma.
			vfnmsub.pd.512"
			}
			break;
			case 's': // 2 strings to match.
			if (NameR[17] != '.')
			break;
			switch (NameR[18]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(NameR.data()+19, "56", 2))
			break;
			return Intrinsic::x86_fma_vfnmsub_ps_256; // "86.fma.
			vfnmsub.ps.256"
			case '5': // 1 string to match.
			if (memcmp(NameR.data()+19, "12", 2))
			break;
			return Intrinsic::x86_fma_vfnmsub_ps_512; // "86.fma.
			vfnmsub.ps.512"
			}
			break;
			}
			break;
			}
			break;
			case 's': // 6 strings to match.
			if (NameR[4] != 's')
			break;
			switch (NameR[5]) {
			default: break;
			case 'e': // 4 strings to match.
			if (memcmp(NameR.data()+6, "42.pcmp", 7))
			break;
			switch (NameR[13]) {
			default: break;
			case 'e': // 2 strings to match.
			if (memcmp(NameR.data()+14, "str", 3))
			break;
			switch (NameR[17]) {
			default: break;
			case 'i': // 1 string to match.
			if (memcmp(NameR.data()+18, "128", 3))
			break;
			return Intrinsic::x86_sse42_pcmpestri128; // "86.sse4
			2.pcmpestri128"
			case 'm': // 1 string to match.
			if (memcmp(NameR.data()+18, "128", 3))
			break;
			return Intrinsic::x86_sse42_pcmpestrm128; // "86.sse4
			2.pcmpestrm128"
			}
			break;
			case 'i': // 2 strings to match.
			if (memcmp(NameR.data()+14, "str", 3))
			break;
			switch (NameR[17]) {
			default: break;
			case 'i': // 1 string to match.
			if (memcmp(NameR.data()+18, "128", 3))
			break;
			return Intrinsic::x86_sse42_pcmpistri128; // "86.sse4
			2.pcmpistri128"
			case 'm': // 1 string to match.
			if (memcmp(NameR.data()+18, "128", 3))
			break;
			return Intrinsic::x86_sse42_pcmpistrm128; // "86.sse4
			2.pcmpistrm128"
			}
			break;
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(NameR.data()+6, "e3.ph", 5))
			break;
			switch (NameR[11]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(NameR.data()+12, "dd.sw.128", 9))
			break;
			return Intrinsic::x86_ssse3_phadd_sw_128; // "86.ssse3.phadd.
			sw.128"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+12, "ub.sw.128", 9))
			break;
			return Intrinsic::x86_ssse3_phsub_sw_128; // "86.ssse3.phsub.
			sw.128"
			}
			break;
			}
			break;
			case 'x': // 2 strings to match.
			if (memcmp(NameR.data()+4, "op.vpermil2p", 12))
			break;
			switch (NameR[16]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+17, ".256", 4))
			break;
			return Intrinsic::x86_xop_vpermil2pd_256; // "86.xop.vpermil2
			pd.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+17, ".256", 4))
			break;
			return Intrinsic::x86_xop_vpermil2ps_256; // "86.xop.vpermil2
			ps.256"
			}
			break;
			}
			break;
			case 22: // 28 strings to match.
			if (memcmp(NameR.data()+0, "86.", 3))
			break;
			switch (NameR[3]) {
			default: break;
			case 'a': // 18 strings to match.
			if (memcmp(NameR.data()+4, "vx", 2))
			break;
			switch (NameR[6]) {
			default: break;
			case '.': // 4 strings to match.
			switch (NameR[7]) {
			default: break;
			case 'm': // 2 strings to match.
			if (memcmp(NameR.data()+8, "askload.p", 9))
			break;
			switch (NameR[17]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+18, ".256", 4))
			break;
			return Intrinsic::x86_avx_maskload_pd_256; // "86.avx.
			maskload.pd.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+18, ".256", 4))
			break;
			return Intrinsic::x86_avx_maskload_ps_256; // "86.avx.
			maskload.ps.256"
			}
			break;
			case 'v': // 2 strings to match.
			if (memcmp(NameR.data()+8, "testnzc.p", 9))
			break;
			switch (NameR[17]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+18, ".256", 4))
			break;
			return Intrinsic::x86_avx_vtestnzc_pd_256; // "86.avx.
			vtestnzc.pd.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+18, ".256", 4))
			break;
			return Intrinsic::x86_avx_vtestnzc_ps_256; // "86.avx.
			vtestnzc.ps.256"
			}
			break;
			}
			break;
			case '2': // 7 strings to match.
			if (NameR[7] != '.')
			break;
			switch (NameR[8]) {
			default: break;
			case 'g': // 4 strings to match.
			if (memcmp(NameR.data()+9, "ather.", 6))
			break;
			switch (NameR[15]) {
			default: break;
			case 'd': // 2 strings to match.
			if (NameR[16] != '.')
			break;
			switch (NameR[17]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+18, ".256", 4))
			break;
			return Intrinsic::x86_avx2_gather_d_d_256; // "86.avx2
			.gather.d.d.256"
			case 'q': // 1 string to match.
			if (memcmp(NameR.data()+18, ".256", 4))
			break;
			return Intrinsic::x86_avx2_gather_d_q_256; // "86.avx2
			.gather.d.q.256"
			}
			break;
			case 'q': // 2 strings to match.
			if (NameR[16] != '.')
			break;
			switch (NameR[17]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+18, ".256", 4))
			break;
			return Intrinsic::x86_avx2_gather_q_d_256; // "86.avx2
			.gather.q.d.256"
			case 'q': // 1 string to match.
			if (memcmp(NameR.data()+18, ".256", 4))
			break;
			return Intrinsic::x86_avx2_gather_q_q_256; // "86.avx2
			.gather.q.q.256"
			}
			break;
			}
			break;
			case 'm': // 2 strings to match.
			if (memcmp(NameR.data()+9, "askload.", 8))
			break;
			switch (NameR[17]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+18, ".256", 4))
			break;
			return Intrinsic::x86_avx2_maskload_d_256; // "86.avx2
			.maskload.d.256"
			case 'q': // 1 string to match.
			if (memcmp(NameR.data()+18, ".256", 4))
			break;
			return Intrinsic::x86_avx2_maskload_q_256; // "86.avx2
			.maskload.q.256"
			}
			break;
			case 'v': // 1 string to match.
			if (memcmp(NameR.data()+9, "broadcasti128", 13))
			break;
			return Intrinsic::x86_avx2_vbroadcasti128; // "86.avx2.vbroadc
			asti128"
			}
			break;
			case '5': // 7 strings to match.
			if (memcmp(NameR.data()+7, "12.", 3))
			break;
			switch (NameR[10]) {
			default: break;
			case 'c': // 3 strings to match.
			switch (NameR[11]) {
			default: break;
			case 'm': // 1 string to match.
			if (memcmp(NameR.data()+12, "peq.pi.512", 10))
			break;
			return Intrinsic::x86_avx512_cmpeq_pi_512; // "86.avx5
			12.cmpeq.pi.512"
			case 'v': // 2 strings to match.
			if (memcmp(NameR.data()+12, "tts", 3))
			break;
			switch (NameR[15]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+16, "2usi64", 6))
			break;
			return Intrinsic::x86_avx512_cvttsd2usi64; // "86.avx5
			12.cvttsd2usi64"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+16, "2usi64", 6))
			break;
			return Intrinsic::x86_avx512_cvttss2usi64; // "86.avx5
			12.cvttss2usi64"
			}
			break;
			}
			break;
			case 'r': // 4 strings to match.
			if (memcmp(NameR.data()+11, "cp", 2))
			break;
			switch (NameR[13]) {
			default: break;
			case '1': // 2 strings to match.
			if (memcmp(NameR.data()+14, "4.p", 3))
			break;
			switch (NameR[17]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+18, ".512", 4))
			break;
			return Intrinsic::x86_avx512_rcp14_pd_512; // "86.avx5
			12.rcp14.pd.512"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+18, ".512", 4))
			break;
			return Intrinsic::x86_avx512_rcp14_ps_512; // "86.avx5
			12.rcp14.ps.512"
			}
			break;
			case '2': // 2 strings to match.
			if (memcmp(NameR.data()+14, "8.p", 3))
			break;
			switch (NameR[17]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+18, ".512", 4))
			break;
			return Intrinsic::x86_avx512_rcp28_pd_512; // "86.avx5
			12.rcp28.pd.512"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+18, ".512", 4))
			break;
			return Intrinsic::x86_avx512_rcp28_ps_512; // "86.avx5
			12.rcp28.ps.512"
			}
			break;
			}
			break;
			}
			break;
			}
			break;
			case 's': // 10 strings to match.
			if (memcmp(NameR.data()+4, "se42.pcmp", 9))
			break;
			switch (NameR[13]) {
			default: break;
			case 'e': // 5 strings to match.
			if (memcmp(NameR.data()+14, "stri", 4))
			break;
			switch (NameR[18]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(NameR.data()+19, "128", 3))
			break;
			return Intrinsic::x86_sse42_pcmpestria128; // "86.sse42.pcmpes
			tria128"
			case 'c': // 1 string to match.
			if (memcmp(NameR.data()+19, "128", 3))
			break;
			return Intrinsic::x86_sse42_pcmpestric128; // "86.sse42.pcmpes
			tric128"
			case 'o': // 1 string to match.
			if (memcmp(NameR.data()+19, "128", 3))
			break;
			return Intrinsic::x86_sse42_pcmpestrio128; // "86.sse42.pcmpes
			trio128"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+19, "128", 3))
			break;
			return Intrinsic::x86_sse42_pcmpestris128; // "86.sse42.pcmpes
			tris128"
			case 'z': // 1 string to match.
			if (memcmp(NameR.data()+19, "128", 3))
			break;
			return Intrinsic::x86_sse42_pcmpestriz128; // "86.sse42.pcmpes
			triz128"
			}
			break;
			case 'i': // 5 strings to match.
			if (memcmp(NameR.data()+14, "stri", 4))
			break;
			switch (NameR[18]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(NameR.data()+19, "128", 3))
			break;
			return Intrinsic::x86_sse42_pcmpistria128; // "86.sse42.pcmpis
			tria128"
			case 'c': // 1 string to match.
			if (memcmp(NameR.data()+19, "128", 3))
			break;
			return Intrinsic::x86_sse42_pcmpistric128; // "86.sse42.pcmpis
			tric128"
			case 'o': // 1 string to match.
			if (memcmp(NameR.data()+19, "128", 3))
			break;
			return Intrinsic::x86_sse42_pcmpistrio128; // "86.sse42.pcmpis
			trio128"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+19, "128", 3))
			break;
			return Intrinsic::x86_sse42_pcmpistris128; // "86.sse42.pcmpis
			tris128"
			case 'z': // 1 string to match.
			if (memcmp(NameR.data()+19, "128", 3))
			break;
			return Intrinsic::x86_sse42_pcmpistriz128; // "86.sse42.pcmpis
			triz128"
			}
			break;
			}
			break;
			}
			break;
			case 23: // 29 strings to match.
			if (memcmp(NameR.data()+0, "86.", 3))
			break;
			switch (NameR[3]) {
			default: break;
			case 'a': // 20 strings to match.
			if (memcmp(NameR.data()+4, "vx", 2))
			break;
			switch (NameR[6]) {
			default: break;
			case '.': // 2 strings to match.
			if (memcmp(NameR.data()+7, "maskstore.p", 11))
			break;
			switch (NameR[18]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+19, ".256", 4))
			break;
			return Intrinsic::x86_avx_maskstore_pd_256; // "86.avx.
			maskstore.pd.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+19, ".256", 4))
			break;
			return Intrinsic::x86_avx_maskstore_ps_256; // "86.avx.
			maskstore.ps.256"
			}
			break;
			case '2': // 14 strings to match.
			if (NameR[7] != '.')
			break;
			switch (NameR[8]) {
			default: break;
			case 'g': // 4 strings to match.
			if (memcmp(NameR.data()+9, "ather.", 6))
			break;
			switch (NameR[15]) {
			default: break;
			case 'd': // 2 strings to match.
			if (memcmp(NameR.data()+16, ".p", 2))
			break;
			switch (NameR[18]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+19, ".256", 4))
			break;
			return Intrinsic::x86_avx2_gather_d_pd_256; // "86.avx2
			.gather.d.pd.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+19, ".256", 4))
			break;
			return Intrinsic::x86_avx2_gather_d_ps_256; // "86.avx2
			.gather.d.ps.256"
			}
			break;
			case 'q': // 2 strings to match.
			if (memcmp(NameR.data()+16, ".p", 2))
			break;
			switch (NameR[18]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+19, ".256", 4))
			break;
			return Intrinsic::x86_avx2_gather_q_pd_256; // "86.avx2
			.gather.q.pd.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+19, ".256", 4))
			break;
			return Intrinsic::x86_avx2_gather_q_ps_256; // "86.avx2
			.gather.q.ps.256"
			}
			break;
			}
			break;
			case 'm': // 2 strings to match.
			if (memcmp(NameR.data()+9, "askstore.", 9))
			break;
			switch (NameR[18]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+19, ".256", 4))
			break;
			return Intrinsic::x86_avx2_maskstore_d_256; // "86.avx2
			.maskstore.d.256"
			case 'q': // 1 string to match.
			if (memcmp(NameR.data()+19, ".256", 4))
			break;
			return Intrinsic::x86_avx2_maskstore_q_256; // "86.avx2
			.maskstore.q.256"
			}
			break;
			case 'p': // 8 strings to match.
			if (memcmp(NameR.data()+9, "broadcast", 9))
			break;
			switch (NameR[18]) {
			default: break;
			case 'b': // 2 strings to match.
			if (NameR[19] != '.')
			break;
			switch (NameR[20]) {
			default: break;
			case '1': // 1 string to match.
			if (memcmp(NameR.data()+21, "28", 2))
			break;
			return Intrinsic::x86_avx2_pbroadcastb_128; // "86.avx2
			.pbroadcastb.128"
			case '2': // 1 string to match.
			if (memcmp(NameR.data()+21, "56", 2))
			break;
			return Intrinsic::x86_avx2_pbroadcastb_256; // "86.avx2
			.pbroadcastb.256"
			}
			break;
			case 'd': // 2 strings to match.
			if (NameR[19] != '.')
			break;
			switch (NameR[20]) {
			default: break;
			case '1': // 1 string to match.
			if (memcmp(NameR.data()+21, "28", 2))
			break;
			return Intrinsic::x86_avx2_pbroadcastd_128; // "86.avx2
			.pbroadcastd.128"
			case '2': // 1 string to match.
			if (memcmp(NameR.data()+21, "56", 2))
			break;
			return Intrinsic::x86_avx2_pbroadcastd_256; // "86.avx2
			.pbroadcastd.256"
			}
			break;
			case 'q': // 2 strings to match.
			if (NameR[19] != '.')
			break;
			switch (NameR[20]) {
			default: break;
			case '1': // 1 string to match.
			if (memcmp(NameR.data()+21, "28", 2))
			break;
			return Intrinsic::x86_avx2_pbroadcastq_128; // "86.avx2
			.pbroadcastq.128"
			case '2': // 1 string to match.
			if (memcmp(NameR.data()+21, "56", 2))
			break;
			return Intrinsic::x86_avx2_pbroadcastq_256; // "86.avx2
			.pbroadcastq.256"
			}
			break;
			case 'w': // 2 strings to match.
			if (NameR[19] != '.')
			break;
			switch (NameR[20]) {
			default: break;
			case '1': // 1 string to match.
			if (memcmp(NameR.data()+21, "28", 2))
			break;
			return Intrinsic::x86_avx2_pbroadcastw_128; // "86.avx2
			.pbroadcastw.128"
			case '2': // 1 string to match.
			if (memcmp(NameR.data()+21, "56", 2))
			break;
			return Intrinsic::x86_avx2_pbroadcastw_256; // "86.avx2
			.pbroadcastw.256"
			}
			break;
			}
			break;
			}
			break;
			case '5': // 4 strings to match.
			if (memcmp(NameR.data()+7, "12.", 3))
			break;
			switch (NameR[10]) {
			default: break;
			case 'c': // 2 strings to match.
			if (memcmp(NameR.data()+11, "vt", 2))
			break;
			switch (NameR[13]) {
			default: break;
			case '.': // 1 string to match.
			if (memcmp(NameR.data()+14, "ps2dq.512", 9))
			break;
			return Intrinsic::x86_avx512_cvt_ps2dq_512; // "86.avx5
			12.cvt.ps2dq.512"
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+14, "q2.ps.512", 9))
			break;
			return Intrinsic::x86_avx512_cvtdq2_ps_512; // "86.avx5
			12.cvtdq2.ps.512"
			}
			break;
			case 'v': // 2 strings to match.
			if (memcmp(NameR.data()+11, "cvtp", 4))
			break;
			switch (NameR[15]) {
			default: break;
			case 'h': // 1 string to match.
			if (memcmp(NameR.data()+16, "2ps.512", 7))
			break;
			return Intrinsic::x86_avx512_vcvtph2ps_512; // "86.avx5
			12.vcvtph2ps.512"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+16, "2ph.512", 7))
			break;
			return Intrinsic::x86_avx512_vcvtps2ph_512; // "86.avx5
			12.vcvtps2ph.512"
			}
			break;
			}
			break;
			}
			break;
			case 'f': // 8 strings to match.
			if (memcmp(NameR.data()+4, "ma.vfm", 6))
			break;
			switch (NameR[10]) {
			default: break;
			case 'a': // 4 strings to match.
			if (memcmp(NameR.data()+11, "ddsub.p", 7))
			break;
			switch (NameR[18]) {
			default: break;
			case 'd': // 2 strings to match.
			if (NameR[19] != '.')
			break;
			switch (NameR[20]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(NameR.data()+21, "56", 2))
			break;
			return Intrinsic::x86_fma_vfmaddsub_pd_256; // "86.fma.
			vfmaddsub.pd.256"
			case '5': // 1 string to match.
			if (memcmp(NameR.data()+21, "12", 2))
			break;
			return Intrinsic::x86_fma_vfmaddsub_pd_512; // "86.fma.
			vfmaddsub.pd.512"
			}
			break;
			case 's': // 2 strings to match.
			if (NameR[19] != '.')
			break;
			switch (NameR[20]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(NameR.data()+21, "56", 2))
			break;
			return Intrinsic::x86_fma_vfmaddsub_ps_256; // "86.fma.
			vfmaddsub.ps.256"
			case '5': // 1 string to match.
			if (memcmp(NameR.data()+21, "12", 2))
			break;
			return Intrinsic::x86_fma_vfmaddsub_ps_512; // "86.fma.
			vfmaddsub.ps.512"
			}
			break;
			}
			break;
			case 's': // 4 strings to match.
			if (memcmp(NameR.data()+11, "ubadd.p", 7))
			break;
			switch (NameR[18]) {
			default: break;
			case 'd': // 2 strings to match.
			if (NameR[19] != '.')
			break;
			switch (NameR[20]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(NameR.data()+21, "56", 2))
			break;
			return Intrinsic::x86_fma_vfmsubadd_pd_256; // "86.fma.
			vfmsubadd.pd.256"
			case '5': // 1 string to match.
			if (memcmp(NameR.data()+21, "12", 2))
			break;
			return Intrinsic::x86_fma_vfmsubadd_pd_512; // "86.fma.
			vfmsubadd.pd.512"
			}
			break;
			case 's': // 2 strings to match.
			if (NameR[19] != '.')
			break;
			switch (NameR[20]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(NameR.data()+21, "56", 2))
			break;
			return Intrinsic::x86_fma_vfmsubadd_ps_256; // "86.fma.
			vfmsubadd.ps.256"
			case '5': // 1 string to match.
			if (memcmp(NameR.data()+21, "12", 2))
			break;
			return Intrinsic::x86_fma_vfmsubadd_ps_512; // "86.fma.
			vfmsubadd.ps.512"
			}
			break;
			}
			break;
			}
			break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+4, "sse3.pmul.hr.sw.128", 19))
			break;
			return Intrinsic::x86_ssse3_pmul_hr_sw_128; // "86.ssse3.pmul.h
			r.sw.128"
			}
			break;
			case 24: // 26 strings to match.
			if (memcmp(NameR.data()+0, "86.", 3))
			break;
			switch (NameR[3]) {
			default: break;
			case 'a': // 25 strings to match.
			switch (NameR[4]) {
			default: break;
			case 'e': // 1 string to match.
			if (memcmp(NameR.data()+5, "sni.aeskeygenassist", 19))
			break;
			return Intrinsic::x86_aesni_aeskeygenassist; // "86.aesni.aeskey
			genassist"
			case 'v': // 24 strings to match.
			if (NameR[5] != 'x')
			break;
			switch (NameR[6]) {
			default: break;
			case '.': // 7 strings to match.
			if (NameR[7] != 'v')
			break;
			switch (NameR[8]) {
			default: break;
			case 'b': // 2 strings to match.
			if (memcmp(NameR.data()+9, "roadcast.s", 10))
			break;
			switch (NameR[19]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+20, ".256", 4))
			break;
			return Intrinsic::x86_avx_vbroadcast_sd_256; // "86.avx.
			vbroadcast.sd.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+20, ".256", 4))
			break;
			return Intrinsic::x86_avx_vbroadcast_ss_256; // "86.avx.
			vbroadcast.ss.256"
			}
			break;
			case 'p': // 5 strings to match.
			if (memcmp(NameR.data()+9, "erm", 3))
			break;
			switch (NameR[12]) {
			default: break;
			case '2': // 3 strings to match.
			if (memcmp(NameR.data()+13, "f128.", 5))
			break;
			switch (NameR[18]) {
			default: break;
			case 'p': // 2 strings to match.
			switch (NameR[19]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+20, ".256", 4))
			break;
			return Intrinsic::x86_avx_vperm2f128_pd_256; //
			"86.avx.vperm2f128.pd.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+20, ".256", 4))
			break;
			return Intrinsic::x86_avx_vperm2f128_ps_256; //
			"86.avx.vperm2f128.ps.256"
			}
			break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+19, "i.256", 5))
			break;
			return Intrinsic::x86_avx_vperm2f128_si_256; // "86.avx.
			vperm2f128.si.256"
			}
			break;
			case 'i': // 2 strings to match.
			if (memcmp(NameR.data()+13, "lvar.p", 6))
			break;
			switch (NameR[19]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+20, ".256", 4))
			break;
			return Intrinsic::x86_avx_vpermilvar_pd_256; // "86.avx.
			vpermilvar.pd.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+20, ".256", 4))
			break;
			return Intrinsic::x86_avx_vpermilvar_ps_256; // "86.avx.
			vpermilvar.ps.256"
			}
			break;
			}
			break;
			}
			break;
			case '2': // 1 string to match.
			if (memcmp(NameR.data()+7, ".vbroadcast.ss.ps", 17))
			break;
			return Intrinsic::x86_avx2_vbroadcast_ss_ps; // "86.avx2
			.vbroadcast.ss.ps"
			case '5': // 16 strings to match.
			if (memcmp(NameR.data()+7, "12.", 3))
			break;
			switch (NameR[10]) {
			default: break;
			case 'c': // 2 strings to match.
			if (memcmp(NameR.data()+11, "onflict.", 8))
			break;
			switch (NameR[19]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+20, ".512", 4))
			break;
			return Intrinsic::x86_avx512_conflict_d_512; // "86.avx5
			12.conflict.d.512"
			case 'q': // 1 string to match.
			if (memcmp(NameR.data()+20, ".512", 4))
			break;
			return Intrinsic::x86_avx512_conflict_q_512; // "86.avx5
			12.conflict.q.512"
			}
			break;
			case 'g': // 8 strings to match.
			if (memcmp(NameR.data()+11, "ather.", 6))
			break;
			switch (NameR[17]) {
			default: break;
			case 'd': // 4 strings to match.
			if (NameR[18] != 'p')
			break;
			switch (NameR[19]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+20, ".512", 4))
			break;
			return Intrinsic::x86_avx512_gather_dpd_512; // "86.avx5
			12.gather.dpd.512"
			case 'i': // 1 string to match.
			if (memcmp(NameR.data()+20, ".512", 4))
			break;
			return Intrinsic::x86_avx512_gather_dpi_512; // "86.avx5
			12.gather.dpi.512"
			case 'q': // 1 string to match.
			if (memcmp(NameR.data()+20, ".512", 4))
			break;
			return Intrinsic::x86_avx512_gather_dpq_512; // "86.avx5
			12.gather.dpq.512"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+20, ".512", 4))
			break;
			return Intrinsic::x86_avx512_gather_dps_512; // "86.avx5
			12.gather.dps.512"
			}
			break;
			case 'q': // 4 strings to match.
			if (NameR[18] != 'p')
			break;
			switch (NameR[19]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+20, ".512", 4))
			break;
			return Intrinsic::x86_avx512_gather_qpd_512; // "86.avx5
			12.gather.qpd.512"
			case 'i': // 1 string to match.
			if (memcmp(NameR.data()+20, ".512", 4))
			break;
			return Intrinsic::x86_avx512_gather_qpi_512; // "86.avx5
			12.gather.qpi.512"
			case 'q': // 1 string to match.
			if (memcmp(NameR.data()+20, ".512", 4))
			break;
			return Intrinsic::x86_avx512_gather_qpq_512; // "86.avx5
			12.gather.qpq.512"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+20, ".512", 4))
			break;
			return Intrinsic::x86_avx512_gather_qps_512; // "86.avx5
			12.gather.qps.512"
			}
			break;
			}
			break;
			case 'm': // 2 strings to match.
			if (memcmp(NameR.data()+11, "skblend.", 8))
			break;
			switch (NameR[19]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+20, ".512", 4))
			break;
			return Intrinsic::x86_avx512_mskblend_d_512; // "86.avx5
			12.mskblend.d.512"
			case 'q': // 1 string to match.
			if (memcmp(NameR.data()+20, ".512", 4))
			break;
			return Intrinsic::x86_avx512_mskblend_q_512; // "86.avx5
			12.mskblend.q.512"
			}
			break;
			case 'r': // 4 strings to match.
			if (memcmp(NameR.data()+11, "sqrt", 4))
			break;
			switch (NameR[15]) {
			default: break;
			case '1': // 2 strings to match.
			if (memcmp(NameR.data()+16, "4.p", 3))
			break;
			switch (NameR[19]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+20, ".512", 4))
			break;
			return Intrinsic::x86_avx512_rsqrt14_pd_512; // "86.avx5
			12.rsqrt14.pd.512"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+20, ".512", 4))
			break;
			return Intrinsic::x86_avx512_rsqrt14_ps_512; // "86.avx5
			12.rsqrt14.ps.512"
			}
			break;
			case '2': // 2 strings to match.
			if (memcmp(NameR.data()+16, "8.p", 3))
			break;
			switch (NameR[19]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+20, ".512", 4))
			break;
			return Intrinsic::x86_avx512_rsqrt28_pd_512; // "86.avx5
			12.rsqrt28.pd.512"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+20, ".512", 4))
			break;
			return Intrinsic::x86_avx512_rsqrt28_ps_512; // "86.avx5
			12.rsqrt28.ps.512"
			}
			break;
			}
			break;
			}
			break;
			}
			break;
			}
			break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+4, "sse3.pmadd.ub.sw.128", 20))
			break;
			return Intrinsic::x86_ssse3_pmadd_ub_sw_128; // "86.ssse3.pmadd.
			ub.sw.128"
			}
			break;
			case 25: // 17 strings to match.
			if (memcmp(NameR.data()+0, "86.avx", 6))
			break;
			switch (NameR[6]) {
			default: break;
			case '.': // 3 strings to match.
			if (memcmp(NameR.data()+7, "vinsertf128.", 12))
			break;
			switch (NameR[19]) {
			default: break;
			case 'p': // 2 strings to match.
			switch (NameR[20]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+21, ".256", 4))
			break;
			return Intrinsic::x86_avx_vinsertf128_pd_256; // "86.avx.
			vinsertf128.pd.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+21, ".256", 4))
			break;
			return Intrinsic::x86_avx_vinsertf128_ps_256; // "86.avx.
			vinsertf128.ps.256"
			}
			break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+20, "i.256", 5))
			break;
			return Intrinsic::x86_avx_vinsertf128_si_256; // "86.avx.
			vinsertf128.si.256"
			}
			break;
			case '5': // 14 strings to match.
			if (memcmp(NameR.data()+7, "12.", 3))
			break;
			switch (NameR[10]) {
			default: break;
			case 'm': // 2 strings to match.
			if (memcmp(NameR.data()+11, "skblend.p", 9))
			break;
			switch (NameR[20]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+21, ".512", 4))
			break;
			return Intrinsic::x86_avx512_mskblend_pd_512; // "86.avx5
			12.mskblend.pd.512"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+21, ".512", 4))
			break;
			return Intrinsic::x86_avx512_mskblend_ps_512; // "86.avx5
			12.mskblend.ps.512"
			}
			break;
			case 'p': // 2 strings to match.
			if (memcmp(NameR.data()+11, "broadcast", 9))
			break;
			switch (NameR[20]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+21, ".512", 4))
			break;
			return Intrinsic::x86_avx512_pbroadcastd_512; // "86.avx5
			12.pbroadcastd.512"
			case 'q': // 1 string to match.
			if (memcmp(NameR.data()+21, ".512", 4))
			break;
			return Intrinsic::x86_avx512_pbroadcastq_512; // "86.avx5
			12.pbroadcastq.512"
			}
			break;
			case 'r': // 2 strings to match.
			if (memcmp(NameR.data()+11, "ndscale.p", 9))
			break;
			switch (NameR[20]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+21, ".512", 4))
			break;
			return Intrinsic::x86_avx512_rndscale_pd_512; // "86.avx5
			12.rndscale.pd.512"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+21, ".512", 4))
			break;
			return Intrinsic::x86_avx512_rndscale_ps_512; // "86.avx5
			12.rndscale.ps.512"
			}
			break;
			case 's': // 8 strings to match.
			if (memcmp(NameR.data()+11, "catter.", 7))
			break;
			switch (NameR[18]) {
			default: break;
			case 'd': // 4 strings to match.
			if (NameR[19] != 'p')
			break;
			switch (NameR[20]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+21, ".512", 4))
			break;
			return Intrinsic::x86_avx512_scatter_dpd_512; // "86.avx5
			12.scatter.dpd.512"
			case 'i': // 1 string to match.
			if (memcmp(NameR.data()+21, ".512", 4))
			break;
			return Intrinsic::x86_avx512_scatter_dpi_512; // "86.avx5
			12.scatter.dpi.512"
			case 'q': // 1 string to match.
			if (memcmp(NameR.data()+21, ".512", 4))
			break;
			return Intrinsic::x86_avx512_scatter_dpq_512; // "86.avx5
			12.scatter.dpq.512"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+21, ".512", 4))
			break;
			return Intrinsic::x86_avx512_scatter_dps_512; // "86.avx5
			12.scatter.dps.512"
			}
			break;
			case 'q': // 4 strings to match.
			if (NameR[19] != 'p')
			break;
			switch (NameR[20]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+21, ".512", 4))
			break;
			return Intrinsic::x86_avx512_scatter_qpd_512; // "86.avx5
			12.scatter.qpd.512"
			case 'i': // 1 string to match.
			if (memcmp(NameR.data()+21, ".512", 4))
			break;
			return Intrinsic::x86_avx512_scatter_qpi_512; // "86.avx5
			12.scatter.qpi.512"
			case 'q': // 1 string to match.
			if (memcmp(NameR.data()+21, ".512", 4))
			break;
			return Intrinsic::x86_avx512_scatter_qpq_512; // "86.avx5
			12.scatter.qpq.512"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+21, ".512", 4))
			break;
			return Intrinsic::x86_avx512_scatter_qps_512; // "86.avx5
			12.scatter.qps.512"
			}
			break;
			}
			break;
			}
			break;
			}
			break;
			case 26: // 3 strings to match.
			if (memcmp(NameR.data()+0, "86.avx.vextractf128.", 20))
			break;
			switch (NameR[20]) {
			default: break;
			case 'p': // 2 strings to match.
			switch (NameR[21]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+22, ".256", 4))
			break;
			return Intrinsic::x86_avx_vextractf128_pd_256; // "86.avx.
			vextractf128.pd.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+22, ".256", 4))
			break;
			return Intrinsic::x86_avx_vextractf128_ps_256; // "86.avx.
			vextractf128.ps.256"
			}
			break;
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+21, "i.256", 5))
			break;
			return Intrinsic::x86_avx_vextractf128_si_256; // "86.avx.vextract
			f128.si.256"
			}
			break;
			case 27: // 2 strings to match.
			if (memcmp(NameR.data()+0, "86.avx512.vbroadcast.s", 22))
			break;
			switch (NameR[22]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+23, ".512", 4))
			break;
			return Intrinsic::x86_avx512_vbroadcast_sd_512; // "86.avx5
			12.vbroadcast.sd.512"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+23, ".512", 4))
			break;
			return Intrinsic::x86_avx512_vbroadcast_ss_512; // "86.avx5
			12.vbroadcast.ss.512"
			}
			break;
			case 28: // 4 strings to match.
			if (memcmp(NameR.data()+0, "86.avx", 6))
			break;
			switch (NameR[6]) {
			default: break;
			case '.': // 2 strings to match.
			if (memcmp(NameR.data()+7, "vbroadcastf128.p", 16))
			break;
			switch (NameR[23]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+24, ".256", 4))
			break;
			return Intrinsic::x86_avx_vbroadcastf128_pd_256; // "86.avx.
			vbroadcastf128.pd.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+24, ".256", 4))
			break;
			return Intrinsic::x86_avx_vbroadcastf128_ps_256; // "86.avx.
			vbroadcastf128.ps.256"
			}
			break;
			case '2': // 2 strings to match.
			if (memcmp(NameR.data()+7, ".vbroadcast.s", 13))
			break;
			switch (NameR[20]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+21, ".pd.256", 7))
			break;
			return Intrinsic::x86_avx2_vbroadcast_sd_pd_256; // "86.avx2
			.vbroadcast.sd.pd.256"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+21, ".ps.256", 7))
			break;
			return Intrinsic::x86_avx2_vbroadcast_ss_ps_256; // "86.avx2
			.vbroadcast.ss.ps.256"
			}
			break;
			}
			break;
			case 29: // 12 strings to match.
			if (memcmp(NameR.data()+0, "86.avx512.", 10))
			break;
			switch (NameR[10]) {
			default: break;
			case 'c': // 2 strings to match.
			if (memcmp(NameR.data()+11, "onflict.", 8))
			break;
			switch (NameR[19]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+20, ".mask.512", 9))
			break;
			return Intrinsic::x86_avx512_conflict_d_mask_512; // "86.avx5
			12.conflict.d.mask.512"
			case 'q': // 1 string to match.
			if (memcmp(NameR.data()+20, ".mask.512", 9))
			break;
			return Intrinsic::x86_avx512_conflict_q_mask_512; // "86.avx5
			12.conflict.q.mask.512"
			}
			break;
			case 'g': // 8 strings to match.
			if (memcmp(NameR.data()+11, "ather.", 6))
			break;
			switch (NameR[17]) {
			default: break;
			case 'd': // 4 strings to match.
			if (NameR[18] != 'p')
			break;
			switch (NameR[19]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+20, ".mask.512", 9))
			break;
			return Intrinsic::x86_avx512_gather_dpd_mask_512; // "86.avx5
			12.gather.dpd.mask.512"
			case 'i': // 1 string to match.
			if (memcmp(NameR.data()+20, ".mask.512", 9))
			break;
			return Intrinsic::x86_avx512_gather_dpi_mask_512; // "86.avx5
			12.gather.dpi.mask.512"
			case 'q': // 1 string to match.
			if (memcmp(NameR.data()+20, ".mask.512", 9))
			break;
			return Intrinsic::x86_avx512_gather_dpq_mask_512; // "86.avx5
			12.gather.dpq.mask.512"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+20, ".mask.512", 9))
			break;
			return Intrinsic::x86_avx512_gather_dps_mask_512; // "86.avx5
			12.gather.dps.mask.512"
			}
			break;
			case 'q': // 4 strings to match.
			if (NameR[18] != 'p')
			break;
			switch (NameR[19]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+20, ".mask.512", 9))
			break;
			return Intrinsic::x86_avx512_gather_qpd_mask_512; // "86.avx5
			12.gather.qpd.mask.512"
			case 'i': // 1 string to match.
			if (memcmp(NameR.data()+20, ".mask.512", 9))
			break;
			return Intrinsic::x86_avx512_gather_qpi_mask_512; // "86.avx5
			12.gather.qpi.mask.512"
			case 'q': // 1 string to match.
			if (memcmp(NameR.data()+20, ".mask.512", 9))
			break;
			return Intrinsic::x86_avx512_gather_qpq_mask_512; // "86.avx5
			12.gather.qpq.mask.512"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+20, ".mask.512", 9))
			break;
			return Intrinsic::x86_avx512_gather_qps_mask_512; // "86.avx5
			12.gather.qps.mask.512"
			}
			break;
			}
			break;
			case 'p': // 2 strings to match.
			if (memcmp(NameR.data()+11, "broadcast", 9))
			break;
			switch (NameR[20]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+21, ".i32.512", 8))
			break;
			return Intrinsic::x86_avx512_pbroadcastd_i32_512; // "86.avx5
			12.pbroadcastd.i32.512"
			case 'q': // 1 string to match.
			if (memcmp(NameR.data()+21, ".i64.512", 8))
			break;
			return Intrinsic::x86_avx512_pbroadcastq_i64_512; // "86.avx5
			12.pbroadcastq.i64.512"
			}
			break;
			}
			break;
			case 30: // 12 strings to match.
			if (memcmp(NameR.data()+0, "86.avx512.", 10))
			break;
			switch (NameR[10]) {
			default: break;
			case 'c': // 2 strings to match.
			if (memcmp(NameR.data()+11, "onflict.", 8))
			break;
			switch (NameR[19]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+20, ".maskz.512", 10))
			break;
			return Intrinsic::x86_avx512_conflict_d_maskz_512; // "86.avx5
			12.conflict.d.maskz.512"
			case 'q': // 1 string to match.
			if (memcmp(NameR.data()+20, ".maskz.512", 10))
			break;
			return Intrinsic::x86_avx512_conflict_q_maskz_512; // "86.avx5
			12.conflict.q.maskz.512"
			}
			break;
			case 's': // 8 strings to match.
			if (memcmp(NameR.data()+11, "catter.", 7))
			break;
			switch (NameR[18]) {
			default: break;
			case 'd': // 4 strings to match.
			if (NameR[19] != 'p')
			break;
			switch (NameR[20]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+21, ".mask.512", 9))
			break;
			return Intrinsic::x86_avx512_scatter_dpd_mask_512; // "86.avx5
			12.scatter.dpd.mask.512"
			case 'i': // 1 string to match.
			if (memcmp(NameR.data()+21, ".mask.512", 9))
			break;
			return Intrinsic::x86_avx512_scatter_dpi_mask_512; // "86.avx5
			12.scatter.dpi.mask.512"
			case 'q': // 1 string to match.
			if (memcmp(NameR.data()+21, ".mask.512", 9))
			break;
			return Intrinsic::x86_avx512_scatter_dpq_mask_512; // "86.avx5
			12.scatter.dpq.mask.512"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+21, ".mask.512", 9))
			break;
			return Intrinsic::x86_avx512_scatter_dps_mask_512; // "86.avx5
			12.scatter.dps.mask.512"
			}
			break;
			case 'q': // 4 strings to match.
			if (NameR[19] != 'p')
			break;
			switch (NameR[20]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+21, ".mask.512", 9))
			break;
			return Intrinsic::x86_avx512_scatter_qpd_mask_512; // "86.avx5
			12.scatter.qpd.mask.512"
			case 'i': // 1 string to match.
			if (memcmp(NameR.data()+21, ".mask.512", 9))
			break;
			return Intrinsic::x86_avx512_scatter_qpi_mask_512; // "86.avx5
			12.scatter.qpi.mask.512"
			case 'q': // 1 string to match.
			if (memcmp(NameR.data()+21, ".mask.512", 9))
			break;
			return Intrinsic::x86_avx512_scatter_qpq_mask_512; // "86.avx5
			12.scatter.qpq.mask.512"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+21, ".mask.512", 9))
			break;
			return Intrinsic::x86_avx512_scatter_qps_mask_512; // "86.avx5
			12.scatter.qps.mask.512"
			}
			break;
			}
			break;
			case 'v': // 2 strings to match.
			if (memcmp(NameR.data()+11, "broadcast.s", 11))
			break;
			switch (NameR[22]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(NameR.data()+23, ".pd.512", 7))
			break;
			return Intrinsic::x86_avx512_vbroadcast_sd_pd_512; // "86.avx5
			12.vbroadcast.sd.pd.512"
			case 's': // 1 string to match.
			if (memcmp(NameR.data()+23, ".ps.512", 7))
			break;
			return Intrinsic::x86_avx512_vbroadcast_ss_ps_512; // "86.avx5
			12.vbroadcast.ss.ps.512"
			}
			break;
			}
			break;
			}
			break; // end of 'x' case.
			}
			#endif
			// Global intrinsic function declaration type table.
			#ifdef GET_INTRINSIC_GENERATOR_GLOBAL
			static const unsigned IIT_Table[] = {
			0x6F2F, 0x6F2F, 0x6F2F, 0x6F2F, 0x6F2F, 0x6F2F, 0x6F2F,
			0x6F2F, 0x6F2F, 0x6F2F, 0x6F2F, 0x2F2F, 0x2F2F, 0x2F2F, 0x6F2F,
			(1U<<31) | 755, (1U<<31) | 755, (1U<<31) | 755, 0x6F2F, 0x6F2F, 0x2F2F2F,
			0x6F2F, 0x6F2F,
			0x6F2F, 0x2F2F2F, 0x2F2F2F, (1U<<31) | 783, 0x898959, 0x898959, (1U<<31)
			| 781, (1U<<31) | 781,
			0x6F2F, 0xAF6F2F, 0xAF6F2F, 0xAF6F2F, 0xAF6F2F, 0xAF6F2F, 0xAF6F2F, 0xAF6
			F2F,
			0xAF6F2F, 0xAF6F2F, (1U<<31) | 749, (1U<<31) | 749, (1U<<31) | 661, (1U<<
			31) | 661, (1U<<31) | 772, (1U<<31) | 772,
			(1U<<31) | 698, (1U<<31) | 698, (1U<<31) | 788, (1U<<31) | 788, (1U<<31)
			| 723, (1U<<31) | 723, (1U<<31) | 404, (1U<<31) | 393,
			(1U<<31) | 380, 0x2F2F2F, 0x6F2F, 0x6F2F, 0x2F2F2F, 0x6F2F, 0x6F2F, 0x1F1
			F1F,
			(1U<<31) | 783, (1U<<31) | 776, (1U<<31) | 792, (1U<<31) | 810, (1U<<31)
			| 792, (1U<<31) | 810, (1U<<31) | 792, (1U<<31) | 810,
			(1U<<31) | 792, 0x2F2F2F, (1U<<31) | 810, (1U<<31) | 792, 0x2F2F2F, (1U<<
			31) | 810, (1U<<31) | 351, (1U<<31) | 351,
			0x2F2F2F, 0x2F2F2F, 0x2F2F2F, 0x42F2F, 0x2F2F2F, 0x42F2F, 0x42F2F, 0x2F2F
			,
			(1U<<31) | 781, (1U<<31) | 781, (1U<<31) | 525, (1U<<31) | 690, (1U<<31)
			| 690, (1U<<31) | 692, (1U<<31) | 781, (1U<<31) | 781,
			(1U<<31) | 692, (1U<<31) | 692, 0x42F2F2F, 0x2F2F2F, (1U<<31) | 525, (1U<
			<31) | 525, 0x42F2F, (1U<<31) | 525,
			(1U<<31) | 525, (1U<<31) | 690, (1U<<31) | 690, 0x42F2F2F, 0x42F2F, 0x42F
			2F2E0, (1U<<31) | 501, (1U<<31) | 512,
			(1U<<31) | 781, (1U<<31) | 781, 0x2F6F2F, 0x2F6F6F2F, (1U<<31) | 308, (1U
			<<31) | 321, 0x2F6F2F2F, (1U<<31) | 295,
			(1U<<31) | 306, (1U<<31) | 319, 0xAF6F2F, 0x2F2F2F, (1U<<31) | 525, (1U<<
			31) | 525, 0x42F2F, 0x6F2F,
			0x2E2E, (1U<<31) | 360, 0x4444440, 0x4444440, 0x0, 0x444, 0x444, 0x444,
			0x444, 0x444, 0x444, 0x40, 0x40, 0x4, 0x3F4, (1U<<31) | 276,
			0x4444440, 0x4444440, 0x444440, 0x444440, 0x444444, 0x444444, 0x2F2F2F, 0
			x2F2F2F,
			0x2F2F, 0x2F2F, 0x2F2F2F2F, 0x2F2F, 0x2F2F2F2F, 0x2F2F2F2F, 0x2F2F2F2F, 0
			x2F2F2F,
			0x2F2F2F2F, 0x2F2F2F2F, 0x2F2F2F, 0x2F2F2F2F, 0x2F2F2F, 0x2F2F2F, 0x2F2F,
			0x797949,
			0x7A7A4A, 0x797949, 0x7A7A4A, 0x2F2F2F2F, 0x2F2F, 0x2F2F, 0x2F2F, 0x6F2F,
			0x6F2F, 0x45F0F, 0x45F0F, 0x7A3A, 0x44F1F, 0x44F1F, 0x3A7A, 0x6F2F,
			0x6F2F, 0x6F2F, 0x6F2F, 0x6F2F, 0x6F2F, 0x2F2F2F, 0x2F2F2F, 0x2F2F2F,
			0x2F2F2F, 0x42E2F, (1U<<31) | 404, (1U<<31) | 545, (1U<<31) | 393, (1U<<3
			1) | 571, (1U<<31) | 380, (1U<<31) | 603,
			0x2F2F2F, 0x2F2F2F, 0x2F2F2F, 0x2F2F2F, 0x2F2F2F, 0x2F2F2F, (1U<<31) | 35
			3, (1U<<31) | 353,
			(1U<<31) | 353, 0x2F2F2F, 0x6F2F2F, 0x6F2F2F, 0x2F2F2F, 0x6F2F, 0x6F2F, 0
			x2F2F2F,
			0x2F2F2F, 0x2F2F2F, 0x2F2F2F, 0x2F2F, 0x2F2F2F, 0x2F2F2F, 0x2F2F2F, (1U<<
			31) | 353,
			(1U<<31) | 339, (1U<<31) | 339, (1U<<31) | 339, 0x2F2F, 0x2F2F2F, (1U<<31
			) | 344, (1U<<31) | 344, (1U<<31) | 344,
			0x2F2F2F, 0x2F2F2F, (1U<<31) | 344, (1U<<31) | 344, (1U<<31) | 344, 0x2F2
			F2F, 0x2F2F2F, 0x2F2F2F,
			0x2F2F2F, 0x2F2F2F, (1U<<31) | 344, 0x2F2F, 0x2F2F2F, 0x2F2F2F, 0x2F2F2F,
			0x2F2F,
			0x2F2F, 0x2F2F, 0x2F2F, 0x2F2F, 0x2F2F, (1U<<31) | 344, 0x2F2F2F, 0x2F2F2
			F,
			0x2F2F, 0x2F2F2F, (1U<<31) | 344, 0x2F2F2F2F, (1U<<31) | 353, (1U<<31) |
			353, (1U<<31) | 344, 0x2F2F2F,
			0x2F2F2F, 0x42F2E0, 0x42F2F2E0, (1U<<31) | 535, (1U<<31) | 501, (1U<<31)
			| 559, (1U<<31) | 512, (1U<<31) | 589,
			0x2B2B2B, 0x2B2B2B2B, (1U<<31) | 265, (1U<<31) | 263, 0x2B2B2B2B, (1U<<31
			) | 265, (1U<<31) | 263, (1U<<31) | 261,
			0x444, 0x444, 0x40, 0x0, 0x444, 0x3F44, 0x2E444, 0x2E,
			0x444, 0x1F7, 0x1F7, 0xF0F, 0x1F1F, 0x37, 0x73, 0x445F1F,
			0x444F1F, 0x444F1F, 0x445F0F, 0x444F0F, 0x444F0F, 0x445F0F, 0x444F0F, 0x4
			44F0F,
			0x1F1F1F, 0x1F1F, 0x10F0F, 0xF0F, 0x10F0F, 0x0, (1U<<31) | 873, (1U<<31)
			| 868,
			0x0, 0x0, 0x42E, 0x2E40, 0x2E50, 0x40, 0x2E0, 0x2E0,
			0x2E, 0x2E4, 0x2E4, 0x0, 0x1F1F, 0x1F1F, 0xF0F0F, (1U<<31) | 885,
			(1U<<31) | 877, (1U<<31) | 893, 0x1F1F, 0x1F1F, 0x4, 0x1F1F1F1F, 0x1F1F1F
			1F, 0x42E,
			0x2EE2E2E, 0x2E2EE0, 0x2EE2E2E0, 0x44, 0x55, 0x44, 0x444, 0x444,
			0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444,
			0x444, 0x444, 0x444, 0x444, 0x555, 0x555, 0x444, 0x545,
			0x444, 0x444, 0x555, 0x44, 0x44, 0x444, 0x444, 0x444,
			0x444, 0x445, 0x445, 0x444, 0x555, 0x444, 0x555, 0x444,
			0x555, 0x444, 0x555, 0x44, 0x55, 0x44, 0x44, 0x55,
			0x444, 0x444, 0x555, 0x54, 0x54, 0x44, 0x44, 0x44,
			0x44, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444,
			0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x555, 0x444,
			0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444,
			0x444, 0x444, 0x44, 0x44, 0x44, 0x45, 0x44, 0x444,
			0x444, 0x55, 0x45, 0x44, 0x55, 0x55, 0x55, 0x55,
			0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555,
			0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555,
			0x555, 0x555, 0x555, 0x555, 0x551, 0x551, 0x551, 0x551,
			0x551, 0x551, 0x551, 0x551, 0x55, 0x555, 0x555, 0x555,
			0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555,
			0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555,
			0x5555, 0x555, 0x5555, 0x555, 0x555, 0x555, 0x555, 0x555,
			0x555, 0x555, 0x555, 0x444, 0x555, 0x44, 0x44, 0x444,
			0x555, 0x445, 0x445, 0x541, 0x441, 0x441, 0x441, 0x441,
			0x441, 0x441, 0x441, 0x441, 0x441, 0x441, 0x441, 0x441,
			0x445, 0x445, 0x444, 0x444, 0x444, 0x444, 0x555, 0x444,
			0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x451,
			0x551, 0x451, 0x551, 0x451, 0x451, 0x451, 0x451, 0x451,
			0x451, 0x451, 0x451, 0x4555, 0x4555, 0x4555, 0x4555, 0x4555,
			0x4555, 0x4555, 0x4555, 0x554, 0x41, 0x441, 0x441, 0x41,
			0x441, 0x441, 0x441, 0x441, 0x441, 0x551, 0x441, 0x441,
			0x441, 0x441, 0x551, 0x441, 0x441, 0x551, 0x441, 0x441,
			0x45, 0x4444, 0x4444, 0x4444, 0x4444, 0x41, 0x441, 0x441,
			0x41, 0x44, 0x41, 0x444, 0x5545, 0x441, 0x4441, 0x4441,
			0x4441, 0x4441, 0x441, 0x441, 0x441, 0x441, 0x441, 0x441,
			0x441, 0x441, 0x441, 0x441, 0x441, 0x4441, 0x4441, 0x4441,
			0x4441, 0x58, 0x57, 0x85, 0x85, 0x87, 0x85, 0x85,
			0x84, 0x84, 0x84, 0x84, 0x75, 0x75, 0x78, 0x75,
			0x75, 0x74, 0x74, 0x74, 0x74, 0x58, 0x57, 0x48,
			0x47, 0x48, 0x47, 0x888, 0x481, 0x881, 0x881, 0x881,
			0x881, 0x888, 0x888, 0x88, 0x8888, 0x8888, 0x48888, 0x8888,
			0x8888, 0x48, 0x48, 0x888, 0x888, 0x888, 0x888, 0x777,
			0x471, 0x771, 0x771, 0x771, 0x771, 0x777, 0x777, 0x77,
			0x7777, 0x7777, 0x47777, 0x7777, 0x7777, 0x47, 0x47, 0x777,
			0x777, 0x777, 0x777, 0x4444, 0x4444, 0x4455, 0x4455, 0x4455,
			0x4455, 0x4455, 0x4455, 0x445, 0x445, 0x444, 0x444, 0x444,
			0x444, 0x445, 0x445, 0x445, 0x445, 0x4455, 0x4455, 0x4455,
			0x4455, 0x4455, 0x4455, 0x444, 0x445, 0x4455, 0x4455, 0x445,
			0x444, 0x444, 0x444, 0x444, 0x4444, 0x4444, 0x4444, 0x5555,
			0x5555, 0x5555, 0x5555, 0x5555, 0x5555, 0x5555, 0x5555, 0x5555,
			0x5555, 0x5555, 0x5555, 0x5555, 0x5555, 0x5555, 0x5555, 0x555,
			0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555,
			0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x555, 0x4444,
			0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444,
			0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x444,
			0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x4444,
			0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444,
			0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x444,
			0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444,
			0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444,
			0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444, 0x444,
			0x444, 0x444, 0x4455, 0x4455, 0x4455, 0x4455, 0x4455, 0x4455,
			0x4455, 0x4455, 0x445, 0x445, 0x445, 0x445, 0x445, 0x445,
			0x445, 0x445, 0x4455, 0x4455, 0x4455, 0x4455, 0x4455, 0x4455,
			0x4455, 0x4455, 0x445, 0x445, 0x445, 0x445, 0x445, 0x445,
			0x445, 0x445, 0x444, 0x444, 0x444, 0x4444, 0x4444, 0x4444,
			0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x444, 0x444, 0x444,
			0x444, 0x444, 0x444, 0x444, 0x444, 0x4444, 0x4444, 0x4444,
			0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x444, 0x4455, 0x4455,
			0x4455, 0x4455, 0x4455, 0x4455, 0x4455, 0x4455, 0x445, 0x445,
			0x445, 0x445, 0x445, 0x445, 0x445, 0x445, 0x4455, 0x4455,
			0x4455, 0x4455, 0x4455, 0x4455, 0x4455, 0x4455, 0x444, 0x4444,
			0x4444, 0x4444, 0x555, 0x555, 0x5555, 0x5555, 0x555, 0x555,
			0x555, 0x555, 0x5555, 0x5555, 0x554, 0x554, 0x555, 0x555,
			0x4455, 0x5555, 0x5555, 0x5555, 0x4455, 0x4455, 0x4455, 0x4455,
			0x555, 0x555, 0x445, 0x444, 0x445, 0x444, 0x445, 0x445,
			0x554, 0x554, 0x5555, 0x5555, 0x5555, 0x5555, 0x555, 0x555,
			0x555, 0x555, 0x4555, 0x455, 0x454, 0x5555, 0x555, 0x4444,
			0x4444, 0x4444, 0x4444, 0x4444, 0x454, 0x454, 0x454, 0x454,
			0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444,
			0x4444, 0x4444, 0x4444, 0x445, 0x4455, 0x445, 0x4455, 0x5555,
			0x5555, 0x555, 0x555, 0x5555, 0x5555, 0x555, 0x555, 0x4444,
			0x4444, 0x4444, 0x5555, 0x5555, 0x555, 0x4455, 0x4455, 0x445,
			0x445, 0x5555, 0x5555, 0x555, 0x555, 0x4444, 0x455, 0x4555,
			0x4555, 0x4555, 0x4555, 0x4555, 0x444, 0x4444, 0x4444, 0x4444,
			0x4444, 0x444, 0x4444, 0x455, 0x455, 0x455, 0x4555, 0x4555,
			0x4555, 0x4555, 0x4555, 0x444, 0x4444, 0x4444, 0x4444, 0x4444,
			0x444, 0x455, 0x455, 0x455, 0x4555, 0x4555, 0x4555, 0x4555,
			0x455, 0x455, 0x444, 0x4444, 0x4444, 0x4444, 0x4444, 0x444,
			0x444, 0x454, 0x455, 0x455, 0x455, 0x4555, 0x4555, 0x4555,
			0x4555, 0x4555, 0x444, 0x4444, 0x4444, 0x4444, 0x4444, 0x444,
			0x454, 0x455, 0x455, 0x44, 0x55, 0x44, 0x54, 0x44,
			0x54, 0x44, 0x44, 0x54, 0x444, 0x444, 0x44, 0x54,
			0x44, 0x54, 0x55, 0x4444, 0x544, 0x4455, 0x555, 0x44444,
			0x5444, 0x44555, 0x5555, 0x55, 0x555, 0x455, 0x4555, 0x4555,
			0x4555, 0x4555, 0x4555, 0x444, 0x4444, 0x4444, 0x4444, 0x4444,
			0x455, 0x455, 0x455, 0x4555, 0x4555, 0x4555, 0x4555, 0x4555,
			0x444, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x455, 0x455,
			0x455, 0x4555, 0x4555, 0x4555, 0x4555, 0x4555, 0x444, 0x4444,
			0x4444, 0x4444, 0x4444, 0x455, 0x455, 0x445, 0x554, 0x444,
			0x444, 0x555, 0x555, 0x555, 0x555, 0x44, 0x44, 0x44444,
			0x44444, 0x44444, 0x44444, 0x444, 0x444, 0x441, 0x441, 0x4555,
			0x4555, 0x455, 0x455, 0x4555, 0x54, 0x54, 0x54, 0x55,
			0x54, 0x55, 0x54, 0x55, 0x54, 0x55, 0x44, 0x45,
			0x4555, 0x4555, 0x45, 0x45, 0x54, 0x555, 0x54, 0x555,
			0x45, 0x45, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x444,
			0x454, 0x54, 0x4444, 0x544, 0x4455, 0x555, 0x444, 0x441,
			0x441, 0x4444, 0x4444, 0x4444, 0x4444, 0x4444, 0x444, 0x4444,
			0x4444, 0x4444, 0x4455, 0x44555, 0x555, 0x555, 0x555, 0x555,
			0x555, 0x555, 0x454, 0x454, 0x54, 0x455, 0x44, 0x442E2E2E,
			0x2E2E2E0, (1U<<31) | 282, (1U<<31) | 283, 0x2E50, 0x2E50, 0x1F1F, 0x1F1F
			, 0x1F1F,
			0x42E0, (1U<<31) | 9, (1U<<31) | 9, 0x144F23F0, 0x3939, 0x2A2A, 0x44, 0x2
			C2C2C,
			0x595959, 0x3B3B3B, 0x4A4A4A, 0x393939, 0x393939, 0x444, 0x393939, 0x3939
			39,
			0x444, 0x444, 0x2C2C2C, 0x595959, 0x3B3B3B, 0x4A4A4A, 0x2C2C2C, 0x595959,
			0x3B3B3B, 0x4A4A4A, 0x2C2C2C, 0x595959, 0x3B3B3B, 0x4A4A4A, 0x444, 0x3939
			39,
			0x2A2A2A, 0x393939, 0x2A2A2A, 0x2A2A2A, 0x2A2A2A, 0x2C2C2C, 0x595959, 0x3
			B3B3B,
			0x4A4A4A, 0x42C2C, 0x45959, 0x43B3B, 0x44A4A, 0x444, 0x2C2C2C, 0x42C2C,
			0x4444, 0x2C2C2C, 0x595959, 0x3B3B3B, 0x4A4A4A, 0x2C2C2C, 0x595959, 0x3B3
			B3B,
			0x4A4A4A, 0x2C2C2C, 0x595959, 0x3B3B3B, 0x4A4A4A, 0x2C2C2C, 0x595959, 0x3
			B3B3B,
			0x4A4A4A, 0x2C2C2C, 0x595959, 0x3B3B3B, 0x4A4A4A, 0x2C2C2C, 0x595959, 0x3
			B3B3B,
			0x4A4A4A, 0x4444, 0x2C2C2C, 0x595959, 0x3B3B3B, 0x4A4A4A, 0x42C2C, 0x4595
			9,
			0x43B3B, 0x44A4A, 0x2C2C2C2C, 0x59595959, 0x3B3B3B3B, 0x4A4A4A4A, 0x42C2C
			2C, 0x4595959,
			0x43B3B3B, 0x44A4A4A, 0x2C2C2C2C, 0x59595959, 0x3B3B3B3B, 0x4A4A4A4A, 0x4
			2C2C2C, 0x4595959,
			0x43B3B3B, 0x44A4A4A, 0x44, 0x2C2C2C2C, 0x42C2C2C, 0x2C2C2C2C, 0x42C2C2C,
			0x2C2C2C,
			0x595959, 0x3B3B3B, 0x4A4A4A, 0x42C2C, 0x45959, 0x43B3B, 0x44A4A, 0x2C4,
			0x594, 0x3B4, 0x2C4, 0x4A4, 0x4, 0x2C2C2C2C, 0x42C2C2C, 0x2C2C2C,
			0x595959, 0x3B3B3B, 0x4A4A4A, 0x42C2C, 0x45959, 0x43B3B, 0x44A4A, 0x2C4,
			0x594, 0x3B4, 0x2C4, 0x4A4, 0x2C2C2C, 0x595959, 0x3B3B3B, 0x4A4A4A,
			0x42C2C, 0x45959, 0x43B3B, 0x44A4A, 0x44, 0x2C2C2C, 0x595959, 0x3B3B3B,
			0x4A4A4A, 0x2C2C2C, 0x595959, 0x3B3B3B, 0x4A4A4A, 0x42C2C, 0x45959, 0x43B
			3B,
			0x44A4A, 0x42C2C, 0x45959, 0x43B3B, 0x44A4A, 0x2C2C2C, 0x595959, 0x3B3B3B
			,
			0x4A4A4A, 0x2C2C2C, 0x595959, 0x3B3B3B, 0x4A4A4A, 0x42C2C, 0x45959, 0x43B
			3B,
			0x44A4A, 0x42C2C, 0x45959, 0x43B3B, 0x44A4A, 0x39390, 0x39390, 0x39390,
			0x2A2A4, 0x2A2A4, 0x2A2A4, 0x2A2A4, 0x2A2A4, 0x2A2A4, 0x2A2A0, 0x2A2A0,
			0x2A2A0, 0x42C4, 0x4595, 0x43B4, 0x44A4, 0x42C4, 0x4595, 0x43B4,
			0x44A4, 0x440, 0x2C2C2C, 0x595959, 0x3B3B3B, 0x4A4A4A, 0x2C2C2C, 0x595959
			,
			0x3B3B3B, 0x4A4A4A, 0x4A4A59, 0x2C2C3B, 0x3B3B4A, 0x4A4A59, 0x2C2C3B, 0x3
			B3B4A,
			0x393955, 0x4A4A5959, 0x2C2C3B3B, 0x3B3B4A4A, 0x4A4A5959, 0x2C2C3B3B, 0x3
			B3B4A4A, 0x393955,
			0x4455, 0x393955, 0x393955, 0x2A2A55, 0x2A2A55, 0x393955, 0x393955, 0x393
			955,
			0x4455, 0x393955, 0x393955, 0x2A2A55, 0x2A2A55, 0x4A4A5959, 0x2C2C3B3B, 0
			x3B3B4A4A,
			0x4A4A5959, 0x2C2C3B3B, 0x3B3B4A4A, 0x393955, 0x454, 0x454, 0x454, 0x454,
			0x454, 0x454, 0x898989, 0x7A7A7A, 0x898959, 0x7A7A4A, 0x898959, 0x7A7A4A,
			0x8959, 0x7A4A, 0x898959, 0x7A7A4A, 0x898959, 0x7A7A4A, 0x898959, 0x7A7A4
			A,
			0x898959, 0x7A7A4A, 0x898959, 0x7A7A4A, 0x898959, 0x7A7A4A, 0x898959, 0x7
			A7A4A,
			0x898959, 0x7A7A4A, 0x898959, 0x7A7A4A, 0x898989, 0x7A7A7A, 0x7A7A6B, 0x8
			9897A,
			0x598989, 0x4A7A7A, 0x7A89, 0x6B7A, 0x7A89, 0x6B7A, 0x5989, 0x4A7A,
			0x5989, 0x4A7A, 0x4A89, 0x3B7A, 0x4A89, 0x3B7A, 0x42C, 0x559,
			0x43B, 0x44A, 0x8989, 0x7A7A, (1U<<31) | 801, 0x7A7A7A7A, 0x898989, 0x7A7
			A7A,
			0x898989, 0x7A7A7A, 0x898989, 0x7A7A7A, 0x898989, 0x7A7A7A, (1U<<31) | 80
			1, 0x7A7A7A7A,
			0x898989, 0x7A7A7A, 0x8989, 0x7A7A, 0x8989, 0x7A7A, 0x8989, 0x7A7A,
			0x898959, 0x7A7A4A, 0x898959, 0x7A7A4A, 0x898959, 0x7A7A4A, 0x898959, 0x7
			A7A4A,
			0x898959, 0x7A7A4A, 0x898959, 0x7A7A4A, 0x8989, 0x7A7A, 0x898989, 0x7A7A7
			A,
			0x898959, 0x7A7A4A, 0x898959, 0x7A7A4A, 0x898959, 0x7A7A4A, 0x898959, 0x7
			A7A4A,
			0x898959, 0x7A7A4A, 0x8959, 0x7A4A, 0x8959, 0x7A4A, 0x7A7A3B, 0x89894A,
			0x8959, 0x7A4A, 0x8959, 0x7A4A, 0x4A4A59, 0x2C2C3B, 0x3B3B4A, 0x4A4A59,
			0x2C2C3B, 0x3B3B4A, 0x4A4A59, 0x2C2C3B, 0x3B3B4A, 0x4A4A59, 0x2C2C3B, 0x3
			B3B4A,
			0x2C2C2C, 0x595959, 0x3B3B3B, 0x4A4A4A, 0x2C2C2C, 0x595959, 0x3B3B3B, 0x4
			A4A4A,
			0x2C2C2C, 0x595959, 0x3B3B3B, 0x4A4A4A, 0x2C2C2C, 0x595959, 0x3B3B3B, 0x4
			A4A4A,
			0x442C2C, 0x545959, 0x443B3B, 0x444A4A, 0x444, 0x2C42C2C, 0x5945959, 0x3B
			43B3B,
			0x4A44A4A, 0x42E4, 0x42E2C, 0x42E59, 0x42E3B, 0x42E4A, 0x42C, 0x459,
			0x43B, 0x44A, 0x42E4, 0x4444, 0x42E4, 0x4455, 0x3B3B3B3B, 0x4A4A4A4A,
			0x3B3B3B3B, 0x4A4A4A4A, 0x4455, 0x2C2C2C2C, 0x59595959, 0x3B3B3B3B, 0x4A4
			A4A4A, 0x393955,
			0x393955, 0x393955, 0x393955, 0x2C2C2C, 0x595959, 0x3B3B3B, 0x4A4A4A, 0x2
			C2C2C,
			0x595959, 0x3B3B3B, 0x4A4A4A, 0x2C2C2C, 0x595959, 0x3B3B3B, 0x4A4A4A, 0x4
			2C2C,
			0x45959, 0x43B3B, 0x44A4A, 0x42C2C, 0x45959, 0x43B3B, 0x44A4A, 0x2C2C2C,
			0x595959, 0x3B3B3B, 0x4A4A4A, 0x2C2C2C, 0x595959, 0x3B3B3B, 0x4A4A4A, 0x2
			C2C2C,
			0x595959, 0x3B3B3B, 0x4A4A4A, 0x42C2C, 0x45959, 0x43B3B, 0x44A4A, 0x42C2C
			,
			0x45959, 0x43B3B, 0x44A4A, 0x2C2C2C, 0x595959, 0x3B3B3B, 0x4A4A4A, 0x2C2C
			2C,
			0x595959, 0x3B3B3B, 0x4A4A4A, 0x444, 0x2C2C, 0x4455, 0x3B3B3B3B, 0x4A4A4A
			4A,
			0x3B3B3B3B, 0x4A4A4A4A, 0x4455, 0x2C2C2C2C, 0x59595959, 0x3B3B3B3B, 0x4A4
			A4A4A, 0x455,
			0x393939, 0x3B3B3B, 0x4A4A4A, 0x393939, 0x39394, 0x39394, 0x392A39, 0x392
			A39,
			0x393939, 0x444, 0x393939, 0x444, 0x3B3B3B, 0x4A4A4A, 0x393955, 0x393955,
			0x445, 0x445, 0x2C2C2C, 0x595959, 0x3B3B3B, 0x4A4A4A, 0x2C2C, 0x5959,
			0x3B3B, 0x4A4A, 0x2C2C, 0x5959, 0x3B3B, 0x4A4A, 0x2C2C2C, 0x42C2C,
			0x2C2C2C, 0x42C2C, 0x393939, 0x2C2C2C, 0x595959, 0x3B3B3B, 0x4A4A4A, 0x2C
			2C2C,
			0x595959, 0x3B3B3B, 0x4A4A4A, 0x2C2C, 0x5959, 0x3B3B, 0x4A4A, 0x393939,
			0x2A2A2A, 0x394, 0x394, 0x2A39, 0x2A39, 0x2A39, 0x2A39, 0x2A39,
			0x2A39, 0x2A39, 0x2A39, 0x39392A, 0x44439, 0x44439, 0x4439, 0x39392A,
			0x4439, 0x39392A, 0x4444, 0x2A4, 0x44, 0x439, 0x42A, 0x42C2C,
			0x45959, 0x43B3B, 0x44A4A, 0x42C2C, 0x45959, 0x43B3B, 0x44A4A, 0x42C2C,
			0x43B3B, 0x44A4A, 0x455, 0x43939, 0x42A2A, 0x43939, 0x444, 0x43939,
			0x42A2A, 0x43939, 0x42A2A, 0x444, 0x43939, 0x42A2A, 0x42C2C, 0x45959,
			0x43B3B, 0x44A4A, 0x42C2C, 0x45959, 0x43B3B, 0x44A4A, 0x2C2C2C, 0x595959,
			0x3B3B3B, 0x4A4A4A, 0x42C2C, 0x45959, 0x43B3B, 0x44A4A, 0x42C2C, 0x45959,
			0x43B3B, 0x44A4A, 0x42C2C, 0x45959, 0x43B3B, 0x44A4A, 0x2C2C2C, 0x595959,
			0x3B3B3B, 0x4A4A4A, 0x42C2C, 0x45959, 0x43B3B, 0x44A4A, 0x2C2C2C, 0x59595
			9,
			0x3B3B3B, 0x4A4A4A, 0x42C2C, 0x45959, 0x43B3B, 0x44A4A, 0x2C2C2C, 0x59595
			9,
			0x3B3B3B, 0x4A4A4A, 0x42C2C, 0x45959, 0x43B3B, 0x44A4A, 0x2C2C2C, 0x59595
			9,
			0x3B3B3B, 0x4A4A4A, 0x42C2C, 0x45959, 0x43B3B, 0x44A4A, 0x42E2C0, 0x42E59
			0,
			0x42E3B0, 0x42E4A0, 0x393939, 0x393939, 0x444, 0x393939, 0x393939, 0x444,
			0x444, 0x2C2C2C, 0x595959, 0x3B3B3B, 0x4A4A4A, 0x2C2C2C, 0x595959, 0x3B3B
			3B,
			0x4A4A4A, 0x2C2C2C, 0x595959, 0x3B3B3B, 0x4A4A4A, 0x2C2C2C, 0x595959, 0x3
			B3B3B,
			0x4A4A4A, 0x393939, 0x2A2A2A, 0x393939, 0x2A2A2A, 0x2A2A2A, 0x2A2A2A, 0x2
			C2C2C,
			0x595959, 0x3B3B3B, 0x4A4A4A, 0x42C2C, 0x45959, 0x43B3B, 0x44A4A, 0x2C2C2
			C2C,
			0x59595959, 0x3B3B3B3B, 0x4A4A4A4A, 0x440, 0x2C2C2C, 0x42C2C, 0x1F1F, 0x4
			4,
			0x55, 0x888, 0x777, 0x777, 0x888, 0x777, 0x777, 0x888,
			0x777, 0x777, 0x888, 0x777, 0x777, 0x73F7, 0x43F4, 0x43F4,
			0x0, 0x44, 0x44, 0x44, 0x85, 0x74, 0x47, 0x58,
			0x44, 0x55, 0x88, 0x77, 0x77, 0x44, 0x54, 0x3F0,
			0x3F0, 0x77, 0x77, 0x87, 0x87, 0x87, 0x87, 0x87,
			0x87, 0x87, 0x87, 0x84, 0x84, 0x84, 0x84, 0x84,
			0x84, 0x85, 0x85, 0x85, 0x85, 0x84, 0x84, 0x84,
			0x84, 0x85, 0x85, 0x85, 0x85, 0x777, 0x777, 0x888,
			0x777, 0x777, 0x888, 0x777, 0x777, 0x888, 0x777, 0x777,
			0x888, 0x777, 0x777, 0x88, 0x77, 0x77, 0x73, 0x73,
			0x74, 0x74, 0x74, 0x74, 0x74, 0x74, 0x74, 0x74,
			0x75, 0x75, 0x75, 0x75, 0x75, 0x75, 0x75, 0x75,
			0x74, 0x74, 0x74, 0x74, 0x74, 0x74, 0x74, 0x74,
			0x75, 0x75, 0x75, 0x75, 0x75, 0x75, 0x75, 0x75,
			0x88, 0x77, 0x77, 0x88, 0x77, 0x77, 0x8888, 0x7777,
			0x7777, 0x8888, 0x7777, 0x7777, 0x8888, 0x7777, 0x7777, 0x8888,
			0x7777, 0x7777, 0x888, 0x777, 0x777, 0x888, 0x777, 0x777,
			0x37, 0x48, 0x48, 0x48, 0x48, 0x47, 0x47, 0x47,
			0x47, 0x1FE1F, 0xFE0F, 0x3FE3F, 0x1FE1F, 0xFE0F, 0x3FE3F, 0x88,
			0x77, 0x77, 0x58, 0x58, 0x58, 0x58, 0x57, 0x57,
			0x57, 0x57, 0x448, 0x444, 0x555, 0x444, 0x555, 0x0,
			0x0, 0x0, 0x444, 0x555, 0x444, 0x555, 0x88, 0x77,
			0x33, 0x44, 0x55, 0x7F3F, 0x444, 0x444, 0x888, 0x777,
			0x777, 0x888, 0x777, 0x777, 0x888, 0x777, 0x777, 0x888,
			0x777, 0x777, 0x444, 0x555, 0x444, 0x555, 0x44, 0x54,
			0x4444, 0x7F3F, 0x7F3F, 0x7F3F, 0x7F3F, 0x7F3F, 0x7F3F, 0x7F3F,
			0x7F3F, 0x7F3F, 0x88, 0x88, 0x77, 0x77, 0x88, 0x77,
			0x77, 0x88, 0x77, 0x77, 0x88, 0x77, 0x77, 0x4,
			0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4,
			0x4, 0x4, 0x4, 0x4, 0x88, 0x77, 0x77, 0x88,
			0x77, 0x77, 0x4444, 0x4444, 0x88, 0x77, 0x77, 0x77,
			0x77, 0x77, 0x77, 0x77, 0x88, 0x77, 0x77, 0x88,
			0x77, 0x77, 0x88, 0x77, 0x77, 0x88, 0x77, 0x77,
			0x88, 0x77, 0x77, 0x48, 0x48, 0x48, 0x48, 0x47,
			0x47, 0x47, 0x47, 0x58, 0x58, 0x58, 0x58, 0x57,
			0x57, 0x57, 0x57, 0x17F0F, 0x40, 0x1F1F1F, 0x41F1F, 0x40,
			0x0, 0x442E0, 0x442E0, 0x442E0, 0x442E0, 0x2E2C, 0x2E3B, 0x2E4A,
			0x2E2C, 0x2E2C, 0x2E4A, 0x2E4A, 0x3B, 0x4A0, 0x2E2C0, 0x2E3B0,
			0x2E4A0, 0x2E4A0, 0x2E4A0, 0x4A4A4A, 0x2C2C2C, 0x3B3B3B, 0x4A4A4A, 0x2C2C
			2C,
			0x3B3B3B, 0x4A4A4A, 0x2C2C2C, 0x3B3B3B, 0x4A4A4A, 0x2C2C2C, 0x3B3B3B, 0x4
			A4A4A,
			0x44A7A, 0x44A7A, 0x7A7A4A, 0x7A7A44, 0x7A7A4A, 0x7A7A44, 0x2C2C2C, 0x2C2
			C44,
			0x3B3B3B, 0x3B3B44, 0x4A4A4A, 0x4A4A44, 0x7A7A4A, 0x7A7A44, 0x7A7A4A, 0x7
			A7A44,
			0x2C2C2C, 0x2C2C44, 0x3B3B3B, 0x3B3B44, 0x4A4A4A, 0x4A4A44, 0x2C2C2C, 0x2
			C2C44,
			0x3B3B3B, 0x3B3B44, 0x4A4A4A, 0x4A4A44, 0x47A4A, 0x47A4A, 0x7A7A, 0x7A7A,
			0x7A7A7A7A, 0x7A7A7A, 0x2C2C2C, 0x3B3B3B, 0x4A4A4A, 0x2C2C2C, 0x3B3B3B, 0
			x4A4A4A,
			0x3B3B3B3B, 0x3B3B3B3B, 0x7A7A7A, 0x2C2C2C, 0x3B3B3B, 0x4A4A4A, 0x2C2C2C,
			0x3B3B3B,
			0x4A4A4A, 0x3B3B3B3B, 0x4A2C2C4A, 0x4A3B3B4A, 0x4A3B3B4A, 0x4A2C2C4A, 0x4
			A3B3B4A, 0x4A3B3B4A,
			0x2C2C3B, 0x3B3B4A, 0x2C2C3B, 0x3B3B4A, 0x2C2C3B, 0x3B3B4A, 0x2C2C3B, 0x3
			B3B4A,
			0x7A7A7A7A, 0x2C4A4A4A, 0x4A4A3B, 0x3B3B2C, 0x3B3B2C, 0x4A4A2C, 0x4A4A3B,
			0x3B3B2C,
			0x4A4A3B, 0x7A7A, 0x7A7A, 0x7A7A, 0x7A7A, 0x7A7A, 0x2C2C2C, 0x3B3B3B,
			0x4A4A4A, 0x7A7A, 0x4A4A4A4A, 0x4A4A4A, 0x2C2C2C, 0x3B3B3B, 0x4A4A4A, 0x4
			A4A4A,
			0x4A4A4A, 0x2C2C2C, 0x3B3B3B, 0x4A4A4A, 0x2C2C2C, 0x3B3B3B, 0x4A4A4A, 0x4
			A4A4A,
			0x4A4A4A, 0x2C2C2C, 0x3B3B3B, 0x4A4A4A, 0x2C2C2C, 0x3B3B3B, 0x4A4A4A, 0x4
			A4A4A,
			0x4A2C4A, 0x4A3B4A, 0x4A2C4A, 0x4A4A4A, 0x3B4A, 0x2C3B, 0x3B4A, 0x3B4A,
			0x2C3B, 0x3B4A, 0x2E0, 0x2E0, 0x2E0, 0x2E0, 0x2E0, 0x2E0,
			0x2E0, 0x2E0, 0x1, 0xF0, 0x0, 0x4442E0, (1U<<31) | 370, 0x40,
			0x4, 0x5, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4,
			0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4,
			0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4,
			0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4,
			0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4,
			0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x4,
			0x5, 0x42E, 0x1F1F, 0x1F1F, (1U<<31) | 0, 0x2E4, 0x42E0, 0x42E4,
			0x1F1F, (1U<<31) | 0, 0x1F1F, (1U<<31) | 0, 0x2EE2E0, 0x2EE0, 0x2E0, 0x2E
			,
			0x0, 0x1F1F, (1U<<31) | 0, (1U<<31) | 0, (1U<<31) | 0, 0x2E2E0, 0x2E0, 0x
			42E2E2E0,
			0x2E0, (1U<<31) | 864, (1U<<31) | 861, (1U<<31) | 864, (1U<<31) | 864, (1
			U<<31) | 864, (1U<<31) | 864, (1U<<31) | 864,
			(1U<<31) | 864, (1U<<31) | 864, (1U<<31) | 864, (1U<<31) | 861, (1U<<31)
			| 864, (1U<<31) | 864, (1U<<31) | 864, (1U<<31) | 861,
			(1U<<31) | 864, (1U<<31) | 864, (1U<<31) | 861, (1U<<31) | 864, (1U<<31)
			| 861, (1U<<31) | 864, (1U<<31) | 864, (1U<<31) | 861,
			(1U<<31) | 861, 0x595959, 0x595959, 0x595959, 0x595959, 0x5959, 0x25959,
			(1U<<31) | 29,
			(1U<<31) | 65, (1U<<31) | 193, (1U<<31) | 227, (1U<<31) | 125, (1U<<31) |
			171, (1U<<31) | 77, (1U<<31) | 101, (1U<<31) | 41,
			(1U<<31) | 53, (1U<<31) | 205, (1U<<31) | 239, (1U<<31) | 137, (1U<<31) |
			149, (1U<<31) | 89, (1U<<31) | 113, 0x4A2E4A,
			0x4B2E4B, 0x592E59, 0x5A2E5A, 0x4A4A2E0, 0x4B4B2E0, 0x59592E0, 0x5A5A2E0,
			0x2E5A,
			0x42D2D3C, 0x2D2D, 0x4B4B, 0x3C3C, 0x4B4B3C, 0x3C3C2D, 0x4B4B3C, 0x3C3C2D
			,
			0x2D2D2D, 0x3C3C3C, 0x2D2D2D, 0x3C3C3C, 0x2D2D2D, 0x3C3C3C, 0x44A4A4A, 0x
			44B4B4B,
			0x2D2D2D2D, 0x43C3C3C, 0x2C2C, 0x2C2D, 0x4A4A, 0x4A4B, 0x5959, 0x595A,
			0x3B3B, 0x3B3C, 0x4B4B4B, 0x7B7B7B, 0x4B4B4B, 0x3C3C3C, 0x3C3C3C, 0x4B4B4
			B,
			0x3C3C3C, 0x3C3C3C, 0x2D2D3C, 0x3C3C4B, 0x2D2D2D, 0x4B4B4B, 0x3C3C3C, 0x2
			D2D2D,
			0x4B4B4B, 0x3C3C3C, 0x2D2D2D, 0x4B4B4B, 0x3C3C3C, 0x2D2D2D, 0x4B4B4B, 0x3
			C3C3C,
			0x2D4, 0x2C4B, 0x2C5A, 0x2C3C, 0x4A5A, 0x3B4B, 0x3B5A, 0x2C4B,
			0x2C5A, 0x2C3C, 0x4A5A, 0x3B4B, 0x3B5A, 0x4B4B5A, 0x3C3C3C, 0x3C3C3C,
			0x3C3C3C, 0x4B4B5A, 0x2D2D5A, 0x2D2D2D, 0x2D2D2D, 0x4B4B4B, 0x3C3C3C, 0x4
			A4B4B,
			0x45A5A, 0x45A5A, 0x595A5A, 0x3B3C3C, 0x44B4B, 0x45A5A, 0x43C3C, 0x4A4A4A
			,
			0x4B4B4B, 0x595959, 0x5A5A5A, 0x4A4B4B, 0x3B3C3C, 0x44B4B, 0x43C3C, 0x4A4
			A4A,
			0x4B4B4B, 0x4A4B4B, 0x45A5A, 0x45A5A, 0x595A5A, 0x3B3C3C, 0x44B4B, 0x45A5
			A,
			0x43C3C, 0x4A4A4A, 0x4B4B4B, 0x595959, 0x5A5A5A, 0x2D2D2D, 0x3C3C3C, 0x2D
			2D2D,
			0x3C3C3C, 0x898A, 0x7A7A, 0x7A7B, 0x2E5A, 0x25A59, 0x2595A5A, 0x25A5A5A,
			0x4C4C4C, 0x4C4C3, 0x4C4C, 0x4C1C4C4C, 0x4C1C4C, 0x5B5B, 0x5B1B5B5B, 0x5B
			1B5B,
			0x7C4C, 0x4C7C, 0x894, 0x895, 0x7A4, 0x7A5, 0x894, 0x895,
			0x7A4, 0x7A5, 0x48989, 0x47A7A, 0x58989, 0x57A7A, 0x42E4B8B, (1U<<31) | 4
			24,
			0x42E4C4C, (1U<<31) | 435, 0x42E4B5B, (1U<<31) | 413, 0x42E4C7C, (1U<<31)
			| 446, 0x42E5B8B, (1U<<31) | 490,
			0x42E5B4B, (1U<<31) | 457, 0x42E5B5B, (1U<<31) | 468, 0x42E5B7B, (1U<<31)
			| 479, 0x334, 0x334,
			0x8B8B8B, 0x7C7C7C, 0x8B8B8B, 0x7C7C7C, 0x4C4C1C4C, (1U<<31) | 828, 0x7C7
			C1C7C, 0x5B5B1B5B,
			0x4A4C, 0x44C, 0x595B, 0x55B, 0x4C4C4C, 0x5B5B5B, 0x4C4C4C, 0x5B5B5B,
			0x4C4C4C, 0x5B5B5B, 0x4C4C4C, 0x5B5B5B, 0x2C4C, 0x2C5B, 0x4B5B, 0x3C4C,
			0x3B5B, 0x45B5B, 0x45B5B, 0x45B5B, 0x45B5B, 0x8B8B, 0x7C7C, 0x8989,
			0x7A7A, 0x8B8B, 0x7C7C, 0x8989, 0x7A7A, 0x48B8B, 0x47C7C, 0x4898989,
			0x47A7A7A, 0x8B8B, 0x7C7C, 0x8989, 0x7A7A, 0x8B8B, 0x7C7C, 0x8989,
			0x7A7A, 0x48B4B2E0, (1U<<31) | 729, 0x44C4C2E0, (1U<<31) | 642, 0x45B4B2E
			0, (1U<<31) | 666, 0x47C4C2E0,
			(1U<<31) | 713, 0x48B5B2E0, (1U<<31) | 739, 0x44B5B2E0, (1U<<31) | 632, 0
			x45B5B2E0, (1U<<31) | 676, 0x47B5B2E0,
			(1U<<31) | 703, 0x8B8B, 0x7C7C, 0x898989, 0x7A7A7A, 0x2E8B, 0x898B, 0x2E7
			C,
			0x7A7C, 0x3C7C, 0x47C3C, 0x8A8A8A, 0x7B7B7B, 0x48A8A8A, 0x47B7B7B, (1U<<3
			1) | 819,
			0x7B7B7B7B, 0x28A8A8A, 0x27B7B7B, 0x8A7A, 0x8A4A, 0x7A8A, 0x7B4B, 0x4A8A,
			0x4B7B, 0x8A4A, 0x7B4B, 0x47B7B7B, 0x8A8A8A, 0x7B7B7B, 0x8A8A8A, 0x7B7B7B
			,
			0x2E2D, 0x892E89, 0x8A2E8A, 0x7A2E7A, 0x7B2E7B, 0x89892E0, 0x8A8A2E0, 0x7
			A7A2E0,
			0x7B7B2E0, 0x8A8A8A, 0x7B7B7B, 0x8A8A8A, 0x7B7B7B, 0x8A4, 0x7B4, 0x5A5A4,
			0x5A5A4, 0x5A5A4, 0x7B7B, 0x48A8A, 0x47B7B, 0x7B7B, 0x8A8A, 0x7B7B,
			0x2D2E0, 0x8A2E0, 0x7B2E0, 0x2E8A, 0x2E7A, 0x2E7B, 0x2E8A, 0x2E7B,
			0x28A89, 0x27B7A, 0x24B4A, 0x2898A8A, 0x27A7B7B, 0x24A4B4B, 0x28A8A8A, 0x
			27B7B7B,
			0x24B4B4B, 0x598989, 0x5A8A8A, 0x4A7A7A, 0x4B7B7B, 0x89894, 0x8A8A4, 0x7A
			7A4,
			0x7B7B4, 0x89894, 0x8A8A4, 0x7A7A4, 0x7B7B4, 0x89894, 0x8A8A4, 0x7A7A4,
			0x7B7B4, 0x0, 0x0, 0x444, 0x555, 0x444, 0x555, 0x444,
			0x555, 0x444, 0x555, (1U<<31) | 801, (1U<<31) | 819, (1U<<31) | 837, 0x7A
			7A7A7A, 0x7B7B7B7B,
			0x7C7C7C7C, (1U<<31) | 801, 0x7A7A7A7A, (1U<<31) | 801, (1U<<31) | 819, (
			1U<<31) | 837, 0x7A7A7A7A, 0x7B7B7B7B,
			0x7C7C7C7C, (1U<<31) | 801, (1U<<31) | 819, (1U<<31) | 837, 0x7A7A7A7A, 0
			x7B7B7B7B, 0x7C7C7C7C, (1U<<31) | 801,
			0x7A7A7A7A, (1U<<31) | 801, (1U<<31) | 819, (1U<<31) | 837, 0x7A7A7A7A, 0
			x7B7B7B7B, 0x7C7C7C7C, (1U<<31) | 801,
			(1U<<31) | 819, (1U<<31) | 837, 0x7A7A7A7A, 0x7B7B7B7B, 0x7C7C7C7C, (1U<<
			31) | 801, 0x7A7A7A7A, (1U<<31) | 801,
			(1U<<31) | 819, (1U<<31) | 837, 0x7A7A7A7A, 0x7B7B7B7B, 0x7C7C7C7C, (1U<<
			31) | 801, 0x7A7A7A7A, 0x20,
			0x41C, 0x1C1C1C, 0x1C1C1C, 0x1C1C1C, 0x1C1C, 0x1C1C1C, 0x1B1B1C, 0x1C1C1C
			,
			0x1C1C1C, 0x1C4, 0x0, 0x0, (1U<<31) | 289, (1U<<31) | 859, (1U<<31) | 864
			, (1U<<31) | 864,
			(1U<<31) | 864, (1U<<31) | 864, (1U<<31) | 864, (1U<<31) | 864, (1U<<31)
			| 864, (1U<<31) | 864, (1U<<31) | 864, (1U<<31) | 864,
			(1U<<31) | 864, (1U<<31) | 334, (1U<<31) | 864, (1U<<31) | 864, (1U<<31)
			| 864, (1U<<31) | 864, (1U<<31) | 864, (1U<<31) | 864,
			(1U<<31) | 864, (1U<<31) | 864, (1U<<31) | 864, (1U<<31) | 864, (1U<<31)
			| 764, (1U<<31) | 652, (1U<<31) | 864, (1U<<31) | 864,
			(1U<<31) | 864, (1U<<31) | 864, (1U<<31) | 864, (1U<<31) | 846, (1U<<31)
			| 864, (1U<<31) | 864, (1U<<31) | 864, (1U<<31) | 864,
			(1U<<31) | 864, (1U<<31) | 864, (1U<<31) | 864, (1U<<31) | 864, (1U<<31)
			| 864, (1U<<31) | 768, (1U<<31) | 768, (1U<<31) | 768,
			(1U<<31) | 864, (1U<<31) | 864, (1U<<31) | 768, (1U<<31) | 768, (1U<<31)
			| 864, (1U<<31) | 864, (1U<<31) | 864, (1U<<31) | 768,
			(1U<<31) | 768, (1U<<31) | 768, (1U<<31) | 864, (1U<<31) | 864, (1U<<31)
			| 864, (1U<<31) | 864, (1U<<31) | 864, (1U<<31) | 864,
			(1U<<31) | 864, (1U<<31) | 864, (1U<<31) | 864, (1U<<31) | 864, (1U<<31)
			| 864, (1U<<31) | 864, (1U<<31) | 864, (1U<<31) | 864,
			(1U<<31) | 864, 0x2595959, 0x4, 0x5, 0x4, 0x5, (1U<<31) | 531, (1U<<31) |
			657,
			(1U<<31) | 686, (1U<<31) | 531, (1U<<31) | 657, (1U<<31) | 686, 0x4A4A4A,
			0x4A4A4A, 0x4A4A4A, 0x24A4A4A,
			0x4A4A4A, 0x4A4A4A, 0x4A4A4A4A, 0x898989, 0x2E0, 0x2898989, 0x2898989, 0x
			89894,
			0x89894, 0x89894, 0x89894, 0x89894, 0x89894, 0x4A89, 0x4A7A, 0x894A,
			0x897A, 0x7A4A, 0x7A89, 0x894, 0x895, 0x897A7A, 0x48989, 0x58989,
			0x7A8989, 0x894A, 0x7A4A, 0x894, 0x895, 0x898989, 0x0, 0x2E2C2C0,
			0x898989, 0x898989, 0x0, 0x898989, 0x898989, 0x894, 0x898989, 0x4A4A3B,
			0x3B3B2C, 0x3B3B2C, 0x2C2C2C, 0x3B3B3B, 0x2C2C2C, 0x3B3B3B, 0x2C2C2C, 0x3
			B3B3B,
			0x3B3B4A, 0x3B3B3B, 0x2C2C2C, 0x3B3B3B, 0x2C2C2C, 0x2C4, 0x3B3B3B, 0x3B3B
			3B,
			0x4A4A59, 0x2C2C59, 0x4A4A4A, 0x45959, 0x45959, 0x595959, 0x3B3B3B, 0x44A
			4A,
			0x45959, 0x43B3B, 0x4A4A4A, 0x3B3B3B, 0x44A4A, 0x43B3B, 0x4A4A4A, 0x45959
			,
			0x45959, 0x595959, 0x3B3B3B, 0x44A4A, 0x45959, 0x43B3B, 0x2C2C2C, 0x3B3B3
			B,
			0x2C2C2C, 0x3B3B3B, 0x8989, 0x8989, 0x4A2E0, 0x2C2E0, 0x892E0, 0x898989,
			0x89894, 0x89894, 0x89894, 0x89894, 0x89894, 0x89894, 0x898989, 0x7A7A7A,
			0x898989, 0x7A7A7A, 0x898989, 0x7A7A7A, 0x2E2C, 0x442E0, 0x440, 0x4898989
			,
			0x47A7A7A, (1U<<31) | 801, 0x7A7A7A7A, 0x4898989, 0x47A7A7A, 0x47A4, 0x47
			A7A7A, 0x2E59,
			0x42C2C3B, 0x4A4A3B, 0x2C2C2C2C, 0x43B3B3B, 0x42C4, 0x44A4, 0x4595, 0x3B3
			B,
			0x2C2C2C, 0x4A4A4A, 0x4A4A4A, 0x3B3B3B, 0x2C2C2C, 0x4A4A4A, 0x4A4A4A, 0x3
			B3B3B,
			0x2C4A, 0x2C59, 0x2C3B, 0x4A59, 0x3B4A, 0x3B59, 0x2C4A, 0x2C59,
			0x2C3B, 0x4A59, 0x3B4A, 0x3B59, 0x4A4A59, 0x59594, 0x59594, 0x59594,
			0x48989, 0x47A7A, 0x4898989, 0x47A7A7A, 0x344, 0x444, 0x244, 0x555,
			0x242C42C4, 0x242C42C4, 0x242C42C4, 0x242C42C4, 0x242C42C4, 0x242C42C4, (
			1U<<31) | 19, 0x22C2C4,
			0x22C2C4, 0x22C2C4, 0x22C2C4, 0x22C2C4, 0x22C2C4, 0x22C2C2C, 0x2C5959, 0x
			225959,
			0x595959, 0x22595959, 0x892E0, 0x7A2E0, 0x7A7A7A, 0x27A7A7A, 0x27A7A7A, 0
			x7A7A4,
			0x7A7A4, 0x7A7A4, 0x7A7A4, 0x7A7A4, 0x7A7A4, (1U<<31) | 815, (1U<<31) | 8
			55, (1U<<31) | 849,
			(1U<<31) | 797, 0x47A7A, 0x57A7A, 0x7A4, 0x7A5, (1U<<31) | 815, (1U<<31)
			| 797, 0x7A4,
			0x7A5, 0x7A7A7A, 0x2E0, 0x7A7A7A, 0x7A7A7A, 0x7A7A7A, 0x7A7A7A, 0x7A4,
			0x7A7A7A, (1U<<31) | 335, 0x7A7A, 0x7A7A, 0x7A7A, 0x7A7A, 0x0, 0x7A7A,
			0x7A7A, 0x2E0, 0x7A2E0, 0x7A7A7A, 0x7A7A4, 0x7A7A4, 0x7A7A4, 0x7A7A4,
			0x7A7A4, 0x7A7A4, (1U<<31) | 861, 0x2C2C, (1U<<31) | 861, 0x4A4A, (1U<<31
			) | 861, 0x3B3B,
			(1U<<31) | 864, 0x4A4A4A, (1U<<31) | 864, 0x3B3B3B, (1U<<31) | 864, 0x3B3
			B3B, (1U<<31) | 864, 0x4A4A4A,
			(1U<<31) | 864, 0x3B3B3B, (1U<<31) | 864, 0x3B3B3B, (1U<<31) | 864, 0x2C2
			C3B, (1U<<31) | 864, 0x3B3B3B,
			(1U<<31) | 864, 0x2C2C2C, (1U<<31) | 864, 0x2C2C2C, (1U<<31) | 864, 0x4A4
			A4A, (1U<<31) | 864, 0x3B3B3B,
			0x444, 0x555, 0x3B7A, 0x3B7B, 0x47A3B, 0x47B3B, 0x40, 0x50,
			0x40, 0x50, 0x20, 0x4, 0x0, 0x8989, 0x8A8A, 0x7A7A,
			0x7B7B, 0x8989, 0x7A7A, 0x59595959, 0x5A5A5A5A, 0x22C2C2C, 0x24A4A4A, 0x2
			595959,
			0x22C2C2C, 0x24A4A4A, 0x2595959, 0x23B3B3B, 0x23B3B3B, (1U<<31) | 217, (1
			U<<31) | 251, (1U<<31) | 161,
			(1U<<31) | 183, 0x2C4A, 0x2C59, 0x2C3B, 0x4A59, 0x2C4A, 0x2C59, 0x2C3B,
			0x4A59, 0x3B4A, 0x3B59, 0x3B4A, 0x3B59, 0x2C3B, 0x4A59, 0x3B4A,
			0x4A4A4A4A, 0x594A4A59, 0x594A4A59, 0x4A4A4A4A, 0x594A4A59, 0x594A4A59, 0
			x4A3B3B4A, 0x3B3B3B3B,
			0x4A3B3B4A, 0x3B3B3B3B, 0x4A3B3B4A, 0x4A3B3B4A, 0x2C2C2C2C, 0x2C2C2C, 0x2
			2C2C, 0x4A4A4A,
			0x24A4A, 0x595959, 0x25959, 0x3B3B3B, 0x23B3B, 0x2C2C2C, 0x4A4A4A, 0x5959
			59,
			0x3B3B3B, 0x2C2C2C, 0x4A4A4A, 0x595959, 0x3B3B3B, 0x4, 0x44, 0x2E2E,
			0x43F0, 0x0, 0x40, 0x4444, (1U<<31) | 625, 0x3F0, 0x3F4, 0x3F0,
			0x4, 0x4, 0x4, 0x44, 0x43F, 0x7F3F, 0x3F4, 0x3F4,
			0x3F4, 0x2E3F0, 0x2E3F0, 0x2E3F0, 0x2E3F0, 0x2E3F0, 0x43F4, 0x3F4,
			0x3F0, 0x3F0, 0x43F0, 0x43F0, 0x43F4, 0x43F0, 0x3F4, 0x43F0,
			0x7F3F0, 0x43F0, 0x2E3F0, 0x440, 0x43F0, 0x43F0, 0x7F3F0, 0x40,
			0x43F0, 0x2E3F0, 0x444, 0x0, 0x3F0, 0x3F4, 0x3F4, 0x2E,
			0x444, 0
			};
			static const unsigned char IIT_LongEncodingTable[] = {
			/* 0 */ 19, 15, 0, 1, 15, 0, 15, 0, 0,
			/* 9 */ 0, 15, 3, 15, 7, 15, 8, 4, 1, 0,
			/* 19 */ 12, 2, 12, 2, 4, 12, 2, 4, 2, 0,
			/* 29 */ 10, 4, 10, 4, 14, 2, 10, 4, 10, 4, 2, 0,
			/* 41 */ 10, 4, 10, 4, 14, 2, 9, 5, 10, 4, 2, 0,
			/* 53 */ 10, 4, 10, 4, 14, 2, 10, 5, 10, 4, 2, 0,
			/* 65 */ 11, 4, 11, 4, 14, 2, 11, 4, 11, 4, 2, 0,
			/* 77 */ 9, 5, 9, 5, 14, 2, 10, 4, 9, 5, 2, 0,
			/* 89 */ 9, 5, 9, 5, 14, 2, 9, 5, 9, 5, 2, 0,
			/* 101 */ 10, 5, 10, 5, 14, 2, 10, 4, 10, 5, 2, 0,
			/* 113 */ 10, 5, 10, 5, 14, 2, 10, 5, 10, 5, 2, 0,
			/* 125 */ 10, 7, 10, 7, 14, 2, 10, 4, 10, 7, 2, 0,
			/* 137 */ 10, 7, 10, 7, 14, 2, 9, 5, 10, 7, 2, 0,
			/* 149 */ 10, 7, 10, 7, 14, 2, 10, 5, 10, 7, 2, 0,
			/* 161 */ 10, 7, 10, 7, 10, 7, 10, 7, 2, 0,
			/* 171 */ 11, 7, 11, 7, 14, 2, 11, 4, 11, 7, 2, 0,
			/* 183 */ 11, 7, 11, 7, 11, 7, 11, 7, 2, 0,
			/* 193 */ 9, 8, 9, 8, 14, 2, 10, 4, 9, 8, 2, 0,
			/* 205 */ 9, 8, 9, 8, 14, 2, 9, 5, 9, 8, 2, 0,
			/* 217 */ 9, 8, 9, 8, 9, 8, 9, 8, 2, 0,
			/* 227 */ 10, 8, 10, 8, 14, 2, 10, 4, 10, 8, 2, 0,
			/* 239 */ 10, 8, 10, 8, 14, 2, 10, 5, 10, 8, 2, 0,
			/* 251 */ 10, 8, 10, 8, 10, 8, 10, 8, 2, 0,
			/* 261 */ 11, 2, 11, 2, 11, 2, 11, 2, 11, 2, 11, 2, 11, 2, 0,
			/* 276 */ 19, 4, 4, 14, 2, 0,
			/* 282 */ 0, 14, 18, 5, 14, 2, 0,
			/* 289 */ 0, 16, 16, 14, 2, 0,
			/* 295 */ 15, 2, 15, 2, 15, 6, 15, 6, 15, 2, 0,
			/* 306 */ 15, 2, 15, 2, 15, 6, 15, 6, 15, 6, 15, 2, 0,
			/* 319 */ 15, 2, 15, 2, 15, 6, 15, 6, 15, 6, 15, 6, 15, 2, 0,
			/* 334 */ 16, 16, 16, 2, 0,
			/* 339 */ 15, 2, 23, 2, 0,
			/* 344 */ 15, 2, 23, 2, 23, 2, 0,
			/* 351 */ 15, 2, 15, 2, 24, 2, 24, 2, 0,
			/* 360 */ 15, 0, 15, 0, 14, 2, 14, 2, 4, 0,
			/* 370 */ 15, 3, 15, 3, 14, 2, 14, 2, 4, 0,
			/* 380 */ 21, 15, 2, 15, 2, 15, 2, 15, 2, 14, 2, 4, 0,
			/* 393 */ 20, 15, 2, 15, 2, 15, 2, 14, 2, 4, 0,
			/* 404 */ 19, 15, 2, 15, 2, 14, 2, 4, 0,
			/* 413 */ 11, 5, 11, 5, 2, 11, 4, 14, 2, 4, 0,
			/* 424 */ 11, 8, 11, 8, 2, 11, 4, 14, 2, 4, 0,
			/* 435 */ 12, 4, 12, 4, 3, 12, 4, 14, 2, 4, 0,
			/* 446 */ 12, 7, 12, 7, 3, 12, 4, 14, 2, 4, 0,
			/* 457 */ 11, 4, 11, 4, 2, 11, 5, 14, 2, 4, 0,
			/* 468 */ 11, 5, 11, 5, 2, 11, 5, 14, 2, 4, 0,
			/* 479 */ 11, 7, 11, 7, 2, 11, 5, 14, 2, 4, 0,
			/* 490 */ 11, 8, 11, 8, 2, 11, 5, 14, 2, 4, 0,
			/* 501 */ 0, 14, 2, 15, 2, 15, 2, 15, 2, 4, 0,
			/* 512 */ 0, 14, 2, 15, 2, 15, 2, 15, 2, 15, 2, 4, 0,
			/* 525 */ 15, 2, 23, 2, 4, 0,
			/* 531 */ 19, 3, 4, 0,
			/* 535 */ 0, 14, 2, 15, 2, 15, 2, 4, 4, 0,
			/* 545 */ 19, 15, 2, 15, 2, 14, 2, 15, 2, 15, 2, 4, 4, 0,
			/* 559 */ 0, 14, 2, 15, 2, 15, 2, 15, 2, 4, 4, 0,
			/* 571 */ 20, 15, 2, 15, 2, 15, 2, 14, 2, 15, 2, 15, 2, 15, 2, 4, 4, 0,
			/* 589 */ 0, 14, 2, 15, 2, 15, 2, 15, 2, 15, 2, 4, 4, 0,
			/* 603 */ 21, 15, 2, 15, 2, 15, 2, 15, 2, 14, 2, 15, 2, 15, 2, 15, 2, 15,
			2, 4, 4, 0,
			/* 625 */ 19, 4, 4, 4, 4, 4, 0,
			/* 632 */ 0, 14, 2, 2, 11, 5, 11, 4, 4, 0,
			/* 642 */ 0, 14, 2, 3, 12, 4, 12, 4, 4, 0,
			/* 652 */ 16, 16, 4, 4, 0,
			/* 657 */ 19, 4, 4, 0,
			/* 661 */ 7, 26, 4, 4, 0,
			/* 666 */ 0, 14, 2, 2, 11, 4, 11, 5, 4, 0,
			/* 676 */ 0, 14, 2, 2, 11, 5, 11, 5, 4, 0,
			/* 686 */ 19, 5, 4, 0,
			/* 690 */ 26, 5, 26, 5, 26, 5, 4, 0,
			/* 698 */ 8, 26, 5, 4, 0,
			/* 703 */ 0, 14, 2, 2, 11, 5, 11, 7, 4, 0,
			/* 713 */ 0, 14, 2, 3, 12, 4, 12, 7, 4, 0,
			/* 723 */ 26, 4, 26, 7, 4, 0,
			/* 729 */ 0, 14, 2, 2, 11, 4, 11, 8, 4, 0,
			/* 739 */ 0, 14, 2, 2, 11, 5, 11, 8, 4, 0,
			/* 749 */ 26, 5, 26, 8, 4, 0,
			/* 755 */ 10, 4, 10, 4, 26, 4, 10, 4, 0,
			/* 764 */ 4, 16, 4, 0,
			/* 768 */ 16, 16, 4, 0,
			/* 772 */ 7, 26, 4, 0,
			/* 776 */ 26, 5, 9, 5, 0,
			/* 781 */ 26, 5, 26, 5, 26, 5, 0,
			/* 788 */ 8, 26, 5, 0,
			/* 792 */ 26, 7, 9, 7, 0,
			/* 797 */ 16, 10, 7, 0,
			/* 801 */ 9, 8, 9, 8, 9, 8, 9, 8, 0,
			/* 810 */ 26, 8, 9, 8, 0,
			/* 815 */ 16, 9, 8, 0,
			/* 819 */ 10, 8, 10, 8, 10, 8, 10, 8, 0,
			/* 828 */ 11, 8, 11, 1, 11, 8, 11, 8, 0,
			/* 837 */ 11, 8, 11, 8, 11, 8, 11, 8, 0,
			/* 846 */ 4, 16, 0,
			/* 849 */ 10, 7, 10, 7, 16, 0,
			/* 855 */ 9, 8, 16, 0,
			/* 859 */ 0, 14, 16, 16, 0,
			/* 864 */ 16, 16, 16, 0,
			/* 868 */ 0, 17, 5, 17, 0,
			/* 873 */ 0, 17, 17, 0,
			/* 877 */ 0, 4, 4, 14, 2, 4, 27, 0,
			/* 885 */ 5, 4, 4, 14, 2, 4, 27, 0,
			/* 893 */ 0, 4, 4, 27, 0,
			255
			};
			#endif
			// Add parameter attributes that are not common to all intrinsics.
			#ifdef GET_INTRINSIC_ATTRIBUTES
			AttributeSet Intrinsic::getAttributes(LLVMContext &C, ID id) {
			static const uint8_t IntrinsicsToAttributesMap[] = {
			1, // llvm.aarch64.neon.fcvtas
			1, // llvm.aarch64.neon.fcvtau
			1, // llvm.aarch64.neon.fcvtms
			1, // llvm.aarch64.neon.fcvtmu
			1, // llvm.aarch64.neon.fcvtns
			1, // llvm.aarch64.neon.fcvtnu
			1, // llvm.aarch64.neon.fcvtps
			1, // llvm.aarch64.neon.fcvtpu
			1, // llvm.aarch64.neon.fcvtxn
			1, // llvm.aarch64.neon.fcvtzs
			1, // llvm.aarch64.neon.fcvtzu
			1, // llvm.aarch64.neon.frintn
			1, // llvm.aarch64.neon.fsqrt
			1, // llvm.aarch64.neon.rbit
			1, // llvm.aarch64.neon.saddlv
			1, // llvm.aarch64.neon.sha1c
			1, // llvm.aarch64.neon.sha1m
			1, // llvm.aarch64.neon.sha1p
			1, // llvm.aarch64.neon.smaxv
			1, // llvm.aarch64.neon.sminv
			1, // llvm.aarch64.neon.suqadd
			1, // llvm.aarch64.neon.uaddlv
			1, // llvm.aarch64.neon.umaxv
			1, // llvm.aarch64.neon.uminv
			1, // llvm.aarch64.neon.usqadd
			1, // llvm.aarch64.neon.vabd
			1, // llvm.aarch64.neon.vabs
			1, // llvm.aarch64.neon.vacgeq
			1, // llvm.aarch64.neon.vacgtq
			1, // llvm.aarch64.neon.vaddds
			1, // llvm.aarch64.neon.vadddu
			1, // llvm.aarch64.neon.vaddv
			1, // llvm.aarch64.neon.vcage
			1, // llvm.aarch64.neon.vcagt
			1, // llvm.aarch64.neon.vceq
			1, // llvm.aarch64.neon.vcge
			1, // llvm.aarch64.neon.vcgt
			1, // llvm.aarch64.neon.vchi
			1, // llvm.aarch64.neon.vchs
			1, // llvm.aarch64.neon.vclez
			1, // llvm.aarch64.neon.vcltz
			1, // llvm.aarch64.neon.vcvtd.n.s64.f64
			1, // llvm.aarch64.neon.vcvtd.n.u64.f64
			1, // llvm.aarch64.neon.vcvtf32.n.s32
			1, // llvm.aarch64.neon.vcvtf32.n.u32
			1, // llvm.aarch64.neon.vcvtf32.s32
			1, // llvm.aarch64.neon.vcvtf32.u32
			1, // llvm.aarch64.neon.vcvtf64.n.s64
			1, // llvm.aarch64.neon.vcvtf64.n.u64
			1, // llvm.aarch64.neon.vcvtf64.s64
			1, // llvm.aarch64.neon.vcvtf64.u64
			1, // llvm.aarch64.neon.vcvts.n.s32.f32
			1, // llvm.aarch64.neon.vcvts.n.u32.f32
			2, // llvm.aarch64.neon.vld1x2
			2, // llvm.aarch64.neon.vld1x3
			2, // llvm.aarch64.neon.vld1x4
			1, // llvm.aarch64.neon.vmaxnm
			1, // llvm.aarch64.neon.vmaxnmv
			1, // llvm.aarch64.neon.vmaxv
			1, // llvm.aarch64.neon.vminnm
			1, // llvm.aarch64.neon.vminnmv
			1, // llvm.aarch64.neon.vminv
			3, // llvm.aarch64.neon.vmulx
			1, // llvm.aarch64.neon.vneg
			1, // llvm.aarch64.neon.vpadd
			1, // llvm.aarch64.neon.vpfadd
			1, // llvm.aarch64.neon.vpfaddq
			1, // llvm.aarch64.neon.vpfmaxnm
			1, // llvm.aarch64.neon.vpfmaxnmq
			1, // llvm.aarch64.neon.vpfminnm
			1, // llvm.aarch64.neon.vpfminnmq
			1, // llvm.aarch64.neon.vpmax
			1, // llvm.aarch64.neon.vpmaxnm
			1, // llvm.aarch64.neon.vpmaxq
			1, // llvm.aarch64.neon.vpmin
			1, // llvm.aarch64.neon.vpminnm
			1, // llvm.aarch64.neon.vpminq
			1, // llvm.aarch64.neon.vqdmlal
			1, // llvm.aarch64.neon.vqdmlsl
			1, // llvm.aarch64.neon.vqrshls
			1, // llvm.aarch64.neon.vqrshlu
			1, // llvm.aarch64.neon.vqshls
			1, // llvm.aarch64.neon.vqshls.n
			1, // llvm.aarch64.neon.vqshlu
			1, // llvm.aarch64.neon.vqshlu.n
			1, // llvm.aarch64.neon.vqshlus.n
			1, // llvm.aarch64.neon.vrecpx
			1, // llvm.aarch64.neon.vrshlds
			1, // llvm.aarch64.neon.vrshldu
			1, // llvm.aarch64.neon.vrshrn
			1, // llvm.aarch64.neon.vrsrads.n
			1, // llvm.aarch64.neon.vrsradu.n
			1, // llvm.aarch64.neon.vshld.n
			1, // llvm.aarch64.neon.vshlds
			1, // llvm.aarch64.neon.vshldu
			1, // llvm.aarch64.neon.vshrds.n
			1, // llvm.aarch64.neon.vshrdu.n
			1, // llvm.aarch64.neon.vsli
			1, // llvm.aarch64.neon.vsqadd
			1, // llvm.aarch64.neon.vsqrshrn
			1, // llvm.aarch64.neon.vsqrshrun
			1, // llvm.aarch64.neon.vsqshlu
			1, // llvm.aarch64.neon.vsqshrn
			1, // llvm.aarch64.neon.vsqshrun
			1, // llvm.aarch64.neon.vsrads.n
			1, // llvm.aarch64.neon.vsradu.n
			1, // llvm.aarch64.neon.vsri
			1, // llvm.aarch64.neon.vsrshr
			3, // llvm.aarch64.neon.vst1x2
			3, // llvm.aarch64.neon.vst1x3
			3, // llvm.aarch64.neon.vst1x4
			1, // llvm.aarch64.neon.vsubds
			1, // llvm.aarch64.neon.vsubdu
			1, // llvm.aarch64.neon.vtbl1
			1, // llvm.aarch64.neon.vtbl2
			1, // llvm.aarch64.neon.vtbl3
			1, // llvm.aarch64.neon.vtbl4
			1, // llvm.aarch64.neon.vtbx1
			1, // llvm.aarch64.neon.vtbx2
			1, // llvm.aarch64.neon.vtbx3
			1, // llvm.aarch64.neon.vtbx4
			1, // llvm.aarch64.neon.vtstd
			1, // llvm.aarch64.neon.vuqadd
			1, // llvm.aarch64.neon.vuqrshrn
			1, // llvm.aarch64.neon.vuqshrn
			1, // llvm.aarch64.neon.vurshr
			1, // llvm.aarch64.neon.xtn
			2, // llvm.adjust.trampoline
			3, // llvm.annotation
			3, // llvm.arm.cdp
			3, // llvm.arm.cdp2
			3, // llvm.arm.clrex
			1, // llvm.arm.crc32b
			1, // llvm.arm.crc32cb
			1, // llvm.arm.crc32ch
			1, // llvm.arm.crc32cw
			1, // llvm.arm.crc32h
			1, // llvm.arm.crc32w
			3, // llvm.arm.dmb
			3, // llvm.arm.dsb
			1, // llvm.arm.get.fpscr
			3, // llvm.arm.ldrex
			3, // llvm.arm.ldrexd
			3, // llvm.arm.mcr
			3, // llvm.arm.mcr2
			3, // llvm.arm.mcrr
			3, // llvm.arm.mcrr2
			3, // llvm.arm.mrc
			3, // llvm.arm.mrc2
			1, // llvm.arm.neon.aesd
			1, // llvm.arm.neon.aese
			1, // llvm.arm.neon.aesimc
			1, // llvm.arm.neon.aesmc
			1, // llvm.arm.neon.sha1c
			1, // llvm.arm.neon.sha1h
			1, // llvm.arm.neon.sha1m
			1, // llvm.arm.neon.sha1p
			1, // llvm.arm.neon.sha1su0
			1, // llvm.arm.neon.sha1su1
			1, // llvm.arm.neon.sha256h
			1, // llvm.arm.neon.sha256h2
			1, // llvm.arm.neon.sha256su0
			1, // llvm.arm.neon.sha256su1
			1, // llvm.arm.neon.vabds
			1, // llvm.arm.neon.vabdu
			1, // llvm.arm.neon.vabs
			1, // llvm.arm.neon.vacged
			1, // llvm.arm.neon.vacgeq
			1, // llvm.arm.neon.vacgtd
			1, // llvm.arm.neon.vacgtq
			1, // llvm.arm.neon.vbsl
			1, // llvm.arm.neon.vcls
			1, // llvm.arm.neon.vclz
			1, // llvm.arm.neon.vcnt
			1, // llvm.arm.neon.vcvtas
			1, // llvm.arm.neon.vcvtau
			1, // llvm.arm.neon.vcvtfp2fxs
			1, // llvm.arm.neon.vcvtfp2fxu
			1, // llvm.arm.neon.vcvtfp2hf
			1, // llvm.arm.neon.vcvtfxs2fp
			1, // llvm.arm.neon.vcvtfxu2fp
			1, // llvm.arm.neon.vcvthf2fp
			1, // llvm.arm.neon.vcvtms
			1, // llvm.arm.neon.vcvtmu
			1, // llvm.arm.neon.vcvtns
			1, // llvm.arm.neon.vcvtnu
			1, // llvm.arm.neon.vcvtps
			1, // llvm.arm.neon.vcvtpu
			1, // llvm.arm.neon.vhadds
			1, // llvm.arm.neon.vhaddu
			1, // llvm.arm.neon.vhsubs
			1, // llvm.arm.neon.vhsubu
			2, // llvm.arm.neon.vld1
			2, // llvm.arm.neon.vld2
			2, // llvm.arm.neon.vld2lane
			2, // llvm.arm.neon.vld3
			2, // llvm.arm.neon.vld3lane
			2, // llvm.arm.neon.vld4
			2, // llvm.arm.neon.vld4lane
			1, // llvm.arm.neon.vmaxnm
			1, // llvm.arm.neon.vmaxs
			1, // llvm.arm.neon.vmaxu
			1, // llvm.arm.neon.vminnm
			1, // llvm.arm.neon.vmins
			1, // llvm.arm.neon.vminu
			1, // llvm.arm.neon.vmullp
			1, // llvm.arm.neon.vmulls
			1, // llvm.arm.neon.vmullu
			1, // llvm.arm.neon.vmulp
			1, // llvm.arm.neon.vpadals
			1, // llvm.arm.neon.vpadalu
			1, // llvm.arm.neon.vpadd
			1, // llvm.arm.neon.vpaddls
			1, // llvm.arm.neon.vpaddlu
			1, // llvm.arm.neon.vpmaxs
			1, // llvm.arm.neon.vpmaxu
			1, // llvm.arm.neon.vpmins
			1, // llvm.arm.neon.vpminu
			1, // llvm.arm.neon.vqabs
			1, // llvm.arm.neon.vqadds
			1, // llvm.arm.neon.vqaddu
			1, // llvm.arm.neon.vqdmulh
			1, // llvm.arm.neon.vqdmull
			1, // llvm.arm.neon.vqmovns
			1, // llvm.arm.neon.vqmovnsu
			1, // llvm.arm.neon.vqmovnu
			1, // llvm.arm.neon.vqneg
			1, // llvm.arm.neon.vqrdmulh
			1, // llvm.arm.neon.vqrshiftns
			1, // llvm.arm.neon.vqrshiftnsu
			1, // llvm.arm.neon.vqrshiftnu
			1, // llvm.arm.neon.vqrshifts
			1, // llvm.arm.neon.vqrshiftu
			1, // llvm.arm.neon.vqshiftns
			1, // llvm.arm.neon.vqshiftnsu
			1, // llvm.arm.neon.vqshiftnu
			1, // llvm.arm.neon.vqshifts
			1, // llvm.arm.neon.vqshiftsu
			1, // llvm.arm.neon.vqshiftu
			1, // llvm.arm.neon.vqsubs
			1, // llvm.arm.neon.vqsubu
			1, // llvm.arm.neon.vraddhn
			1, // llvm.arm.neon.vrecpe
			1, // llvm.arm.neon.vrecps
			1, // llvm.arm.neon.vrhadds
			1, // llvm.arm.neon.vrhaddu
			1, // llvm.arm.neon.vrinta
			1, // llvm.arm.neon.vrintm
			1, // llvm.arm.neon.vrintn
			1, // llvm.arm.neon.vrintp
			1, // llvm.arm.neon.vrintx
			1, // llvm.arm.neon.vrintz
			1, // llvm.arm.neon.vrshiftn
			1, // llvm.arm.neon.vrshifts
			1, // llvm.arm.neon.vrshiftu
			1, // llvm.arm.neon.vrsqrte
			1, // llvm.arm.neon.vrsqrts
			1, // llvm.arm.neon.vrsubhn
			1, // llvm.arm.neon.vshiftins
			1, // llvm.arm.neon.vshiftls
			1, // llvm.arm.neon.vshiftlu
			1, // llvm.arm.neon.vshiftn
			1, // llvm.arm.neon.vshifts
			1, // llvm.arm.neon.vshiftu
			3, // llvm.arm.neon.vst1
			3, // llvm.arm.neon.vst2
			3, // llvm.arm.neon.vst2lane
			3, // llvm.arm.neon.vst3
			3, // llvm.arm.neon.vst3lane
			3, // llvm.arm.neon.vst4
			3, // llvm.arm.neon.vst4lane
			1, // llvm.arm.neon.vtbl1
			1, // llvm.arm.neon.vtbl2
			1, // llvm.arm.neon.vtbl3
			1, // llvm.arm.neon.vtbl4
			1, // llvm.arm.neon.vtbx1
			1, // llvm.arm.neon.vtbx2
			1, // llvm.arm.neon.vtbx3
			1, // llvm.arm.neon.vtbx4
			1, // llvm.arm.qadd
			1, // llvm.arm.qsub
			3, // llvm.arm.set.fpscr
			3, // llvm.arm.sevl
			1, // llvm.arm.ssat
			3, // llvm.arm.strex
			3, // llvm.arm.strexd
			1, // llvm.arm.thread.pointer
			1, // llvm.arm.usat
			1, // llvm.arm.vcvtr
			1, // llvm.arm.vcvtru
			1, // llvm.bswap
			2, // llvm.ceil
			1, // llvm.convert.from.fp16
			1, // llvm.convert.to.fp16
			3, // llvm.convertff
			3, // llvm.convertfsi
			3, // llvm.convertfui
			3, // llvm.convertsif
			3, // llvm.convertss
			3, // llvm.convertsu
			3, // llvm.convertuif
			3, // llvm.convertus
			3, // llvm.convertuu
			2, // llvm.copysign
			2, // llvm.cos
			1, // llvm.ctlz
			1, // llvm.ctpop
			1, // llvm.cttz
			3, // llvm.cuda.syncthreads
			1, // llvm.dbg.declare
			1, // llvm.dbg.value
			3, // llvm.debugtrap
			1, // llvm.donothing
			3, // llvm.eh.dwarf.cfa
			3, // llvm.eh.return.i32
			3, // llvm.eh.return.i64
			1, // llvm.eh.sjlj.callsite
			3, // llvm.eh.sjlj.functioncontext
			4, // llvm.eh.sjlj.longjmp
			1, // llvm.eh.sjlj.lsda
			3, // llvm.eh.sjlj.setjmp
			1, // llvm.eh.typeid.for
			3, // llvm.eh.unwind.init
			2, // llvm.exp
			2, // llvm.exp2
			1, // llvm.expect
			3, // llvm.experimental.patchpoint.i64
			3, // llvm.experimental.patchpoint.void
			3, // llvm.experimental.stackmap
			2, // llvm.fabs
			2, // llvm.floor
			3, // llvm.flt.rounds
			1, // llvm.fma
			1, // llvm.fmuladd
			1, // llvm.frameaddress
			2, // llvm.gcread
			3, // llvm.gcroot
			5, // llvm.gcwrite
			1, // llvm.hexagon.A2.abs
			1, // llvm.hexagon.A2.absp
			1, // llvm.hexagon.A2.abssat
			1, // llvm.hexagon.A2.add
			1, // llvm.hexagon.A2.addh.h16.hh
			1, // llvm.hexagon.A2.addh.h16.hl
			1, // llvm.hexagon.A2.addh.h16.lh
			1, // llvm.hexagon.A2.addh.h16.ll
			1, // llvm.hexagon.A2.addh.h16.sat.hh
			1, // llvm.hexagon.A2.addh.h16.sat.hl
			1, // llvm.hexagon.A2.addh.h16.sat.lh
			1, // llvm.hexagon.A2.addh.h16.sat.ll
			1, // llvm.hexagon.A2.addh.l16.hl
			1, // llvm.hexagon.A2.addh.l16.ll
			1, // llvm.hexagon.A2.addh.l16.sat.hl
			1, // llvm.hexagon.A2.addh.l16.sat.ll
			1, // llvm.hexagon.A2.addi
			1, // llvm.hexagon.A2.addp
			1, // llvm.hexagon.A2.addpsat
			1, // llvm.hexagon.A2.addsat
			1, // llvm.hexagon.A2.addsp
			1, // llvm.hexagon.A2.and
			1, // llvm.hexagon.A2.andir
			1, // llvm.hexagon.A2.andp
			1, // llvm.hexagon.A2.aslh
			1, // llvm.hexagon.A2.asrh
			1, // llvm.hexagon.A2.combine.hh
			1, // llvm.hexagon.A2.combine.hl
			1, // llvm.hexagon.A2.combine.lh
			1, // llvm.hexagon.A2.combine.ll
			1, // llvm.hexagon.A2.combineii
			1, // llvm.hexagon.A2.combinew
			1, // llvm.hexagon.A2.max
			1, // llvm.hexagon.A2.maxp
			1, // llvm.hexagon.A2.maxu
			1, // llvm.hexagon.A2.maxup
			1, // llvm.hexagon.A2.min
			1, // llvm.hexagon.A2.minp
			1, // llvm.hexagon.A2.minu
			1, // llvm.hexagon.A2.minup
			1, // llvm.hexagon.A2.neg
			1, // llvm.hexagon.A2.negp
			1, // llvm.hexagon.A2.negsat
			1, // llvm.hexagon.A2.not
			1, // llvm.hexagon.A2.notp
			1, // llvm.hexagon.A2.or
			1, // llvm.hexagon.A2.orir
			1, // llvm.hexagon.A2.orp
			1, // llvm.hexagon.A2.roundsat
			1, // llvm.hexagon.A2.sat
			1, // llvm.hexagon.A2.satb
			1, // llvm.hexagon.A2.sath
			1, // llvm.hexagon.A2.satub
			1, // llvm.hexagon.A2.satuh
			1, // llvm.hexagon.A2.sub
			1, // llvm.hexagon.A2.subh.h16.hh
			1, // llvm.hexagon.A2.subh.h16.hl
			1, // llvm.hexagon.A2.subh.h16.lh
			1, // llvm.hexagon.A2.subh.h16.ll
			1, // llvm.hexagon.A2.subh.h16.sat.hh
			1, // llvm.hexagon.A2.subh.h16.sat.hl
			1, // llvm.hexagon.A2.subh.h16.sat.lh
			1, // llvm.hexagon.A2.subh.h16.sat.ll
			1, // llvm.hexagon.A2.subh.l16.hl
			1, // llvm.hexagon.A2.subh.l16.ll
			1, // llvm.hexagon.A2.subh.l16.sat.hl
			1, // llvm.hexagon.A2.subh.l16.sat.ll
			1, // llvm.hexagon.A2.subp
			1, // llvm.hexagon.A2.subri
			1, // llvm.hexagon.A2.subsat
			1, // llvm.hexagon.A2.svaddh
			1, // llvm.hexagon.A2.svaddhs
			1, // llvm.hexagon.A2.svadduhs
			1, // llvm.hexagon.A2.svavgh
			1, // llvm.hexagon.A2.svavghs
			1, // llvm.hexagon.A2.svnavgh
			1, // llvm.hexagon.A2.svsubh
			1, // llvm.hexagon.A2.svsubhs
			1, // llvm.hexagon.A2.svsubuhs
			1, // llvm.hexagon.A2.swiz
			1, // llvm.hexagon.A2.sxtb
			1, // llvm.hexagon.A2.sxth
			1, // llvm.hexagon.A2.sxtw
			1, // llvm.hexagon.A2.tfr
			1, // llvm.hexagon.A2.tfrih
			1, // llvm.hexagon.A2.tfril
			1, // llvm.hexagon.A2.tfrp
			1, // llvm.hexagon.A2.tfrpi
			1, // llvm.hexagon.A2.tfrsi
			1, // llvm.hexagon.A2.vabsh
			1, // llvm.hexagon.A2.vabshsat
			1, // llvm.hexagon.A2.vabsw
			1, // llvm.hexagon.A2.vabswsat
			1, // llvm.hexagon.A2.vaddb.map
			1, // llvm.hexagon.A2.vaddh
			1, // llvm.hexagon.A2.vaddhs
			1, // llvm.hexagon.A2.vaddub
			1, // llvm.hexagon.A2.vaddubs
			1, // llvm.hexagon.A2.vadduhs
			1, // llvm.hexagon.A2.vaddw
			1, // llvm.hexagon.A2.vaddws
			1, // llvm.hexagon.A2.vavgh
			1, // llvm.hexagon.A2.vavghcr
			1, // llvm.hexagon.A2.vavghr
			1, // llvm.hexagon.A2.vavgub
			1, // llvm.hexagon.A2.vavgubr
			1, // llvm.hexagon.A2.vavguh
			1, // llvm.hexagon.A2.vavguhr
			1, // llvm.hexagon.A2.vavguw
			1, // llvm.hexagon.A2.vavguwr
			1, // llvm.hexagon.A2.vavgw
			1, // llvm.hexagon.A2.vavgwcr
			1, // llvm.hexagon.A2.vavgwr
			1, // llvm.hexagon.A2.vcmpbeq
			1, // llvm.hexagon.A2.vcmpbgtu
			1, // llvm.hexagon.A2.vcmpheq
			1, // llvm.hexagon.A2.vcmphgt
			1, // llvm.hexagon.A2.vcmphgtu
			1, // llvm.hexagon.A2.vcmpweq
			1, // llvm.hexagon.A2.vcmpwgt
			1, // llvm.hexagon.A2.vcmpwgtu
			1, // llvm.hexagon.A2.vconj
			1, // llvm.hexagon.A2.vmaxb
			1, // llvm.hexagon.A2.vmaxh
			1, // llvm.hexagon.A2.vmaxub
			1, // llvm.hexagon.A2.vmaxuh
			1, // llvm.hexagon.A2.vmaxuw
			1, // llvm.hexagon.A2.vmaxw
			1, // llvm.hexagon.A2.vminb
			1, // llvm.hexagon.A2.vminh
			1, // llvm.hexagon.A2.vminub
			1, // llvm.hexagon.A2.vminuh
			1, // llvm.hexagon.A2.vminuw
			1, // llvm.hexagon.A2.vminw
			1, // llvm.hexagon.A2.vnavgh
			1, // llvm.hexagon.A2.vnavghcr
			1, // llvm.hexagon.A2.vnavghr
			1, // llvm.hexagon.A2.vnavgw
			1, // llvm.hexagon.A2.vnavgwcr
			1, // llvm.hexagon.A2.vnavgwr
			1, // llvm.hexagon.A2.vraddub
			1, // llvm.hexagon.A2.vraddub.acc
			1, // llvm.hexagon.A2.vrsadub
			1, // llvm.hexagon.A2.vrsadub.acc
			1, // llvm.hexagon.A2.vsubb.map
			1, // llvm.hexagon.A2.vsubh
			1, // llvm.hexagon.A2.vsubhs
			1, // llvm.hexagon.A2.vsubub
			1, // llvm.hexagon.A2.vsububs
			1, // llvm.hexagon.A2.vsubuhs
			1, // llvm.hexagon.A2.vsubw
			1, // llvm.hexagon.A2.vsubws
			1, // llvm.hexagon.A2.xor
			1, // llvm.hexagon.A2.xorp
			1, // llvm.hexagon.A2.zxtb
			1, // llvm.hexagon.A2.zxth
			1, // llvm.hexagon.A4.andn
			1, // llvm.hexagon.A4.andnp
			1, // llvm.hexagon.A4.bitsplit
			1, // llvm.hexagon.A4.bitspliti
			1, // llvm.hexagon.A4.boundscheck
			1, // llvm.hexagon.A4.cmpbeq
			1, // llvm.hexagon.A4.cmpbeqi
			1, // llvm.hexagon.A4.cmpbgt
			1, // llvm.hexagon.A4.cmpbgti
			1, // llvm.hexagon.A4.cmpbgtu
			1, // llvm.hexagon.A4.cmpbgtui
			1, // llvm.hexagon.A4.cmpheq
			1, // llvm.hexagon.A4.cmpheqi
			1, // llvm.hexagon.A4.cmphgt
			1, // llvm.hexagon.A4.cmphgti
			1, // llvm.hexagon.A4.cmphgtu
			1, // llvm.hexagon.A4.cmphgtui
			1, // llvm.hexagon.A4.combineir
			1, // llvm.hexagon.A4.combineri
			1, // llvm.hexagon.A4.cround.ri
			1, // llvm.hexagon.A4.cround.rr
			1, // llvm.hexagon.A4.modwrapu
			1, // llvm.hexagon.A4.orn
			1, // llvm.hexagon.A4.ornp
			1, // llvm.hexagon.A4.rcmpeq
			1, // llvm.hexagon.A4.rcmpeqi
			1, // llvm.hexagon.A4.rcmpneq
			1, // llvm.hexagon.A4.rcmpneqi
			1, // llvm.hexagon.A4.round.ri
			1, // llvm.hexagon.A4.round.ri.sat
			1, // llvm.hexagon.A4.round.rr
			1, // llvm.hexagon.A4.round.rr.sat
			1, // llvm.hexagon.A4.tlbmatch
			1, // llvm.hexagon.A4.vcmpbeq.any
			1, // llvm.hexagon.A4.vcmpbeqi
			1, // llvm.hexagon.A4.vcmpbgt
			1, // llvm.hexagon.A4.vcmpbgti
			1, // llvm.hexagon.A4.vcmpbgtui
			1, // llvm.hexagon.A4.vcmpheqi
			1, // llvm.hexagon.A4.vcmphgti
			1, // llvm.hexagon.A4.vcmphgtui
			1, // llvm.hexagon.A4.vcmpweqi
			1, // llvm.hexagon.A4.vcmpwgti
			1, // llvm.hexagon.A4.vcmpwgtui
			1, // llvm.hexagon.A4.vrmaxh
			1, // llvm.hexagon.A4.vrmaxuh
			1, // llvm.hexagon.A4.vrmaxuw
			1, // llvm.hexagon.A4.vrmaxw
			1, // llvm.hexagon.A4.vrminh
			1, // llvm.hexagon.A4.vrminuh
			1, // llvm.hexagon.A4.vrminuw
			1, // llvm.hexagon.A4.vrminw
			1, // llvm.hexagon.A5.vaddhubs
			1, // llvm.hexagon.C2.all8
			1, // llvm.hexagon.C2.and
			1, // llvm.hexagon.C2.andn
			1, // llvm.hexagon.C2.any8
			1, // llvm.hexagon.C2.bitsclr
			1, // llvm.hexagon.C2.bitsclri
			1, // llvm.hexagon.C2.bitsset
			1, // llvm.hexagon.C2.cmpeq
			1, // llvm.hexagon.C2.cmpeqi
			1, // llvm.hexagon.C2.cmpeqp
			1, // llvm.hexagon.C2.cmpgei
			1, // llvm.hexagon.C2.cmpgeui
			1, // llvm.hexagon.C2.cmpgt
			1, // llvm.hexagon.C2.cmpgti
			1, // llvm.hexagon.C2.cmpgtp
			1, // llvm.hexagon.C2.cmpgtu
			1, // llvm.hexagon.C2.cmpgtui
			1, // llvm.hexagon.C2.cmpgtup
			1, // llvm.hexagon.C2.cmplt
			1, // llvm.hexagon.C2.cmpltu
			1, // llvm.hexagon.C2.mask
			1, // llvm.hexagon.C2.mux
			1, // llvm.hexagon.C2.muxii
			1, // llvm.hexagon.C2.muxir
			1, // llvm.hexagon.C2.muxri
			1, // llvm.hexagon.C2.not
			1, // llvm.hexagon.C2.or
			1, // llvm.hexagon.C2.orn
			1, // llvm.hexagon.C2.pxfer.map
			1, // llvm.hexagon.C2.tfrpr
			1, // llvm.hexagon.C2.tfrrp
			1, // llvm.hexagon.C2.vitpack
			1, // llvm.hexagon.C2.vmux
			1, // llvm.hexagon.C2.xor
			1, // llvm.hexagon.C4.and.and
			1, // llvm.hexagon.C4.and.andn
			1, // llvm.hexagon.C4.and.or
			1, // llvm.hexagon.C4.and.orn
			1, // llvm.hexagon.C4.cmplte
			1, // llvm.hexagon.C4.cmpltei
			1, // llvm.hexagon.C4.cmplteu
			1, // llvm.hexagon.C4.cmplteui
			1, // llvm.hexagon.C4.cmpneq
			1, // llvm.hexagon.C4.cmpneqi
			1, // llvm.hexagon.C4.fastcorner9
			1, // llvm.hexagon.C4.fastcorner9.not
			1, // llvm.hexagon.C4.nbitsclr
			1, // llvm.hexagon.C4.nbitsclri
			1, // llvm.hexagon.C4.nbitsset
			1, // llvm.hexagon.C4.or.and
			1, // llvm.hexagon.C4.or.andn
			1, // llvm.hexagon.C4.or.or
			1, // llvm.hexagon.C4.or.orn
			1, // llvm.hexagon.F2.conv.d2df
			1, // llvm.hexagon.F2.conv.d2sf
			1, // llvm.hexagon.F2.conv.df2d
			1, // llvm.hexagon.F2.conv.df2d.chop
			1, // llvm.hexagon.F2.conv.df2sf
			1, // llvm.hexagon.F2.conv.df2ud
			1, // llvm.hexagon.F2.conv.df2ud.chop
			1, // llvm.hexagon.F2.conv.df2uw
			1, // llvm.hexagon.F2.conv.df2uw.chop
			1, // llvm.hexagon.F2.conv.df2w
			1, // llvm.hexagon.F2.conv.df2w.chop
			1, // llvm.hexagon.F2.conv.sf2d
			1, // llvm.hexagon.F2.conv.sf2d.chop
			1, // llvm.hexagon.F2.conv.sf2df
			1, // llvm.hexagon.F2.conv.sf2ud
			1, // llvm.hexagon.F2.conv.sf2ud.chop
			1, // llvm.hexagon.F2.conv.sf2uw
			1, // llvm.hexagon.F2.conv.sf2uw.chop
			1, // llvm.hexagon.F2.conv.sf2w
			1, // llvm.hexagon.F2.conv.sf2w.chop
			1, // llvm.hexagon.F2.conv.ud2df
			1, // llvm.hexagon.F2.conv.ud2sf
			1, // llvm.hexagon.F2.conv.uw2df
			1, // llvm.hexagon.F2.conv.uw2sf
			1, // llvm.hexagon.F2.conv.w2df
			1, // llvm.hexagon.F2.conv.w2sf
			1, // llvm.hexagon.F2.dfadd
			1, // llvm.hexagon.F2.dfclass
			1, // llvm.hexagon.F2.dfcmpeq
			1, // llvm.hexagon.F2.dfcmpge
			1, // llvm.hexagon.F2.dfcmpgt
			1, // llvm.hexagon.F2.dfcmpuo
			1, // llvm.hexagon.F2.dffixupd
			1, // llvm.hexagon.F2.dffixupn
			1, // llvm.hexagon.F2.dffixupr
			1, // llvm.hexagon.F2.dffma
			1, // llvm.hexagon.F2.dffma.lib
			1, // llvm.hexagon.F2.dffma.sc
			1, // llvm.hexagon.F2.dffms
			1, // llvm.hexagon.F2.dffms.lib
			1, // llvm.hexagon.F2.dfimm.n
			1, // llvm.hexagon.F2.dfimm.p
			1, // llvm.hexagon.F2.dfmax
			1, // llvm.hexagon.F2.dfmin
			1, // llvm.hexagon.F2.dfmpy
			1, // llvm.hexagon.F2.dfsub
			1, // llvm.hexagon.F2.sfadd
			1, // llvm.hexagon.F2.sfclass
			1, // llvm.hexagon.F2.sfcmpeq
			1, // llvm.hexagon.F2.sfcmpge
			1, // llvm.hexagon.F2.sfcmpgt
			1, // llvm.hexagon.F2.sfcmpuo
			1, // llvm.hexagon.F2.sffixupd
			1, // llvm.hexagon.F2.sffixupn
			1, // llvm.hexagon.F2.sffixupr
			1, // llvm.hexagon.F2.sffma
			1, // llvm.hexagon.F2.sffma.lib
			1, // llvm.hexagon.F2.sffma.sc
			1, // llvm.hexagon.F2.sffms
			1, // llvm.hexagon.F2.sffms.lib
			1, // llvm.hexagon.F2.sfimm.n
			1, // llvm.hexagon.F2.sfimm.p
			1, // llvm.hexagon.F2.sfmax
			1, // llvm.hexagon.F2.sfmin
			1, // llvm.hexagon.F2.sfmpy
			1, // llvm.hexagon.F2.sfsub
			1, // llvm.hexagon.M2.acci
			1, // llvm.hexagon.M2.accii
			1, // llvm.hexagon.M2.cmaci.s0
			1, // llvm.hexagon.M2.cmacr.s0
			1, // llvm.hexagon.M2.cmacs.s0
			1, // llvm.hexagon.M2.cmacs.s1
			1, // llvm.hexagon.M2.cmacsc.s0
			1, // llvm.hexagon.M2.cmacsc.s1
			1, // llvm.hexagon.M2.cmpyi.s0
			1, // llvm.hexagon.M2.cmpyr.s0
			1, // llvm.hexagon.M2.cmpyrs.s0
			1, // llvm.hexagon.M2.cmpyrs.s1
			1, // llvm.hexagon.M2.cmpyrsc.s0
			1, // llvm.hexagon.M2.cmpyrsc.s1
			1, // llvm.hexagon.M2.cmpys.s0
			1, // llvm.hexagon.M2.cmpys.s1
			1, // llvm.hexagon.M2.cmpysc.s0
			1, // llvm.hexagon.M2.cmpysc.s1
			1, // llvm.hexagon.M2.cnacs.s0
			1, // llvm.hexagon.M2.cnacs.s1
			1, // llvm.hexagon.M2.cnacsc.s0
			1, // llvm.hexagon.M2.cnacsc.s1
			1, // llvm.hexagon.M2.dpmpyss.acc.s0
			1, // llvm.hexagon.M2.dpmpyss.nac.s0
			1, // llvm.hexagon.M2.dpmpyss.rnd.s0
			1, // llvm.hexagon.M2.dpmpyss.s0
			1, // llvm.hexagon.M2.dpmpyuu.acc.s0
			1, // llvm.hexagon.M2.dpmpyuu.nac.s0
			1, // llvm.hexagon.M2.dpmpyuu.s0
			1, // llvm.hexagon.M2.hmmpyh.rs1
			1, // llvm.hexagon.M2.hmmpyh.s1
			1, // llvm.hexagon.M2.hmmpyl.rs1
			1, // llvm.hexagon.M2.hmmpyl.s1
			1, // llvm.hexagon.M2.maci
			1, // llvm.hexagon.M2.macsin
			1, // llvm.hexagon.M2.macsip
			1, // llvm.hexagon.M2.mmachs.rs0
			1, // llvm.hexagon.M2.mmachs.rs1
			1, // llvm.hexagon.M2.mmachs.s0
			1, // llvm.hexagon.M2.mmachs.s1
			1, // llvm.hexagon.M2.mmacls.rs0
			1, // llvm.hexagon.M2.mmacls.rs1
			1, // llvm.hexagon.M2.mmacls.s0
			1, // llvm.hexagon.M2.mmacls.s1
			1, // llvm.hexagon.M2.mmacuhs.rs0
			1, // llvm.hexagon.M2.mmacuhs.rs1
			1, // llvm.hexagon.M2.mmacuhs.s0
			1, // llvm.hexagon.M2.mmacuhs.s1
			1, // llvm.hexagon.M2.mmaculs.rs0
			1, // llvm.hexagon.M2.mmaculs.rs1
			1, // llvm.hexagon.M2.mmaculs.s0
			1, // llvm.hexagon.M2.mmaculs.s1
			1, // llvm.hexagon.M2.mmpyh.rs0
			1, // llvm.hexagon.M2.mmpyh.rs1
			1, // llvm.hexagon.M2.mmpyh.s0
			1, // llvm.hexagon.M2.mmpyh.s1
			1, // llvm.hexagon.M2.mmpyl.rs0
			1, // llvm.hexagon.M2.mmpyl.rs1
			1, // llvm.hexagon.M2.mmpyl.s0
			1, // llvm.hexagon.M2.mmpyl.s1
			1, // llvm.hexagon.M2.mmpyuh.rs0
			1, // llvm.hexagon.M2.mmpyuh.rs1
			1, // llvm.hexagon.M2.mmpyuh.s0
			1, // llvm.hexagon.M2.mmpyuh.s1
			1, // llvm.hexagon.M2.mmpyul.rs0
			1, // llvm.hexagon.M2.mmpyul.rs1
			1, // llvm.hexagon.M2.mmpyul.s0
			1, // llvm.hexagon.M2.mmpyul.s1
			1, // llvm.hexagon.M2.mpy.acc.hh.s0
			1, // llvm.hexagon.M2.mpy.acc.hh.s1
			1, // llvm.hexagon.M2.mpy.acc.hl.s0
			1, // llvm.hexagon.M2.mpy.acc.hl.s1
			1, // llvm.hexagon.M2.mpy.acc.lh.s0
			1, // llvm.hexagon.M2.mpy.acc.lh.s1
			1, // llvm.hexagon.M2.mpy.acc.ll.s0
			1, // llvm.hexagon.M2.mpy.acc.ll.s1
			1, // llvm.hexagon.M2.mpy.acc.sat.hh.s0
			1, // llvm.hexagon.M2.mpy.acc.sat.hh.s1
			1, // llvm.hexagon.M2.mpy.acc.sat.hl.s0
			1, // llvm.hexagon.M2.mpy.acc.sat.hl.s1
			1, // llvm.hexagon.M2.mpy.acc.sat.lh.s0
			1, // llvm.hexagon.M2.mpy.acc.sat.lh.s1
			1, // llvm.hexagon.M2.mpy.acc.sat.ll.s0
			1, // llvm.hexagon.M2.mpy.acc.sat.ll.s1
			1, // llvm.hexagon.M2.mpy.hh.s0
			1, // llvm.hexagon.M2.mpy.hh.s1
			1, // llvm.hexagon.M2.mpy.hl.s0
			1, // llvm.hexagon.M2.mpy.hl.s1
			1, // llvm.hexagon.M2.mpy.lh.s0
			1, // llvm.hexagon.M2.mpy.lh.s1
			1, // llvm.hexagon.M2.mpy.ll.s0
			1, // llvm.hexagon.M2.mpy.ll.s1
			1, // llvm.hexagon.M2.mpy.nac.hh.s0
			1, // llvm.hexagon.M2.mpy.nac.hh.s1
			1, // llvm.hexagon.M2.mpy.nac.hl.s0
			1, // llvm.hexagon.M2.mpy.nac.hl.s1
			1, // llvm.hexagon.M2.mpy.nac.lh.s0
			1, // llvm.hexagon.M2.mpy.nac.lh.s1
			1, // llvm.hexagon.M2.mpy.nac.ll.s0
			1, // llvm.hexagon.M2.mpy.nac.ll.s1
			1, // llvm.hexagon.M2.mpy.nac.sat.hh.s0
			1, // llvm.hexagon.M2.mpy.nac.sat.hh.s1
			1, // llvm.hexagon.M2.mpy.nac.sat.hl.s0
			1, // llvm.hexagon.M2.mpy.nac.sat.hl.s1
			1, // llvm.hexagon.M2.mpy.nac.sat.lh.s0
			1, // llvm.hexagon.M2.mpy.nac.sat.lh.s1
			1, // llvm.hexagon.M2.mpy.nac.sat.ll.s0
			1, // llvm.hexagon.M2.mpy.nac.sat.ll.s1
			1, // llvm.hexagon.M2.mpy.rnd.hh.s0
			1, // llvm.hexagon.M2.mpy.rnd.hh.s1
			1, // llvm.hexagon.M2.mpy.rnd.hl.s0
			1, // llvm.hexagon.M2.mpy.rnd.hl.s1
			1, // llvm.hexagon.M2.mpy.rnd.lh.s0
			1, // llvm.hexagon.M2.mpy.rnd.lh.s1
			1, // llvm.hexagon.M2.mpy.rnd.ll.s0
			1, // llvm.hexagon.M2.mpy.rnd.ll.s1
			1, // llvm.hexagon.M2.mpy.sat.hh.s0
			1, // llvm.hexagon.M2.mpy.sat.hh.s1
			1, // llvm.hexagon.M2.mpy.sat.hl.s0
			1, // llvm.hexagon.M2.mpy.sat.hl.s1
			1, // llvm.hexagon.M2.mpy.sat.lh.s0
			1, // llvm.hexagon.M2.mpy.sat.lh.s1
			1, // llvm.hexagon.M2.mpy.sat.ll.s0
			1, // llvm.hexagon.M2.mpy.sat.ll.s1
			1, // llvm.hexagon.M2.mpy.sat.rnd.hh.s0
			1, // llvm.hexagon.M2.mpy.sat.rnd.hh.s1
			1, // llvm.hexagon.M2.mpy.sat.rnd.hl.s0
			1, // llvm.hexagon.M2.mpy.sat.rnd.hl.s1
			1, // llvm.hexagon.M2.mpy.sat.rnd.lh.s0
			1, // llvm.hexagon.M2.mpy.sat.rnd.lh.s1
			1, // llvm.hexagon.M2.mpy.sat.rnd.ll.s0
			1, // llvm.hexagon.M2.mpy.sat.rnd.ll.s1
			1, // llvm.hexagon.M2.mpy.up
			1, // llvm.hexagon.M2.mpy.up.s1
			1, // llvm.hexagon.M2.mpy.up.s1.sat
			1, // llvm.hexagon.M2.mpyd.acc.hh.s0
			1, // llvm.hexagon.M2.mpyd.acc.hh.s1
			1, // llvm.hexagon.M2.mpyd.acc.hl.s0
			1, // llvm.hexagon.M2.mpyd.acc.hl.s1
			1, // llvm.hexagon.M2.mpyd.acc.lh.s0
			1, // llvm.hexagon.M2.mpyd.acc.lh.s1
			1, // llvm.hexagon.M2.mpyd.acc.ll.s0
			1, // llvm.hexagon.M2.mpyd.acc.ll.s1
			1, // llvm.hexagon.M2.mpyd.hh.s0
			1, // llvm.hexagon.M2.mpyd.hh.s1
			1, // llvm.hexagon.M2.mpyd.hl.s0
			1, // llvm.hexagon.M2.mpyd.hl.s1
			1, // llvm.hexagon.M2.mpyd.lh.s0
			1, // llvm.hexagon.M2.mpyd.lh.s1
			1, // llvm.hexagon.M2.mpyd.ll.s0
			1, // llvm.hexagon.M2.mpyd.ll.s1
			1, // llvm.hexagon.M2.mpyd.nac.hh.s0
			1, // llvm.hexagon.M2.mpyd.nac.hh.s1
			1, // llvm.hexagon.M2.mpyd.nac.hl.s0
			1, // llvm.hexagon.M2.mpyd.nac.hl.s1
			1, // llvm.hexagon.M2.mpyd.nac.lh.s0
			1, // llvm.hexagon.M2.mpyd.nac.lh.s1
			1, // llvm.hexagon.M2.mpyd.nac.ll.s0
			1, // llvm.hexagon.M2.mpyd.nac.ll.s1
			1, // llvm.hexagon.M2.mpyd.rnd.hh.s0
			1, // llvm.hexagon.M2.mpyd.rnd.hh.s1
			1, // llvm.hexagon.M2.mpyd.rnd.hl.s0
			1, // llvm.hexagon.M2.mpyd.rnd.hl.s1
			1, // llvm.hexagon.M2.mpyd.rnd.lh.s0
			1, // llvm.hexagon.M2.mpyd.rnd.lh.s1
			1, // llvm.hexagon.M2.mpyd.rnd.ll.s0
			1, // llvm.hexagon.M2.mpyd.rnd.ll.s1
			1, // llvm.hexagon.M2.mpyi
			1, // llvm.hexagon.M2.mpysmi
			1, // llvm.hexagon.M2.mpysu.up
			1, // llvm.hexagon.M2.mpyu.acc.hh.s0
			1, // llvm.hexagon.M2.mpyu.acc.hh.s1
			1, // llvm.hexagon.M2.mpyu.acc.hl.s0
			1, // llvm.hexagon.M2.mpyu.acc.hl.s1
			1, // llvm.hexagon.M2.mpyu.acc.lh.s0
			1, // llvm.hexagon.M2.mpyu.acc.lh.s1
			1, // llvm.hexagon.M2.mpyu.acc.ll.s0
			1, // llvm.hexagon.M2.mpyu.acc.ll.s1
			1, // llvm.hexagon.M2.mpyu.hh.s0
			1, // llvm.hexagon.M2.mpyu.hh.s1
			1, // llvm.hexagon.M2.mpyu.hl.s0
			1, // llvm.hexagon.M2.mpyu.hl.s1
			1, // llvm.hexagon.M2.mpyu.lh.s0
			1, // llvm.hexagon.M2.mpyu.lh.s1
			1, // llvm.hexagon.M2.mpyu.ll.s0
			1, // llvm.hexagon.M2.mpyu.ll.s1
			1, // llvm.hexagon.M2.mpyu.nac.hh.s0
			1, // llvm.hexagon.M2.mpyu.nac.hh.s1
			1, // llvm.hexagon.M2.mpyu.nac.hl.s0
			1, // llvm.hexagon.M2.mpyu.nac.hl.s1
			1, // llvm.hexagon.M2.mpyu.nac.lh.s0
			1, // llvm.hexagon.M2.mpyu.nac.lh.s1
			1, // llvm.hexagon.M2.mpyu.nac.ll.s0
			1, // llvm.hexagon.M2.mpyu.nac.ll.s1
			1, // llvm.hexagon.M2.mpyu.up
			1, // llvm.hexagon.M2.mpyud.acc.hh.s0
			1, // llvm.hexagon.M2.mpyud.acc.hh.s1
			1, // llvm.hexagon.M2.mpyud.acc.hl.s0
			1, // llvm.hexagon.M2.mpyud.acc.hl.s1
			1, // llvm.hexagon.M2.mpyud.acc.lh.s0
			1, // llvm.hexagon.M2.mpyud.acc.lh.s1
			1, // llvm.hexagon.M2.mpyud.acc.ll.s0
			1, // llvm.hexagon.M2.mpyud.acc.ll.s1
			1, // llvm.hexagon.M2.mpyud.hh.s0
			1, // llvm.hexagon.M2.mpyud.hh.s1
			1, // llvm.hexagon.M2.mpyud.hl.s0
			1, // llvm.hexagon.M2.mpyud.hl.s1
			1, // llvm.hexagon.M2.mpyud.lh.s0
			1, // llvm.hexagon.M2.mpyud.lh.s1
			1, // llvm.hexagon.M2.mpyud.ll.s0
			1, // llvm.hexagon.M2.mpyud.ll.s1
			1, // llvm.hexagon.M2.mpyud.nac.hh.s0
			1, // llvm.hexagon.M2.mpyud.nac.hh.s1
			1, // llvm.hexagon.M2.mpyud.nac.hl.s0
			1, // llvm.hexagon.M2.mpyud.nac.hl.s1
			1, // llvm.hexagon.M2.mpyud.nac.lh.s0
			1, // llvm.hexagon.M2.mpyud.nac.lh.s1
			1, // llvm.hexagon.M2.mpyud.nac.ll.s0
			1, // llvm.hexagon.M2.mpyud.nac.ll.s1
			1, // llvm.hexagon.M2.mpyui
			1, // llvm.hexagon.M2.nacci
			1, // llvm.hexagon.M2.naccii
			1, // llvm.hexagon.M2.subacc
			1, // llvm.hexagon.M2.vabsdiffh
			1, // llvm.hexagon.M2.vabsdiffw
			1, // llvm.hexagon.M2.vcmac.s0.sat.i
			1, // llvm.hexagon.M2.vcmac.s0.sat.r
			1, // llvm.hexagon.M2.vcmpy.s0.sat.i
			1, // llvm.hexagon.M2.vcmpy.s0.sat.r
			1, // llvm.hexagon.M2.vcmpy.s1.sat.i
			1, // llvm.hexagon.M2.vcmpy.s1.sat.r
			1, // llvm.hexagon.M2.vdmacs.s0
			1, // llvm.hexagon.M2.vdmacs.s1
			1, // llvm.hexagon.M2.vdmpyrs.s0
			1, // llvm.hexagon.M2.vdmpyrs.s1
			1, // llvm.hexagon.M2.vdmpys.s0
			1, // llvm.hexagon.M2.vdmpys.s1
			1, // llvm.hexagon.M2.vmac2
			1, // llvm.hexagon.M2.vmac2es
			1, // llvm.hexagon.M2.vmac2es.s0
			1, // llvm.hexagon.M2.vmac2es.s1
			1, // llvm.hexagon.M2.vmac2s.s0
			1, // llvm.hexagon.M2.vmac2s.s1
			1, // llvm.hexagon.M2.vmac2su.s0
			1, // llvm.hexagon.M2.vmac2su.s1
			1, // llvm.hexagon.M2.vmpy2es.s0
			1, // llvm.hexagon.M2.vmpy2es.s1
			1, // llvm.hexagon.M2.vmpy2s.s0
			1, // llvm.hexagon.M2.vmpy2s.s0pack
			1, // llvm.hexagon.M2.vmpy2s.s1
			1, // llvm.hexagon.M2.vmpy2s.s1pack
			1, // llvm.hexagon.M2.vmpy2su.s0
			1, // llvm.hexagon.M2.vmpy2su.s1
			1, // llvm.hexagon.M2.vraddh
			1, // llvm.hexagon.M2.vradduh
			1, // llvm.hexagon.M2.vrcmaci.s0
			1, // llvm.hexagon.M2.vrcmaci.s0c
			1, // llvm.hexagon.M2.vrcmacr.s0
			1, // llvm.hexagon.M2.vrcmacr.s0c
			1, // llvm.hexagon.M2.vrcmpyi.s0
			1, // llvm.hexagon.M2.vrcmpyi.s0c
			1, // llvm.hexagon.M2.vrcmpyr.s0
			1, // llvm.hexagon.M2.vrcmpyr.s0c
			1, // llvm.hexagon.M2.vrcmpys.acc.s1
			1, // llvm.hexagon.M2.vrcmpys.s1
			1, // llvm.hexagon.M2.vrcmpys.s1rp
			1, // llvm.hexagon.M2.vrmac.s0
			1, // llvm.hexagon.M2.vrmpy.s0
			1, // llvm.hexagon.M2.xor.xacc
			1, // llvm.hexagon.M4.and.and
			1, // llvm.hexagon.M4.and.andn
			1, // llvm.hexagon.M4.and.or
			1, // llvm.hexagon.M4.and.xor
			1, // llvm.hexagon.M4.cmpyi.wh
			1, // llvm.hexagon.M4.cmpyi.whc
			1, // llvm.hexagon.M4.cmpyr.wh
			1, // llvm.hexagon.M4.cmpyr.whc
			1, // llvm.hexagon.M4.mac.up.s1.sat
			1, // llvm.hexagon.M4.mpyri.addi
			1, // llvm.hexagon.M4.mpyri.addr
			1, // llvm.hexagon.M4.mpyri.addr.u2
			1, // llvm.hexagon.M4.mpyrr.addi
			1, // llvm.hexagon.M4.mpyrr.addr
			1, // llvm.hexagon.M4.nac.up.s1.sat
			1, // llvm.hexagon.M4.or.and
			1, // llvm.hexagon.M4.or.andn
			1, // llvm.hexagon.M4.or.or
			1, // llvm.hexagon.M4.or.xor
			1, // llvm.hexagon.M4.pmpyw
			1, // llvm.hexagon.M4.pmpyw.acc
			1, // llvm.hexagon.M4.vpmpyh
			1, // llvm.hexagon.M4.vpmpyh.acc
			1, // llvm.hexagon.M4.vrmpyeh.acc.s0
			1, // llvm.hexagon.M4.vrmpyeh.acc.s1
			1, // llvm.hexagon.M4.vrmpyeh.s0
			1, // llvm.hexagon.M4.vrmpyeh.s1
			1, // llvm.hexagon.M4.vrmpyoh.acc.s0
			1, // llvm.hexagon.M4.vrmpyoh.acc.s1
			1, // llvm.hexagon.M4.vrmpyoh.s0
			1, // llvm.hexagon.M4.vrmpyoh.s1
			1, // llvm.hexagon.M4.xor.and
			1, // llvm.hexagon.M4.xor.andn
			1, // llvm.hexagon.M4.xor.or
			1, // llvm.hexagon.M4.xor.xacc
			1, // llvm.hexagon.M5.vdmacbsu
			1, // llvm.hexagon.M5.vdmpybsu
			1, // llvm.hexagon.M5.vmacbsu
			1, // llvm.hexagon.M5.vmacbuu
			1, // llvm.hexagon.M5.vmpybsu
			1, // llvm.hexagon.M5.vmpybuu
			1, // llvm.hexagon.M5.vrmacbsu
			1, // llvm.hexagon.M5.vrmacbuu
			1, // llvm.hexagon.M5.vrmpybsu
			1, // llvm.hexagon.M5.vrmpybuu
			1, // llvm.hexagon.S2.addasl.rrri
			1, // llvm.hexagon.S2.asl.i.p
			1, // llvm.hexagon.S2.asl.i.p.acc
			1, // llvm.hexagon.S2.asl.i.p.and
			1, // llvm.hexagon.S2.asl.i.p.nac
			1, // llvm.hexagon.S2.asl.i.p.or
			1, // llvm.hexagon.S2.asl.i.p.xacc
			1, // llvm.hexagon.S2.asl.i.r
			1, // llvm.hexagon.S2.asl.i.r.acc
			1, // llvm.hexagon.S2.asl.i.r.and
			1, // llvm.hexagon.S2.asl.i.r.nac
			1, // llvm.hexagon.S2.asl.i.r.or
			1, // llvm.hexagon.S2.asl.i.r.sat
			1, // llvm.hexagon.S2.asl.i.r.xacc
			1, // llvm.hexagon.S2.asl.i.vh
			1, // llvm.hexagon.S2.asl.i.vw
			1, // llvm.hexagon.S2.asl.r.p
			1, // llvm.hexagon.S2.asl.r.p.acc
			1, // llvm.hexagon.S2.asl.r.p.and
			1, // llvm.hexagon.S2.asl.r.p.nac
			1, // llvm.hexagon.S2.asl.r.p.or
			1, // llvm.hexagon.S2.asl.r.p.xor
			1, // llvm.hexagon.S2.asl.r.r
			1, // llvm.hexagon.S2.asl.r.r.acc
			1, // llvm.hexagon.S2.asl.r.r.and
			1, // llvm.hexagon.S2.asl.r.r.nac
			1, // llvm.hexagon.S2.asl.r.r.or
			1, // llvm.hexagon.S2.asl.r.r.sat
			1, // llvm.hexagon.S2.asl.r.vh
			1, // llvm.hexagon.S2.asl.r.vw
			1, // llvm.hexagon.S2.asr.i.p
			1, // llvm.hexagon.S2.asr.i.p.acc
			1, // llvm.hexagon.S2.asr.i.p.and
			1, // llvm.hexagon.S2.asr.i.p.nac
			1, // llvm.hexagon.S2.asr.i.p.or
			1, // llvm.hexagon.S2.asr.i.p.rnd
			1, // llvm.hexagon.S2.asr.i.p.rnd.goodsyntax
			1, // llvm.hexagon.S2.asr.i.r
			1, // llvm.hexagon.S2.asr.i.r.acc
			1, // llvm.hexagon.S2.asr.i.r.and
			1, // llvm.hexagon.S2.asr.i.r.nac
			1, // llvm.hexagon.S2.asr.i.r.or
			1, // llvm.hexagon.S2.asr.i.r.rnd
			1, // llvm.hexagon.S2.asr.i.r.rnd.goodsyntax
			1, // llvm.hexagon.S2.asr.i.svw.trun
			1, // llvm.hexagon.S2.asr.i.vh
			1, // llvm.hexagon.S2.asr.i.vw
			1, // llvm.hexagon.S2.asr.r.p
			1, // llvm.hexagon.S2.asr.r.p.acc
			1, // llvm.hexagon.S2.asr.r.p.and
			1, // llvm.hexagon.S2.asr.r.p.nac
			1, // llvm.hexagon.S2.asr.r.p.or
			1, // llvm.hexagon.S2.asr.r.p.xor
			1, // llvm.hexagon.S2.asr.r.r
			1, // llvm.hexagon.S2.asr.r.r.acc
			1, // llvm.hexagon.S2.asr.r.r.and
			1, // llvm.hexagon.S2.asr.r.r.nac
			1, // llvm.hexagon.S2.asr.r.r.or
			1, // llvm.hexagon.S2.asr.r.r.sat
			1, // llvm.hexagon.S2.asr.r.svw.trun
			1, // llvm.hexagon.S2.asr.r.vh
			1, // llvm.hexagon.S2.asr.r.vw
			1, // llvm.hexagon.S2.brev
			1, // llvm.hexagon.S2.brevp
			1, // llvm.hexagon.S2.cl0
			1, // llvm.hexagon.S2.cl0p
			1, // llvm.hexagon.S2.cl1
			1, // llvm.hexagon.S2.cl1p
			1, // llvm.hexagon.S2.clb
			1, // llvm.hexagon.S2.clbnorm
			1, // llvm.hexagon.S2.clbp
			1, // llvm.hexagon.S2.clrbit.i
			1, // llvm.hexagon.S2.clrbit.r
			1, // llvm.hexagon.S2.ct0
			1, // llvm.hexagon.S2.ct0p
			1, // llvm.hexagon.S2.ct1
			1, // llvm.hexagon.S2.ct1p
			1, // llvm.hexagon.S2.deinterleave
			1, // llvm.hexagon.S2.extractu
			1, // llvm.hexagon.S2.extractu.rp
			1, // llvm.hexagon.S2.extractup
			1, // llvm.hexagon.S2.extractup.rp
			1, // llvm.hexagon.S2.insert
			1, // llvm.hexagon.S2.insert.rp
			1, // llvm.hexagon.S2.insertp
			1, // llvm.hexagon.S2.insertp.rp
			1, // llvm.hexagon.S2.interleave
			1, // llvm.hexagon.S2.lfsp
			1, // llvm.hexagon.S2.lsl.r.p
			1, // llvm.hexagon.S2.lsl.r.p.acc
			1, // llvm.hexagon.S2.lsl.r.p.and
			1, // llvm.hexagon.S2.lsl.r.p.nac
			1, // llvm.hexagon.S2.lsl.r.p.or
			1, // llvm.hexagon.S2.lsl.r.p.xor
			1, // llvm.hexagon.S2.lsl.r.r
			1, // llvm.hexagon.S2.lsl.r.r.acc
			1, // llvm.hexagon.S2.lsl.r.r.and
			1, // llvm.hexagon.S2.lsl.r.r.nac
			1, // llvm.hexagon.S2.lsl.r.r.or
			1, // llvm.hexagon.S2.lsl.r.vh
			1, // llvm.hexagon.S2.lsl.r.vw
			1, // llvm.hexagon.S2.lsr.i.p
			1, // llvm.hexagon.S2.lsr.i.p.acc
			1, // llvm.hexagon.S2.lsr.i.p.and
			1, // llvm.hexagon.S2.lsr.i.p.nac
			1, // llvm.hexagon.S2.lsr.i.p.or
			1, // llvm.hexagon.S2.lsr.i.p.xacc
			1, // llvm.hexagon.S2.lsr.i.r
			1, // llvm.hexagon.S2.lsr.i.r.acc
			1, // llvm.hexagon.S2.lsr.i.r.and
			1, // llvm.hexagon.S2.lsr.i.r.nac
			1, // llvm.hexagon.S2.lsr.i.r.or
			1, // llvm.hexagon.S2.lsr.i.r.xacc
			1, // llvm.hexagon.S2.lsr.i.vh
			1, // llvm.hexagon.S2.lsr.i.vw
			1, // llvm.hexagon.S2.lsr.r.p
			1, // llvm.hexagon.S2.lsr.r.p.acc
			1, // llvm.hexagon.S2.lsr.r.p.and
			1, // llvm.hexagon.S2.lsr.r.p.nac
			1, // llvm.hexagon.S2.lsr.r.p.or
			1, // llvm.hexagon.S2.lsr.r.p.xor
			1, // llvm.hexagon.S2.lsr.r.r
			1, // llvm.hexagon.S2.lsr.r.r.acc
			1, // llvm.hexagon.S2.lsr.r.r.and
			1, // llvm.hexagon.S2.lsr.r.r.nac
			1, // llvm.hexagon.S2.lsr.r.r.or
			1, // llvm.hexagon.S2.lsr.r.vh
			1, // llvm.hexagon.S2.lsr.r.vw
			1, // llvm.hexagon.S2.packhl
			1, // llvm.hexagon.S2.parityp
			1, // llvm.hexagon.S2.setbit.i
			1, // llvm.hexagon.S2.setbit.r
			1, // llvm.hexagon.S2.shuffeb
			1, // llvm.hexagon.S2.shuffeh
			1, // llvm.hexagon.S2.shuffob
			1, // llvm.hexagon.S2.shuffoh
			1, // llvm.hexagon.S2.svsathb
			1, // llvm.hexagon.S2.svsathub
			1, // llvm.hexagon.S2.tableidxb.goodsyntax
			1, // llvm.hexagon.S2.tableidxd.goodsyntax
			1, // llvm.hexagon.S2.tableidxh.goodsyntax
			1, // llvm.hexagon.S2.tableidxw.goodsyntax
			1, // llvm.hexagon.S2.togglebit.i
			1, // llvm.hexagon.S2.togglebit.r
			1, // llvm.hexagon.S2.tstbit.i
			1, // llvm.hexagon.S2.tstbit.r
			1, // llvm.hexagon.S2.valignib
			1, // llvm.hexagon.S2.valignrb
			1, // llvm.hexagon.S2.vcnegh
			1, // llvm.hexagon.S2.vcrotate
			1, // llvm.hexagon.S2.vrcnegh
			1, // llvm.hexagon.S2.vrndpackwh
			1, // llvm.hexagon.S2.vrndpackwhs
			1, // llvm.hexagon.S2.vsathb
			1, // llvm.hexagon.S2.vsathb.nopack
			1, // llvm.hexagon.S2.vsathub
			1, // llvm.hexagon.S2.vsathub.nopack
			1, // llvm.hexagon.S2.vsatwh
			1, // llvm.hexagon.S2.vsatwh.nopack
			1, // llvm.hexagon.S2.vsatwuh
			1, // llvm.hexagon.S2.vsatwuh.nopack
			1, // llvm.hexagon.S2.vsplatrb
			1, // llvm.hexagon.S2.vsplatrh
			1, // llvm.hexagon.S2.vspliceib
			1, // llvm.hexagon.S2.vsplicerb
			1, // llvm.hexagon.S2.vsxtbh
			1, // llvm.hexagon.S2.vsxthw
			1, // llvm.hexagon.S2.vtrunehb
			1, // llvm.hexagon.S2.vtrunewh
			1, // llvm.hexagon.S2.vtrunohb
			1, // llvm.hexagon.S2.vtrunowh
			1, // llvm.hexagon.S2.vzxtbh
			1, // llvm.hexagon.S2.vzxthw
			1, // llvm.hexagon.S4.addaddi
			1, // llvm.hexagon.S4.addi.asl.ri
			1, // llvm.hexagon.S4.addi.lsr.ri
			1, // llvm.hexagon.S4.andi.asl.ri
			1, // llvm.hexagon.S4.andi.lsr.ri
			1, // llvm.hexagon.S4.clbaddi
			1, // llvm.hexagon.S4.clbpaddi
			1, // llvm.hexagon.S4.clbpnorm
			1, // llvm.hexagon.S4.extract
			1, // llvm.hexagon.S4.extract.rp
			1, // llvm.hexagon.S4.extractp
			1, // llvm.hexagon.S4.extractp.rp
			1, // llvm.hexagon.S4.lsli
			1, // llvm.hexagon.S4.ntstbit.i
			1, // llvm.hexagon.S4.ntstbit.r
			1, // llvm.hexagon.S4.or.andi
			1, // llvm.hexagon.S4.or.andix
			1, // llvm.hexagon.S4.or.ori
			1, // llvm.hexagon.S4.ori.asl.ri
			1, // llvm.hexagon.S4.ori.lsr.ri
			1, // llvm.hexagon.S4.parity
			1, // llvm.hexagon.S4.subaddi
			1, // llvm.hexagon.S4.subi.asl.ri
			1, // llvm.hexagon.S4.subi.lsr.ri
			1, // llvm.hexagon.S4.vrcrotate
			1, // llvm.hexagon.S4.vrcrotate.acc
			1, // llvm.hexagon.S4.vxaddsubh
			1, // llvm.hexagon.S4.vxaddsubhr
			1, // llvm.hexagon.S4.vxaddsubw
			1, // llvm.hexagon.S4.vxsubaddh
			1, // llvm.hexagon.S4.vxsubaddhr
			1, // llvm.hexagon.S4.vxsubaddw
			1, // llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax
			1, // llvm.hexagon.S5.asrhub.sat
			1, // llvm.hexagon.S5.popcountp
			1, // llvm.hexagon.S5.vasrhrnd.goodsyntax
			1, // llvm.hexagon.SI.to.SXTHI.asrh
			3, // llvm.hexagon.circ.ldd
			6, // llvm.init.trampoline
			7, // llvm.invariant.end
			8, // llvm.invariant.start
			8, // llvm.lifetime.end
			8, // llvm.lifetime.start
			2, // llvm.log
			2, // llvm.log10
			2, // llvm.log2
			4, // llvm.longjmp
			9, // llvm.memcpy
			9, // llvm.memmove
			6, // llvm.memset
			3, // llvm.mips.absq.s.ph
			3, // llvm.mips.absq.s.qb
			3, // llvm.mips.absq.s.w
			1, // llvm.mips.add.a.b
			1, // llvm.mips.add.a.d
			1, // llvm.mips.add.a.h
			1, // llvm.mips.add.a.w
			3, // llvm.mips.addq.ph
			3, // llvm.mips.addq.s.ph
			3, // llvm.mips.addq.s.w
			1, // llvm.mips.addqh.ph
			1, // llvm.mips.addqh.r.ph
			1, // llvm.mips.addqh.r.w
			1, // llvm.mips.addqh.w
			1, // llvm.mips.adds.a.b
			1, // llvm.mips.adds.a.d
			1, // llvm.mips.adds.a.h
			1, // llvm.mips.adds.a.w
			1, // llvm.mips.adds.s.b
			1, // llvm.mips.adds.s.d
			1, // llvm.mips.adds.s.h
			1, // llvm.mips.adds.s.w
			1, // llvm.mips.adds.u.b
			1, // llvm.mips.adds.u.d
			1, // llvm.mips.adds.u.h
			1, // llvm.mips.adds.u.w
			3, // llvm.mips.addsc
			3, // llvm.mips.addu.ph
			3, // llvm.mips.addu.qb
			3, // llvm.mips.addu.s.ph
			3, // llvm.mips.addu.s.qb
			1, // llvm.mips.adduh.qb
			1, // llvm.mips.adduh.r.qb
			1, // llvm.mips.addv.b
			1, // llvm.mips.addv.d
			1, // llvm.mips.addv.h
			1, // llvm.mips.addv.w
			1, // llvm.mips.addvi.b
			1, // llvm.mips.addvi.d
			1, // llvm.mips.addvi.h
			1, // llvm.mips.addvi.w
			3, // llvm.mips.addwc
			1, // llvm.mips.and.v
			1, // llvm.mips.andi.b
			1, // llvm.mips.append
			1, // llvm.mips.asub.s.b
			1, // llvm.mips.asub.s.d
			1, // llvm.mips.asub.s.h
			1, // llvm.mips.asub.s.w
			1, // llvm.mips.asub.u.b
			1, // llvm.mips.asub.u.d
			1, // llvm.mips.asub.u.h
			1, // llvm.mips.asub.u.w
			1, // llvm.mips.ave.s.b
			1, // llvm.mips.ave.s.d
			1, // llvm.mips.ave.s.h
			1, // llvm.mips.ave.s.w
			1, // llvm.mips.ave.u.b
			1, // llvm.mips.ave.u.d
			1, // llvm.mips.ave.u.h
			1, // llvm.mips.ave.u.w
			1, // llvm.mips.aver.s.b
			1, // llvm.mips.aver.s.d
			1, // llvm.mips.aver.s.h
			1, // llvm.mips.aver.s.w
			1, // llvm.mips.aver.u.b
			1, // llvm.mips.aver.u.d
			1, // llvm.mips.aver.u.h
			1, // llvm.mips.aver.u.w
			1, // llvm.mips.balign
			1, // llvm.mips.bclr.b
			1, // llvm.mips.bclr.d
			1, // llvm.mips.bclr.h
			1, // llvm.mips.bclr.w
			1, // llvm.mips.bclri.b
			1, // llvm.mips.bclri.d
			1, // llvm.mips.bclri.h
			1, // llvm.mips.bclri.w
			1, // llvm.mips.binsl.b
			1, // llvm.mips.binsl.d
			1, // llvm.mips.binsl.h
			1, // llvm.mips.binsl.w
			1, // llvm.mips.binsli.b
			1, // llvm.mips.binsli.d
			1, // llvm.mips.binsli.h
			1, // llvm.mips.binsli.w
			1, // llvm.mips.binsr.b
			1, // llvm.mips.binsr.d
			1, // llvm.mips.binsr.h
			1, // llvm.mips.binsr.w
			1, // llvm.mips.binsri.b
			1, // llvm.mips.binsri.d
			1, // llvm.mips.binsri.h
			1, // llvm.mips.binsri.w
			1, // llvm.mips.bitrev
			1, // llvm.mips.bmnz.v
			1, // llvm.mips.bmnzi.b
			1, // llvm.mips.bmz.v
			1, // llvm.mips.bmzi.b
			1, // llvm.mips.bneg.b
			1, // llvm.mips.bneg.d
			1, // llvm.mips.bneg.h
			1, // llvm.mips.bneg.w
			1, // llvm.mips.bnegi.b
			1, // llvm.mips.bnegi.d
			1, // llvm.mips.bnegi.h
			1, // llvm.mips.bnegi.w
			1, // llvm.mips.bnz.b
			1, // llvm.mips.bnz.d
			1, // llvm.mips.bnz.h
			1, // llvm.mips.bnz.v
			1, // llvm.mips.bnz.w
			2, // llvm.mips.bposge32
			1, // llvm.mips.bsel.v
			1, // llvm.mips.bseli.b
			1, // llvm.mips.bset.b
			1, // llvm.mips.bset.d
			1, // llvm.mips.bset.h
			1, // llvm.mips.bset.w
			1, // llvm.mips.bseti.b
			1, // llvm.mips.bseti.d
			1, // llvm.mips.bseti.h
			1, // llvm.mips.bseti.w
			1, // llvm.mips.bz.b
			1, // llvm.mips.bz.d
			1, // llvm.mips.bz.h
			1, // llvm.mips.bz.v
			1, // llvm.mips.bz.w
			1, // llvm.mips.ceq.b
			1, // llvm.mips.ceq.d
			1, // llvm.mips.ceq.h
			1, // llvm.mips.ceq.w
			1, // llvm.mips.ceqi.b
			1, // llvm.mips.ceqi.d
			1, // llvm.mips.ceqi.h
			1, // llvm.mips.ceqi.w
			3, // llvm.mips.cfcmsa
			1, // llvm.mips.cle.s.b
			1, // llvm.mips.cle.s.d
			1, // llvm.mips.cle.s.h
			1, // llvm.mips.cle.s.w
			1, // llvm.mips.cle.u.b
			1, // llvm.mips.cle.u.d
			1, // llvm.mips.cle.u.h
			1, // llvm.mips.cle.u.w
			1, // llvm.mips.clei.s.b
			1, // llvm.mips.clei.s.d
			1, // llvm.mips.clei.s.h
			1, // llvm.mips.clei.s.w
			1, // llvm.mips.clei.u.b
			1, // llvm.mips.clei.u.d
			1, // llvm.mips.clei.u.h
			1, // llvm.mips.clei.u.w
			1, // llvm.mips.clt.s.b
			1, // llvm.mips.clt.s.d
			1, // llvm.mips.clt.s.h
			1, // llvm.mips.clt.s.w
			1, // llvm.mips.clt.u.b
			1, // llvm.mips.clt.u.d
			1, // llvm.mips.clt.u.h
			1, // llvm.mips.clt.u.w
			1, // llvm.mips.clti.s.b
			1, // llvm.mips.clti.s.d
			1, // llvm.mips.clti.s.h
			1, // llvm.mips.clti.s.w
			1, // llvm.mips.clti.u.b
			1, // llvm.mips.clti.u.d
			1, // llvm.mips.clti.u.h
			1, // llvm.mips.clti.u.w
			3, // llvm.mips.cmp.eq.ph
			3, // llvm.mips.cmp.le.ph
			3, // llvm.mips.cmp.lt.ph
			3, // llvm.mips.cmpgdu.eq.qb
			3, // llvm.mips.cmpgdu.le.qb
			3, // llvm.mips.cmpgdu.lt.qb
			3, // llvm.mips.cmpgu.eq.qb
			3, // llvm.mips.cmpgu.le.qb
			3, // llvm.mips.cmpgu.lt.qb
			3, // llvm.mips.cmpu.eq.qb
			3, // llvm.mips.cmpu.le.qb
			3, // llvm.mips.cmpu.lt.qb
			1, // llvm.mips.copy.s.b
			1, // llvm.mips.copy.s.d
			1, // llvm.mips.copy.s.h
			1, // llvm.mips.copy.s.w
			1, // llvm.mips.copy.u.b
			1, // llvm.mips.copy.u.d
			1, // llvm.mips.copy.u.h
			1, // llvm.mips.copy.u.w
			3, // llvm.mips.ctcmsa
			1, // llvm.mips.div.s.b
			1, // llvm.mips.div.s.d
			1, // llvm.mips.div.s.h
			1, // llvm.mips.div.s.w
			1, // llvm.mips.div.u.b
			1, // llvm.mips.div.u.d
			1, // llvm.mips.div.u.h
			1, // llvm.mips.div.u.w
			1, // llvm.mips.dotp.s.d
			1, // llvm.mips.dotp.s.h
			1, // llvm.mips.dotp.s.w
			1, // llvm.mips.dotp.u.d
			1, // llvm.mips.dotp.u.h
			1, // llvm.mips.dotp.u.w
			1, // llvm.mips.dpa.w.ph
			1, // llvm.mips.dpadd.s.d
			1, // llvm.mips.dpadd.s.h
			1, // llvm.mips.dpadd.s.w
			1, // llvm.mips.dpadd.u.d
			1, // llvm.mips.dpadd.u.h
			1, // llvm.mips.dpadd.u.w
			3, // llvm.mips.dpaq.s.w.ph
			3, // llvm.mips.dpaq.sa.l.w
			3, // llvm.mips.dpaqx.s.w.ph
			3, // llvm.mips.dpaqx.sa.w.ph
			1, // llvm.mips.dpau.h.qbl
			1, // llvm.mips.dpau.h.qbr
			1, // llvm.mips.dpax.w.ph
			1, // llvm.mips.dps.w.ph
			3, // llvm.mips.dpsq.s.w.ph
			3, // llvm.mips.dpsq.sa.l.w
			3, // llvm.mips.dpsqx.s.w.ph
			3, // llvm.mips.dpsqx.sa.w.ph
			1, // llvm.mips.dpsu.h.qbl
			1, // llvm.mips.dpsu.h.qbr
			1, // llvm.mips.dpsub.s.d
			1, // llvm.mips.dpsub.s.h
			1, // llvm.mips.dpsub.s.w
			1, // llvm.mips.dpsub.u.d
			1, // llvm.mips.dpsub.u.h
			1, // llvm.mips.dpsub.u.w
			1, // llvm.mips.dpsx.w.ph
			3, // llvm.mips.extp
			3, // llvm.mips.extpdp
			3, // llvm.mips.extr.r.w
			3, // llvm.mips.extr.rs.w
			3, // llvm.mips.extr.s.h
			3, // llvm.mips.extr.w
			1, // llvm.mips.fadd.d
			1, // llvm.mips.fadd.w
			1, // llvm.mips.fcaf.d
			1, // llvm.mips.fcaf.w
			1, // llvm.mips.fceq.d
			1, // llvm.mips.fceq.w
			1, // llvm.mips.fclass.d
			1, // llvm.mips.fclass.w
			1, // llvm.mips.fcle.d
			1, // llvm.mips.fcle.w
			1, // llvm.mips.fclt.d
			1, // llvm.mips.fclt.w
			1, // llvm.mips.fcne.d
			1, // llvm.mips.fcne.w
			1, // llvm.mips.fcor.d
			1, // llvm.mips.fcor.w
			1, // llvm.mips.fcueq.d
			1, // llvm.mips.fcueq.w
			1, // llvm.mips.fcule.d
			1, // llvm.mips.fcule.w
			1, // llvm.mips.fcult.d
			1, // llvm.mips.fcult.w
			1, // llvm.mips.fcun.d
			1, // llvm.mips.fcun.w
			1, // llvm.mips.fcune.d
			1, // llvm.mips.fcune.w
			1, // llvm.mips.fdiv.d
			1, // llvm.mips.fdiv.w
			1, // llvm.mips.fexdo.h
			1, // llvm.mips.fexdo.w
			1, // llvm.mips.fexp2.d
			1, // llvm.mips.fexp2.w
			1, // llvm.mips.fexupl.d
			1, // llvm.mips.fexupl.w
			1, // llvm.mips.fexupr.d
			1, // llvm.mips.fexupr.w
			1, // llvm.mips.ffint.s.d
			1, // llvm.mips.ffint.s.w
			1, // llvm.mips.ffint.u.d
			1, // llvm.mips.ffint.u.w
			1, // llvm.mips.ffql.d
			1, // llvm.mips.ffql.w
			1, // llvm.mips.ffqr.d
			1, // llvm.mips.ffqr.w
			1, // llvm.mips.fill.b
			1, // llvm.mips.fill.d
			1, // llvm.mips.fill.h
			1, // llvm.mips.fill.w
			1, // llvm.mips.flog2.d
			1, // llvm.mips.flog2.w
			1, // llvm.mips.fmadd.d
			1, // llvm.mips.fmadd.w
			1, // llvm.mips.fmax.a.d
			1, // llvm.mips.fmax.a.w
			1, // llvm.mips.fmax.d
			1, // llvm.mips.fmax.w
			1, // llvm.mips.fmin.a.d
			1, // llvm.mips.fmin.a.w
			1, // llvm.mips.fmin.d
			1, // llvm.mips.fmin.w
			1, // llvm.mips.fmsub.d
			1, // llvm.mips.fmsub.w
			1, // llvm.mips.fmul.d
			1, // llvm.mips.fmul.w
			1, // llvm.mips.frcp.d
			1, // llvm.mips.frcp.w
			1, // llvm.mips.frint.d
			1, // llvm.mips.frint.w
			1, // llvm.mips.frsqrt.d
			1, // llvm.mips.frsqrt.w
			1, // llvm.mips.fsaf.d
			1, // llvm.mips.fsaf.w
			1, // llvm.mips.fseq.d
			1, // llvm.mips.fseq.w
			1, // llvm.mips.fsle.d
			1, // llvm.mips.fsle.w
			1, // llvm.mips.fslt.d
			1, // llvm.mips.fslt.w
			1, // llvm.mips.fsne.d
			1, // llvm.mips.fsne.w
			1, // llvm.mips.fsor.d
			1, // llvm.mips.fsor.w
			1, // llvm.mips.fsqrt.d
			1, // llvm.mips.fsqrt.w
			1, // llvm.mips.fsub.d
			1, // llvm.mips.fsub.w
			1, // llvm.mips.fsueq.d
			1, // llvm.mips.fsueq.w
			1, // llvm.mips.fsule.d
			1, // llvm.mips.fsule.w
			1, // llvm.mips.fsult.d
			1, // llvm.mips.fsult.w
			1, // llvm.mips.fsun.d
			1, // llvm.mips.fsun.w
			1, // llvm.mips.fsune.d
			1, // llvm.mips.fsune.w
			1, // llvm.mips.ftint.s.d
			1, // llvm.mips.ftint.s.w
			1, // llvm.mips.ftint.u.d
			1, // llvm.mips.ftint.u.w
			1, // llvm.mips.ftq.h
			1, // llvm.mips.ftq.w
			1, // llvm.mips.ftrunc.s.d
			1, // llvm.mips.ftrunc.s.w
			1, // llvm.mips.ftrunc.u.d
			1, // llvm.mips.ftrunc.u.w
			1, // llvm.mips.hadd.s.d
			1, // llvm.mips.hadd.s.h
			1, // llvm.mips.hadd.s.w
			1, // llvm.mips.hadd.u.d
			1, // llvm.mips.hadd.u.h
			1, // llvm.mips.hadd.u.w
			1, // llvm.mips.hsub.s.d
			1, // llvm.mips.hsub.s.h
			1, // llvm.mips.hsub.s.w
			1, // llvm.mips.hsub.u.d
			1, // llvm.mips.hsub.u.h
			1, // llvm.mips.hsub.u.w
			1, // llvm.mips.ilvev.b
			1, // llvm.mips.ilvev.d
			1, // llvm.mips.ilvev.h
			1, // llvm.mips.ilvev.w
			1, // llvm.mips.ilvl.b
			1, // llvm.mips.ilvl.d
			1, // llvm.mips.ilvl.h
			1, // llvm.mips.ilvl.w
			1, // llvm.mips.ilvod.b
			1, // llvm.mips.ilvod.d
			1, // llvm.mips.ilvod.h
			1, // llvm.mips.ilvod.w
			1, // llvm.mips.ilvr.b
			1, // llvm.mips.ilvr.d
			1, // llvm.mips.ilvr.h
			1, // llvm.mips.ilvr.w
			1, // llvm.mips.insert.b
			1, // llvm.mips.insert.d
			1, // llvm.mips.insert.h
			1, // llvm.mips.insert.w
			2, // llvm.mips.insv
			1, // llvm.mips.insve.b
			1, // llvm.mips.insve.d
			1, // llvm.mips.insve.h
			1, // llvm.mips.insve.w
			2, // llvm.mips.lbux
			2, // llvm.mips.ld.b
			2, // llvm.mips.ld.d
			2, // llvm.mips.ld.h
			2, // llvm.mips.ld.w
			1, // llvm.mips.ldi.b
			1, // llvm.mips.ldi.d
			1, // llvm.mips.ldi.h
			1, // llvm.mips.ldi.w
			2, // llvm.mips.lhx
			1, // llvm.mips.lsa
			2, // llvm.mips.lwx
			1, // llvm.mips.madd
			1, // llvm.mips.madd.q.h
			1, // llvm.mips.madd.q.w
			1, // llvm.mips.maddr.q.h
			1, // llvm.mips.maddr.q.w
			1, // llvm.mips.maddu
			1, // llvm.mips.maddv.b
			1, // llvm.mips.maddv.d
			1, // llvm.mips.maddv.h
			1, // llvm.mips.maddv.w
			3, // llvm.mips.maq.s.w.phl
			3, // llvm.mips.maq.s.w.phr
			3, // llvm.mips.maq.sa.w.phl
			3, // llvm.mips.maq.sa.w.phr
			1, // llvm.mips.max.a.b
			1, // llvm.mips.max.a.d
			1, // llvm.mips.max.a.h
			1, // llvm.mips.max.a.w
			1, // llvm.mips.max.s.b
			1, // llvm.mips.max.s.d
			1, // llvm.mips.max.s.h
			1, // llvm.mips.max.s.w
			1, // llvm.mips.max.u.b
			1, // llvm.mips.max.u.d
			1, // llvm.mips.max.u.h
			1, // llvm.mips.max.u.w
			1, // llvm.mips.maxi.s.b
			1, // llvm.mips.maxi.s.d
			1, // llvm.mips.maxi.s.h
			1, // llvm.mips.maxi.s.w
			1, // llvm.mips.maxi.u.b
			1, // llvm.mips.maxi.u.d
			1, // llvm.mips.maxi.u.h
			1, // llvm.mips.maxi.u.w
			1, // llvm.mips.min.a.b
			1, // llvm.mips.min.a.d
			1, // llvm.mips.min.a.h
			1, // llvm.mips.min.a.w
			1, // llvm.mips.min.s.b
			1, // llvm.mips.min.s.d
			1, // llvm.mips.min.s.h
			1, // llvm.mips.min.s.w
			1, // llvm.mips.min.u.b
			1, // llvm.mips.min.u.d
			1, // llvm.mips.min.u.h
			1, // llvm.mips.min.u.w
			1, // llvm.mips.mini.s.b
			1, // llvm.mips.mini.s.d
			1, // llvm.mips.mini.s.h
			1, // llvm.mips.mini.s.w
			1, // llvm.mips.mini.u.b
			1, // llvm.mips.mini.u.d
			1, // llvm.mips.mini.u.h
			1, // llvm.mips.mini.u.w
			1, // llvm.mips.mod.s.b
			1, // llvm.mips.mod.s.d
			1, // llvm.mips.mod.s.h
			1, // llvm.mips.mod.s.w
			1, // llvm.mips.mod.u.b
			1, // llvm.mips.mod.u.d
			1, // llvm.mips.mod.u.h
			1, // llvm.mips.mod.u.w
			1, // llvm.mips.modsub
			1, // llvm.mips.move.v
			1, // llvm.mips.msub
			1, // llvm.mips.msub.q.h
			1, // llvm.mips.msub.q.w
			1, // llvm.mips.msubr.q.h
			1, // llvm.mips.msubr.q.w
			1, // llvm.mips.msubu
			1, // llvm.mips.msubv.b
			1, // llvm.mips.msubv.d
			1, // llvm.mips.msubv.h
			1, // llvm.mips.msubv.w
			3, // llvm.mips.mthlip
			3, // llvm.mips.mul.ph
			1, // llvm.mips.mul.q.h
			1, // llvm.mips.mul.q.w
			3, // llvm.mips.mul.s.ph
			3, // llvm.mips.muleq.s.w.phl
			3, // llvm.mips.muleq.s.w.phr
			3, // llvm.mips.muleu.s.ph.qbl
			3, // llvm.mips.muleu.s.ph.qbr
			3, // llvm.mips.mulq.rs.ph
			3, // llvm.mips.mulq.rs.w
			3, // llvm.mips.mulq.s.ph
			3, // llvm.mips.mulq.s.w
			1, // llvm.mips.mulr.q.h
			1, // llvm.mips.mulr.q.w
			1, // llvm.mips.mulsa.w.ph
			3, // llvm.mips.mulsaq.s.w.ph
			1, // llvm.mips.mult
			1, // llvm.mips.multu
			1, // llvm.mips.mulv.b
			1, // llvm.mips.mulv.d
			1, // llvm.mips.mulv.h
			1, // llvm.mips.mulv.w
			1, // llvm.mips.nloc.b
			1, // llvm.mips.nloc.d
			1, // llvm.mips.nloc.h
			1, // llvm.mips.nloc.w
			1, // llvm.mips.nlzc.b
			1, // llvm.mips.nlzc.d
			1, // llvm.mips.nlzc.h
			1, // llvm.mips.nlzc.w
			1, // llvm.mips.nor.v
			1, // llvm.mips.nori.b
			1, // llvm.mips.or.v
			1, // llvm.mips.ori.b
			1, // llvm.mips.packrl.ph
			1, // llvm.mips.pckev.b
			1, // llvm.mips.pckev.d
			1, // llvm.mips.pckev.h
			1, // llvm.mips.pckev.w
			1, // llvm.mips.pckod.b
			1, // llvm.mips.pckod.d
			1, // llvm.mips.pckod.h
			1, // llvm.mips.pckod.w
			1, // llvm.mips.pcnt.b
			1, // llvm.mips.pcnt.d
			1, // llvm.mips.pcnt.h
			1, // llvm.mips.pcnt.w
			2, // llvm.mips.pick.ph
			2, // llvm.mips.pick.qb
			1, // llvm.mips.preceq.w.phl
			1, // llvm.mips.preceq.w.phr
			1, // llvm.mips.precequ.ph.qbl
			1, // llvm.mips.precequ.ph.qbla
			1, // llvm.mips.precequ.ph.qbr
			1, // llvm.mips.precequ.ph.qbra
			1, // llvm.mips.preceu.ph.qbl
			1, // llvm.mips.preceu.ph.qbla
			1, // llvm.mips.preceu.ph.qbr
			1, // llvm.mips.preceu.ph.qbra
			3, // llvm.mips.precr.qb.ph
			1, // llvm.mips.precr.sra.ph.w
			1, // llvm.mips.precr.sra.r.ph.w
			1, // llvm.mips.precrq.ph.w
			1, // llvm.mips.precrq.qb.ph
			3, // llvm.mips.precrq.rs.ph.w
			3, // llvm.mips.precrqu.s.qb.ph
			1, // llvm.mips.prepend
			1, // llvm.mips.raddu.w.qb
			2, // llvm.mips.rddsp
			1, // llvm.mips.repl.ph
			1, // llvm.mips.repl.qb
			1, // llvm.mips.sat.s.b
			1, // llvm.mips.sat.s.d
			1, // llvm.mips.sat.s.h
			1, // llvm.mips.sat.s.w
			1, // llvm.mips.sat.u.b
			1, // llvm.mips.sat.u.d
			1, // llvm.mips.sat.u.h
			1, // llvm.mips.sat.u.w
			1, // llvm.mips.shf.b
			1, // llvm.mips.shf.h
			1, // llvm.mips.shf.w
			1, // llvm.mips.shilo
			3, // llvm.mips.shll.ph
			3, // llvm.mips.shll.qb
			3, // llvm.mips.shll.s.ph
			3, // llvm.mips.shll.s.w
			1, // llvm.mips.shra.ph
			1, // llvm.mips.shra.qb
			1, // llvm.mips.shra.r.ph
			1, // llvm.mips.shra.r.qb
			1, // llvm.mips.shra.r.w
			1, // llvm.mips.shrl.ph
			1, // llvm.mips.shrl.qb
			1, // llvm.mips.sld.b
			1, // llvm.mips.sld.d
			1, // llvm.mips.sld.h
			1, // llvm.mips.sld.w
			1, // llvm.mips.sldi.b
			1, // llvm.mips.sldi.d
			1, // llvm.mips.sldi.h
			1, // llvm.mips.sldi.w
			1, // llvm.mips.sll.b
			1, // llvm.mips.sll.d
			1, // llvm.mips.sll.h
			1, // llvm.mips.sll.w
			1, // llvm.mips.slli.b
			1, // llvm.mips.slli.d
			1, // llvm.mips.slli.h
			1, // llvm.mips.slli.w
			1, // llvm.mips.splat.b
			1, // llvm.mips.splat.d
			1, // llvm.mips.splat.h
			1, // llvm.mips.splat.w
			1, // llvm.mips.splati.b
			1, // llvm.mips.splati.d
			1, // llvm.mips.splati.h
			1, // llvm.mips.splati.w
			1, // llvm.mips.sra.b
			1, // llvm.mips.sra.d
			1, // llvm.mips.sra.h
			1, // llvm.mips.sra.w
			1, // llvm.mips.srai.b
			1, // llvm.mips.srai.d
			1, // llvm.mips.srai.h
			1, // llvm.mips.srai.w
			1, // llvm.mips.srar.b
			1, // llvm.mips.srar.d
			1, // llvm.mips.srar.h
			1, // llvm.mips.srar.w
			1, // llvm.mips.srari.b
			1, // llvm.mips.srari.d
			1, // llvm.mips.srari.h
			1, // llvm.mips.srari.w
			1, // llvm.mips.srl.b
			1, // llvm.mips.srl.d
			1, // llvm.mips.srl.h
			1, // llvm.mips.srl.w
			1, // llvm.mips.srli.b
			1, // llvm.mips.srli.d
			1, // llvm.mips.srli.h
			1, // llvm.mips.srli.w
			1, // llvm.mips.srlr.b
			1, // llvm.mips.srlr.d
			1, // llvm.mips.srlr.h
			1, // llvm.mips.srlr.w
			1, // llvm.mips.srlri.b
			1, // llvm.mips.srlri.d
			1, // llvm.mips.srlri.h
			1, // llvm.mips.srlri.w
			3, // llvm.mips.st.b
			3, // llvm.mips.st.d
			3, // llvm.mips.st.h
			3, // llvm.mips.st.w
			3, // llvm.mips.subq.ph
			3, // llvm.mips.subq.s.ph
			3, // llvm.mips.subq.s.w
			1, // llvm.mips.subqh.ph
			1, // llvm.mips.subqh.r.ph
			1, // llvm.mips.subqh.r.w
			1, // llvm.mips.subqh.w
			1, // llvm.mips.subs.s.b
			1, // llvm.mips.subs.s.d
			1, // llvm.mips.subs.s.h
			1, // llvm.mips.subs.s.w
			1, // llvm.mips.subs.u.b
			1, // llvm.mips.subs.u.d
			1, // llvm.mips.subs.u.h
			1, // llvm.mips.subs.u.w
			1, // llvm.mips.subsus.u.b
			1, // llvm.mips.subsus.u.d
			1, // llvm.mips.subsus.u.h
			1, // llvm.mips.subsus.u.w
			1, // llvm.mips.subsuu.s.b
			1, // llvm.mips.subsuu.s.d
			1, // llvm.mips.subsuu.s.h
			1, // llvm.mips.subsuu.s.w
			3, // llvm.mips.subu.ph
			3, // llvm.mips.subu.qb
			3, // llvm.mips.subu.s.ph
			3, // llvm.mips.subu.s.qb
			1, // llvm.mips.subuh.qb
			1, // llvm.mips.subuh.r.qb
			1, // llvm.mips.subv.b
			1, // llvm.mips.subv.d
			1, // llvm.mips.subv.h
			1, // llvm.mips.subv.w
			1, // llvm.mips.subvi.b
			1, // llvm.mips.subvi.d
			1, // llvm.mips.subvi.h
			1, // llvm.mips.subvi.w
			1, // llvm.mips.vshf.b
			1, // llvm.mips.vshf.d
			1, // llvm.mips.vshf.h
			1, // llvm.mips.vshf.w
			3, // llvm.mips.wrdsp
			1, // llvm.mips.xor.v
			1, // llvm.mips.xori.b
			2, // llvm.nearbyint
			1, // llvm.nvvm.abs.i
			1, // llvm.nvvm.abs.ll
			1, // llvm.nvvm.add.rm.d
			1, // llvm.nvvm.add.rm.f
			1, // llvm.nvvm.add.rm.ftz.f
			1, // llvm.nvvm.add.rn.d
			1, // llvm.nvvm.add.rn.f
			1, // llvm.nvvm.add.rn.ftz.f
			1, // llvm.nvvm.add.rp.d
			1, // llvm.nvvm.add.rp.f
			1, // llvm.nvvm.add.rp.ftz.f
			1, // llvm.nvvm.add.rz.d
			1, // llvm.nvvm.add.rz.f
			1, // llvm.nvvm.add.rz.ftz.f
			6, // llvm.nvvm.atomic.load.add.f32
			6, // llvm.nvvm.atomic.load.dec.32
			6, // llvm.nvvm.atomic.load.inc.32
			3, // llvm.nvvm.barrier0
			3, // llvm.nvvm.barrier0.and
			3, // llvm.nvvm.barrier0.or
			3, // llvm.nvvm.barrier0.popc
			1, // llvm.nvvm.bitcast.d2ll
			1, // llvm.nvvm.bitcast.f2i
			1, // llvm.nvvm.bitcast.i2f
			1, // llvm.nvvm.bitcast.ll2d
			1, // llvm.nvvm.brev32
			1, // llvm.nvvm.brev64
			1, // llvm.nvvm.ceil.d
			1, // llvm.nvvm.ceil.f
			1, // llvm.nvvm.ceil.ftz.f
			1, // llvm.nvvm.clz.i
			1, // llvm.nvvm.clz.ll
			3, // llvm.nvvm.compiler.error
			3, // llvm.nvvm.compiler.warn
			1, // llvm.nvvm.cos.approx.f
			1, // llvm.nvvm.cos.approx.ftz.f
			1, // llvm.nvvm.d2f.rm
			1, // llvm.nvvm.d2f.rm.ftz
			1, // llvm.nvvm.d2f.rn
			1, // llvm.nvvm.d2f.rn.ftz
			1, // llvm.nvvm.d2f.rp
			1, // llvm.nvvm.d2f.rp.ftz
			1, // llvm.nvvm.d2f.rz
			1, // llvm.nvvm.d2f.rz.ftz
			1, // llvm.nvvm.d2i.hi
			1, // llvm.nvvm.d2i.lo
			1, // llvm.nvvm.d2i.rm
			1, // llvm.nvvm.d2i.rn
			1, // llvm.nvvm.d2i.rp
			1, // llvm.nvvm.d2i.rz
			1, // llvm.nvvm.d2ll.rm
			1, // llvm.nvvm.d2ll.rn
			1, // llvm.nvvm.d2ll.rp
			1, // llvm.nvvm.d2ll.rz
			1, // llvm.nvvm.d2ui.rm
			1, // llvm.nvvm.d2ui.rn
			1, // llvm.nvvm.d2ui.rp
			1, // llvm.nvvm.d2ui.rz
			1, // llvm.nvvm.d2ull.rm
			1, // llvm.nvvm.d2ull.rn
			1, // llvm.nvvm.d2ull.rp
			1, // llvm.nvvm.d2ull.rz
			1, // llvm.nvvm.div.approx.f
			1, // llvm.nvvm.div.approx.ftz.f
			1, // llvm.nvvm.div.rm.d
			1, // llvm.nvvm.div.rm.f
			1, // llvm.nvvm.div.rm.ftz.f
			1, // llvm.nvvm.div.rn.d
			1, // llvm.nvvm.div.rn.f
			1, // llvm.nvvm.div.rn.ftz.f
			1, // llvm.nvvm.div.rp.d
			1, // llvm.nvvm.div.rp.f
			1, // llvm.nvvm.div.rp.ftz.f
			1, // llvm.nvvm.div.rz.d
			1, // llvm.nvvm.div.rz.f
			1, // llvm.nvvm.div.rz.ftz.f
			1, // llvm.nvvm.ex2.approx.d
			1, // llvm.nvvm.ex2.approx.f
			1, // llvm.nvvm.ex2.approx.ftz.f
			1, // llvm.nvvm.f2h.rn
			1, // llvm.nvvm.f2h.rn.ftz
			1, // llvm.nvvm.f2i.rm
			1, // llvm.nvvm.f2i.rm.ftz
			1, // llvm.nvvm.f2i.rn
			1, // llvm.nvvm.f2i.rn.ftz
			1, // llvm.nvvm.f2i.rp
			1, // llvm.nvvm.f2i.rp.ftz
			1, // llvm.nvvm.f2i.rz
			1, // llvm.nvvm.f2i.rz.ftz
			1, // llvm.nvvm.f2ll.rm
			1, // llvm.nvvm.f2ll.rm.ftz
			1, // llvm.nvvm.f2ll.rn
			1, // llvm.nvvm.f2ll.rn.ftz
			1, // llvm.nvvm.f2ll.rp
			1, // llvm.nvvm.f2ll.rp.ftz
			1, // llvm.nvvm.f2ll.rz
			1, // llvm.nvvm.f2ll.rz.ftz
			1, // llvm.nvvm.f2ui.rm
			1, // llvm.nvvm.f2ui.rm.ftz
			1, // llvm.nvvm.f2ui.rn
			1, // llvm.nvvm.f2ui.rn.ftz
			1, // llvm.nvvm.f2ui.rp
			1, // llvm.nvvm.f2ui.rp.ftz
			1, // llvm.nvvm.f2ui.rz
			1, // llvm.nvvm.f2ui.rz.ftz
			1, // llvm.nvvm.f2ull.rm
			1, // llvm.nvvm.f2ull.rm.ftz
			1, // llvm.nvvm.f2ull.rn
			1, // llvm.nvvm.f2ull.rn.ftz
			1, // llvm.nvvm.f2ull.rp
			1, // llvm.nvvm.f2ull.rp.ftz
			1, // llvm.nvvm.f2ull.rz
			1, // llvm.nvvm.f2ull.rz.ftz
			1, // llvm.nvvm.fabs.d
			1, // llvm.nvvm.fabs.f
			1, // llvm.nvvm.fabs.ftz.f
			1, // llvm.nvvm.floor.d
			1, // llvm.nvvm.floor.f
			1, // llvm.nvvm.floor.ftz.f
			1, // llvm.nvvm.fma.rm.d
			1, // llvm.nvvm.fma.rm.f
			1, // llvm.nvvm.fma.rm.ftz.f
			1, // llvm.nvvm.fma.rn.d
			1, // llvm.nvvm.fma.rn.f
			1, // llvm.nvvm.fma.rn.ftz.f
			1, // llvm.nvvm.fma.rp.d
			1, // llvm.nvvm.fma.rp.f
			1, // llvm.nvvm.fma.rp.ftz.f
			1, // llvm.nvvm.fma.rz.d
			1, // llvm.nvvm.fma.rz.f
			1, // llvm.nvvm.fma.rz.ftz.f
			1, // llvm.nvvm.fmax.d
			1, // llvm.nvvm.fmax.f
			1, // llvm.nvvm.fmax.ftz.f
			1, // llvm.nvvm.fmin.d
			1, // llvm.nvvm.fmin.f
			1, // llvm.nvvm.fmin.ftz.f
			1, // llvm.nvvm.h2f
			1, // llvm.nvvm.i2d.rm
			1, // llvm.nvvm.i2d.rn
			1, // llvm.nvvm.i2d.rp
			1, // llvm.nvvm.i2d.rz
			1, // llvm.nvvm.i2f.rm
			1, // llvm.nvvm.i2f.rn
			1, // llvm.nvvm.i2f.rp
			1, // llvm.nvvm.i2f.rz
			10, // llvm.nvvm.ldg.global.f
			10, // llvm.nvvm.ldg.global.i
			10, // llvm.nvvm.ldg.global.p
			10, // llvm.nvvm.ldu.global.f
			10, // llvm.nvvm.ldu.global.i
			10, // llvm.nvvm.ldu.global.p
			1, // llvm.nvvm.lg2.approx.d
			1, // llvm.nvvm.lg2.approx.f
			1, // llvm.nvvm.lg2.approx.ftz.f
			1, // llvm.nvvm.ll2d.rm
			1, // llvm.nvvm.ll2d.rn
			1, // llvm.nvvm.ll2d.rp
			1, // llvm.nvvm.ll2d.rz
			1, // llvm.nvvm.ll2f.rm
			1, // llvm.nvvm.ll2f.rn
			1, // llvm.nvvm.ll2f.rp
			1, // llvm.nvvm.ll2f.rz
			1, // llvm.nvvm.lohi.i2d
			1, // llvm.nvvm.max.i
			1, // llvm.nvvm.max.ll
			1, // llvm.nvvm.max.ui
			1, // llvm.nvvm.max.ull
			3, // llvm.nvvm.membar.cta
			3, // llvm.nvvm.membar.gl
			3, // llvm.nvvm.membar.sys
			1, // llvm.nvvm.min.i
			1, // llvm.nvvm.min.ll
			1, // llvm.nvvm.min.ui
			1, // llvm.nvvm.min.ull
			1, // llvm.nvvm.move.double
			1, // llvm.nvvm.move.float
			1, // llvm.nvvm.move.i16
			1, // llvm.nvvm.move.i32
			1, // llvm.nvvm.move.i64
			11, // llvm.nvvm.move.ptr
			1, // llvm.nvvm.mul24.i
			1, // llvm.nvvm.mul24.ui
			1, // llvm.nvvm.mul.rm.d
			1, // llvm.nvvm.mul.rm.f
			1, // llvm.nvvm.mul.rm.ftz.f
			1, // llvm.nvvm.mul.rn.d
			1, // llvm.nvvm.mul.rn.f
			1, // llvm.nvvm.mul.rn.ftz.f
			1, // llvm.nvvm.mul.rp.d
			1, // llvm.nvvm.mul.rp.f
			1, // llvm.nvvm.mul.rp.ftz.f
			1, // llvm.nvvm.mul.rz.d
			1, // llvm.nvvm.mul.rz.f
			1, // llvm.nvvm.mul.rz.ftz.f
			1, // llvm.nvvm.mulhi.i
			1, // llvm.nvvm.mulhi.ll
			1, // llvm.nvvm.mulhi.ui
			1, // llvm.nvvm.mulhi.ull
			1, // llvm.nvvm.popc.i
			1, // llvm.nvvm.popc.ll
			1, // llvm.nvvm.prmt
			1, // llvm.nvvm.ptr.constant.to.gen
			1, // llvm.nvvm.ptr.gen.to.constant
			1, // llvm.nvvm.ptr.gen.to.global
			1, // llvm.nvvm.ptr.gen.to.local
			1, // llvm.nvvm.ptr.gen.to.param
			1, // llvm.nvvm.ptr.gen.to.shared
			1, // llvm.nvvm.ptr.global.to.gen
			1, // llvm.nvvm.ptr.local.to.gen
			1, // llvm.nvvm.ptr.shared.to.gen
			1, // llvm.nvvm.rcp.approx.ftz.d
			1, // llvm.nvvm.rcp.rm.d
			1, // llvm.nvvm.rcp.rm.f
			1, // llvm.nvvm.rcp.rm.ftz.f
			1, // llvm.nvvm.rcp.rn.d
			1, // llvm.nvvm.rcp.rn.f
			1, // llvm.nvvm.rcp.rn.ftz.f
			1, // llvm.nvvm.rcp.rp.d
			1, // llvm.nvvm.rcp.rp.f
			1, // llvm.nvvm.rcp.rp.ftz.f
			1, // llvm.nvvm.rcp.rz.d
			1, // llvm.nvvm.rcp.rz.f
			1, // llvm.nvvm.rcp.rz.ftz.f
			1, // llvm.nvvm.read.ptx.sreg.ctaid.x
			1, // llvm.nvvm.read.ptx.sreg.ctaid.y
			1, // llvm.nvvm.read.ptx.sreg.ctaid.z
			1, // llvm.nvvm.read.ptx.sreg.nctaid.x
			1, // llvm.nvvm.read.ptx.sreg.nctaid.y
			1, // llvm.nvvm.read.ptx.sreg.nctaid.z
			1, // llvm.nvvm.read.ptx.sreg.ntid.x
			1, // llvm.nvvm.read.ptx.sreg.ntid.y
			1, // llvm.nvvm.read.ptx.sreg.ntid.z
			1, // llvm.nvvm.read.ptx.sreg.tid.x
			1, // llvm.nvvm.read.ptx.sreg.tid.y
			1, // llvm.nvvm.read.ptx.sreg.tid.z
			1, // llvm.nvvm.read.ptx.sreg.warpsize
			1, // llvm.nvvm.round.d
			1, // llvm.nvvm.round.f
			1, // llvm.nvvm.round.ftz.f
			1, // llvm.nvvm.rsqrt.approx.d
			1, // llvm.nvvm.rsqrt.approx.f
			1, // llvm.nvvm.rsqrt.approx.ftz.f
			1, // llvm.nvvm.sad.i
			1, // llvm.nvvm.sad.ui
			1, // llvm.nvvm.saturate.d
			1, // llvm.nvvm.saturate.f
			1, // llvm.nvvm.saturate.ftz.f
			1, // llvm.nvvm.sin.approx.f
			1, // llvm.nvvm.sin.approx.ftz.f
			1, // llvm.nvvm.sqrt.approx.f
			1, // llvm.nvvm.sqrt.approx.ftz.f
			1, // llvm.nvvm.sqrt.f
			1, // llvm.nvvm.sqrt.rm.d
			1, // llvm.nvvm.sqrt.rm.f
			1, // llvm.nvvm.sqrt.rm.ftz.f
			1, // llvm.nvvm.sqrt.rn.d
			1, // llvm.nvvm.sqrt.rn.f
			1, // llvm.nvvm.sqrt.rn.ftz.f
			1, // llvm.nvvm.sqrt.rp.d
			1, // llvm.nvvm.sqrt.rp.f
			1, // llvm.nvvm.sqrt.rp.ftz.f
			1, // llvm.nvvm.sqrt.rz.d
			1, // llvm.nvvm.sqrt.rz.f
			1, // llvm.nvvm.sqrt.rz.ftz.f
			1, // llvm.nvvm.trunc.d
			1, // llvm.nvvm.trunc.f
			1, // llvm.nvvm.trunc.ftz.f
			1, // llvm.nvvm.ui2d.rm
			1, // llvm.nvvm.ui2d.rn
			1, // llvm.nvvm.ui2d.rp
			1, // llvm.nvvm.ui2d.rz
			1, // llvm.nvvm.ui2f.rm
			1, // llvm.nvvm.ui2f.rn
			1, // llvm.nvvm.ui2f.rp
			1, // llvm.nvvm.ui2f.rz
			1, // llvm.nvvm.ull2d.rm
			1, // llvm.nvvm.ull2d.rn
			1, // llvm.nvvm.ull2d.rp
			1, // llvm.nvvm.ull2d.rz
			1, // llvm.nvvm.ull2f.rm
			1, // llvm.nvvm.ull2f.rn
			1, // llvm.nvvm.ull2f.rp
			1, // llvm.nvvm.ull2f.rz
			1, // llvm.objectsize
			3, // llvm.pcmarker
			2, // llvm.pow
			2, // llvm.powi
			3, // llvm.ppc.altivec.dss
			3, // llvm.ppc.altivec.dssall
			3, // llvm.ppc.altivec.dst
			3, // llvm.ppc.altivec.dstst
			3, // llvm.ppc.altivec.dststt
			3, // llvm.ppc.altivec.dstt
			2, // llvm.ppc.altivec.lvebx
			2, // llvm.ppc.altivec.lvehx
			2, // llvm.ppc.altivec.lvewx
			1, // llvm.ppc.altivec.lvsl
			1, // llvm.ppc.altivec.lvsr
			2, // llvm.ppc.altivec.lvx
			2, // llvm.ppc.altivec.lvxl
			2, // llvm.ppc.altivec.mfvscr
			3, // llvm.ppc.altivec.mtvscr
			3, // llvm.ppc.altivec.stvebx
			3, // llvm.ppc.altivec.stvehx
			3, // llvm.ppc.altivec.stvewx
			3, // llvm.ppc.altivec.stvx
			3, // llvm.ppc.altivec.stvxl
			1, // llvm.ppc.altivec.vaddcuw
			1, // llvm.ppc.altivec.vaddsbs
			1, // llvm.ppc.altivec.vaddshs
			1, // llvm.ppc.altivec.vaddsws
			1, // llvm.ppc.altivec.vaddubs
			1, // llvm.ppc.altivec.vadduhs
			1, // llvm.ppc.altivec.vadduws
			1, // llvm.ppc.altivec.vavgsb
			1, // llvm.ppc.altivec.vavgsh
			1, // llvm.ppc.altivec.vavgsw
			1, // llvm.ppc.altivec.vavgub
			1, // llvm.ppc.altivec.vavguh
			1, // llvm.ppc.altivec.vavguw
			1, // llvm.ppc.altivec.vcfsx
			1, // llvm.ppc.altivec.vcfux
			1, // llvm.ppc.altivec.vcmpbfp
			1, // llvm.ppc.altivec.vcmpbfp.p
			1, // llvm.ppc.altivec.vcmpeqfp
			1, // llvm.ppc.altivec.vcmpeqfp.p
			1, // llvm.ppc.altivec.vcmpequb
			1, // llvm.ppc.altivec.vcmpequb.p
			1, // llvm.ppc.altivec.vcmpequh
			1, // llvm.ppc.altivec.vcmpequh.p
			1, // llvm.ppc.altivec.vcmpequw
			1, // llvm.ppc.altivec.vcmpequw.p
			1, // llvm.ppc.altivec.vcmpgefp
			1, // llvm.ppc.altivec.vcmpgefp.p
			1, // llvm.ppc.altivec.vcmpgtfp
			1, // llvm.ppc.altivec.vcmpgtfp.p
			1, // llvm.ppc.altivec.vcmpgtsb
			1, // llvm.ppc.altivec.vcmpgtsb.p
			1, // llvm.ppc.altivec.vcmpgtsh
			1, // llvm.ppc.altivec.vcmpgtsh.p
			1, // llvm.ppc.altivec.vcmpgtsw
			1, // llvm.ppc.altivec.vcmpgtsw.p
			1, // llvm.ppc.altivec.vcmpgtub
			1, // llvm.ppc.altivec.vcmpgtub.p
			1, // llvm.ppc.altivec.vcmpgtuh
			1, // llvm.ppc.altivec.vcmpgtuh.p
			1, // llvm.ppc.altivec.vcmpgtuw
			1, // llvm.ppc.altivec.vcmpgtuw.p
			1, // llvm.ppc.altivec.vctsxs
			1, // llvm.ppc.altivec.vctuxs
			1, // llvm.ppc.altivec.vexptefp
			1, // llvm.ppc.altivec.vlogefp
			1, // llvm.ppc.altivec.vmaddfp
			1, // llvm.ppc.altivec.vmaxfp
			1, // llvm.ppc.altivec.vmaxsb
			1, // llvm.ppc.altivec.vmaxsh
			1, // llvm.ppc.altivec.vmaxsw
			1, // llvm.ppc.altivec.vmaxub
			1, // llvm.ppc.altivec.vmaxuh
			1, // llvm.ppc.altivec.vmaxuw
			1, // llvm.ppc.altivec.vmhaddshs
			1, // llvm.ppc.altivec.vmhraddshs
			1, // llvm.ppc.altivec.vminfp
			1, // llvm.ppc.altivec.vminsb
			1, // llvm.ppc.altivec.vminsh
			1, // llvm.ppc.altivec.vminsw
			1, // llvm.ppc.altivec.vminub
			1, // llvm.ppc.altivec.vminuh
			1, // llvm.ppc.altivec.vminuw
			1, // llvm.ppc.altivec.vmladduhm
			1, // llvm.ppc.altivec.vmsummbm
			1, // llvm.ppc.altivec.vmsumshm
			1, // llvm.ppc.altivec.vmsumshs
			1, // llvm.ppc.altivec.vmsumubm
			1, // llvm.ppc.altivec.vmsumuhm
			1, // llvm.ppc.altivec.vmsumuhs
			1, // llvm.ppc.altivec.vmulesb
			1, // llvm.ppc.altivec.vmulesh
			1, // llvm.ppc.altivec.vmuleub
			1, // llvm.ppc.altivec.vmuleuh
			1, // llvm.ppc.altivec.vmulosb
			1, // llvm.ppc.altivec.vmulosh
			1, // llvm.ppc.altivec.vmuloub
			1, // llvm.ppc.altivec.vmulouh
			1, // llvm.ppc.altivec.vnmsubfp
			1, // llvm.ppc.altivec.vperm
			1, // llvm.ppc.altivec.vpkpx
			1, // llvm.ppc.altivec.vpkshss
			1, // llvm.ppc.altivec.vpkshus
			1, // llvm.ppc.altivec.vpkswss
			1, // llvm.ppc.altivec.vpkswus
			1, // llvm.ppc.altivec.vpkuhus
			1, // llvm.ppc.altivec.vpkuwus
			1, // llvm.ppc.altivec.vrefp
			1, // llvm.ppc.altivec.vrfim
			1, // llvm.ppc.altivec.vrfin
			1, // llvm.ppc.altivec.vrfip
			1, // llvm.ppc.altivec.vrfiz
			1, // llvm.ppc.altivec.vrlb
			1, // llvm.ppc.altivec.vrlh
			1, // llvm.ppc.altivec.vrlw
			1, // llvm.ppc.altivec.vrsqrtefp
			1, // llvm.ppc.altivec.vsel
			1, // llvm.ppc.altivec.vsl
			1, // llvm.ppc.altivec.vslb
			1, // llvm.ppc.altivec.vslh
			1, // llvm.ppc.altivec.vslo
			1, // llvm.ppc.altivec.vslw
			1, // llvm.ppc.altivec.vsr
			1, // llvm.ppc.altivec.vsrab
			1, // llvm.ppc.altivec.vsrah
			1, // llvm.ppc.altivec.vsraw
			1, // llvm.ppc.altivec.vsrb
			1, // llvm.ppc.altivec.vsrh
			1, // llvm.ppc.altivec.vsro
			1, // llvm.ppc.altivec.vsrw
			1, // llvm.ppc.altivec.vsubcuw
			1, // llvm.ppc.altivec.vsubsbs
			1, // llvm.ppc.altivec.vsubshs
			1, // llvm.ppc.altivec.vsubsws
			1, // llvm.ppc.altivec.vsububs
			1, // llvm.ppc.altivec.vsubuhs
			1, // llvm.ppc.altivec.vsubuws
			1, // llvm.ppc.altivec.vsum2sws
			1, // llvm.ppc.altivec.vsum4sbs
			1, // llvm.ppc.altivec.vsum4shs
			1, // llvm.ppc.altivec.vsum4ubs
			1, // llvm.ppc.altivec.vsumsws
			1, // llvm.ppc.altivec.vupkhpx
			1, // llvm.ppc.altivec.vupkhsb
			1, // llvm.ppc.altivec.vupkhsh
			1, // llvm.ppc.altivec.vupklpx
			1, // llvm.ppc.altivec.vupklsb
			1, // llvm.ppc.altivec.vupklsh
			3, // llvm.ppc.dcba
			3, // llvm.ppc.dcbf
			3, // llvm.ppc.dcbi
			3, // llvm.ppc.dcbst
			6, // llvm.ppc.dcbt
			3, // llvm.ppc.dcbtst
			3, // llvm.ppc.dcbz
			3, // llvm.ppc.dcbzl
			3, // llvm.ppc.is.decremented.ctr.nonzero
			3, // llvm.ppc.mtctr
			3, // llvm.ppc.sync
			6, // llvm.prefetch
			3, // llvm.ptr.annotation
			3, // llvm.ptx.bar.sync
			1, // llvm.ptx.read.clock
			1, // llvm.ptx.read.clock64
			1, // llvm.ptx.read.ctaid.w
			1, // llvm.ptx.read.ctaid.x
			1, // llvm.ptx.read.ctaid.y
			1, // llvm.ptx.read.ctaid.z
			1, // llvm.ptx.read.gridid
			1, // llvm.ptx.read.laneid
			1, // llvm.ptx.read.lanemask.eq
			1, // llvm.ptx.read.lanemask.ge
			1, // llvm.ptx.read.lanemask.gt
			1, // llvm.ptx.read.lanemask.le
			1, // llvm.ptx.read.lanemask.lt
			1, // llvm.ptx.read.nctaid.w
			1, // llvm.ptx.read.nctaid.x
			1, // llvm.ptx.read.nctaid.y
			1, // llvm.ptx.read.nctaid.z
			1, // llvm.ptx.read.nsmid
			1, // llvm.ptx.read.ntid.w
			1, // llvm.ptx.read.ntid.x
			1, // llvm.ptx.read.ntid.y
			1, // llvm.ptx.read.ntid.z
			1, // llvm.ptx.read.nwarpid
			1, // llvm.ptx.read.pm0
			1, // llvm.ptx.read.pm1
			1, // llvm.ptx.read.pm2
			1, // llvm.ptx.read.pm3
			1, // llvm.ptx.read.smid
			1, // llvm.ptx.read.tid.w
			1, // llvm.ptx.read.tid.x
			1, // llvm.ptx.read.tid.y
			1, // llvm.ptx.read.tid.z
			1, // llvm.ptx.read.warpid
			1, // llvm.r600.read.global.size.x
			1, // llvm.r600.read.global.size.y
			1, // llvm.r600.read.global.size.z
			1, // llvm.r600.read.local.size.x
			1, // llvm.r600.read.local.size.y
			1, // llvm.r600.read.local.size.z
			1, // llvm.r600.read.ngroups.x
			1, // llvm.r600.read.ngroups.y
			1, // llvm.r600.read.ngroups.z
			1, // llvm.r600.read.tgid.x
			1, // llvm.r600.read.tgid.y
			1, // llvm.r600.read.tgid.z
			1, // llvm.r600.read.tidig.x
			1, // llvm.r600.read.tidig.y
			1, // llvm.r600.read.tidig.z
			3, // llvm.readcyclecounter
			1, // llvm.returnaddress
			2, // llvm.rint
			2, // llvm.round
			1, // llvm.sadd.with.overflow
			3, // llvm.setjmp
			4, // llvm.siglongjmp
			3, // llvm.sigsetjmp
			2, // llvm.sin
			1, // llvm.smul.with.overflow
			2, // llvm.sqrt
			1, // llvm.ssub.with.overflow
			3, // llvm.stackprotector
			3, // llvm.stackprotectorcheck
			3, // llvm.stackrestore
			3, // llvm.stacksave
			4, // llvm.trap
			2, // llvm.trunc
			1, // llvm.uadd.with.overflow
			1, // llvm.umul.with.overflow
			1, // llvm.usub.with.overflow
			3, // llvm.va_copy
			3, // llvm.va_end
			3, // llvm.var.annotation
			3, // llvm.va_start
			1, // llvm.x86.3dnow.pavgusb
			1, // llvm.x86.3dnow.pf2id
			1, // llvm.x86.3dnow.pfacc
			1, // llvm.x86.3dnow.pfadd
			1, // llvm.x86.3dnow.pfcmpeq
			1, // llvm.x86.3dnow.pfcmpge
			1, // llvm.x86.3dnow.pfcmpgt
			1, // llvm.x86.3dnow.pfmax
			1, // llvm.x86.3dnow.pfmin
			1, // llvm.x86.3dnow.pfmul
			1, // llvm.x86.3dnow.pfrcp
			1, // llvm.x86.3dnow.pfrcpit1
			1, // llvm.x86.3dnow.pfrcpit2
			1, // llvm.x86.3dnow.pfrsqit1
			1, // llvm.x86.3dnow.pfrsqrt
			1, // llvm.x86.3dnow.pfsub
			1, // llvm.x86.3dnow.pfsubr
			1, // llvm.x86.3dnow.pi2fd
			1, // llvm.x86.3dnow.pmulhrw
			1, // llvm.x86.3dnowa.pf2iw
			1, // llvm.x86.3dnowa.pfnacc
			1, // llvm.x86.3dnowa.pfpnacc
			1, // llvm.x86.3dnowa.pi2fw
			1, // llvm.x86.3dnowa.pswapd
			1, // llvm.x86.aesni.aesdec
			1, // llvm.x86.aesni.aesdeclast
			1, // llvm.x86.aesni.aesenc
			1, // llvm.x86.aesni.aesenclast
			1, // llvm.x86.aesni.aesimc
			1, // llvm.x86.aesni.aeskeygenassist
			2, // llvm.x86.avx2.gather.d.d
			2, // llvm.x86.avx2.gather.d.d.256
			2, // llvm.x86.avx2.gather.d.pd
			2, // llvm.x86.avx2.gather.d.pd.256
			2, // llvm.x86.avx2.gather.d.ps
			2, // llvm.x86.avx2.gather.d.ps.256
			2, // llvm.x86.avx2.gather.d.q
			2, // llvm.x86.avx2.gather.d.q.256
			2, // llvm.x86.avx2.gather.q.d
			2, // llvm.x86.avx2.gather.q.d.256
			2, // llvm.x86.avx2.gather.q.pd
			2, // llvm.x86.avx2.gather.q.pd.256
			2, // llvm.x86.avx2.gather.q.ps
			2, // llvm.x86.avx2.gather.q.ps.256
			2, // llvm.x86.avx2.gather.q.q
			2, // llvm.x86.avx2.gather.q.q.256
			2, // llvm.x86.avx2.maskload.d
			2, // llvm.x86.avx2.maskload.d.256
			2, // llvm.x86.avx2.maskload.q
			2, // llvm.x86.avx2.maskload.q.256
			3, // llvm.x86.avx2.maskstore.d
			3, // llvm.x86.avx2.maskstore.d.256
			3, // llvm.x86.avx2.maskstore.q
			3, // llvm.x86.avx2.maskstore.q.256
			2, // llvm.x86.avx2.movntdqa
			1, // llvm.x86.avx2.mpsadbw
			1, // llvm.x86.avx2.pabs.b
			1, // llvm.x86.avx2.pabs.d
			1, // llvm.x86.avx2.pabs.w
			1, // llvm.x86.avx2.packssdw
			1, // llvm.x86.avx2.packsswb
			1, // llvm.x86.avx2.packusdw
			1, // llvm.x86.avx2.packuswb
			1, // llvm.x86.avx2.padds.b
			1, // llvm.x86.avx2.padds.w
			1, // llvm.x86.avx2.paddus.b
			1, // llvm.x86.avx2.paddus.w
			1, // llvm.x86.avx2.pavg.b
			1, // llvm.x86.avx2.pavg.w
			1, // llvm.x86.avx2.pblendd.128
			1, // llvm.x86.avx2.pblendd.256
			1, // llvm.x86.avx2.pblendvb
			1, // llvm.x86.avx2.pblendw
			1, // llvm.x86.avx2.pbroadcastb.128
			1, // llvm.x86.avx2.pbroadcastb.256
			1, // llvm.x86.avx2.pbroadcastd.128
			1, // llvm.x86.avx2.pbroadcastd.256
			1, // llvm.x86.avx2.pbroadcastq.128
			1, // llvm.x86.avx2.pbroadcastq.256
			1, // llvm.x86.avx2.pbroadcastw.128
			1, // llvm.x86.avx2.pbroadcastw.256
			1, // llvm.x86.avx2.permd
			1, // llvm.x86.avx2.permps
			1, // llvm.x86.avx2.phadd.d
			1, // llvm.x86.avx2.phadd.sw
			1, // llvm.x86.avx2.phadd.w
			1, // llvm.x86.avx2.phsub.d
			1, // llvm.x86.avx2.phsub.sw
			1, // llvm.x86.avx2.phsub.w
			1, // llvm.x86.avx2.pmadd.ub.sw
			1, // llvm.x86.avx2.pmadd.wd
			1, // llvm.x86.avx2.pmaxs.b
			1, // llvm.x86.avx2.pmaxs.d
			1, // llvm.x86.avx2.pmaxs.w
			1, // llvm.x86.avx2.pmaxu.b
			1, // llvm.x86.avx2.pmaxu.d
			1, // llvm.x86.avx2.pmaxu.w
			1, // llvm.x86.avx2.pmins.b
			1, // llvm.x86.avx2.pmins.d
			1, // llvm.x86.avx2.pmins.w
			1, // llvm.x86.avx2.pminu.b
			1, // llvm.x86.avx2.pminu.d
			1, // llvm.x86.avx2.pminu.w
			1, // llvm.x86.avx2.pmovmskb
			1, // llvm.x86.avx2.pmovsxbd
			1, // llvm.x86.avx2.pmovsxbq
			1, // llvm.x86.avx2.pmovsxbw
			1, // llvm.x86.avx2.pmovsxdq
			1, // llvm.x86.avx2.pmovsxwd
			1, // llvm.x86.avx2.pmovsxwq
			1, // llvm.x86.avx2.pmovzxbd
			1, // llvm.x86.avx2.pmovzxbq
			1, // llvm.x86.avx2.pmovzxbw
			1, // llvm.x86.avx2.pmovzxdq
			1, // llvm.x86.avx2.pmovzxwd
			1, // llvm.x86.avx2.pmovzxwq
			1, // llvm.x86.avx2.pmul.dq
			1, // llvm.x86.avx2.pmul.hr.sw
			1, // llvm.x86.avx2.pmulh.w
			1, // llvm.x86.avx2.pmulhu.w
			1, // llvm.x86.avx2.pmulu.dq
			1, // llvm.x86.avx2.psad.bw
			1, // llvm.x86.avx2.pshuf.b
			1, // llvm.x86.avx2.psign.b
			1, // llvm.x86.avx2.psign.d
			1, // llvm.x86.avx2.psign.w
			1, // llvm.x86.avx2.psll.d
			1, // llvm.x86.avx2.psll.dq
			1, // llvm.x86.avx2.psll.dq.bs
			1, // llvm.x86.avx2.psll.q
			1, // llvm.x86.avx2.psll.w
			1, // llvm.x86.avx2.pslli.d
			1, // llvm.x86.avx2.pslli.q
			1, // llvm.x86.avx2.pslli.w
			1, // llvm.x86.avx2.psllv.d
			1, // llvm.x86.avx2.psllv.d.256
			1, // llvm.x86.avx2.psllv.q
			1, // llvm.x86.avx2.psllv.q.256
			1, // llvm.x86.avx2.psra.d
			1, // llvm.x86.avx2.psra.w
			1, // llvm.x86.avx2.psrai.d
			1, // llvm.x86.avx2.psrai.w
			1, // llvm.x86.avx2.psrav.d
			1, // llvm.x86.avx2.psrav.d.256
			1, // llvm.x86.avx2.psrl.d
			1, // llvm.x86.avx2.psrl.dq
			1, // llvm.x86.avx2.psrl.dq.bs
			1, // llvm.x86.avx2.psrl.q
			1, // llvm.x86.avx2.psrl.w
			1, // llvm.x86.avx2.psrli.d
			1, // llvm.x86.avx2.psrli.q
			1, // llvm.x86.avx2.psrli.w
			1, // llvm.x86.avx2.psrlv.d
			1, // llvm.x86.avx2.psrlv.d.256
			1, // llvm.x86.avx2.psrlv.q
			1, // llvm.x86.avx2.psrlv.q.256
			1, // llvm.x86.avx2.psubs.b
			1, // llvm.x86.avx2.psubs.w
			1, // llvm.x86.avx2.psubus.b
			1, // llvm.x86.avx2.psubus.w
			1, // llvm.x86.avx2.vbroadcast.sd.pd.256
			1, // llvm.x86.avx2.vbroadcast.ss.ps
			1, // llvm.x86.avx2.vbroadcast.ss.ps.256
			2, // llvm.x86.avx2.vbroadcasti128
			1, // llvm.x86.avx2.vextracti128
			1, // llvm.x86.avx2.vinserti128
			1, // llvm.x86.avx2.vperm2i128
			1, // llvm.x86.avx512.and.pi
			1, // llvm.x86.avx512.cmpeq.pi.512
			3, // llvm.x86.avx512.conflict.d.512
			3, // llvm.x86.avx512.conflict.d.mask.512
			3, // llvm.x86.avx512.conflict.d.maskz.512
			3, // llvm.x86.avx512.conflict.q.512
			3, // llvm.x86.avx512.conflict.q.mask.512
			3, // llvm.x86.avx512.conflict.q.maskz.512
			1, // llvm.x86.avx512.cvt.ps2dq.512
			1, // llvm.x86.avx512.cvtdq2.ps.512
			1, // llvm.x86.avx512.cvtsd2usi
			1, // llvm.x86.avx512.cvtsd2usi64
			1, // llvm.x86.avx512.cvtss2usi
			1, // llvm.x86.avx512.cvtss2usi64
			1, // llvm.x86.avx512.cvttsd2usi
			1, // llvm.x86.avx512.cvttsd2usi64
			1, // llvm.x86.avx512.cvttss2usi
			1, // llvm.x86.avx512.cvttss2usi64
			1, // llvm.x86.avx512.cvtusi2sd
			1, // llvm.x86.avx512.cvtusi2ss
			1, // llvm.x86.avx512.cvtusi642sd
			1, // llvm.x86.avx512.cvtusi642ss
			2, // llvm.x86.avx512.gather.dpd.512
			2, // llvm.x86.avx512.gather.dpd.mask.512
			2, // llvm.x86.avx512.gather.dpi.512
			2, // llvm.x86.avx512.gather.dpi.mask.512
			2, // llvm.x86.avx512.gather.dpq.512
			2, // llvm.x86.avx512.gather.dpq.mask.512
			2, // llvm.x86.avx512.gather.dps.512
			2, // llvm.x86.avx512.gather.dps.mask.512
			2, // llvm.x86.avx512.gather.qpd.512
			2, // llvm.x86.avx512.gather.qpd.mask.512
			2, // llvm.x86.avx512.gather.qpi.512
			2, // llvm.x86.avx512.gather.qpi.mask.512
			2, // llvm.x86.avx512.gather.qpq.512
			2, // llvm.x86.avx512.gather.qpq.mask.512
			2, // llvm.x86.avx512.gather.qps.512
			2, // llvm.x86.avx512.gather.qps.mask.512
			1, // llvm.x86.avx512.kortestc
			1, // llvm.x86.avx512.kortestz
			1, // llvm.x86.avx512.max.pd.512
			1, // llvm.x86.avx512.max.ps.512
			1, // llvm.x86.avx512.min.pd.512
			1, // llvm.x86.avx512.min.ps.512
			1, // llvm.x86.avx512.mskblend.d.512
			1, // llvm.x86.avx512.mskblend.pd.512
			1, // llvm.x86.avx512.mskblend.ps.512
			1, // llvm.x86.avx512.mskblend.q.512
			1, // llvm.x86.avx512.pbroadcastd.512
			1, // llvm.x86.avx512.pbroadcastd.i32.512
			1, // llvm.x86.avx512.pbroadcastq.512
			1, // llvm.x86.avx512.pbroadcastq.i64.512
			1, // llvm.x86.avx512.pmaxs.d
			1, // llvm.x86.avx512.pmaxs.q
			1, // llvm.x86.avx512.pmaxu.d
			1, // llvm.x86.avx512.pmaxu.q
			1, // llvm.x86.avx512.pmins.d
			1, // llvm.x86.avx512.pmins.q
			1, // llvm.x86.avx512.pminu.d
			1, // llvm.x86.avx512.pminu.q
			1, // llvm.x86.avx512.pmovzxbd
			1, // llvm.x86.avx512.pmovzxbq
			1, // llvm.x86.avx512.pmovzxdq
			1, // llvm.x86.avx512.pmovzxwd
			1, // llvm.x86.avx512.pmovzxwq
			1, // llvm.x86.avx512.psll.dq
			1, // llvm.x86.avx512.psll.dq.bs
			1, // llvm.x86.avx512.psrl.dq
			1, // llvm.x86.avx512.psrl.dq.bs
			1, // llvm.x86.avx512.rcp14.pd.512
			1, // llvm.x86.avx512.rcp14.ps.512
			1, // llvm.x86.avx512.rcp14.sd
			1, // llvm.x86.avx512.rcp14.ss
			1, // llvm.x86.avx512.rcp28.pd.512
			1, // llvm.x86.avx512.rcp28.ps.512
			1, // llvm.x86.avx512.rcp28.sd
			1, // llvm.x86.avx512.rcp28.ss
			1, // llvm.x86.avx512.rndscale.pd.512
			1, // llvm.x86.avx512.rndscale.ps.512
			1, // llvm.x86.avx512.rndscale.sd
			1, // llvm.x86.avx512.rndscale.ss
			1, // llvm.x86.avx512.rsqrt14.pd.512
			1, // llvm.x86.avx512.rsqrt14.ps.512
			1, // llvm.x86.avx512.rsqrt14.sd
			1, // llvm.x86.avx512.rsqrt14.ss
			1, // llvm.x86.avx512.rsqrt28.pd.512
			1, // llvm.x86.avx512.rsqrt28.ps.512
			1, // llvm.x86.avx512.rsqrt28.sd
			1, // llvm.x86.avx512.rsqrt28.ss
			3, // llvm.x86.avx512.scatter.dpd.512
			3, // llvm.x86.avx512.scatter.dpd.mask.512
			3, // llvm.x86.avx512.scatter.dpi.512
			3, // llvm.x86.avx512.scatter.dpi.mask.512
			3, // llvm.x86.avx512.scatter.dpq.512
			3, // llvm.x86.avx512.scatter.dpq.mask.512
			3, // llvm.x86.avx512.scatter.dps.512
			3, // llvm.x86.avx512.scatter.dps.mask.512
			3, // llvm.x86.avx512.scatter.qpd.512
			3, // llvm.x86.avx512.scatter.qpd.mask.512
			3, // llvm.x86.avx512.scatter.qpi.512
			3, // llvm.x86.avx512.scatter.qpi.mask.512
			3, // llvm.x86.avx512.scatter.qpq.512
			3, // llvm.x86.avx512.scatter.qpq.mask.512
			3, // llvm.x86.avx512.scatter.qps.512
			3, // llvm.x86.avx512.scatter.qps.mask.512
			1, // llvm.x86.avx512.sqrt.pd.512
			1, // llvm.x86.avx512.sqrt.ps.512
			1, // llvm.x86.avx512.sqrt.sd
			1, // llvm.x86.avx512.sqrt.ss
			2, // llvm.x86.avx512.vbroadcast.sd.512
			1, // llvm.x86.avx512.vbroadcast.sd.pd.512
			2, // llvm.x86.avx512.vbroadcast.ss.512
			1, // llvm.x86.avx512.vbroadcast.ss.ps.512
			1, // llvm.x86.avx512.vcvtph2ps.512
			1, // llvm.x86.avx512.vcvtps2ph.512
			1, // llvm.x86.avx.addsub.pd.256
			1, // llvm.x86.avx.addsub.ps.256
			1, // llvm.x86.avx.blend.pd.256
			1, // llvm.x86.avx.blend.ps.256
			1, // llvm.x86.avx.blendv.pd.256
			1, // llvm.x86.avx.blendv.ps.256
			1, // llvm.x86.avx.cmp.pd.256
			1, // llvm.x86.avx.cmp.ps.256
			1, // llvm.x86.avx.cvt.pd2.ps.256
			1, // llvm.x86.avx.cvt.pd2dq.256
			1, // llvm.x86.avx.cvt.ps2.pd.256
			1, // llvm.x86.avx.cvt.ps2dq.256
			1, // llvm.x86.avx.cvtdq2.pd.256
			1, // llvm.x86.avx.cvtdq2.ps.256
			1, // llvm.x86.avx.cvtt.pd2dq.256
			1, // llvm.x86.avx.cvtt.ps2dq.256
			1, // llvm.x86.avx.dp.ps.256
			1, // llvm.x86.avx.hadd.pd.256
			1, // llvm.x86.avx.hadd.ps.256
			1, // llvm.x86.avx.hsub.pd.256
			1, // llvm.x86.avx.hsub.ps.256
			2, // llvm.x86.avx.ldu.dq.256
			2, // llvm.x86.avx.maskload.pd
			2, // llvm.x86.avx.maskload.pd.256
			2, // llvm.x86.avx.maskload.ps
			2, // llvm.x86.avx.maskload.ps.256
			3, // llvm.x86.avx.maskstore.pd
			3, // llvm.x86.avx.maskstore.pd.256
			3, // llvm.x86.avx.maskstore.ps
			3, // llvm.x86.avx.maskstore.ps.256
			1, // llvm.x86.avx.max.pd.256
			1, // llvm.x86.avx.max.ps.256
			1, // llvm.x86.avx.min.pd.256
			1, // llvm.x86.avx.min.ps.256
			1, // llvm.x86.avx.movmsk.pd.256
			1, // llvm.x86.avx.movmsk.ps.256
			1, // llvm.x86.avx.ptestc.256
			1, // llvm.x86.avx.ptestnzc.256
			1, // llvm.x86.avx.ptestz.256
			1, // llvm.x86.avx.rcp.ps.256
			1, // llvm.x86.avx.round.pd.256
			1, // llvm.x86.avx.round.ps.256
			1, // llvm.x86.avx.rsqrt.ps.256
			1, // llvm.x86.avx.sqrt.pd.256
			1, // llvm.x86.avx.sqrt.ps.256
			3, // llvm.x86.avx.storeu.dq.256
			3, // llvm.x86.avx.storeu.pd.256
			3, // llvm.x86.avx.storeu.ps.256
			2, // llvm.x86.avx.vbroadcast.sd.256
			2, // llvm.x86.avx.vbroadcast.ss
			2, // llvm.x86.avx.vbroadcast.ss.256
			2, // llvm.x86.avx.vbroadcastf128.pd.256
			2, // llvm.x86.avx.vbroadcastf128.ps.256
			1, // llvm.x86.avx.vextractf128.pd.256
			1, // llvm.x86.avx.vextractf128.ps.256
			1, // llvm.x86.avx.vextractf128.si.256
			1, // llvm.x86.avx.vinsertf128.pd.256
			1, // llvm.x86.avx.vinsertf128.ps.256
			1, // llvm.x86.avx.vinsertf128.si.256
			1, // llvm.x86.avx.vperm2f128.pd.256
			1, // llvm.x86.avx.vperm2f128.ps.256
			1, // llvm.x86.avx.vperm2f128.si.256
			1, // llvm.x86.avx.vpermilvar.pd
			1, // llvm.x86.avx.vpermilvar.pd.256
			1, // llvm.x86.avx.vpermilvar.ps
			1, // llvm.x86.avx.vpermilvar.ps.256
			1, // llvm.x86.avx.vtestc.pd
			1, // llvm.x86.avx.vtestc.pd.256
			1, // llvm.x86.avx.vtestc.ps
			1, // llvm.x86.avx.vtestc.ps.256
			1, // llvm.x86.avx.vtestnzc.pd
			1, // llvm.x86.avx.vtestnzc.pd.256
			1, // llvm.x86.avx.vtestnzc.ps
			1, // llvm.x86.avx.vtestnzc.ps.256
			1, // llvm.x86.avx.vtestz.pd
			1, // llvm.x86.avx.vtestz.pd.256
			1, // llvm.x86.avx.vtestz.ps
			1, // llvm.x86.avx.vtestz.ps.256
			3, // llvm.x86.avx.vzeroall
			3, // llvm.x86.avx.vzeroupper
			1, // llvm.x86.bmi.bextr.32
			1, // llvm.x86.bmi.bextr.64
			1, // llvm.x86.bmi.bzhi.32
			1, // llvm.x86.bmi.bzhi.64
			1, // llvm.x86.bmi.pdep.32
			1, // llvm.x86.bmi.pdep.64
			1, // llvm.x86.bmi.pext.32
			1, // llvm.x86.bmi.pext.64
			1, // llvm.x86.fma.vfmadd.pd
			1, // llvm.x86.fma.vfmadd.pd.256
			1, // llvm.x86.fma.vfmadd.pd.512
			1, // llvm.x86.fma.vfmadd.ps
			1, // llvm.x86.fma.vfmadd.ps.256
			1, // llvm.x86.fma.vfmadd.ps.512
			1, // llvm.x86.fma.vfmadd.sd
			1, // llvm.x86.fma.vfmadd.ss
			1, // llvm.x86.fma.vfmaddsub.pd
			1, // llvm.x86.fma.vfmaddsub.pd.256
			1, // llvm.x86.fma.vfmaddsub.pd.512
			1, // llvm.x86.fma.vfmaddsub.ps
			1, // llvm.x86.fma.vfmaddsub.ps.256
			1, // llvm.x86.fma.vfmaddsub.ps.512
			1, // llvm.x86.fma.vfmsub.pd
			1, // llvm.x86.fma.vfmsub.pd.256
			1, // llvm.x86.fma.vfmsub.pd.512
			1, // llvm.x86.fma.vfmsub.ps
			1, // llvm.x86.fma.vfmsub.ps.256
			1, // llvm.x86.fma.vfmsub.ps.512
			1, // llvm.x86.fma.vfmsub.sd
			1, // llvm.x86.fma.vfmsub.ss
			1, // llvm.x86.fma.vfmsubadd.pd
			1, // llvm.x86.fma.vfmsubadd.pd.256
			1, // llvm.x86.fma.vfmsubadd.pd.512
			1, // llvm.x86.fma.vfmsubadd.ps
			1, // llvm.x86.fma.vfmsubadd.ps.256
			1, // llvm.x86.fma.vfmsubadd.ps.512
			1, // llvm.x86.fma.vfnmadd.pd
			1, // llvm.x86.fma.vfnmadd.pd.256
			1, // llvm.x86.fma.vfnmadd.pd.512
			1, // llvm.x86.fma.vfnmadd.ps
			1, // llvm.x86.fma.vfnmadd.ps.256
			1, // llvm.x86.fma.vfnmadd.ps.512
			1, // llvm.x86.fma.vfnmadd.sd
			1, // llvm.x86.fma.vfnmadd.ss
			1, // llvm.x86.fma.vfnmsub.pd
			1, // llvm.x86.fma.vfnmsub.pd.256
			1, // llvm.x86.fma.vfnmsub.pd.512
			1, // llvm.x86.fma.vfnmsub.ps
			1, // llvm.x86.fma.vfnmsub.ps.256
			1, // llvm.x86.fma.vfnmsub.ps.512
			1, // llvm.x86.fma.vfnmsub.sd
			1, // llvm.x86.fma.vfnmsub.ss
			3, // llvm.x86.int
			1, // llvm.x86.int2mask.v16i1
			1, // llvm.x86.kadd.v16i1
			1, // llvm.x86.kand.v16i1
			1, // llvm.x86.kandn.v16i1
			1, // llvm.x86.knot.v16i1
			1, // llvm.x86.kor.v16i1
			1, // llvm.x86.kunpck.v16i1
			1, // llvm.x86.kxnor.v16i1
			1, // llvm.x86.kxor.v16i1
			1, // llvm.x86.mask2int.v16i1
			3, // llvm.x86.mmx.emms
			3, // llvm.x86.mmx.femms
			3, // llvm.x86.mmx.maskmovq
			3, // llvm.x86.mmx.movnt.dq
			1, // llvm.x86.mmx.packssdw
			1, // llvm.x86.mmx.packsswb
			1, // llvm.x86.mmx.packuswb
			1, // llvm.x86.mmx.padd.b
			1, // llvm.x86.mmx.padd.d
			1, // llvm.x86.mmx.padd.q
			1, // llvm.x86.mmx.padd.w
			1, // llvm.x86.mmx.padds.b
			1, // llvm.x86.mmx.padds.w
			1, // llvm.x86.mmx.paddus.b
			1, // llvm.x86.mmx.paddus.w
			1, // llvm.x86.mmx.palignr.b
			1, // llvm.x86.mmx.pand
			1, // llvm.x86.mmx.pandn
			1, // llvm.x86.mmx.pavg.b
			1, // llvm.x86.mmx.pavg.w
			1, // llvm.x86.mmx.pcmpeq.b
			1, // llvm.x86.mmx.pcmpeq.d
			1, // llvm.x86.mmx.pcmpeq.w
			1, // llvm.x86.mmx.pcmpgt.b
			1, // llvm.x86.mmx.pcmpgt.d
			1, // llvm.x86.mmx.pcmpgt.w
			1, // llvm.x86.mmx.pextr.w
			1, // llvm.x86.mmx.pinsr.w
			1, // llvm.x86.mmx.pmadd.wd
			1, // llvm.x86.mmx.pmaxs.w
			1, // llvm.x86.mmx.pmaxu.b
			1, // llvm.x86.mmx.pmins.w
			1, // llvm.x86.mmx.pminu.b
			1, // llvm.x86.mmx.pmovmskb
			1, // llvm.x86.mmx.pmulh.w
			1, // llvm.x86.mmx.pmulhu.w
			1, // llvm.x86.mmx.pmull.w
			1, // llvm.x86.mmx.pmulu.dq
			1, // llvm.x86.mmx.por
			1, // llvm.x86.mmx.psad.bw
			1, // llvm.x86.mmx.psll.d
			1, // llvm.x86.mmx.psll.q
			1, // llvm.x86.mmx.psll.w
			1, // llvm.x86.mmx.pslli.d
			1, // llvm.x86.mmx.pslli.q
			1, // llvm.x86.mmx.pslli.w
			1, // llvm.x86.mmx.psra.d
			1, // llvm.x86.mmx.psra.w
			1, // llvm.x86.mmx.psrai.d
			1, // llvm.x86.mmx.psrai.w
			1, // llvm.x86.mmx.psrl.d
			1, // llvm.x86.mmx.psrl.q
			1, // llvm.x86.mmx.psrl.w
			1, // llvm.x86.mmx.psrli.d
			1, // llvm.x86.mmx.psrli.q
			1, // llvm.x86.mmx.psrli.w
			1, // llvm.x86.mmx.psub.b
			1, // llvm.x86.mmx.psub.d
			1, // llvm.x86.mmx.psub.q
			1, // llvm.x86.mmx.psub.w
			1, // llvm.x86.mmx.psubs.b
			1, // llvm.x86.mmx.psubs.w
			1, // llvm.x86.mmx.psubus.b
			1, // llvm.x86.mmx.psubus.w
			1, // llvm.x86.mmx.punpckhbw
			1, // llvm.x86.mmx.punpckhdq
			1, // llvm.x86.mmx.punpckhwd
			1, // llvm.x86.mmx.punpcklbw
			1, // llvm.x86.mmx.punpckldq
			1, // llvm.x86.mmx.punpcklwd
			1, // llvm.x86.mmx.pxor
			1, // llvm.x86.pclmulqdq
			3, // llvm.x86.rdfsbase.32
			3, // llvm.x86.rdfsbase.64
			3, // llvm.x86.rdgsbase.32
			3, // llvm.x86.rdgsbase.64
			3, // llvm.x86.rdrand.16
			3, // llvm.x86.rdrand.32
			3, // llvm.x86.rdrand.64
			3, // llvm.x86.rdseed.16
			3, // llvm.x86.rdseed.32
			3, // llvm.x86.rdseed.64
			1, // llvm.x86.sha1msg1
			1, // llvm.x86.sha1msg2
			1, // llvm.x86.sha1nexte
			1, // llvm.x86.sha1rnds4
			1, // llvm.x86.sha256msg1
			1, // llvm.x86.sha256msg2
			1, // llvm.x86.sha256rnds2
			1, // llvm.x86.sse2.add.sd
			3, // llvm.x86.sse2.clflush
			1, // llvm.x86.sse2.cmp.pd
			1, // llvm.x86.sse2.cmp.sd
			1, // llvm.x86.sse2.comieq.sd
			1, // llvm.x86.sse2.comige.sd
			1, // llvm.x86.sse2.comigt.sd
			1, // llvm.x86.sse2.comile.sd
			1, // llvm.x86.sse2.comilt.sd
			1, // llvm.x86.sse2.comineq.sd
			1, // llvm.x86.sse2.cvtdq2pd
			1, // llvm.x86.sse2.cvtdq2ps
			1, // llvm.x86.sse2.cvtpd2dq
			1, // llvm.x86.sse2.cvtpd2ps
			1, // llvm.x86.sse2.cvtps2dq
			1, // llvm.x86.sse2.cvtps2pd
			1, // llvm.x86.sse2.cvtsd2si
			1, // llvm.x86.sse2.cvtsd2si64
			1, // llvm.x86.sse2.cvtsd2ss
			1, // llvm.x86.sse2.cvtsi2sd
			1, // llvm.x86.sse2.cvtsi642sd
			1, // llvm.x86.sse2.cvtss2sd
			1, // llvm.x86.sse2.cvttpd2dq
			1, // llvm.x86.sse2.cvttps2dq
			1, // llvm.x86.sse2.cvttsd2si
			1, // llvm.x86.sse2.cvttsd2si64
			1, // llvm.x86.sse2.div.sd
			3, // llvm.x86.sse2.lfence
			3, // llvm.x86.sse2.maskmov.dqu
			1, // llvm.x86.sse2.max.pd
			1, // llvm.x86.sse2.max.sd
			3, // llvm.x86.sse2.mfence
			1, // llvm.x86.sse2.min.pd
			1, // llvm.x86.sse2.min.sd
			1, // llvm.x86.sse2.movmsk.pd
			1, // llvm.x86.sse2.mul.sd
			1, // llvm.x86.sse2.packssdw.128
			1, // llvm.x86.sse2.packsswb.128
			1, // llvm.x86.sse2.packuswb.128
			1, // llvm.x86.sse2.padds.b
			1, // llvm.x86.sse2.padds.w
			1, // llvm.x86.sse2.paddus.b
			1, // llvm.x86.sse2.paddus.w
			1, // llvm.x86.sse2.pavg.b
			1, // llvm.x86.sse2.pavg.w
			1, // llvm.x86.sse2.pmadd.wd
			1, // llvm.x86.sse2.pmaxs.w
			1, // llvm.x86.sse2.pmaxu.b
			1, // llvm.x86.sse2.pmins.w
			1, // llvm.x86.sse2.pminu.b
			1, // llvm.x86.sse2.pmovmskb.128
			1, // llvm.x86.sse2.pmulh.w
			1, // llvm.x86.sse2.pmulhu.w
			1, // llvm.x86.sse2.pmulu.dq
			1, // llvm.x86.sse2.psad.bw
			1, // llvm.x86.sse2.psll.d
			1, // llvm.x86.sse2.psll.dq
			1, // llvm.x86.sse2.psll.dq.bs
			1, // llvm.x86.sse2.psll.q
			1, // llvm.x86.sse2.psll.w
			1, // llvm.x86.sse2.pslli.d
			1, // llvm.x86.sse2.pslli.q
			1, // llvm.x86.sse2.pslli.w
			1, // llvm.x86.sse2.psra.d
			1, // llvm.x86.sse2.psra.w
			1, // llvm.x86.sse2.psrai.d
			1, // llvm.x86.sse2.psrai.w
			1, // llvm.x86.sse2.psrl.d
			1, // llvm.x86.sse2.psrl.dq
			1, // llvm.x86.sse2.psrl.dq.bs
			1, // llvm.x86.sse2.psrl.q
			1, // llvm.x86.sse2.psrl.w
			1, // llvm.x86.sse2.psrli.d
			1, // llvm.x86.sse2.psrli.q
			1, // llvm.x86.sse2.psrli.w
			1, // llvm.x86.sse2.psubs.b
			1, // llvm.x86.sse2.psubs.w
			1, // llvm.x86.sse2.psubus.b
			1, // llvm.x86.sse2.psubus.w
			1, // llvm.x86.sse2.sqrt.pd
			1, // llvm.x86.sse2.sqrt.sd
			3, // llvm.x86.sse2.storel.dq
			3, // llvm.x86.sse2.storeu.dq
			3, // llvm.x86.sse2.storeu.pd
			1, // llvm.x86.sse2.sub.sd
			1, // llvm.x86.sse2.ucomieq.sd
			1, // llvm.x86.sse2.ucomige.sd
			1, // llvm.x86.sse2.ucomigt.sd
			1, // llvm.x86.sse2.ucomile.sd
			1, // llvm.x86.sse2.ucomilt.sd
			1, // llvm.x86.sse2.ucomineq.sd
			1, // llvm.x86.sse3.addsub.pd
			1, // llvm.x86.sse3.addsub.ps
			1, // llvm.x86.sse3.hadd.pd
			1, // llvm.x86.sse3.hadd.ps
			1, // llvm.x86.sse3.hsub.pd
			1, // llvm.x86.sse3.hsub.ps
			2, // llvm.x86.sse3.ldu.dq
			3, // llvm.x86.sse3.monitor
			3, // llvm.x86.sse3.mwait
			1, // llvm.x86.sse41.blendpd
			1, // llvm.x86.sse41.blendps
			1, // llvm.x86.sse41.blendvpd
			1, // llvm.x86.sse41.blendvps
			1, // llvm.x86.sse41.dppd
			1, // llvm.x86.sse41.dpps
			1, // llvm.x86.sse41.extractps
			1, // llvm.x86.sse41.insertps
			2, // llvm.x86.sse41.movntdqa
			1, // llvm.x86.sse41.mpsadbw
			1, // llvm.x86.sse41.packusdw
			1, // llvm.x86.sse41.pblendvb
			1, // llvm.x86.sse41.pblendw
			1, // llvm.x86.sse41.pextrb
			1, // llvm.x86.sse41.pextrd
			1, // llvm.x86.sse41.pextrq
			1, // llvm.x86.sse41.phminposuw
			1, // llvm.x86.sse41.pmaxsb
			1, // llvm.x86.sse41.pmaxsd
			1, // llvm.x86.sse41.pmaxud
			1, // llvm.x86.sse41.pmaxuw
			1, // llvm.x86.sse41.pminsb
			1, // llvm.x86.sse41.pminsd
			1, // llvm.x86.sse41.pminud
			1, // llvm.x86.sse41.pminuw
			1, // llvm.x86.sse41.pmovsxbd
			1, // llvm.x86.sse41.pmovsxbq
			1, // llvm.x86.sse41.pmovsxbw
			1, // llvm.x86.sse41.pmovsxdq
			1, // llvm.x86.sse41.pmovsxwd
			1, // llvm.x86.sse41.pmovsxwq
			1, // llvm.x86.sse41.pmovzxbd
			1, // llvm.x86.sse41.pmovzxbq
			1, // llvm.x86.sse41.pmovzxbw
			1, // llvm.x86.sse41.pmovzxdq
			1, // llvm.x86.sse41.pmovzxwd
			1, // llvm.x86.sse41.pmovzxwq
			1, // llvm.x86.sse41.pmuldq
			1, // llvm.x86.sse41.ptestc
			1, // llvm.x86.sse41.ptestnzc
			1, // llvm.x86.sse41.ptestz
			1, // llvm.x86.sse41.round.pd
			1, // llvm.x86.sse41.round.ps
			1, // llvm.x86.sse41.round.sd
			1, // llvm.x86.sse41.round.ss
			1, // llvm.x86.sse42.crc32.32.16
			1, // llvm.x86.sse42.crc32.32.32
			1, // llvm.x86.sse42.crc32.32.8
			1, // llvm.x86.sse42.crc32.64.64
			1, // llvm.x86.sse42.pcmpestri128
			1, // llvm.x86.sse42.pcmpestria128
			1, // llvm.x86.sse42.pcmpestric128
			1, // llvm.x86.sse42.pcmpestrio128
			1, // llvm.x86.sse42.pcmpestris128
			1, // llvm.x86.sse42.pcmpestriz128
			1, // llvm.x86.sse42.pcmpestrm128
			1, // llvm.x86.sse42.pcmpistri128
			1, // llvm.x86.sse42.pcmpistria128
			1, // llvm.x86.sse42.pcmpistric128
			1, // llvm.x86.sse42.pcmpistrio128
			1, // llvm.x86.sse42.pcmpistris128
			1, // llvm.x86.sse42.pcmpistriz128
			1, // llvm.x86.sse42.pcmpistrm128
			1, // llvm.x86.sse4a.extrq
			1, // llvm.x86.sse4a.extrqi
			1, // llvm.x86.sse4a.insertq
			1, // llvm.x86.sse4a.insertqi
			3, // llvm.x86.sse4a.movnt.sd
			3, // llvm.x86.sse4a.movnt.ss
			1, // llvm.x86.sse.add.ss
			1, // llvm.x86.sse.cmp.ps
			1, // llvm.x86.sse.cmp.ss
			1, // llvm.x86.sse.comieq.ss
			1, // llvm.x86.sse.comige.ss
			1, // llvm.x86.sse.comigt.ss
			1, // llvm.x86.sse.comile.ss
			1, // llvm.x86.sse.comilt.ss
			1, // llvm.x86.sse.comineq.ss
			1, // llvm.x86.sse.cvtpd2pi
			1, // llvm.x86.sse.cvtpi2pd
			1, // llvm.x86.sse.cvtpi2ps
			1, // llvm.x86.sse.cvtps2pi
			1, // llvm.x86.sse.cvtsi2ss
			1, // llvm.x86.sse.cvtsi642ss
			1, // llvm.x86.sse.cvtss2si
			1, // llvm.x86.sse.cvtss2si64
			1, // llvm.x86.sse.cvttpd2pi
			1, // llvm.x86.sse.cvttps2pi
			1, // llvm.x86.sse.cvttss2si
			1, // llvm.x86.sse.cvttss2si64
			1, // llvm.x86.sse.div.ss
			3, // llvm.x86.sse.ldmxcsr
			1, // llvm.x86.sse.max.ps
			1, // llvm.x86.sse.max.ss
			1, // llvm.x86.sse.min.ps
			1, // llvm.x86.sse.min.ss
			1, // llvm.x86.sse.movmsk.ps
			1, // llvm.x86.sse.mul.ss
			1, // llvm.x86.sse.pshuf.w
			1, // llvm.x86.sse.rcp.ps
			1, // llvm.x86.sse.rcp.ss
			1, // llvm.x86.sse.rsqrt.ps
			1, // llvm.x86.sse.rsqrt.ss
			3, // llvm.x86.sse.sfence
			1, // llvm.x86.sse.sqrt.ps
			1, // llvm.x86.sse.sqrt.ss
			3, // llvm.x86.sse.stmxcsr
			3, // llvm.x86.sse.storeu.ps
			1, // llvm.x86.sse.sub.ss
			1, // llvm.x86.sse.ucomieq.ss
			1, // llvm.x86.sse.ucomige.ss
			1, // llvm.x86.sse.ucomigt.ss
			1, // llvm.x86.sse.ucomile.ss
			1, // llvm.x86.sse.ucomilt.ss
			1, // llvm.x86.sse.ucomineq.ss
			1, // llvm.x86.ssse3.pabs.b
			1, // llvm.x86.ssse3.pabs.b.128
			1, // llvm.x86.ssse3.pabs.d
			1, // llvm.x86.ssse3.pabs.d.128
			1, // llvm.x86.ssse3.pabs.w
			1, // llvm.x86.ssse3.pabs.w.128
			1, // llvm.x86.ssse3.phadd.d
			1, // llvm.x86.ssse3.phadd.d.128
			1, // llvm.x86.ssse3.phadd.sw
			1, // llvm.x86.ssse3.phadd.sw.128
			1, // llvm.x86.ssse3.phadd.w
			1, // llvm.x86.ssse3.phadd.w.128
			1, // llvm.x86.ssse3.phsub.d
			1, // llvm.x86.ssse3.phsub.d.128
			1, // llvm.x86.ssse3.phsub.sw
			1, // llvm.x86.ssse3.phsub.sw.128
			1, // llvm.x86.ssse3.phsub.w
			1, // llvm.x86.ssse3.phsub.w.128
			1, // llvm.x86.ssse3.pmadd.ub.sw
			1, // llvm.x86.ssse3.pmadd.ub.sw.128
			1, // llvm.x86.ssse3.pmul.hr.sw
			1, // llvm.x86.ssse3.pmul.hr.sw.128
			1, // llvm.x86.ssse3.pshuf.b
			1, // llvm.x86.ssse3.pshuf.b.128
			1, // llvm.x86.ssse3.psign.b
			1, // llvm.x86.ssse3.psign.b.128
			1, // llvm.x86.ssse3.psign.d
			1, // llvm.x86.ssse3.psign.d.128
			1, // llvm.x86.ssse3.psign.w
			1, // llvm.x86.ssse3.psign.w.128
			1, // llvm.x86.tbm.bextri.u32
			1, // llvm.x86.tbm.bextri.u64
			1, // llvm.x86.vcvtph2ps.128
			1, // llvm.x86.vcvtph2ps.256
			1, // llvm.x86.vcvtps2ph.128
			1, // llvm.x86.vcvtps2ph.256
			3, // llvm.x86.wrfsbase.32
			3, // llvm.x86.wrfsbase.64
			3, // llvm.x86.wrgsbase.32
			3, // llvm.x86.wrgsbase.64
			4, // llvm.x86.xabort
			3, // llvm.x86.xbegin
			3, // llvm.x86.xend
			1, // llvm.x86.xop.vfrcz.pd
			1, // llvm.x86.xop.vfrcz.pd.256
			1, // llvm.x86.xop.vfrcz.ps
			1, // llvm.x86.xop.vfrcz.ps.256
			1, // llvm.x86.xop.vfrcz.sd
			1, // llvm.x86.xop.vfrcz.ss
			1, // llvm.x86.xop.vpcmov
			1, // llvm.x86.xop.vpcmov.256
			1, // llvm.x86.xop.vpcomb
			1, // llvm.x86.xop.vpcomd
			1, // llvm.x86.xop.vpcomq
			1, // llvm.x86.xop.vpcomub
			1, // llvm.x86.xop.vpcomud
			1, // llvm.x86.xop.vpcomuq
			1, // llvm.x86.xop.vpcomuw
			1, // llvm.x86.xop.vpcomw
			1, // llvm.x86.xop.vpermil2pd
			1, // llvm.x86.xop.vpermil2pd.256
			1, // llvm.x86.xop.vpermil2ps
			1, // llvm.x86.xop.vpermil2ps.256
			1, // llvm.x86.xop.vphaddbd
			1, // llvm.x86.xop.vphaddbq
			1, // llvm.x86.xop.vphaddbw
			1, // llvm.x86.xop.vphadddq
			1, // llvm.x86.xop.vphaddubd
			1, // llvm.x86.xop.vphaddubq
			1, // llvm.x86.xop.vphaddubw
			1, // llvm.x86.xop.vphaddudq
			1, // llvm.x86.xop.vphadduwd
			1, // llvm.x86.xop.vphadduwq
			1, // llvm.x86.xop.vphaddwd
			1, // llvm.x86.xop.vphaddwq
			1, // llvm.x86.xop.vphsubbw
			1, // llvm.x86.xop.vphsubdq
			1, // llvm.x86.xop.vphsubwd
			1, // llvm.x86.xop.vpmacsdd
			1, // llvm.x86.xop.vpmacsdqh
			1, // llvm.x86.xop.vpmacsdql
			1, // llvm.x86.xop.vpmacssdd
			1, // llvm.x86.xop.vpmacssdqh
			1, // llvm.x86.xop.vpmacssdql
			1, // llvm.x86.xop.vpmacsswd
			1, // llvm.x86.xop.vpmacssww
			1, // llvm.x86.xop.vpmacswd
			1, // llvm.x86.xop.vpmacsww
			1, // llvm.x86.xop.vpmadcsswd
			1, // llvm.x86.xop.vpmadcswd
			1, // llvm.x86.xop.vpperm
			1, // llvm.x86.xop.vprotb
			1, // llvm.x86.xop.vprotbi
			1, // llvm.x86.xop.vprotd
			1, // llvm.x86.xop.vprotdi
			1, // llvm.x86.xop.vprotq
			1, // llvm.x86.xop.vprotqi
			1, // llvm.x86.xop.vprotw
			1, // llvm.x86.xop.vprotwi
			1, // llvm.x86.xop.vpshab
			1, // llvm.x86.xop.vpshad
			1, // llvm.x86.xop.vpshaq
			1, // llvm.x86.xop.vpshaw
			1, // llvm.x86.xop.vpshlb
			1, // llvm.x86.xop.vpshld
			1, // llvm.x86.xop.vpshlq
			1, // llvm.x86.xop.vpshlw
			3, // llvm.x86.xtest
			1, // llvm.xcore.bitrev
			3, // llvm.xcore.checkevent
			6, // llvm.xcore.chkct
			3, // llvm.xcore.clre
			3, // llvm.xcore.clrsr
			1, // llvm.xcore.crc32
			1, // llvm.xcore.crc8
			6, // llvm.xcore.eeu
			6, // llvm.xcore.endin
			6, // llvm.xcore.freer
			3, // llvm.xcore.geted
			3, // llvm.xcore.getet
			1, // llvm.xcore.getid
			3, // llvm.xcore.getps
			3, // llvm.xcore.getr
			6, // llvm.xcore.getst
			6, // llvm.xcore.getts
			6, // llvm.xcore.in
			6, // llvm.xcore.inct
			6, // llvm.xcore.initcp
			6, // llvm.xcore.initdp
			6, // llvm.xcore.initlr
			6, // llvm.xcore.initpc
			6, // llvm.xcore.initsp
			6, // llvm.xcore.inshr
			6, // llvm.xcore.int
			6, // llvm.xcore.mjoin
			6, // llvm.xcore.msync
			6, // llvm.xcore.out
			6, // llvm.xcore.outct
			6, // llvm.xcore.outshr
			6, // llvm.xcore.outt
			6, // llvm.xcore.peek
			6, // llvm.xcore.setc
			12, // llvm.xcore.setclk
			6, // llvm.xcore.setd
			6, // llvm.xcore.setev
			3, // llvm.xcore.setps
			6, // llvm.xcore.setpsc
			6, // llvm.xcore.setpt
			12, // llvm.xcore.setrdy
			3, // llvm.xcore.setsr
			6, // llvm.xcore.settw
			6, // llvm.xcore.setv
			1, // llvm.xcore.sext
			3, // llvm.xcore.ssync
			6, // llvm.xcore.syncr
			6, // llvm.xcore.testct
			6, // llvm.xcore.testwct
			2, // llvm.xcore.waitevent
			1, // llvm.xcore.zext
			};
			AttributeSet AS[4];
			unsigned NumAttrs = 0;
			if (id != 0) {
			switch(IntrinsicsToAttributesMap[id - 1]) {
			default: llvm_unreachable("Invalid attribute number");
			case 1: {
			const Attribute::AttrKind Atts[] = {Attribute::NoUnwind,Attribute::Re
			adNone};
			AS[0] = AttributeSet::get(C, AttributeSet::FunctionIndex, Atts);
			NumAttrs = 1;
			break;
			}
			case 11: {
			const Attribute::AttrKind AttrParam1[]= {Attribute::NoCapture};
			AS[0] = AttributeSet::get(C, 1, AttrParam1);
			const Attribute::AttrKind Atts[] = {Attribute::NoUnwind,Attribute::Re
			adNone};
			AS[1] = AttributeSet::get(C, AttributeSet::FunctionIndex, Atts);
			NumAttrs = 2;
			break;
			}
			case 2: {
			const Attribute::AttrKind Atts[] = {Attribute::NoUnwind,Attribute::Re
			adOnly};
			AS[0] = AttributeSet::get(C, AttributeSet::FunctionIndex, Atts);
			NumAttrs = 1;
			break;
			}
			case 10: {
			const Attribute::AttrKind AttrParam1[]= {Attribute::NoCapture};
			AS[0] = AttributeSet::get(C, 1, AttrParam1);
			const Attribute::AttrKind Atts[] = {Attribute::NoUnwind,Attribute::Re
			adOnly};
			AS[1] = AttributeSet::get(C, AttributeSet::FunctionIndex, Atts);
			NumAttrs = 2;
			break;
			}
			case 3: {
			const Attribute::AttrKind Atts[] = {Attribute::NoUnwind};
			AS[0] = AttributeSet::get(C, AttributeSet::FunctionIndex, Atts);
			NumAttrs = 1;
			break;
			}
			case 6: {
			const Attribute::AttrKind AttrParam1[]= {Attribute::NoCapture};
			AS[0] = AttributeSet::get(C, 1, AttrParam1);
			const Attribute::AttrKind Atts[] = {Attribute::NoUnwind};
			AS[1] = AttributeSet::get(C, AttributeSet::FunctionIndex, Atts);
			NumAttrs = 2;
			break;
			}
			case 12: {
			const Attribute::AttrKind AttrParam1[]= {Attribute::NoCapture};
			AS[0] = AttributeSet::get(C, 1, AttrParam1);
			const Attribute::AttrKind AttrParam2[]= {Attribute::NoCapture};
			AS[1] = AttributeSet::get(C, 2, AttrParam2);
			const Attribute::AttrKind Atts[] = {Attribute::NoUnwind};
			AS[2] = AttributeSet::get(C, AttributeSet::FunctionIndex, Atts);
			NumAttrs = 3;
			break;
			}
			case 9: {
			const Attribute::AttrKind AttrParam1[]= {Attribute::NoCapture};
			AS[0] = AttributeSet::get(C, 1, AttrParam1);
			const Attribute::AttrKind AttrParam2[]= {Attribute::NoCapture,Attribu
			te::ReadOnly};
			AS[1] = AttributeSet::get(C, 2, AttrParam2);
			const Attribute::AttrKind Atts[] = {Attribute::NoUnwind};
			AS[2] = AttributeSet::get(C, AttributeSet::FunctionIndex, Atts);
			NumAttrs = 3;
			break;
			}
			case 8: {
			const Attribute::AttrKind AttrParam2[]= {Attribute::NoCapture};
			AS[0] = AttributeSet::get(C, 2, AttrParam2);
			const Attribute::AttrKind Atts[] = {Attribute::NoUnwind};
			AS[1] = AttributeSet::get(C, AttributeSet::FunctionIndex, Atts);
			NumAttrs = 2;
			break;
			}
			case 5: {
			const Attribute::AttrKind AttrParam2[]= {Attribute::NoCapture};
			AS[0] = AttributeSet::get(C, 2, AttrParam2);
			const Attribute::AttrKind AttrParam3[]= {Attribute::NoCapture};
			AS[1] = AttributeSet::get(C, 3, AttrParam3);
			const Attribute::AttrKind Atts[] = {Attribute::NoUnwind};
			AS[2] = AttributeSet::get(C, AttributeSet::FunctionIndex, Atts);
			NumAttrs = 3;
			break;
			}
			case 7: {
			const Attribute::AttrKind AttrParam3[]= {Attribute::NoCapture};
			AS[0] = AttributeSet::get(C, 3, AttrParam3);
			const Attribute::AttrKind Atts[] = {Attribute::NoUnwind};
			AS[1] = AttributeSet::get(C, AttributeSet::FunctionIndex, Atts);
			NumAttrs = 2;
			break;
			}
			case 4: {
			const Attribute::AttrKind Atts[] = {Attribute::NoUnwind,Attribute::No
			Return};
			AS[0] = AttributeSet::get(C, AttributeSet::FunctionIndex, Atts);
			NumAttrs = 1;
			break;
			}
			}
			}
			return AttributeSet::get(C, ArrayRef<AttributeSet>(AS, NumAttrs));
			}
			#endif // GET_INTRINSIC_ATTRIBUTES
			// Determine intrinsic alias analysis mod/ref behavior.
			#ifdef GET_INTRINSIC_MODREF_BEHAVIOR
			assert(iid <= Intrinsic::xcore_zext && "Unknown intrinsic.");
			static const uint8_t IntrinsicModRefBehavior[] = {
			/* invalid */ UnknownModRefBehavior,
			/* aarch64_neon_fcvtas */ DoesNotAccessMemory,
			/* aarch64_neon_fcvtau */ DoesNotAccessMemory,
			/* aarch64_neon_fcvtms */ DoesNotAccessMemory,
			/* aarch64_neon_fcvtmu */ DoesNotAccessMemory,
			/* aarch64_neon_fcvtns */ DoesNotAccessMemory,
			/* aarch64_neon_fcvtnu */ DoesNotAccessMemory,
			/* aarch64_neon_fcvtps */ DoesNotAccessMemory,
			/* aarch64_neon_fcvtpu */ DoesNotAccessMemory,
			/* aarch64_neon_fcvtxn */ DoesNotAccessMemory,
			/* aarch64_neon_fcvtzs */ DoesNotAccessMemory,
			/* aarch64_neon_fcvtzu */ DoesNotAccessMemory,
			/* aarch64_neon_frintn */ DoesNotAccessMemory,
			/* aarch64_neon_fsqrt */ DoesNotAccessMemory,
			/* aarch64_neon_rbit */ DoesNotAccessMemory,
			/* aarch64_neon_saddlv */ DoesNotAccessMemory,
			/* aarch64_neon_sha1c */ DoesNotAccessMemory,
			/* aarch64_neon_sha1m */ DoesNotAccessMemory,
			/* aarch64_neon_sha1p */ DoesNotAccessMemory,
			/* aarch64_neon_smaxv */ DoesNotAccessMemory,
			/* aarch64_neon_sminv */ DoesNotAccessMemory,
			/* aarch64_neon_suqadd */ DoesNotAccessMemory,
			/* aarch64_neon_uaddlv */ DoesNotAccessMemory,
			/* aarch64_neon_umaxv */ DoesNotAccessMemory,
			/* aarch64_neon_uminv */ DoesNotAccessMemory,
			/* aarch64_neon_usqadd */ DoesNotAccessMemory,
			/* aarch64_neon_vabd */ DoesNotAccessMemory,
			/* aarch64_neon_vabs */ DoesNotAccessMemory,
			/* aarch64_neon_vacgeq */ DoesNotAccessMemory,
			/* aarch64_neon_vacgtq */ DoesNotAccessMemory,
			/* aarch64_neon_vaddds */ DoesNotAccessMemory,
			/* aarch64_neon_vadddu */ DoesNotAccessMemory,
			/* aarch64_neon_vaddv */ DoesNotAccessMemory,
			/* aarch64_neon_vcage */ DoesNotAccessMemory,
			/* aarch64_neon_vcagt */ DoesNotAccessMemory,
			/* aarch64_neon_vceq */ DoesNotAccessMemory,
			/* aarch64_neon_vcge */ DoesNotAccessMemory,
			/* aarch64_neon_vcgt */ DoesNotAccessMemory,
			/* aarch64_neon_vchi */ DoesNotAccessMemory,
			/* aarch64_neon_vchs */ DoesNotAccessMemory,
			/* aarch64_neon_vclez */ DoesNotAccessMemory,
			/* aarch64_neon_vcltz */ DoesNotAccessMemory,
			/* aarch64_neon_vcvtd_n_s64_f64 */ DoesNotAccessMemory,
			/* aarch64_neon_vcvtd_n_u64_f64 */ DoesNotAccessMemory,
			/* aarch64_neon_vcvtf32_n_s32 */ DoesNotAccessMemory,
			/* aarch64_neon_vcvtf32_n_u32 */ DoesNotAccessMemory,
			/* aarch64_neon_vcvtf32_s32 */ DoesNotAccessMemory,
			/* aarch64_neon_vcvtf32_u32 */ DoesNotAccessMemory,
			/* aarch64_neon_vcvtf64_n_s64 */ DoesNotAccessMemory,
			/* aarch64_neon_vcvtf64_n_u64 */ DoesNotAccessMemory,
			/* aarch64_neon_vcvtf64_s64 */ DoesNotAccessMemory,
			/* aarch64_neon_vcvtf64_u64 */ DoesNotAccessMemory,
			/* aarch64_neon_vcvts_n_s32_f32 */ DoesNotAccessMemory,
			/* aarch64_neon_vcvts_n_u32_f32 */ DoesNotAccessMemory,
			/* aarch64_neon_vld1x2 */ OnlyReadsArgumentPointees,
			/* aarch64_neon_vld1x3 */ OnlyReadsArgumentPointees,
			/* aarch64_neon_vld1x4 */ OnlyReadsArgumentPointees,
			/* aarch64_neon_vmaxnm */ DoesNotAccessMemory,
			/* aarch64_neon_vmaxnmv */ DoesNotAccessMemory,
			/* aarch64_neon_vmaxv */ DoesNotAccessMemory,
			/* aarch64_neon_vminnm */ DoesNotAccessMemory,
			/* aarch64_neon_vminnmv */ DoesNotAccessMemory,
			/* aarch64_neon_vminv */ DoesNotAccessMemory,
			/* aarch64_neon_vmulx */ UnknownModRefBehavior,
			/* aarch64_neon_vneg */ DoesNotAccessMemory,
			/* aarch64_neon_vpadd */ DoesNotAccessMemory,
			/* aarch64_neon_vpfadd */ DoesNotAccessMemory,
			/* aarch64_neon_vpfaddq */ DoesNotAccessMemory,
			/* aarch64_neon_vpfmaxnm */ DoesNotAccessMemory,
			/* aarch64_neon_vpfmaxnmq */ DoesNotAccessMemory,
			/* aarch64_neon_vpfminnm */ DoesNotAccessMemory,
			/* aarch64_neon_vpfminnmq */ DoesNotAccessMemory,
			/* aarch64_neon_vpmax */ DoesNotAccessMemory,
			/* aarch64_neon_vpmaxnm */ DoesNotAccessMemory,
			/* aarch64_neon_vpmaxq */ DoesNotAccessMemory,
			/* aarch64_neon_vpmin */ DoesNotAccessMemory,
			/* aarch64_neon_vpminnm */ DoesNotAccessMemory,
			/* aarch64_neon_vpminq */ DoesNotAccessMemory,
			/* aarch64_neon_vqdmlal */ DoesNotAccessMemory,
			/* aarch64_neon_vqdmlsl */ DoesNotAccessMemory,
			/* aarch64_neon_vqrshls */ DoesNotAccessMemory,
			/* aarch64_neon_vqrshlu */ DoesNotAccessMemory,
			/* aarch64_neon_vqshls */ DoesNotAccessMemory,
			/* aarch64_neon_vqshls_n */ DoesNotAccessMemory,
			/* aarch64_neon_vqshlu */ DoesNotAccessMemory,
			/* aarch64_neon_vqshlu_n */ DoesNotAccessMemory,
			/* aarch64_neon_vqshlus_n */ DoesNotAccessMemory,
			/* aarch64_neon_vrecpx */ DoesNotAccessMemory,
			/* aarch64_neon_vrshlds */ DoesNotAccessMemory,
			/* aarch64_neon_vrshldu */ DoesNotAccessMemory,
			/* aarch64_neon_vrshrn */ DoesNotAccessMemory,
			/* aarch64_neon_vrsrads_n */ DoesNotAccessMemory,
			/* aarch64_neon_vrsradu_n */ DoesNotAccessMemory,
			/* aarch64_neon_vshld_n */ DoesNotAccessMemory,
			/* aarch64_neon_vshlds */ DoesNotAccessMemory,
			/* aarch64_neon_vshldu */ DoesNotAccessMemory,
			/* aarch64_neon_vshrds_n */ DoesNotAccessMemory,
			/* aarch64_neon_vshrdu_n */ DoesNotAccessMemory,
			/* aarch64_neon_vsli */ DoesNotAccessMemory,
			/* aarch64_neon_vsqadd */ DoesNotAccessMemory,
			/* aarch64_neon_vsqrshrn */ DoesNotAccessMemory,
			/* aarch64_neon_vsqrshrun */ DoesNotAccessMemory,
			/* aarch64_neon_vsqshlu */ DoesNotAccessMemory,
			/* aarch64_neon_vsqshrn */ DoesNotAccessMemory,
			/* aarch64_neon_vsqshrun */ DoesNotAccessMemory,
			/* aarch64_neon_vsrads_n */ DoesNotAccessMemory,
			/* aarch64_neon_vsradu_n */ DoesNotAccessMemory,
			/* aarch64_neon_vsri */ DoesNotAccessMemory,
			/* aarch64_neon_vsrshr */ DoesNotAccessMemory,
			/* aarch64_neon_vst1x2 */ OnlyAccessesArgumentPointees,
			/* aarch64_neon_vst1x3 */ OnlyAccessesArgumentPointees,
			/* aarch64_neon_vst1x4 */ OnlyAccessesArgumentPointees,
			/* aarch64_neon_vsubds */ DoesNotAccessMemory,
			/* aarch64_neon_vsubdu */ DoesNotAccessMemory,
			/* aarch64_neon_vtbl1 */ DoesNotAccessMemory,
			/* aarch64_neon_vtbl2 */ DoesNotAccessMemory,
			/* aarch64_neon_vtbl3 */ DoesNotAccessMemory,
			/* aarch64_neon_vtbl4 */ DoesNotAccessMemory,
			/* aarch64_neon_vtbx1 */ DoesNotAccessMemory,
			/* aarch64_neon_vtbx2 */ DoesNotAccessMemory,
			/* aarch64_neon_vtbx3 */ DoesNotAccessMemory,
			/* aarch64_neon_vtbx4 */ DoesNotAccessMemory,
			/* aarch64_neon_vtstd */ DoesNotAccessMemory,
			/* aarch64_neon_vuqadd */ DoesNotAccessMemory,
			/* aarch64_neon_vuqrshrn */ DoesNotAccessMemory,
			/* aarch64_neon_vuqshrn */ DoesNotAccessMemory,
			/* aarch64_neon_vurshr */ DoesNotAccessMemory,
			/* aarch64_neon_xtn */ DoesNotAccessMemory,
			/* adjust_trampoline */ OnlyReadsArgumentPointees,
			/* annotation */ UnknownModRefBehavior,
			/* arm_cdp */ UnknownModRefBehavior,
			/* arm_cdp2 */ UnknownModRefBehavior,
			/* arm_clrex */ UnknownModRefBehavior,
			/* arm_crc32b */ DoesNotAccessMemory,
			/* arm_crc32cb */ DoesNotAccessMemory,
			/* arm_crc32ch */ DoesNotAccessMemory,
			/* arm_crc32cw */ DoesNotAccessMemory,
			/* arm_crc32h */ DoesNotAccessMemory,
			/* arm_crc32w */ DoesNotAccessMemory,
			/* arm_dmb */ UnknownModRefBehavior,
			/* arm_dsb */ UnknownModRefBehavior,
			/* arm_get_fpscr */ DoesNotAccessMemory,
			/* arm_ldrex */ UnknownModRefBehavior,
			/* arm_ldrexd */ UnknownModRefBehavior,
			/* arm_mcr */ UnknownModRefBehavior,
			/* arm_mcr2 */ UnknownModRefBehavior,
			/* arm_mcrr */ UnknownModRefBehavior,
			/* arm_mcrr2 */ UnknownModRefBehavior,
			/* arm_mrc */ UnknownModRefBehavior,
			/* arm_mrc2 */ UnknownModRefBehavior,
			/* arm_neon_aesd */ DoesNotAccessMemory,
			/* arm_neon_aese */ DoesNotAccessMemory,
			/* arm_neon_aesimc */ DoesNotAccessMemory,
			/* arm_neon_aesmc */ DoesNotAccessMemory,
			/* arm_neon_sha1c */ DoesNotAccessMemory,
			/* arm_neon_sha1h */ DoesNotAccessMemory,
			/* arm_neon_sha1m */ DoesNotAccessMemory,
			/* arm_neon_sha1p */ DoesNotAccessMemory,
			/* arm_neon_sha1su0 */ DoesNotAccessMemory,
			/* arm_neon_sha1su1 */ DoesNotAccessMemory,
			/* arm_neon_sha256h */ DoesNotAccessMemory,
			/* arm_neon_sha256h2 */ DoesNotAccessMemory,
			/* arm_neon_sha256su0 */ DoesNotAccessMemory,
			/* arm_neon_sha256su1 */ DoesNotAccessMemory,
			/* arm_neon_vabds */ DoesNotAccessMemory,
			/* arm_neon_vabdu */ DoesNotAccessMemory,
			/* arm_neon_vabs */ DoesNotAccessMemory,
			/* arm_neon_vacged */ DoesNotAccessMemory,
			/* arm_neon_vacgeq */ DoesNotAccessMemory,
			/* arm_neon_vacgtd */ DoesNotAccessMemory,
			/* arm_neon_vacgtq */ DoesNotAccessMemory,
			/* arm_neon_vbsl */ DoesNotAccessMemory,
			/* arm_neon_vcls */ DoesNotAccessMemory,
			/* arm_neon_vclz */ DoesNotAccessMemory,
			/* arm_neon_vcnt */ DoesNotAccessMemory,
			/* arm_neon_vcvtas */ DoesNotAccessMemory,
			/* arm_neon_vcvtau */ DoesNotAccessMemory,
			/* arm_neon_vcvtfp2fxs */ DoesNotAccessMemory,
			/* arm_neon_vcvtfp2fxu */ DoesNotAccessMemory,
			/* arm_neon_vcvtfp2hf */ DoesNotAccessMemory,
			/* arm_neon_vcvtfxs2fp */ DoesNotAccessMemory,
			/* arm_neon_vcvtfxu2fp */ DoesNotAccessMemory,
			/* arm_neon_vcvthf2fp */ DoesNotAccessMemory,
			/* arm_neon_vcvtms */ DoesNotAccessMemory,
			/* arm_neon_vcvtmu */ DoesNotAccessMemory,
			/* arm_neon_vcvtns */ DoesNotAccessMemory,
			/* arm_neon_vcvtnu */ DoesNotAccessMemory,
			/* arm_neon_vcvtps */ DoesNotAccessMemory,
			/* arm_neon_vcvtpu */ DoesNotAccessMemory,
			/* arm_neon_vhadds */ DoesNotAccessMemory,
			/* arm_neon_vhaddu */ DoesNotAccessMemory,
			/* arm_neon_vhsubs */ DoesNotAccessMemory,
			/* arm_neon_vhsubu */ DoesNotAccessMemory,
			/* arm_neon_vld1 */ OnlyReadsArgumentPointees,
			/* arm_neon_vld2 */ OnlyReadsArgumentPointees,
			/* arm_neon_vld2lane */ OnlyReadsArgumentPointees,
			/* arm_neon_vld3 */ OnlyReadsArgumentPointees,
			/* arm_neon_vld3lane */ OnlyReadsArgumentPointees,
			/* arm_neon_vld4 */ OnlyReadsArgumentPointees,
			/* arm_neon_vld4lane */ OnlyReadsArgumentPointees,
			/* arm_neon_vmaxnm */ DoesNotAccessMemory,
			/* arm_neon_vmaxs */ DoesNotAccessMemory,
			/* arm_neon_vmaxu */ DoesNotAccessMemory,
			/* arm_neon_vminnm */ DoesNotAccessMemory,
			/* arm_neon_vmins */ DoesNotAccessMemory,
			/* arm_neon_vminu */ DoesNotAccessMemory,
			/* arm_neon_vmullp */ DoesNotAccessMemory,
			/* arm_neon_vmulls */ DoesNotAccessMemory,
			/* arm_neon_vmullu */ DoesNotAccessMemory,
			/* arm_neon_vmulp */ DoesNotAccessMemory,
			/* arm_neon_vpadals */ DoesNotAccessMemory,
			/* arm_neon_vpadalu */ DoesNotAccessMemory,
			/* arm_neon_vpadd */ DoesNotAccessMemory,
			/* arm_neon_vpaddls */ DoesNotAccessMemory,
			/* arm_neon_vpaddlu */ DoesNotAccessMemory,
			/* arm_neon_vpmaxs */ DoesNotAccessMemory,
			/* arm_neon_vpmaxu */ DoesNotAccessMemory,
			/* arm_neon_vpmins */ DoesNotAccessMemory,
			/* arm_neon_vpminu */ DoesNotAccessMemory,
			/* arm_neon_vqabs */ DoesNotAccessMemory,
			/* arm_neon_vqadds */ DoesNotAccessMemory,
			/* arm_neon_vqaddu */ DoesNotAccessMemory,
			/* arm_neon_vqdmulh */ DoesNotAccessMemory,
			/* arm_neon_vqdmull */ DoesNotAccessMemory,
			/* arm_neon_vqmovns */ DoesNotAccessMemory,
			/* arm_neon_vqmovnsu */ DoesNotAccessMemory,
			/* arm_neon_vqmovnu */ DoesNotAccessMemory,
			/* arm_neon_vqneg */ DoesNotAccessMemory,
			/* arm_neon_vqrdmulh */ DoesNotAccessMemory,
			/* arm_neon_vqrshiftns */ DoesNotAccessMemory,
			/* arm_neon_vqrshiftnsu */ DoesNotAccessMemory,
			/* arm_neon_vqrshiftnu */ DoesNotAccessMemory,
			/* arm_neon_vqrshifts */ DoesNotAccessMemory,
			/* arm_neon_vqrshiftu */ DoesNotAccessMemory,
			/* arm_neon_vqshiftns */ DoesNotAccessMemory,
			/* arm_neon_vqshiftnsu */ DoesNotAccessMemory,
			/* arm_neon_vqshiftnu */ DoesNotAccessMemory,
			/* arm_neon_vqshifts */ DoesNotAccessMemory,
			/* arm_neon_vqshiftsu */ DoesNotAccessMemory,
			/* arm_neon_vqshiftu */ DoesNotAccessMemory,
			/* arm_neon_vqsubs */ DoesNotAccessMemory,
			/* arm_neon_vqsubu */ DoesNotAccessMemory,
			/* arm_neon_vraddhn */ DoesNotAccessMemory,
			/* arm_neon_vrecpe */ DoesNotAccessMemory,
			/* arm_neon_vrecps */ DoesNotAccessMemory,
			/* arm_neon_vrhadds */ DoesNotAccessMemory,
			/* arm_neon_vrhaddu */ DoesNotAccessMemory,
			/* arm_neon_vrinta */ DoesNotAccessMemory,
			/* arm_neon_vrintm */ DoesNotAccessMemory,
			/* arm_neon_vrintn */ DoesNotAccessMemory,
			/* arm_neon_vrintp */ DoesNotAccessMemory,
			/* arm_neon_vrintx */ DoesNotAccessMemory,
			/* arm_neon_vrintz */ DoesNotAccessMemory,
			/* arm_neon_vrshiftn */ DoesNotAccessMemory,
			/* arm_neon_vrshifts */ DoesNotAccessMemory,
			/* arm_neon_vrshiftu */ DoesNotAccessMemory,
			/* arm_neon_vrsqrte */ DoesNotAccessMemory,
			/* arm_neon_vrsqrts */ DoesNotAccessMemory,
			/* arm_neon_vrsubhn */ DoesNotAccessMemory,
			/* arm_neon_vshiftins */ DoesNotAccessMemory,
			/* arm_neon_vshiftls */ DoesNotAccessMemory,
			/* arm_neon_vshiftlu */ DoesNotAccessMemory,
			/* arm_neon_vshiftn */ DoesNotAccessMemory,
			/* arm_neon_vshifts */ DoesNotAccessMemory,
			/* arm_neon_vshiftu */ DoesNotAccessMemory,
			/* arm_neon_vst1 */ OnlyAccessesArgumentPointees,
			/* arm_neon_vst2 */ OnlyAccessesArgumentPointees,
			/* arm_neon_vst2lane */ OnlyAccessesArgumentPointees,
			/* arm_neon_vst3 */ OnlyAccessesArgumentPointees,
			/* arm_neon_vst3lane */ OnlyAccessesArgumentPointees,
			/* arm_neon_vst4 */ OnlyAccessesArgumentPointees,
			/* arm_neon_vst4lane */ OnlyAccessesArgumentPointees,
			/* arm_neon_vtbl1 */ DoesNotAccessMemory,
			/* arm_neon_vtbl2 */ DoesNotAccessMemory,
			/* arm_neon_vtbl3 */ DoesNotAccessMemory,
			/* arm_neon_vtbl4 */ DoesNotAccessMemory,
			/* arm_neon_vtbx1 */ DoesNotAccessMemory,
			/* arm_neon_vtbx2 */ DoesNotAccessMemory,
			/* arm_neon_vtbx3 */ DoesNotAccessMemory,
			/* arm_neon_vtbx4 */ DoesNotAccessMemory,
			/* arm_qadd */ DoesNotAccessMemory,
			/* arm_qsub */ DoesNotAccessMemory,
			/* arm_set_fpscr */ UnknownModRefBehavior,
			/* arm_sevl */ UnknownModRefBehavior,
			/* arm_ssat */ DoesNotAccessMemory,
			/* arm_strex */ UnknownModRefBehavior,
			/* arm_strexd */ UnknownModRefBehavior,
			/* arm_thread_pointer */ DoesNotAccessMemory,
			/* arm_usat */ DoesNotAccessMemory,
			/* arm_vcvtr */ DoesNotAccessMemory,
			/* arm_vcvtru */ DoesNotAccessMemory,
			/* bswap */ DoesNotAccessMemory,
			/* ceil */ OnlyReadsMemory,
			/* convert_from_fp16 */ DoesNotAccessMemory,
			/* convert_to_fp16 */ DoesNotAccessMemory,
			/* convertff */ UnknownModRefBehavior,
			/* convertfsi */ UnknownModRefBehavior,
			/* convertfui */ UnknownModRefBehavior,
			/* convertsif */ UnknownModRefBehavior,
			/* convertss */ UnknownModRefBehavior,
			/* convertsu */ UnknownModRefBehavior,
			/* convertuif */ UnknownModRefBehavior,
			/* convertus */ UnknownModRefBehavior,
			/* convertuu */ UnknownModRefBehavior,
			/* copysign */ OnlyReadsMemory,
			/* cos */ OnlyReadsMemory,
			/* ctlz */ DoesNotAccessMemory,
			/* ctpop */ DoesNotAccessMemory,
			/* cttz */ DoesNotAccessMemory,
			/* cuda_syncthreads */ UnknownModRefBehavior,
			/* dbg_declare */ DoesNotAccessMemory,
			/* dbg_value */ DoesNotAccessMemory,
			/* debugtrap */ UnknownModRefBehavior,
			/* donothing */ DoesNotAccessMemory,
			/* eh_dwarf_cfa */ UnknownModRefBehavior,
			/* eh_return_i32 */ UnknownModRefBehavior,
			/* eh_return_i64 */ UnknownModRefBehavior,
			/* eh_sjlj_callsite */ DoesNotAccessMemory,
			/* eh_sjlj_functioncontext */ UnknownModRefBehavior,
			/* eh_sjlj_longjmp */ UnknownModRefBehavior,
			/* eh_sjlj_lsda */ DoesNotAccessMemory,
			/* eh_sjlj_setjmp */ UnknownModRefBehavior,
			/* eh_typeid_for */ DoesNotAccessMemory,
			/* eh_unwind_init */ UnknownModRefBehavior,
			/* exp */ OnlyReadsMemory,
			/* exp2 */ OnlyReadsMemory,
			/* expect */ DoesNotAccessMemory,
			/* experimental_patchpoint_i64 */ UnknownModRefBehavior,
			/* experimental_patchpoint_void */ UnknownModRefBehavior,
			/* experimental_stackmap */ UnknownModRefBehavior,
			/* fabs */ OnlyReadsMemory,
			/* floor */ OnlyReadsMemory,
			/* flt_rounds */ UnknownModRefBehavior,
			/* fma */ DoesNotAccessMemory,
			/* fmuladd */ DoesNotAccessMemory,
			/* frameaddress */ DoesNotAccessMemory,
			/* gcread */ OnlyReadsArgumentPointees,
			/* gcroot */ UnknownModRefBehavior,
			/* gcwrite */ OnlyAccessesArgumentPointees,
			/* hexagon_A2_abs */ DoesNotAccessMemory,
			/* hexagon_A2_absp */ DoesNotAccessMemory,
			/* hexagon_A2_abssat */ DoesNotAccessMemory,
			/* hexagon_A2_add */ DoesNotAccessMemory,
			/* hexagon_A2_addh_h16_hh */ DoesNotAccessMemory,
	/* hexagon_A2_addh_h16_hl */ DoesNotAccessMemory,		/* hexagon_A2_addh_h16_hl */ DoesNotAccessMemory,
	/* hexagon_A2_addh_h16_lh */ DoesNotAccessMemory,		/* hexagon_A2_addh_h16_lh */ DoesNotAccessMemory,
	/* hexagon_A2_addh_h16_ll */ DoesNotAccessMemory,		/* hexagon_A2_addh_h16_ll */ DoesNotAccessMemory,
	/* hexagon_A2_addh_h16_sat_hh */ DoesNotAccessMemory,		/* hexagon_A2_addh_h16_sat_hh */ DoesNotAccessMemory,
	/* hexagon_A2_addh_h16_sat_hl */ DoesNotAccessMemory,		/* hexagon_A2_addh_h16_sat_hl */ DoesNotAccessMemory,
	/* hexagon_A2_addh_h16_sat_lh */ DoesNotAccessMemory,		/* hexagon_A2_addh_h16_sat_lh */ DoesNotAccessMemory,
	/* hexagon_A2_addh_h16_sat_ll */ DoesNotAccessMemory,		/* hexagon_A2_addh_h16_sat_ll */ DoesNotAccessMemory,
	/* hexagon_A2_addh_l16_hl */ DoesNotAccessMemory,		/* hexagon_A2_addh_l16_hl */ DoesNotAccessMemory,
	/* hexagon_A2_addh_l16_ll */ DoesNotAccessMemory,		/* hexagon_A2_addh_l16_ll */ DoesNotAccessMemory,
	/* hexagon_A2_addh_l16_sat_hl */ DoesNotAccessMemory,		/* hexagon_A2_addh_l16_sat_hl */ DoesNotAccessMemory,
	skipping to change at line 25972		skipping to change at line 33411
	/* log */ OnlyReadsMemory,		/* log */ OnlyReadsMemory,
	/* log10 */ OnlyReadsMemory,		/* log10 */ OnlyReadsMemory,
	/* log2 */ OnlyReadsMemory,		/* log2 */ OnlyReadsMemory,
	/* longjmp */ UnknownModRefBehavior,		/* longjmp */ UnknownModRefBehavior,
	/* memcpy */ OnlyAccessesArgumentPointees,		/* memcpy */ OnlyAccessesArgumentPointees,
	/* memmove */ OnlyAccessesArgumentPointees,		/* memmove */ OnlyAccessesArgumentPointees,
	/* memset */ OnlyAccessesArgumentPointees,		/* memset */ OnlyAccessesArgumentPointees,
	/* mips_absq_s_ph */ UnknownModRefBehavior,		/* mips_absq_s_ph */ UnknownModRefBehavior,
	/* mips_absq_s_qb */ UnknownModRefBehavior,		/* mips_absq_s_qb */ UnknownModRefBehavior,
	/* mips_absq_s_w */ UnknownModRefBehavior,		/* mips_absq_s_w */ UnknownModRefBehavior,
			/* mips_add_a_b */ DoesNotAccessMemory,
			/* mips_add_a_d */ DoesNotAccessMemory,
			/* mips_add_a_h */ DoesNotAccessMemory,
			/* mips_add_a_w */ DoesNotAccessMemory,
	/* mips_addq_ph */ UnknownModRefBehavior,		/* mips_addq_ph */ UnknownModRefBehavior,
	/* mips_addq_s_ph */ UnknownModRefBehavior,		/* mips_addq_s_ph */ UnknownModRefBehavior,
	/* mips_addq_s_w */ UnknownModRefBehavior,		/* mips_addq_s_w */ UnknownModRefBehavior,
	/* mips_addqh_ph */ DoesNotAccessMemory,		/* mips_addqh_ph */ DoesNotAccessMemory,
	/* mips_addqh_r_ph */ DoesNotAccessMemory,		/* mips_addqh_r_ph */ DoesNotAccessMemory,
	/* mips_addqh_r_w */ DoesNotAccessMemory,		/* mips_addqh_r_w */ DoesNotAccessMemory,
	/* mips_addqh_w */ DoesNotAccessMemory,		/* mips_addqh_w */ DoesNotAccessMemory,
			/* mips_adds_a_b */ DoesNotAccessMemory,
			/* mips_adds_a_d */ DoesNotAccessMemory,
			/* mips_adds_a_h */ DoesNotAccessMemory,
			/* mips_adds_a_w */ DoesNotAccessMemory,
			/* mips_adds_s_b */ DoesNotAccessMemory,
			/* mips_adds_s_d */ DoesNotAccessMemory,
			/* mips_adds_s_h */ DoesNotAccessMemory,
			/* mips_adds_s_w */ DoesNotAccessMemory,
			/* mips_adds_u_b */ DoesNotAccessMemory,
			/* mips_adds_u_d */ DoesNotAccessMemory,
			/* mips_adds_u_h */ DoesNotAccessMemory,
			/* mips_adds_u_w */ DoesNotAccessMemory,
	/* mips_addsc */ UnknownModRefBehavior,		/* mips_addsc */ UnknownModRefBehavior,
	/* mips_addu_ph */ UnknownModRefBehavior,		/* mips_addu_ph */ UnknownModRefBehavior,
	/* mips_addu_qb */ UnknownModRefBehavior,		/* mips_addu_qb */ UnknownModRefBehavior,
	/* mips_addu_s_ph */ UnknownModRefBehavior,		/* mips_addu_s_ph */ UnknownModRefBehavior,
	/* mips_addu_s_qb */ UnknownModRefBehavior,		/* mips_addu_s_qb */ UnknownModRefBehavior,
	/* mips_adduh_qb */ DoesNotAccessMemory,		/* mips_adduh_qb */ DoesNotAccessMemory,
	/* mips_adduh_r_qb */ DoesNotAccessMemory,		/* mips_adduh_r_qb */ DoesNotAccessMemory,
			/* mips_addv_b */ DoesNotAccessMemory,
			/* mips_addv_d */ DoesNotAccessMemory,
			/* mips_addv_h */ DoesNotAccessMemory,
			/* mips_addv_w */ DoesNotAccessMemory,
			/* mips_addvi_b */ DoesNotAccessMemory,
			/* mips_addvi_d */ DoesNotAccessMemory,
			/* mips_addvi_h */ DoesNotAccessMemory,
			/* mips_addvi_w */ DoesNotAccessMemory,
	/* mips_addwc */ UnknownModRefBehavior,		/* mips_addwc */ UnknownModRefBehavior,
			/* mips_and_v */ DoesNotAccessMemory,
			/* mips_andi_b */ DoesNotAccessMemory,
	/* mips_append */ DoesNotAccessMemory,		/* mips_append */ DoesNotAccessMemory,
			/* mips_asub_s_b */ DoesNotAccessMemory,
			/* mips_asub_s_d */ DoesNotAccessMemory,
			/* mips_asub_s_h */ DoesNotAccessMemory,
			/* mips_asub_s_w */ DoesNotAccessMemory,
			/* mips_asub_u_b */ DoesNotAccessMemory,
			/* mips_asub_u_d */ DoesNotAccessMemory,
			/* mips_asub_u_h */ DoesNotAccessMemory,
			/* mips_asub_u_w */ DoesNotAccessMemory,
			/* mips_ave_s_b */ DoesNotAccessMemory,
			/* mips_ave_s_d */ DoesNotAccessMemory,
			/* mips_ave_s_h */ DoesNotAccessMemory,
			/* mips_ave_s_w */ DoesNotAccessMemory,
			/* mips_ave_u_b */ DoesNotAccessMemory,
			/* mips_ave_u_d */ DoesNotAccessMemory,
			/* mips_ave_u_h */ DoesNotAccessMemory,
			/* mips_ave_u_w */ DoesNotAccessMemory,
			/* mips_aver_s_b */ DoesNotAccessMemory,
			/* mips_aver_s_d */ DoesNotAccessMemory,
			/* mips_aver_s_h */ DoesNotAccessMemory,
			/* mips_aver_s_w */ DoesNotAccessMemory,
			/* mips_aver_u_b */ DoesNotAccessMemory,
			/* mips_aver_u_d */ DoesNotAccessMemory,
			/* mips_aver_u_h */ DoesNotAccessMemory,
			/* mips_aver_u_w */ DoesNotAccessMemory,
	/* mips_balign */ DoesNotAccessMemory,		/* mips_balign */ DoesNotAccessMemory,
			/* mips_bclr_b */ DoesNotAccessMemory,
			/* mips_bclr_d */ DoesNotAccessMemory,
			/* mips_bclr_h */ DoesNotAccessMemory,
			/* mips_bclr_w */ DoesNotAccessMemory,
			/* mips_bclri_b */ DoesNotAccessMemory,
			/* mips_bclri_d */ DoesNotAccessMemory,
			/* mips_bclri_h */ DoesNotAccessMemory,
			/* mips_bclri_w */ DoesNotAccessMemory,
			/* mips_binsl_b */ DoesNotAccessMemory,
			/* mips_binsl_d */ DoesNotAccessMemory,
			/* mips_binsl_h */ DoesNotAccessMemory,
			/* mips_binsl_w */ DoesNotAccessMemory,
			/* mips_binsli_b */ DoesNotAccessMemory,
			/* mips_binsli_d */ DoesNotAccessMemory,
			/* mips_binsli_h */ DoesNotAccessMemory,
			/* mips_binsli_w */ DoesNotAccessMemory,
			/* mips_binsr_b */ DoesNotAccessMemory,
			/* mips_binsr_d */ DoesNotAccessMemory,
			/* mips_binsr_h */ DoesNotAccessMemory,
			/* mips_binsr_w */ DoesNotAccessMemory,
			/* mips_binsri_b */ DoesNotAccessMemory,
			/* mips_binsri_d */ DoesNotAccessMemory,
			/* mips_binsri_h */ DoesNotAccessMemory,
			/* mips_binsri_w */ DoesNotAccessMemory,
	/* mips_bitrev */ DoesNotAccessMemory,		/* mips_bitrev */ DoesNotAccessMemory,
			/* mips_bmnz_v */ DoesNotAccessMemory,
			/* mips_bmnzi_b */ DoesNotAccessMemory,
			/* mips_bmz_v */ DoesNotAccessMemory,
			/* mips_bmzi_b */ DoesNotAccessMemory,
			/* mips_bneg_b */ DoesNotAccessMemory,
			/* mips_bneg_d */ DoesNotAccessMemory,
			/* mips_bneg_h */ DoesNotAccessMemory,
			/* mips_bneg_w */ DoesNotAccessMemory,
			/* mips_bnegi_b */ DoesNotAccessMemory,
			/* mips_bnegi_d */ DoesNotAccessMemory,
			/* mips_bnegi_h */ DoesNotAccessMemory,
			/* mips_bnegi_w */ DoesNotAccessMemory,
			/* mips_bnz_b */ DoesNotAccessMemory,
			/* mips_bnz_d */ DoesNotAccessMemory,
			/* mips_bnz_h */ DoesNotAccessMemory,
			/* mips_bnz_v */ DoesNotAccessMemory,
			/* mips_bnz_w */ DoesNotAccessMemory,
	/* mips_bposge32 */ OnlyReadsMemory,		/* mips_bposge32 */ OnlyReadsMemory,
			/* mips_bsel_v */ DoesNotAccessMemory,
			/* mips_bseli_b */ DoesNotAccessMemory,
			/* mips_bset_b */ DoesNotAccessMemory,
			/* mips_bset_d */ DoesNotAccessMemory,
			/* mips_bset_h */ DoesNotAccessMemory,
			/* mips_bset_w */ DoesNotAccessMemory,
			/* mips_bseti_b */ DoesNotAccessMemory,
			/* mips_bseti_d */ DoesNotAccessMemory,
			/* mips_bseti_h */ DoesNotAccessMemory,
			/* mips_bseti_w */ DoesNotAccessMemory,
			/* mips_bz_b */ DoesNotAccessMemory,
			/* mips_bz_d */ DoesNotAccessMemory,
			/* mips_bz_h */ DoesNotAccessMemory,
			/* mips_bz_v */ DoesNotAccessMemory,
			/* mips_bz_w */ DoesNotAccessMemory,
			/* mips_ceq_b */ DoesNotAccessMemory,
			/* mips_ceq_d */ DoesNotAccessMemory,
			/* mips_ceq_h */ DoesNotAccessMemory,
			/* mips_ceq_w */ DoesNotAccessMemory,
			/* mips_ceqi_b */ DoesNotAccessMemory,
			/* mips_ceqi_d */ DoesNotAccessMemory,
			/* mips_ceqi_h */ DoesNotAccessMemory,
			/* mips_ceqi_w */ DoesNotAccessMemory,
			/* mips_cfcmsa */ UnknownModRefBehavior,
			/* mips_cle_s_b */ DoesNotAccessMemory,
			/* mips_cle_s_d */ DoesNotAccessMemory,
			/* mips_cle_s_h */ DoesNotAccessMemory,
			/* mips_cle_s_w */ DoesNotAccessMemory,
			/* mips_cle_u_b */ DoesNotAccessMemory,
			/* mips_cle_u_d */ DoesNotAccessMemory,
			/* mips_cle_u_h */ DoesNotAccessMemory,
			/* mips_cle_u_w */ DoesNotAccessMemory,
			/* mips_clei_s_b */ DoesNotAccessMemory,
			/* mips_clei_s_d */ DoesNotAccessMemory,
			/* mips_clei_s_h */ DoesNotAccessMemory,
			/* mips_clei_s_w */ DoesNotAccessMemory,
			/* mips_clei_u_b */ DoesNotAccessMemory,
			/* mips_clei_u_d */ DoesNotAccessMemory,
			/* mips_clei_u_h */ DoesNotAccessMemory,
			/* mips_clei_u_w */ DoesNotAccessMemory,
			/* mips_clt_s_b */ DoesNotAccessMemory,
			/* mips_clt_s_d */ DoesNotAccessMemory,
			/* mips_clt_s_h */ DoesNotAccessMemory,
			/* mips_clt_s_w */ DoesNotAccessMemory,
			/* mips_clt_u_b */ DoesNotAccessMemory,
			/* mips_clt_u_d */ DoesNotAccessMemory,
			/* mips_clt_u_h */ DoesNotAccessMemory,
			/* mips_clt_u_w */ DoesNotAccessMemory,
			/* mips_clti_s_b */ DoesNotAccessMemory,
			/* mips_clti_s_d */ DoesNotAccessMemory,
			/* mips_clti_s_h */ DoesNotAccessMemory,
			/* mips_clti_s_w */ DoesNotAccessMemory,
			/* mips_clti_u_b */ DoesNotAccessMemory,
			/* mips_clti_u_d */ DoesNotAccessMemory,
			/* mips_clti_u_h */ DoesNotAccessMemory,
			/* mips_clti_u_w */ DoesNotAccessMemory,
	/* mips_cmp_eq_ph */ UnknownModRefBehavior,		/* mips_cmp_eq_ph */ UnknownModRefBehavior,
	/* mips_cmp_le_ph */ UnknownModRefBehavior,		/* mips_cmp_le_ph */ UnknownModRefBehavior,
	/* mips_cmp_lt_ph */ UnknownModRefBehavior,		/* mips_cmp_lt_ph */ UnknownModRefBehavior,
	/* mips_cmpgdu_eq_qb */ UnknownModRefBehavior,		/* mips_cmpgdu_eq_qb */ UnknownModRefBehavior,
	/* mips_cmpgdu_le_qb */ UnknownModRefBehavior,		/* mips_cmpgdu_le_qb */ UnknownModRefBehavior,
	/* mips_cmpgdu_lt_qb */ UnknownModRefBehavior,		/* mips_cmpgdu_lt_qb */ UnknownModRefBehavior,
	/* mips_cmpgu_eq_qb */ UnknownModRefBehavior,		/* mips_cmpgu_eq_qb */ UnknownModRefBehavior,
	/* mips_cmpgu_le_qb */ UnknownModRefBehavior,		/* mips_cmpgu_le_qb */ UnknownModRefBehavior,
	/* mips_cmpgu_lt_qb */ UnknownModRefBehavior,		/* mips_cmpgu_lt_qb */ UnknownModRefBehavior,
	/* mips_cmpu_eq_qb */ UnknownModRefBehavior,		/* mips_cmpu_eq_qb */ UnknownModRefBehavior,
	/* mips_cmpu_le_qb */ UnknownModRefBehavior,		/* mips_cmpu_le_qb */ UnknownModRefBehavior,
	/* mips_cmpu_lt_qb */ UnknownModRefBehavior,		/* mips_cmpu_lt_qb */ UnknownModRefBehavior,
			/* mips_copy_s_b */ DoesNotAccessMemory,
			/* mips_copy_s_d */ DoesNotAccessMemory,
			/* mips_copy_s_h */ DoesNotAccessMemory,
			/* mips_copy_s_w */ DoesNotAccessMemory,
			/* mips_copy_u_b */ DoesNotAccessMemory,
			/* mips_copy_u_d */ DoesNotAccessMemory,
			/* mips_copy_u_h */ DoesNotAccessMemory,
			/* mips_copy_u_w */ DoesNotAccessMemory,
			/* mips_ctcmsa */ UnknownModRefBehavior,
			/* mips_div_s_b */ DoesNotAccessMemory,
			/* mips_div_s_d */ DoesNotAccessMemory,
			/* mips_div_s_h */ DoesNotAccessMemory,
			/* mips_div_s_w */ DoesNotAccessMemory,
			/* mips_div_u_b */ DoesNotAccessMemory,
			/* mips_div_u_d */ DoesNotAccessMemory,
			/* mips_div_u_h */ DoesNotAccessMemory,
			/* mips_div_u_w */ DoesNotAccessMemory,
			/* mips_dotp_s_d */ DoesNotAccessMemory,
			/* mips_dotp_s_h */ DoesNotAccessMemory,
			/* mips_dotp_s_w */ DoesNotAccessMemory,
			/* mips_dotp_u_d */ DoesNotAccessMemory,
			/* mips_dotp_u_h */ DoesNotAccessMemory,
			/* mips_dotp_u_w */ DoesNotAccessMemory,
	/* mips_dpa_w_ph */ DoesNotAccessMemory,		/* mips_dpa_w_ph */ DoesNotAccessMemory,
			/* mips_dpadd_s_d */ DoesNotAccessMemory,
			/* mips_dpadd_s_h */ DoesNotAccessMemory,
			/* mips_dpadd_s_w */ DoesNotAccessMemory,
			/* mips_dpadd_u_d */ DoesNotAccessMemory,
			/* mips_dpadd_u_h */ DoesNotAccessMemory,
			/* mips_dpadd_u_w */ DoesNotAccessMemory,
	/* mips_dpaq_s_w_ph */ UnknownModRefBehavior,		/* mips_dpaq_s_w_ph */ UnknownModRefBehavior,
	/* mips_dpaq_sa_l_w */ UnknownModRefBehavior,		/* mips_dpaq_sa_l_w */ UnknownModRefBehavior,
	/* mips_dpaqx_s_w_ph */ UnknownModRefBehavior,		/* mips_dpaqx_s_w_ph */ UnknownModRefBehavior,
	/* mips_dpaqx_sa_w_ph */ UnknownModRefBehavior,		/* mips_dpaqx_sa_w_ph */ UnknownModRefBehavior,
	/* mips_dpau_h_qbl */ DoesNotAccessMemory,		/* mips_dpau_h_qbl */ DoesNotAccessMemory,
	/* mips_dpau_h_qbr */ DoesNotAccessMemory,		/* mips_dpau_h_qbr */ DoesNotAccessMemory,
	/* mips_dpax_w_ph */ DoesNotAccessMemory,		/* mips_dpax_w_ph */ DoesNotAccessMemory,
	/* mips_dps_w_ph */ DoesNotAccessMemory,		/* mips_dps_w_ph */ DoesNotAccessMemory,
	/* mips_dpsq_s_w_ph */ UnknownModRefBehavior,		/* mips_dpsq_s_w_ph */ UnknownModRefBehavior,
	/* mips_dpsq_sa_l_w */ UnknownModRefBehavior,		/* mips_dpsq_sa_l_w */ UnknownModRefBehavior,
	/* mips_dpsqx_s_w_ph */ UnknownModRefBehavior,		/* mips_dpsqx_s_w_ph */ UnknownModRefBehavior,
	/* mips_dpsqx_sa_w_ph */ UnknownModRefBehavior,		/* mips_dpsqx_sa_w_ph */ UnknownModRefBehavior,
	/* mips_dpsu_h_qbl */ DoesNotAccessMemory,		/* mips_dpsu_h_qbl */ DoesNotAccessMemory,
	/* mips_dpsu_h_qbr */ DoesNotAccessMemory,		/* mips_dpsu_h_qbr */ DoesNotAccessMemory,
			/* mips_dpsub_s_d */ DoesNotAccessMemory,
			/* mips_dpsub_s_h */ DoesNotAccessMemory,
			/* mips_dpsub_s_w */ DoesNotAccessMemory,
			/* mips_dpsub_u_d */ DoesNotAccessMemory,
			/* mips_dpsub_u_h */ DoesNotAccessMemory,
			/* mips_dpsub_u_w */ DoesNotAccessMemory,
	/* mips_dpsx_w_ph */ DoesNotAccessMemory,		/* mips_dpsx_w_ph */ DoesNotAccessMemory,
	/* mips_extp */ UnknownModRefBehavior,		/* mips_extp */ UnknownModRefBehavior,
	/* mips_extpdp */ UnknownModRefBehavior,		/* mips_extpdp */ UnknownModRefBehavior,
	/* mips_extr_r_w */ UnknownModRefBehavior,		/* mips_extr_r_w */ UnknownModRefBehavior,
	/* mips_extr_rs_w */ UnknownModRefBehavior,		/* mips_extr_rs_w */ UnknownModRefBehavior,
	/* mips_extr_s_h */ UnknownModRefBehavior,		/* mips_extr_s_h */ UnknownModRefBehavior,
	/* mips_extr_w */ UnknownModRefBehavior,		/* mips_extr_w */ UnknownModRefBehavior,
			/* mips_fadd_d */ DoesNotAccessMemory,
			/* mips_fadd_w */ DoesNotAccessMemory,
			/* mips_fcaf_d */ DoesNotAccessMemory,
			/* mips_fcaf_w */ DoesNotAccessMemory,
			/* mips_fceq_d */ DoesNotAccessMemory,
			/* mips_fceq_w */ DoesNotAccessMemory,
			/* mips_fclass_d */ DoesNotAccessMemory,
			/* mips_fclass_w */ DoesNotAccessMemory,
			/* mips_fcle_d */ DoesNotAccessMemory,
			/* mips_fcle_w */ DoesNotAccessMemory,
			/* mips_fclt_d */ DoesNotAccessMemory,
			/* mips_fclt_w */ DoesNotAccessMemory,
			/* mips_fcne_d */ DoesNotAccessMemory,
			/* mips_fcne_w */ DoesNotAccessMemory,
			/* mips_fcor_d */ DoesNotAccessMemory,
			/* mips_fcor_w */ DoesNotAccessMemory,
			/* mips_fcueq_d */ DoesNotAccessMemory,
			/* mips_fcueq_w */ DoesNotAccessMemory,
			/* mips_fcule_d */ DoesNotAccessMemory,
			/* mips_fcule_w */ DoesNotAccessMemory,
			/* mips_fcult_d */ DoesNotAccessMemory,
			/* mips_fcult_w */ DoesNotAccessMemory,
			/* mips_fcun_d */ DoesNotAccessMemory,
			/* mips_fcun_w */ DoesNotAccessMemory,
			/* mips_fcune_d */ DoesNotAccessMemory,
			/* mips_fcune_w */ DoesNotAccessMemory,
			/* mips_fdiv_d */ DoesNotAccessMemory,
			/* mips_fdiv_w */ DoesNotAccessMemory,
			/* mips_fexdo_h */ DoesNotAccessMemory,
			/* mips_fexdo_w */ DoesNotAccessMemory,
			/* mips_fexp2_d */ DoesNotAccessMemory,
			/* mips_fexp2_w */ DoesNotAccessMemory,
			/* mips_fexupl_d */ DoesNotAccessMemory,
			/* mips_fexupl_w */ DoesNotAccessMemory,
			/* mips_fexupr_d */ DoesNotAccessMemory,
			/* mips_fexupr_w */ DoesNotAccessMemory,
			/* mips_ffint_s_d */ DoesNotAccessMemory,
			/* mips_ffint_s_w */ DoesNotAccessMemory,
			/* mips_ffint_u_d */ DoesNotAccessMemory,
			/* mips_ffint_u_w */ DoesNotAccessMemory,
			/* mips_ffql_d */ DoesNotAccessMemory,
			/* mips_ffql_w */ DoesNotAccessMemory,
			/* mips_ffqr_d */ DoesNotAccessMemory,
			/* mips_ffqr_w */ DoesNotAccessMemory,
			/* mips_fill_b */ DoesNotAccessMemory,
			/* mips_fill_d */ DoesNotAccessMemory,
			/* mips_fill_h */ DoesNotAccessMemory,
			/* mips_fill_w */ DoesNotAccessMemory,
			/* mips_flog2_d */ DoesNotAccessMemory,
			/* mips_flog2_w */ DoesNotAccessMemory,
			/* mips_fmadd_d */ DoesNotAccessMemory,
			/* mips_fmadd_w */ DoesNotAccessMemory,
			/* mips_fmax_a_d */ DoesNotAccessMemory,
			/* mips_fmax_a_w */ DoesNotAccessMemory,
			/* mips_fmax_d */ DoesNotAccessMemory,
			/* mips_fmax_w */ DoesNotAccessMemory,
			/* mips_fmin_a_d */ DoesNotAccessMemory,
			/* mips_fmin_a_w */ DoesNotAccessMemory,
			/* mips_fmin_d */ DoesNotAccessMemory,
			/* mips_fmin_w */ DoesNotAccessMemory,
			/* mips_fmsub_d */ DoesNotAccessMemory,
			/* mips_fmsub_w */ DoesNotAccessMemory,
			/* mips_fmul_d */ DoesNotAccessMemory,
			/* mips_fmul_w */ DoesNotAccessMemory,
			/* mips_frcp_d */ DoesNotAccessMemory,
			/* mips_frcp_w */ DoesNotAccessMemory,
			/* mips_frint_d */ DoesNotAccessMemory,
			/* mips_frint_w */ DoesNotAccessMemory,
			/* mips_frsqrt_d */ DoesNotAccessMemory,
			/* mips_frsqrt_w */ DoesNotAccessMemory,
			/* mips_fsaf_d */ DoesNotAccessMemory,
			/* mips_fsaf_w */ DoesNotAccessMemory,
			/* mips_fseq_d */ DoesNotAccessMemory,
			/* mips_fseq_w */ DoesNotAccessMemory,
			/* mips_fsle_d */ DoesNotAccessMemory,
			/* mips_fsle_w */ DoesNotAccessMemory,
			/* mips_fslt_d */ DoesNotAccessMemory,
			/* mips_fslt_w */ DoesNotAccessMemory,
			/* mips_fsne_d */ DoesNotAccessMemory,
			/* mips_fsne_w */ DoesNotAccessMemory,
			/* mips_fsor_d */ DoesNotAccessMemory,
			/* mips_fsor_w */ DoesNotAccessMemory,
			/* mips_fsqrt_d */ DoesNotAccessMemory,
			/* mips_fsqrt_w */ DoesNotAccessMemory,
			/* mips_fsub_d */ DoesNotAccessMemory,
			/* mips_fsub_w */ DoesNotAccessMemory,
			/* mips_fsueq_d */ DoesNotAccessMemory,
			/* mips_fsueq_w */ DoesNotAccessMemory,
			/* mips_fsule_d */ DoesNotAccessMemory,
			/* mips_fsule_w */ DoesNotAccessMemory,
			/* mips_fsult_d */ DoesNotAccessMemory,
			/* mips_fsult_w */ DoesNotAccessMemory,
			/* mips_fsun_d */ DoesNotAccessMemory,
			/* mips_fsun_w */ DoesNotAccessMemory,
			/* mips_fsune_d */ DoesNotAccessMemory,
			/* mips_fsune_w */ DoesNotAccessMemory,
			/* mips_ftint_s_d */ DoesNotAccessMemory,
			/* mips_ftint_s_w */ DoesNotAccessMemory,
			/* mips_ftint_u_d */ DoesNotAccessMemory,
			/* mips_ftint_u_w */ DoesNotAccessMemory,
			/* mips_ftq_h */ DoesNotAccessMemory,
			/* mips_ftq_w */ DoesNotAccessMemory,
			/* mips_ftrunc_s_d */ DoesNotAccessMemory,
			/* mips_ftrunc_s_w */ DoesNotAccessMemory,
			/* mips_ftrunc_u_d */ DoesNotAccessMemory,
			/* mips_ftrunc_u_w */ DoesNotAccessMemory,
			/* mips_hadd_s_d */ DoesNotAccessMemory,
			/* mips_hadd_s_h */ DoesNotAccessMemory,
			/* mips_hadd_s_w */ DoesNotAccessMemory,
			/* mips_hadd_u_d */ DoesNotAccessMemory,
			/* mips_hadd_u_h */ DoesNotAccessMemory,
			/* mips_hadd_u_w */ DoesNotAccessMemory,
			/* mips_hsub_s_d */ DoesNotAccessMemory,
			/* mips_hsub_s_h */ DoesNotAccessMemory,
			/* mips_hsub_s_w */ DoesNotAccessMemory,
			/* mips_hsub_u_d */ DoesNotAccessMemory,
			/* mips_hsub_u_h */ DoesNotAccessMemory,
			/* mips_hsub_u_w */ DoesNotAccessMemory,
			/* mips_ilvev_b */ DoesNotAccessMemory,
			/* mips_ilvev_d */ DoesNotAccessMemory,
			/* mips_ilvev_h */ DoesNotAccessMemory,
			/* mips_ilvev_w */ DoesNotAccessMemory,
			/* mips_ilvl_b */ DoesNotAccessMemory,
			/* mips_ilvl_d */ DoesNotAccessMemory,
			/* mips_ilvl_h */ DoesNotAccessMemory,
			/* mips_ilvl_w */ DoesNotAccessMemory,
			/* mips_ilvod_b */ DoesNotAccessMemory,
			/* mips_ilvod_d */ DoesNotAccessMemory,
			/* mips_ilvod_h */ DoesNotAccessMemory,
			/* mips_ilvod_w */ DoesNotAccessMemory,
			/* mips_ilvr_b */ DoesNotAccessMemory,
			/* mips_ilvr_d */ DoesNotAccessMemory,
			/* mips_ilvr_h */ DoesNotAccessMemory,
			/* mips_ilvr_w */ DoesNotAccessMemory,
			/* mips_insert_b */ DoesNotAccessMemory,
			/* mips_insert_d */ DoesNotAccessMemory,
			/* mips_insert_h */ DoesNotAccessMemory,
			/* mips_insert_w */ DoesNotAccessMemory,
	/* mips_insv */ OnlyReadsMemory,		/* mips_insv */ OnlyReadsMemory,
			/* mips_insve_b */ DoesNotAccessMemory,
			/* mips_insve_d */ DoesNotAccessMemory,
			/* mips_insve_h */ DoesNotAccessMemory,
			/* mips_insve_w */ DoesNotAccessMemory,
	/* mips_lbux */ OnlyReadsArgumentPointees,		/* mips_lbux */ OnlyReadsArgumentPointees,
			/* mips_ld_b */ OnlyReadsArgumentPointees,
			/* mips_ld_d */ OnlyReadsArgumentPointees,
			/* mips_ld_h */ OnlyReadsArgumentPointees,
			/* mips_ld_w */ OnlyReadsArgumentPointees,
			/* mips_ldi_b */ DoesNotAccessMemory,
			/* mips_ldi_d */ DoesNotAccessMemory,
			/* mips_ldi_h */ DoesNotAccessMemory,
			/* mips_ldi_w */ DoesNotAccessMemory,
	/* mips_lhx */ OnlyReadsArgumentPointees,		/* mips_lhx */ OnlyReadsArgumentPointees,
			/* mips_lsa */ DoesNotAccessMemory,
	/* mips_lwx */ OnlyReadsArgumentPointees,		/* mips_lwx */ OnlyReadsArgumentPointees,
	/* mips_madd */ DoesNotAccessMemory,		/* mips_madd */ DoesNotAccessMemory,
			/* mips_madd_q_h */ DoesNotAccessMemory,
			/* mips_madd_q_w */ DoesNotAccessMemory,
			/* mips_maddr_q_h */ DoesNotAccessMemory,
			/* mips_maddr_q_w */ DoesNotAccessMemory,
	/* mips_maddu */ DoesNotAccessMemory,		/* mips_maddu */ DoesNotAccessMemory,
			/* mips_maddv_b */ DoesNotAccessMemory,
			/* mips_maddv_d */ DoesNotAccessMemory,
			/* mips_maddv_h */ DoesNotAccessMemory,
			/* mips_maddv_w */ DoesNotAccessMemory,
	/* mips_maq_s_w_phl */ UnknownModRefBehavior,		/* mips_maq_s_w_phl */ UnknownModRefBehavior,
	/* mips_maq_s_w_phr */ UnknownModRefBehavior,		/* mips_maq_s_w_phr */ UnknownModRefBehavior,
	/* mips_maq_sa_w_phl */ UnknownModRefBehavior,		/* mips_maq_sa_w_phl */ UnknownModRefBehavior,
	/* mips_maq_sa_w_phr */ UnknownModRefBehavior,		/* mips_maq_sa_w_phr */ UnknownModRefBehavior,
			/* mips_max_a_b */ DoesNotAccessMemory,
			/* mips_max_a_d */ DoesNotAccessMemory,
			/* mips_max_a_h */ DoesNotAccessMemory,
			/* mips_max_a_w */ DoesNotAccessMemory,
			/* mips_max_s_b */ DoesNotAccessMemory,
			/* mips_max_s_d */ DoesNotAccessMemory,
			/* mips_max_s_h */ DoesNotAccessMemory,
			/* mips_max_s_w */ DoesNotAccessMemory,
			/* mips_max_u_b */ DoesNotAccessMemory,
			/* mips_max_u_d */ DoesNotAccessMemory,
			/* mips_max_u_h */ DoesNotAccessMemory,
			/* mips_max_u_w */ DoesNotAccessMemory,
			/* mips_maxi_s_b */ DoesNotAccessMemory,
			/* mips_maxi_s_d */ DoesNotAccessMemory,
			/* mips_maxi_s_h */ DoesNotAccessMemory,
			/* mips_maxi_s_w */ DoesNotAccessMemory,
			/* mips_maxi_u_b */ DoesNotAccessMemory,
			/* mips_maxi_u_d */ DoesNotAccessMemory,
			/* mips_maxi_u_h */ DoesNotAccessMemory,
			/* mips_maxi_u_w */ DoesNotAccessMemory,
			/* mips_min_a_b */ DoesNotAccessMemory,
			/* mips_min_a_d */ DoesNotAccessMemory,
			/* mips_min_a_h */ DoesNotAccessMemory,
			/* mips_min_a_w */ DoesNotAccessMemory,
			/* mips_min_s_b */ DoesNotAccessMemory,
			/* mips_min_s_d */ DoesNotAccessMemory,
			/* mips_min_s_h */ DoesNotAccessMemory,
			/* mips_min_s_w */ DoesNotAccessMemory,
			/* mips_min_u_b */ DoesNotAccessMemory,
			/* mips_min_u_d */ DoesNotAccessMemory,
			/* mips_min_u_h */ DoesNotAccessMemory,
			/* mips_min_u_w */ DoesNotAccessMemory,
			/* mips_mini_s_b */ DoesNotAccessMemory,
			/* mips_mini_s_d */ DoesNotAccessMemory,
			/* mips_mini_s_h */ DoesNotAccessMemory,
			/* mips_mini_s_w */ DoesNotAccessMemory,
			/* mips_mini_u_b */ DoesNotAccessMemory,
			/* mips_mini_u_d */ DoesNotAccessMemory,
			/* mips_mini_u_h */ DoesNotAccessMemory,
			/* mips_mini_u_w */ DoesNotAccessMemory,
			/* mips_mod_s_b */ DoesNotAccessMemory,
			/* mips_mod_s_d */ DoesNotAccessMemory,
			/* mips_mod_s_h */ DoesNotAccessMemory,
			/* mips_mod_s_w */ DoesNotAccessMemory,
			/* mips_mod_u_b */ DoesNotAccessMemory,
			/* mips_mod_u_d */ DoesNotAccessMemory,
			/* mips_mod_u_h */ DoesNotAccessMemory,
			/* mips_mod_u_w */ DoesNotAccessMemory,
	/* mips_modsub */ DoesNotAccessMemory,		/* mips_modsub */ DoesNotAccessMemory,
			/* mips_move_v */ DoesNotAccessMemory,
	/* mips_msub */ DoesNotAccessMemory,		/* mips_msub */ DoesNotAccessMemory,
			/* mips_msub_q_h */ DoesNotAccessMemory,
			/* mips_msub_q_w */ DoesNotAccessMemory,
			/* mips_msubr_q_h */ DoesNotAccessMemory,
			/* mips_msubr_q_w */ DoesNotAccessMemory,
	/* mips_msubu */ DoesNotAccessMemory,		/* mips_msubu */ DoesNotAccessMemory,
			/* mips_msubv_b */ DoesNotAccessMemory,
			/* mips_msubv_d */ DoesNotAccessMemory,
			/* mips_msubv_h */ DoesNotAccessMemory,
			/* mips_msubv_w */ DoesNotAccessMemory,
	/* mips_mthlip */ UnknownModRefBehavior,		/* mips_mthlip */ UnknownModRefBehavior,
	/* mips_mul_ph */ UnknownModRefBehavior,		/* mips_mul_ph */ UnknownModRefBehavior,
			/* mips_mul_q_h */ DoesNotAccessMemory,
			/* mips_mul_q_w */ DoesNotAccessMemory,
	/* mips_mul_s_ph */ UnknownModRefBehavior,		/* mips_mul_s_ph */ UnknownModRefBehavior,
	/* mips_muleq_s_w_phl */ UnknownModRefBehavior,		/* mips_muleq_s_w_phl */ UnknownModRefBehavior,
	/* mips_muleq_s_w_phr */ UnknownModRefBehavior,		/* mips_muleq_s_w_phr */ UnknownModRefBehavior,
	/* mips_muleu_s_ph_qbl */ UnknownModRefBehavior,		/* mips_muleu_s_ph_qbl */ UnknownModRefBehavior,
	/* mips_muleu_s_ph_qbr */ UnknownModRefBehavior,		/* mips_muleu_s_ph_qbr */ UnknownModRefBehavior,
	/* mips_mulq_rs_ph */ UnknownModRefBehavior,		/* mips_mulq_rs_ph */ UnknownModRefBehavior,
	/* mips_mulq_rs_w */ UnknownModRefBehavior,		/* mips_mulq_rs_w */ UnknownModRefBehavior,
	/* mips_mulq_s_ph */ UnknownModRefBehavior,		/* mips_mulq_s_ph */ UnknownModRefBehavior,
	/* mips_mulq_s_w */ UnknownModRefBehavior,		/* mips_mulq_s_w */ UnknownModRefBehavior,
			/* mips_mulr_q_h */ DoesNotAccessMemory,
			/* mips_mulr_q_w */ DoesNotAccessMemory,
	/* mips_mulsa_w_ph */ DoesNotAccessMemory,		/* mips_mulsa_w_ph */ DoesNotAccessMemory,
	/* mips_mulsaq_s_w_ph */ UnknownModRefBehavior,		/* mips_mulsaq_s_w_ph */ UnknownModRefBehavior,
	/* mips_mult */ DoesNotAccessMemory,		/* mips_mult */ DoesNotAccessMemory,
	/* mips_multu */ DoesNotAccessMemory,		/* mips_multu */ DoesNotAccessMemory,
			/* mips_mulv_b */ DoesNotAccessMemory,
			/* mips_mulv_d */ DoesNotAccessMemory,
			/* mips_mulv_h */ DoesNotAccessMemory,
			/* mips_mulv_w */ DoesNotAccessMemory,
			/* mips_nloc_b */ DoesNotAccessMemory,
			/* mips_nloc_d */ DoesNotAccessMemory,
			/* mips_nloc_h */ DoesNotAccessMemory,
			/* mips_nloc_w */ DoesNotAccessMemory,
			/* mips_nlzc_b */ DoesNotAccessMemory,
			/* mips_nlzc_d */ DoesNotAccessMemory,
			/* mips_nlzc_h */ DoesNotAccessMemory,
			/* mips_nlzc_w */ DoesNotAccessMemory,
			/* mips_nor_v */ DoesNotAccessMemory,
			/* mips_nori_b */ DoesNotAccessMemory,
			/* mips_or_v */ DoesNotAccessMemory,
			/* mips_ori_b */ DoesNotAccessMemory,
	/* mips_packrl_ph */ DoesNotAccessMemory,		/* mips_packrl_ph */ DoesNotAccessMemory,
			/* mips_pckev_b */ DoesNotAccessMemory,
			/* mips_pckev_d */ DoesNotAccessMemory,
			/* mips_pckev_h */ DoesNotAccessMemory,
			/* mips_pckev_w */ DoesNotAccessMemory,
			/* mips_pckod_b */ DoesNotAccessMemory,
			/* mips_pckod_d */ DoesNotAccessMemory,
			/* mips_pckod_h */ DoesNotAccessMemory,
			/* mips_pckod_w */ DoesNotAccessMemory,
			/* mips_pcnt_b */ DoesNotAccessMemory,
			/* mips_pcnt_d */ DoesNotAccessMemory,
			/* mips_pcnt_h */ DoesNotAccessMemory,
			/* mips_pcnt_w */ DoesNotAccessMemory,
	/* mips_pick_ph */ OnlyReadsMemory,		/* mips_pick_ph */ OnlyReadsMemory,
	/* mips_pick_qb */ OnlyReadsMemory,		/* mips_pick_qb */ OnlyReadsMemory,
	/* mips_preceq_w_phl */ DoesNotAccessMemory,		/* mips_preceq_w_phl */ DoesNotAccessMemory,
	/* mips_preceq_w_phr */ DoesNotAccessMemory,		/* mips_preceq_w_phr */ DoesNotAccessMemory,
	/* mips_precequ_ph_qbl */ DoesNotAccessMemory,		/* mips_precequ_ph_qbl */ DoesNotAccessMemory,
	/* mips_precequ_ph_qbla */ DoesNotAccessMemory,		/* mips_precequ_ph_qbla */ DoesNotAccessMemory,
	/* mips_precequ_ph_qbr */ DoesNotAccessMemory,		/* mips_precequ_ph_qbr */ DoesNotAccessMemory,
	/* mips_precequ_ph_qbra */ DoesNotAccessMemory,		/* mips_precequ_ph_qbra */ DoesNotAccessMemory,
	/* mips_preceu_ph_qbl */ DoesNotAccessMemory,		/* mips_preceu_ph_qbl */ DoesNotAccessMemory,
	/* mips_preceu_ph_qbla */ DoesNotAccessMemory,		/* mips_preceu_ph_qbla */ DoesNotAccessMemory,
	skipping to change at line 26078		skipping to change at line 33947
	/* mips_precr_sra_r_ph_w */ DoesNotAccessMemory,		/* mips_precr_sra_r_ph_w */ DoesNotAccessMemory,
	/* mips_precrq_ph_w */ DoesNotAccessMemory,		/* mips_precrq_ph_w */ DoesNotAccessMemory,
	/* mips_precrq_qb_ph */ DoesNotAccessMemory,		/* mips_precrq_qb_ph */ DoesNotAccessMemory,
	/* mips_precrq_rs_ph_w */ UnknownModRefBehavior,		/* mips_precrq_rs_ph_w */ UnknownModRefBehavior,
	/* mips_precrqu_s_qb_ph */ UnknownModRefBehavior,		/* mips_precrqu_s_qb_ph */ UnknownModRefBehavior,
	/* mips_prepend */ DoesNotAccessMemory,		/* mips_prepend */ DoesNotAccessMemory,
	/* mips_raddu_w_qb */ DoesNotAccessMemory,		/* mips_raddu_w_qb */ DoesNotAccessMemory,
	/* mips_rddsp */ OnlyReadsMemory,		/* mips_rddsp */ OnlyReadsMemory,
	/* mips_repl_ph */ DoesNotAccessMemory,		/* mips_repl_ph */ DoesNotAccessMemory,
	/* mips_repl_qb */ DoesNotAccessMemory,		/* mips_repl_qb */ DoesNotAccessMemory,
			/* mips_sat_s_b */ DoesNotAccessMemory,
			/* mips_sat_s_d */ DoesNotAccessMemory,
			/* mips_sat_s_h */ DoesNotAccessMemory,
			/* mips_sat_s_w */ DoesNotAccessMemory,
			/* mips_sat_u_b */ DoesNotAccessMemory,
			/* mips_sat_u_d */ DoesNotAccessMemory,
			/* mips_sat_u_h */ DoesNotAccessMemory,
			/* mips_sat_u_w */ DoesNotAccessMemory,
			/* mips_shf_b */ DoesNotAccessMemory,
			/* mips_shf_h */ DoesNotAccessMemory,
			/* mips_shf_w */ DoesNotAccessMemory,
	/* mips_shilo */ DoesNotAccessMemory,		/* mips_shilo */ DoesNotAccessMemory,
	/* mips_shll_ph */ UnknownModRefBehavior,		/* mips_shll_ph */ UnknownModRefBehavior,
	/* mips_shll_qb */ UnknownModRefBehavior,		/* mips_shll_qb */ UnknownModRefBehavior,
	/* mips_shll_s_ph */ UnknownModRefBehavior,		/* mips_shll_s_ph */ UnknownModRefBehavior,
	/* mips_shll_s_w */ UnknownModRefBehavior,		/* mips_shll_s_w */ UnknownModRefBehavior,
	/* mips_shra_ph */ DoesNotAccessMemory,		/* mips_shra_ph */ DoesNotAccessMemory,
	/* mips_shra_qb */ DoesNotAccessMemory,		/* mips_shra_qb */ DoesNotAccessMemory,
	/* mips_shra_r_ph */ DoesNotAccessMemory,		/* mips_shra_r_ph */ DoesNotAccessMemory,
	/* mips_shra_r_qb */ DoesNotAccessMemory,		/* mips_shra_r_qb */ DoesNotAccessMemory,
	/* mips_shra_r_w */ DoesNotAccessMemory,		/* mips_shra_r_w */ DoesNotAccessMemory,
	/* mips_shrl_ph */ DoesNotAccessMemory,		/* mips_shrl_ph */ DoesNotAccessMemory,
	/* mips_shrl_qb */ DoesNotAccessMemory,		/* mips_shrl_qb */ DoesNotAccessMemory,
			/* mips_sld_b */ DoesNotAccessMemory,
			/* mips_sld_d */ DoesNotAccessMemory,
			/* mips_sld_h */ DoesNotAccessMemory,
			/* mips_sld_w */ DoesNotAccessMemory,
			/* mips_sldi_b */ DoesNotAccessMemory,
			/* mips_sldi_d */ DoesNotAccessMemory,
			/* mips_sldi_h */ DoesNotAccessMemory,
			/* mips_sldi_w */ DoesNotAccessMemory,
			/* mips_sll_b */ DoesNotAccessMemory,
			/* mips_sll_d */ DoesNotAccessMemory,
			/* mips_sll_h */ DoesNotAccessMemory,
			/* mips_sll_w */ DoesNotAccessMemory,
			/* mips_slli_b */ DoesNotAccessMemory,
			/* mips_slli_d */ DoesNotAccessMemory,
			/* mips_slli_h */ DoesNotAccessMemory,
			/* mips_slli_w */ DoesNotAccessMemory,
			/* mips_splat_b */ DoesNotAccessMemory,
			/* mips_splat_d */ DoesNotAccessMemory,
			/* mips_splat_h */ DoesNotAccessMemory,
			/* mips_splat_w */ DoesNotAccessMemory,
			/* mips_splati_b */ DoesNotAccessMemory,
			/* mips_splati_d */ DoesNotAccessMemory,
			/* mips_splati_h */ DoesNotAccessMemory,
			/* mips_splati_w */ DoesNotAccessMemory,
			/* mips_sra_b */ DoesNotAccessMemory,
			/* mips_sra_d */ DoesNotAccessMemory,
			/* mips_sra_h */ DoesNotAccessMemory,
			/* mips_sra_w */ DoesNotAccessMemory,
			/* mips_srai_b */ DoesNotAccessMemory,
			/* mips_srai_d */ DoesNotAccessMemory,
			/* mips_srai_h */ DoesNotAccessMemory,
			/* mips_srai_w */ DoesNotAccessMemory,
			/* mips_srar_b */ DoesNotAccessMemory,
			/* mips_srar_d */ DoesNotAccessMemory,
			/* mips_srar_h */ DoesNotAccessMemory,
			/* mips_srar_w */ DoesNotAccessMemory,
			/* mips_srari_b */ DoesNotAccessMemory,
			/* mips_srari_d */ DoesNotAccessMemory,
			/* mips_srari_h */ DoesNotAccessMemory,
			/* mips_srari_w */ DoesNotAccessMemory,
			/* mips_srl_b */ DoesNotAccessMemory,
			/* mips_srl_d */ DoesNotAccessMemory,
			/* mips_srl_h */ DoesNotAccessMemory,
			/* mips_srl_w */ DoesNotAccessMemory,
			/* mips_srli_b */ DoesNotAccessMemory,
			/* mips_srli_d */ DoesNotAccessMemory,
			/* mips_srli_h */ DoesNotAccessMemory,
			/* mips_srli_w */ DoesNotAccessMemory,
			/* mips_srlr_b */ DoesNotAccessMemory,
			/* mips_srlr_d */ DoesNotAccessMemory,
			/* mips_srlr_h */ DoesNotAccessMemory,
			/* mips_srlr_w */ DoesNotAccessMemory,
			/* mips_srlri_b */ DoesNotAccessMemory,
			/* mips_srlri_d */ DoesNotAccessMemory,
			/* mips_srlri_h */ DoesNotAccessMemory,
			/* mips_srlri_w */ DoesNotAccessMemory,
			/* mips_st_b */ OnlyAccessesArgumentPointees,
			/* mips_st_d */ OnlyAccessesArgumentPointees,
			/* mips_st_h */ OnlyAccessesArgumentPointees,
			/* mips_st_w */ OnlyAccessesArgumentPointees,
	/* mips_subq_ph */ UnknownModRefBehavior,		/* mips_subq_ph */ UnknownModRefBehavior,
	/* mips_subq_s_ph */ UnknownModRefBehavior,		/* mips_subq_s_ph */ UnknownModRefBehavior,
	/* mips_subq_s_w */ UnknownModRefBehavior,		/* mips_subq_s_w */ UnknownModRefBehavior,
	/* mips_subqh_ph */ DoesNotAccessMemory,		/* mips_subqh_ph */ DoesNotAccessMemory,
	/* mips_subqh_r_ph */ DoesNotAccessMemory,		/* mips_subqh_r_ph */ DoesNotAccessMemory,
	/* mips_subqh_r_w */ DoesNotAccessMemory,		/* mips_subqh_r_w */ DoesNotAccessMemory,
	/* mips_subqh_w */ DoesNotAccessMemory,		/* mips_subqh_w */ DoesNotAccessMemory,
			/* mips_subs_s_b */ DoesNotAccessMemory,
			/* mips_subs_s_d */ DoesNotAccessMemory,
			/* mips_subs_s_h */ DoesNotAccessMemory,
			/* mips_subs_s_w */ DoesNotAccessMemory,
			/* mips_subs_u_b */ DoesNotAccessMemory,
			/* mips_subs_u_d */ DoesNotAccessMemory,
			/* mips_subs_u_h */ DoesNotAccessMemory,
			/* mips_subs_u_w */ DoesNotAccessMemory,
			/* mips_subsus_u_b */ DoesNotAccessMemory,
			/* mips_subsus_u_d */ DoesNotAccessMemory,
			/* mips_subsus_u_h */ DoesNotAccessMemory,
			/* mips_subsus_u_w */ DoesNotAccessMemory,
			/* mips_subsuu_s_b */ DoesNotAccessMemory,
			/* mips_subsuu_s_d */ DoesNotAccessMemory,
			/* mips_subsuu_s_h */ DoesNotAccessMemory,
			/* mips_subsuu_s_w */ DoesNotAccessMemory,
	/* mips_subu_ph */ UnknownModRefBehavior,		/* mips_subu_ph */ UnknownModRefBehavior,
	/* mips_subu_qb */ UnknownModRefBehavior,		/* mips_subu_qb */ UnknownModRefBehavior,
	/* mips_subu_s_ph */ UnknownModRefBehavior,		/* mips_subu_s_ph */ UnknownModRefBehavior,
	/* mips_subu_s_qb */ UnknownModRefBehavior,		/* mips_subu_s_qb */ UnknownModRefBehavior,
	/* mips_subuh_qb */ DoesNotAccessMemory,		/* mips_subuh_qb */ DoesNotAccessMemory,
	/* mips_subuh_r_qb */ DoesNotAccessMemory,		/* mips_subuh_r_qb */ DoesNotAccessMemory,
			/* mips_subv_b */ DoesNotAccessMemory,
			/* mips_subv_d */ DoesNotAccessMemory,
			/* mips_subv_h */ DoesNotAccessMemory,
			/* mips_subv_w */ DoesNotAccessMemory,
			/* mips_subvi_b */ DoesNotAccessMemory,
			/* mips_subvi_d */ DoesNotAccessMemory,
			/* mips_subvi_h */ DoesNotAccessMemory,
			/* mips_subvi_w */ DoesNotAccessMemory,
			/* mips_vshf_b */ DoesNotAccessMemory,
			/* mips_vshf_d */ DoesNotAccessMemory,
			/* mips_vshf_h */ DoesNotAccessMemory,
			/* mips_vshf_w */ DoesNotAccessMemory,
	/* mips_wrdsp */ UnknownModRefBehavior,		/* mips_wrdsp */ UnknownModRefBehavior,
			/* mips_xor_v */ DoesNotAccessMemory,
			/* mips_xori_b */ DoesNotAccessMemory,
	/* nearbyint */ OnlyReadsMemory,		/* nearbyint */ OnlyReadsMemory,
	/* nvvm_abs_i */ DoesNotAccessMemory,		/* nvvm_abs_i */ DoesNotAccessMemory,
	/* nvvm_abs_ll */ DoesNotAccessMemory,		/* nvvm_abs_ll */ DoesNotAccessMemory,
	/* nvvm_add_rm_d */ DoesNotAccessMemory,		/* nvvm_add_rm_d */ DoesNotAccessMemory,
	/* nvvm_add_rm_f */ DoesNotAccessMemory,		/* nvvm_add_rm_f */ DoesNotAccessMemory,
	/* nvvm_add_rm_ftz_f */ DoesNotAccessMemory,		/* nvvm_add_rm_ftz_f */ DoesNotAccessMemory,
	/* nvvm_add_rn_d */ DoesNotAccessMemory,		/* nvvm_add_rn_d */ DoesNotAccessMemory,
	/* nvvm_add_rn_f */ DoesNotAccessMemory,		/* nvvm_add_rn_f */ DoesNotAccessMemory,
	/* nvvm_add_rn_ftz_f */ DoesNotAccessMemory,		/* nvvm_add_rn_ftz_f */ DoesNotAccessMemory,
	/* nvvm_add_rp_d */ DoesNotAccessMemory,		/* nvvm_add_rp_d */ DoesNotAccessMemory,
	skipping to change at line 26285		skipping to change at line 34255
	/* nvvm_membar_sys */ UnknownModRefBehavior,		/* nvvm_membar_sys */ UnknownModRefBehavior,
	/* nvvm_min_i */ DoesNotAccessMemory,		/* nvvm_min_i */ DoesNotAccessMemory,
	/* nvvm_min_ll */ DoesNotAccessMemory,		/* nvvm_min_ll */ DoesNotAccessMemory,
	/* nvvm_min_ui */ DoesNotAccessMemory,		/* nvvm_min_ui */ DoesNotAccessMemory,
	/* nvvm_min_ull */ DoesNotAccessMemory,		/* nvvm_min_ull */ DoesNotAccessMemory,
	/* nvvm_move_double */ DoesNotAccessMemory,		/* nvvm_move_double */ DoesNotAccessMemory,
	/* nvvm_move_float */ DoesNotAccessMemory,		/* nvvm_move_float */ DoesNotAccessMemory,
	/* nvvm_move_i16 */ DoesNotAccessMemory,		/* nvvm_move_i16 */ DoesNotAccessMemory,
	/* nvvm_move_i32 */ DoesNotAccessMemory,		/* nvvm_move_i32 */ DoesNotAccessMemory,
	/* nvvm_move_i64 */ DoesNotAccessMemory,		/* nvvm_move_i64 */ DoesNotAccessMemory,
	/* nvvm_move_i8 */ DoesNotAccessMemory,
	/* nvvm_move_ptr */ DoesNotAccessMemory,		/* nvvm_move_ptr */ DoesNotAccessMemory,
	/* nvvm_mul24_i */ DoesNotAccessMemory,		/* nvvm_mul24_i */ DoesNotAccessMemory,
	/* nvvm_mul24_ui */ DoesNotAccessMemory,		/* nvvm_mul24_ui */ DoesNotAccessMemory,
	/* nvvm_mul_rm_d */ DoesNotAccessMemory,		/* nvvm_mul_rm_d */ DoesNotAccessMemory,
	/* nvvm_mul_rm_f */ DoesNotAccessMemory,		/* nvvm_mul_rm_f */ DoesNotAccessMemory,
	/* nvvm_mul_rm_ftz_f */ DoesNotAccessMemory,		/* nvvm_mul_rm_ftz_f */ DoesNotAccessMemory,
	/* nvvm_mul_rn_d */ DoesNotAccessMemory,		/* nvvm_mul_rn_d */ DoesNotAccessMemory,
	/* nvvm_mul_rn_f */ DoesNotAccessMemory,		/* nvvm_mul_rn_f */ DoesNotAccessMemory,
	/* nvvm_mul_rn_ftz_f */ DoesNotAccessMemory,		/* nvvm_mul_rn_ftz_f */ DoesNotAccessMemory,
	/* nvvm_mul_rp_d */ DoesNotAccessMemory,		/* nvvm_mul_rp_d */ DoesNotAccessMemory,
	skipping to change at line 26549		skipping to change at line 34518
	/* ppc_altivec_vupklsb */ DoesNotAccessMemory,		/* ppc_altivec_vupklsb */ DoesNotAccessMemory,
	/* ppc_altivec_vupklsh */ DoesNotAccessMemory,		/* ppc_altivec_vupklsh */ DoesNotAccessMemory,
	/* ppc_dcba */ UnknownModRefBehavior,		/* ppc_dcba */ UnknownModRefBehavior,
	/* ppc_dcbf */ UnknownModRefBehavior,		/* ppc_dcbf */ UnknownModRefBehavior,
	/* ppc_dcbi */ UnknownModRefBehavior,		/* ppc_dcbi */ UnknownModRefBehavior,
	/* ppc_dcbst */ UnknownModRefBehavior,		/* ppc_dcbst */ UnknownModRefBehavior,
	/* ppc_dcbt */ OnlyAccessesArgumentPointees,		/* ppc_dcbt */ OnlyAccessesArgumentPointees,
	/* ppc_dcbtst */ UnknownModRefBehavior,		/* ppc_dcbtst */ UnknownModRefBehavior,
	/* ppc_dcbz */ UnknownModRefBehavior,		/* ppc_dcbz */ UnknownModRefBehavior,
	/* ppc_dcbzl */ UnknownModRefBehavior,		/* ppc_dcbzl */ UnknownModRefBehavior,
			/* ppc_is_decremented_ctr_nonzero */ UnknownModRefBehavior,
			/* ppc_mtctr */ UnknownModRefBehavior,
	/* ppc_sync */ UnknownModRefBehavior,		/* ppc_sync */ UnknownModRefBehavior,
	/* prefetch */ OnlyAccessesArgumentPointees,		/* prefetch */ OnlyAccessesArgumentPointees,
	/* ptr_annotation */ UnknownModRefBehavior,		/* ptr_annotation */ UnknownModRefBehavior,
	/* ptx_bar_sync */ UnknownModRefBehavior,		/* ptx_bar_sync */ UnknownModRefBehavior,
	/* ptx_read_clock */ DoesNotAccessMemory,		/* ptx_read_clock */ DoesNotAccessMemory,
	/* ptx_read_clock64 */ DoesNotAccessMemory,		/* ptx_read_clock64 */ DoesNotAccessMemory,
	/* ptx_read_ctaid_w */ DoesNotAccessMemory,		/* ptx_read_ctaid_w */ DoesNotAccessMemory,
	/* ptx_read_ctaid_x */ DoesNotAccessMemory,		/* ptx_read_ctaid_x */ DoesNotAccessMemory,
	/* ptx_read_ctaid_y */ DoesNotAccessMemory,		/* ptx_read_ctaid_y */ DoesNotAccessMemory,
	/* ptx_read_ctaid_z */ DoesNotAccessMemory,		/* ptx_read_ctaid_z */ DoesNotAccessMemory,
	skipping to change at line 26604		skipping to change at line 34575
	/* r600_read_ngroups_z */ DoesNotAccessMemory,		/* r600_read_ngroups_z */ DoesNotAccessMemory,
	/* r600_read_tgid_x */ DoesNotAccessMemory,		/* r600_read_tgid_x */ DoesNotAccessMemory,
	/* r600_read_tgid_y */ DoesNotAccessMemory,		/* r600_read_tgid_y */ DoesNotAccessMemory,
	/* r600_read_tgid_z */ DoesNotAccessMemory,		/* r600_read_tgid_z */ DoesNotAccessMemory,
	/* r600_read_tidig_x */ DoesNotAccessMemory,		/* r600_read_tidig_x */ DoesNotAccessMemory,
	/* r600_read_tidig_y */ DoesNotAccessMemory,		/* r600_read_tidig_y */ DoesNotAccessMemory,
	/* r600_read_tidig_z */ DoesNotAccessMemory,		/* r600_read_tidig_z */ DoesNotAccessMemory,
	/* readcyclecounter */ UnknownModRefBehavior,		/* readcyclecounter */ UnknownModRefBehavior,
	/* returnaddress */ DoesNotAccessMemory,		/* returnaddress */ DoesNotAccessMemory,
	/* rint */ OnlyReadsMemory,		/* rint */ OnlyReadsMemory,
			/* round */ OnlyReadsMemory,
	/* sadd_with_overflow */ DoesNotAccessMemory,		/* sadd_with_overflow */ DoesNotAccessMemory,
	/* setjmp */ UnknownModRefBehavior,		/* setjmp */ UnknownModRefBehavior,
	/* siglongjmp */ UnknownModRefBehavior,		/* siglongjmp */ UnknownModRefBehavior,
	/* sigsetjmp */ UnknownModRefBehavior,		/* sigsetjmp */ UnknownModRefBehavior,
	/* sin */ OnlyReadsMemory,		/* sin */ OnlyReadsMemory,
	/* smul_with_overflow */ DoesNotAccessMemory,		/* smul_with_overflow */ DoesNotAccessMemory,
	/* sqrt */ OnlyReadsMemory,		/* sqrt */ OnlyReadsMemory,
	/* ssub_with_overflow */ DoesNotAccessMemory,		/* ssub_with_overflow */ DoesNotAccessMemory,
	/* stackprotector */ UnknownModRefBehavior,		/* stackprotector */ UnknownModRefBehavior,
			/* stackprotectorcheck */ OnlyAccessesArgumentPointees,
	/* stackrestore */ UnknownModRefBehavior,		/* stackrestore */ UnknownModRefBehavior,
	/* stacksave */ UnknownModRefBehavior,		/* stacksave */ UnknownModRefBehavior,
	/* trap */ UnknownModRefBehavior,		/* trap */ UnknownModRefBehavior,
	/* trunc */ OnlyReadsMemory,		/* trunc */ OnlyReadsMemory,
	/* uadd_with_overflow */ DoesNotAccessMemory,		/* uadd_with_overflow */ DoesNotAccessMemory,
	/* umul_with_overflow */ DoesNotAccessMemory,		/* umul_with_overflow */ DoesNotAccessMemory,
	/* usub_with_overflow */ DoesNotAccessMemory,		/* usub_with_overflow */ DoesNotAccessMemory,
	/* vacopy */ UnknownModRefBehavior,		/* vacopy */ UnknownModRefBehavior,
	/* vaend */ UnknownModRefBehavior,		/* vaend */ UnknownModRefBehavior,
	/* var_annotation */ UnknownModRefBehavior,		/* var_annotation */ UnknownModRefBehavior,
	skipping to change at line 26791		skipping to change at line 34764
	/* x86_avx2_psubs_w */ DoesNotAccessMemory,		/* x86_avx2_psubs_w */ DoesNotAccessMemory,
	/* x86_avx2_psubus_b */ DoesNotAccessMemory,		/* x86_avx2_psubus_b */ DoesNotAccessMemory,
	/* x86_avx2_psubus_w */ DoesNotAccessMemory,		/* x86_avx2_psubus_w */ DoesNotAccessMemory,
	/* x86_avx2_vbroadcast_sd_pd_256 */ DoesNotAccessMemory,		/* x86_avx2_vbroadcast_sd_pd_256 */ DoesNotAccessMemory,
	/* x86_avx2_vbroadcast_ss_ps */ DoesNotAccessMemory,		/* x86_avx2_vbroadcast_ss_ps */ DoesNotAccessMemory,
	/* x86_avx2_vbroadcast_ss_ps_256 */ DoesNotAccessMemory,		/* x86_avx2_vbroadcast_ss_ps_256 */ DoesNotAccessMemory,
	/* x86_avx2_vbroadcasti128 */ OnlyReadsArgumentPointees,		/* x86_avx2_vbroadcasti128 */ OnlyReadsArgumentPointees,
	/* x86_avx2_vextracti128 */ DoesNotAccessMemory,		/* x86_avx2_vextracti128 */ DoesNotAccessMemory,
	/* x86_avx2_vinserti128 */ DoesNotAccessMemory,		/* x86_avx2_vinserti128 */ DoesNotAccessMemory,
	/* x86_avx2_vperm2i128 */ DoesNotAccessMemory,		/* x86_avx2_vperm2i128 */ DoesNotAccessMemory,
			/* x86_avx512_and_pi */ DoesNotAccessMemory,
			/* x86_avx512_cmpeq_pi_512 */ DoesNotAccessMemory,
			/* x86_avx512_conflict_d_512 */ UnknownModRefBehavior,
			/* x86_avx512_conflict_d_mask_512 */ UnknownModRefBehavior,
			/* x86_avx512_conflict_d_maskz_512 */ UnknownModRefBehavior,
			/* x86_avx512_conflict_q_512 */ UnknownModRefBehavior,
			/* x86_avx512_conflict_q_mask_512 */ UnknownModRefBehavior,
			/* x86_avx512_conflict_q_maskz_512 */ UnknownModRefBehavior,
			/* x86_avx512_cvt_ps2dq_512 */ DoesNotAccessMemory,
			/* x86_avx512_cvtdq2_ps_512 */ DoesNotAccessMemory,
			/* x86_avx512_cvtsd2usi */ DoesNotAccessMemory,
			/* x86_avx512_cvtsd2usi64 */ DoesNotAccessMemory,
			/* x86_avx512_cvtss2usi */ DoesNotAccessMemory,
			/* x86_avx512_cvtss2usi64 */ DoesNotAccessMemory,
			/* x86_avx512_cvttsd2usi */ DoesNotAccessMemory,
			/* x86_avx512_cvttsd2usi64 */ DoesNotAccessMemory,
			/* x86_avx512_cvttss2usi */ DoesNotAccessMemory,
			/* x86_avx512_cvttss2usi64 */ DoesNotAccessMemory,
			/* x86_avx512_cvtusi2sd */ DoesNotAccessMemory,
			/* x86_avx512_cvtusi2ss */ DoesNotAccessMemory,
			/* x86_avx512_cvtusi642sd */ DoesNotAccessMemory,
			/* x86_avx512_cvtusi642ss */ DoesNotAccessMemory,
			/* x86_avx512_gather_dpd_512 */ OnlyReadsMemory,
			/* x86_avx512_gather_dpd_mask_512 */ OnlyReadsMemory,
			/* x86_avx512_gather_dpi_512 */ OnlyReadsArgumentPointees,
			/* x86_avx512_gather_dpi_mask_512 */ OnlyReadsArgumentPointees,
			/* x86_avx512_gather_dpq_512 */ OnlyReadsArgumentPointees,
			/* x86_avx512_gather_dpq_mask_512 */ OnlyReadsMemory,
			/* x86_avx512_gather_dps_512 */ OnlyReadsMemory,
			/* x86_avx512_gather_dps_mask_512 */ OnlyReadsMemory,
			/* x86_avx512_gather_qpd_512 */ OnlyReadsArgumentPointees,
			/* x86_avx512_gather_qpd_mask_512 */ OnlyReadsMemory,
			/* x86_avx512_gather_qpi_512 */ OnlyReadsArgumentPointees,
			/* x86_avx512_gather_qpi_mask_512 */ OnlyReadsMemory,
			/* x86_avx512_gather_qpq_512 */ OnlyReadsArgumentPointees,
			/* x86_avx512_gather_qpq_mask_512 */ OnlyReadsArgumentPointees,
			/* x86_avx512_gather_qps_512 */ OnlyReadsMemory,
			/* x86_avx512_gather_qps_mask_512 */ OnlyReadsMemory,
			/* x86_avx512_kortestc */ DoesNotAccessMemory,
			/* x86_avx512_kortestz */ DoesNotAccessMemory,
			/* x86_avx512_max_pd_512 */ DoesNotAccessMemory,
			/* x86_avx512_max_ps_512 */ DoesNotAccessMemory,
			/* x86_avx512_min_pd_512 */ DoesNotAccessMemory,
			/* x86_avx512_min_ps_512 */ DoesNotAccessMemory,
			/* x86_avx512_mskblend_d_512 */ DoesNotAccessMemory,
			/* x86_avx512_mskblend_pd_512 */ DoesNotAccessMemory,
			/* x86_avx512_mskblend_ps_512 */ DoesNotAccessMemory,
			/* x86_avx512_mskblend_q_512 */ DoesNotAccessMemory,
			/* x86_avx512_pbroadcastd_512 */ DoesNotAccessMemory,
			/* x86_avx512_pbroadcastd_i32_512 */ DoesNotAccessMemory,
			/* x86_avx512_pbroadcastq_512 */ DoesNotAccessMemory,
			/* x86_avx512_pbroadcastq_i64_512 */ DoesNotAccessMemory,
			/* x86_avx512_pmaxs_d */ DoesNotAccessMemory,
			/* x86_avx512_pmaxs_q */ DoesNotAccessMemory,
			/* x86_avx512_pmaxu_d */ DoesNotAccessMemory,
			/* x86_avx512_pmaxu_q */ DoesNotAccessMemory,
			/* x86_avx512_pmins_d */ DoesNotAccessMemory,
			/* x86_avx512_pmins_q */ DoesNotAccessMemory,
			/* x86_avx512_pminu_d */ DoesNotAccessMemory,
			/* x86_avx512_pminu_q */ DoesNotAccessMemory,
			/* x86_avx512_pmovzxbd */ DoesNotAccessMemory,
			/* x86_avx512_pmovzxbq */ DoesNotAccessMemory,
			/* x86_avx512_pmovzxdq */ DoesNotAccessMemory,
			/* x86_avx512_pmovzxwd */ DoesNotAccessMemory,
			/* x86_avx512_pmovzxwq */ DoesNotAccessMemory,
			/* x86_avx512_psll_dq */ DoesNotAccessMemory,
			/* x86_avx512_psll_dq_bs */ DoesNotAccessMemory,
			/* x86_avx512_psrl_dq */ DoesNotAccessMemory,
			/* x86_avx512_psrl_dq_bs */ DoesNotAccessMemory,
			/* x86_avx512_rcp14_pd_512 */ DoesNotAccessMemory,
			/* x86_avx512_rcp14_ps_512 */ DoesNotAccessMemory,
			/* x86_avx512_rcp14_sd */ DoesNotAccessMemory,
			/* x86_avx512_rcp14_ss */ DoesNotAccessMemory,
			/* x86_avx512_rcp28_pd_512 */ DoesNotAccessMemory,
			/* x86_avx512_rcp28_ps_512 */ DoesNotAccessMemory,
			/* x86_avx512_rcp28_sd */ DoesNotAccessMemory,
			/* x86_avx512_rcp28_ss */ DoesNotAccessMemory,
			/* x86_avx512_rndscale_pd_512 */ DoesNotAccessMemory,
			/* x86_avx512_rndscale_ps_512 */ DoesNotAccessMemory,
			/* x86_avx512_rndscale_sd */ DoesNotAccessMemory,
			/* x86_avx512_rndscale_ss */ DoesNotAccessMemory,
			/* x86_avx512_rsqrt14_pd_512 */ DoesNotAccessMemory,
			/* x86_avx512_rsqrt14_ps_512 */ DoesNotAccessMemory,
			/* x86_avx512_rsqrt14_sd */ DoesNotAccessMemory,
			/* x86_avx512_rsqrt14_ss */ DoesNotAccessMemory,
			/* x86_avx512_rsqrt28_pd_512 */ DoesNotAccessMemory,
			/* x86_avx512_rsqrt28_ps_512 */ DoesNotAccessMemory,
			/* x86_avx512_rsqrt28_sd */ DoesNotAccessMemory,
			/* x86_avx512_rsqrt28_ss */ DoesNotAccessMemory,
			/* x86_avx512_scatter_dpd_512 */ OnlyAccessesArgumentPointees,
			/* x86_avx512_scatter_dpd_mask_512 */ OnlyAccessesArgumentPointees,
			/* x86_avx512_scatter_dpi_512 */ UnknownModRefBehavior,
			/* x86_avx512_scatter_dpi_mask_512 */ OnlyAccessesArgumentPointees,
			/* x86_avx512_scatter_dpq_512 */ UnknownModRefBehavior,
			/* x86_avx512_scatter_dpq_mask_512 */ OnlyAccessesArgumentPointees,
			/* x86_avx512_scatter_dps_512 */ OnlyAccessesArgumentPointees,
			/* x86_avx512_scatter_dps_mask_512 */ OnlyAccessesArgumentPointees,
			/* x86_avx512_scatter_qpd_512 */ OnlyAccessesArgumentPointees,
			/* x86_avx512_scatter_qpd_mask_512 */ OnlyAccessesArgumentPointees,
			/* x86_avx512_scatter_qpi_512 */ UnknownModRefBehavior,
			/* x86_avx512_scatter_qpi_mask_512 */ OnlyAccessesArgumentPointees,
			/* x86_avx512_scatter_qpq_512 */ UnknownModRefBehavior,
			/* x86_avx512_scatter_qpq_mask_512 */ OnlyAccessesArgumentPointees,
			/* x86_avx512_scatter_qps_512 */ OnlyAccessesArgumentPointees,
			/* x86_avx512_scatter_qps_mask_512 */ OnlyAccessesArgumentPointees,
			/* x86_avx512_sqrt_pd_512 */ DoesNotAccessMemory,
			/* x86_avx512_sqrt_ps_512 */ DoesNotAccessMemory,
			/* x86_avx512_sqrt_sd */ DoesNotAccessMemory,
			/* x86_avx512_sqrt_ss */ DoesNotAccessMemory,
			/* x86_avx512_vbroadcast_sd_512 */ OnlyReadsArgumentPointees,
			/* x86_avx512_vbroadcast_sd_pd_512 */ DoesNotAccessMemory,
			/* x86_avx512_vbroadcast_ss_512 */ OnlyReadsArgumentPointees,
			/* x86_avx512_vbroadcast_ss_ps_512 */ DoesNotAccessMemory,
			/* x86_avx512_vcvtph2ps_512 */ DoesNotAccessMemory,
			/* x86_avx512_vcvtps2ph_512 */ DoesNotAccessMemory,
	/* x86_avx_addsub_pd_256 */ DoesNotAccessMemory,		/* x86_avx_addsub_pd_256 */ DoesNotAccessMemory,
	/* x86_avx_addsub_ps_256 */ DoesNotAccessMemory,		/* x86_avx_addsub_ps_256 */ DoesNotAccessMemory,
	/* x86_avx_blend_pd_256 */ DoesNotAccessMemory,		/* x86_avx_blend_pd_256 */ DoesNotAccessMemory,
	/* x86_avx_blend_ps_256 */ DoesNotAccessMemory,		/* x86_avx_blend_ps_256 */ DoesNotAccessMemory,
	/* x86_avx_blendv_pd_256 */ DoesNotAccessMemory,		/* x86_avx_blendv_pd_256 */ DoesNotAccessMemory,
	/* x86_avx_blendv_ps_256 */ DoesNotAccessMemory,		/* x86_avx_blendv_ps_256 */ DoesNotAccessMemory,
	/* x86_avx_cmp_pd_256 */ DoesNotAccessMemory,		/* x86_avx_cmp_pd_256 */ DoesNotAccessMemory,
	/* x86_avx_cmp_ps_256 */ DoesNotAccessMemory,		/* x86_avx_cmp_ps_256 */ DoesNotAccessMemory,
	/* x86_avx_cvt_pd2_ps_256 */ DoesNotAccessMemory,		/* x86_avx_cvt_pd2_ps_256 */ DoesNotAccessMemory,
	/* x86_avx_cvt_pd2dq_256 */ DoesNotAccessMemory,		/* x86_avx_cvt_pd2dq_256 */ DoesNotAccessMemory,
	skipping to change at line 26881		skipping to change at line 34969
	/* x86_bmi_bextr_32 */ DoesNotAccessMemory,		/* x86_bmi_bextr_32 */ DoesNotAccessMemory,
	/* x86_bmi_bextr_64 */ DoesNotAccessMemory,		/* x86_bmi_bextr_64 */ DoesNotAccessMemory,
	/* x86_bmi_bzhi_32 */ DoesNotAccessMemory,		/* x86_bmi_bzhi_32 */ DoesNotAccessMemory,
	/* x86_bmi_bzhi_64 */ DoesNotAccessMemory,		/* x86_bmi_bzhi_64 */ DoesNotAccessMemory,
	/* x86_bmi_pdep_32 */ DoesNotAccessMemory,		/* x86_bmi_pdep_32 */ DoesNotAccessMemory,
	/* x86_bmi_pdep_64 */ DoesNotAccessMemory,		/* x86_bmi_pdep_64 */ DoesNotAccessMemory,
	/* x86_bmi_pext_32 */ DoesNotAccessMemory,		/* x86_bmi_pext_32 */ DoesNotAccessMemory,
	/* x86_bmi_pext_64 */ DoesNotAccessMemory,		/* x86_bmi_pext_64 */ DoesNotAccessMemory,
	/* x86_fma_vfmadd_pd */ DoesNotAccessMemory,		/* x86_fma_vfmadd_pd */ DoesNotAccessMemory,
	/* x86_fma_vfmadd_pd_256 */ DoesNotAccessMemory,		/* x86_fma_vfmadd_pd_256 */ DoesNotAccessMemory,
			/* x86_fma_vfmadd_pd_512 */ DoesNotAccessMemory,
	/* x86_fma_vfmadd_ps */ DoesNotAccessMemory,		/* x86_fma_vfmadd_ps */ DoesNotAccessMemory,
	/* x86_fma_vfmadd_ps_256 */ DoesNotAccessMemory,		/* x86_fma_vfmadd_ps_256 */ DoesNotAccessMemory,
			/* x86_fma_vfmadd_ps_512 */ DoesNotAccessMemory,
	/* x86_fma_vfmadd_sd */ DoesNotAccessMemory,		/* x86_fma_vfmadd_sd */ DoesNotAccessMemory,
	/* x86_fma_vfmadd_ss */ DoesNotAccessMemory,		/* x86_fma_vfmadd_ss */ DoesNotAccessMemory,
	/* x86_fma_vfmaddsub_pd */ DoesNotAccessMemory,		/* x86_fma_vfmaddsub_pd */ DoesNotAccessMemory,
	/* x86_fma_vfmaddsub_pd_256 */ DoesNotAccessMemory,		/* x86_fma_vfmaddsub_pd_256 */ DoesNotAccessMemory,
			/* x86_fma_vfmaddsub_pd_512 */ DoesNotAccessMemory,
	/* x86_fma_vfmaddsub_ps */ DoesNotAccessMemory,		/* x86_fma_vfmaddsub_ps */ DoesNotAccessMemory,
	/* x86_fma_vfmaddsub_ps_256 */ DoesNotAccessMemory,		/* x86_fma_vfmaddsub_ps_256 */ DoesNotAccessMemory,
			/* x86_fma_vfmaddsub_ps_512 */ DoesNotAccessMemory,
	/* x86_fma_vfmsub_pd */ DoesNotAccessMemory,		/* x86_fma_vfmsub_pd */ DoesNotAccessMemory,
	/* x86_fma_vfmsub_pd_256 */ DoesNotAccessMemory,		/* x86_fma_vfmsub_pd_256 */ DoesNotAccessMemory,
			/* x86_fma_vfmsub_pd_512 */ DoesNotAccessMemory,
	/* x86_fma_vfmsub_ps */ DoesNotAccessMemory,		/* x86_fma_vfmsub_ps */ DoesNotAccessMemory,
	/* x86_fma_vfmsub_ps_256 */ DoesNotAccessMemory,		/* x86_fma_vfmsub_ps_256 */ DoesNotAccessMemory,
			/* x86_fma_vfmsub_ps_512 */ DoesNotAccessMemory,
	/* x86_fma_vfmsub_sd */ DoesNotAccessMemory,		/* x86_fma_vfmsub_sd */ DoesNotAccessMemory,
	/* x86_fma_vfmsub_ss */ DoesNotAccessMemory,		/* x86_fma_vfmsub_ss */ DoesNotAccessMemory,
	/* x86_fma_vfmsubadd_pd */ DoesNotAccessMemory,		/* x86_fma_vfmsubadd_pd */ DoesNotAccessMemory,
	/* x86_fma_vfmsubadd_pd_256 */ DoesNotAccessMemory,		/* x86_fma_vfmsubadd_pd_256 */ DoesNotAccessMemory,
			/* x86_fma_vfmsubadd_pd_512 */ DoesNotAccessMemory,
	/* x86_fma_vfmsubadd_ps */ DoesNotAccessMemory,		/* x86_fma_vfmsubadd_ps */ DoesNotAccessMemory,
	/* x86_fma_vfmsubadd_ps_256 */ DoesNotAccessMemory,		/* x86_fma_vfmsubadd_ps_256 */ DoesNotAccessMemory,
			/* x86_fma_vfmsubadd_ps_512 */ DoesNotAccessMemory,
	/* x86_fma_vfnmadd_pd */ DoesNotAccessMemory,		/* x86_fma_vfnmadd_pd */ DoesNotAccessMemory,
	/* x86_fma_vfnmadd_pd_256 */ DoesNotAccessMemory,		/* x86_fma_vfnmadd_pd_256 */ DoesNotAccessMemory,
			/* x86_fma_vfnmadd_pd_512 */ DoesNotAccessMemory,
	/* x86_fma_vfnmadd_ps */ DoesNotAccessMemory,		/* x86_fma_vfnmadd_ps */ DoesNotAccessMemory,
	/* x86_fma_vfnmadd_ps_256 */ DoesNotAccessMemory,		/* x86_fma_vfnmadd_ps_256 */ DoesNotAccessMemory,
			/* x86_fma_vfnmadd_ps_512 */ DoesNotAccessMemory,
	/* x86_fma_vfnmadd_sd */ DoesNotAccessMemory,		/* x86_fma_vfnmadd_sd */ DoesNotAccessMemory,
	/* x86_fma_vfnmadd_ss */ DoesNotAccessMemory,		/* x86_fma_vfnmadd_ss */ DoesNotAccessMemory,
	/* x86_fma_vfnmsub_pd */ DoesNotAccessMemory,		/* x86_fma_vfnmsub_pd */ DoesNotAccessMemory,
	/* x86_fma_vfnmsub_pd_256 */ DoesNotAccessMemory,		/* x86_fma_vfnmsub_pd_256 */ DoesNotAccessMemory,
			/* x86_fma_vfnmsub_pd_512 */ DoesNotAccessMemory,
	/* x86_fma_vfnmsub_ps */ DoesNotAccessMemory,		/* x86_fma_vfnmsub_ps */ DoesNotAccessMemory,
	/* x86_fma_vfnmsub_ps_256 */ DoesNotAccessMemory,		/* x86_fma_vfnmsub_ps_256 */ DoesNotAccessMemory,
			/* x86_fma_vfnmsub_ps_512 */ DoesNotAccessMemory,
	/* x86_fma_vfnmsub_sd */ DoesNotAccessMemory,		/* x86_fma_vfnmsub_sd */ DoesNotAccessMemory,
	/* x86_fma_vfnmsub_ss */ DoesNotAccessMemory,		/* x86_fma_vfnmsub_ss */ DoesNotAccessMemory,
	/* x86_int */ UnknownModRefBehavior,		/* x86_int */ UnknownModRefBehavior,
			/* x86_int2mask_v16i1 */ DoesNotAccessMemory,
			/* x86_kadd_v16i1 */ DoesNotAccessMemory,
			/* x86_kand_v16i1 */ DoesNotAccessMemory,
			/* x86_kandn_v16i1 */ DoesNotAccessMemory,
			/* x86_knot_v16i1 */ DoesNotAccessMemory,
			/* x86_kor_v16i1 */ DoesNotAccessMemory,
			/* x86_kunpck_v16i1 */ DoesNotAccessMemory,
			/* x86_kxnor_v16i1 */ DoesNotAccessMemory,
			/* x86_kxor_v16i1 */ DoesNotAccessMemory,
			/* x86_mask2int_v16i1 */ DoesNotAccessMemory,
	/* x86_mmx_emms */ UnknownModRefBehavior,		/* x86_mmx_emms */ UnknownModRefBehavior,
	/* x86_mmx_femms */ UnknownModRefBehavior,		/* x86_mmx_femms */ UnknownModRefBehavior,
	/* x86_mmx_maskmovq */ UnknownModRefBehavior,		/* x86_mmx_maskmovq */ UnknownModRefBehavior,
	/* x86_mmx_movnt_dq */ UnknownModRefBehavior,		/* x86_mmx_movnt_dq */ UnknownModRefBehavior,
	/* x86_mmx_packssdw */ DoesNotAccessMemory,		/* x86_mmx_packssdw */ DoesNotAccessMemory,
	/* x86_mmx_packsswb */ DoesNotAccessMemory,		/* x86_mmx_packsswb */ DoesNotAccessMemory,
	/* x86_mmx_packuswb */ DoesNotAccessMemory,		/* x86_mmx_packuswb */ DoesNotAccessMemory,
	/* x86_mmx_padd_b */ DoesNotAccessMemory,		/* x86_mmx_padd_b */ DoesNotAccessMemory,
	/* x86_mmx_padd_d */ DoesNotAccessMemory,		/* x86_mmx_padd_d */ DoesNotAccessMemory,
	/* x86_mmx_padd_q */ DoesNotAccessMemory,		/* x86_mmx_padd_q */ DoesNotAccessMemory,
	skipping to change at line 26994		skipping to change at line 35104
	/* x86_rdfsbase_32 */ UnknownModRefBehavior,		/* x86_rdfsbase_32 */ UnknownModRefBehavior,
	/* x86_rdfsbase_64 */ UnknownModRefBehavior,		/* x86_rdfsbase_64 */ UnknownModRefBehavior,
	/* x86_rdgsbase_32 */ UnknownModRefBehavior,		/* x86_rdgsbase_32 */ UnknownModRefBehavior,
	/* x86_rdgsbase_64 */ UnknownModRefBehavior,		/* x86_rdgsbase_64 */ UnknownModRefBehavior,
	/* x86_rdrand_16 */ UnknownModRefBehavior,		/* x86_rdrand_16 */ UnknownModRefBehavior,
	/* x86_rdrand_32 */ UnknownModRefBehavior,		/* x86_rdrand_32 */ UnknownModRefBehavior,
	/* x86_rdrand_64 */ UnknownModRefBehavior,		/* x86_rdrand_64 */ UnknownModRefBehavior,
	/* x86_rdseed_16 */ UnknownModRefBehavior,		/* x86_rdseed_16 */ UnknownModRefBehavior,
	/* x86_rdseed_32 */ UnknownModRefBehavior,		/* x86_rdseed_32 */ UnknownModRefBehavior,
	/* x86_rdseed_64 */ UnknownModRefBehavior,		/* x86_rdseed_64 */ UnknownModRefBehavior,
			/* x86_sha1msg1 */ DoesNotAccessMemory,
			/* x86_sha1msg2 */ DoesNotAccessMemory,
			/* x86_sha1nexte */ DoesNotAccessMemory,
			/* x86_sha1rnds4 */ DoesNotAccessMemory,
			/* x86_sha256msg1 */ DoesNotAccessMemory,
			/* x86_sha256msg2 */ DoesNotAccessMemory,
			/* x86_sha256rnds2 */ DoesNotAccessMemory,
	/* x86_sse2_add_sd */ DoesNotAccessMemory,		/* x86_sse2_add_sd */ DoesNotAccessMemory,
	/* x86_sse2_clflush */ UnknownModRefBehavior,		/* x86_sse2_clflush */ UnknownModRefBehavior,
	/* x86_sse2_cmp_pd */ DoesNotAccessMemory,		/* x86_sse2_cmp_pd */ DoesNotAccessMemory,
	/* x86_sse2_cmp_sd */ DoesNotAccessMemory,		/* x86_sse2_cmp_sd */ DoesNotAccessMemory,
	/* x86_sse2_comieq_sd */ DoesNotAccessMemory,		/* x86_sse2_comieq_sd */ DoesNotAccessMemory,
	/* x86_sse2_comige_sd */ DoesNotAccessMemory,		/* x86_sse2_comige_sd */ DoesNotAccessMemory,
	/* x86_sse2_comigt_sd */ DoesNotAccessMemory,		/* x86_sse2_comigt_sd */ DoesNotAccessMemory,
	/* x86_sse2_comile_sd */ DoesNotAccessMemory,		/* x86_sse2_comile_sd */ DoesNotAccessMemory,
	/* x86_sse2_comilt_sd */ DoesNotAccessMemory,		/* x86_sse2_comilt_sd */ DoesNotAccessMemory,
	/* x86_sse2_comineq_sd */ DoesNotAccessMemory,		/* x86_sse2_comineq_sd */ DoesNotAccessMemory,
	skipping to change at line 27143		skipping to change at line 35260
	/* x86_sse41_ptestnzc */ DoesNotAccessMemory,		/* x86_sse41_ptestnzc */ DoesNotAccessMemory,
	/* x86_sse41_ptestz */ DoesNotAccessMemory,		/* x86_sse41_ptestz */ DoesNotAccessMemory,
	/* x86_sse41_round_pd */ DoesNotAccessMemory,		/* x86_sse41_round_pd */ DoesNotAccessMemory,
	/* x86_sse41_round_ps */ DoesNotAccessMemory,		/* x86_sse41_round_ps */ DoesNotAccessMemory,
	/* x86_sse41_round_sd */ DoesNotAccessMemory,		/* x86_sse41_round_sd */ DoesNotAccessMemory,
	/* x86_sse41_round_ss */ DoesNotAccessMemory,		/* x86_sse41_round_ss */ DoesNotAccessMemory,
	/* x86_sse42_crc32_32_16 */ DoesNotAccessMemory,		/* x86_sse42_crc32_32_16 */ DoesNotAccessMemory,
	/* x86_sse42_crc32_32_32 */ DoesNotAccessMemory,		/* x86_sse42_crc32_32_32 */ DoesNotAccessMemory,
	/* x86_sse42_crc32_32_8 */ DoesNotAccessMemory,		/* x86_sse42_crc32_32_8 */ DoesNotAccessMemory,
	/* x86_sse42_crc32_64_64 */ DoesNotAccessMemory,		/* x86_sse42_crc32_64_64 */ DoesNotAccessMemory,
	/* x86_sse42_crc32_64_8 */ DoesNotAccessMemory,
	/* x86_sse42_pcmpestri128 */ DoesNotAccessMemory,		/* x86_sse42_pcmpestri128 */ DoesNotAccessMemory,
	/* x86_sse42_pcmpestria128 */ DoesNotAccessMemory,		/* x86_sse42_pcmpestria128 */ DoesNotAccessMemory,
	/* x86_sse42_pcmpestric128 */ DoesNotAccessMemory,		/* x86_sse42_pcmpestric128 */ DoesNotAccessMemory,
	/* x86_sse42_pcmpestrio128 */ DoesNotAccessMemory,		/* x86_sse42_pcmpestrio128 */ DoesNotAccessMemory,
	/* x86_sse42_pcmpestris128 */ DoesNotAccessMemory,		/* x86_sse42_pcmpestris128 */ DoesNotAccessMemory,
	/* x86_sse42_pcmpestriz128 */ DoesNotAccessMemory,		/* x86_sse42_pcmpestriz128 */ DoesNotAccessMemory,
	/* x86_sse42_pcmpestrm128 */ DoesNotAccessMemory,		/* x86_sse42_pcmpestrm128 */ DoesNotAccessMemory,
	/* x86_sse42_pcmpistri128 */ DoesNotAccessMemory,		/* x86_sse42_pcmpistri128 */ DoesNotAccessMemory,
	/* x86_sse42_pcmpistria128 */ DoesNotAccessMemory,		/* x86_sse42_pcmpistria128 */ DoesNotAccessMemory,
	/* x86_sse42_pcmpistric128 */ DoesNotAccessMemory,		/* x86_sse42_pcmpistric128 */ DoesNotAccessMemory,
	skipping to change at line 27240		skipping to change at line 35356
	/* x86_ssse3_pmul_hr_sw */ DoesNotAccessMemory,		/* x86_ssse3_pmul_hr_sw */ DoesNotAccessMemory,
	/* x86_ssse3_pmul_hr_sw_128 */ DoesNotAccessMemory,		/* x86_ssse3_pmul_hr_sw_128 */ DoesNotAccessMemory,
	/* x86_ssse3_pshuf_b */ DoesNotAccessMemory,		/* x86_ssse3_pshuf_b */ DoesNotAccessMemory,
	/* x86_ssse3_pshuf_b_128 */ DoesNotAccessMemory,		/* x86_ssse3_pshuf_b_128 */ DoesNotAccessMemory,
	/* x86_ssse3_psign_b */ DoesNotAccessMemory,		/* x86_ssse3_psign_b */ DoesNotAccessMemory,
	/* x86_ssse3_psign_b_128 */ DoesNotAccessMemory,		/* x86_ssse3_psign_b_128 */ DoesNotAccessMemory,
	/* x86_ssse3_psign_d */ DoesNotAccessMemory,		/* x86_ssse3_psign_d */ DoesNotAccessMemory,
	/* x86_ssse3_psign_d_128 */ DoesNotAccessMemory,		/* x86_ssse3_psign_d_128 */ DoesNotAccessMemory,
	/* x86_ssse3_psign_w */ DoesNotAccessMemory,		/* x86_ssse3_psign_w */ DoesNotAccessMemory,
	/* x86_ssse3_psign_w_128 */ DoesNotAccessMemory,		/* x86_ssse3_psign_w_128 */ DoesNotAccessMemory,
			/* x86_tbm_bextri_u32 */ DoesNotAccessMemory,
			/* x86_tbm_bextri_u64 */ DoesNotAccessMemory,
	/* x86_vcvtph2ps_128 */ DoesNotAccessMemory,		/* x86_vcvtph2ps_128 */ DoesNotAccessMemory,
	/* x86_vcvtph2ps_256 */ DoesNotAccessMemory,		/* x86_vcvtph2ps_256 */ DoesNotAccessMemory,
	/* x86_vcvtps2ph_128 */ DoesNotAccessMemory,		/* x86_vcvtps2ph_128 */ DoesNotAccessMemory,
	/* x86_vcvtps2ph_256 */ DoesNotAccessMemory,		/* x86_vcvtps2ph_256 */ DoesNotAccessMemory,
	/* x86_wrfsbase_32 */ UnknownModRefBehavior,		/* x86_wrfsbase_32 */ UnknownModRefBehavior,
	/* x86_wrfsbase_64 */ UnknownModRefBehavior,		/* x86_wrfsbase_64 */ UnknownModRefBehavior,
	/* x86_wrgsbase_32 */ UnknownModRefBehavior,		/* x86_wrgsbase_32 */ UnknownModRefBehavior,
	/* x86_wrgsbase_64 */ UnknownModRefBehavior,		/* x86_wrgsbase_64 */ UnknownModRefBehavior,
	/* x86_xabort */ UnknownModRefBehavior,		/* x86_xabort */ UnknownModRefBehavior,
	/* x86_xbegin */ UnknownModRefBehavior,		/* x86_xbegin */ UnknownModRefBehavior,
	skipping to change at line 27387		skipping to change at line 35505
	Intrinsic::ID Intrinsic::getIntrinsicForGCCBuiltin(const char *TargetPrefix Str, const char *BuiltinNameStr) {		Intrinsic::ID Intrinsic::getIntrinsicForGCCBuiltin(const char *TargetPrefix Str, const char *BuiltinNameStr) {
	StringRef BuiltinName(BuiltinNameStr);		StringRef BuiltinName(BuiltinNameStr);
	StringRef TargetPrefix(TargetPrefixStr);		StringRef TargetPrefix(TargetPrefixStr);
	/* Target Independent Builtins */ {		/* Target Independent Builtins */ {
	switch (BuiltinName.size()) {		switch (BuiltinName.size()) {
	default: break;		default: break;
	case 10: // 1 string to match.		case 10: // 1 string to match.
	if (memcmp(BuiltinName.data()+0, "__nvvm_h2f", 10))		if (memcmp(BuiltinName.data()+0, "__nvvm_h2f", 10))
	break;		break;
	return Intrinsic::nvvm_h2f; // "__nvvm_h2f"		return Intrinsic::nvvm_h2f; // "__nvvm_h2f"
	case 11: // 2 strings to match.		case 11: // 2 strings to match.
	if (memcmp(BuiltinName.data()+0, "__nvvm_", 7))		if (memcmp(BuiltinName.data()+0, "__nvvm_", 7))
			break;
			switch (BuiltinName[7]) {
			default: break;
			case 'b': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "ar0", 3))
			break;
			return Intrinsic::nvvm_barrier0; // "__nvvm_bar0"
			case 'p': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "rmt", 3))
			break;
			return Intrinsic::nvvm_prmt; // "__nvvm_prmt"
			}
			break;
			case 12: // 5 strings to match.
			if (memcmp(BuiltinName.data()+0, "__nvvm_", 7))
			break;
			switch (BuiltinName[7]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "bs_i", 4))
			break;
			return Intrinsic::nvvm_abs_i; // "__nvvm_abs_i"
			case 'c': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "lz_i", 4))
			break;
			return Intrinsic::nvvm_clz_i; // "__nvvm_clz_i"
			case 'm': // 2 strings to match.
			switch (BuiltinName[8]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(BuiltinName.data()+9, "x_i", 3))
			break;
			return Intrinsic::nvvm_max_i; // "__nvvm_max_i"
			case 'i': // 1 string to match.
			if (memcmp(BuiltinName.data()+9, "n_i", 3))
			break;
			return Intrinsic::nvvm_min_i; // "__nvvm_min_i"
			}
			break;
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "ad_i", 4))
			break;
			return Intrinsic::nvvm_sad_i; // "__nvvm_sad_i"
			}
			break;
			case 13: // 43 strings to match.
			if (memcmp(BuiltinName.data()+0, "__", 2))
			break;
			switch (BuiltinName[2]) {
			default: break;
			case 'n': // 42 strings to match.
			if (memcmp(BuiltinName.data()+3, "vvm_", 4))
			break;
			switch (BuiltinName[7]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "bs_ll", 5))
			break;
			return Intrinsic::nvvm_abs_ll; // "__nvvm_abs_ll"
			case 'b': // 2 strings to match.
			if (memcmp(BuiltinName.data()+8, "rev", 3))
			break;
			switch (BuiltinName[11]) {
			default: break;
			case '3': // 1 string to match.
			if (BuiltinName[12] != '2')
			break;
			return Intrinsic::nvvm_brev32; // "__nvvm_brev32"
			case '6': // 1 string to match.
			if (BuiltinName[12] != '4')
			break;
			return Intrinsic::nvvm_brev64; // "__nvvm_brev64"
			}
			break;
			case 'c': // 3 strings to match.
			switch (BuiltinName[8]) {
			default: break;
			case 'e': // 2 strings to match.
			if (memcmp(BuiltinName.data()+9, "il_", 3))
			break;
			switch (BuiltinName[12]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_ceil_d; // "__nvvm_ceil_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_ceil_f; // "__nvvm_ceil_f"
			}
			break;
			case 'l': // 1 string to match.
			if (memcmp(BuiltinName.data()+9, "z_ll", 4))
			break;
			return Intrinsic::nvvm_clz_ll; // "__nvvm_clz_ll"
			}
			break;
			case 'd': // 10 strings to match.
			if (BuiltinName[8] != '2')
			break;
			switch (BuiltinName[9]) {
			default: break;
			case 'f': // 4 strings to match.
			if (memcmp(BuiltinName.data()+10, "_r", 2))
			break;
			switch (BuiltinName[12]) {
			default: break;
			case 'm': // 1 string to match.
			return Intrinsic::nvvm_d2f_rm; // "__nvvm_d2f_rm"
			case 'n': // 1 string to match.
			return Intrinsic::nvvm_d2f_rn; // "__nvvm_d2f_rn"
			case 'p': // 1 string to match.
			return Intrinsic::nvvm_d2f_rp; // "__nvvm_d2f_rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_d2f_rz; // "__nvvm_d2f_rz"
			}
			break;
			case 'i': // 6 strings to match.
			if (BuiltinName[10] != '_')
			break;
			switch (BuiltinName[11]) {
			default: break;
			case 'h': // 1 string to match.
			if (BuiltinName[12] != 'i')
			break;
			return Intrinsic::nvvm_d2i_hi; // "__nvvm_d2i_hi"
			case 'l': // 1 string to match.
			if (BuiltinName[12] != 'o')
			break;
			return Intrinsic::nvvm_d2i_lo; // "__nvvm_d2i_lo"
			case 'r': // 4 strings to match.
			switch (BuiltinName[12]) {
			default: break;
			case 'm': // 1 string to match.
			return Intrinsic::nvvm_d2i_rm; // "__nvvm_d2i_rm"
			case 'n': // 1 string to match.
			return Intrinsic::nvvm_d2i_rn; // "__nvvm_d2i_rn"
			case 'p': // 1 string to match.
			return Intrinsic::nvvm_d2i_rp; // "__nvvm_d2i_rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_d2i_rz; // "__nvvm_d2i_rz"
			}
			break;
			}
			break;
			}
			break;
			case 'f': // 11 strings to match.
			switch (BuiltinName[8]) {
			default: break;
			case '2': // 5 strings to match.
			switch (BuiltinName[9]) {
			default: break;
			case 'h': // 1 string to match.
			if (memcmp(BuiltinName.data()+10, "_rn", 3))
			break;
			return Intrinsic::nvvm_f2h_rn; // "__nvvm_f2h_rn"
			case 'i': // 4 strings to match.
			if (memcmp(BuiltinName.data()+10, "_r", 2))
			break;
			switch (BuiltinName[12]) {
			default: break;
			case 'm': // 1 string to match.
			return Intrinsic::nvvm_f2i_rm; // "__nvvm_f2i_rm"
			case 'n': // 1 string to match.
			return Intrinsic::nvvm_f2i_rn; // "__nvvm_f2i_rn"
			case 'p': // 1 string to match.
			return Intrinsic::nvvm_f2i_rp; // "__nvvm_f2i_rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_f2i_rz; // "__nvvm_f2i_rz"
			}
			break;
			}
			break;
			case 'a': // 2 strings to match.
			if (memcmp(BuiltinName.data()+9, "bs_", 3))
			break;
			switch (BuiltinName[12]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_fabs_d; // "__nvvm_fabs_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_fabs_f; // "__nvvm_fabs_f"
			}
			break;
			case 'm': // 4 strings to match.
			switch (BuiltinName[9]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(BuiltinName.data()+10, "x_", 2))
			break;
			switch (BuiltinName[12]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_fmax_d; // "__nvvm_fmax_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_fmax_f; // "__nvvm_fmax_f"
			}
			break;
			case 'i': // 2 strings to match.
			if (memcmp(BuiltinName.data()+10, "n_", 2))
			break;
			switch (BuiltinName[12]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_fmin_d; // "__nvvm_fmin_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_fmin_f; // "__nvvm_fmin_f"
			}
			break;
			}
			break;
			}
			break;
			case 'i': // 8 strings to match.
			if (BuiltinName[8] != '2')
			break;
			switch (BuiltinName[9]) {
			default: break;
			case 'd': // 4 strings to match.
			if (memcmp(BuiltinName.data()+10, "_r", 2))
			break;
			switch (BuiltinName[12]) {
			default: break;
			case 'm': // 1 string to match.
			return Intrinsic::nvvm_i2d_rm; // "__nvvm_i2d_rm"
			case 'n': // 1 string to match.
			return Intrinsic::nvvm_i2d_rn; // "__nvvm_i2d_rn"
			case 'p': // 1 string to match.
			return Intrinsic::nvvm_i2d_rp; // "__nvvm_i2d_rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_i2d_rz; // "__nvvm_i2d_rz"
			}
			break;
			case 'f': // 4 strings to match.
			if (memcmp(BuiltinName.data()+10, "_r", 2))
			break;
			switch (BuiltinName[12]) {
			default: break;
			case 'm': // 1 string to match.
			return Intrinsic::nvvm_i2f_rm; // "__nvvm_i2f_rm"
			case 'n': // 1 string to match.
			return Intrinsic::nvvm_i2f_rn; // "__nvvm_i2f_rn"
			case 'p': // 1 string to match.
			return Intrinsic::nvvm_i2f_rp; // "__nvvm_i2f_rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_i2f_rz; // "__nvvm_i2f_rz"
			}
			break;
			}
			break;
			case 'm': // 4 strings to match.
			switch (BuiltinName[8]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(BuiltinName.data()+9, "x_", 2))
			break;
			switch (BuiltinName[11]) {
			default: break;
			case 'l': // 1 string to match.
			if (BuiltinName[12] != 'l')
			break;
			return Intrinsic::nvvm_max_ll; // "__nvvm_max_ll"
			case 'u': // 1 string to match.
			if (BuiltinName[12] != 'i')
			break;
			return Intrinsic::nvvm_max_ui; // "__nvvm_max_ui"
			}
			break;
			case 'i': // 2 strings to match.
			if (memcmp(BuiltinName.data()+9, "n_", 2))
			break;
			switch (BuiltinName[11]) {
			default: break;
			case 'l': // 1 string to match.
			if (BuiltinName[12] != 'l')
			break;
			return Intrinsic::nvvm_min_ll; // "__nvvm_min_ll"
			case 'u': // 1 string to match.
			if (BuiltinName[12] != 'i')
			break;
			return Intrinsic::nvvm_min_ui; // "__nvvm_min_ui"
			}
			break;
			}
			break;
			case 'p': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "opc_i", 5))
			break;
			return Intrinsic::nvvm_popc_i; // "__nvvm_popc_i"
			case 's': // 2 strings to match.
			switch (BuiltinName[8]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(BuiltinName.data()+9, "d_ui", 4))
			break;
			return Intrinsic::nvvm_sad_ui; // "__nvvm_sad_ui"
			case 'q': // 1 string to match.
			if (memcmp(BuiltinName.data()+9, "rt_f", 4))
			break;
			return Intrinsic::nvvm_sqrt_f; // "__nvvm_sqrt_f"
			}
			break;
			}
			break;
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+3, "yncthreads", 10))
			break;
			return Intrinsic::cuda_syncthreads; // "__syncthreads"
			}
			break;
			case 14: // 47 strings to match.
			if (memcmp(BuiltinName.data()+0, "__", 2))
			break;
			switch (BuiltinName[2]) {
			default: break;
			case 'b': // 1 string to match.
			if (memcmp(BuiltinName.data()+3, "uiltin_trap", 11))
			break;
			return Intrinsic::trap; // "__builtin_trap"
			case 'g': // 2 strings to match.
			if (memcmp(BuiltinName.data()+3, "nu_", 3))
			break;
			switch (BuiltinName[6]) {
			default: break;
			case 'f': // 1 string to match.
			if (memcmp(BuiltinName.data()+7, "2h_ieee", 7))
			break;
			return Intrinsic::convert_to_fp16; // "__gnu_f2h_ieee"
			case 'h': // 1 string to match.
			if (memcmp(BuiltinName.data()+7, "2f_ieee", 7))
			break;
			return Intrinsic::convert_from_fp16; // "__gnu_h2f_ieee"
			}
			break;
			case 'n': // 44 strings to match.
			if (memcmp(BuiltinName.data()+3, "vvm_", 4))
			break;
			switch (BuiltinName[7]) {
			default: break;
			case 'b': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "ar0_or", 6))
			break;
			return Intrinsic::nvvm_barrier0_or; // "__nvvm_bar0_or"
			case 'd': // 8 strings to match.
			if (BuiltinName[8] != '2')
			break;
			switch (BuiltinName[9]) {
			default: break;
			case 'l': // 4 strings to match.
			if (memcmp(BuiltinName.data()+10, "l_r", 3))
			break;
			switch (BuiltinName[13]) {
			default: break;
			case 'm': // 1 string to match.
			return Intrinsic::nvvm_d2ll_rm; // "__nvvm_d2ll_rm"
			case 'n': // 1 string to match.
			return Intrinsic::nvvm_d2ll_rn; // "__nvvm_d2ll_rn"
			case 'p': // 1 string to match.
			return Intrinsic::nvvm_d2ll_rp; // "__nvvm_d2ll_rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_d2ll_rz; // "__nvvm_d2ll_rz"
			}
			break;
			case 'u': // 4 strings to match.
			if (memcmp(BuiltinName.data()+10, "i_r", 3))
			break;
			switch (BuiltinName[13]) {
			default: break;
			case 'm': // 1 string to match.
			return Intrinsic::nvvm_d2ui_rm; // "__nvvm_d2ui_rm"
			case 'n': // 1 string to match.
			return Intrinsic::nvvm_d2ui_rn; // "__nvvm_d2ui_rn"
			case 'p': // 1 string to match.
			return Intrinsic::nvvm_d2ui_rp; // "__nvvm_d2ui_rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_d2ui_rz; // "__nvvm_d2ui_rz"
			}
			break;
			}
			break;
			case 'f': // 10 strings to match.
			switch (BuiltinName[8]) {
			default: break;
			case '2': // 8 strings to match.
			switch (BuiltinName[9]) {
			default: break;
			case 'l': // 4 strings to match.
			if (memcmp(BuiltinName.data()+10, "l_r", 3))
			break;
			switch (BuiltinName[13]) {
			default: break;
			case 'm': // 1 string to match.
			return Intrinsic::nvvm_f2ll_rm; // "__nvvm_f2ll_rm"
			case 'n': // 1 string to match.
			return Intrinsic::nvvm_f2ll_rn; // "__nvvm_f2ll_rn"
			case 'p': // 1 string to match.
			return Intrinsic::nvvm_f2ll_rp; // "__nvvm_f2ll_rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_f2ll_rz; // "__nvvm_f2ll_rz"
			}
			break;
			case 'u': // 4 strings to match.
			if (memcmp(BuiltinName.data()+10, "i_r", 3))
			break;
			switch (BuiltinName[13]) {
			default: break;
			case 'm': // 1 string to match.
			return Intrinsic::nvvm_f2ui_rm; // "__nvvm_f2ui_rm"
			case 'n': // 1 string to match.
			return Intrinsic::nvvm_f2ui_rn; // "__nvvm_f2ui_rn"
			case 'p': // 1 string to match.
			return Intrinsic::nvvm_f2ui_rp; // "__nvvm_f2ui_rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_f2ui_rz; // "__nvvm_f2ui_rz"
			}
			break;
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+9, "oor_", 4))
			break;
			switch (BuiltinName[13]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_floor_d; // "__nvvm_floor_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_floor_f; // "__nvvm_floor_f"
			}
			break;
			}
			break;
			case 'l': // 8 strings to match.
			if (memcmp(BuiltinName.data()+8, "l2", 2))
			break;
			switch (BuiltinName[10]) {
			default: break;
			case 'd': // 4 strings to match.
			if (memcmp(BuiltinName.data()+11, "_r", 2))
			break;
			switch (BuiltinName[13]) {
			default: break;
			case 'm': // 1 string to match.
			return Intrinsic::nvvm_ll2d_rm; // "__nvvm_ll2d_rm"
			case 'n': // 1 string to match.
			return Intrinsic::nvvm_ll2d_rn; // "__nvvm_ll2d_rn"
			case 'p': // 1 string to match.
			return Intrinsic::nvvm_ll2d_rp; // "__nvvm_ll2d_rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_ll2d_rz; // "__nvvm_ll2d_rz"
			}
			break;
			case 'f': // 4 strings to match.
			if (memcmp(BuiltinName.data()+11, "_r", 2))
			break;
			switch (BuiltinName[13]) {
			default: break;
			case 'm': // 1 string to match.
			return Intrinsic::nvvm_ll2f_rm; // "__nvvm_ll2f_rm"
			case 'n': // 1 string to match.
			return Intrinsic::nvvm_ll2f_rn; // "__nvvm_ll2f_rn"
			case 'p': // 1 string to match.
			return Intrinsic::nvvm_ll2f_rp; // "__nvvm_ll2f_rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_ll2f_rz; // "__nvvm_ll2f_rz"
			}
			break;
			}
			break;
			case 'm': // 4 strings to match.
			switch (BuiltinName[8]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(BuiltinName.data()+9, "x_ull", 5))
			break;
			return Intrinsic::nvvm_max_ull; // "__nvvm_max_ull"
			case 'i': // 1 string to match.
			if (memcmp(BuiltinName.data()+9, "n_ull", 5))
			break;
			return Intrinsic::nvvm_min_ull; // "__nvvm_min_ull"
			case 'u': // 2 strings to match.
			if (BuiltinName[9] != 'l')
			break;
			switch (BuiltinName[10]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(BuiltinName.data()+11, "4_i", 3))
			break;
			return Intrinsic::nvvm_mul24_i; // "__nvvm_mul24_i"
			case 'h': // 1 string to match.
			if (memcmp(BuiltinName.data()+11, "i_i", 3))
			break;
			return Intrinsic::nvvm_mulhi_i; // "__nvvm_mulhi_i"
			}
			break;
			}
			break;
			case 'p': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "opc_ll", 6))
			break;
			return Intrinsic::nvvm_popc_ll; // "__nvvm_popc_ll"
			case 'r': // 2 strings to match.
			if (memcmp(BuiltinName.data()+8, "ound_", 5))
			break;
			switch (BuiltinName[13]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_round_d; // "__nvvm_round_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_round_f; // "__nvvm_round_f"
			}
			break;
			case 't': // 2 strings to match.
			if (memcmp(BuiltinName.data()+8, "runc_", 5))
			break;
			switch (BuiltinName[13]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_trunc_d; // "__nvvm_trunc_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_trunc_f; // "__nvvm_trunc_f"
			}
			break;
			case 'u': // 8 strings to match.
			if (memcmp(BuiltinName.data()+8, "i2", 2))
			break;
			switch (BuiltinName[10]) {
			default: break;
			case 'd': // 4 strings to match.
			if (memcmp(BuiltinName.data()+11, "_r", 2))
			break;
			switch (BuiltinName[13]) {
			default: break;
			case 'm': // 1 string to match.
			return Intrinsic::nvvm_ui2d_rm; // "__nvvm_ui2d_rm"
			case 'n': // 1 string to match.
			return Intrinsic::nvvm_ui2d_rn; // "__nvvm_ui2d_rn"
			case 'p': // 1 string to match.
			return Intrinsic::nvvm_ui2d_rp; // "__nvvm_ui2d_rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_ui2d_rz; // "__nvvm_ui2d_rz"
			}
			break;
			case 'f': // 4 strings to match.
			if (memcmp(BuiltinName.data()+11, "_r", 2))
			break;
			switch (BuiltinName[13]) {
			default: break;
			case 'm': // 1 string to match.
			return Intrinsic::nvvm_ui2f_rm; // "__nvvm_ui2f_rm"
			case 'n': // 1 string to match.
			return Intrinsic::nvvm_ui2f_rn; // "__nvvm_ui2f_rn"
			case 'p': // 1 string to match.
			return Intrinsic::nvvm_ui2f_rp; // "__nvvm_ui2f_rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_ui2f_rz; // "__nvvm_ui2f_rz"
			}
			break;
			}
			break;
			}
			break;
			}
			break;
			case 15: // 61 strings to match.
			if (memcmp(BuiltinName.data()+0, "__nvvm_", 7))
			break;
			switch (BuiltinName[7]) {
			default: break;
			case 'a': // 8 strings to match.
			if (memcmp(BuiltinName.data()+8, "dd_r", 4))
			break;
			switch (BuiltinName[12]) {
			default: break;
			case 'm': // 2 strings to match.
			if (BuiltinName[13] != '_')
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_add_rm_d; // "__nvvm_add_rm_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_add_rm_f; // "__nvvm_add_rm_f"
			}
			break;
			case 'n': // 2 strings to match.
			if (BuiltinName[13] != '_')
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_add_rn_d; // "__nvvm_add_rn_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_add_rn_f; // "__nvvm_add_rn_f"
			}
			break;
			case 'p': // 2 strings to match.
			if (BuiltinName[13] != '_')
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_add_rp_d; // "__nvvm_add_rp_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_add_rp_f; // "__nvvm_add_rp_f"
			}
			break;
			case 'z': // 2 strings to match.
			if (BuiltinName[13] != '_')
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_add_rz_d; // "__nvvm_add_rz_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_add_rz_f; // "__nvvm_add_rz_f"
			}
			break;
			}
			break;
			case 'b': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "ar0_and", 7))
			break;
			return Intrinsic::nvvm_barrier0_and; // "__nvvm_bar0_and"
			case 'd': // 12 strings to match.
			switch (BuiltinName[8]) {
			default: break;
			case '2': // 4 strings to match.
			if (memcmp(BuiltinName.data()+9, "ull_r", 5))
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'm': // 1 string to match.
			return Intrinsic::nvvm_d2ull_rm; // "__nvvm_d2ull_rm"
			case 'n': // 1 string to match.
			return Intrinsic::nvvm_d2ull_rn; // "__nvvm_d2ull_rn"
			case 'p': // 1 string to match.
			return Intrinsic::nvvm_d2ull_rp; // "__nvvm_d2ull_rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_d2ull_rz; // "__nvvm_d2ull_rz"
			}
			break;
			case 'i': // 8 strings to match.
			if (memcmp(BuiltinName.data()+9, "v_r", 3))
			break;
			switch (BuiltinName[12]) {
			default: break;
			case 'm': // 2 strings to match.
			if (BuiltinName[13] != '_')
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_div_rm_d; // "__nvvm_div_rm_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_div_rm_f; // "__nvvm_div_rm_f"
			}
			break;
			case 'n': // 2 strings to match.
			if (BuiltinName[13] != '_')
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_div_rn_d; // "__nvvm_div_rn_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_div_rn_f; // "__nvvm_div_rn_f"
			}
			break;
			case 'p': // 2 strings to match.
			if (BuiltinName[13] != '_')
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_div_rp_d; // "__nvvm_div_rp_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_div_rp_f; // "__nvvm_div_rp_f"
			}
			break;
			case 'z': // 2 strings to match.
			if (BuiltinName[13] != '_')
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_div_rz_d; // "__nvvm_div_rz_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_div_rz_f; // "__nvvm_div_rz_f"
			}
			break;
			}
			break;
			}
			break;
			case 'f': // 12 strings to match.
			switch (BuiltinName[8]) {
			default: break;
			case '2': // 4 strings to match.
			if (memcmp(BuiltinName.data()+9, "ull_r", 5))
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'm': // 1 string to match.
			return Intrinsic::nvvm_f2ull_rm; // "__nvvm_f2ull_rm"
			case 'n': // 1 string to match.
			return Intrinsic::nvvm_f2ull_rn; // "__nvvm_f2ull_rn"
			case 'p': // 1 string to match.
			return Intrinsic::nvvm_f2ull_rp; // "__nvvm_f2ull_rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_f2ull_rz; // "__nvvm_f2ull_rz"
			}
			break;
			case 'm': // 8 strings to match.
			if (memcmp(BuiltinName.data()+9, "a_r", 3))
			break;
			switch (BuiltinName[12]) {
			default: break;
			case 'm': // 2 strings to match.
			if (BuiltinName[13] != '_')
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_fma_rm_d; // "__nvvm_fma_rm_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_fma_rm_f; // "__nvvm_fma_rm_f"
			}
			break;
			case 'n': // 2 strings to match.
			if (BuiltinName[13] != '_')
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_fma_rn_d; // "__nvvm_fma_rn_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_fma_rn_f; // "__nvvm_fma_rn_f"
			}
			break;
			case 'p': // 2 strings to match.
			if (BuiltinName[13] != '_')
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_fma_rp_d; // "__nvvm_fma_rp_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_fma_rp_f; // "__nvvm_fma_rp_f"
			}
			break;
			case 'z': // 2 strings to match.
			if (BuiltinName[13] != '_')
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_fma_rz_d; // "__nvvm_fma_rz_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_fma_rz_f; // "__nvvm_fma_rz_f"
			}
			break;
			}
			break;
			}
			break;
			case 'l': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "ohi_i2d", 7))
			break;
			return Intrinsic::nvvm_lohi_i2d; // "__nvvm_lohi_i2d"
			case 'm': // 11 strings to match.
			if (memcmp(BuiltinName.data()+8, "ul", 2))
			break;
			switch (BuiltinName[10]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(BuiltinName.data()+11, "4_ui", 4))
			break;
			return Intrinsic::nvvm_mul24_ui; // "__nvvm_mul24_ui"
			case '_': // 8 strings to match.
			if (BuiltinName[11] != 'r')
			break;
			switch (BuiltinName[12]) {
			default: break;
			case 'm': // 2 strings to match.
			if (BuiltinName[13] != '_')
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_mul_rm_d; // "__nvvm_mul_rm_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_mul_rm_f; // "__nvvm_mul_rm_f"
			}
			break;
			case 'n': // 2 strings to match.
			if (BuiltinName[13] != '_')
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_mul_rn_d; // "__nvvm_mul_rn_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_mul_rn_f; // "__nvvm_mul_rn_f"
			}
			break;
			case 'p': // 2 strings to match.
			if (BuiltinName[13] != '_')
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_mul_rp_d; // "__nvvm_mul_rp_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_mul_rp_f; // "__nvvm_mul_rp_f"
			}
			break;
			case 'z': // 2 strings to match.
			if (BuiltinName[13] != '_')
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_mul_rz_d; // "__nvvm_mul_rz_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_mul_rz_f; // "__nvvm_mul_rz_f"
			}
			break;
			}
			break;
			case 'h': // 2 strings to match.
			if (memcmp(BuiltinName.data()+11, "i_", 2))
			break;
			switch (BuiltinName[13]) {
			default: break;
			case 'l': // 1 string to match.
			if (BuiltinName[14] != 'l')
			break;
			return Intrinsic::nvvm_mulhi_ll; // "__nvvm_mulhi_ll"
			case 'u': // 1 string to match.
			if (BuiltinName[14] != 'i')
			break;
			return Intrinsic::nvvm_mulhi_ui; // "__nvvm_mulhi_ui"
			}
			break;
			}
			break;
			case 'r': // 8 strings to match.
			if (memcmp(BuiltinName.data()+8, "cp_r", 4))
			break;
			switch (BuiltinName[12]) {
			default: break;
			case 'm': // 2 strings to match.
			if (BuiltinName[13] != '_')
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_rcp_rm_d; // "__nvvm_rcp_rm_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_rcp_rm_f; // "__nvvm_rcp_rm_f"
			}
			break;
			case 'n': // 2 strings to match.
			if (BuiltinName[13] != '_')
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_rcp_rn_d; // "__nvvm_rcp_rn_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_rcp_rn_f; // "__nvvm_rcp_rn_f"
			}
			break;
			case 'p': // 2 strings to match.
			if (BuiltinName[13] != '_')
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_rcp_rp_d; // "__nvvm_rcp_rp_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_rcp_rp_f; // "__nvvm_rcp_rp_f"
			}
			break;
			case 'z': // 2 strings to match.
			if (BuiltinName[13] != '_')
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_rcp_rz_d; // "__nvvm_rcp_rz_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_rcp_rz_f; // "__nvvm_rcp_rz_f"
			}
			break;
			}
			break;
			case 'u': // 8 strings to match.
			if (memcmp(BuiltinName.data()+8, "ll2", 3))
			break;
			switch (BuiltinName[11]) {
			default: break;
			case 'd': // 4 strings to match.
			if (memcmp(BuiltinName.data()+12, "_r", 2))
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'm': // 1 string to match.
			return Intrinsic::nvvm_ull2d_rm; // "__nvvm_ull2d_rm"
			case 'n': // 1 string to match.
			return Intrinsic::nvvm_ull2d_rn; // "__nvvm_ull2d_rn"
			case 'p': // 1 string to match.
			return Intrinsic::nvvm_ull2d_rp; // "__nvvm_ull2d_rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_ull2d_rz; // "__nvvm_ull2d_rz"
			}
			break;
			case 'f': // 4 strings to match.
			if (memcmp(BuiltinName.data()+12, "_r", 2))
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'm': // 1 string to match.
			return Intrinsic::nvvm_ull2f_rm; // "__nvvm_ull2f_rm"
			case 'n': // 1 string to match.
			return Intrinsic::nvvm_ull2f_rn; // "__nvvm_ull2f_rn"
			case 'p': // 1 string to match.
			return Intrinsic::nvvm_ull2f_rp; // "__nvvm_ull2f_rp"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_ull2f_rz; // "__nvvm_ull2f_rz"
			}
			break;
			}
			break;
			}
			break;
			case 16: // 11 strings to match.
			if (memcmp(BuiltinName.data()+0, "__nvvm_", 7))
			break;
			switch (BuiltinName[7]) {
			default: break;
			case 'b': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "ar0_popc", 8))
			break;
			return Intrinsic::nvvm_barrier0_popc; // "__nvvm_bar0_popc"
			case 'm': // 2 strings to match.
			switch (BuiltinName[8]) {
			default: break;
			case 'e': // 1 string to match.
			if (memcmp(BuiltinName.data()+9, "mbar_gl", 7))
			break;
			return Intrinsic::nvvm_membar_gl; // "__nvvm_membar_gl"
			case 'u': // 1 string to match.
			if (memcmp(BuiltinName.data()+9, "lhi_ull", 7))
			break;
			return Intrinsic::nvvm_mulhi_ull; // "__nvvm_mulhi_ull"
			}
			break;
			case 's': // 8 strings to match.
			if (memcmp(BuiltinName.data()+8, "qrt_r", 5))
			break;
			switch (BuiltinName[13]) {
			default: break;
			case 'm': // 2 strings to match.
			if (BuiltinName[14] != '_')
			break;
			switch (BuiltinName[15]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_sqrt_rm_d; // "__nvvm_sqrt_rm_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_sqrt_rm_f; // "__nvvm_sqrt_rm_f"
			}
			break;
			case 'n': // 2 strings to match.
			if (BuiltinName[14] != '_')
			break;
			switch (BuiltinName[15]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_sqrt_rn_d; // "__nvvm_sqrt_rn_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_sqrt_rn_f; // "__nvvm_sqrt_rn_f"
			}
			break;
			case 'p': // 2 strings to match.
			if (BuiltinName[14] != '_')
			break;
			switch (BuiltinName[15]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_sqrt_rp_d; // "__nvvm_sqrt_rp_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_sqrt_rp_f; // "__nvvm_sqrt_rp_f"
			}
			break;
			case 'z': // 2 strings to match.
			if (BuiltinName[14] != '_')
			break;
			switch (BuiltinName[15]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_sqrt_rz_d; // "__nvvm_sqrt_rz_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_sqrt_rz_f; // "__nvvm_sqrt_rz_f"
			}
			break;
			}
			break;
			}
			break;
			case 17: // 17 strings to match.
			if (memcmp(BuiltinName.data()+0, "__nvvm_", 7))
			break;
			switch (BuiltinName[7]) {
			default: break;
			case 'c': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "eil_ftz_f", 9))
			break;
			return Intrinsic::nvvm_ceil_ftz_f; // "__nvvm_ceil_ftz_f"
			case 'd': // 4 strings to match.
			if (memcmp(BuiltinName.data()+8, "2f_r", 4))
			break;
			switch (BuiltinName[12]) {
			default: break;
			case 'm': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz", 4))
			break;
			return Intrinsic::nvvm_d2f_rm_ftz; // "__nvvm_d2f_rm_ftz"
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz", 4))
			break;
			return Intrinsic::nvvm_d2f_rn_ftz; // "__nvvm_d2f_rn_ftz"
			case 'p': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz", 4))
			break;
			return Intrinsic::nvvm_d2f_rp_ftz; // "__nvvm_d2f_rp_ftz"
			case 'z': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz", 4))
			break;
			return Intrinsic::nvvm_d2f_rz_ftz; // "__nvvm_d2f_rz_ftz"
			}
			break;
			case 'f': // 8 strings to match.
			switch (BuiltinName[8]) {
			default: break;
			case '2': // 5 strings to match.
			switch (BuiltinName[9]) {
			default: break;
			case 'h': // 1 string to match.
			if (memcmp(BuiltinName.data()+10, "_rn_ftz", 7))
			break;
			return Intrinsic::nvvm_f2h_rn_ftz; // "__nvvm_f2h_rn_ftz"
			case 'i': // 4 strings to match.
			if (memcmp(BuiltinName.data()+10, "_r", 2))
			break;
			switch (BuiltinName[12]) {
			default: break;
			case 'm': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz", 4))
			break;
			return Intrinsic::nvvm_f2i_rm_ftz; // "__nvvm_f2i_rm_ftz"
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz", 4))
			break;
			return Intrinsic::nvvm_f2i_rn_ftz; // "__nvvm_f2i_rn_ftz"
			case 'p': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz", 4))
			break;
			return Intrinsic::nvvm_f2i_rp_ftz; // "__nvvm_f2i_rp_ftz"
			case 'z': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz", 4))
			break;
			return Intrinsic::nvvm_f2i_rz_ftz; // "__nvvm_f2i_rz_ftz"
			}
			break;
			}
			break;
			case 'a': // 1 string to match.
			if (memcmp(BuiltinName.data()+9, "bs_ftz_f", 8))
			break;
			return Intrinsic::nvvm_fabs_ftz_f; // "__nvvm_fabs_ftz_f"
			case 'm': // 2 strings to match.
			switch (BuiltinName[9]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(BuiltinName.data()+10, "x_ftz_f", 7))
			break;
			return Intrinsic::nvvm_fmax_ftz_f; // "__nvvm_fmax_ftz_f"
			case 'i': // 1 string to match.
			if (memcmp(BuiltinName.data()+10, "n_ftz_f", 7))
			break;
			return Intrinsic::nvvm_fmin_ftz_f; // "__nvvm_fmin_ftz_f"
			}
			break;
			}
			break;
			case 'm': // 2 strings to match.
			if (memcmp(BuiltinName.data()+8, "embar_", 6))
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'c': // 1 string to match.
			if (memcmp(BuiltinName.data()+15, "ta", 2))
			break;
			return Intrinsic::nvvm_membar_cta; // "__nvvm_membar_cta"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+15, "ys", 2))
			break;
			return Intrinsic::nvvm_membar_sys; // "__nvvm_membar_sys"
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(BuiltinName.data()+8, "aturate_", 8))
			break;
			switch (BuiltinName[16]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_saturate_d; // "__nvvm_saturate_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_saturate_f; // "__nvvm_saturate_f"
			}
			break;
			}
			break;
			case 18: // 13 strings to match.
			if (memcmp(BuiltinName.data()+0, "__nvvm_", 7))
			break;
			switch (BuiltinName[7]) {
			default: break;
			case 'b': // 2 strings to match.
			if (memcmp(BuiltinName.data()+8, "itcast_", 7))
			break;
			switch (BuiltinName[15]) {
			default: break;
			case 'f': // 1 string to match.
			if (memcmp(BuiltinName.data()+16, "2i", 2))
			break;
			return Intrinsic::nvvm_bitcast_f2i; // "__nvvm_bitcast_f2i"
			case 'i': // 1 string to match.
			if (memcmp(BuiltinName.data()+16, "2f", 2))
			break;
			return Intrinsic::nvvm_bitcast_i2f; // "__nvvm_bitcast_i2f"
			}
			break;
			case 'f': // 9 strings to match.
			switch (BuiltinName[8]) {
			default: break;
			case '2': // 8 strings to match.
			switch (BuiltinName[9]) {
			default: break;
			case 'l': // 4 strings to match.
			if (memcmp(BuiltinName.data()+10, "l_r", 3))
			break;
			switch (BuiltinName[13]) {
			default: break;
			case 'm': // 1 string to match.
			if (memcmp(BuiltinName.data()+14, "_ftz", 4))
			break;
			return Intrinsic::nvvm_f2ll_rm_ftz; // "__nvvm_f2ll_rm_
			ftz"
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+14, "_ftz", 4))
			break;
			return Intrinsic::nvvm_f2ll_rn_ftz; // "__nvvm_f2ll_rn_
			ftz"
			case 'p': // 1 string to match.
			if (memcmp(BuiltinName.data()+14, "_ftz", 4))
			break;
			return Intrinsic::nvvm_f2ll_rp_ftz; // "__nvvm_f2ll_rp_
			ftz"
			case 'z': // 1 string to match.
			if (memcmp(BuiltinName.data()+14, "_ftz", 4))
			break;
			return Intrinsic::nvvm_f2ll_rz_ftz; // "__nvvm_f2ll_rz_
			ftz"
			}
			break;
			case 'u': // 4 strings to match.
			if (memcmp(BuiltinName.data()+10, "i_r", 3))
			break;
			switch (BuiltinName[13]) {
			default: break;
			case 'm': // 1 string to match.
			if (memcmp(BuiltinName.data()+14, "_ftz", 4))
			break;
			return Intrinsic::nvvm_f2ui_rm_ftz; // "__nvvm_f2ui_rm_
			ftz"
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+14, "_ftz", 4))
			break;
			return Intrinsic::nvvm_f2ui_rn_ftz; // "__nvvm_f2ui_rn_
			ftz"
			case 'p': // 1 string to match.
			if (memcmp(BuiltinName.data()+14, "_ftz", 4))
			break;
			return Intrinsic::nvvm_f2ui_rp_ftz; // "__nvvm_f2ui_rp_
			ftz"
			case 'z': // 1 string to match.
			if (memcmp(BuiltinName.data()+14, "_ftz", 4))
			break;
			return Intrinsic::nvvm_f2ui_rz_ftz; // "__nvvm_f2ui_rz_
			ftz"
			}
			break;
			}
			break;
			case 'l': // 1 string to match.
			if (memcmp(BuiltinName.data()+9, "oor_ftz_f", 9))
			break;
			return Intrinsic::nvvm_floor_ftz_f; // "__nvvm_floor_ftz_f"
			}
			break;
			case 'r': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "ound_ftz_f", 10))
			break;
			return Intrinsic::nvvm_round_ftz_f; // "__nvvm_round_ftz_f"
			case 't': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "runc_ftz_f", 10))
			break;
			return Intrinsic::nvvm_trunc_ftz_f; // "__nvvm_trunc_ftz_f"
			}
			break;
			case 19: // 34 strings to match.
			if (memcmp(BuiltinName.data()+0, "__", 2))
			break;
			switch (BuiltinName[2]) {
			default: break;
			case 'b': // 1 string to match.
			if (memcmp(BuiltinName.data()+3, "uiltin_debugtrap", 16))
			break;
			return Intrinsic::debugtrap; // "__builtin_debugtrap"
			case 'n': // 33 strings to match.
			if (memcmp(BuiltinName.data()+3, "vvm_", 4))
			break;
			switch (BuiltinName[7]) {
			default: break;
			case 'a': // 4 strings to match.
			if (memcmp(BuiltinName.data()+8, "dd_r", 4))
			break;
			switch (BuiltinName[12]) {
			default: break;
			case 'm': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_add_rm_ftz_f; // "__nvvm_add_rm_ftz_f"
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_add_rn_ftz_f; // "__nvvm_add_rn_ftz_f"
			case 'p': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_add_rp_ftz_f; // "__nvvm_add_rp_ftz_f"
			case 'z': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_add_rz_ftz_f; // "__nvvm_add_rz_ftz_f"
			}
			break;
			case 'b': // 2 strings to match.
			if (memcmp(BuiltinName.data()+8, "itcast_", 7))
			break;
			switch (BuiltinName[15]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+16, "2ll", 3))
			break;
			return Intrinsic::nvvm_bitcast_d2ll; // "__nvvm_bitcast_d2ll"
			case 'l': // 1 string to match.
			if (memcmp(BuiltinName.data()+16, "l2d", 3))
			break;
			return Intrinsic::nvvm_bitcast_ll2d; // "__nvvm_bitcast_ll2d"
			}
			break;
			case 'c': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "os_approx_f", 11))
			break;
			return Intrinsic::nvvm_cos_approx_f; // "__nvvm_cos_approx_f"
			case 'd': // 5 strings to match.
			if (memcmp(BuiltinName.data()+8, "iv_", 3))
			break;
			switch (BuiltinName[11]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(BuiltinName.data()+12, "pprox_f", 7))
			break;
			return Intrinsic::nvvm_div_approx_f; // "__nvvm_div_approx_f"
			case 'r': // 4 strings to match.
			switch (BuiltinName[12]) {
			default: break;
			case 'm': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_div_rm_ftz_f; // "__nvvm_div_rm_f
			tz_f"
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_div_rn_ftz_f; // "__nvvm_div_rn_f
			tz_f"
			case 'p': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_div_rp_ftz_f; // "__nvvm_div_rp_f
			tz_f"
			case 'z': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_div_rz_ftz_f; // "__nvvm_div_rz_f
			tz_f"
			}
			break;
			}
			break;
			case 'e': // 2 strings to match.
			if (memcmp(BuiltinName.data()+8, "x2_approx_", 10))
			break;
			switch (BuiltinName[18]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_ex2_approx_d; // "__nvvm_ex2_approx_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_ex2_approx_f; // "__nvvm_ex2_approx_f"
			}
			break;
			case 'f': // 8 strings to match.
			switch (BuiltinName[8]) {
			default: break;
			case '2': // 4 strings to match.
			if (memcmp(BuiltinName.data()+9, "ull_r", 5))
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'm': // 1 string to match.
			if (memcmp(BuiltinName.data()+15, "_ftz", 4))
			break;
			return Intrinsic::nvvm_f2ull_rm_ftz; // "__nvvm_f2ull_rm
			_ftz"
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+15, "_ftz", 4))
			break;
			return Intrinsic::nvvm_f2ull_rn_ftz; // "__nvvm_f2ull_rn
			_ftz"
			case 'p': // 1 string to match.
			if (memcmp(BuiltinName.data()+15, "_ftz", 4))
			break;
			return Intrinsic::nvvm_f2ull_rp_ftz; // "__nvvm_f2ull_rp
			_ftz"
			case 'z': // 1 string to match.
			if (memcmp(BuiltinName.data()+15, "_ftz", 4))
			break;
			return Intrinsic::nvvm_f2ull_rz_ftz; // "__nvvm_f2ull_rz
			_ftz"
			}
			break;
			case 'm': // 4 strings to match.
			if (memcmp(BuiltinName.data()+9, "a_r", 3))
			break;
			switch (BuiltinName[12]) {
			default: break;
			case 'm': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_fma_rm_ftz_f; // "__nvvm_fma_rm_f
			tz_f"
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_fma_rn_ftz_f; // "__nvvm_fma_rn_f
			tz_f"
			case 'p': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_fma_rp_ftz_f; // "__nvvm_fma_rp_f
			tz_f"
			case 'z': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_fma_rz_ftz_f; // "__nvvm_fma_rz_f
			tz_f"
			}
			break;
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+8, "g2_approx_", 10))
			break;
			switch (BuiltinName[18]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_lg2_approx_d; // "__nvvm_lg2_approx_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_lg2_approx_f; // "__nvvm_lg2_approx_f"
			}
			break;
			case 'm': // 4 strings to match.
			if (memcmp(BuiltinName.data()+8, "ul_r", 4))
			break;
			switch (BuiltinName[12]) {
			default: break;
			case 'm': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_mul_rm_ftz_f; // "__nvvm_mul_rm_ftz_f"
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_mul_rn_ftz_f; // "__nvvm_mul_rn_ftz_f"
			case 'p': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_mul_rp_ftz_f; // "__nvvm_mul_rp_ftz_f"
			case 'z': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_mul_rz_ftz_f; // "__nvvm_mul_rz_ftz_f"
			}
			break;
			case 'r': // 4 strings to match.
			if (memcmp(BuiltinName.data()+8, "cp_r", 4))
			break;
			switch (BuiltinName[12]) {
			default: break;
			case 'm': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_rcp_rm_ftz_f; // "__nvvm_rcp_rm_ftz_f"
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_rcp_rn_ftz_f; // "__nvvm_rcp_rn_ftz_f"
			case 'p': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_rcp_rp_ftz_f; // "__nvvm_rcp_rp_ftz_f"
			case 'z': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_rcp_rz_ftz_f; // "__nvvm_rcp_rz_ftz_f"
			}
			break;
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "in_approx_f", 11))
			break;
			return Intrinsic::nvvm_sin_approx_f; // "__nvvm_sin_approx_f"
			}
			break;
			}
			break;
			case 20: // 7 strings to match.
			if (memcmp(BuiltinName.data()+0, "__", 2))
			break;
			switch (BuiltinName[2]) {
			default: break;
			case 'b': // 2 strings to match.
			if (memcmp(BuiltinName.data()+3, "uiltin_", 7))
			break;
			switch (BuiltinName[10]) {
			default: break;
			case 'f': // 1 string to match.
			if (memcmp(BuiltinName.data()+11, "lt_rounds", 9))
			break;
			return Intrinsic::flt_rounds; // "__builtin_flt_rounds"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+11, "tack_save", 9))
			break;
			return Intrinsic::stacksave; // "__builtin_stack_save"
			}
			break;
			case 'n': // 5 strings to match.
			if (memcmp(BuiltinName.data()+3, "vvm_sqrt_", 9))
			break;
			switch (BuiltinName[12]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(BuiltinName.data()+13, "pprox_f", 7))
			break;
			return Intrinsic::nvvm_sqrt_approx_f; // "__nvvm_sqrt_approx_f"
			case 'r': // 4 strings to match.
			switch (BuiltinName[13]) {
			default: break;
			case 'm': // 1 string to match.
			if (memcmp(BuiltinName.data()+14, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_sqrt_rm_ftz_f; // "__nvvm_sqrt_rm_
			ftz_f"
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+14, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_sqrt_rn_ftz_f; // "__nvvm_sqrt_rn_
			ftz_f"
			case 'p': // 1 string to match.
			if (memcmp(BuiltinName.data()+14, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_sqrt_rp_ftz_f; // "__nvvm_sqrt_rp_
			ftz_f"
			case 'z': // 1 string to match.
			if (memcmp(BuiltinName.data()+14, "_ftz_f", 6))
			break;
			return Intrinsic::nvvm_sqrt_rz_ftz_f; // "__nvvm_sqrt_rz_
			ftz_f"
			}
			break;
			}
			break;
			}
			break;
			case 21: // 23 strings to match.
			if (memcmp(BuiltinName.data()+0, "__", 2))
			break;
			switch (BuiltinName[2]) {
			default: break;
			case 'b': // 20 strings to match.
			if (memcmp(BuiltinName.data()+3, "uiltin_", 7))
			break;
			switch (BuiltinName[10]) {
			default: break;
			case 'i': // 18 strings to match.
			if (memcmp(BuiltinName.data()+11, "a32_vp", 6))
			break;
			switch (BuiltinName[17]) {
			default: break;
			case 'c': // 5 strings to match.
			switch (BuiltinName[18]) {
			default: break;
			case 'm': // 1 string to match.
			if (memcmp(BuiltinName.data()+19, "ov", 2))
			break;
			return Intrinsic::x86_xop_vpcmov; // "__builtin_ia32_vpcmov"
			case 'o': // 4 strings to match.
			if (BuiltinName[19] != 'm')
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_xop_vpcomb; // "__builtin_ia32_
			vpcomb"
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vpcomd; // "__builtin_ia32_
			vpcomd"
			case 'q': // 1 string to match.
			return Intrinsic::x86_xop_vpcomq; // "__builtin_ia32_
			vpcomq"
			case 'w': // 1 string to match.
			return Intrinsic::x86_xop_vpcomw; // "__builtin_ia32_
			vpcomw"
			}
			break;
			}
			break;
			case 'p': // 1 string to match.
			if (memcmp(BuiltinName.data()+18, "erm", 3))
			break;
			return Intrinsic::x86_xop_vpperm; // "__builtin_ia32_vpperm"
			case 'r': // 4 strings to match.
			if (memcmp(BuiltinName.data()+18, "ot", 2))
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_xop_vprotb; // "__builtin_ia32_vprotb"
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vprotd; // "__builtin_ia32_vprotd"
			case 'q': // 1 string to match.
			return Intrinsic::x86_xop_vprotq; // "__builtin_ia32_vprotq"
			case 'w': // 1 string to match.
			return Intrinsic::x86_xop_vprotw; // "__builtin_ia32_vprotw"
			}
			break;
			case 's': // 8 strings to match.
			if (BuiltinName[18] != 'h')
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'a': // 4 strings to match.
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_xop_vpshab; // "__builtin_ia32_
			vpshab"
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vpshad; // "__builtin_ia32_
			vpshad"
			case 'q': // 1 string to match.
			return Intrinsic::x86_xop_vpshaq; // "__builtin_ia32_
			vpshaq"
			case 'w': // 1 string to match.
			return Intrinsic::x86_xop_vpshaw; // "__builtin_ia32_
			vpshaw"
			}
			break;
			case 'l': // 4 strings to match.
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_xop_vpshlb; // "__builtin_ia32_
			vpshlb"
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vpshld; // "__builtin_ia32_
			vpshld"
			case 'q': // 1 string to match.
			return Intrinsic::x86_xop_vpshlq; // "__builtin_ia32_
			vpshlq"
			case 'w': // 1 string to match.
			return Intrinsic::x86_xop_vpshlw; // "__builtin_ia32_
			vpshlw"
			}
			break;
			}
			break;
			}
			break;
			case 'o': // 1 string to match.
			if (memcmp(BuiltinName.data()+11, "bject_size", 10))
			break;
			return Intrinsic::objectsize; // "__builtin_object_size"
			case 'u': // 1 string to match.
			if (memcmp(BuiltinName.data()+11, "nwind_init", 10))
			break;
			return Intrinsic::eh_unwind_init; // "__builtin_unwind_init"
			}
			break;
			case 'n': // 3 strings to match.
			if (memcmp(BuiltinName.data()+3, "vvm_", 4))
			break;
			switch (BuiltinName[7]) {
			default: break;
			case 'r': // 2 strings to match.
			if (memcmp(BuiltinName.data()+8, "sqrt_approx_", 12))
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::nvvm_rsqrt_approx_d; // "__nvvm_rsqrt_ap
			prox_d"
			case 'f': // 1 string to match.
			return Intrinsic::nvvm_rsqrt_approx_f; // "__nvvm_rsqrt_ap
			prox_f"
			}
			break;
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "aturate_ftz_f", 13))
			break;
			return Intrinsic::nvvm_saturate_ftz_f; // "__nvvm_saturate_ftz_f"
			}
			break;
			}
			break;
			case 22: // 17 strings to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_", 10))
			break;
			switch (BuiltinName[10]) {
			default: break;
			case 'i': // 12 strings to match.
			if (memcmp(BuiltinName.data()+11, "a32_v", 5))
			break;
			switch (BuiltinName[16]) {
			default: break;
			case 'f': // 4 strings to match.
			if (memcmp(BuiltinName.data()+17, "rcz", 3))
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'p': // 2 strings to match.
			switch (BuiltinName[21]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vfrcz_pd; // "__builtin_ia32_
			vfrczpd"
			case 's': // 1 string to match.
			return Intrinsic::x86_xop_vfrcz_ps; // "__builtin_ia32_
			vfrczps"
			}
			break;
			case 's': // 2 strings to match.
			switch (BuiltinName[21]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vfrcz_sd; // "__builtin_ia32_
			vfrczsd"
			case 's': // 1 string to match.
			return Intrinsic::x86_xop_vfrcz_ss; // "__builtin_ia32_
			vfrczss"
			}
			break;
			}
			break;
			case 'p': // 8 strings to match.
			switch (BuiltinName[17]) {
			default: break;
			case 'c': // 4 strings to match.
			if (memcmp(BuiltinName.data()+18, "omu", 3))
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::x86_xop_vpcomub; // "__builtin_ia32_vpcomub"
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vpcomud; // "__builtin_ia32_vpcomud"
			case 'q': // 1 string to match.
			return Intrinsic::x86_xop_vpcomuq; // "__builtin_ia32_vpcomuq"
			case 'w': // 1 string to match.
			return Intrinsic::x86_xop_vpcomuw; // "__builtin_ia32_vpcomuw"
			}
			break;
			case 'r': // 4 strings to match.
			if (memcmp(BuiltinName.data()+18, "ot", 2))
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			if (BuiltinName[21] != 'i')
			break;
			return Intrinsic::x86_xop_vprotbi; // "__builtin_ia32_vprotbi"
			case 'd': // 1 string to match.
			if (BuiltinName[21] != 'i')
			break;
			return Intrinsic::x86_xop_vprotdi; // "__builtin_ia32_vprotdi"
			case 'q': // 1 string to match.
			if (BuiltinName[21] != 'i')
			break;
			return Intrinsic::x86_xop_vprotqi; // "__builtin_ia32_vprotqi"
			case 'w': // 1 string to match.
			if (BuiltinName[21] != 'i')
			break;
			return Intrinsic::x86_xop_vprotwi; // "__builtin_ia32_vprotwi"
			}
			break;
			}
			break;
			}
			break;
			case 'p': // 5 strings to match.
			if (memcmp(BuiltinName.data()+11, "tx_", 3))
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'b': // 1 string to match.
			if (memcmp(BuiltinName.data()+15, "ar_sync", 7))
			break;
			return Intrinsic::ptx_bar_sync; // "__builtin_ptx_bar_sync"
			case 'r': // 4 strings to match.
			if (memcmp(BuiltinName.data()+15, "ead_pm", 6))
			break;
			switch (BuiltinName[21]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::ptx_read_pm0; // "__builtin_ptx_read_pm0"
			case '1': // 1 string to match.
			return Intrinsic::ptx_read_pm1; // "__builtin_ptx_read_pm1"
			case '2': // 1 string to match.
			return Intrinsic::ptx_read_pm2; // "__builtin_ptx_read_pm2"
			case '3': // 1 string to match.
			return Intrinsic::ptx_read_pm3; // "__builtin_ptx_read_pm3"
			}
			break;
			}
	break;		break;
	switch (BuiltinName[7]) {		}
			break;
			case 23: // 20 strings to match.
			if (memcmp(BuiltinName.data()+0, "__", 2))
			break;
			switch (BuiltinName[2]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'b': // 14 strings to match.
	if (memcmp(BuiltinName.data()+8, "ar0", 3))		if (memcmp(BuiltinName.data()+3, "uiltin_", 7))
			break;
			switch (BuiltinName[10]) {
			default: break;
			case 'i': // 12 strings to match.
			if (memcmp(BuiltinName.data()+11, "a32_vp", 6))
			break;
			switch (BuiltinName[17]) {
			default: break;
			case 'h': // 9 strings to match.
			switch (BuiltinName[18]) {
			default: break;
			case 'a': // 6 strings to match.
			if (memcmp(BuiltinName.data()+19, "dd", 2))
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'b': // 3 strings to match.
			switch (BuiltinName[22]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vphaddbd; // "__builtin_ia32_
			vphaddbd"
			case 'q': // 1 string to match.
			return Intrinsic::x86_xop_vphaddbq; // "__builtin_ia32_
			vphaddbq"
			case 'w': // 1 string to match.
			return Intrinsic::x86_xop_vphaddbw; // "__builtin_ia32_
			vphaddbw"
			}
			break;
			case 'd': // 1 string to match.
			if (BuiltinName[22] != 'q')
			break;
			return Intrinsic::x86_xop_vphadddq; // "__builtin_ia32_
			vphadddq"
			case 'w': // 2 strings to match.
			switch (BuiltinName[22]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vphaddwd; // "__builtin_ia32_
			vphaddwd"
			case 'q': // 1 string to match.
			return Intrinsic::x86_xop_vphaddwq; // "__builtin_ia32_
			vphaddwq"
			}
			break;
			}
			break;
			case 's': // 3 strings to match.
			if (memcmp(BuiltinName.data()+19, "ub", 2))
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'b': // 1 string to match.
			if (BuiltinName[22] != 'w')
			break;
			return Intrinsic::x86_xop_vphsubbw; // "__builtin_ia32_
			vphsubbw"
			case 'd': // 1 string to match.
			if (BuiltinName[22] != 'q')
			break;
			return Intrinsic::x86_xop_vphsubdq; // "__builtin_ia32_
			vphsubdq"
			case 'w': // 1 string to match.
			if (BuiltinName[22] != 'd')
			break;
			return Intrinsic::x86_xop_vphsubwd; // "__builtin_ia32_
			vphsubwd"
			}
			break;
			}
			break;
			case 'm': // 3 strings to match.
			if (memcmp(BuiltinName.data()+18, "acs", 3))
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'd': // 1 string to match.
			if (BuiltinName[22] != 'd')
			break;
			return Intrinsic::x86_xop_vpmacsdd; // "__builtin_ia32_
			vpmacsdd"
			case 'w': // 2 strings to match.
			switch (BuiltinName[22]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vpmacswd; // "__builtin_ia32_
			vpmacswd"
			case 'w': // 1 string to match.
			return Intrinsic::x86_xop_vpmacsww; // "__builtin_ia32_
			vpmacsww"
			}
			break;
			}
			break;
			}
			break;
			case 'p': // 1 string to match.
			if (memcmp(BuiltinName.data()+11, "tx_read_smid", 12))
			break;
			return Intrinsic::ptx_read_smid; // "__builtin_ptx_read_smid
			"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+11, "tack_restore", 12))
			break;
			return Intrinsic::stackrestore; // "__builtin_stack_restore
			"
			}
			break;
			case 'n': // 6 strings to match.
			if (memcmp(BuiltinName.data()+3, "vvm_", 4))
			break;
			switch (BuiltinName[7]) {
			default: break;
			case 'c': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "os_approx_ftz_f", 15))
			break;
			return Intrinsic::nvvm_cos_approx_ftz_f; // "__nvvm_cos_appr
			ox_ftz_f"
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "iv_approx_ftz_f", 15))
			break;
			return Intrinsic::nvvm_div_approx_ftz_f; // "__nvvm_div_appr
			ox_ftz_f"
			case 'e': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "x2_approx_ftz_f", 15))
			break;
			return Intrinsic::nvvm_ex2_approx_ftz_f; // "__nvvm_ex2_appr
			ox_ftz_f"
			case 'l': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "g2_approx_ftz_f", 15))
			break;
			return Intrinsic::nvvm_lg2_approx_ftz_f; // "__nvvm_lg2_appr
			ox_ftz_f"
			case 'r': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "cp_approx_ftz_d", 15))
			break;
			return Intrinsic::nvvm_rcp_approx_ftz_d; // "__nvvm_rcp_appr
			ox_ftz_d"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+8, "in_approx_ftz_f", 15))
			break;
			return Intrinsic::nvvm_sin_approx_ftz_f; // "__nvvm_sin_appr
			ox_ftz_f"
			}
			break;
			}
			break;
			case 24: // 19 strings to match.
			if (memcmp(BuiltinName.data()+0, "__", 2))
			break;
			switch (BuiltinName[2]) {
			default: break;
			case 'b': // 18 strings to match.
			if (memcmp(BuiltinName.data()+3, "uiltin_", 7))
			break;
			switch (BuiltinName[10]) {
			default: break;
			case 'i': // 12 strings to match.
			if (memcmp(BuiltinName.data()+11, "a32_vp", 6))
			break;
			switch (BuiltinName[17]) {
			default: break;
			case 'h': // 6 strings to match.
			if (memcmp(BuiltinName.data()+18, "addu", 4))
			break;
			switch (BuiltinName[22]) {
			default: break;
			case 'b': // 3 strings to match.
			switch (BuiltinName[23]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vphaddubd; // "__builtin_ia32_
			vphaddubd"
			case 'q': // 1 string to match.
			return Intrinsic::x86_xop_vphaddubq; // "__builtin_ia32_
			vphaddubq"
			case 'w': // 1 string to match.
			return Intrinsic::x86_xop_vphaddubw; // "__builtin_ia32_
			vphaddubw"
			}
			break;
			case 'd': // 1 string to match.
			if (BuiltinName[23] != 'q')
			break;
			return Intrinsic::x86_xop_vphaddudq; // "__builtin_ia32_
			vphaddudq"
			case 'w': // 2 strings to match.
			switch (BuiltinName[23]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vphadduwd; // "__builtin_ia32_
			vphadduwd"
			case 'q': // 1 string to match.
			return Intrinsic::x86_xop_vphadduwq; // "__builtin_ia32_
			vphadduwq"
			}
			break;
			}
			break;
			case 'm': // 6 strings to match.
			if (BuiltinName[18] != 'a')
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'c': // 5 strings to match.
			if (BuiltinName[20] != 's')
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'd': // 2 strings to match.
			if (BuiltinName[22] != 'q')
			break;
			switch (BuiltinName[23]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::x86_xop_vpmacsdqh; // "__builtin_ia32_
			vpmacsdqh"
			case 'l': // 1 string to match.
			return Intrinsic::x86_xop_vpmacsdql; // "__builtin_ia32_
			vpmacsdql"
			}
			break;
			case 's': // 3 strings to match.
			switch (BuiltinName[22]) {
			default: break;
			case 'd': // 1 string to match.
			if (BuiltinName[23] != 'd')
			break;
			return Intrinsic::x86_xop_vpmacssdd; // "__builtin_ia32_
			vpmacssdd"
			case 'w': // 2 strings to match.
			switch (BuiltinName[23]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vpmacsswd; // "__builtin_ia32_
			vpmacsswd"
			case 'w': // 1 string to match.
			return Intrinsic::x86_xop_vpmacssww; // "__builtin_ia32_
			vpmacssww"
			}
			break;
			}
			break;
			}
			break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "cswd", 4))
			break;
			return Intrinsic::x86_xop_vpmadcswd; // "__builtin_ia32_
			vpmadcswd"
			}
			break;
			}
			break;
			case 'p': // 6 strings to match.
			if (memcmp(BuiltinName.data()+11, "tx_read_", 8))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'c': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "lock", 4))
			break;
			return Intrinsic::ptx_read_clock; // "__builtin_ptx_read_cloc
			k"
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "smid", 4))
			break;
			return Intrinsic::ptx_read_nsmid; // "__builtin_ptx_read_nsmi
			d"
			case 't': // 4 strings to match.
			if (memcmp(BuiltinName.data()+20, "id_", 3))
			break;
			switch (BuiltinName[23]) {
			default: break;
			case 'w': // 1 string to match.
			return Intrinsic::ptx_read_tid_w; // "__builtin_ptx_read_tid_
			w"
			case 'x': // 1 string to match.
			return Intrinsic::ptx_read_tid_x; // "__builtin_ptx_read_tid_
			x"
			case 'y': // 1 string to match.
			return Intrinsic::ptx_read_tid_y; // "__builtin_ptx_read_tid_
			y"
			case 'z': // 1 string to match.
			return Intrinsic::ptx_read_tid_z; // "__builtin_ptx_read_tid_
			z"
			}
			break;
			}
			break;
			}
			break;
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+3, "vvm_sqrt_approx_ftz_f", 21))
			break;
			return Intrinsic::nvvm_sqrt_approx_ftz_f; // "__nvvm_sqrt_app
			rox_ftz_f"
			}
			break;
			case 25: // 17 strings to match.
			if (memcmp(BuiltinName.data()+0, "__", 2))
			break;
			switch (BuiltinName[2]) {
			default: break;
			case 'b': // 16 strings to match.
			if (memcmp(BuiltinName.data()+3, "uiltin_", 7))
			break;
			switch (BuiltinName[10]) {
			default: break;
			case 'i': // 9 strings to match.
			switch (BuiltinName[11]) {
			default: break;
			case 'a': // 8 strings to match.
			if (memcmp(BuiltinName.data()+12, "32_v", 4))
			break;
			switch (BuiltinName[16]) {
			default: break;
			case 'f': // 2 strings to match.
			if (memcmp(BuiltinName.data()+17, "rczp", 4))
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "256", 3))
			break;
			return Intrinsic::x86_xop_vfrcz_pd_256; // "__builtin_ia32_
			vfrczpd256"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "256", 3))
			break;
			return Intrinsic::x86_xop_vfrcz_ps_256; // "__builtin_ia32_
			vfrczps256"
			}
			break;
			case 'p': // 6 strings to match.
			switch (BuiltinName[17]) {
			default: break;
			case 'c': // 1 string to match.
			if (memcmp(BuiltinName.data()+18, "mov_256", 7))
			break;
			return Intrinsic::x86_xop_vpcmov_256; // "__builtin_ia32_
			vpcmov_256"
			case 'e': // 2 strings to match.
			if (memcmp(BuiltinName.data()+18, "rmil2p", 6))
			break;
			switch (BuiltinName[24]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_xop_vpermil2pd; // "__builtin_ia32_
			vpermil2pd"
			case 's': // 1 string to match.
			return Intrinsic::x86_xop_vpermil2ps; // "__builtin_ia32_
			vpermil2ps"
			}
			break;
			case 'm': // 3 strings to match.
			if (BuiltinName[18] != 'a')
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'c': // 2 strings to match.
			if (memcmp(BuiltinName.data()+20, "ssdq", 4))
			break;
			switch (BuiltinName[24]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::x86_xop_vpmacssdqh; // "__built
			in_ia32_vpmacssdqh"
			case 'l': // 1 string to match.
			return Intrinsic::x86_xop_vpmacssdql; // "__built
			in_ia32_vpmacssdql"
			}
			break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "csswd", 5))
			break;
			return Intrinsic::x86_xop_vpmadcsswd; // "__builtin_ia32_
			vpmadcsswd"
			}
			break;
			}
			break;
			}
			break;
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+12, "it_trampoline", 13))
			break;
			return Intrinsic::init_trampoline; // "__builtin_init_trampoli
			ne"
			}
			break;
			case 'p': // 7 strings to match.
			if (memcmp(BuiltinName.data()+11, "tx_read_", 8))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'g': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "ridid", 5))
			break;
			return Intrinsic::ptx_read_gridid; // "__builtin_ptx_read_grid
			id"
			case 'l': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "aneid", 5))
			break;
			return Intrinsic::ptx_read_laneid; // "__builtin_ptx_read_lane
			id"
			case 'n': // 4 strings to match.
			if (memcmp(BuiltinName.data()+20, "tid_", 4))
			break;
			switch (BuiltinName[24]) {
			default: break;
			case 'w': // 1 string to match.
			return Intrinsic::ptx_read_ntid_w; // "__builtin_ptx_read_ntid
			_w"
			case 'x': // 1 string to match.
			return Intrinsic::ptx_read_ntid_x; // "__builtin_ptx_read_ntid
			_x"
			case 'y': // 1 string to match.
			return Intrinsic::ptx_read_ntid_y; // "__builtin_ptx_read_ntid
			_y"
			case 'z': // 1 string to match.
			return Intrinsic::ptx_read_ntid_z; // "__builtin_ptx_read_ntid
			_z"
			}
			break;
			case 'w': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "arpid", 5))
			break;
			return Intrinsic::ptx_read_warpid; // "__builtin_ptx_read_warp
			id"
			}
			break;
			}
			break;
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+3, "vvm_rsqrt_approx_ftz_f", 22))
			break;
			return Intrinsic::nvvm_rsqrt_approx_ftz_f; // "__nvvm_rsqrt_ap
			prox_ftz_f"
			}
			break;
			case 26: // 9 strings to match.
			if (memcmp(BuiltinName.data()+0, "__", 2))
			break;
			switch (BuiltinName[2]) {
			default: break;
			case 'b': // 6 strings to match.
			if (memcmp(BuiltinName.data()+3, "uiltin_ptx_read_", 16))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'c': // 5 strings to match.
			switch (BuiltinName[20]) {
			default: break;
			case 'l': // 1 string to match.
			if (memcmp(BuiltinName.data()+21, "ock64", 5))
			break;
			return Intrinsic::ptx_read_clock64; // "__builtin_ptx_read_cloc
			k64"
			case 't': // 4 strings to match.
			if (memcmp(BuiltinName.data()+21, "aid_", 4))
			break;
			switch (BuiltinName[25]) {
			default: break;
			case 'w': // 1 string to match.
			return Intrinsic::ptx_read_ctaid_w; // "__builtin_ptx_r
			ead_ctaid_w"
			case 'x': // 1 string to match.
			return Intrinsic::ptx_read_ctaid_x; // "__builtin_ptx_r
			ead_ctaid_x"
			case 'y': // 1 string to match.
			return Intrinsic::ptx_read_ctaid_y; // "__builtin_ptx_r
			ead_ctaid_y"
			case 'z': // 1 string to match.
			return Intrinsic::ptx_read_ctaid_z; // "__builtin_ptx_r
			ead_ctaid_z"
			}
			break;
			}
	break;		break;
	return Intrinsic::nvvm_barrier0; // "__nvvm_bar0"		case 'n': // 1 string to match.
	case 'p': // 1 string to match.		if (memcmp(BuiltinName.data()+20, "warpid", 6))
	if (memcmp(BuiltinName.data()+8, "rmt", 3))		break;
			return Intrinsic::ptx_read_nwarpid; // "__builtin_ptx_read_nwar
			pid"
			}
			break;
			case 'n': // 3 strings to match.
			if (memcmp(BuiltinName.data()+3, "vvm_read_ptx_sreg_tid_", 22))
	break;		break;
	return Intrinsic::nvvm_prmt; // "__nvvm_prmt"		switch (BuiltinName[25]) {
			default: break;
			case 'x': // 1 string to match.
			return Intrinsic::nvvm_read_ptx_sreg_tid_x; // "__nvvm_read_ptx
			_sreg_tid_x"
			case 'y': // 1 string to match.
			return Intrinsic::nvvm_read_ptx_sreg_tid_y; // "__nvvm_read_ptx
			_sreg_tid_y"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_read_ptx_sreg_tid_z; // "__nvvm_read_ptx
			_sreg_tid_z"
			}
			break;
	}		}
	break;		break;
	case 12: // 5 strings to match.		case 27: // 8 strings to match.
	if (memcmp(BuiltinName.data()+0, "__nvvm_", 7))		if (memcmp(BuiltinName.data()+0, "__", 2))
	break;		break;
	switch (BuiltinName[7]) {		switch (BuiltinName[2]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'b': // 5 strings to match.
	if (memcmp(BuiltinName.data()+8, "bs_i", 4))		if (memcmp(BuiltinName.data()+3, "uiltin_", 7))
	break;
	return Intrinsic::nvvm_abs_i; // "__nvvm_abs_i"
	case 'c': // 1 string to match.
	if (memcmp(BuiltinName.data()+8, "lz_i", 4))
	break;		break;
	return Intrinsic::nvvm_clz_i; // "__nvvm_clz_i"		switch (BuiltinName[10]) {
	case 'm': // 2 strings to match.
	switch (BuiltinName[8]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+9, "x_i", 3))		if (memcmp(BuiltinName.data()+11, "djust_trampoline", 16))
	break;		break;
	return Intrinsic::nvvm_max_i; // "__nvvm_max_i"		return Intrinsic::adjust_trampoline; // "__builtin_adjust_trampo
	case 'i': // 1 string to match.		line"
	if (memcmp(BuiltinName.data()+9, "n_i", 3))		case 'p': // 4 strings to match.
			if (memcmp(BuiltinName.data()+11, "tx_read_nctaid_", 15))
	break;		break;
	return Intrinsic::nvvm_min_i; // "__nvvm_min_i"		switch (BuiltinName[26]) {
			default: break;
			case 'w': // 1 string to match.
			return Intrinsic::ptx_read_nctaid_w; // "__builtin_ptx_read_ncta
			id_w"
			case 'x': // 1 string to match.
			return Intrinsic::ptx_read_nctaid_x; // "__builtin_ptx_read_ncta
			id_x"
			case 'y': // 1 string to match.
			return Intrinsic::ptx_read_nctaid_y; // "__builtin_ptx_read_ncta
			id_y"
			case 'z': // 1 string to match.
			return Intrinsic::ptx_read_nctaid_z; // "__builtin_ptx_read_ncta
			id_z"
			}
			break;
	}		}
	break;		break;
	case 's': // 1 string to match.		case 'n': // 3 strings to match.
	if (memcmp(BuiltinName.data()+8, "ad_i", 4))		if (memcmp(BuiltinName.data()+3, "vvm_read_ptx_sreg_ntid_", 23))
	break;		break;
	return Intrinsic::nvvm_sad_i; // "__nvvm_sad_i"		switch (BuiltinName[26]) {
			default: break;
			case 'x': // 1 string to match.
			return Intrinsic::nvvm_read_ptx_sreg_ntid_x; // "__nvvm_read_ptx
			_sreg_ntid_x"
			case 'y': // 1 string to match.
			return Intrinsic::nvvm_read_ptx_sreg_ntid_y; // "__nvvm_read_ptx
			_sreg_ntid_y"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_read_ptx_sreg_ntid_z; // "__nvvm_read_ptx
			_sreg_ntid_z"
			}
			break;
	}		}
	break;		break;
	case 13: // 43 strings to match.		case 28: // 5 strings to match.
	if (memcmp(BuiltinName.data()+0, "__", 2))		if (memcmp(BuiltinName.data()+0, "__", 2))
	break;		break;
	switch (BuiltinName[2]) {		switch (BuiltinName[2]) {
	default: break;		default: break;
	case 'n': // 42 strings to match.		case 'b': // 2 strings to match.
	if (memcmp(BuiltinName.data()+3, "vvm_", 4))		if (memcmp(BuiltinName.data()+3, "uiltin_ia32_vpermil2p", 21))
	break;		break;
	switch (BuiltinName[7]) {		switch (BuiltinName[24]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+8, "bs_ll", 5))		if (memcmp(BuiltinName.data()+25, "256", 3))
	break;		break;
	return Intrinsic::nvvm_abs_ll; // "__nvvm_abs_ll"		return Intrinsic::x86_xop_vpermil2pd_256; // "__builtin_ia32_
	case 'b': // 2 strings to match.		vpermil2pd256"
	if (memcmp(BuiltinName.data()+8, "rev", 3))		case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "256", 3))
	break;		break;
	switch (BuiltinName[11]) {		return Intrinsic::x86_xop_vpermil2ps_256; // "__builtin_ia32_
	default: break;		vpermil2ps256"
	case '3': // 1 string to match.		}
	if (BuiltinName[12] != '2')		break;
	break;		case 'n': // 3 strings to match.
	return Intrinsic::nvvm_brev32; // "__nvvm_brev32"		if (memcmp(BuiltinName.data()+3, "vvm_read_ptx_sreg_ctaid_", 24))
	case '6': // 1 string to match.
	if (BuiltinName[12] != '4')
	break;
	return Intrinsic::nvvm_brev64; // "__nvvm_brev64"
	}
	break;		break;
	case 'c': // 3 strings to match.		switch (BuiltinName[27]) {
	switch (BuiltinName[8]) {		default: break;
	default: break;		case 'x': // 1 string to match.
	case 'e': // 2 strings to match.		return Intrinsic::nvvm_read_ptx_sreg_ctaid_x; // "__nvvm_read_ptx
	if (memcmp(BuiltinName.data()+9, "il_", 3))		_sreg_ctaid_x"
	break;		case 'y': // 1 string to match.
	switch (BuiltinName[12]) {		return Intrinsic::nvvm_read_ptx_sreg_ctaid_y; // "__nvvm_read_ptx
	default: break;		_sreg_ctaid_y"
	case 'd': // 1 string to match.		case 'z': // 1 string to match.
	return Intrinsic::nvvm_ceil_d; // "__nvvm_ceil_d"		return Intrinsic::nvvm_read_ptx_sreg_ctaid_z; // "__nvvm_read_ptx
	case 'f': // 1 string to match.		_sreg_ctaid_z"
	return Intrinsic::nvvm_ceil_f; // "__nvvm_ceil_f"		}
	}		break;
	break;		}
	case 'l': // 1 string to match.		break;
	if (memcmp(BuiltinName.data()+9, "z_ll", 4))		case 29: // 4 strings to match.
	break;		if (memcmp(BuiltinName.data()+0, "__nvvm_read_ptx_sreg_", 21))
	return Intrinsic::nvvm_clz_ll; // "__nvvm_clz_ll"		break;
	}		switch (BuiltinName[21]) {
			default: break;
			case 'n': // 3 strings to match.
			if (memcmp(BuiltinName.data()+22, "ctaid_", 6))
	break;		break;
	case 'd': // 10 strings to match.		switch (BuiltinName[28]) {
	if (BuiltinName[8] != '2')		default: break;
			case 'x': // 1 string to match.
			return Intrinsic::nvvm_read_ptx_sreg_nctaid_x; // "__nvvm_read_ptx
			_sreg_nctaid_x"
			case 'y': // 1 string to match.
			return Intrinsic::nvvm_read_ptx_sreg_nctaid_y; // "__nvvm_read_ptx
			_sreg_nctaid_y"
			case 'z': // 1 string to match.
			return Intrinsic::nvvm_read_ptx_sreg_nctaid_z; // "__nvvm_read_ptx
			_sreg_nctaid_z"
			}
			break;
			case 'w': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "arpsize", 7))
			break;
			return Intrinsic::nvvm_read_ptx_sreg_warpsize; // "__nvvm_read_ptx
			_sreg_warpsize"
			}
			break;
			case 30: // 5 strings to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_ptx_read_lanemask_", 28))
			break;
			switch (BuiltinName[28]) {
			default: break;
			case 'e': // 1 string to match.
			if (BuiltinName[29] != 'q')
			break;
			return Intrinsic::ptx_read_lanemask_eq; // "__builtin_ptx_read_lane
			mask_eq"
			case 'g': // 2 strings to match.
			switch (BuiltinName[29]) {
			default: break;
			case 'e': // 1 string to match.
			return Intrinsic::ptx_read_lanemask_ge; // "__builtin_ptx_r
			ead_lanemask_ge"
			case 't': // 1 string to match.
			return Intrinsic::ptx_read_lanemask_gt; // "__builtin_ptx_r
			ead_lanemask_gt"
			}
			break;
			case 'l': // 2 strings to match.
			switch (BuiltinName[29]) {
			default: break;
			case 'e': // 1 string to match.
			return Intrinsic::ptx_read_lanemask_le; // "__builtin_ptx_r
			ead_lanemask_le"
			case 't': // 1 string to match.
			return Intrinsic::ptx_read_lanemask_lt; // "__builtin_ptx_r
			ead_lanemask_lt"
			}
			break;
			}
			break;
			}
			}
			if (TargetPrefix == "arm") {
			switch (BuiltinName.size()) {
			default: break;
			case 17: // 5 strings to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_arm_", 14))
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'c': // 1 string to match.
			if (memcmp(BuiltinName.data()+15, "dp", 2))
			break;
			return Intrinsic::arm_cdp; // "__builtin_arm_cdp"
			case 'd': // 2 strings to match.
			switch (BuiltinName[15]) {
			default: break;
			case 'm': // 1 string to match.
			if (BuiltinName[16] != 'b')
	break;		break;
	switch (BuiltinName[9]) {		return Intrinsic::arm_dmb; // "__builtin_arm_dmb"
	default: break;		case 's': // 1 string to match.
	case 'f': // 4 strings to match.		if (BuiltinName[16] != 'b')
	if (memcmp(BuiltinName.data()+10, "_r", 2))
	break;
	switch (BuiltinName[12]) {
	default: break;
	case 'm': // 1 string to match.
	return Intrinsic::nvvm_d2f_rm; // "__nvvm_d2f_rm"
	case 'n': // 1 string to match.
	return Intrinsic::nvvm_d2f_rn; // "__nvvm_d2f_rn"
	case 'p': // 1 string to match.
	return Intrinsic::nvvm_d2f_rp; // "__nvvm_d2f_rp"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_d2f_rz; // "__nvvm_d2f_rz"
	}
	break;		break;
	case 'i': // 6 strings to match.		return Intrinsic::arm_dsb; // "__builtin_arm_dsb"
	if (BuiltinName[10] != '_')		}
	break;		break;
	switch (BuiltinName[11]) {		case 'm': // 2 strings to match.
	default: break;		switch (BuiltinName[15]) {
	case 'h': // 1 string to match.		default: break;
	if (BuiltinName[12] != 'i')		case 'c': // 1 string to match.
	break;		if (BuiltinName[16] != 'r')
	return Intrinsic::nvvm_d2i_hi; // "__nvvm_d2i_hi"
	case 'l': // 1 string to match.
	if (BuiltinName[12] != 'o')
	break;
	return Intrinsic::nvvm_d2i_lo; // "__nvvm_d2i_lo"
	case 'r': // 4 strings to match.
	switch (BuiltinName[12]) {
	default: break;
	case 'm': // 1 string to match.
	return Intrinsic::nvvm_d2i_rm; // "__nvvm_d2i_rm"
	case 'n': // 1 string to match.
	return Intrinsic::nvvm_d2i_rn; // "__nvvm_d2i_rn"
	case 'p': // 1 string to match.
	return Intrinsic::nvvm_d2i_rp; // "__nvvm_d2i_rp"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_d2i_rz; // "__nvvm_d2i_rz"
	}
	break;
	}
	break;		break;
	}		return Intrinsic::arm_mcr; // "__builtin_arm_mcr"
			case 'r': // 1 string to match.
			if (BuiltinName[16] != 'c')
			break;
			return Intrinsic::arm_mrc; // "__builtin_arm_mrc"
			}
			break;
			}
			break;
			case 18: // 8 strings to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_arm_", 14))
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'c': // 1 string to match.
			if (memcmp(BuiltinName.data()+15, "dp2", 3))
	break;		break;
	case 'f': // 11 strings to match.		return Intrinsic::arm_cdp2; // "__builtin_arm_cdp2"
	switch (BuiltinName[8]) {		case 'm': // 3 strings to match.
			switch (BuiltinName[15]) {
			default: break;
			case 'c': // 2 strings to match.
			if (BuiltinName[16] != 'r')
			break;
			switch (BuiltinName[17]) {
	default: break;		default: break;
	case '2': // 5 strings to match.		case '2': // 1 string to match.
	switch (BuiltinName[9]) {		return Intrinsic::arm_mcr2; // "__builtin_arm_mcr2"
	default: break;		case 'r': // 1 string to match.
	case 'h': // 1 string to match.		return Intrinsic::arm_mcrr; // "__builtin_arm_mcrr"
	if (memcmp(BuiltinName.data()+10, "_rn", 3))		}
	break;		break;
	return Intrinsic::nvvm_f2h_rn; // "__nvvm_f2h_rn"		case 'r': // 1 string to match.
	case 'i': // 4 strings to match.		if (memcmp(BuiltinName.data()+16, "c2", 2))
	if (memcmp(BuiltinName.data()+10, "_r", 2))
	break;
	switch (BuiltinName[12]) {
	default: break;
	case 'm': // 1 string to match.
	return Intrinsic::nvvm_f2i_rm; // "__nvvm_f2i_rm"
	case 'n': // 1 string to match.
	return Intrinsic::nvvm_f2i_rn; // "__nvvm_f2i_rn"
	case 'p': // 1 string to match.
	return Intrinsic::nvvm_f2i_rp; // "__nvvm_f2i_rp"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_f2i_rz; // "__nvvm_f2i_rz"
	}
	break;
	}
	break;		break;
	case 'a': // 2 strings to match.		return Intrinsic::arm_mrc2; // "__builtin_arm_mrc2"
	if (memcmp(BuiltinName.data()+9, "bs_", 3))		}
	break;		break;
	switch (BuiltinName[12]) {		case 'q': // 2 strings to match.
	default: break;		switch (BuiltinName[15]) {
	case 'd': // 1 string to match.		default: break;
	return Intrinsic::nvvm_fabs_d; // "__nvvm_fabs_d"		case 'a': // 1 string to match.
	case 'f': // 1 string to match.		if (memcmp(BuiltinName.data()+16, "dd", 2))
	return Intrinsic::nvvm_fabs_f; // "__nvvm_fabs_f"
	}
	break;		break;
	case 'm': // 4 strings to match.		return Intrinsic::arm_qadd; // "__builtin_arm_qadd"
	switch (BuiltinName[9]) {		case 's': // 1 string to match.
	default: break;		if (memcmp(BuiltinName.data()+16, "ub", 2))
	case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+10, "x_", 2))
	break;
	switch (BuiltinName[12]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_fmax_d; // "__nvvm_fmax_d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_fmax_f; // "__nvvm_fmax_f"
	}
	break;
	case 'i': // 2 strings to match.
	if (memcmp(BuiltinName.data()+10, "n_", 2))
	break;
	switch (BuiltinName[12]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_fmin_d; // "__nvvm_fmin_d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_fmin_f; // "__nvvm_fmin_f"
	}
	break;
	}
	break;		break;
	}		return Intrinsic::arm_qsub; // "__builtin_arm_qsub"
			}
			break;
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+15, "sat", 3))
	break;		break;
	case 'i': // 8 strings to match.		return Intrinsic::arm_ssat; // "__builtin_arm_ssat"
	if (BuiltinName[8] != '2')		case 'u': // 1 string to match.
			if (memcmp(BuiltinName.data()+15, "sat", 3))
			break;
			return Intrinsic::arm_usat; // "__builtin_arm_usat"
			}
			break;
			case 19: // 1 string to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_arm_mcrr2", 19))
			break;
			return Intrinsic::arm_mcrr2; // "__builtin_arm_mcrr2"
			case 23: // 2 strings to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_arm_", 14))
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'g': // 1 string to match.
			if (memcmp(BuiltinName.data()+15, "et_fpscr", 8))
			break;
			return Intrinsic::arm_get_fpscr; // "__builtin_arm_get_fpscr"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+15, "et_fpscr", 8))
			break;
			return Intrinsic::arm_set_fpscr; // "__builtin_arm_set_fpscr"
			}
			break;
			case 24: // 1 string to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_thread_pointer", 24))
			break;
			return Intrinsic::arm_thread_pointer; // "__builtin_thread_pointe
			r"
			}
			}
			if (TargetPrefix == "hexagon") {
			switch (BuiltinName.size()) {
			default: break;
			case 18: // 1 string to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_circ_ldd", 18))
			break;
			return Intrinsic::hexagon_circ_ldd; // "__builtin_circ_ldd"
			case 23: // 2 strings to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
			break;
			switch (BuiltinName[18]) {
			default: break;
			case 'A': // 1 string to match.
			if (memcmp(BuiltinName.data()+19, "2_or", 4))
			break;
			return Intrinsic::hexagon_A2_or; // "__builtin_HEXAGON_A2_or"
			case 'C': // 1 string to match.
			if (memcmp(BuiltinName.data()+19, "2_or", 4))
			break;
			return Intrinsic::hexagon_C2_or; // "__builtin_HEXAGON_C2_or"
			}
			break;
			case 24: // 23 strings to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
			break;
			switch (BuiltinName[18]) {
			default: break;
			case 'A': // 13 strings to match.
			switch (BuiltinName[19]) {
			default: break;
			case '2': // 12 strings to match.
			if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[9]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'd': // 4 strings to match.		case 'a': // 3 strings to match.
	if (memcmp(BuiltinName.data()+10, "_r", 2))		switch (BuiltinName[22]) {
	break;
	switch (BuiltinName[12]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::nvvm_i2d_rm; // "__nvvm_i2d_rm"		if (BuiltinName[23] != 's')
			break;
			return Intrinsic::hexagon_A2_abs; // "__builtin_HEXAGON_A2_ab
			s"
			case 'd': // 1 string to match.
			if (BuiltinName[23] != 'd')
			break;
			return Intrinsic::hexagon_A2_add; // "__builtin_HEXAGON_A2_ad
			d"
	case 'n': // 1 string to match.		case 'n': // 1 string to match.
	return Intrinsic::nvvm_i2d_rn; // "__nvvm_i2d_rn"		if (BuiltinName[23] != 'd')
	case 'p': // 1 string to match.		break;
	return Intrinsic::nvvm_i2d_rp; // "__nvvm_i2d_rp"		return Intrinsic::hexagon_A2_and; // "__builtin_HEXAGON_A2_an
	case 'z': // 1 string to match.		d"
	return Intrinsic::nvvm_i2d_rz; // "__nvvm_i2d_rz"
	}		}
	break;		break;
	case 'f': // 4 strings to match.		case 'm': // 2 strings to match.
	if (memcmp(BuiltinName.data()+10, "_r", 2))		switch (BuiltinName[22]) {
	break;
	switch (BuiltinName[12]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'a': // 1 string to match.
	return Intrinsic::nvvm_i2f_rm; // "__nvvm_i2f_rm"		if (BuiltinName[23] != 'x')
	case 'n': // 1 string to match.		break;
	return Intrinsic::nvvm_i2f_rn; // "__nvvm_i2f_rn"		return Intrinsic::hexagon_A2_max; // "__builtin_HEXAGON_A2_ma
	case 'p': // 1 string to match.		x"
	return Intrinsic::nvvm_i2f_rp; // "__nvvm_i2f_rp"		case 'i': // 1 string to match.
	case 'z': // 1 string to match.		if (BuiltinName[23] != 'n')
	return Intrinsic::nvvm_i2f_rz; // "__nvvm_i2f_rz"		break;
	}		return Intrinsic::hexagon_A2_min; // "__builtin_HEXAGON_A2_mi
	break;		n"
	}		}
	break;		break;
	case 'm': // 4 strings to match.		case 'n': // 2 strings to match.
	switch (BuiltinName[8]) {		switch (BuiltinName[22]) {
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+9, "x_", 2))
	break;
	switch (BuiltinName[11]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'e': // 1 string to match.
	if (BuiltinName[12] != 'l')		if (BuiltinName[23] != 'g')
	break;		break;
	return Intrinsic::nvvm_max_ll; // "__nvvm_max_ll"		return Intrinsic::hexagon_A2_neg; // "__builtin_HEXAGON_A2_ne
	case 'u': // 1 string to match.		g"
	if (BuiltinName[12] != 'i')		case 'o': // 1 string to match.
			if (BuiltinName[23] != 't')
	break;		break;
	return Intrinsic::nvvm_max_ui; // "__nvvm_max_ui"		return Intrinsic::hexagon_A2_not; // "__builtin_HEXAGON_A2_no t"
	}		}
	break;		break;
	case 'i': // 2 strings to match.		case 'o': // 1 string to match.
	if (memcmp(BuiltinName.data()+9, "n_", 2))		if (memcmp(BuiltinName.data()+22, "rp", 2))
	break;		break;
	switch (BuiltinName[11]) {		return Intrinsic::hexagon_A2_orp; // "__builtin_HEXAGON_A2_or
			p"
			case 's': // 2 strings to match.
			switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'a': // 1 string to match.
	if (BuiltinName[12] != 'l')		if (BuiltinName[23] != 't')
	break;		break;
	return Intrinsic::nvvm_min_ll; // "__nvvm_min_ll"		return Intrinsic::hexagon_A2_sat; // "__builtin_HEXAGON_A2_sa t"
	case 'u': // 1 string to match.		case 'u': // 1 string to match.
	if (BuiltinName[12] != 'i')		if (BuiltinName[23] != 'b')
	break;		break;
	return Intrinsic::nvvm_min_ui; // "__nvvm_min_ui"		return Intrinsic::hexagon_A2_sub; // "__builtin_HEXAGON_A2_su b"
	}		}
	break;		break;
	}		case 't': // 1 string to match.
	break;		if (memcmp(BuiltinName.data()+22, "fr", 2))
	case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+8, "opc_i", 5))
	break;
	return Intrinsic::nvvm_popc_i; // "__nvvm_popc_i"
	case 's': // 2 strings to match.
	switch (BuiltinName[8]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+9, "d_ui", 4))
	break;		break;
	return Intrinsic::nvvm_sad_ui; // "__nvvm_sad_ui"		return Intrinsic::hexagon_A2_tfr; // "__builtin_HEXAGON_A2_tf
	case 'q': // 1 string to match.		r"
	if (memcmp(BuiltinName.data()+9, "rt_f", 4))		case 'x': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "or", 2))
	break;		break;
	return Intrinsic::nvvm_sqrt_f; // "__nvvm_sqrt_f"		return Intrinsic::hexagon_A2_xor; // "__builtin_HEXAGON_A2_xo r"
	}		}
	break;		break;
			case '4': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "_orn", 4))
			break;
			return Intrinsic::hexagon_A4_orn; // "__builtin_HEXAGON_A4_or
			n"
	}		}
	break;		break;
	case 's': // 1 string to match.		case 'C': // 5 strings to match.
	if (memcmp(BuiltinName.data()+3, "yncthreads", 10))		if (memcmp(BuiltinName.data()+19, "2_", 2))
	break;
	return Intrinsic::cuda_syncthreads; // "__syncthreads"
	}
	break;
	case 14: // 47 strings to match.
	if (memcmp(BuiltinName.data()+0, "__", 2))
	break;
	switch (BuiltinName[2]) {
	default: break;
	case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+3, "uiltin_trap", 11))
	break;
	return Intrinsic::trap; // "__builtin_trap"
	case 'g': // 2 strings to match.
	if (memcmp(BuiltinName.data()+3, "nu_", 3))
	break;		break;
	switch (BuiltinName[6]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'f': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+7, "2h_ieee", 7))		if (memcmp(BuiltinName.data()+22, "nd", 2))
	break;		break;
	return Intrinsic::convert_to_fp16; // "__gnu_f2h_ieee"		return Intrinsic::hexagon_C2_and; // "__builtin_HEXAGON_C2_an
	case 'h': // 1 string to match.		d"
	if (memcmp(BuiltinName.data()+7, "2f_ieee", 7))		case 'm': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "ux", 2))
	break;		break;
	return Intrinsic::convert_from_fp16; // "__gnu_h2f_ieee"		return Intrinsic::hexagon_C2_mux; // "__builtin_HEXAGON_C2_mu
			x"
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "ot", 2))
			break;
			return Intrinsic::hexagon_C2_not; // "__builtin_HEXAGON_C2_no
			t"
			case 'o': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "rn", 2))
			break;
			return Intrinsic::hexagon_C2_orn; // "__builtin_HEXAGON_C2_or
			n"
			case 'x': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "or", 2))
			break;
			return Intrinsic::hexagon_C2_xor; // "__builtin_HEXAGON_C2_xo
			r"
	}		}
	break;		break;
	case 'n': // 44 strings to match.		case 'S': // 5 strings to match.
	if (memcmp(BuiltinName.data()+3, "vvm_", 4))		if (memcmp(BuiltinName.data()+19, "2_c", 3))
	break;		break;
	switch (BuiltinName[7]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'l': // 3 strings to match.
	if (memcmp(BuiltinName.data()+8, "ar0_or", 6))		switch (BuiltinName[23]) {
	break;
	return Intrinsic::nvvm_barrier0_or; // "__nvvm_bar0_or"
	case 'd': // 8 strings to match.
	if (BuiltinName[8] != '2')
	break;
	switch (BuiltinName[9]) {
	default: break;		default: break;
	case 'l': // 4 strings to match.		case '0': // 1 string to match.
	if (memcmp(BuiltinName.data()+10, "l_r", 3))		return Intrinsic::hexagon_S2_cl0; // "__builtin_HEXAGON_S2_cl
	break;		0"
	switch (BuiltinName[13]) {		case '1': // 1 string to match.
	default: break;		return Intrinsic::hexagon_S2_cl1; // "__builtin_HEXAGON_S2_cl
	case 'm': // 1 string to match.		1"
	return Intrinsic::nvvm_d2ll_rm; // "__nvvm_d2ll_rm"		case 'b': // 1 string to match.
	case 'n': // 1 string to match.		return Intrinsic::hexagon_S2_clb; // "__builtin_HEXAGON_S2_cl
	return Intrinsic::nvvm_d2ll_rn; // "__nvvm_d2ll_rn"		b"
	case 'p': // 1 string to match.
	return Intrinsic::nvvm_d2ll_rp; // "__nvvm_d2ll_rp"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_d2ll_rz; // "__nvvm_d2ll_rz"
	}
	break;
	case 'u': // 4 strings to match.
	if (memcmp(BuiltinName.data()+10, "i_r", 3))
	break;
	switch (BuiltinName[13]) {
	default: break;
	case 'm': // 1 string to match.
	return Intrinsic::nvvm_d2ui_rm; // "__nvvm_d2ui_rm"
	case 'n': // 1 string to match.
	return Intrinsic::nvvm_d2ui_rn; // "__nvvm_d2ui_rn"
	case 'p': // 1 string to match.
	return Intrinsic::nvvm_d2ui_rp; // "__nvvm_d2ui_rp"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_d2ui_rz; // "__nvvm_d2ui_rz"
	}
	break;
	}		}
	break;		break;
	case 'f': // 10 strings to match.		case 't': // 2 strings to match.
	switch (BuiltinName[8]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case '2': // 8 strings to match.		case '0': // 1 string to match.
	switch (BuiltinName[9]) {		return Intrinsic::hexagon_S2_ct0; // "__builtin_HEXAGON_S2_ct
			0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_S2_ct1; // "__builtin_HEXAGON_S2_ct
			1"
			}
			break;
			}
			break;
			}
			break;
			case 25: // 42 strings to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
			break;
			switch (BuiltinName[18]) {
			default: break;
			case 'A': // 26 strings to match.
			switch (BuiltinName[19]) {
			default: break;
			case '2': // 24 strings to match.
			if (BuiltinName[20] != '_')
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'a': // 6 strings to match.
			switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'l': // 4 strings to match.		case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+10, "l_r", 3))		if (memcmp(BuiltinName.data()+23, "sp", 2))
	break;		break;
	switch (BuiltinName[13]) {		return Intrinsic::hexagon_A2_absp; // "__builtin_HEXAGON_A2_ab
			sp"
			case 'd': // 2 strings to match.
			if (BuiltinName[23] != 'd')
			break;
			switch (BuiltinName[24]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'i': // 1 string to match.
	return Intrinsic::nvvm_f2ll_rm; // "__nvvm_f2ll_rm"		return Intrinsic::hexagon_A2_addi; // "__builtin_HEXAG
	case 'n': // 1 string to match.		ON_A2_addi"
	return Intrinsic::nvvm_f2ll_rn; // "__nvvm_f2ll_rn"
	case 'p': // 1 string to match.		case 'p': // 1 string to match.
	return Intrinsic::nvvm_f2ll_rp; // "__nvvm_f2ll_rp"		return Intrinsic::hexagon_A2_addp; // "__builtin_HEXAG
	case 'z': // 1 string to match.		ON_A2_addp"
	return Intrinsic::nvvm_f2ll_rz; // "__nvvm_f2ll_rz"
	}		}
	break;		break;
	case 'u': // 4 strings to match.		case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+10, "i_r", 3))		if (memcmp(BuiltinName.data()+23, "dp", 2))
	break;		break;
	switch (BuiltinName[13]) {		return Intrinsic::hexagon_A2_andp; // "__builtin_HEXAGON_A2_an
			dp"
			case 's': // 2 strings to match.
			switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'l': // 1 string to match.
	return Intrinsic::nvvm_f2ui_rm; // "__nvvm_f2ui_rm"		if (BuiltinName[24] != 'h')
	case 'n': // 1 string to match.		break;
	return Intrinsic::nvvm_f2ui_rn; // "__nvvm_f2ui_rn"		return Intrinsic::hexagon_A2_aslh; // "__builtin_HEXAG
	case 'p': // 1 string to match.		ON_A2_aslh"
	return Intrinsic::nvvm_f2ui_rp; // "__nvvm_f2ui_rp"		case 'r': // 1 string to match.
	case 'z': // 1 string to match.		if (BuiltinName[24] != 'h')
	return Intrinsic::nvvm_f2ui_rz; // "__nvvm_f2ui_rz"		break;
			return Intrinsic::hexagon_A2_asrh; // "__builtin_HEXAG
			ON_A2_asrh"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'm': // 4 strings to match.
	if (memcmp(BuiltinName.data()+9, "oor_", 4))		switch (BuiltinName[22]) {
	break;
	switch (BuiltinName[13]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'a': // 2 strings to match.
	return Intrinsic::nvvm_floor_d; // "__nvvm_floor_d"		if (BuiltinName[23] != 'x')
	case 'f': // 1 string to match.		break;
	return Intrinsic::nvvm_floor_f; // "__nvvm_floor_f"		switch (BuiltinName[24]) {
	}		default: break;
	break;		case 'p': // 1 string to match.
	}		return Intrinsic::hexagon_A2_maxp; // "__builtin_HEXAG
	break;		ON_A2_maxp"
	case 'l': // 8 strings to match.		case 'u': // 1 string to match.
	if (memcmp(BuiltinName.data()+8, "l2", 2))		return Intrinsic::hexagon_A2_maxu; // "__builtin_HEXAG
	break;		ON_A2_maxu"
	switch (BuiltinName[10]) {		}
	default: break;
	case 'd': // 4 strings to match.
	if (memcmp(BuiltinName.data()+11, "_r", 2))
	break;		break;
	switch (BuiltinName[13]) {		case 'i': // 2 strings to match.
	default: break;		if (BuiltinName[23] != 'n')
	case 'm': // 1 string to match.		break;
	return Intrinsic::nvvm_ll2d_rm; // "__nvvm_ll2d_rm"		switch (BuiltinName[24]) {
	case 'n': // 1 string to match.		default: break;
	return Intrinsic::nvvm_ll2d_rn; // "__nvvm_ll2d_rn"		case 'p': // 1 string to match.
	case 'p': // 1 string to match.		return Intrinsic::hexagon_A2_minp; // "__builtin_HEXAG
	return Intrinsic::nvvm_ll2d_rp; // "__nvvm_ll2d_rp"		ON_A2_minp"
	case 'z': // 1 string to match.		case 'u': // 1 string to match.
	return Intrinsic::nvvm_ll2d_rz; // "__nvvm_ll2d_rz"		return Intrinsic::hexagon_A2_minu; // "__builtin_HEXAG
	}		ON_A2_minu"
	break;		}
	case 'f': // 4 strings to match.
	if (memcmp(BuiltinName.data()+11, "_r", 2))
	break;		break;
	switch (BuiltinName[13]) {
	default: break;
	case 'm': // 1 string to match.
	return Intrinsic::nvvm_ll2f_rm; // "__nvvm_ll2f_rm"
	case 'n': // 1 string to match.
	return Intrinsic::nvvm_ll2f_rn; // "__nvvm_ll2f_rn"
	case 'p': // 1 string to match.
	return Intrinsic::nvvm_ll2f_rp; // "__nvvm_ll2f_rp"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_ll2f_rz; // "__nvvm_ll2f_rz"
	}		}
	break;		break;
	}		case 'n': // 2 strings to match.
	break;		switch (BuiltinName[22]) {
	case 'm': // 4 strings to match.
	switch (BuiltinName[8]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+9, "x_ull", 5))
	break;
	return Intrinsic::nvvm_max_ull; // "__nvvm_max_ull"
	case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+9, "n_ull", 5))
	break;
	return Intrinsic::nvvm_min_ull; // "__nvvm_min_ull"
	case 'u': // 2 strings to match.
	if (BuiltinName[9] != 'l')
	break;
	switch (BuiltinName[10]) {
	default: break;		default: break;
	case '2': // 1 string to match.		case 'e': // 1 string to match.
	if (memcmp(BuiltinName.data()+11, "4_i", 3))		if (memcmp(BuiltinName.data()+23, "gp", 2))
	break;		break;
	return Intrinsic::nvvm_mul24_i; // "__nvvm_mul24_i"		return Intrinsic::hexagon_A2_negp; // "__builtin_HEXAGON_A2_ne
	case 'h': // 1 string to match.		gp"
	if (memcmp(BuiltinName.data()+11, "i_i", 3))		case 'o': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "tp", 2))
	break;		break;
	return Intrinsic::nvvm_mulhi_i; // "__nvvm_mulhi_i"		return Intrinsic::hexagon_A2_notp; // "__builtin_HEXAGON_A2_no tp"
	}		}
	break;		break;
	}		case 'o': // 1 string to match.
	break;		if (memcmp(BuiltinName.data()+22, "rir", 3))
	case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+8, "opc_ll", 6))
	break;
	return Intrinsic::nvvm_popc_ll; // "__nvvm_popc_ll"
	case 'r': // 2 strings to match.
	if (memcmp(BuiltinName.data()+8, "ound_", 5))
	break;
	switch (BuiltinName[13]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_round_d; // "__nvvm_round_d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_round_f; // "__nvvm_round_f"
	}
	break;
	case 't': // 2 strings to match.
	if (memcmp(BuiltinName.data()+8, "runc_", 5))
	break;
	switch (BuiltinName[13]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_trunc_d; // "__nvvm_trunc_d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_trunc_f; // "__nvvm_trunc_f"
	}
	break;
	case 'u': // 8 strings to match.
	if (memcmp(BuiltinName.data()+8, "i2", 2))
	break;
	switch (BuiltinName[10]) {
	default: break;
	case 'd': // 4 strings to match.
	if (memcmp(BuiltinName.data()+11, "_r", 2))
	break;		break;
	switch (BuiltinName[13]) {		return Intrinsic::hexagon_A2_orir; // "__builtin_HEXAGON_A2_or
			ir"
			case 's': // 7 strings to match.
			switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'a': // 2 strings to match.
	return Intrinsic::nvvm_ui2d_rm; // "__nvvm_ui2d_rm"		if (BuiltinName[23] != 't')
	case 'n': // 1 string to match.		break;
	return Intrinsic::nvvm_ui2d_rn; // "__nvvm_ui2d_rn"		switch (BuiltinName[24]) {
	case 'p': // 1 string to match.		default: break;
	return Intrinsic::nvvm_ui2d_rp; // "__nvvm_ui2d_rp"		case 'b': // 1 string to match.
	case 'z': // 1 string to match.		return Intrinsic::hexagon_A2_satb; // "__builtin_HEXAG
	return Intrinsic::nvvm_ui2d_rz; // "__nvvm_ui2d_rz"		ON_A2_satb"
	}		case 'h': // 1 string to match.
	break;		return Intrinsic::hexagon_A2_sath; // "__builtin_HEXAG
	case 'f': // 4 strings to match.		ON_A2_sath"
	if (memcmp(BuiltinName.data()+11, "_r", 2))		}
	break;		break;
	switch (BuiltinName[13]) {		case 'u': // 1 string to match.
	default: break;		if (memcmp(BuiltinName.data()+23, "bp", 2))
	case 'm': // 1 string to match.		break;
	return Intrinsic::nvvm_ui2f_rm; // "__nvvm_ui2f_rm"		return Intrinsic::hexagon_A2_subp; // "__builtin_HEXAGON_A2_su
	case 'n': // 1 string to match.		bp"
	return Intrinsic::nvvm_ui2f_rn; // "__nvvm_ui2f_rn"		case 'w': // 1 string to match.
	case 'p': // 1 string to match.		if (memcmp(BuiltinName.data()+23, "iz", 2))
	return Intrinsic::nvvm_ui2f_rp; // "__nvvm_ui2f_rp"		break;
	case 'z': // 1 string to match.		return Intrinsic::hexagon_A2_swiz; // "__builtin_HEXAGON_A2_sw
	return Intrinsic::nvvm_ui2f_rz; // "__nvvm_ui2f_rz"		iz"
	}		case 'x': // 3 strings to match.
	break;		if (BuiltinName[23] != 't')
	}		break;
	break;		switch (BuiltinName[24]) {
	}		default: break;
	break;		case 'b': // 1 string to match.
	}		return Intrinsic::hexagon_A2_sxtb; // "__builtin_HEXAG
	break;		ON_A2_sxtb"
	case 15: // 61 strings to match.		case 'h': // 1 string to match.
	if (memcmp(BuiltinName.data()+0, "__nvvm_", 7))		return Intrinsic::hexagon_A2_sxth; // "__builtin_HEXAG
	break;		ON_A2_sxth"
	switch (BuiltinName[7]) {		case 'w': // 1 string to match.
	default: break;		return Intrinsic::hexagon_A2_sxtw; // "__builtin_HEXAG
	case 'a': // 8 strings to match.		ON_A2_sxtw"
	if (memcmp(BuiltinName.data()+8, "dd_r", 4))		}
	break;
	switch (BuiltinName[12]) {
	default: break;
	case 'm': // 2 strings to match.
	if (BuiltinName[13] != '_')
	break;
	switch (BuiltinName[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_add_rm_d; // "__nvvm_add_rm_d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_add_rm_f; // "__nvvm_add_rm_f"
	}
	break;
	case 'n': // 2 strings to match.
	if (BuiltinName[13] != '_')
	break;
	switch (BuiltinName[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_add_rn_d; // "__nvvm_add_rn_d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_add_rn_f; // "__nvvm_add_rn_f"
	}
	break;
	case 'p': // 2 strings to match.
	if (BuiltinName[13] != '_')
	break;
	switch (BuiltinName[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_add_rp_d; // "__nvvm_add_rp_d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_add_rp_f; // "__nvvm_add_rp_f"
	}
	break;
	case 'z': // 2 strings to match.
	if (BuiltinName[13] != '_')
	break;
	switch (BuiltinName[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_add_rz_d; // "__nvvm_add_rz_d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_add_rz_f; // "__nvvm_add_rz_f"
	}
	break;
	}
	break;
	case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+8, "ar0_and", 7))
	break;
	return Intrinsic::nvvm_barrier0_and; // "__nvvm_bar0_and"
	case 'd': // 12 strings to match.
	switch (BuiltinName[8]) {
	default: break;
	case '2': // 4 strings to match.
	if (memcmp(BuiltinName.data()+9, "ull_r", 5))
	break;
	switch (BuiltinName[14]) {
	default: break;
	case 'm': // 1 string to match.
	return Intrinsic::nvvm_d2ull_rm; // "__nvvm_d2ull_rm"
	case 'n': // 1 string to match.
	return Intrinsic::nvvm_d2ull_rn; // "__nvvm_d2ull_rn"
	case 'p': // 1 string to match.
	return Intrinsic::nvvm_d2ull_rp; // "__nvvm_d2ull_rp"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_d2ull_rz; // "__nvvm_d2ull_rz"
	}
	break;
	case 'i': // 8 strings to match.
	if (memcmp(BuiltinName.data()+9, "v_r", 3))
	break;
	switch (BuiltinName[12]) {
	default: break;
	case 'm': // 2 strings to match.
	if (BuiltinName[13] != '_')
	break;		break;
	switch (BuiltinName[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_div_rm_d; // "__nvvm_div_rm_d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_div_rm_f; // "__nvvm_div_rm_f"
	}		}
	break;		break;
	case 'n': // 2 strings to match.		case 't': // 1 string to match.
	if (BuiltinName[13] != '_')		if (memcmp(BuiltinName.data()+22, "frp", 3))
	break;		break;
	switch (BuiltinName[14]) {		return Intrinsic::hexagon_A2_tfrp; // "__builtin_HEXAGON_A2_tf
	default: break;		rp"
	case 'd': // 1 string to match.		case 'x': // 1 string to match.
	return Intrinsic::nvvm_div_rn_d; // "__nvvm_div_rn_d"		if (memcmp(BuiltinName.data()+22, "orp", 3))
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_div_rn_f; // "__nvvm_div_rn_f"
	}
	break;
	case 'p': // 2 strings to match.
	if (BuiltinName[13] != '_')
	break;		break;
	switch (BuiltinName[14]) {		return Intrinsic::hexagon_A2_xorp; // "__builtin_HEXAGON_A2_xo
			rp"
			case 'z': // 2 strings to match.
			if (memcmp(BuiltinName.data()+22, "xt", 2))
			break;
			switch (BuiltinName[24]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::nvvm_div_rp_d; // "__nvvm_div_rp_d"		return Intrinsic::hexagon_A2_zxtb; // "__builtin_HEXAGON_A2_zx
	case 'f': // 1 string to match.		tb"
	return Intrinsic::nvvm_div_rp_f; // "__nvvm_div_rp_f"		case 'h': // 1 string to match.
			return Intrinsic::hexagon_A2_zxth; // "__builtin_HEXAGON_A2_zx
			th"
	}		}
	break;		break;
	case 'z': // 2 strings to match.		}
	if (BuiltinName[13] != '_')		break;
			case '4': // 2 strings to match.
			if (BuiltinName[20] != '_')
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "ndn", 3))
	break;		break;
	switch (BuiltinName[14]) {		return Intrinsic::hexagon_A4_andn; // "__builtin_HEXAGON_A4_an
			dn"
			case 'o': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "rnp", 3))
			break;
			return Intrinsic::hexagon_A4_ornp; // "__builtin_HEXAGON_A4_or
			np"
			}
			break;
			}
			break;
			case 'C': // 5 strings to match.
			if (memcmp(BuiltinName.data()+19, "2_", 2))
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'a': // 3 strings to match.
			switch (BuiltinName[22]) {
			default: break;
			case 'l': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "l8", 2))
			break;
			return Intrinsic::hexagon_C2_all8; // "__builtin_HEXAGON_C2_al
			l8"
			case 'n': // 2 strings to match.
			switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::nvvm_div_rz_d; // "__nvvm_div_rz_d"		if (BuiltinName[24] != 'n')
	case 'f': // 1 string to match.		break;
	return Intrinsic::nvvm_div_rz_f; // "__nvvm_div_rz_f"		return Intrinsic::hexagon_C2_andn; // "__builtin_HEXAGON_C2_an
			dn"
			case 'y': // 1 string to match.
			if (BuiltinName[24] != '8')
			break;
			return Intrinsic::hexagon_C2_any8; // "__builtin_HEXAGON_C2_an
			y8"
	}		}
	break;		break;
	}		}
	break;		break;
			case 'm': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "ask", 3))
			break;
			return Intrinsic::hexagon_C2_mask; // "__builtin_HEXAGON_C2_ma
			sk"
			case 'v': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "mux", 3))
			break;
			return Intrinsic::hexagon_C2_vmux; // "__builtin_HEXAGON_C2_vm
			ux"
	}		}
	break;		break;
	case 'f': // 12 strings to match.		case 'M': // 3 strings to match.
	switch (BuiltinName[8]) {		if (memcmp(BuiltinName.data()+19, "2_", 2))
			break;
			switch (BuiltinName[21]) {
	default: break;		default: break;
	case '2': // 4 strings to match.		case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+9, "ull_r", 5))		if (memcmp(BuiltinName.data()+22, "cci", 3))
	break;		break;
	switch (BuiltinName[14]) {		return Intrinsic::hexagon_M2_acci; // "__builtin_HEXAGON_M2_ac
			ci"
			case 'm': // 2 strings to match.
			switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'a': // 1 string to match.
	return Intrinsic::nvvm_f2ull_rm; // "__nvvm_f2ull_rm"		if (memcmp(BuiltinName.data()+23, "ci", 2))
	case 'n': // 1 string to match.		break;
	return Intrinsic::nvvm_f2ull_rn; // "__nvvm_f2ull_rn"		return Intrinsic::hexagon_M2_maci; // "__builtin_HEXAGON_M2_ma
			ci"
	case 'p': // 1 string to match.		case 'p': // 1 string to match.
	return Intrinsic::nvvm_f2ull_rp; // "__nvvm_f2ull_rp"		if (memcmp(BuiltinName.data()+23, "yi", 2))
	case 'z': // 1 string to match.		break;
	return Intrinsic::nvvm_f2ull_rz; // "__nvvm_f2ull_rz"		return Intrinsic::hexagon_M2_mpyi; // "__builtin_HEXAGON_M2_mp
			yi"
	}		}
	break;		break;
	case 'm': // 8 strings to match.		}
	if (memcmp(BuiltinName.data()+9, "a_r", 3))		break;
			case 'S': // 8 strings to match.
			switch (BuiltinName[19]) {
			default: break;
			case '2': // 7 strings to match.
			if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[12]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'm': // 2 strings to match.		case 'b': // 1 string to match.
	if (BuiltinName[13] != '_')		if (memcmp(BuiltinName.data()+22, "rev", 3))
	break;		break;
	switch (BuiltinName[14]) {		return Intrinsic::hexagon_S2_brev; // "__builtin_HEXAGON_S2_br
			ev"
			case 'c': // 5 strings to match.
			switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'l': // 3 strings to match.
	return Intrinsic::nvvm_fma_rm_d; // "__nvvm_fma_rm_d"		switch (BuiltinName[23]) {
	case 'f': // 1 string to match.		default: break;
	return Intrinsic::nvvm_fma_rm_f; // "__nvvm_fma_rm_f"		case '0': // 1 string to match.
			if (BuiltinName[24] != 'p')
			break;
			return Intrinsic::hexagon_S2_cl0p; // "__builtin_HEXAG
			ON_S2_cl0p"
			case '1': // 1 string to match.
			if (BuiltinName[24] != 'p')
			break;
			return Intrinsic::hexagon_S2_cl1p; // "__builtin_HEXAG
			ON_S2_cl1p"
			case 'b': // 1 string to match.
			if (BuiltinName[24] != 'p')
			break;
			return Intrinsic::hexagon_S2_clbp; // "__builtin_HEXAG
			ON_S2_clbp"
			}
			break;
			case 't': // 2 strings to match.
			switch (BuiltinName[23]) {
			default: break;
			case '0': // 1 string to match.
			if (BuiltinName[24] != 'p')
			break;
			return Intrinsic::hexagon_S2_ct0p; // "__builtin_HEXAG
			ON_S2_ct0p"
			case '1': // 1 string to match.
			if (BuiltinName[24] != 'p')
			break;
			return Intrinsic::hexagon_S2_ct1p; // "__builtin_HEXAG
			ON_S2_ct1p"
			}
			break;
	}		}
	break;		break;
	case 'n': // 2 strings to match.		case 'l': // 1 string to match.
	if (BuiltinName[13] != '_')		if (memcmp(BuiltinName.data()+22, "fsp", 3))
	break;		break;
	switch (BuiltinName[14]) {		return Intrinsic::hexagon_S2_lfsp; // "__builtin_HEXAGON_S2_lf
	default: break;		sp"
	case 'd': // 1 string to match.		}
	return Intrinsic::nvvm_fma_rn_d; // "__nvvm_fma_rn_d"		break;
	case 'f': // 1 string to match.		case '4': // 1 string to match.
	return Intrinsic::nvvm_fma_rn_f; // "__nvvm_fma_rn_f"		if (memcmp(BuiltinName.data()+20, "_lsli", 5))
	}
	break;		break;
	case 'p': // 2 strings to match.		return Intrinsic::hexagon_S4_lsli; // "__builtin_HEXAGON_S4_ls
	if (BuiltinName[13] != '_')		li"
			}
			break;
			}
			break;
			case 26: // 58 strings to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_", 10))
			break;
			switch (BuiltinName[10]) {
			default: break;
			case 'H': // 57 strings to match.
			if (memcmp(BuiltinName.data()+11, "EXAGON_", 7))
			break;
			switch (BuiltinName[18]) {
			default: break;
			case 'A': // 27 strings to match.
			switch (BuiltinName[19]) {
			default: break;
			case '2': // 26 strings to match.
			if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[14]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'a': // 2 strings to match.
	return Intrinsic::nvvm_fma_rp_d; // "__nvvm_fma_rp_d"		switch (BuiltinName[22]) {
	case 'f': // 1 string to match.		default: break;
	return Intrinsic::nvvm_fma_rp_f; // "__nvvm_fma_rp_f"		case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "dsp", 3))
			break;
			return Intrinsic::hexagon_A2_addsp; // "__builtin_HEXAG
			ON_A2_addsp"
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "dir", 3))
			break;
			return Intrinsic::hexagon_A2_andir; // "__builtin_HEXAG
			ON_A2_andir"
			}
			break;
			case 'm': // 2 strings to match.
			switch (BuiltinName[22]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "xup", 3))
			break;
			return Intrinsic::hexagon_A2_maxup; // "__builtin_HEXAG
			ON_A2_maxup"
			case 'i': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "nup", 3))
			break;
			return Intrinsic::hexagon_A2_minup; // "__builtin_HEXAG
			ON_A2_minup"
			}
			break;
			case 's': // 3 strings to match.
			switch (BuiltinName[22]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(BuiltinName.data()+23, "tu", 2))
			break;
			switch (BuiltinName[25]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::hexagon_A2_satub; // "__builtin_HEXAG
			ON_A2_satub"
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_A2_satuh; // "__builtin_HEXAG
			ON_A2_satuh"
			}
			break;
			case 'u': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "bri", 3))
			break;
			return Intrinsic::hexagon_A2_subri; // "__builtin_HEXAG
			ON_A2_subri"
			}
			break;
			case 't': // 4 strings to match.
			if (memcmp(BuiltinName.data()+22, "fr", 2))
			break;
			switch (BuiltinName[24]) {
			default: break;
			case 'i': // 2 strings to match.
			switch (BuiltinName[25]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_A2_tfrih; // "__builtin_HEXAG
			ON_A2_tfrih"
			case 'l': // 1 string to match.
			return Intrinsic::hexagon_A2_tfril; // "__builtin_HEXAG
			ON_A2_tfril"
			}
			break;
			case 'p': // 1 string to match.
			if (BuiltinName[25] != 'i')
			break;
			return Intrinsic::hexagon_A2_tfrpi; // "__builtin_HEXAG
			ON_A2_tfrpi"
			case 's': // 1 string to match.
			if (BuiltinName[25] != 'i')
			break;
			return Intrinsic::hexagon_A2_tfrsi; // "__builtin_HEXAG
			ON_A2_tfrsi"
			}
			break;
			case 'v': // 15 strings to match.
			switch (BuiltinName[22]) {
			default: break;
			case 'a': // 6 strings to match.
			switch (BuiltinName[23]) {
			default: break;
			case 'b': // 2 strings to match.
			if (BuiltinName[24] != 's')
			break;
			switch (BuiltinName[25]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_A2_vabsh; // "__builtin_HEXAG
			ON_A2_vabsh"
			case 'w': // 1 string to match.
			return Intrinsic::hexagon_A2_vabsw; // "__builtin_HEXAG
			ON_A2_vabsw"
			}
			break;
			case 'd': // 2 strings to match.
			if (BuiltinName[24] != 'd')
			break;
			switch (BuiltinName[25]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_A2_vaddh; // "__builtin_HEXAG
			ON_A2_vaddh"
			case 'w': // 1 string to match.
			return Intrinsic::hexagon_A2_vaddw; // "__builtin_HEXAG
			ON_A2_vaddw"
			}
			break;
			case 'v': // 2 strings to match.
			if (BuiltinName[24] != 'g')
			break;
			switch (BuiltinName[25]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_A2_vavgh; // "__builtin_HEXAG
			ON_A2_vavgh"
			case 'w': // 1 string to match.
			return Intrinsic::hexagon_A2_vavgw; // "__builtin_HEXAG
			ON_A2_vavgw"
			}
			break;
			}
			break;
			case 'c': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "onj", 3))
			break;
			return Intrinsic::hexagon_A2_vconj; // "__builtin_HEXAG
			ON_A2_vconj"
			case 'm': // 6 strings to match.
			switch (BuiltinName[23]) {
			default: break;
			case 'a': // 3 strings to match.
			if (BuiltinName[24] != 'x')
			break;
			switch (BuiltinName[25]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::hexagon_A2_vmaxb; // "__builtin_HEXAG
			ON_A2_vmaxb"
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_A2_vmaxh; // "__builtin_HEXAG
			ON_A2_vmaxh"
			case 'w': // 1 string to match.
			return Intrinsic::hexagon_A2_vmaxw; // "__builtin_HEXAG
			ON_A2_vmaxw"
			}
			break;
			case 'i': // 3 strings to match.
			if (BuiltinName[24] != 'n')
			break;
			switch (BuiltinName[25]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::hexagon_A2_vminb; // "__builtin_HEXAG
			ON_A2_vminb"
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_A2_vminh; // "__builtin_HEXAG
			ON_A2_vminh"
			case 'w': // 1 string to match.
			return Intrinsic::hexagon_A2_vminw; // "__builtin_HEXAG
			ON_A2_vminw"
			}
			break;
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(BuiltinName.data()+23, "ub", 2))
			break;
			switch (BuiltinName[25]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_A2_vsubh; // "__builtin_HEXAG
			ON_A2_vsubh"
			case 'w': // 1 string to match.
			return Intrinsic::hexagon_A2_vsubw; // "__builtin_HEXAG
			ON_A2_vsubw"
			}
			break;
			}
			break;
	}		}
	break;		break;
	case 'z': // 2 strings to match.		case '4': // 1 string to match.
	if (BuiltinName[13] != '_')		if (memcmp(BuiltinName.data()+20, "_andnp", 6))
	break;		break;
	switch (BuiltinName[14]) {		return Intrinsic::hexagon_A4_andnp; // "__builtin_HEXAGON_A4_an
			dnp"
			}
			break;
			case 'C': // 9 strings to match.
			switch (BuiltinName[19]) {
			default: break;
			case '2': // 8 strings to match.
			if (BuiltinName[20] != '_')
			break;
			switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'c': // 3 strings to match.
	return Intrinsic::nvvm_fma_rz_d; // "__nvvm_fma_rz_d"		if (memcmp(BuiltinName.data()+22, "mp", 2))
	case 'f': // 1 string to match.		break;
	return Intrinsic::nvvm_fma_rz_f; // "__nvvm_fma_rz_f"		switch (BuiltinName[24]) {
			default: break;
			case 'e': // 1 string to match.
			if (BuiltinName[25] != 'q')
			break;
			return Intrinsic::hexagon_C2_cmpeq; // "__builtin_HEXAG
			ON_C2_cmpeq"
			case 'g': // 1 string to match.
			if (BuiltinName[25] != 't')
			break;
			return Intrinsic::hexagon_C2_cmpgt; // "__builtin_HEXAG
			ON_C2_cmpgt"
			case 'l': // 1 string to match.
			if (BuiltinName[25] != 't')
			break;
			return Intrinsic::hexagon_C2_cmplt; // "__builtin_HEXAG
			ON_C2_cmplt"
			}
			break;
			case 'm': // 3 strings to match.
			if (memcmp(BuiltinName.data()+22, "ux", 2))
			break;
			switch (BuiltinName[24]) {
			default: break;
			case 'i': // 2 strings to match.
			switch (BuiltinName[25]) {
			default: break;
			case 'i': // 1 string to match.
			return Intrinsic::hexagon_C2_muxii; // "__builtin_HEXAG
			ON_C2_muxii"
			case 'r': // 1 string to match.
			return Intrinsic::hexagon_C2_muxir; // "__builtin_HEXAG
			ON_C2_muxir"
			}
			break;
			case 'r': // 1 string to match.
			if (BuiltinName[25] != 'i')
			break;
			return Intrinsic::hexagon_C2_muxri; // "__builtin_HEXAG
			ON_C2_muxri"
			}
			break;
			case 't': // 2 strings to match.
			if (memcmp(BuiltinName.data()+22, "fr", 2))
			break;
			switch (BuiltinName[24]) {
			default: break;
			case 'p': // 1 string to match.
			if (BuiltinName[25] != 'r')
			break;
			return Intrinsic::hexagon_C2_tfrpr; // "__builtin_HEXAG
			ON_C2_tfrpr"
			case 'r': // 1 string to match.
			if (BuiltinName[25] != 'p')
			break;
			return Intrinsic::hexagon_C2_tfrrp; // "__builtin_HEXAG
			ON_C2_tfrrp"
			}
			break;
	}		}
	break;		break;
			case '4': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "_or_or", 6))
			break;
			return Intrinsic::hexagon_C4_or_or; // "__builtin_HEXAGON_C4_or
			_or"
	}		}
	break;		break;
	}		case 'F': // 14 strings to match.
	break;		if (memcmp(BuiltinName.data()+19, "2_", 2))
	case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+8, "ohi_i2d", 7))
	break;
	return Intrinsic::nvvm_lohi_i2d; // "__nvvm_lohi_i2d"
	case 'm': // 11 strings to match.
	if (memcmp(BuiltinName.data()+8, "ul", 2))
	break;
	switch (BuiltinName[10]) {
	default: break;
	case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+11, "4_ui", 4))
	break;
	return Intrinsic::nvvm_mul24_ui; // "__nvvm_mul24_ui"
	case '_': // 8 strings to match.
	if (BuiltinName[11] != 'r')
	break;		break;
	switch (BuiltinName[12]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'm': // 2 strings to match.		case 'd': // 7 strings to match.
	if (BuiltinName[13] != '_')		if (BuiltinName[22] != 'f')
	break;		break;
	switch (BuiltinName[14]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'a': // 1 string to match.
	return Intrinsic::nvvm_mul_rm_d; // "__nvvm_mul_rm_d"		if (memcmp(BuiltinName.data()+24, "dd", 2))
	case 'f': // 1 string to match.		break;
	return Intrinsic::nvvm_mul_rm_f; // "__nvvm_mul_rm_f"		return Intrinsic::hexagon_F2_dfadd; // "__builtin_HEXAG
	}		ON_F2_dfadd"
	break;		case 'f': // 2 strings to match.
	case 'n': // 2 strings to match.		if (BuiltinName[24] != 'm')
	if (BuiltinName[13] != '_')		break;
			switch (BuiltinName[25]) {
			default: break;
			case 'a': // 1 string to match.
			return Intrinsic::hexagon_F2_dffma; // "__builtin_HEXAG
			ON_F2_dffma"
			case 's': // 1 string to match.
			return Intrinsic::hexagon_F2_dffms; // "__builtin_HEXAG
			ON_F2_dffms"
			}
			break;
			case 'm': // 3 strings to match.
			switch (BuiltinName[24]) {
			default: break;
			case 'a': // 1 string to match.
			if (BuiltinName[25] != 'x')
			break;
			return Intrinsic::hexagon_F2_dfmax; // "__builtin_HEXAG
			ON_F2_dfmax"
			case 'i': // 1 string to match.
			if (BuiltinName[25] != 'n')
			break;
			return Intrinsic::hexagon_F2_dfmin; // "__builtin_HEXAG
			ON_F2_dfmin"
			case 'p': // 1 string to match.
			if (BuiltinName[25] != 'y')
			break;
			return Intrinsic::hexagon_F2_dfmpy; // "__builtin_HEXAG
			ON_F2_dfmpy"
			}
	break;		break;
	switch (BuiltinName[14]) {		case 's': // 1 string to match.
	default: break;		if (memcmp(BuiltinName.data()+24, "ub", 2))
	case 'd': // 1 string to match.		break;
	return Intrinsic::nvvm_mul_rn_d; // "__nvvm_mul_rn_d"		return Intrinsic::hexagon_F2_dfsub; // "__builtin_HEXAG
	case 'f': // 1 string to match.		ON_F2_dfsub"
	return Intrinsic::nvvm_mul_rn_f; // "__nvvm_mul_rn_f"
	}		}
	break;		break;
	case 'p': // 2 strings to match.		case 's': // 7 strings to match.
	if (BuiltinName[13] != '_')		if (BuiltinName[22] != 'f')
	break;		break;
	switch (BuiltinName[14]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'a': // 1 string to match.
	return Intrinsic::nvvm_mul_rp_d; // "__nvvm_mul_rp_d"		if (memcmp(BuiltinName.data()+24, "dd", 2))
	case 'f': // 1 string to match.		break;
	return Intrinsic::nvvm_mul_rp_f; // "__nvvm_mul_rp_f"		return Intrinsic::hexagon_F2_sfadd; // "__builtin_HEXAG
	}		ON_F2_sfadd"
	break;		case 'f': // 2 strings to match.
	case 'z': // 2 strings to match.		if (BuiltinName[24] != 'm')
	if (BuiltinName[13] != '_')		break;
			switch (BuiltinName[25]) {
			default: break;
			case 'a': // 1 string to match.
			return Intrinsic::hexagon_F2_sffma; // "__builtin_HEXAG
			ON_F2_sffma"
			case 's': // 1 string to match.
			return Intrinsic::hexagon_F2_sffms; // "__builtin_HEXAG
			ON_F2_sffms"
			}
	break;		break;
	switch (BuiltinName[14]) {		case 'm': // 3 strings to match.
	default: break;		switch (BuiltinName[24]) {
	case 'd': // 1 string to match.		default: break;
	return Intrinsic::nvvm_mul_rz_d; // "__nvvm_mul_rz_d"		case 'a': // 1 string to match.
	case 'f': // 1 string to match.		if (BuiltinName[25] != 'x')
	return Intrinsic::nvvm_mul_rz_f; // "__nvvm_mul_rz_f"		break;
			return Intrinsic::hexagon_F2_sfmax; // "__builtin_HEXAG
			ON_F2_sfmax"
			case 'i': // 1 string to match.
			if (BuiltinName[25] != 'n')
			break;
			return Intrinsic::hexagon_F2_sfmin; // "__builtin_HEXAG
			ON_F2_sfmin"
			case 'p': // 1 string to match.
			if (BuiltinName[25] != 'y')
			break;
			return Intrinsic::hexagon_F2_sfmpy; // "__builtin_HEXAG
			ON_F2_sfmpy"
			}
			break;
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "ub", 2))
			break;
			return Intrinsic::hexagon_F2_sfsub; // "__builtin_HEXAG
			ON_F2_sfsub"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'h': // 2 strings to match.		case 'M': // 6 strings to match.
	if (memcmp(BuiltinName.data()+11, "i_", 2))		switch (BuiltinName[19]) {
	break;
	switch (BuiltinName[13]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case '2': // 4 strings to match.
	if (BuiltinName[14] != 'l')		if (BuiltinName[20] != '_')
	break;
	return Intrinsic::nvvm_mulhi_ll; // "__nvvm_mulhi_ll"
	case 'u': // 1 string to match.
	if (BuiltinName[14] != 'i')
	break;		break;
	return Intrinsic::nvvm_mulhi_ui; // "__nvvm_mulhi_ui"		switch (BuiltinName[21]) {
	}		default: break;
	break;		case 'a': // 1 string to match.
	}		if (memcmp(BuiltinName.data()+22, "ccii", 4))
	break;		break;
	case 'r': // 8 strings to match.		return Intrinsic::hexagon_M2_accii; // "__builtin_HEXAG
	if (memcmp(BuiltinName.data()+8, "cp_r", 4))		ON_M2_accii"
	break;		case 'm': // 1 string to match.
	switch (BuiltinName[12]) {		if (memcmp(BuiltinName.data()+22, "pyui", 4))
	default: break;		break;
	case 'm': // 2 strings to match.		return Intrinsic::hexagon_M2_mpyui; // "__builtin_HEXAG
	if (BuiltinName[13] != '_')		ON_M2_mpyui"
	break;		case 'n': // 1 string to match.
	switch (BuiltinName[14]) {		if (memcmp(BuiltinName.data()+22, "acci", 4))
	default: break;		break;
	case 'd': // 1 string to match.		return Intrinsic::hexagon_M2_nacci; // "__builtin_HEXAG
	return Intrinsic::nvvm_rcp_rm_d; // "__nvvm_rcp_rm_d"		ON_M2_nacci"
	case 'f': // 1 string to match.		case 'v': // 1 string to match.
	return Intrinsic::nvvm_rcp_rm_f; // "__nvvm_rcp_rm_f"		if (memcmp(BuiltinName.data()+22, "mac2", 4))
	}		break;
	break;		return Intrinsic::hexagon_M2_vmac2; // "__builtin_HEXAG
	case 'n': // 2 strings to match.		ON_M2_vmac2"
	if (BuiltinName[13] != '_')		}
	break;		break;
	switch (BuiltinName[14]) {		case '4': // 2 strings to match.
	default: break;		if (BuiltinName[20] != '_')
	case 'd': // 1 string to match.		break;
	return Intrinsic::nvvm_rcp_rn_d; // "__nvvm_rcp_rn_d"		switch (BuiltinName[21]) {
	case 'f': // 1 string to match.		default: break;
	return Intrinsic::nvvm_rcp_rn_f; // "__nvvm_rcp_rn_f"		case 'o': // 1 string to match.
	}		if (memcmp(BuiltinName.data()+22, "r_or", 4))
	break;		break;
	case 'p': // 2 strings to match.		return Intrinsic::hexagon_M4_or_or; // "__builtin_HEXAG
	if (BuiltinName[13] != '_')		ON_M4_or_or"
			case 'p': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "mpyw", 4))
			break;
			return Intrinsic::hexagon_M4_pmpyw; // "__builtin_HEXAG
			ON_M4_pmpyw"
			}
	break;		break;
	switch (BuiltinName[14]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_rcp_rp_d; // "__nvvm_rcp_rp_d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_rcp_rp_f; // "__nvvm_rcp_rp_f"
	}		}
	break;		break;
	case 'z': // 2 strings to match.		case 'S': // 1 string to match.
	if (BuiltinName[13] != '_')		if (memcmp(BuiltinName.data()+19, "2_brevp", 7))
	break;		break;
	switch (BuiltinName[14]) {		return Intrinsic::hexagon_S2_brevp; // "__builtin_HEXAGON_S2_br
	default: break;		evp"
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_rcp_rz_d; // "__nvvm_rcp_rz_d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_rcp_rz_f; // "__nvvm_rcp_rz_f"
	}
	break;
	}		}
	break;		break;
	case 'u': // 8 strings to match.		case 'S': // 1 string to match.
	if (memcmp(BuiltinName.data()+8, "ll2", 3))		if (memcmp(BuiltinName.data()+11, "I_to_SXTHI_asrh", 15))
	break;
	switch (BuiltinName[11]) {
	default: break;
	case 'd': // 4 strings to match.
	if (memcmp(BuiltinName.data()+12, "_r", 2))
	break;
	switch (BuiltinName[14]) {
	default: break;
	case 'm': // 1 string to match.
	return Intrinsic::nvvm_ull2d_rm; // "__nvvm_ull2d_rm"
	case 'n': // 1 string to match.
	return Intrinsic::nvvm_ull2d_rn; // "__nvvm_ull2d_rn"
	case 'p': // 1 string to match.
	return Intrinsic::nvvm_ull2d_rp; // "__nvvm_ull2d_rp"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_ull2d_rz; // "__nvvm_ull2d_rz"
	}
	break;
	case 'f': // 4 strings to match.
	if (memcmp(BuiltinName.data()+12, "_r", 2))
	break;
	switch (BuiltinName[14]) {
	default: break;
	case 'm': // 1 string to match.
	return Intrinsic::nvvm_ull2f_rm; // "__nvvm_ull2f_rm"
	case 'n': // 1 string to match.
	return Intrinsic::nvvm_ull2f_rn; // "__nvvm_ull2f_rn"
	case 'p': // 1 string to match.
	return Intrinsic::nvvm_ull2f_rp; // "__nvvm_ull2f_rp"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_ull2f_rz; // "__nvvm_ull2f_rz"
	}
	break;		break;
	}		return Intrinsic::hexagon_SI_to_SXTHI_asrh; // "__builtin_SI_to
	break;		_SXTHI_asrh"
	}		}
	break;		break;
	case 16: // 11 strings to match.		case 27: // 70 strings to match.
	if (memcmp(BuiltinName.data()+0, "__nvvm_", 7))		if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
	break;		break;
	switch (BuiltinName[7]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'A': // 35 strings to match.
	if (memcmp(BuiltinName.data()+8, "ar0_popc", 8))		switch (BuiltinName[19]) {
	break;
	return Intrinsic::nvvm_barrier0_popc; // "__nvvm_bar0_popc"
	case 'm': // 2 strings to match.
	switch (BuiltinName[8]) {
	default: break;
	case 'e': // 1 string to match.
	if (memcmp(BuiltinName.data()+9, "mbar_gl", 7))
	break;
	return Intrinsic::nvvm_membar_gl; // "__nvvm_membar_gl"
	case 'u': // 1 string to match.
	if (memcmp(BuiltinName.data()+9, "lhi_ull", 7))
	break;
	return Intrinsic::nvvm_mulhi_ull; // "__nvvm_mulhi_ull"
	}
	break;
	case 's': // 8 strings to match.
	if (memcmp(BuiltinName.data()+8, "qrt_r", 5))
	break;
	switch (BuiltinName[13]) {
	default: break;		default: break;
	case 'm': // 2 strings to match.		case '2': // 26 strings to match.
	if (BuiltinName[14] != '_')		if (BuiltinName[20] != '_')
	break;
	switch (BuiltinName[15]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_sqrt_rm_d; // "__nvvm_sqrt_rm_d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_sqrt_rm_f; // "__nvvm_sqrt_rm_f"
	}
	break;
	case 'n': // 2 strings to match.
	if (BuiltinName[14] != '_')
	break;
	switch (BuiltinName[15]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_sqrt_rn_d; // "__nvvm_sqrt_rn_d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_sqrt_rn_f; // "__nvvm_sqrt_rn_f"
	}
	break;
	case 'p': // 2 strings to match.
	if (BuiltinName[14] != '_')
	break;
	switch (BuiltinName[15]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_sqrt_rp_d; // "__nvvm_sqrt_rp_d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_sqrt_rp_f; // "__nvvm_sqrt_rp_f"
	}
	break;
	case 'z': // 2 strings to match.
	if (BuiltinName[14] != '_')
	break;		break;
	switch (BuiltinName[15]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'a': // 2 strings to match.
	return Intrinsic::nvvm_sqrt_rz_d; // "__nvvm_sqrt_rz_d"		switch (BuiltinName[22]) {
	case 'f': // 1 string to match.		default: break;
	return Intrinsic::nvvm_sqrt_rz_f; // "__nvvm_sqrt_rz_f"		case 'b': // 1 string to match.
	}		if (memcmp(BuiltinName.data()+23, "ssat", 4))
	break;		break;
	}		return Intrinsic::hexagon_A2_abssat; // "__builtin_HEXAG
	break;		ON_A2_abssat"
	}		case 'd': // 1 string to match.
	break;		if (memcmp(BuiltinName.data()+23, "dsat", 4))
	case 17: // 17 strings to match.		break;
	if (memcmp(BuiltinName.data()+0, "__nvvm_", 7))		return Intrinsic::hexagon_A2_addsat; // "__builtin_HEXAG
	break;		ON_A2_addsat"
	switch (BuiltinName[7]) {		}
	default: break;
	case 'c': // 1 string to match.
	if (memcmp(BuiltinName.data()+8, "eil_ftz_f", 9))
	break;
	return Intrinsic::nvvm_ceil_ftz_f; // "__nvvm_ceil_ftz_f"
	case 'd': // 4 strings to match.
	if (memcmp(BuiltinName.data()+8, "2f_r", 4))
	break;
	switch (BuiltinName[12]) {
	default: break;
	case 'm': // 1 string to match.
	if (memcmp(BuiltinName.data()+13, "_ftz", 4))
	break;
	return Intrinsic::nvvm_d2f_rm_ftz; // "__nvvm_d2f_rm_ftz"
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+13, "_ftz", 4))
	break;
	return Intrinsic::nvvm_d2f_rn_ftz; // "__nvvm_d2f_rn_ftz"
	case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+13, "_ftz", 4))
	break;
	return Intrinsic::nvvm_d2f_rp_ftz; // "__nvvm_d2f_rp_ftz"
	case 'z': // 1 string to match.
	if (memcmp(BuiltinName.data()+13, "_ftz", 4))
	break;		break;
	return Intrinsic::nvvm_d2f_rz_ftz; // "__nvvm_d2f_rz_ftz"		case 'n': // 1 string to match.
	}		if (memcmp(BuiltinName.data()+22, "egsat", 5))
	break;
	case 'f': // 8 strings to match.
	switch (BuiltinName[8]) {
	default: break;
	case '2': // 5 strings to match.
	switch (BuiltinName[9]) {
	default: break;
	case 'h': // 1 string to match.
	if (memcmp(BuiltinName.data()+10, "_rn_ftz", 7))
	break;		break;
	return Intrinsic::nvvm_f2h_rn_ftz; // "__nvvm_f2h_rn_ftz"		return Intrinsic::hexagon_A2_negsat; // "__builtin_HEXAGON_A2_ne
	case 'i': // 4 strings to match.		gsat"
	if (memcmp(BuiltinName.data()+10, "_r", 2))		case 's': // 4 strings to match.
			switch (BuiltinName[22]) {
			default: break;
			case 'u': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "bsat", 4))
			break;
			return Intrinsic::hexagon_A2_subsat; // "__builtin_HEXAG
			ON_A2_subsat"
			case 'v': // 3 strings to match.
			switch (BuiltinName[23]) {
			default: break;
			case 'a': // 2 strings to match.
			switch (BuiltinName[24]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "dh", 2))
			break;
			return Intrinsic::hexagon_A2_svaddh; // "__builtin_HEXAG
			ON_A2_svaddh"
			case 'v': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "gh", 2))
			break;
			return Intrinsic::hexagon_A2_svavgh; // "__builtin_HEXAG
			ON_A2_svavgh"
			}
			break;
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "ubh", 3))
			break;
			return Intrinsic::hexagon_A2_svsubh; // "__builtin_HEXAG
			ON_A2_svsubh"
			}
	break;		break;
	switch (BuiltinName[12]) {		}
			break;
			case 'v': // 19 strings to match.
			switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'a': // 8 strings to match.
	if (memcmp(BuiltinName.data()+13, "_ftz", 4))		switch (BuiltinName[23]) {
			default: break;
			case 'd': // 3 strings to match.
			if (BuiltinName[24] != 'd')
			break;
			switch (BuiltinName[25]) {
			default: break;
			case 'h': // 1 string to match.
			if (BuiltinName[26] != 's')
			break;
			return Intrinsic::hexagon_A2_vaddhs; // "__builtin_HEXAG
			ON_A2_vaddhs"
			case 'u': // 1 string to match.
			if (BuiltinName[26] != 'b')
			break;
			return Intrinsic::hexagon_A2_vaddub; // "__builtin_HEXAG
			ON_A2_vaddub"
			case 'w': // 1 string to match.
			if (BuiltinName[26] != 's')
			break;
			return Intrinsic::hexagon_A2_vaddws; // "__builtin_HEXAG
			ON_A2_vaddws"
			}
	break;		break;
	return Intrinsic::nvvm_f2i_rm_ftz; // "__nvvm_f2i_rm_ftz"		case 'v': // 5 strings to match.
	case 'n': // 1 string to match.		if (BuiltinName[24] != 'g')
	if (memcmp(BuiltinName.data()+13, "_ftz", 4))		break;
			switch (BuiltinName[25]) {
			default: break;
			case 'h': // 1 string to match.
			if (BuiltinName[26] != 'r')
			break;
			return Intrinsic::hexagon_A2_vavghr; // "__builtin_HEXAG
			ON_A2_vavghr"
			case 'u': // 3 strings to match.
			switch (BuiltinName[26]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::hexagon_A2_vavgub; // "__builtin_HEXAG
			ON_A2_vavgub"
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_A2_vavguh; // "__builtin_HEXAG
			ON_A2_vavguh"
			case 'w': // 1 string to match.
			return Intrinsic::hexagon_A2_vavguw; // "__builtin_HEXAG
			ON_A2_vavguw"
			}
			break;
			case 'w': // 1 string to match.
			if (BuiltinName[26] != 'r')
			break;
			return Intrinsic::hexagon_A2_vavgwr; // "__builtin_HEXAG
			ON_A2_vavgwr"
			}
	break;		break;
	return Intrinsic::nvvm_f2i_rn_ftz; // "__nvvm_f2i_rn_ftz"		}
	case 'p': // 1 string to match.		break;
	if (memcmp(BuiltinName.data()+13, "_ftz", 4))		case 'm': // 6 strings to match.
			switch (BuiltinName[23]) {
			default: break;
			case 'a': // 3 strings to match.
			if (memcmp(BuiltinName.data()+24, "xu", 2))
			break;
			switch (BuiltinName[26]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::hexagon_A2_vmaxub; // "__builtin_HEXAG
			ON_A2_vmaxub"
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_A2_vmaxuh; // "__builtin_HEXAG
			ON_A2_vmaxuh"
			case 'w': // 1 string to match.
			return Intrinsic::hexagon_A2_vmaxuw; // "__builtin_HEXAG
			ON_A2_vmaxuw"
			}
	break;		break;
	return Intrinsic::nvvm_f2i_rp_ftz; // "__nvvm_f2i_rp_ftz"		case 'i': // 3 strings to match.
	case 'z': // 1 string to match.		if (memcmp(BuiltinName.data()+24, "nu", 2))
	if (memcmp(BuiltinName.data()+13, "_ftz", 4))		break;
			switch (BuiltinName[26]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::hexagon_A2_vminub; // "__builtin_HEXAG
			ON_A2_vminub"
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_A2_vminuh; // "__builtin_HEXAG
			ON_A2_vminuh"
			case 'w': // 1 string to match.
			return Intrinsic::hexagon_A2_vminuw; // "__builtin_HEXAG
			ON_A2_vminuw"
			}
	break;		break;
	return Intrinsic::nvvm_f2i_rz_ftz; // "__nvvm_f2i_rz_ftz"		}
	}
	break;
	}
	break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+9, "bs_ftz_f", 8))
	break;
	return Intrinsic::nvvm_fabs_ftz_f; // "__nvvm_fabs_ftz_f"
	case 'm': // 2 strings to match.
	switch (BuiltinName[9]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+10, "x_ftz_f", 7))
	break;		break;
	return Intrinsic::nvvm_fmax_ftz_f; // "__nvvm_fmax_ftz_f"		case 'n': // 2 strings to match.
	case 'i': // 1 string to match.		if (memcmp(BuiltinName.data()+23, "avg", 3))
	if (memcmp(BuiltinName.data()+10, "n_ftz_f", 7))		break;
			switch (BuiltinName[26]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_A2_vnavgh; // "__builtin_HEXAG
			ON_A2_vnavgh"
			case 'w': // 1 string to match.
			return Intrinsic::hexagon_A2_vnavgw; // "__builtin_HEXAG
			ON_A2_vnavgw"
			}
	break;		break;
	return Intrinsic::nvvm_fmin_ftz_f; // "__nvvm_fmin_ftz_f"		case 's': // 3 strings to match.
	}		if (memcmp(BuiltinName.data()+23, "ub", 2))
	break;		break;
	}		switch (BuiltinName[25]) {
	break;		default: break;
	case 'm': // 2 strings to match.		case 'h': // 1 string to match.
	if (memcmp(BuiltinName.data()+8, "embar_", 6))		if (BuiltinName[26] != 's')
	break;		break;
	switch (BuiltinName[14]) {		return Intrinsic::hexagon_A2_vsubhs; // "__builtin_HEXAG
	default: break;		ON_A2_vsubhs"
	case 'c': // 1 string to match.		case 'u': // 1 string to match.
	if (memcmp(BuiltinName.data()+15, "ta", 2))		if (BuiltinName[26] != 'b')
	break;		break;
	return Intrinsic::nvvm_membar_cta; // "__nvvm_membar_cta"		return Intrinsic::hexagon_A2_vsubub; // "__builtin_HEXAG
	case 's': // 1 string to match.		ON_A2_vsubub"
	if (memcmp(BuiltinName.data()+15, "ys", 2))		case 'w': // 1 string to match.
			if (BuiltinName[26] != 's')
			break;
			return Intrinsic::hexagon_A2_vsubws; // "__builtin_HEXAG
			ON_A2_vsubws"
			}
			break;
			}
	break;		break;
	return Intrinsic::nvvm_membar_sys; // "__nvvm_membar_sys"		}
	}
	break;
	case 's': // 2 strings to match.
	if (memcmp(BuiltinName.data()+8, "aturate_", 8))
	break;
	switch (BuiltinName[16]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_saturate_d; // "__nvvm_saturate_d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_saturate_f; // "__nvvm_saturate_f"
	}
	break;
	}
	break;
	case 18: // 13 strings to match.
	if (memcmp(BuiltinName.data()+0, "__nvvm_", 7))
	break;
	switch (BuiltinName[7]) {
	default: break;
	case 'b': // 2 strings to match.
	if (memcmp(BuiltinName.data()+8, "itcast_", 7))
	break;		break;
	switch (BuiltinName[15]) {		case '4': // 9 strings to match.
	default: break;		if (BuiltinName[20] != '_')
	case 'f': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "2i", 2))
	break;
	return Intrinsic::nvvm_bitcast_f2i; // "__nvvm_bitcast_f2i"
	case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "2f", 2))
	break;		break;
	return Intrinsic::nvvm_bitcast_i2f; // "__nvvm_bitcast_i2f"		switch (BuiltinName[21]) {
	}
	break;
	case 'f': // 9 strings to match.
	switch (BuiltinName[8]) {
	default: break;
	case '2': // 8 strings to match.
	switch (BuiltinName[9]) {
	default: break;		default: break;
	case 'l': // 4 strings to match.		case 'c': // 4 strings to match.
	if (memcmp(BuiltinName.data()+10, "l_r", 3))		if (memcmp(BuiltinName.data()+22, "mp", 2))
	break;		break;
	switch (BuiltinName[13]) {		switch (BuiltinName[24]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'b': // 2 strings to match.
	if (memcmp(BuiltinName.data()+14, "_ftz", 4))		switch (BuiltinName[25]) {
	break;		default: break;
	return Intrinsic::nvvm_f2ll_rm_ftz; // "__nvvm_f2ll_rm_		case 'e': // 1 string to match.
	ftz"		if (BuiltinName[26] != 'q')
	case 'n': // 1 string to match.		break;
	if (memcmp(BuiltinName.data()+14, "_ftz", 4))		return Intrinsic::hexagon_A4_cmpbeq; // "__builtin_HEXAG
	break;		ON_A4_cmpbeq"
	return Intrinsic::nvvm_f2ll_rn_ftz; // "__nvvm_f2ll_rn_		case 'g': // 1 string to match.
	ftz"		if (BuiltinName[26] != 't')
	case 'p': // 1 string to match.		break;
	if (memcmp(BuiltinName.data()+14, "_ftz", 4))		return Intrinsic::hexagon_A4_cmpbgt; // "__builtin_HEXAG
	break;		ON_A4_cmpbgt"
	return Intrinsic::nvvm_f2ll_rp_ftz; // "__nvvm_f2ll_rp_		}
	ftz"		break;
	case 'z': // 1 string to match.		case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+14, "_ftz", 4))		switch (BuiltinName[25]) {
	break;		default: break;
	return Intrinsic::nvvm_f2ll_rz_ftz; // "__nvvm_f2ll_rz_		case 'e': // 1 string to match.
	ftz"		if (BuiltinName[26] != 'q')
			break;
			return Intrinsic::hexagon_A4_cmpheq; // "__builtin_HEXAG
			ON_A4_cmpheq"
			case 'g': // 1 string to match.
			if (BuiltinName[26] != 't')
			break;
			return Intrinsic::hexagon_A4_cmphgt; // "__builtin_HEXAG
			ON_A4_cmphgt"
			}
			break;
	}		}
	break;		break;
	case 'u': // 4 strings to match.		case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+10, "i_r", 3))		if (memcmp(BuiltinName.data()+22, "cmpeq", 5))
	break;		break;
	switch (BuiltinName[13]) {		return Intrinsic::hexagon_A4_rcmpeq; // "__builtin_HEXAGON_A4_rc
			mpeq"
			case 'v': // 4 strings to match.
			if (memcmp(BuiltinName.data()+22, "rm", 2))
			break;
			switch (BuiltinName[24]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+14, "_ftz", 4))		if (BuiltinName[25] != 'x')
	break;
	return Intrinsic::nvvm_f2ui_rm_ftz; // "__nvvm_f2ui_rm_
	ftz"
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+14, "_ftz", 4))
	break;
	return Intrinsic::nvvm_f2ui_rn_ftz; // "__nvvm_f2ui_rn_
	ftz"
	case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+14, "_ftz", 4))
	break;		break;
	return Intrinsic::nvvm_f2ui_rp_ftz; // "__nvvm_f2ui_rp_		switch (BuiltinName[26]) {
	ftz"		default: break;
	case 'z': // 1 string to match.		case 'h': // 1 string to match.
	if (memcmp(BuiltinName.data()+14, "_ftz", 4))		return Intrinsic::hexagon_A4_vrmaxh; // "__builtin_HEXAG
			ON_A4_vrmaxh"
			case 'w': // 1 string to match.
			return Intrinsic::hexagon_A4_vrmaxw; // "__builtin_HEXAG
			ON_A4_vrmaxw"
			}
			break;
			case 'i': // 2 strings to match.
			if (BuiltinName[25] != 'n')
	break;		break;
	return Intrinsic::nvvm_f2ui_rz_ftz; // "__nvvm_f2ui_rz_		switch (BuiltinName[26]) {
	ftz"		default: break;
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_A4_vrminh; // "__builtin_HEXAG
			ON_A4_vrminh"
			case 'w': // 1 string to match.
			return Intrinsic::hexagon_A4_vrminw; // "__builtin_HEXAG
			ON_A4_vrminw"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+9, "oor_ftz_f", 9))
	break;
	return Intrinsic::nvvm_floor_ftz_f; // "__nvvm_floor_ftz_f"
	}		}
	break;		break;
	case 'r': // 1 string to match.		case 'C': // 12 strings to match.
	if (memcmp(BuiltinName.data()+8, "ound_ftz_f", 10))		switch (BuiltinName[19]) {
	break;
	return Intrinsic::nvvm_round_ftz_f; // "__nvvm_round_ftz_f"
	case 't': // 1 string to match.
	if (memcmp(BuiltinName.data()+8, "runc_ftz_f", 10))
	break;
	return Intrinsic::nvvm_trunc_ftz_f; // "__nvvm_trunc_ftz_f"
	}
	break;
	case 19: // 34 strings to match.
	if (memcmp(BuiltinName.data()+0, "__", 2))
	break;
	switch (BuiltinName[2]) {
	default: break;
	case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+3, "uiltin_debugtrap", 16))
	break;
	return Intrinsic::debugtrap; // "__builtin_debugtrap"
	case 'n': // 33 strings to match.
	if (memcmp(BuiltinName.data()+3, "vvm_", 4))
	break;
	switch (BuiltinName[7]) {
	default: break;		default: break;
	case 'a': // 4 strings to match.		case '2': // 7 strings to match.
	if (memcmp(BuiltinName.data()+8, "dd_r", 4))		if (memcmp(BuiltinName.data()+20, "_cmp", 4))
	break;		break;
	switch (BuiltinName[12]) {		switch (BuiltinName[24]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'e': // 2 strings to match.
	if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))		if (BuiltinName[25] != 'q')
	break;
	return Intrinsic::nvvm_add_rm_ftz_f; // "__nvvm_add_rm_ftz_f"
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
	break;
	return Intrinsic::nvvm_add_rn_ftz_f; // "__nvvm_add_rn_ftz_f"
	case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
	break;
	return Intrinsic::nvvm_add_rp_ftz_f; // "__nvvm_add_rp_ftz_f"
	case 'z': // 1 string to match.
	if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
	break;		break;
	return Intrinsic::nvvm_add_rz_ftz_f; // "__nvvm_add_rz_ftz_f"		switch (BuiltinName[26]) {
	}		default: break;
	break;		case 'i': // 1 string to match.
	case 'b': // 2 strings to match.		return Intrinsic::hexagon_C2_cmpeqi; // "__builtin_HEXAG
	if (memcmp(BuiltinName.data()+8, "itcast_", 7))		ON_C2_cmpeqi"
			case 'p': // 1 string to match.
			return Intrinsic::hexagon_C2_cmpeqp; // "__builtin_HEXAG
			ON_C2_cmpeqp"
			}
	break;		break;
	switch (BuiltinName[15]) {		case 'g': // 4 strings to match.
	default: break;		switch (BuiltinName[25]) {
	case 'd': // 1 string to match.		default: break;
	if (memcmp(BuiltinName.data()+16, "2ll", 3))		case 'e': // 1 string to match.
			if (BuiltinName[26] != 'i')
			break;
			return Intrinsic::hexagon_C2_cmpgei; // "__builtin_HEXAG
			ON_C2_cmpgei"
			case 't': // 3 strings to match.
			switch (BuiltinName[26]) {
			default: break;
			case 'i': // 1 string to match.
			return Intrinsic::hexagon_C2_cmpgti; // "__builtin_HEXAG
			ON_C2_cmpgti"
			case 'p': // 1 string to match.
			return Intrinsic::hexagon_C2_cmpgtp; // "__builtin_HEXAG
			ON_C2_cmpgtp"
			case 'u': // 1 string to match.
			return Intrinsic::hexagon_C2_cmpgtu; // "__builtin_HEXAG
			ON_C2_cmpgtu"
			}
	break;		break;
	return Intrinsic::nvvm_bitcast_d2ll; // "__nvvm_bitcast_d2ll"		}
			break;
	case 'l': // 1 string to match.		case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "l2d", 3))		if (memcmp(BuiltinName.data()+25, "tu", 2))
	break;		break;
	return Intrinsic::nvvm_bitcast_ll2d; // "__nvvm_bitcast_ll2d"		return Intrinsic::hexagon_C2_cmpltu; // "__builtin_HEXAGON_C2_cm pltu"
	}		}
	break;		break;
	case 'c': // 1 string to match.		case '4': // 5 strings to match.
	if (memcmp(BuiltinName.data()+8, "os_approx_f", 11))		if (BuiltinName[20] != '_')
	break;
	return Intrinsic::nvvm_cos_approx_f; // "__nvvm_cos_approx_f"
	case 'd': // 5 strings to match.
	if (memcmp(BuiltinName.data()+8, "iv_", 3))
	break;		break;
	switch (BuiltinName[11]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+12, "pprox_f", 7))		if (memcmp(BuiltinName.data()+22, "nd_or", 5))
	break;		break;
	return Intrinsic::nvvm_div_approx_f; // "__nvvm_div_approx_f"		return Intrinsic::hexagon_C4_and_or; // "__builtin_HEXAGON_C4_an
	case 'r': // 4 strings to match.		d_or"
	switch (BuiltinName[12]) {		case 'c': // 2 strings to match.
			if (memcmp(BuiltinName.data()+22, "mp", 2))
			break;
			switch (BuiltinName[24]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))		if (memcmp(BuiltinName.data()+25, "te", 2))
	break;		break;
	return Intrinsic::nvvm_div_rm_ftz_f; // "__nvvm_div_rm_f tz_f"		return Intrinsic::hexagon_C4_cmplte; // "__builtin_HEXAG ON_C4_cmplte"
	case 'n': // 1 string to match.		case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))		if (memcmp(BuiltinName.data()+25, "eq", 2))
	break;
	return Intrinsic::nvvm_div_rn_ftz_f; // "__nvvm_div_rn_f
	tz_f"
	case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
	break;
	return Intrinsic::nvvm_div_rp_ftz_f; // "__nvvm_div_rp_f
	tz_f"
	case 'z': // 1 string to match.
	if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
	break;		break;
	return Intrinsic::nvvm_div_rz_ftz_f; // "__nvvm_div_rz_f tz_f"		return Intrinsic::hexagon_C4_cmpneq; // "__builtin_HEXAG ON_C4_cmpneq"
	}		}
	break;		break;
	}		case 'o': // 2 strings to match.
	break;		if (memcmp(BuiltinName.data()+22, "r_", 2))
	case 'e': // 2 strings to match.
	if (memcmp(BuiltinName.data()+8, "x2_approx_", 10))
	break;
	switch (BuiltinName[18]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_ex2_approx_d; // "__nvvm_ex2_approx_d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_ex2_approx_f; // "__nvvm_ex2_approx_f"
	}
	break;
	case 'f': // 8 strings to match.
	switch (BuiltinName[8]) {
	default: break;
	case '2': // 4 strings to match.
	if (memcmp(BuiltinName.data()+9, "ull_r", 5))
	break;		break;
	switch (BuiltinName[14]) {		switch (BuiltinName[24]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+15, "_ftz", 4))		if (memcmp(BuiltinName.data()+25, "nd", 2))
	break;
	return Intrinsic::nvvm_f2ull_rm_ftz; // "__nvvm_f2ull_rm
	_ftz"
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+15, "_ftz", 4))
	break;
	return Intrinsic::nvvm_f2ull_rn_ftz; // "__nvvm_f2ull_rn
	_ftz"
	case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+15, "_ftz", 4))
	break;		break;
	return Intrinsic::nvvm_f2ull_rp_ftz; // "__nvvm_f2ull_rp		return Intrinsic::hexagon_C4_or_and; // "__builtin_HEXAG
	_ftz"		ON_C4_or_and"
	case 'z': // 1 string to match.		case 'o': // 1 string to match.
	if (memcmp(BuiltinName.data()+15, "_ftz", 4))		if (memcmp(BuiltinName.data()+25, "rn", 2))
	break;		break;
	return Intrinsic::nvvm_f2ull_rz_ftz; // "__nvvm_f2ull_rz _ftz"		return Intrinsic::hexagon_C4_or_orn; // "__builtin_HEXAG ON_C4_or_orn"
	}		}
	break;		break;
			}
			break;
			}
			break;
			case 'M': // 12 strings to match.
			switch (BuiltinName[19]) {
			default: break;
			case '2': // 7 strings to match.
			if (BuiltinName[20] != '_')
			break;
			switch (BuiltinName[21]) {
			default: break;
	case 'm': // 4 strings to match.		case 'm': // 4 strings to match.
	if (memcmp(BuiltinName.data()+9, "a_r", 3))		switch (BuiltinName[22]) {
	break;
	switch (BuiltinName[12]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))		if (memcmp(BuiltinName.data()+23, "csi", 3))
	break;
	return Intrinsic::nvvm_fma_rm_ftz_f; // "__nvvm_fma_rm_f
	tz_f"
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
	break;
	return Intrinsic::nvvm_fma_rn_ftz_f; // "__nvvm_fma_rn_f
	tz_f"
	case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
	break;		break;
	return Intrinsic::nvvm_fma_rp_ftz_f; // "__nvvm_fma_rp_f		switch (BuiltinName[26]) {
	tz_f"		default: break;
	case 'z': // 1 string to match.		case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))		return Intrinsic::hexagon_M2_macsin; // "__builtin_HEXAG
			ON_M2_macsin"
			case 'p': // 1 string to match.
			return Intrinsic::hexagon_M2_macsip; // "__builtin_HEXAG
			ON_M2_macsip"
			}
			break;
			case 'p': // 2 strings to match.
			if (BuiltinName[23] != 'y')
	break;		break;
	return Intrinsic::nvvm_fma_rz_ftz_f; // "__nvvm_fma_rz_f		switch (BuiltinName[24]) {
	tz_f"		default: break;
			case '_': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "up", 2))
			break;
			return Intrinsic::hexagon_M2_mpy_up; // "__builtin_HEXAG
			ON_M2_mpy_up"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "mi", 2))
			break;
			return Intrinsic::hexagon_M2_mpysmi; // "__builtin_HEXAG
			ON_M2_mpysmi"
			}
			break;
	}		}
	break;		break;
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "accii", 5))
			break;
			return Intrinsic::hexagon_M2_naccii; // "__builtin_HEXAGON_M2_na
			ccii"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "ubacc", 5))
			break;
			return Intrinsic::hexagon_M2_subacc; // "__builtin_HEXAGON_M2_su
			bacc"
			case 'v': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "raddh", 5))
			break;
			return Intrinsic::hexagon_M2_vraddh; // "__builtin_HEXAGON_M2_vr
			addh"
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case '4': // 5 strings to match.
	if (memcmp(BuiltinName.data()+8, "g2_approx_", 10))		if (BuiltinName[20] != '_')
	break;
	switch (BuiltinName[18]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_lg2_approx_d; // "__nvvm_lg2_approx_d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_lg2_approx_f; // "__nvvm_lg2_approx_f"
	}
	break;
	case 'm': // 4 strings to match.
	if (memcmp(BuiltinName.data()+8, "ul_r", 4))
	break;		break;
	switch (BuiltinName[12]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))		if (memcmp(BuiltinName.data()+22, "nd_or", 5))
	break;		break;
	return Intrinsic::nvvm_mul_rm_ftz_f; // "__nvvm_mul_rm_ftz_f"		return Intrinsic::hexagon_M4_and_or; // "__builtin_HEXAGON_M4_an
	case 'n': // 1 string to match.		d_or"
	if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))		case 'o': // 2 strings to match.
			if (memcmp(BuiltinName.data()+22, "r_", 2))
	break;		break;
	return Intrinsic::nvvm_mul_rn_ftz_f; // "__nvvm_mul_rn_ftz_f"		switch (BuiltinName[24]) {
	case 'p': // 1 string to match.		default: break;
	if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))		case 'a': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "nd", 2))
			break;
			return Intrinsic::hexagon_M4_or_and; // "__builtin_HEXAG
			ON_M4_or_and"
			case 'x': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "or", 2))
			break;
			return Intrinsic::hexagon_M4_or_xor; // "__builtin_HEXAG
			ON_M4_or_xor"
			}
			break;
			case 'v': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "pmpyh", 5))
	break;		break;
	return Intrinsic::nvvm_mul_rp_ftz_f; // "__nvvm_mul_rp_ftz_f"		return Intrinsic::hexagon_M4_vpmpyh; // "__builtin_HEXAGON_M4_vp
	case 'z': // 1 string to match.		mpyh"
	if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))		case 'x': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "or_or", 5))
	break;		break;
	return Intrinsic::nvvm_mul_rz_ftz_f; // "__nvvm_mul_rz_ftz_f"		return Intrinsic::hexagon_M4_xor_or; // "__builtin_HEXAGON_M4_xo r_or"
	}		}
	break;		break;
	case 'r': // 4 strings to match.		}
	if (memcmp(BuiltinName.data()+8, "cp_r", 4))		break;
			case 'S': // 11 strings to match.
			switch (BuiltinName[19]) {
			default: break;
			case '2': // 9 strings to match.
			if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[12]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))		if (memcmp(BuiltinName.data()+22, "nsert", 5))
	break;
	return Intrinsic::nvvm_rcp_rm_ftz_f; // "__nvvm_rcp_rm_ftz_f"
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))
	break;		break;
	return Intrinsic::nvvm_rcp_rn_ftz_f; // "__nvvm_rcp_rn_ftz_f"		return Intrinsic::hexagon_S2_insert; // "__builtin_HEXAGON_S2_in sert"
	case 'p': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))		if (memcmp(BuiltinName.data()+22, "ackhl", 5))
	break;		break;
	return Intrinsic::nvvm_rcp_rp_ftz_f; // "__nvvm_rcp_rp_ftz_f"		return Intrinsic::hexagon_S2_packhl; // "__builtin_HEXAGON_S2_pa
	case 'z': // 1 string to match.		ckhl"
	if (memcmp(BuiltinName.data()+13, "_ftz_f", 6))		case 'v': // 7 strings to match.
			switch (BuiltinName[22]) {
			default: break;
			case 'c': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "negh", 4))
			break;
			return Intrinsic::hexagon_S2_vcnegh; // "__builtin_HEXAG
			ON_S2_vcnegh"
			case 's': // 4 strings to match.
			switch (BuiltinName[23]) {
			default: break;
			case 'a': // 2 strings to match.
			if (BuiltinName[24] != 't')
			break;
			switch (BuiltinName[25]) {
			default: break;
			case 'h': // 1 string to match.
			if (BuiltinName[26] != 'b')
			break;
			return Intrinsic::hexagon_S2_vsathb; // "__builtin_HEXAG
			ON_S2_vsathb"
			case 'w': // 1 string to match.
			if (BuiltinName[26] != 'h')
			break;
			return Intrinsic::hexagon_S2_vsatwh; // "__builtin_HEXAG
			ON_S2_vsatwh"
			}
			break;
			case 'x': // 2 strings to match.
			if (BuiltinName[24] != 't')
			break;
			switch (BuiltinName[25]) {
			default: break;
			case 'b': // 1 string to match.
			if (BuiltinName[26] != 'h')
			break;
			return Intrinsic::hexagon_S2_vsxtbh; // "__builtin_HEXAG
			ON_S2_vsxtbh"
			case 'h': // 1 string to match.
			if (BuiltinName[26] != 'w')
			break;
			return Intrinsic::hexagon_S2_vsxthw; // "__builtin_HEXAG
			ON_S2_vsxthw"
			}
			break;
			}
			break;
			case 'z': // 2 strings to match.
			if (memcmp(BuiltinName.data()+23, "xt", 2))
			break;
			switch (BuiltinName[25]) {
			default: break;
			case 'b': // 1 string to match.
			if (BuiltinName[26] != 'h')
			break;
			return Intrinsic::hexagon_S2_vzxtbh; // "__builtin_HEXAG
			ON_S2_vzxtbh"
			case 'h': // 1 string to match.
			if (BuiltinName[26] != 'w')
			break;
			return Intrinsic::hexagon_S2_vzxthw; // "__builtin_HEXAG
			ON_S2_vzxthw"
			}
	break;		break;
	return Intrinsic::nvvm_rcp_rz_ftz_f; // "__nvvm_rcp_rz_ftz_f"		}
	}
	break;
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+8, "in_approx_f", 11))
	break;
	return Intrinsic::nvvm_sin_approx_f; // "__nvvm_sin_approx_f"
	}
	break;
	}
	break;
	case 20: // 7 strings to match.
	if (memcmp(BuiltinName.data()+0, "__", 2))
	break;
	switch (BuiltinName[2]) {
	default: break;
	case 'b': // 2 strings to match.
	if (memcmp(BuiltinName.data()+3, "uiltin_", 7))
	break;
	switch (BuiltinName[10]) {
	default: break;
	case 'f': // 1 string to match.
	if (memcmp(BuiltinName.data()+11, "lt_rounds", 9))
	break;
	return Intrinsic::flt_rounds; // "__builtin_flt_rounds"
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+11, "tack_save", 9))
	break;		break;
	return Intrinsic::stacksave; // "__builtin_stack_save"		}
	}
	break;
	case 'n': // 5 strings to match.
	if (memcmp(BuiltinName.data()+3, "vvm_sqrt_", 9))
	break;		break;
	switch (BuiltinName[12]) {		case '4': // 2 strings to match.
	default: break;		if (BuiltinName[20] != '_')
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+13, "pprox_f", 7))
	break;		break;
	return Intrinsic::nvvm_sqrt_approx_f; // "__nvvm_sqrt_approx_f"		switch (BuiltinName[21]) {
	case 'r': // 4 strings to match.
	switch (BuiltinName[13]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'o': // 1 string to match.
	if (memcmp(BuiltinName.data()+14, "_ftz_f", 6))		if (memcmp(BuiltinName.data()+22, "r_ori", 5))
	break;
	return Intrinsic::nvvm_sqrt_rm_ftz_f; // "__nvvm_sqrt_rm_
	ftz_f"
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+14, "_ftz_f", 6))
	break;		break;
	return Intrinsic::nvvm_sqrt_rn_ftz_f; // "__nvvm_sqrt_rn_ ftz_f"		return Intrinsic::hexagon_S4_or_ori; // "__builtin_HEXAGON_S4_or _ori"
	case 'p': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+14, "_ftz_f", 6))		if (memcmp(BuiltinName.data()+22, "arity", 5))
	break;
	return Intrinsic::nvvm_sqrt_rp_ftz_f; // "__nvvm_sqrt_rp_
	ftz_f"
	case 'z': // 1 string to match.
	if (memcmp(BuiltinName.data()+14, "_ftz_f", 6))
	break;		break;
	return Intrinsic::nvvm_sqrt_rz_ftz_f; // "__nvvm_sqrt_rz_ ftz_f"		return Intrinsic::hexagon_S4_parity; // "__builtin_HEXAGON_S4_pa rity"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 21: // 23 strings to match.		case 28: // 103 strings to match.
	if (memcmp(BuiltinName.data()+0, "__", 2))		if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
	break;		break;
	switch (BuiltinName[2]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'b': // 20 strings to match.		case 'A': // 36 strings to match.
	if (memcmp(BuiltinName.data()+3, "uiltin_", 7))		switch (BuiltinName[19]) {
	break;
	switch (BuiltinName[10]) {
	default: break;		default: break;
	case 'i': // 18 strings to match.		case '2': // 23 strings to match.
	if (memcmp(BuiltinName.data()+11, "a32_vp", 6))		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[17]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'c': // 5 strings to match.		case 'a': // 1 string to match.
	switch (BuiltinName[18]) {		if (memcmp(BuiltinName.data()+22, "ddpsat", 6))
			break;
			return Intrinsic::hexagon_A2_addpsat; // "__builtin_HEXAG
			ON_A2_addpsat"
			case 's': // 4 strings to match.
			if (BuiltinName[22] != 'v')
			break;
			switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'm': // 1 string to match.		case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+19, "ov", 2))		switch (BuiltinName[24]) {
	break;
	return Intrinsic::x86_xop_vpcmov; // "__builtin_ia32_vpcmov"
	case 'o': // 4 strings to match.
	if (BuiltinName[19] != 'm')
	break;
	switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'b': // 1 string to match.
	return Intrinsic::x86_xop_vpcomb; // "__builtin_ia32_
	vpcomb"
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::x86_xop_vpcomd; // "__builtin_ia32_		if (memcmp(BuiltinName.data()+25, "dhs", 3))
	vpcomd"		break;
	case 'q': // 1 string to match.		return Intrinsic::hexagon_A2_svaddhs; // "__builtin_HEXAG
	return Intrinsic::x86_xop_vpcomq; // "__builtin_ia32_		ON_A2_svaddhs"
	vpcomq"		case 'v': // 1 string to match.
	case 'w': // 1 string to match.		if (memcmp(BuiltinName.data()+25, "ghs", 3))
	return Intrinsic::x86_xop_vpcomw; // "__builtin_ia32_		break;
	vpcomw"		return Intrinsic::hexagon_A2_svavghs; // "__builtin_HEXAG
			ON_A2_svavghs"
	}		}
	break;		break;
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "avgh", 4))
			break;
			return Intrinsic::hexagon_A2_svnavgh; // "__builtin_HEXAG
			ON_A2_svnavgh"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "ubhs", 4))
			break;
			return Intrinsic::hexagon_A2_svsubhs; // "__builtin_HEXAG
			ON_A2_svsubhs"
	}		}
	break;		break;
	case 'p': // 1 string to match.		case 'v': // 18 strings to match.
	if (memcmp(BuiltinName.data()+18, "erm", 3))		switch (BuiltinName[22]) {
	break;
	return Intrinsic::x86_xop_vpperm; // "__builtin_ia32_vpperm"
	case 'r': // 4 strings to match.
	if (memcmp(BuiltinName.data()+18, "ot", 2))
	break;
	switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'a': // 7 strings to match.
	return Intrinsic::x86_xop_vprotb; // "__builtin_ia32_vprotb"		switch (BuiltinName[23]) {
	case 'd': // 1 string to match.		default: break;
	return Intrinsic::x86_xop_vprotd; // "__builtin_ia32_vprotd"		case 'd': // 2 strings to match.
	case 'q': // 1 string to match.		if (memcmp(BuiltinName.data()+24, "du", 2))
	return Intrinsic::x86_xop_vprotq; // "__builtin_ia32_vprotq"		break;
	case 'w': // 1 string to match.		switch (BuiltinName[26]) {
	return Intrinsic::x86_xop_vprotw; // "__builtin_ia32_vprotw"		default: break;
	}		case 'b': // 1 string to match.
	break;		if (BuiltinName[27] != 's')
	case 's': // 8 strings to match.		break;
	if (BuiltinName[18] != 'h')		return Intrinsic::hexagon_A2_vaddubs; // "__builtin_HEXAG
			ON_A2_vaddubs"
			case 'h': // 1 string to match.
			if (BuiltinName[27] != 's')
			break;
			return Intrinsic::hexagon_A2_vadduhs; // "__builtin_HEXAG
			ON_A2_vadduhs"
			}
			break;
			case 'v': // 5 strings to match.
			if (BuiltinName[24] != 'g')
			break;
			switch (BuiltinName[25]) {
			default: break;
			case 'h': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "cr", 2))
			break;
			return Intrinsic::hexagon_A2_vavghcr; // "__builtin_HEXAG
			ON_A2_vavghcr"
			case 'u': // 3 strings to match.
			switch (BuiltinName[26]) {
			default: break;
			case 'b': // 1 string to match.
			if (BuiltinName[27] != 'r')
			break;
			return Intrinsic::hexagon_A2_vavgubr; // "__built
			in_HEXAGON_A2_vavgubr"
			case 'h': // 1 string to match.
			if (BuiltinName[27] != 'r')
			break;
			return Intrinsic::hexagon_A2_vavguhr; // "__built
			in_HEXAGON_A2_vavguhr"
			case 'w': // 1 string to match.
			if (BuiltinName[27] != 'r')
			break;
			return Intrinsic::hexagon_A2_vavguwr; // "__built
			in_HEXAGON_A2_vavguwr"
			}
			break;
			case 'w': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "cr", 2))
			break;
			return Intrinsic::hexagon_A2_vavgwcr; // "__builtin_HEXAG
			ON_A2_vavgwcr"
			}
			break;
			}
	break;		break;
	switch (BuiltinName[19]) {		case 'c': // 5 strings to match.
	default: break;		if (memcmp(BuiltinName.data()+23, "mp", 2))
	case 'a': // 4 strings to match.		break;
	switch (BuiltinName[20]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::x86_xop_vpshab; // "__builtin_ia32_		if (memcmp(BuiltinName.data()+26, "eq", 2))
	vpshab"		break;
	case 'd': // 1 string to match.		return Intrinsic::hexagon_A2_vcmpbeq; // "__builtin_HEXAG
	return Intrinsic::x86_xop_vpshad; // "__builtin_ia32_		ON_A2_vcmpbeq"
	vpshad"		case 'h': // 2 strings to match.
	case 'q': // 1 string to match.		switch (BuiltinName[26]) {
	return Intrinsic::x86_xop_vpshaq; // "__builtin_ia32_		default: break;
	vpshaq"		case 'e': // 1 string to match.
			if (BuiltinName[27] != 'q')
			break;
			return Intrinsic::hexagon_A2_vcmpheq; // "__builtin_HEXAG
			ON_A2_vcmpheq"
			case 'g': // 1 string to match.
			if (BuiltinName[27] != 't')
			break;
			return Intrinsic::hexagon_A2_vcmphgt; // "__builtin_HEXAG
			ON_A2_vcmphgt"
			}
			break;
			case 'w': // 2 strings to match.
			switch (BuiltinName[26]) {
			default: break;
			case 'e': // 1 string to match.
			if (BuiltinName[27] != 'q')
			break;
			return Intrinsic::hexagon_A2_vcmpweq; // "__builtin_HEXAG
			ON_A2_vcmpweq"
			case 'g': // 1 string to match.
			if (BuiltinName[27] != 't')
			break;
			return Intrinsic::hexagon_A2_vcmpwgt; // "__builtin_HEXAG
			ON_A2_vcmpwgt"
			}
			break;
			}
			break;
			case 'n': // 2 strings to match.
			if (memcmp(BuiltinName.data()+23, "avg", 3))
			break;
			switch (BuiltinName[26]) {
			default: break;
			case 'h': // 1 string to match.
			if (BuiltinName[27] != 'r')
			break;
			return Intrinsic::hexagon_A2_vnavghr; // "__builtin_HEXAG
			ON_A2_vnavghr"
	case 'w': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::x86_xop_vpshaw; // "__builtin_ia32_		if (BuiltinName[27] != 'r')
	vpshaw"		break;
			return Intrinsic::hexagon_A2_vnavgwr; // "__builtin_HEXAG
			ON_A2_vnavgwr"
	}		}
	break;		break;
	case 'l': // 4 strings to match.		case 'r': // 2 strings to match.
	switch (BuiltinName[20]) {		switch (BuiltinName[23]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "ddub", 4))
			break;
			return Intrinsic::hexagon_A2_vraddub; // "__builtin_HEXAG
			ON_A2_vraddub"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "adub", 4))
			break;
			return Intrinsic::hexagon_A2_vrsadub; // "__builtin_HEXAG
			ON_A2_vrsadub"
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(BuiltinName.data()+23, "ubu", 3))
			break;
			switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::x86_xop_vpshlb; // "__builtin_ia32_		if (BuiltinName[27] != 's')
	vpshlb"		break;
	case 'd': // 1 string to match.		return Intrinsic::hexagon_A2_vsububs; // "__builtin_HEXAG
	return Intrinsic::x86_xop_vpshld; // "__builtin_ia32_		ON_A2_vsububs"
	vpshld"		case 'h': // 1 string to match.
	case 'q': // 1 string to match.		if (BuiltinName[27] != 's')
	return Intrinsic::x86_xop_vpshlq; // "__builtin_ia32_		break;
	vpshlq"		return Intrinsic::hexagon_A2_vsubuhs; // "__builtin_HEXAG
	case 'w': // 1 string to match.		ON_A2_vsubuhs"
	return Intrinsic::x86_xop_vpshlw; // "__builtin_ia32_
	vpshlw"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'o': // 1 string to match.		case '4': // 13 strings to match.
	if (memcmp(BuiltinName.data()+11, "bject_size", 10))		if (BuiltinName[20] != '_')
	break;		break;
	return Intrinsic::objectsize; // "__builtin_object_size"		switch (BuiltinName[21]) {
	case 'u': // 1 string to match.		default: break;
	if (memcmp(BuiltinName.data()+11, "nwind_init", 10))		case 'c': // 6 strings to match.
			if (memcmp(BuiltinName.data()+22, "mp", 2))
			break;
			switch (BuiltinName[24]) {
			default: break;
			case 'b': // 3 strings to match.
			switch (BuiltinName[25]) {
			default: break;
			case 'e': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "qi", 2))
			break;
			return Intrinsic::hexagon_A4_cmpbeqi; // "__builtin_HEXAG
			ON_A4_cmpbeqi"
			case 'g': // 2 strings to match.
			if (BuiltinName[26] != 't')
			break;
			switch (BuiltinName[27]) {
			default: break;
			case 'i': // 1 string to match.
			return Intrinsic::hexagon_A4_cmpbgti; // "__builtin_HEXAG
			ON_A4_cmpbgti"
			case 'u': // 1 string to match.
			return Intrinsic::hexagon_A4_cmpbgtu; // "__builtin_HEXAG
			ON_A4_cmpbgtu"
			}
			break;
			}
			break;
			case 'h': // 3 strings to match.
			switch (BuiltinName[25]) {
			default: break;
			case 'e': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "qi", 2))
			break;
			return Intrinsic::hexagon_A4_cmpheqi; // "__builtin_HEXAG
			ON_A4_cmpheqi"
			case 'g': // 2 strings to match.
			if (BuiltinName[26] != 't')
			break;
			switch (BuiltinName[27]) {
			default: break;
			case 'i': // 1 string to match.
			return Intrinsic::hexagon_A4_cmphgti; // "__builtin_HEXAG
			ON_A4_cmphgti"
			case 'u': // 1 string to match.
			return Intrinsic::hexagon_A4_cmphgtu; // "__builtin_HEXAG
			ON_A4_cmphgtu"
			}
			break;
			}
			break;
			}
	break;		break;
	return Intrinsic::eh_unwind_init; // "__builtin_unwind_init"		case 'r': // 2 strings to match.
	}		if (memcmp(BuiltinName.data()+22, "cmp", 3))
	break;		break;
	case 'n': // 3 strings to match.		switch (BuiltinName[25]) {
	if (memcmp(BuiltinName.data()+3, "vvm_", 4))		default: break;
	break;		case 'e': // 1 string to match.
	switch (BuiltinName[7]) {		if (memcmp(BuiltinName.data()+26, "qi", 2))
	default: break;		break;
	case 'r': // 2 strings to match.		return Intrinsic::hexagon_A4_rcmpeqi; // "__builtin_HEXAG
	if (memcmp(BuiltinName.data()+8, "sqrt_approx_", 12))		ON_A4_rcmpeqi"
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "eq", 2))
			break;
			return Intrinsic::hexagon_A4_rcmpneq; // "__builtin_HEXAG
			ON_A4_rcmpneq"
			}
			break;
			case 'v': // 5 strings to match.
			switch (BuiltinName[22]) {
			default: break;
			case 'c': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "mpbgt", 5))
			break;
			return Intrinsic::hexagon_A4_vcmpbgt; // "__builtin_HEXAG
			ON_A4_vcmpbgt"
			case 'r': // 4 strings to match.
			if (BuiltinName[23] != 'm')
			break;
			switch (BuiltinName[24]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(BuiltinName.data()+25, "xu", 2))
			break;
			switch (BuiltinName[27]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_A4_vrmaxuh; // "__builtin_HEXAG
			ON_A4_vrmaxuh"
			case 'w': // 1 string to match.
			return Intrinsic::hexagon_A4_vrmaxuw; // "__builtin_HEXAG
			ON_A4_vrmaxuw"
			}
			break;
			case 'i': // 2 strings to match.
			if (memcmp(BuiltinName.data()+25, "nu", 2))
			break;
			switch (BuiltinName[27]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_A4_vrminuh; // "__builtin_HEXAG
			ON_A4_vrminuh"
			case 'w': // 1 string to match.
			return Intrinsic::hexagon_A4_vrminuw; // "__builtin_HEXAG
			ON_A4_vrminuw"
			}
			break;
			}
			break;
			}
	break;		break;
	switch (BuiltinName[20]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::nvvm_rsqrt_approx_d; // "__nvvm_rsqrt_ap
	prox_d"
	case 'f': // 1 string to match.
	return Intrinsic::nvvm_rsqrt_approx_f; // "__nvvm_rsqrt_ap
	prox_f"
	}		}
	break;		break;
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+8, "aturate_ftz_f", 13))
	break;
	return Intrinsic::nvvm_saturate_ftz_f; // "__nvvm_saturate_ftz_f"
	}		}
	break;		break;
	}		case 'C': // 12 strings to match.
	break;		switch (BuiltinName[19]) {
	case 22: // 17 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_", 10))
	break;
	switch (BuiltinName[10]) {
	default: break;
	case 'i': // 12 strings to match.
	if (memcmp(BuiltinName.data()+11, "a32_v", 5))
	break;
	switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'f': // 4 strings to match.		case '2': // 6 strings to match.
	if (memcmp(BuiltinName.data()+17, "rcz", 3))		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[20]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'p': // 2 strings to match.		case 'b': // 2 strings to match.
	switch (BuiltinName[21]) {		if (memcmp(BuiltinName.data()+22, "its", 3))
			break;
			switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'c': // 1 string to match.
	return Intrinsic::x86_xop_vfrcz_pd; // "__builtin_ia32_		if (memcmp(BuiltinName.data()+26, "lr", 2))
	vfrczpd"		break;
			return Intrinsic::hexagon_C2_bitsclr; // "__builtin_HEXAG
			ON_C2_bitsclr"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	return Intrinsic::x86_xop_vfrcz_ps; // "__builtin_ia32_		if (memcmp(BuiltinName.data()+26, "et", 2))
	vfrczps"		break;
			return Intrinsic::hexagon_C2_bitsset; // "__builtin_HEXAG
			ON_C2_bitsset"
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 'c': // 3 strings to match.
	switch (BuiltinName[21]) {		if (memcmp(BuiltinName.data()+22, "mpg", 3))
			break;
			switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'e': // 1 string to match.
	return Intrinsic::x86_xop_vfrcz_sd; // "__builtin_ia32_		if (memcmp(BuiltinName.data()+26, "ui", 2))
	vfrczsd"		break;
	case 's': // 1 string to match.		return Intrinsic::hexagon_C2_cmpgeui; // "__builtin_HEXAG
	return Intrinsic::x86_xop_vfrcz_ss; // "__builtin_ia32_		ON_C2_cmpgeui"
	vfrczss"		case 't': // 2 strings to match.
			if (BuiltinName[26] != 'u')
			break;
			switch (BuiltinName[27]) {
			default: break;
			case 'i': // 1 string to match.
			return Intrinsic::hexagon_C2_cmpgtui; // "__builtin_HEXAG
			ON_C2_cmpgtui"
			case 'p': // 1 string to match.
			return Intrinsic::hexagon_C2_cmpgtup; // "__builtin_HEXAG
			ON_C2_cmpgtup"
			}
			break;
	}		}
	break;		break;
			case 'v': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "itpack", 6))
			break;
			return Intrinsic::hexagon_C2_vitpack; // "__builtin_HEXAG
			ON_C2_vitpack"
	}		}
	break;		break;
	case 'p': // 8 strings to match.		case '4': // 6 strings to match.
	switch (BuiltinName[17]) {		if (BuiltinName[20] != '_')
	default: break;
	case 'c': // 4 strings to match.
	if (memcmp(BuiltinName.data()+18, "omu", 3))
	break;
	switch (BuiltinName[21]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::x86_xop_vpcomub; // "__builtin_ia32_vpcomub"
	case 'd': // 1 string to match.
	return Intrinsic::x86_xop_vpcomud; // "__builtin_ia32_vpcomud"
	case 'q': // 1 string to match.
	return Intrinsic::x86_xop_vpcomuq; // "__builtin_ia32_vpcomuq"
	case 'w': // 1 string to match.
	return Intrinsic::x86_xop_vpcomuw; // "__builtin_ia32_vpcomuw"
	}
	break;		break;
	case 'r': // 4 strings to match.		switch (BuiltinName[21]) {
	if (memcmp(BuiltinName.data()+18, "ot", 2))		default: break;
			case 'a': // 2 strings to match.
			if (memcmp(BuiltinName.data()+22, "nd_", 3))
	break;		break;
	switch (BuiltinName[20]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'a': // 1 string to match.
	if (BuiltinName[21] != 'i')		if (memcmp(BuiltinName.data()+26, "nd", 2))
	break;		break;
	return Intrinsic::x86_xop_vprotbi; // "__builtin_ia32_vprotbi"		return Intrinsic::hexagon_C4_and_and; // "__builtin_HEXAG
	case 'd': // 1 string to match.		ON_C4_and_and"
	if (BuiltinName[21] != 'i')		case 'o': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "rn", 2))
	break;		break;
	return Intrinsic::x86_xop_vprotdi; // "__builtin_ia32_vprotdi"		return Intrinsic::hexagon_C4_and_orn; // "__builtin_HEXAG
	case 'q': // 1 string to match.		ON_C4_and_orn"
	if (BuiltinName[21] != 'i')		}
			break;
			case 'c': // 3 strings to match.
			if (memcmp(BuiltinName.data()+22, "mp", 2))
			break;
			switch (BuiltinName[24]) {
			default: break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+25, "te", 2))
	break;		break;
	return Intrinsic::x86_xop_vprotqi; // "__builtin_ia32_vprotqi"		switch (BuiltinName[27]) {
	case 'w': // 1 string to match.		default: break;
	if (BuiltinName[21] != 'i')		case 'i': // 1 string to match.
			return Intrinsic::hexagon_C4_cmpltei; // "__builtin_HEXAG
			ON_C4_cmpltei"
			case 'u': // 1 string to match.
			return Intrinsic::hexagon_C4_cmplteu; // "__builtin_HEXAG
			ON_C4_cmplteu"
			}
			break;
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "eqi", 3))
	break;		break;
	return Intrinsic::x86_xop_vprotwi; // "__builtin_ia32_vprotwi"		return Intrinsic::hexagon_C4_cmpneqi; // "__builtin_HEXAG ON_C4_cmpneqi"
	}		}
	break;		break;
			case 'o': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "r_andn", 6))
			break;
			return Intrinsic::hexagon_C4_or_andn; // "__builtin_HEXAG
			ON_C4_or_andn"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'p': // 5 strings to match.		case 'F': // 14 strings to match.
	if (memcmp(BuiltinName.data()+11, "tx_", 3))		if (memcmp(BuiltinName.data()+19, "2_", 2))
	break;
	switch (BuiltinName[14]) {
	default: break;
	case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+15, "ar_sync", 7))
	break;
	return Intrinsic::ptx_bar_sync; // "__builtin_ptx_bar_sync"
	case 'r': // 4 strings to match.
	if (memcmp(BuiltinName.data()+15, "ead_pm", 6))
	break;
	switch (BuiltinName[21]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::ptx_read_pm0; // "__builtin_ptx_read_pm0"
	case '1': // 1 string to match.
	return Intrinsic::ptx_read_pm1; // "__builtin_ptx_read_pm1"
	case '2': // 1 string to match.
	return Intrinsic::ptx_read_pm2; // "__builtin_ptx_read_pm2"
	case '3': // 1 string to match.
	return Intrinsic::ptx_read_pm3; // "__builtin_ptx_read_pm3"
	}
	break;
	}
	break;
	}
	break;
	case 23: // 20 strings to match.
	if (memcmp(BuiltinName.data()+0, "__", 2))
	break;
	switch (BuiltinName[2]) {
	default: break;
	case 'b': // 14 strings to match.
	if (memcmp(BuiltinName.data()+3, "uiltin_", 7))
	break;		break;
	switch (BuiltinName[10]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'i': // 12 strings to match.		case 'd': // 7 strings to match.
	if (memcmp(BuiltinName.data()+11, "a32_vp", 6))		if (BuiltinName[22] != 'f')
	break;		break;
	switch (BuiltinName[17]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'h': // 9 strings to match.		case 'c': // 5 strings to match.
	switch (BuiltinName[18]) {		switch (BuiltinName[24]) {
	default: break;		default: break;
	case 'a': // 6 strings to match.		case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+19, "dd", 2))		if (memcmp(BuiltinName.data()+25, "ass", 3))
	break;		break;
	switch (BuiltinName[21]) {		return Intrinsic::hexagon_F2_dfclass; // "__builtin_HEXAG
	default: break;		ON_F2_dfclass"
	case 'b': // 3 strings to match.		case 'm': // 4 strings to match.
	switch (BuiltinName[22]) {		if (BuiltinName[25] != 'p')
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_xop_vphaddbd; // "__builtin_ia32_
	vphaddbd"
	case 'q': // 1 string to match.
	return Intrinsic::x86_xop_vphaddbq; // "__builtin_ia32_
	vphaddbq"
	case 'w': // 1 string to match.
	return Intrinsic::x86_xop_vphaddbw; // "__builtin_ia32_
	vphaddbw"
	}
	break;		break;
	case 'd': // 1 string to match.		switch (BuiltinName[26]) {
	if (BuiltinName[22] != 'q')		default: break;
			case 'e': // 1 string to match.
			if (BuiltinName[27] != 'q')
	break;		break;
	return Intrinsic::x86_xop_vphadddq; // "__builtin_ia32_		return Intrinsic::hexagon_F2_dfcmpeq; // "__builtin_HEXAG
	vphadddq"		ON_F2_dfcmpeq"
	case 'w': // 2 strings to match.		case 'g': // 2 strings to match.
	switch (BuiltinName[22]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'e': // 1 string to match.
	return Intrinsic::x86_xop_vphaddwd; // "__builtin_ia32_		return Intrinsic::hexagon_F2_dfcmpge; // "__builtin_HEXAG
	vphaddwd"		ON_F2_dfcmpge"
	case 'q': // 1 string to match.		case 't': // 1 string to match.
	return Intrinsic::x86_xop_vphaddwq; // "__builtin_ia32_		return Intrinsic::hexagon_F2_dfcmpgt; // "__builtin_HEXAG
	vphaddwq"		ON_F2_dfcmpgt"
	}		}
	break;		break;
			case 'u': // 1 string to match.
			if (BuiltinName[27] != 'o')
			break;
			return Intrinsic::hexagon_F2_dfcmpuo; // "__builtin_HEXAG
			ON_F2_dfcmpuo"
	}		}
	break;		break;
	case 's': // 3 strings to match.		}
	if (memcmp(BuiltinName.data()+19, "ub", 2))		break;
			case 'i': // 2 strings to match.
			if (memcmp(BuiltinName.data()+24, "mm_", 3))
			break;
			switch (BuiltinName[27]) {
			default: break;
			case 'n': // 1 string to match.
			return Intrinsic::hexagon_F2_dfimm_n; // "__builtin_HEXAG
			ON_F2_dfimm_n"
			case 'p': // 1 string to match.
			return Intrinsic::hexagon_F2_dfimm_p; // "__builtin_HEXAG
			ON_F2_dfimm_p"
			}
			break;
			}
			break;
			case 's': // 7 strings to match.
			if (BuiltinName[22] != 'f')
			break;
			switch (BuiltinName[23]) {
			default: break;
			case 'c': // 5 strings to match.
			switch (BuiltinName[24]) {
			default: break;
			case 'l': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "ass", 3))
	break;		break;
	switch (BuiltinName[21]) {		return Intrinsic::hexagon_F2_sfclass; // "__builtin_HEXAG
			ON_F2_sfclass"
			case 'm': // 4 strings to match.
			if (BuiltinName[25] != 'p')
			break;
			switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'e': // 1 string to match.
	if (BuiltinName[22] != 'w')		if (BuiltinName[27] != 'q')
	break;
	return Intrinsic::x86_xop_vphsubbw; // "__builtin_ia32_
	vphsubbw"
	case 'd': // 1 string to match.
	if (BuiltinName[22] != 'q')
	break;		break;
	return Intrinsic::x86_xop_vphsubdq; // "__builtin_ia32_		return Intrinsic::hexagon_F2_sfcmpeq; // "__builtin_HEXAG
	vphsubdq"		ON_F2_sfcmpeq"
	case 'w': // 1 string to match.		case 'g': // 2 strings to match.
	if (BuiltinName[22] != 'd')		switch (BuiltinName[27]) {
			default: break;
			case 'e': // 1 string to match.
			return Intrinsic::hexagon_F2_sfcmpge; // "__builtin_HEXAG
			ON_F2_sfcmpge"
			case 't': // 1 string to match.
			return Intrinsic::hexagon_F2_sfcmpgt; // "__builtin_HEXAG
			ON_F2_sfcmpgt"
			}
			break;
			case 'u': // 1 string to match.
			if (BuiltinName[27] != 'o')
	break;		break;
	return Intrinsic::x86_xop_vphsubwd; // "__builtin_ia32_ vphsubwd"		return Intrinsic::hexagon_F2_sfcmpuo; // "__builtin_HEXAG ON_F2_sfcmpuo"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'm': // 3 strings to match.		case 'i': // 2 strings to match.
	if (memcmp(BuiltinName.data()+18, "acs", 3))		if (memcmp(BuiltinName.data()+24, "mm_", 3))
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'n': // 1 string to match.
	if (BuiltinName[22] != 'd')		return Intrinsic::hexagon_F2_sfimm_n; // "__builtin_HEXAG
	break;		ON_F2_sfimm_n"
	return Intrinsic::x86_xop_vpmacsdd; // "__builtin_ia32_		case 'p': // 1 string to match.
	vpmacsdd"		return Intrinsic::hexagon_F2_sfimm_p; // "__builtin_HEXAG
	case 'w': // 2 strings to match.		ON_F2_sfimm_p"
	switch (BuiltinName[22]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_xop_vpmacswd; // "__builtin_ia32_
	vpmacswd"
	case 'w': // 1 string to match.
	return Intrinsic::x86_xop_vpmacsww; // "__builtin_ia32_
	vpmacsww"
	}
	break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+11, "tx_read_smid", 12))
	break;
	return Intrinsic::ptx_read_smid; // "__builtin_ptx_read_smid
	"
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+11, "tack_restore", 12))
	break;
	return Intrinsic::stackrestore; // "__builtin_stack_restore
	"
	}		}
	break;		break;
	case 'n': // 6 strings to match.		case 'M': // 11 strings to match.
	if (memcmp(BuiltinName.data()+3, "vvm_", 4))		switch (BuiltinName[19]) {
	break;
	switch (BuiltinName[7]) {
	default: break;		default: break;
	case 'c': // 1 string to match.		case '2': // 3 strings to match.
	if (memcmp(BuiltinName.data()+8, "os_approx_ftz_f", 15))		if (BuiltinName[20] != '_')
	break;		break;
	return Intrinsic::nvvm_cos_approx_ftz_f; // "__nvvm_cos_appr		switch (BuiltinName[21]) {
	ox_ftz_f"		default: break;
	case 'd': // 1 string to match.		case 'm': // 1 string to match.
	if (memcmp(BuiltinName.data()+8, "iv_approx_ftz_f", 15))		if (memcmp(BuiltinName.data()+22, "pyu_up", 6))
			break;
			return Intrinsic::hexagon_M2_mpyu_up; // "__builtin_HEXAG
			ON_M2_mpyu_up"
			case 'v': // 2 strings to match.
			switch (BuiltinName[22]) {
			default: break;
			case 'm': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "ac2es", 5))
			break;
			return Intrinsic::hexagon_M2_vmac2es; // "__builtin_HEXAG
			ON_M2_vmac2es"
			case 'r': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "adduh", 5))
			break;
			return Intrinsic::hexagon_M2_vradduh; // "__builtin_HEXAG
			ON_M2_vradduh"
			}
	break;		break;
	return Intrinsic::nvvm_div_approx_ftz_f; // "__nvvm_div_appr		}
	ox_ftz_f"		break;
	case 'e': // 1 string to match.		case '4': // 4 strings to match.
	if (memcmp(BuiltinName.data()+8, "x2_approx_ftz_f", 15))		if (BuiltinName[20] != '_')
	break;		break;
	return Intrinsic::nvvm_ex2_approx_ftz_f; // "__nvvm_ex2_appr		switch (BuiltinName[21]) {
	ox_ftz_f"		default: break;
	case 'l': // 1 string to match.		case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+8, "g2_approx_ftz_f", 15))		if (memcmp(BuiltinName.data()+22, "nd_", 3))
			break;
			switch (BuiltinName[25]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "nd", 2))
			break;
			return Intrinsic::hexagon_M4_and_and; // "__builtin_HEXAG
			ON_M4_and_and"
			case 'x': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "or", 2))
			break;
			return Intrinsic::hexagon_M4_and_xor; // "__builtin_HEXAG
			ON_M4_and_xor"
			}
	break;		break;
	return Intrinsic::nvvm_lg2_approx_ftz_f; // "__nvvm_lg2_appr		case 'o': // 1 string to match.
	ox_ftz_f"		if (memcmp(BuiltinName.data()+22, "r_andn", 6))
	case 'r': // 1 string to match.		break;
	if (memcmp(BuiltinName.data()+8, "cp_approx_ftz_d", 15))		return Intrinsic::hexagon_M4_or_andn; // "__builtin_HEXAG
			ON_M4_or_andn"
			case 'x': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "or_and", 6))
			break;
			return Intrinsic::hexagon_M4_xor_and; // "__builtin_HEXAG
			ON_M4_xor_and"
			}
			break;
			case '5': // 4 strings to match.
			if (memcmp(BuiltinName.data()+20, "_vm", 3))
	break;		break;
	return Intrinsic::nvvm_rcp_approx_ftz_d; // "__nvvm_rcp_appr		switch (BuiltinName[23]) {
	ox_ftz_d"		default: break;
	case 's': // 1 string to match.		case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+8, "in_approx_ftz_f", 15))		if (memcmp(BuiltinName.data()+24, "cb", 2))
			break;
			switch (BuiltinName[26]) {
			default: break;
			case 's': // 1 string to match.
			if (BuiltinName[27] != 'u')
			break;
			return Intrinsic::hexagon_M5_vmacbsu; // "__builtin_HEXAG
			ON_M5_vmacbsu"
			case 'u': // 1 string to match.
			if (BuiltinName[27] != 'u')
			break;
			return Intrinsic::hexagon_M5_vmacbuu; // "__builtin_HEXAG
			ON_M5_vmacbuu"
			}
	break;		break;
	return Intrinsic::nvvm_sin_approx_ftz_f; // "__nvvm_sin_appr		case 'p': // 2 strings to match.
	ox_ftz_f"		if (memcmp(BuiltinName.data()+24, "yb", 2))
			break;
			switch (BuiltinName[26]) {
			default: break;
			case 's': // 1 string to match.
			if (BuiltinName[27] != 'u')
			break;
			return Intrinsic::hexagon_M5_vmpybsu; // "__builtin_HEXAG
			ON_M5_vmpybsu"
			case 'u': // 1 string to match.
			if (BuiltinName[27] != 'u')
			break;
			return Intrinsic::hexagon_M5_vmpybuu; // "__builtin_HEXAG
			ON_M5_vmpybuu"
			}
			break;
			}
			break;
	}		}
	break;		break;
	}		case 'S': // 30 strings to match.
	break;		switch (BuiltinName[19]) {
	case 24: // 19 strings to match.
	if (memcmp(BuiltinName.data()+0, "__", 2))
	break;
	switch (BuiltinName[2]) {
	default: break;
	case 'b': // 18 strings to match.
	if (memcmp(BuiltinName.data()+3, "uiltin_", 7))
	break;
	switch (BuiltinName[10]) {
	default: break;		default: break;
	case 'i': // 12 strings to match.		case '2': // 25 strings to match.
	if (memcmp(BuiltinName.data()+11, "a32_vp", 6))		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[17]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'h': // 6 strings to match.		case 'a': // 8 strings to match.
	if (memcmp(BuiltinName.data()+18, "addu", 4))		if (BuiltinName[22] != 's')
	break;		break;
	switch (BuiltinName[22]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'b': // 3 strings to match.		case 'l': // 4 strings to match.
	switch (BuiltinName[23]) {		if (BuiltinName[24] != '_')
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_xop_vphaddubd; // "__builtin_ia32_
	vphaddubd"
	case 'q': // 1 string to match.
	return Intrinsic::x86_xop_vphaddubq; // "__builtin_ia32_
	vphaddubq"
	case 'w': // 1 string to match.
	return Intrinsic::x86_xop_vphaddubw; // "__builtin_ia32_
	vphaddubw"
	}
	break;
	case 'd': // 1 string to match.
	if (BuiltinName[23] != 'q')
	break;		break;
	return Intrinsic::x86_xop_vphaddudq; // "__builtin_ia32_		switch (BuiltinName[25]) {
	vphaddudq"
	case 'w': // 2 strings to match.
	switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'i': // 2 strings to match.
	return Intrinsic::x86_xop_vphadduwd; // "__builtin_ia32_		if (BuiltinName[26] != '_')
	vphadduwd"		break;
	case 'q': // 1 string to match.		switch (BuiltinName[27]) {
	return Intrinsic::x86_xop_vphadduwq; // "__builtin_ia32_		default: break;
	vphadduwq"		case 'p': // 1 string to match.
			return Intrinsic::hexagon_S2_asl_i_p; // "__builtin_HEXAG
			ON_S2_asl_i_p"
			case 'r': // 1 string to match.
			return Intrinsic::hexagon_S2_asl_i_r; // "__builtin_HEXAG
			ON_S2_asl_i_r"
			}
			break;
			case 'r': // 2 strings to match.
			if (BuiltinName[26] != '_')
			break;
			switch (BuiltinName[27]) {
			default: break;
			case 'p': // 1 string to match.
			return Intrinsic::hexagon_S2_asl_r_p; // "__builtin_HEXAG
			ON_S2_asl_r_p"
			case 'r': // 1 string to match.
			return Intrinsic::hexagon_S2_asl_r_r; // "__builtin_HEXAG
			ON_S2_asl_r_r"
			}
			break;
	}		}
	break;		break;
	}		case 'r': // 4 strings to match.
	break;		if (BuiltinName[24] != '_')
	case 'm': // 6 strings to match.
	if (BuiltinName[18] != 'a')
	break;
	switch (BuiltinName[19]) {
	default: break;
	case 'c': // 5 strings to match.
	if (BuiltinName[20] != 's')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'd': // 2 strings to match.		case 'i': // 2 strings to match.
	if (BuiltinName[22] != 'q')		if (BuiltinName[26] != '_')
	break;		break;
	switch (BuiltinName[23]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'p': // 1 string to match.
	return Intrinsic::x86_xop_vpmacsdqh; // "__builtin_ia32_		return Intrinsic::hexagon_S2_asr_i_p; // "__builtin_HEXAG
	vpmacsdqh"		ON_S2_asr_i_p"
	case 'l': // 1 string to match.		case 'r': // 1 string to match.
	return Intrinsic::x86_xop_vpmacsdql; // "__builtin_ia32_		return Intrinsic::hexagon_S2_asr_i_r; // "__builtin_HEXAG
	vpmacsdql"		ON_S2_asr_i_r"
	}		}
	break;		break;
	case 's': // 3 strings to match.		case 'r': // 2 strings to match.
	switch (BuiltinName[22]) {		if (BuiltinName[26] != '_')
	default: break;
	case 'd': // 1 string to match.
	if (BuiltinName[23] != 'd')
	break;
	return Intrinsic::x86_xop_vpmacssdd; // "__builtin_ia32_
	vpmacssdd"
	case 'w': // 2 strings to match.
	switch (BuiltinName[23]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::x86_xop_vpmacsswd; // "__builtin_ia32_
	vpmacsswd"
	case 'w': // 1 string to match.
	return Intrinsic::x86_xop_vpmacssww; // "__builtin_ia32_
	vpmacssww"
	}
	break;		break;
			switch (BuiltinName[27]) {
			default: break;
			case 'p': // 1 string to match.
			return Intrinsic::hexagon_S2_asr_r_p; // "__builtin_HEXAG
			ON_S2_asr_r_p"
			case 'r': // 1 string to match.
			return Intrinsic::hexagon_S2_asr_r_r; // "__builtin_HEXAG
			ON_S2_asr_r_r"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "cswd", 4))
	break;
	return Intrinsic::x86_xop_vpmadcswd; // "__builtin_ia32_
	vpmadcswd"
	}		}
	break;		break;
	}
	break;
	case 'p': // 6 strings to match.
	if (memcmp(BuiltinName.data()+11, "tx_read_", 8))
	break;
	switch (BuiltinName[19]) {
	default: break;
	case 'c': // 1 string to match.		case 'c': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "lock", 4))		if (memcmp(BuiltinName.data()+22, "lbnorm", 6))
	break;
	return Intrinsic::ptx_read_clock; // "__builtin_ptx_read_cloc
	k"
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "smid", 4))
	break;
	return Intrinsic::ptx_read_nsmid; // "__builtin_ptx_read_nsmi
	d"
	case 't': // 4 strings to match.
	if (memcmp(BuiltinName.data()+20, "id_", 3))
	break;
	switch (BuiltinName[23]) {
	default: break;
	case 'w': // 1 string to match.
	return Intrinsic::ptx_read_tid_w; // "__builtin_ptx_read_tid_
	w"
	case 'x': // 1 string to match.
	return Intrinsic::ptx_read_tid_x; // "__builtin_ptx_read_tid_
	x"
	case 'y': // 1 string to match.
	return Intrinsic::ptx_read_tid_y; // "__builtin_ptx_read_tid_
	y"
	case 'z': // 1 string to match.
	return Intrinsic::ptx_read_tid_z; // "__builtin_ptx_read_tid_
	z"
	}
	break;
	}
	break;
	}
	break;
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+3, "vvm_sqrt_approx_ftz_f", 21))
	break;
	return Intrinsic::nvvm_sqrt_approx_ftz_f; // "__nvvm_sqrt_app
	rox_ftz_f"
	}
	break;
	case 25: // 17 strings to match.
	if (memcmp(BuiltinName.data()+0, "__", 2))
	break;
	switch (BuiltinName[2]) {
	default: break;
	case 'b': // 16 strings to match.
	if (memcmp(BuiltinName.data()+3, "uiltin_", 7))
	break;
	switch (BuiltinName[10]) {
	default: break;
	case 'i': // 9 strings to match.
	switch (BuiltinName[11]) {
	default: break;
	case 'a': // 8 strings to match.
	if (memcmp(BuiltinName.data()+12, "32_v", 4))
	break;		break;
	switch (BuiltinName[16]) {		return Intrinsic::hexagon_S2_clbnorm; // "__builtin_HEXAG
			ON_S2_clbnorm"
			case 'i': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "nsertp", 6))
			break;
			return Intrinsic::hexagon_S2_insertp; // "__builtin_HEXAG
			ON_S2_insertp"
			case 'l': // 6 strings to match.
			if (BuiltinName[22] != 's')
			break;
			switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'f': // 2 strings to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+17, "rczp", 4))		if (memcmp(BuiltinName.data()+24, "_r_", 3))
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "256", 3))		return Intrinsic::hexagon_S2_lsl_r_p; // "__builtin_HEXAG
	break;		ON_S2_lsl_r_p"
	return Intrinsic::x86_xop_vfrcz_pd_256; // "__builtin_ia32_		case 'r': // 1 string to match.
	vfrczpd256"		return Intrinsic::hexagon_S2_lsl_r_r; // "__builtin_HEXAG
	case 's': // 1 string to match.		ON_S2_lsl_r_r"
	if (memcmp(BuiltinName.data()+22, "256", 3))
	break;
	return Intrinsic::x86_xop_vfrcz_ps_256; // "__builtin_ia32_
	vfrczps256"
	}		}
	break;		break;
	case 'p': // 6 strings to match.		case 'r': // 4 strings to match.
	switch (BuiltinName[17]) {		if (BuiltinName[24] != '_')
			break;
			switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'c': // 1 string to match.		case 'i': // 2 strings to match.
	if (memcmp(BuiltinName.data()+18, "mov_256", 7))		if (BuiltinName[26] != '_')
	break;
	return Intrinsic::x86_xop_vpcmov_256; // "__builtin_ia32_
	vpcmov_256"
	case 'e': // 2 strings to match.
	if (memcmp(BuiltinName.data()+18, "rmil2p", 6))
	break;		break;
	switch (BuiltinName[24]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'p': // 1 string to match.
	return Intrinsic::x86_xop_vpermil2pd; // "__builtin_ia32_		return Intrinsic::hexagon_S2_lsr_i_p; // "__builtin_HEXAG
	vpermil2pd"		ON_S2_lsr_i_p"
	case 's': // 1 string to match.		case 'r': // 1 string to match.
	return Intrinsic::x86_xop_vpermil2ps; // "__builtin_ia32_		return Intrinsic::hexagon_S2_lsr_i_r; // "__builtin_HEXAG
	vpermil2ps"		ON_S2_lsr_i_r"
	}		}
	break;		break;
	case 'm': // 3 strings to match.		case 'r': // 2 strings to match.
	if (BuiltinName[18] != 'a')		if (BuiltinName[26] != '_')
	break;		break;
	switch (BuiltinName[19]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'c': // 2 strings to match.		case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "ssdq", 4))		return Intrinsic::hexagon_S2_lsr_r_p; // "__builtin_HEXAG
	break;		ON_S2_lsr_r_p"
	switch (BuiltinName[24]) {		case 'r': // 1 string to match.
	default: break;		return Intrinsic::hexagon_S2_lsr_r_r; // "__builtin_HEXAG
	case 'h': // 1 string to match.		ON_S2_lsr_r_r"
	return Intrinsic::x86_xop_vpmacssdqh; // "__built
	in_ia32_vpmacssdqh"
	case 'l': // 1 string to match.
	return Intrinsic::x86_xop_vpmacssdql; // "__built
	in_ia32_vpmacssdql"
	}
	break;
	case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "csswd", 5))
	break;
	return Intrinsic::x86_xop_vpmadcsswd; // "__builtin_ia32_
	vpmadcsswd"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'n': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+12, "it_trampoline", 13))		if (memcmp(BuiltinName.data()+22, "arityp", 6))
	break;
	return Intrinsic::init_trampoline; // "__builtin_init_trampoli
	ne"
	}
	break;
	case 'p': // 7 strings to match.
	if (memcmp(BuiltinName.data()+11, "tx_read_", 8))
	break;
	switch (BuiltinName[19]) {
	default: break;
	case 'g': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "ridid", 5))
	break;
	return Intrinsic::ptx_read_gridid; // "__builtin_ptx_read_grid
	id"
	case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "aneid", 5))
	break;
	return Intrinsic::ptx_read_laneid; // "__builtin_ptx_read_lane
	id"
	case 'n': // 4 strings to match.
	if (memcmp(BuiltinName.data()+20, "tid_", 4))
	break;		break;
	switch (BuiltinName[24]) {		return Intrinsic::hexagon_S2_parityp; // "__builtin_HEXAG
			ON_S2_parityp"
			case 's': // 5 strings to match.
			switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'w': // 1 string to match.		case 'h': // 4 strings to match.
	return Intrinsic::ptx_read_ntid_w; // "__builtin_ptx_read_ntid		if (memcmp(BuiltinName.data()+23, "uff", 3))
	_w"		break;
	case 'x': // 1 string to match.		switch (BuiltinName[26]) {
	return Intrinsic::ptx_read_ntid_x; // "__builtin_ptx_read_ntid		default: break;
	_x"		case 'e': // 2 strings to match.
	case 'y': // 1 string to match.		switch (BuiltinName[27]) {
	return Intrinsic::ptx_read_ntid_y; // "__builtin_ptx_read_ntid		default: break;
	_y"		case 'b': // 1 string to match.
	case 'z': // 1 string to match.		return Intrinsic::hexagon_S2_shuffeb; // "__builtin_HEXAG
	return Intrinsic::ptx_read_ntid_z; // "__builtin_ptx_read_ntid		ON_S2_shuffeb"
	_z"		case 'h': // 1 string to match.
			return Intrinsic::hexagon_S2_shuffeh; // "__builtin_HEXAG
			ON_S2_shuffeh"
			}
			break;
			case 'o': // 2 strings to match.
			switch (BuiltinName[27]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::hexagon_S2_shuffob; // "__builtin_HEXAG
			ON_S2_shuffob"
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_S2_shuffoh; // "__builtin_HEXAG
			ON_S2_shuffoh"
			}
			break;
			}
			break;
			case 'v': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "sathb", 5))
			break;
			return Intrinsic::hexagon_S2_svsathb; // "__builtin_HEXAG
			ON_S2_svsathb"
	}		}
	break;		break;
	case 'w': // 1 string to match.		case 'v': // 3 strings to match.
	if (memcmp(BuiltinName.data()+20, "arpid", 5))		switch (BuiltinName[22]) {
	break;
	return Intrinsic::ptx_read_warpid; // "__builtin_ptx_read_warp
	id"
	}
	break;
	}
	break;
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+3, "vvm_rsqrt_approx_ftz_f", 22))
	break;
	return Intrinsic::nvvm_rsqrt_approx_ftz_f; // "__nvvm_rsqrt_ap
	prox_ftz_f"
	}
	break;
	case 26: // 9 strings to match.
	if (memcmp(BuiltinName.data()+0, "__", 2))
	break;
	switch (BuiltinName[2]) {
	default: break;
	case 'b': // 6 strings to match.
	if (memcmp(BuiltinName.data()+3, "uiltin_ptx_read_", 16))
	break;
	switch (BuiltinName[19]) {
	default: break;
	case 'c': // 5 strings to match.
	switch (BuiltinName[20]) {
	default: break;
	case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+21, "ock64", 5))
	break;
	return Intrinsic::ptx_read_clock64; // "__builtin_ptx_read_cloc
	k64"
	case 't': // 4 strings to match.
	if (memcmp(BuiltinName.data()+21, "aid_", 4))
	break;
	switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'w': // 1 string to match.		case 'r': // 1 string to match.
	return Intrinsic::ptx_read_ctaid_w; // "__builtin_ptx_r		if (memcmp(BuiltinName.data()+23, "cnegh", 5))
	ead_ctaid_w"		break;
	case 'x': // 1 string to match.		return Intrinsic::hexagon_S2_vrcnegh; // "__builtin_HEXAG
	return Intrinsic::ptx_read_ctaid_x; // "__builtin_ptx_r		ON_S2_vrcnegh"
	ead_ctaid_x"		case 's': // 2 strings to match.
	case 'y': // 1 string to match.		if (memcmp(BuiltinName.data()+23, "at", 2))
	return Intrinsic::ptx_read_ctaid_y; // "__builtin_ptx_r		break;
	ead_ctaid_y"		switch (BuiltinName[25]) {
	case 'z': // 1 string to match.		default: break;
	return Intrinsic::ptx_read_ctaid_z; // "__builtin_ptx_r		case 'h': // 1 string to match.
	ead_ctaid_z"		if (memcmp(BuiltinName.data()+26, "ub", 2))
			break;
			return Intrinsic::hexagon_S2_vsathub; // "__builtin_HEXAG
			ON_S2_vsathub"
			case 'w': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "uh", 2))
			break;
			return Intrinsic::hexagon_S2_vsatwuh; // "__builtin_HEXAG
			ON_S2_vsatwuh"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'n': // 1 string to match.		case '4': // 5 strings to match.
	if (memcmp(BuiltinName.data()+20, "warpid", 6))		if (BuiltinName[20] != '_')
	break;
	return Intrinsic::ptx_read_nwarpid; // "__builtin_ptx_read_nwar
	pid"
	}
	break;
	case 'n': // 3 strings to match.
	if (memcmp(BuiltinName.data()+3, "vvm_read_ptx_sreg_tid_", 22))
	break;
	switch (BuiltinName[25]) {
	default: break;
	case 'x': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_tid_x; // "__nvvm_read_ptx
	_sreg_tid_x"
	case 'y': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_tid_y; // "__nvvm_read_ptx
	_sreg_tid_y"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_tid_z; // "__nvvm_read_ptx
	_sreg_tid_z"
	}
	break;
	}
	break;
	case 27: // 8 strings to match.
	if (memcmp(BuiltinName.data()+0, "__", 2))
	break;
	switch (BuiltinName[2]) {
	default: break;
	case 'b': // 5 strings to match.
	if (memcmp(BuiltinName.data()+3, "uiltin_", 7))
	break;
	switch (BuiltinName[10]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+11, "djust_trampoline", 16))
	break;
	return Intrinsic::adjust_trampoline; // "__builtin_adjust_trampo
	line"
	case 'p': // 4 strings to match.
	if (memcmp(BuiltinName.data()+11, "tx_read_nctaid_", 15))
	break;
	switch (BuiltinName[26]) {
	default: break;
	case 'w': // 1 string to match.
	return Intrinsic::ptx_read_nctaid_w; // "__builtin_ptx_read_ncta
	id_w"
	case 'x': // 1 string to match.
	return Intrinsic::ptx_read_nctaid_x; // "__builtin_ptx_read_ncta
	id_x"
	case 'y': // 1 string to match.
	return Intrinsic::ptx_read_nctaid_y; // "__builtin_ptx_read_ncta
	id_y"
	case 'z': // 1 string to match.
	return Intrinsic::ptx_read_nctaid_z; // "__builtin_ptx_read_ncta
	id_z"
	}
	break;
	}
	break;
	case 'n': // 3 strings to match.
	if (memcmp(BuiltinName.data()+3, "vvm_read_ptx_sreg_ntid_", 23))
	break;
	switch (BuiltinName[26]) {
	default: break;
	case 'x': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_ntid_x; // "__nvvm_read_ptx
	_sreg_ntid_x"
	case 'y': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_ntid_y; // "__nvvm_read_ptx
	_sreg_ntid_y"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_ntid_z; // "__nvvm_read_ptx
	_sreg_ntid_z"
	}
	break;
	}
	break;
	case 28: // 5 strings to match.
	if (memcmp(BuiltinName.data()+0, "__", 2))
	break;
	switch (BuiltinName[2]) {
	default: break;
	case 'b': // 2 strings to match.
	if (memcmp(BuiltinName.data()+3, "uiltin_ia32_vpermil2p", 21))
	break;
	switch (BuiltinName[24]) {
	default: break;
	case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "256", 3))
	break;
	return Intrinsic::x86_xop_vpermil2pd_256; // "__builtin_ia32_
	vpermil2pd256"
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "256", 3))
	break;
	return Intrinsic::x86_xop_vpermil2ps_256; // "__builtin_ia32_
	vpermil2ps256"
	}
	break;
	case 'n': // 3 strings to match.
	if (memcmp(BuiltinName.data()+3, "vvm_read_ptx_sreg_ctaid_", 24))
	break;
	switch (BuiltinName[27]) {
	default: break;
	case 'x': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_ctaid_x; // "__nvvm_read_ptx
	_sreg_ctaid_x"
	case 'y': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_ctaid_y; // "__nvvm_read_ptx
	_sreg_ctaid_y"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_ctaid_z; // "__nvvm_read_ptx
	_sreg_ctaid_z"
	}
	break;
	}
	break;
	case 29: // 4 strings to match.
	if (memcmp(BuiltinName.data()+0, "__nvvm_read_ptx_sreg_", 21))
	break;
	switch (BuiltinName[21]) {
	default: break;
	case 'n': // 3 strings to match.
	if (memcmp(BuiltinName.data()+22, "ctaid_", 6))
	break;
	switch (BuiltinName[28]) {
	default: break;
	case 'x': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_nctaid_x; // "__nvvm_read_ptx
	_sreg_nctaid_x"
	case 'y': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_nctaid_y; // "__nvvm_read_ptx
	_sreg_nctaid_y"
	case 'z': // 1 string to match.
	return Intrinsic::nvvm_read_ptx_sreg_nctaid_z; // "__nvvm_read_ptx
	_sreg_nctaid_z"
	}
	break;
	case 'w': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "arpsize", 7))
	break;
	return Intrinsic::nvvm_read_ptx_sreg_warpsize; // "__nvvm_read_ptx
	_sreg_warpsize"
	}
	break;
	case 30: // 5 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_ptx_read_lanemask_", 28))
	break;
	switch (BuiltinName[28]) {
	default: break;
	case 'e': // 1 string to match.
	if (BuiltinName[29] != 'q')
	break;
	return Intrinsic::ptx_read_lanemask_eq; // "__builtin_ptx_read_lane
	mask_eq"
	case 'g': // 2 strings to match.
	switch (BuiltinName[29]) {
	default: break;
	case 'e': // 1 string to match.
	return Intrinsic::ptx_read_lanemask_ge; // "__builtin_ptx_r
	ead_lanemask_ge"
	case 't': // 1 string to match.
	return Intrinsic::ptx_read_lanemask_gt; // "__builtin_ptx_r
	ead_lanemask_gt"
	}
	break;
	case 'l': // 2 strings to match.
	switch (BuiltinName[29]) {
	default: break;
	case 'e': // 1 string to match.
	return Intrinsic::ptx_read_lanemask_le; // "__builtin_ptx_r
	ead_lanemask_le"
	case 't': // 1 string to match.
	return Intrinsic::ptx_read_lanemask_lt; // "__builtin_ptx_r
	ead_lanemask_lt"
	}
	break;
	}
	break;
	}
	}
	if (TargetPrefix == "arm") {
	switch (BuiltinName.size()) {
	default: break;
	case 17: // 3 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_arm_", 14))
	break;
	switch (BuiltinName[14]) {
	default: break;
	case 'c': // 1 string to match.
	if (memcmp(BuiltinName.data()+15, "dp", 2))
	break;
	return Intrinsic::arm_cdp; // "__builtin_arm_cdp"
	case 'm': // 2 strings to match.
	switch (BuiltinName[15]) {
	default: break;
	case 'c': // 1 string to match.
	if (BuiltinName[16] != 'r')
	break;
	return Intrinsic::arm_mcr; // "__builtin_arm_mcr"
	case 'r': // 1 string to match.
	if (BuiltinName[16] != 'c')
	break;
	return Intrinsic::arm_mrc; // "__builtin_arm_mrc"
	}
	break;
	}
	break;
	case 18: // 8 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_arm_", 14))
	break;
	switch (BuiltinName[14]) {
	default: break;
	case 'c': // 1 string to match.
	if (memcmp(BuiltinName.data()+15, "dp2", 3))
	break;
	return Intrinsic::arm_cdp2; // "__builtin_arm_cdp2"
	case 'm': // 3 strings to match.
	switch (BuiltinName[15]) {
	default: break;
	case 'c': // 2 strings to match.
	if (BuiltinName[16] != 'r')
	break;		break;
	switch (BuiltinName[17]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case '2': // 1 string to match.		case 'a': // 1 string to match.
	return Intrinsic::arm_mcr2; // "__builtin_arm_mcr2"		if (memcmp(BuiltinName.data()+22, "ddaddi", 6))
	case 'r': // 1 string to match.		break;
	return Intrinsic::arm_mcrr; // "__builtin_arm_mcrr"		return Intrinsic::hexagon_S4_addaddi; // "__builtin_HEXAG
			ON_S4_addaddi"
			case 'c': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "lbaddi", 6))
			break;
			return Intrinsic::hexagon_S4_clbaddi; // "__builtin_HEXAG
			ON_S4_clbaddi"
			case 'e': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "xtract", 6))
			break;
			return Intrinsic::hexagon_S4_extract; // "__builtin_HEXAG
			ON_S4_extract"
			case 'o': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "r_andi", 6))
			break;
			return Intrinsic::hexagon_S4_or_andi; // "__builtin_HEXAG
			ON_S4_or_andi"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "ubaddi", 6))
			break;
			return Intrinsic::hexagon_S4_subaddi; // "__builtin_HEXAG
			ON_S4_subaddi"
	}		}
	break;		break;
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "c2", 2))
	break;
	return Intrinsic::arm_mrc2; // "__builtin_arm_mrc2"
	}
	break;
	case 'q': // 2 strings to match.
	switch (BuiltinName[15]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "dd", 2))
	break;
	return Intrinsic::arm_qadd; // "__builtin_arm_qadd"
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "ub", 2))
	break;
	return Intrinsic::arm_qsub; // "__builtin_arm_qsub"
	}		}
	break;		break;
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+15, "sat", 3))
	break;
	return Intrinsic::arm_ssat; // "__builtin_arm_ssat"
	case 'u': // 1 string to match.
	if (memcmp(BuiltinName.data()+15, "sat", 3))
	break;
	return Intrinsic::arm_usat; // "__builtin_arm_usat"
	}
	break;
	case 19: // 1 string to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_arm_mcrr2", 19))
	break;
	return Intrinsic::arm_mcrr2; // "__builtin_arm_mcrr2"
	case 23: // 2 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_arm_", 14))
	break;
	switch (BuiltinName[14]) {
	default: break;
	case 'g': // 1 string to match.
	if (memcmp(BuiltinName.data()+15, "et_fpscr", 8))
	break;
	return Intrinsic::arm_get_fpscr; // "__builtin_arm_get_fpscr"
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+15, "et_fpscr", 8))
	break;
	return Intrinsic::arm_set_fpscr; // "__builtin_arm_set_fpscr"
	}
	break;
	case 24: // 1 string to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_thread_pointer", 24))
	break;
	return Intrinsic::arm_thread_pointer; // "__builtin_thread_pointe
	r"
	}
	}
	if (TargetPrefix == "hexagon") {
	switch (BuiltinName.size()) {
	default: break;
	case 18: // 1 string to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_circ_ldd", 18))
	break;
	return Intrinsic::hexagon_circ_ldd; // "__builtin_circ_ldd"
	case 23: // 2 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
	break;
	switch (BuiltinName[18]) {
	default: break;
	case 'A': // 1 string to match.
	if (memcmp(BuiltinName.data()+19, "2_or", 4))
	break;
	return Intrinsic::hexagon_A2_or; // "__builtin_HEXAGON_A2_or"
	case 'C': // 1 string to match.
	if (memcmp(BuiltinName.data()+19, "2_or", 4))
	break;
	return Intrinsic::hexagon_C2_or; // "__builtin_HEXAGON_C2_or"
	}		}
	break;		break;
	case 24: // 23 strings to match.		case 29: // 103 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))		if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
	break;		break;
	switch (BuiltinName[18]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'A': // 13 strings to match.		case 'A': // 26 strings to match.
	switch (BuiltinName[19]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case '2': // 12 strings to match.		case '2': // 11 strings to match.
	if (BuiltinName[20] != '_')		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'a': // 3 strings to match.		case 'c': // 1 string to match.
	switch (BuiltinName[22]) {		if (memcmp(BuiltinName.data()+22, "ombinew", 7))
			break;
			return Intrinsic::hexagon_A2_combinew; // "__builtin_HEXAG
			ON_A2_combinew"
			case 'r': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "oundsat", 7))
			break;
			return Intrinsic::hexagon_A2_roundsat; // "__builtin_HEXAG
			ON_A2_roundsat"
			case 's': // 2 strings to match.
			if (BuiltinName[22] != 'v')
			break;
			switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'a': // 1 string to match.
	if (BuiltinName[23] != 's')		if (memcmp(BuiltinName.data()+24, "dduhs", 5))
	break;
	return Intrinsic::hexagon_A2_abs; // "__builtin_HEXAGON_A2_ab
	s"
	case 'd': // 1 string to match.
	if (BuiltinName[23] != 'd')
	break;		break;
	return Intrinsic::hexagon_A2_add; // "__builtin_HEXAGON_A2_ad		return Intrinsic::hexagon_A2_svadduhs; // "__builtin_HEXAG
	d"		ON_A2_svadduhs"
	case 'n': // 1 string to match.		case 's': // 1 string to match.
	if (BuiltinName[23] != 'd')		if (memcmp(BuiltinName.data()+24, "ubuhs", 5))
	break;		break;
	return Intrinsic::hexagon_A2_and; // "__builtin_HEXAGON_A2_an d"		return Intrinsic::hexagon_A2_svsubuhs; // "__builtin_HEXAG ON_A2_svsubuhs"
	}		}
	break;		break;
	case 'm': // 2 strings to match.		case 'v': // 7 strings to match.
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'a': // 2 strings to match.
	if (BuiltinName[23] != 'x')		if (memcmp(BuiltinName.data()+23, "bs", 2))
	break;		break;
	return Intrinsic::hexagon_A2_max; // "__builtin_HEXAGON_A2_ma		switch (BuiltinName[25]) {
	x"		default: break;
	case 'i': // 1 string to match.		case 'h': // 1 string to match.
	if (BuiltinName[23] != 'n')		if (memcmp(BuiltinName.data()+26, "sat", 3))
			break;
			return Intrinsic::hexagon_A2_vabshsat; // "__builtin_HEXAG
			ON_A2_vabshsat"
			case 'w': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "sat", 3))
			break;
			return Intrinsic::hexagon_A2_vabswsat; // "__builtin_HEXAG
			ON_A2_vabswsat"
			}
			break;
			case 'c': // 3 strings to match.
			if (memcmp(BuiltinName.data()+23, "mp", 2))
	break;		break;
	return Intrinsic::hexagon_A2_min; // "__builtin_HEXAGON_A2_mi		switch (BuiltinName[25]) {
	n"		default: break;
			case 'b': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "gtu", 3))
			break;
			return Intrinsic::hexagon_A2_vcmpbgtu; // "__builtin_HEXAG
			ON_A2_vcmpbgtu"
			case 'h': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "gtu", 3))
			break;
			return Intrinsic::hexagon_A2_vcmphgtu; // "__builtin_HEXAG
			ON_A2_vcmphgtu"
			case 'w': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "gtu", 3))
			break;
			return Intrinsic::hexagon_A2_vcmpwgtu; // "__builtin_HEXAG
			ON_A2_vcmpwgtu"
			}
			break;
			case 'n': // 2 strings to match.
			if (memcmp(BuiltinName.data()+23, "avg", 3))
			break;
			switch (BuiltinName[26]) {
			default: break;
			case 'h': // 1 string to match.
			if (memcmp(BuiltinName.data()+27, "cr", 2))
			break;
			return Intrinsic::hexagon_A2_vnavghcr; // "__builtin_HEXAG
			ON_A2_vnavghcr"
			case 'w': // 1 string to match.
			if (memcmp(BuiltinName.data()+27, "cr", 2))
			break;
			return Intrinsic::hexagon_A2_vnavgwcr; // "__builtin_HEXAG
			ON_A2_vnavgwcr"
			}
			break;
	}		}
	break;		break;
	case 'n': // 2 strings to match.		}
	switch (BuiltinName[22]) {		break;
			case '4': // 14 strings to match.
			if (BuiltinName[20] != '_')
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'b': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "itsplit", 7))
			break;
			return Intrinsic::hexagon_A4_bitsplit; // "__builtin_HEXAG
			ON_A4_bitsplit"
			case 'c': // 2 strings to match.
			if (memcmp(BuiltinName.data()+22, "mp", 2))
			break;
			switch (BuiltinName[24]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'b': // 1 string to match.
	if (BuiltinName[23] != 'g')		if (memcmp(BuiltinName.data()+25, "gtui", 4))
	break;		break;
	return Intrinsic::hexagon_A2_neg; // "__builtin_HEXAGON_A2_ne		return Intrinsic::hexagon_A4_cmpbgtui; // "__builtin_HEXAG
	g"		ON_A4_cmpbgtui"
	case 'o': // 1 string to match.		case 'h': // 1 string to match.
	if (BuiltinName[23] != 't')		if (memcmp(BuiltinName.data()+25, "gtui", 4))
	break;		break;
	return Intrinsic::hexagon_A2_not; // "__builtin_HEXAGON_A2_no t"		return Intrinsic::hexagon_A4_cmphgtui; // "__builtin_HEXAG ON_A4_cmphgtui"
	}		}
	break;		break;
	case 'o': // 1 string to match.		case 'm': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "rp", 2))		if (memcmp(BuiltinName.data()+22, "odwrapu", 7))
	break;		break;
	return Intrinsic::hexagon_A2_orp; // "__builtin_HEXAGON_A2_or		return Intrinsic::hexagon_A4_modwrapu; // "__builtin_HEXAG
	p"		ON_A4_modwrapu"
	case 's': // 2 strings to match.		case 'r': // 3 strings to match.
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'c': // 1 string to match.
	if (BuiltinName[23] != 't')		if (memcmp(BuiltinName.data()+23, "mpneqi", 6))
	break;		break;
	return Intrinsic::hexagon_A2_sat; // "__builtin_HEXAGON_A2_sa		return Intrinsic::hexagon_A4_rcmpneqi; // "__builtin_HEXAG
	t"		ON_A4_rcmpneqi"
	case 'u': // 1 string to match.		case 'o': // 2 strings to match.
	if (BuiltinName[23] != 'b')		if (memcmp(BuiltinName.data()+23, "und_r", 5))
	break;		break;
	return Intrinsic::hexagon_A2_sub; // "__builtin_HEXAGON_A2_su		switch (BuiltinName[28]) {
	b"		default: break;
			case 'i': // 1 string to match.
			return Intrinsic::hexagon_A4_round_ri; // "__builtin_HEXAG
			ON_A4_round_ri"
			case 'r': // 1 string to match.
			return Intrinsic::hexagon_A4_round_rr; // "__builtin_HEXAG
			ON_A4_round_rr"
			}
			break;
	}		}
	break;		break;
	case 't': // 1 string to match.		case 't': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "fr", 2))		if (memcmp(BuiltinName.data()+22, "lbmatch", 7))
	break;		break;
	return Intrinsic::hexagon_A2_tfr; // "__builtin_HEXAGON_A2_tf		return Intrinsic::hexagon_A4_tlbmatch; // "__builtin_HEXAG
	r"		ON_A4_tlbmatch"
	case 'x': // 1 string to match.		case 'v': // 6 strings to match.
	if (memcmp(BuiltinName.data()+22, "or", 2))		if (memcmp(BuiltinName.data()+22, "cmp", 3))
	break;		break;
	return Intrinsic::hexagon_A2_xor; // "__builtin_HEXAGON_A2_xo		switch (BuiltinName[25]) {
	r"		default: break;
			case 'b': // 2 strings to match.
			switch (BuiltinName[26]) {
			default: break;
			case 'e': // 1 string to match.
			if (memcmp(BuiltinName.data()+27, "qi", 2))
			break;
			return Intrinsic::hexagon_A4_vcmpbeqi; // "__builtin_HEXAG
			ON_A4_vcmpbeqi"
			case 'g': // 1 string to match.
			if (memcmp(BuiltinName.data()+27, "ti", 2))
			break;
			return Intrinsic::hexagon_A4_vcmpbgti; // "__builtin_HEXAG
			ON_A4_vcmpbgti"
			}
			break;
			case 'h': // 2 strings to match.
			switch (BuiltinName[26]) {
			default: break;
			case 'e': // 1 string to match.
			if (memcmp(BuiltinName.data()+27, "qi", 2))
			break;
			return Intrinsic::hexagon_A4_vcmpheqi; // "__builtin_HEXAG
			ON_A4_vcmpheqi"
			case 'g': // 1 string to match.
			if (memcmp(BuiltinName.data()+27, "ti", 2))
			break;
			return Intrinsic::hexagon_A4_vcmphgti; // "__builtin_HEXAG
			ON_A4_vcmphgti"
			}
			break;
			case 'w': // 2 strings to match.
			switch (BuiltinName[26]) {
			default: break;
			case 'e': // 1 string to match.
			if (memcmp(BuiltinName.data()+27, "qi", 2))
			break;
			return Intrinsic::hexagon_A4_vcmpweqi; // "__builtin_HEXAG
			ON_A4_vcmpweqi"
			case 'g': // 1 string to match.
			if (memcmp(BuiltinName.data()+27, "ti", 2))
			break;
			return Intrinsic::hexagon_A4_vcmpwgti; // "__builtin_HEXAG
			ON_A4_vcmpwgti"
			}
			break;
			}
			break;
	}		}
	break;		break;
	case '4': // 1 string to match.		case '5': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "_orn", 4))		if (memcmp(BuiltinName.data()+20, "_vaddhubs", 9))
	break;		break;
	return Intrinsic::hexagon_A4_orn; // "__builtin_HEXAGON_A4_or n"		return Intrinsic::hexagon_A5_vaddhubs; // "__builtin_HEXAGON_A5_va ddhubs"
	}		}
	break;		break;
	case 'C': // 5 strings to match.		case 'C': // 5 strings to match.
	if (memcmp(BuiltinName.data()+19, "2_", 2))		switch (BuiltinName[19]) {
	break;
	switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "nd", 2))		if (memcmp(BuiltinName.data()+20, "_bitsclri", 9))
	break;
	return Intrinsic::hexagon_C2_and; // "__builtin_HEXAGON_C2_an
	d"
	case 'm': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "ux", 2))
	break;
	return Intrinsic::hexagon_C2_mux; // "__builtin_HEXAGON_C2_mu
	x"
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "ot", 2))
	break;		break;
	return Intrinsic::hexagon_C2_not; // "__builtin_HEXAGON_C2_no		return Intrinsic::hexagon_C2_bitsclri; // "__builtin_HEXAGON_C2_bi
	t"		tsclri"
	case 'o': // 1 string to match.		case '4': // 4 strings to match.
	if (memcmp(BuiltinName.data()+22, "rn", 2))		if (BuiltinName[20] != '_')
	break;		break;
	return Intrinsic::hexagon_C2_orn; // "__builtin_HEXAGON_C2_or		switch (BuiltinName[21]) {
	n"		default: break;
	case 'x': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "or", 2))		if (memcmp(BuiltinName.data()+22, "nd_andn", 7))
			break;
			return Intrinsic::hexagon_C4_and_andn; // "__builtin_HEXAG
			ON_C4_and_andn"
			case 'c': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "mplteui", 7))
			break;
			return Intrinsic::hexagon_C4_cmplteui; // "__builtin_HEXAG
			ON_C4_cmplteui"
			case 'n': // 2 strings to match.
			if (memcmp(BuiltinName.data()+22, "bits", 4))
			break;
			switch (BuiltinName[26]) {
			default: break;
			case 'c': // 1 string to match.
			if (memcmp(BuiltinName.data()+27, "lr", 2))
			break;
			return Intrinsic::hexagon_C4_nbitsclr; // "__builtin_HEXAG
			ON_C4_nbitsclr"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+27, "et", 2))
			break;
			return Intrinsic::hexagon_C4_nbitsset; // "__builtin_HEXAG
			ON_C4_nbitsset"
			}
	break;		break;
	return Intrinsic::hexagon_C2_xor; // "__builtin_HEXAGON_C2_xo		}
	r"		break;
	}		}
	break;		break;
	case 'S': // 5 strings to match.		case 'F': // 8 strings to match.
	if (memcmp(BuiltinName.data()+19, "2_c", 3))		if (memcmp(BuiltinName.data()+19, "2_", 2))
	break;		break;
	switch (BuiltinName[22]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'l': // 3 strings to match.		case 'd': // 4 strings to match.
	switch (BuiltinName[23]) {		if (memcmp(BuiltinName.data()+22, "ff", 2))
			break;
			switch (BuiltinName[24]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'i': // 3 strings to match.
	return Intrinsic::hexagon_S2_cl0; // "__builtin_HEXAGON_S2_cl		if (memcmp(BuiltinName.data()+25, "xup", 3))
	0"		break;
	case '1': // 1 string to match.		switch (BuiltinName[28]) {
	return Intrinsic::hexagon_S2_cl1; // "__builtin_HEXAGON_S2_cl		default: break;
	1"		case 'd': // 1 string to match.
	case 'b': // 1 string to match.		return Intrinsic::hexagon_F2_dffixupd; // "__builtin_HEXAG
	return Intrinsic::hexagon_S2_clb; // "__builtin_HEXAGON_S2_cl		ON_F2_dffixupd"
	b"		case 'n': // 1 string to match.
			return Intrinsic::hexagon_F2_dffixupn; // "__builtin_HEXAG
			ON_F2_dffixupn"
			case 'r': // 1 string to match.
			return Intrinsic::hexagon_F2_dffixupr; // "__builtin_HEXAG
			ON_F2_dffixupr"
			}
			break;
			case 'm': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "a_sc", 4))
			break;
			return Intrinsic::hexagon_F2_dffma_sc; // "__builtin_HEXAG
			ON_F2_dffma_sc"
	}		}
	break;		break;
	case 't': // 2 strings to match.		case 's': // 4 strings to match.
	switch (BuiltinName[23]) {		if (memcmp(BuiltinName.data()+22, "ff", 2))
			break;
			switch (BuiltinName[24]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'i': // 3 strings to match.
	return Intrinsic::hexagon_S2_ct0; // "__builtin_HEXAGON_S2_ct		if (memcmp(BuiltinName.data()+25, "xup", 3))
	0"		break;
	case '1': // 1 string to match.		switch (BuiltinName[28]) {
	return Intrinsic::hexagon_S2_ct1; // "__builtin_HEXAGON_S2_ct		default: break;
	1"		case 'd': // 1 string to match.
			return Intrinsic::hexagon_F2_sffixupd; // "__builtin_HEXAG
			ON_F2_sffixupd"
			case 'n': // 1 string to match.
			return Intrinsic::hexagon_F2_sffixupn; // "__builtin_HEXAG
			ON_F2_sffixupn"
			case 'r': // 1 string to match.
			return Intrinsic::hexagon_F2_sffixupr; // "__builtin_HEXAG
			ON_F2_sffixupr"
			}
			break;
			case 'm': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "a_sc", 4))
			break;
			return Intrinsic::hexagon_F2_sffma_sc; // "__builtin_HEXAG
			ON_F2_sffma_sc"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'M': // 29 strings to match.
	break;
	case 25: // 42 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
	break;
	switch (BuiltinName[18]) {
	default: break;
	case 'A': // 26 strings to match.
	switch (BuiltinName[19]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case '2': // 24 strings to match.		case '2': // 18 strings to match.
	if (BuiltinName[20] != '_')		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'a': // 6 strings to match.		case 'c': // 10 strings to match.
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'm': // 8 strings to match.
	if (memcmp(BuiltinName.data()+23, "sp", 2))
	break;
	return Intrinsic::hexagon_A2_absp; // "__builtin_HEXAGON_A2_ab
	sp"
	case 'd': // 2 strings to match.
	if (BuiltinName[23] != 'd')
	break;
	switch (BuiltinName[24]) {
	default: break;
	case 'i': // 1 string to match.
	return Intrinsic::hexagon_A2_addi; // "__builtin_HEXAG
	ON_A2_addi"
	case 'p': // 1 string to match.
	return Intrinsic::hexagon_A2_addp; // "__builtin_HEXAG
	ON_A2_addp"
	}
	break;
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "dp", 2))
	break;
	return Intrinsic::hexagon_A2_andp; // "__builtin_HEXAGON_A2_an
	dp"
	case 's': // 2 strings to match.
	switch (BuiltinName[23]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'a': // 4 strings to match.
	if (BuiltinName[24] != 'h')		if (BuiltinName[24] != 'c')
	break;		break;
	return Intrinsic::hexagon_A2_aslh; // "__builtin_HEXAG		switch (BuiltinName[25]) {
	ON_A2_aslh"		default: break;
	case 'r': // 1 string to match.		case 'i': // 1 string to match.
	if (BuiltinName[24] != 'h')		if (memcmp(BuiltinName.data()+26, "_s0", 3))
			break;
			return Intrinsic::hexagon_M2_cmaci_s0; // "__builtin_HEXAG
			ON_M2_cmaci_s0"
			case 'r': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "_s0", 3))
			break;
			return Intrinsic::hexagon_M2_cmacr_s0; // "__builtin_HEXAG
			ON_M2_cmacr_s0"
			case 's': // 2 strings to match.
			if (memcmp(BuiltinName.data()+26, "_s", 2))
			break;
			switch (BuiltinName[28]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_cmacs_s0; // "__built
			in_HEXAGON_M2_cmacs_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_cmacs_s1; // "__built
			in_HEXAGON_M2_cmacs_s1"
			}
	break;		break;
	return Intrinsic::hexagon_A2_asrh; // "__builtin_HEXAG		}
	ON_A2_asrh"		break;
	}		case 'p': // 4 strings to match.
	break;		if (BuiltinName[24] != 'y')
	}		break;
	break;		switch (BuiltinName[25]) {
	case 'm': // 4 strings to match.		default: break;
	switch (BuiltinName[22]) {		case 'i': // 1 string to match.
	default: break;		if (memcmp(BuiltinName.data()+26, "_s0", 3))
	case 'a': // 2 strings to match.		break;
	if (BuiltinName[23] != 'x')		return Intrinsic::hexagon_M2_cmpyi_s0; // "__builtin_HEXAG
			ON_M2_cmpyi_s0"
			case 'r': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "_s0", 3))
			break;
			return Intrinsic::hexagon_M2_cmpyr_s0; // "__builtin_HEXAG
			ON_M2_cmpyr_s0"
			case 's': // 2 strings to match.
			if (memcmp(BuiltinName.data()+26, "_s", 2))
			break;
			switch (BuiltinName[28]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_cmpys_s0; // "__built
			in_HEXAGON_M2_cmpys_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_cmpys_s1; // "__built
			in_HEXAGON_M2_cmpys_s1"
			}
			break;
			}
	break;		break;
	switch (BuiltinName[24]) {
	default: break;
	case 'p': // 1 string to match.
	return Intrinsic::hexagon_A2_maxp; // "__builtin_HEXAG
	ON_A2_maxp"
	case 'u': // 1 string to match.
	return Intrinsic::hexagon_A2_maxu; // "__builtin_HEXAG
	ON_A2_maxu"
	}		}
	break;		break;
	case 'i': // 2 strings to match.		case 'n': // 2 strings to match.
	if (BuiltinName[23] != 'n')		if (memcmp(BuiltinName.data()+23, "acs_s", 5))
	break;		break;
	switch (BuiltinName[24]) {		switch (BuiltinName[28]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_A2_minp; // "__builtin_HEXAG		return Intrinsic::hexagon_M2_cnacs_s0; // "__builtin_HEXAG
	ON_A2_minp"		ON_M2_cnacs_s0"
	case 'u': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_A2_minu; // "__builtin_HEXAG		return Intrinsic::hexagon_M2_cnacs_s1; // "__builtin_HEXAG
	ON_A2_minu"		ON_M2_cnacs_s1"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'n': // 2 strings to match.		case 'm': // 5 strings to match.
	switch (BuiltinName[22]) {
	default: break;
	case 'e': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "gp", 2))
	break;
	return Intrinsic::hexagon_A2_negp; // "__builtin_HEXAGON_A2_ne
	gp"
	case 'o': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "tp", 2))
	break;
	return Intrinsic::hexagon_A2_notp; // "__builtin_HEXAGON_A2_no
	tp"
	}
	break;
	case 'o': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "rir", 3))
	break;
	return Intrinsic::hexagon_A2_orir; // "__builtin_HEXAGON_A2_or
	ir"
	case 's': // 7 strings to match.
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'm': // 4 strings to match.
	if (BuiltinName[23] != 't')		if (memcmp(BuiltinName.data()+23, "py", 2))
	break;		break;
	switch (BuiltinName[24]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'h': // 2 strings to match.
	return Intrinsic::hexagon_A2_satb; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+26, "_s", 2))
	ON_A2_satb"		break;
	case 'h': // 1 string to match.		switch (BuiltinName[28]) {
	return Intrinsic::hexagon_A2_sath; // "__builtin_HEXAG		default: break;
	ON_A2_sath"		case '0': // 1 string to match.
	}		return Intrinsic::hexagon_M2_mmpyh_s0; // "__builtin_HEXAG
	break;		ON_M2_mmpyh_s0"
	case 'u': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "bp", 2))		return Intrinsic::hexagon_M2_mmpyh_s1; // "__builtin_HEXAG
	break;		ON_M2_mmpyh_s1"
	return Intrinsic::hexagon_A2_subp; // "__builtin_HEXAGON_A2_su		}
	bp"
	case 'w': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "iz", 2))
	break;		break;
	return Intrinsic::hexagon_A2_swiz; // "__builtin_HEXAGON_A2_sw		case 'l': // 2 strings to match.
	iz"		if (memcmp(BuiltinName.data()+26, "_s", 2))
	case 'x': // 3 strings to match.		break;
	if (BuiltinName[23] != 't')		switch (BuiltinName[28]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mmpyl_s0; // "__builtin_HEXAG
			ON_M2_mmpyl_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mmpyl_s1; // "__builtin_HEXAG
			ON_M2_mmpyl_s1"
			}
	break;		break;
	switch (BuiltinName[24]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::hexagon_A2_sxtb; // "__builtin_HEXAG
	ON_A2_sxtb"
	case 'h': // 1 string to match.
	return Intrinsic::hexagon_A2_sxth; // "__builtin_HEXAG
	ON_A2_sxth"
	case 'w': // 1 string to match.
	return Intrinsic::hexagon_A2_sxtw; // "__builtin_HEXAG
	ON_A2_sxtw"
	}		}
	break;		break;
			case 'p': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "ysu_up", 6))
			break;
			return Intrinsic::hexagon_M2_mpysu_up; // "__builtin_HEXAG
			ON_M2_mpysu_up"
	}		}
	break;		break;
	case 't': // 1 string to match.		case 'v': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "frp", 3))		if (memcmp(BuiltinName.data()+22, "rm", 2))
	break;
	return Intrinsic::hexagon_A2_tfrp; // "__builtin_HEXAGON_A2_tf
	rp"
	case 'x': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "orp", 3))
	break;
	return Intrinsic::hexagon_A2_xorp; // "__builtin_HEXAGON_A2_xo
	rp"
	case 'z': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "xt", 2))
	break;		break;
	switch (BuiltinName[24]) {		switch (BuiltinName[24]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'a': // 1 string to match.
	return Intrinsic::hexagon_A2_zxtb; // "__builtin_HEXAGON_A2_zx		if (memcmp(BuiltinName.data()+25, "c_s0", 4))
	tb"		break;
	case 'h': // 1 string to match.		return Intrinsic::hexagon_M2_vrmac_s0; // "__builtin_HEXAG
	return Intrinsic::hexagon_A2_zxth; // "__builtin_HEXAGON_A2_zx		ON_M2_vrmac_s0"
	th"		case 'p': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "y_s0", 4))
			break;
			return Intrinsic::hexagon_M2_vrmpy_s0; // "__builtin_HEXAG
			ON_M2_vrmpy_s0"
	}		}
	break;		break;
			case 'x': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "or_xacc", 7))
			break;
			return Intrinsic::hexagon_M2_xor_xacc; // "__builtin_HEXAG
			ON_M2_xor_xacc"
	}		}
	break;		break;
	case '4': // 2 strings to match.		case '4': // 5 strings to match.
	if (BuiltinName[20] != '_')		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "ndn", 3))		if (memcmp(BuiltinName.data()+22, "nd_andn", 7))
	break;		break;
	return Intrinsic::hexagon_A4_andn; // "__builtin_HEXAGON_A4_an		return Intrinsic::hexagon_M4_and_andn; // "__builtin_HEXAG
	dn"		ON_M4_and_andn"
	case 'o': // 1 string to match.		case 'c': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "rnp", 3))		if (memcmp(BuiltinName.data()+22, "mpy", 3))
	break;		break;
	return Intrinsic::hexagon_A4_ornp; // "__builtin_HEXAGON_A4_or		switch (BuiltinName[25]) {
	np"		default: break;
	}		case 'i': // 1 string to match.
	break;		if (memcmp(BuiltinName.data()+26, "_wh", 3))
	}		break;
	break;		return Intrinsic::hexagon_M4_cmpyi_wh; // "__builtin_HEXAG
	case 'C': // 5 strings to match.		ON_M4_cmpyi_wh"
	if (memcmp(BuiltinName.data()+19, "2_", 2))		case 'r': // 1 string to match.
	break;		if (memcmp(BuiltinName.data()+26, "_wh", 3))
	switch (BuiltinName[21]) {		break;
	default: break;		return Intrinsic::hexagon_M4_cmpyr_wh; // "__builtin_HEXAG
	case 'a': // 3 strings to match.		ON_M4_cmpyr_wh"
	switch (BuiltinName[22]) {		}
	default: break;		break;
	case 'l': // 1 string to match.		case 'x': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "l8", 2))		if (memcmp(BuiltinName.data()+22, "or_", 3))
	break;		break;
	return Intrinsic::hexagon_C2_all8; // "__builtin_HEXAGON_C2_al		switch (BuiltinName[25]) {
	l8"
	case 'n': // 2 strings to match.
	switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'a': // 1 string to match.
	if (BuiltinName[24] != 'n')		if (memcmp(BuiltinName.data()+26, "ndn", 3))
	break;		break;
	return Intrinsic::hexagon_C2_andn; // "__builtin_HEXAGON_C2_an		return Intrinsic::hexagon_M4_xor_andn; // "__builtin_HEXAG
	dn"		ON_M4_xor_andn"
	case 'y': // 1 string to match.		case 'x': // 1 string to match.
	if (BuiltinName[24] != '8')		if (memcmp(BuiltinName.data()+26, "acc", 3))
	break;		break;
	return Intrinsic::hexagon_C2_any8; // "__builtin_HEXAGON_C2_an y8"		return Intrinsic::hexagon_M4_xor_xacc; // "__builtin_HEXAG ON_M4_xor_xacc"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'm': // 1 string to match.		case '5': // 6 strings to match.
	if (memcmp(BuiltinName.data()+22, "ask", 3))		if (memcmp(BuiltinName.data()+20, "_v", 2))
	break;
	return Intrinsic::hexagon_C2_mask; // "__builtin_HEXAGON_C2_ma
	sk"
	case 'v': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "mux", 3))
	break;
	return Intrinsic::hexagon_C2_vmux; // "__builtin_HEXAGON_C2_vm
	ux"
	}
	break;
	case 'M': // 3 strings to match.
	if (memcmp(BuiltinName.data()+19, "2_", 2))
	break;
	switch (BuiltinName[21]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "cci", 3))
	break;		break;
	return Intrinsic::hexagon_M2_acci; // "__builtin_HEXAGON_M2_ac
	ci"
	case 'm': // 2 strings to match.
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'd': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "ci", 2))		if (BuiltinName[23] != 'm')
	break;
	return Intrinsic::hexagon_M2_maci; // "__builtin_HEXAGON_M2_ma
	ci"
	case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "yi", 2))
	break;		break;
	return Intrinsic::hexagon_M2_mpyi; // "__builtin_HEXAGON_M2_mp		switch (BuiltinName[24]) {
	yi"		default: break;
	}		case 'a': // 1 string to match.
	break;		if (memcmp(BuiltinName.data()+25, "cbsu", 4))
	}		break;
	break;		return Intrinsic::hexagon_M5_vdmacbsu; // "__builtin_HEXAG
	case 'S': // 8 strings to match.		ON_M5_vdmacbsu"
	switch (BuiltinName[19]) {		case 'p': // 1 string to match.
	default: break;		if (memcmp(BuiltinName.data()+25, "ybsu", 4))
	case '2': // 7 strings to match.		break;
	if (BuiltinName[20] != '_')		return Intrinsic::hexagon_M5_vdmpybsu; // "__builtin_HEXAG
			ON_M5_vdmpybsu"
			}
	break;		break;
	switch (BuiltinName[21]) {		case 'r': // 4 strings to match.
	default: break;		if (BuiltinName[23] != 'm')
	case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "rev", 3))
	break;		break;
	return Intrinsic::hexagon_S2_brev; // "__builtin_HEXAGON_S2_br		switch (BuiltinName[24]) {
	ev"
	case 'c': // 5 strings to match.
	switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'l': // 3 strings to match.		case 'a': // 2 strings to match.
	switch (BuiltinName[23]) {		if (memcmp(BuiltinName.data()+25, "cb", 2))
			break;
			switch (BuiltinName[27]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 's': // 1 string to match.
	if (BuiltinName[24] != 'p')		if (BuiltinName[28] != 'u')
	break;
	return Intrinsic::hexagon_S2_cl0p; // "__builtin_HEXAG
	ON_S2_cl0p"
	case '1': // 1 string to match.
	if (BuiltinName[24] != 'p')
	break;		break;
	return Intrinsic::hexagon_S2_cl1p; // "__builtin_HEXAG		return Intrinsic::hexagon_M5_vrmacbsu; // "__builtin_HEXAG
	ON_S2_cl1p"		ON_M5_vrmacbsu"
	case 'b': // 1 string to match.		case 'u': // 1 string to match.
	if (BuiltinName[24] != 'p')		if (BuiltinName[28] != 'u')
	break;		break;
	return Intrinsic::hexagon_S2_clbp; // "__builtin_HEXAG ON_S2_clbp"		return Intrinsic::hexagon_M5_vrmacbuu; // "__builtin_HEXAG ON_M5_vrmacbuu"
	}		}
	break;		break;
	case 't': // 2 strings to match.		case 'p': // 2 strings to match.
	switch (BuiltinName[23]) {		if (memcmp(BuiltinName.data()+25, "yb", 2))
			break;
			switch (BuiltinName[27]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 's': // 1 string to match.
	if (BuiltinName[24] != 'p')		if (BuiltinName[28] != 'u')
	break;		break;
	return Intrinsic::hexagon_S2_ct0p; // "__builtin_HEXAG		return Intrinsic::hexagon_M5_vrmpybsu; // "__builtin_HEXAG
	ON_S2_ct0p"		ON_M5_vrmpybsu"
	case '1': // 1 string to match.		case 'u': // 1 string to match.
	if (BuiltinName[24] != 'p')		if (BuiltinName[28] != 'u')
	break;		break;
	return Intrinsic::hexagon_S2_ct1p; // "__builtin_HEXAG ON_S2_ct1p"		return Intrinsic::hexagon_M5_vrmpybuu; // "__builtin_HEXAG ON_M5_vrmpybuu"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "fsp", 3))
	break;
	return Intrinsic::hexagon_S2_lfsp; // "__builtin_HEXAGON_S2_lf
	sp"
	}		}
	break;		break;
	case '4': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "_lsli", 5))
	break;
	return Intrinsic::hexagon_S4_lsli; // "__builtin_HEXAGON_S4_ls
	li"
	}		}
	break;		break;
	}		case 'S': // 35 strings to match.
	break;		switch (BuiltinName[19]) {
	case 26: // 58 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_", 10))
	break;
	switch (BuiltinName[10]) {
	default: break;
	case 'H': // 57 strings to match.
	if (memcmp(BuiltinName.data()+11, "EXAGON_", 7))
	break;
	switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'A': // 27 strings to match.		case '2': // 31 strings to match.
	switch (BuiltinName[19]) {		if (BuiltinName[20] != '_')
			break;
			switch (BuiltinName[21]) {
	default: break;		default: break;
	case '2': // 26 strings to match.		case 'a': // 8 strings to match.
	if (BuiltinName[20] != '_')		if (BuiltinName[22] != 's')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'l': // 4 strings to match.
	switch (BuiltinName[22]) {		if (BuiltinName[24] != '_')
	default: break;		break;
	case 'd': // 1 string to match.		switch (BuiltinName[25]) {
	if (memcmp(BuiltinName.data()+23, "dsp", 3))
	break;
	return Intrinsic::hexagon_A2_addsp; // "__builtin_HEXAG
	ON_A2_addsp"
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "dir", 3))
	break;
	return Intrinsic::hexagon_A2_andir; // "__builtin_HEXAG
	ON_A2_andir"
	}
	break;
	case 'm': // 2 strings to match.
	switch (BuiltinName[22]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "xup", 3))
	break;
	return Intrinsic::hexagon_A2_maxup; // "__builtin_HEXAG
	ON_A2_maxup"
	case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "nup", 3))
	break;
	return Intrinsic::hexagon_A2_minup; // "__builtin_HEXAG
	ON_A2_minup"
	}
	break;
	case 's': // 3 strings to match.
	switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'i': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "tu", 2))		if (memcmp(BuiltinName.data()+26, "_v", 2))
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[28]) {
	default: break;		default: break;
	case 'b': // 1 string to match.
	return Intrinsic::hexagon_A2_satub; // "__builtin_HEXAG
	ON_A2_satub"
	case 'h': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::hexagon_A2_satuh; // "__builtin_HEXAG		return Intrinsic::hexagon_S2_asl_i_vh; // "__builtin_HEXAG
	ON_A2_satuh"		ON_S2_asl_i_vh"
			case 'w': // 1 string to match.
			return Intrinsic::hexagon_S2_asl_i_vw; // "__builtin_HEXAG
			ON_S2_asl_i_vw"
	}		}
	break;		break;
	case 'u': // 1 string to match.		case 'r': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "bri", 3))		if (memcmp(BuiltinName.data()+26, "_v", 2))
	break;		break;
	return Intrinsic::hexagon_A2_subri; // "__builtin_HEXAG		switch (BuiltinName[28]) {
	ON_A2_subri"		default: break;
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_S2_asl_r_vh; // "__builtin_HEXAG
			ON_S2_asl_r_vh"
			case 'w': // 1 string to match.
			return Intrinsic::hexagon_S2_asl_r_vw; // "__builtin_HEXAG
			ON_S2_asl_r_vw"
			}
			break;
	}		}
	break;		break;
	case 't': // 4 strings to match.		case 'r': // 4 strings to match.
	if (memcmp(BuiltinName.data()+22, "fr", 2))		if (BuiltinName[24] != '_')
	break;		break;
	switch (BuiltinName[24]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'i': // 2 strings to match.		case 'i': // 2 strings to match.
	switch (BuiltinName[25]) {		if (memcmp(BuiltinName.data()+26, "_v", 2))
			break;
			switch (BuiltinName[28]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::hexagon_A2_tfrih; // "__builtin_HEXAG		return Intrinsic::hexagon_S2_asr_i_vh; // "__builtin_HEXAG
	ON_A2_tfrih"		ON_S2_asr_i_vh"
	case 'l': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::hexagon_A2_tfril; // "__builtin_HEXAG		return Intrinsic::hexagon_S2_asr_i_vw; // "__builtin_HEXAG
	ON_A2_tfril"		ON_S2_asr_i_vw"
	}		}
	break;		break;
	case 'p': // 1 string to match.		case 'r': // 2 strings to match.
	if (BuiltinName[25] != 'i')		if (memcmp(BuiltinName.data()+26, "_v", 2))
	break;
	return Intrinsic::hexagon_A2_tfrpi; // "__builtin_HEXAG
	ON_A2_tfrpi"
	case 's': // 1 string to match.
	if (BuiltinName[25] != 'i')
	break;		break;
	return Intrinsic::hexagon_A2_tfrsi; // "__builtin_HEXAG		switch (BuiltinName[28]) {
	ON_A2_tfrsi"		default: break;
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_S2_asr_r_vh; // "__builtin_HEXAG
			ON_S2_asr_r_vh"
			case 'w': // 1 string to match.
			return Intrinsic::hexagon_S2_asr_r_vw; // "__builtin_HEXAG
			ON_S2_asr_r_vw"
			}
			break;
	}		}
	break;		break;
	case 'v': // 15 strings to match.		}
	switch (BuiltinName[22]) {		break;
			case 'c': // 2 strings to match.
			if (memcmp(BuiltinName.data()+22, "lrbit_", 6))
			break;
			switch (BuiltinName[28]) {
			default: break;
			case 'i': // 1 string to match.
			return Intrinsic::hexagon_S2_clrbit_i; // "__builtin_HEXAG
			ON_S2_clrbit_i"
			case 'r': // 1 string to match.
			return Intrinsic::hexagon_S2_clrbit_r; // "__builtin_HEXAG
			ON_S2_clrbit_r"
			}
			break;
			case 'e': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "xtractu", 7))
			break;
			return Intrinsic::hexagon_S2_extractu; // "__builtin_HEXAG
			ON_S2_extractu"
			case 'l': // 6 strings to match.
			if (BuiltinName[22] != 's')
			break;
			switch (BuiltinName[23]) {
			default: break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+24, "_r_v", 4))
			break;
			switch (BuiltinName[28]) {
	default: break;		default: break;
	case 'a': // 6 strings to match.		case 'h': // 1 string to match.
	switch (BuiltinName[23]) {		return Intrinsic::hexagon_S2_lsl_r_vh; // "__builtin_HEXAG
	default: break;		ON_S2_lsl_r_vh"
	case 'b': // 2 strings to match.		case 'w': // 1 string to match.
	if (BuiltinName[24] != 's')		return Intrinsic::hexagon_S2_lsl_r_vw; // "__builtin_HEXAG
	break;		ON_S2_lsl_r_vw"
	switch (BuiltinName[25]) {		}
	default: break;		break;
	case 'h': // 1 string to match.		case 'r': // 4 strings to match.
	return Intrinsic::hexagon_A2_vabsh; // "__builtin_HEXAG		if (BuiltinName[24] != '_')
	ON_A2_vabsh"
	case 'w': // 1 string to match.
	return Intrinsic::hexagon_A2_vabsw; // "__builtin_HEXAG
	ON_A2_vabsw"
	}
	break;
	case 'd': // 2 strings to match.
	if (BuiltinName[24] != 'd')
	break;
	switch (BuiltinName[25]) {
	default: break;
	case 'h': // 1 string to match.
	return Intrinsic::hexagon_A2_vaddh; // "__builtin_HEXAG
	ON_A2_vaddh"
	case 'w': // 1 string to match.
	return Intrinsic::hexagon_A2_vaddw; // "__builtin_HEXAG
	ON_A2_vaddw"
	}
	break;
	case 'v': // 2 strings to match.
	if (BuiltinName[24] != 'g')
	break;
	switch (BuiltinName[25]) {
	default: break;
	case 'h': // 1 string to match.
	return Intrinsic::hexagon_A2_vavgh; // "__builtin_HEXAG
	ON_A2_vavgh"
	case 'w': // 1 string to match.
	return Intrinsic::hexagon_A2_vavgw; // "__builtin_HEXAG
	ON_A2_vavgw"
	}
	break;
	}
	break;		break;
	case 'c': // 1 string to match.		switch (BuiltinName[25]) {
	if (memcmp(BuiltinName.data()+23, "onj", 3))		default: break;
			case 'i': // 2 strings to match.
			if (memcmp(BuiltinName.data()+26, "_v", 2))
	break;		break;
	return Intrinsic::hexagon_A2_vconj; // "__builtin_HEXAG		switch (BuiltinName[28]) {
	ON_A2_vconj"
	case 'm': // 6 strings to match.
	switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'a': // 3 strings to match.		case 'h': // 1 string to match.
	if (BuiltinName[24] != 'x')		return Intrinsic::hexagon_S2_lsr_i_vh; // "__builtin_HEXAG
	break;		ON_S2_lsr_i_vh"
	switch (BuiltinName[25]) {		case 'w': // 1 string to match.
	default: break;		return Intrinsic::hexagon_S2_lsr_i_vw; // "__builtin_HEXAG
	case 'b': // 1 string to match.		ON_S2_lsr_i_vw"
	return Intrinsic::hexagon_A2_vmaxb; // "__builtin_HEXAG
	ON_A2_vmaxb"
	case 'h': // 1 string to match.
	return Intrinsic::hexagon_A2_vmaxh; // "__builtin_HEXAG
	ON_A2_vmaxh"
	case 'w': // 1 string to match.
	return Intrinsic::hexagon_A2_vmaxw; // "__builtin_HEXAG
	ON_A2_vmaxw"
	}
	break;
	case 'i': // 3 strings to match.
	if (BuiltinName[24] != 'n')
	break;
	switch (BuiltinName[25]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::hexagon_A2_vminb; // "__builtin_HEXAG
	ON_A2_vminb"
	case 'h': // 1 string to match.
	return Intrinsic::hexagon_A2_vminh; // "__builtin_HEXAG
	ON_A2_vminh"
	case 'w': // 1 string to match.
	return Intrinsic::hexagon_A2_vminw; // "__builtin_HEXAG
	ON_A2_vminw"
	}
	break;
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 'r': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "ub", 2))		if (memcmp(BuiltinName.data()+26, "_v", 2))
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[28]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::hexagon_A2_vsubh; // "__builtin_HEXAG ON_A2_vsubh"		return Intrinsic::hexagon_S2_lsr_r_vh; // "__builtin_HEXAG ON_S2_lsr_r_vh"
	case 'w': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::hexagon_A2_vsubw; // "__builtin_HEXAG ON_A2_vsubw"		return Intrinsic::hexagon_S2_lsr_r_vw; // "__builtin_HEXAG ON_S2_lsr_r_vw"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case '4': // 1 string to match.		case 's': // 3 strings to match.
	if (memcmp(BuiltinName.data()+20, "_andnp", 6))		switch (BuiltinName[22]) {
			default: break;
			case 'e': // 2 strings to match.
			if (memcmp(BuiltinName.data()+23, "tbit_", 5))
			break;
			switch (BuiltinName[28]) {
			default: break;
			case 'i': // 1 string to match.
			return Intrinsic::hexagon_S2_setbit_i; // "__builtin_HEXAG
			ON_S2_setbit_i"
			case 'r': // 1 string to match.
			return Intrinsic::hexagon_S2_setbit_r; // "__builtin_HEXAG
			ON_S2_setbit_r"
			}
	break;		break;
	return Intrinsic::hexagon_A4_andnp; // "__builtin_HEXAGON_A4_an		case 'v': // 1 string to match.
	dnp"		if (memcmp(BuiltinName.data()+23, "sathub", 6))
	}		break;
	break;		return Intrinsic::hexagon_S2_svsathub; // "__builtin_HEXAG
	case 'C': // 9 strings to match.		ON_S2_svsathub"
	switch (BuiltinName[19]) {		}
	default: break;		break;
	case '2': // 8 strings to match.		case 't': // 2 strings to match.
	if (BuiltinName[20] != '_')		if (memcmp(BuiltinName.data()+22, "stbit_", 6))
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[28]) {
	default: break;		default: break;
	case 'c': // 3 strings to match.		case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "mp", 2))		return Intrinsic::hexagon_S2_tstbit_i; // "__builtin_HEXAG
			ON_S2_tstbit_i"
			case 'r': // 1 string to match.
			return Intrinsic::hexagon_S2_tstbit_r; // "__builtin_HEXAG
			ON_S2_tstbit_r"
			}
			break;
			case 'v': // 9 strings to match.
			switch (BuiltinName[22]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(BuiltinName.data()+23, "lign", 4))
	break;		break;
	switch (BuiltinName[24]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'i': // 1 string to match.
	if (BuiltinName[25] != 'q')		if (BuiltinName[28] != 'b')
	break;
	return Intrinsic::hexagon_C2_cmpeq; // "__builtin_HEXAG
	ON_C2_cmpeq"
	case 'g': // 1 string to match.
	if (BuiltinName[25] != 't')
	break;		break;
	return Intrinsic::hexagon_C2_cmpgt; // "__builtin_HEXAG		return Intrinsic::hexagon_S2_valignib; // "__builtin_HEXAG
	ON_C2_cmpgt"		ON_S2_valignib"
	case 'l': // 1 string to match.		case 'r': // 1 string to match.
	if (BuiltinName[25] != 't')		if (BuiltinName[28] != 'b')
	break;		break;
	return Intrinsic::hexagon_C2_cmplt; // "__builtin_HEXAG ON_C2_cmplt"		return Intrinsic::hexagon_S2_valignrb; // "__builtin_HEXAG ON_S2_valignrb"
	}		}
	break;		break;
	case 'm': // 3 strings to match.		case 'c': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "ux", 2))		if (memcmp(BuiltinName.data()+23, "rotate", 6))
			break;
			return Intrinsic::hexagon_S2_vcrotate; // "__builtin_HEXAG
			ON_S2_vcrotate"
			case 's': // 2 strings to match.
			if (memcmp(BuiltinName.data()+23, "platr", 5))
			break;
			switch (BuiltinName[28]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::hexagon_S2_vsplatrb; // "__builtin_HEXAG
			ON_S2_vsplatrb"
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_S2_vsplatrh; // "__builtin_HEXAG
			ON_S2_vsplatrh"
			}
			break;
			case 't': // 4 strings to match.
			if (memcmp(BuiltinName.data()+23, "run", 3))
			break;
			switch (BuiltinName[26]) {
			default: break;
			case 'e': // 2 strings to match.
			switch (BuiltinName[27]) {
			default: break;
			case 'h': // 1 string to match.
			if (BuiltinName[28] != 'b')
			break;
			return Intrinsic::hexagon_S2_vtrunehb; // "__builtin_HEXAG
			ON_S2_vtrunehb"
			case 'w': // 1 string to match.
			if (BuiltinName[28] != 'h')
			break;
			return Intrinsic::hexagon_S2_vtrunewh; // "__builtin_HEXAG
			ON_S2_vtrunewh"
			}
	break;		break;
	switch (BuiltinName[24]) {		case 'o': // 2 strings to match.
	default: break;		switch (BuiltinName[27]) {
	case 'i': // 2 strings to match.
	switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'i': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::hexagon_C2_muxii; // "__builtin_HEXAG		if (BuiltinName[28] != 'b')
	ON_C2_muxii"		break;
	case 'r': // 1 string to match.		return Intrinsic::hexagon_S2_vtrunohb; // "__builtin_HEXAG
	return Intrinsic::hexagon_C2_muxir; // "__builtin_HEXAG		ON_S2_vtrunohb"
	ON_C2_muxir"		case 'w': // 1 string to match.
			if (BuiltinName[28] != 'h')
			break;
			return Intrinsic::hexagon_S2_vtrunowh; // "__builtin_HEXAG
			ON_S2_vtrunowh"
	}		}
	break;		break;
	case 'r': // 1 string to match.
	if (BuiltinName[25] != 'i')
	break;
	return Intrinsic::hexagon_C2_muxri; // "__builtin_HEXAG
	ON_C2_muxri"
	}		}
	break;		break;
	case 't': // 2 strings to match.		}
	if (memcmp(BuiltinName.data()+22, "fr", 2))		break;
	break;		}
	switch (BuiltinName[24]) {		break;
	default: break;		case '4': // 4 strings to match.
	case 'p': // 1 string to match.		if (BuiltinName[20] != '_')
	if (BuiltinName[25] != 'r')		break;
	break;		switch (BuiltinName[21]) {
	return Intrinsic::hexagon_C2_tfrpr; // "__builtin_HEXAG		default: break;
	ON_C2_tfrpr"		case 'c': // 2 strings to match.
	case 'r': // 1 string to match.		if (memcmp(BuiltinName.data()+22, "lbp", 3))
	if (BuiltinName[25] != 'p')
	break;
	return Intrinsic::hexagon_C2_tfrrp; // "__builtin_HEXAG
	ON_C2_tfrrp"
	}
	break;		break;
			switch (BuiltinName[25]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "ddi", 3))
			break;
			return Intrinsic::hexagon_S4_clbpaddi; // "__builtin_HEXAG
			ON_S4_clbpaddi"
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "orm", 3))
			break;
			return Intrinsic::hexagon_S4_clbpnorm; // "__builtin_HEXAG
			ON_S4_clbpnorm"
	}		}
	break;		break;
	case '4': // 1 string to match.		case 'e': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "_or_or", 6))		if (memcmp(BuiltinName.data()+22, "xtractp", 7))
	break;		break;
	return Intrinsic::hexagon_C4_or_or; // "__builtin_HEXAGON_C4_or		return Intrinsic::hexagon_S4_extractp; // "__builtin_HEXAG
	_or"		ON_S4_extractp"
			case 'o': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "r_andix", 7))
			break;
			return Intrinsic::hexagon_S4_or_andix; // "__builtin_HEXAG
			ON_S4_or_andix"
	}		}
	break;		break;
	case 'F': // 14 strings to match.		}
	if (memcmp(BuiltinName.data()+19, "2_", 2))		break;
			}
			break;
			case 30: // 81 strings to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
			break;
			switch (BuiltinName[18]) {
			default: break;
			case 'A': // 11 strings to match.
			switch (BuiltinName[19]) {
			default: break;
			case '2': // 3 strings to match.
			if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'd': // 7 strings to match.		case 'c': // 1 string to match.
	if (BuiltinName[22] != 'f')		if (memcmp(BuiltinName.data()+22, "ombineii", 8))
	break;		break;
	switch (BuiltinName[23]) {		return Intrinsic::hexagon_A2_combineii; // "__builtin_HEXAG
			ON_A2_combineii"
			case 'v': // 2 strings to match.
			switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "dd", 2))		if (memcmp(BuiltinName.data()+23, "ddb_map", 7))
	break;		break;
	return Intrinsic::hexagon_F2_dfadd; // "__builtin_HEXAG		return Intrinsic::hexagon_A2_vaddb_map; // "__builtin_HEXAG
	ON_F2_dfadd"		ON_A2_vaddb_map"
	case 'f': // 2 strings to match.		case 's': // 1 string to match.
	if (BuiltinName[24] != 'm')		if (memcmp(BuiltinName.data()+23, "ubb_map", 7))
	break;		break;
	switch (BuiltinName[25]) {		return Intrinsic::hexagon_A2_vsubb_map; // "__builtin_HEXAG
	default: break;		ON_A2_vsubb_map"
	case 'a': // 1 string to match.		}
	return Intrinsic::hexagon_F2_dffma; // "__builtin_HEXAG		break;
	ON_F2_dffma"		}
	case 's': // 1 string to match.		break;
	return Intrinsic::hexagon_F2_dffms; // "__builtin_HEXAG		case '4': // 8 strings to match.
	ON_F2_dffms"		if (BuiltinName[20] != '_')
	}		break;
			switch (BuiltinName[21]) {
			default: break;
			case 'b': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "itspliti", 8))
	break;		break;
	case 'm': // 3 strings to match.		return Intrinsic::hexagon_A4_bitspliti; // "__builtin_HEXAG
	switch (BuiltinName[24]) {		ON_A4_bitspliti"
			case 'c': // 4 strings to match.
			switch (BuiltinName[22]) {
			default: break;
			case 'o': // 2 strings to match.
			if (memcmp(BuiltinName.data()+23, "mbine", 5))
			break;
			switch (BuiltinName[28]) {
	default: break;		default: break;
	case 'a': // 1 string to match.
	if (BuiltinName[25] != 'x')
	break;
	return Intrinsic::hexagon_F2_dfmax; // "__builtin_HEXAG
	ON_F2_dfmax"
	case 'i': // 1 string to match.		case 'i': // 1 string to match.
	if (BuiltinName[25] != 'n')		if (BuiltinName[29] != 'r')
	break;		break;
	return Intrinsic::hexagon_F2_dfmin; // "__builtin_HEXAG		return Intrinsic::hexagon_A4_combineir; // "__builtin_HEXAG
	ON_F2_dfmin"		ON_A4_combineir"
	case 'p': // 1 string to match.		case 'r': // 1 string to match.
	if (BuiltinName[25] != 'y')		if (BuiltinName[29] != 'i')
	break;		break;
	return Intrinsic::hexagon_F2_dfmpy; // "__builtin_HEXAG ON_F2_dfmpy"		return Intrinsic::hexagon_A4_combineri; // "__builtin_HEXAG ON_A4_combineri"
	}		}
	break;		break;
	case 's': // 1 string to match.		case 'r': // 2 strings to match.
	if (memcmp(BuiltinName.data()+24, "ub", 2))		if (memcmp(BuiltinName.data()+23, "ound_r", 6))
	break;		break;
	return Intrinsic::hexagon_F2_dfsub; // "__builtin_HEXAG		switch (BuiltinName[29]) {
	ON_F2_dfsub"		default: break;
			case 'i': // 1 string to match.
			return Intrinsic::hexagon_A4_cround_ri; // "__builtin_HEXAG
			ON_A4_cround_ri"
			case 'r': // 1 string to match.
			return Intrinsic::hexagon_A4_cround_rr; // "__builtin_HEXAG
			ON_A4_cround_rr"
			}
			break;
	}		}
	break;		break;
	case 's': // 7 strings to match.		case 'v': // 3 strings to match.
	if (BuiltinName[22] != 'f')		if (memcmp(BuiltinName.data()+22, "cmp", 3))
	break;		break;
	switch (BuiltinName[23]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "dd", 2))		if (memcmp(BuiltinName.data()+26, "gtui", 4))
	break;		break;
	return Intrinsic::hexagon_F2_sfadd; // "__builtin_HEXAG		return Intrinsic::hexagon_A4_vcmpbgtui; // "__builtin_HEXAG
	ON_F2_sfadd"		ON_A4_vcmpbgtui"
	case 'f': // 2 strings to match.		case 'h': // 1 string to match.
	if (BuiltinName[24] != 'm')		if (memcmp(BuiltinName.data()+26, "gtui", 4))
	break;		break;
	switch (BuiltinName[25]) {		return Intrinsic::hexagon_A4_vcmphgtui; // "__builtin_HEXAG
			ON_A4_vcmphgtui"
			case 'w': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "gtui", 4))
			break;
			return Intrinsic::hexagon_A4_vcmpwgtui; // "__builtin_HEXAG
			ON_A4_vcmpwgtui"
			}
			break;
			}
			break;
			}
			break;
			case 'C': // 2 strings to match.
			switch (BuiltinName[19]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "_pxfer_map", 10))
			break;
			return Intrinsic::hexagon_C2_pxfer_map; // "__builtin_HEXAG
			ON_C2_pxfer_map"
			case '4': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "_nbitsclri", 10))
			break;
			return Intrinsic::hexagon_C4_nbitsclri; // "__builtin_HEXAG
			ON_C4_nbitsclri"
			}
			break;
			case 'F': // 12 strings to match.
			if (memcmp(BuiltinName.data()+19, "2_", 2))
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'c': // 8 strings to match.
			if (memcmp(BuiltinName.data()+22, "onv_", 4))
			break;
			switch (BuiltinName[26]) {
			default: break;
			case 'd': // 4 strings to match.
			switch (BuiltinName[27]) {
			default: break;
			case '2': // 2 strings to match.
			switch (BuiltinName[28]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::hexagon_F2_sffma; // "__builtin_HEXAG		if (BuiltinName[29] != 'f')
	ON_F2_sffma"		break;
			return Intrinsic::hexagon_F2_conv_d2df; // "__builtin_HEXAG
			ON_F2_conv_d2df"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	return Intrinsic::hexagon_F2_sffms; // "__builtin_HEXAG		if (BuiltinName[29] != 'f')
	ON_F2_sffms"		break;
			return Intrinsic::hexagon_F2_conv_d2sf; // "__builtin_HEXAG
			ON_F2_conv_d2sf"
	}		}
	break;		break;
	case 'm': // 3 strings to match.		case 'f': // 2 strings to match.
	switch (BuiltinName[24]) {		if (BuiltinName[28] != '2')
			break;
			switch (BuiltinName[29]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'd': // 1 string to match.
	if (BuiltinName[25] != 'x')		return Intrinsic::hexagon_F2_conv_df2d; // "__builtin_HEXAG
	break;		ON_F2_conv_df2d"
	return Intrinsic::hexagon_F2_sfmax; // "__builtin_HEXAG		case 'w': // 1 string to match.
	ON_F2_sfmax"		return Intrinsic::hexagon_F2_conv_df2w; // "__builtin_HEXAG
	case 'i': // 1 string to match.		ON_F2_conv_df2w"
	if (BuiltinName[25] != 'n')
	break;
	return Intrinsic::hexagon_F2_sfmin; // "__builtin_HEXAG
	ON_F2_sfmin"
	case 'p': // 1 string to match.
	if (BuiltinName[25] != 'y')
	break;
	return Intrinsic::hexagon_F2_sfmpy; // "__builtin_HEXAG
	ON_F2_sfmpy"
	}		}
	break;		break;
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "ub", 2))
	break;
	return Intrinsic::hexagon_F2_sfsub; // "__builtin_HEXAG
	ON_F2_sfsub"
	}		}
	break;		break;
	}		case 's': // 2 strings to match.
	break;		if (memcmp(BuiltinName.data()+27, "f2", 2))
	case 'M': // 6 strings to match.
	switch (BuiltinName[19]) {
	default: break;
	case '2': // 4 strings to match.
	if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[29]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "ccii", 4))		return Intrinsic::hexagon_F2_conv_sf2d; // "__builtin_HEXAG
	break;		ON_F2_conv_sf2d"
	return Intrinsic::hexagon_M2_accii; // "__builtin_HEXAG		case 'w': // 1 string to match.
	ON_M2_accii"		return Intrinsic::hexagon_F2_conv_sf2w; // "__builtin_HEXAG
	case 'm': // 1 string to match.		ON_F2_conv_sf2w"
	if (memcmp(BuiltinName.data()+22, "pyui", 4))
	break;
	return Intrinsic::hexagon_M2_mpyui; // "__builtin_HEXAG
	ON_M2_mpyui"
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "acci", 4))
	break;
	return Intrinsic::hexagon_M2_nacci; // "__builtin_HEXAG
	ON_M2_nacci"
	case 'v': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "mac2", 4))
	break;
	return Intrinsic::hexagon_M2_vmac2; // "__builtin_HEXAG
	ON_M2_vmac2"
	}		}
	break;		break;
	case '4': // 2 strings to match.		case 'w': // 2 strings to match.
	if (BuiltinName[20] != '_')		if (BuiltinName[27] != '2')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[28]) {
	default: break;		default: break;
	case 'o': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "r_or", 4))		if (BuiltinName[29] != 'f')
	break;		break;
	return Intrinsic::hexagon_M4_or_or; // "__builtin_HEXAG		return Intrinsic::hexagon_F2_conv_w2df; // "__builtin_HEXAG
	ON_M4_or_or"		ON_F2_conv_w2df"
	case 'p': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "mpyw", 4))		if (BuiltinName[29] != 'f')
	break;		break;
	return Intrinsic::hexagon_M4_pmpyw; // "__builtin_HEXAG ON_M4_pmpyw"		return Intrinsic::hexagon_F2_conv_w2sf; // "__builtin_HEXAG ON_F2_conv_w2sf"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'S': // 1 string to match.		case 'd': // 2 strings to match.
	if (memcmp(BuiltinName.data()+19, "2_brevp", 7))		if (memcmp(BuiltinName.data()+22, "ffm", 3))
	break;		break;
	return Intrinsic::hexagon_S2_brevp; // "__builtin_HEXAGON_S2_br		switch (BuiltinName[25]) {
	evp"		default: break;
	}		case 'a': // 1 string to match.
	break;		if (memcmp(BuiltinName.data()+26, "_lib", 4))
	case 'S': // 1 string to match.		break;
	if (memcmp(BuiltinName.data()+11, "I_to_SXTHI_asrh", 15))		return Intrinsic::hexagon_F2_dffma_lib; // "__builtin_HEXAG
			ON_F2_dffma_lib"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "_lib", 4))
			break;
			return Intrinsic::hexagon_F2_dffms_lib; // "__builtin_HEXAG
			ON_F2_dffms_lib"
			}
	break;		break;
	return Intrinsic::hexagon_SI_to_SXTHI_asrh; // "__builtin_SI_to		case 's': // 2 strings to match.
	_SXTHI_asrh"		if (memcmp(BuiltinName.data()+22, "ffm", 3))
	}		break;
	break;		switch (BuiltinName[25]) {
	case 27: // 70 strings to match.		default: break;
	if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))		case 'a': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "_lib", 4))
			break;
			return Intrinsic::hexagon_F2_sffma_lib; // "__builtin_HEXAG
			ON_F2_sffma_lib"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "_lib", 4))
			break;
			return Intrinsic::hexagon_F2_sffms_lib; // "__builtin_HEXAG
			ON_F2_sffms_lib"
			}
			break;
			}
	break;		break;
	switch (BuiltinName[18]) {		case 'M': // 44 strings to match.
	default: break;
	case 'A': // 35 strings to match.
	switch (BuiltinName[19]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case '2': // 26 strings to match.		case '2': // 41 strings to match.
	if (BuiltinName[20] != '_')		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'c': // 8 strings to match.
	switch (BuiltinName[22]) {
	default: break;
	case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "ssat", 4))
	break;
	return Intrinsic::hexagon_A2_abssat; // "__builtin_HEXAG
	ON_A2_abssat"
	case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "dsat", 4))
	break;
	return Intrinsic::hexagon_A2_addsat; // "__builtin_HEXAG
	ON_A2_addsat"
	}
	break;
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "egsat", 5))
	break;
	return Intrinsic::hexagon_A2_negsat; // "__builtin_HEXAGON_A2_ne
	gsat"
	case 's': // 4 strings to match.
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'u': // 1 string to match.		case 'm': // 6 strings to match.
	if (memcmp(BuiltinName.data()+23, "bsat", 4))
	break;
	return Intrinsic::hexagon_A2_subsat; // "__builtin_HEXAG
	ON_A2_subsat"
	case 'v': // 3 strings to match.
	switch (BuiltinName[23]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'a': // 2 strings to match.
	switch (BuiltinName[24]) {		if (memcmp(BuiltinName.data()+24, "csc_s", 5))
			break;
			switch (BuiltinName[29]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case '0': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "dh", 2))		return Intrinsic::hexagon_M2_cmacsc_s0; // "__built
			in_HEXAGON_M2_cmacsc_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_cmacsc_s1; // "__built
			in_HEXAGON_M2_cmacsc_s1"
			}
			break;
			case 'p': // 4 strings to match.
			if (BuiltinName[24] != 'y')
			break;
			switch (BuiltinName[25]) {
			default: break;
			case 'r': // 2 strings to match.
			if (memcmp(BuiltinName.data()+26, "s_s", 3))
	break;		break;
	return Intrinsic::hexagon_A2_svaddh; // "__builtin_HEXAG		switch (BuiltinName[29]) {
	ON_A2_svaddh"		default: break;
	case 'v': // 1 string to match.		case '0': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "gh", 2))		return Intrinsic::hexagon_M2_cmpyrs_s0; // "__built
			in_HEXAGON_M2_cmpyrs_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_cmpyrs_s1; // "__built
			in_HEXAGON_M2_cmpyrs_s1"
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(BuiltinName.data()+26, "c_s", 3))
	break;		break;
	return Intrinsic::hexagon_A2_svavgh; // "__builtin_HEXAG		switch (BuiltinName[29]) {
	ON_A2_svavgh"		default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_cmpysc_s0; // "__built
			in_HEXAGON_M2_cmpysc_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_cmpysc_s1; // "__built
			in_HEXAGON_M2_cmpysc_s1"
			}
			break;
	}		}
	break;		break;
	case 's': // 1 string to match.		}
	if (memcmp(BuiltinName.data()+24, "ubh", 3))		break;
	break;		case 'n': // 2 strings to match.
	return Intrinsic::hexagon_A2_svsubh; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+23, "acsc_s", 6))
	ON_A2_svsubh"		break;
			switch (BuiltinName[29]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_cnacsc_s0; // "__builtin_HEXAG
			ON_M2_cnacsc_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_cnacsc_s1; // "__builtin_HEXAG
			ON_M2_cnacsc_s1"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'v': // 19 strings to match.		case 'h': // 2 strings to match.
			if (memcmp(BuiltinName.data()+22, "mmpy", 4))
			break;
			switch (BuiltinName[26]) {
			default: break;
			case 'h': // 1 string to match.
			if (memcmp(BuiltinName.data()+27, "_s1", 3))
			break;
			return Intrinsic::hexagon_M2_hmmpyh_s1; // "__builtin_HEXAG
			ON_M2_hmmpyh_s1"
			case 'l': // 1 string to match.
			if (memcmp(BuiltinName.data()+27, "_s1", 3))
			break;
			return Intrinsic::hexagon_M2_hmmpyl_s1; // "__builtin_HEXAG
			ON_M2_hmmpyl_s1"
			}
			break;
			case 'm': // 21 strings to match.
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'a': // 8 strings to match.		case 'm': // 12 strings to match.
	switch (BuiltinName[23]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'd': // 3 strings to match.		case 'a': // 4 strings to match.
	if (BuiltinName[24] != 'd')		if (BuiltinName[24] != 'c')
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'h': // 2 strings to match.
	if (BuiltinName[26] != 's')		if (memcmp(BuiltinName.data()+26, "s_s", 3))
	break;
	return Intrinsic::hexagon_A2_vaddhs; // "__builtin_HEXAG
	ON_A2_vaddhs"
	case 'u': // 1 string to match.
	if (BuiltinName[26] != 'b')
	break;		break;
	return Intrinsic::hexagon_A2_vaddub; // "__builtin_HEXAG		switch (BuiltinName[29]) {
	ON_A2_vaddub"		default: break;
	case 'w': // 1 string to match.		case '0': // 1 string to match.
	if (BuiltinName[26] != 's')		return Intrinsic::hexagon_M2_mmachs_s0; // "__built
			in_HEXAGON_M2_mmachs_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mmachs_s1; // "__built
			in_HEXAGON_M2_mmachs_s1"
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+26, "s_s", 3))
	break;		break;
	return Intrinsic::hexagon_A2_vaddws; // "__builtin_HEXAG		switch (BuiltinName[29]) {
	ON_A2_vaddws"		default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mmacls_s0; // "__built
			in_HEXAGON_M2_mmacls_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mmacls_s1; // "__built
			in_HEXAGON_M2_mmacls_s1"
			}
			break;
	}		}
	break;		break;
	case 'v': // 5 strings to match.		case 'p': // 8 strings to match.
	if (BuiltinName[24] != 'g')		if (BuiltinName[24] != 'y')
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'h': // 2 strings to match.
	if (BuiltinName[26] != 'r')		if (memcmp(BuiltinName.data()+26, "_rs", 3))
	break;		break;
	return Intrinsic::hexagon_A2_vavghr; // "__builtin_HEXAG		switch (BuiltinName[29]) {
	ON_A2_vavghr"
	case 'u': // 3 strings to match.
	switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_A2_vavgub; // "__builtin_HEXAG		return Intrinsic::hexagon_M2_mmpyh_rs0; // "__built
	ON_A2_vavgub"		in_HEXAGON_M2_mmpyh_rs0"
	case 'h': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_A2_vavguh; // "__builtin_HEXAG		return Intrinsic::hexagon_M2_mmpyh_rs1; // "__built
	ON_A2_vavguh"		in_HEXAGON_M2_mmpyh_rs1"
	case 'w': // 1 string to match.		}
	return Intrinsic::hexagon_A2_vavguw; // "__builtin_HEXAG		break;
	ON_A2_vavguw"		case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+26, "_rs", 3))
			break;
			switch (BuiltinName[29]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mmpyl_rs0; // "__built
			in_HEXAGON_M2_mmpyl_rs0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mmpyl_rs1; // "__built
			in_HEXAGON_M2_mmpyl_rs1"
	}		}
	break;		break;
	case 'w': // 1 string to match.		case 'u': // 4 strings to match.
	if (BuiltinName[26] != 'r')		switch (BuiltinName[26]) {
			default: break;
			case 'h': // 2 strings to match.
			if (memcmp(BuiltinName.data()+27, "_s", 2))
			break;
			switch (BuiltinName[29]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mmpyuh_s0; // "__built
			in_HEXAGON_M2_mmpyuh_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mmpyuh_s1; // "__built
			in_HEXAGON_M2_mmpyuh_s1"
			}
	break;		break;
	return Intrinsic::hexagon_A2_vavgwr; // "__builtin_HEXAG		case 'l': // 2 strings to match.
	ON_A2_vavgwr"		if (memcmp(BuiltinName.data()+27, "_s", 2))
			break;
			switch (BuiltinName[29]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mmpyul_s0; // "__built
			in_HEXAGON_M2_mmpyul_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mmpyul_s1; // "__built
			in_HEXAGON_M2_mmpyul_s1"
			}
			break;
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'm': // 6 strings to match.		case 'p': // 9 strings to match.
	switch (BuiltinName[23]) {		if (memcmp(BuiltinName.data()+23, "y_", 2))
			break;
			switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'a': // 3 strings to match.		case 'h': // 4 strings to match.
	if (memcmp(BuiltinName.data()+24, "xu", 2))
	break;
	switch (BuiltinName[26]) {		switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'h': // 2 strings to match.
	return Intrinsic::hexagon_A2_vmaxub; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+27, "_s", 2))
	ON_A2_vmaxub"		break;
	case 'h': // 1 string to match.		switch (BuiltinName[29]) {
	return Intrinsic::hexagon_A2_vmaxuh; // "__builtin_HEXAG		default: break;
	ON_A2_vmaxuh"		case '0': // 1 string to match.
	case 'w': // 1 string to match.		return Intrinsic::hexagon_M2_mpy_hh_s0; // "__built
	return Intrinsic::hexagon_A2_vmaxuw; // "__builtin_HEXAG		in_HEXAGON_M2_mpy_hh_s0"
	ON_A2_vmaxuw"		case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_hh_s1; // "__built
			in_HEXAGON_M2_mpy_hh_s1"
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+27, "_s", 2))
			break;
			switch (BuiltinName[29]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_hl_s0; // "__built
			in_HEXAGON_M2_mpy_hl_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_hl_s1; // "__built
			in_HEXAGON_M2_mpy_hl_s1"
			}
			break;
	}		}
	break;		break;
	case 'i': // 3 strings to match.		case 'l': // 4 strings to match.
	if (memcmp(BuiltinName.data()+24, "nu", 2))
	break;
	switch (BuiltinName[26]) {		switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'h': // 2 strings to match.
	return Intrinsic::hexagon_A2_vminub; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+27, "_s", 2))
	ON_A2_vminub"		break;
	case 'h': // 1 string to match.		switch (BuiltinName[29]) {
	return Intrinsic::hexagon_A2_vminuh; // "__builtin_HEXAG		default: break;
	ON_A2_vminuh"		case '0': // 1 string to match.
	case 'w': // 1 string to match.		return Intrinsic::hexagon_M2_mpy_lh_s0; // "__built
	return Intrinsic::hexagon_A2_vminuw; // "__builtin_HEXAG		in_HEXAGON_M2_mpy_lh_s0"
	ON_A2_vminuw"		case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_lh_s1; // "__built
			in_HEXAGON_M2_mpy_lh_s1"
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+27, "_s", 2))
			break;
			switch (BuiltinName[29]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_ll_s0; // "__built
			in_HEXAGON_M2_mpy_ll_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_ll_s1; // "__built
			in_HEXAGON_M2_mpy_ll_s1"
			}
			break;
	}		}
	break;		break;
	}
	break;
	case 'n': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "avg", 3))
	break;
	switch (BuiltinName[26]) {
	default: break;
	case 'h': // 1 string to match.
	return Intrinsic::hexagon_A2_vnavgh; // "__builtin_HEXAG
	ON_A2_vnavgh"
	case 'w': // 1 string to match.
	return Intrinsic::hexagon_A2_vnavgw; // "__builtin_HEXAG
	ON_A2_vnavgw"
	}
	break;
	case 's': // 3 strings to match.
	if (memcmp(BuiltinName.data()+23, "ub", 2))
	break;
	switch (BuiltinName[25]) {
	default: break;
	case 'h': // 1 string to match.
	if (BuiltinName[26] != 's')
	break;
	return Intrinsic::hexagon_A2_vsubhs; // "__builtin_HEXAG
	ON_A2_vsubhs"
	case 'u': // 1 string to match.		case 'u': // 1 string to match.
	if (BuiltinName[26] != 'b')		if (memcmp(BuiltinName.data()+26, "p_s1", 4))
	break;
	return Intrinsic::hexagon_A2_vsubub; // "__builtin_HEXAG
	ON_A2_vsubub"
	case 'w': // 1 string to match.
	if (BuiltinName[26] != 's')
	break;
	return Intrinsic::hexagon_A2_vsubws; // "__builtin_HEXAG
	ON_A2_vsubws"
	}
	break;
	}
	break;
	}
	break;
	case '4': // 9 strings to match.
	if (BuiltinName[20] != '_')
	break;
	switch (BuiltinName[21]) {
	default: break;
	case 'c': // 4 strings to match.
	if (memcmp(BuiltinName.data()+22, "mp", 2))
	break;
	switch (BuiltinName[24]) {
	default: break;
	case 'b': // 2 strings to match.
	switch (BuiltinName[25]) {
	default: break;
	case 'e': // 1 string to match.
	if (BuiltinName[26] != 'q')
	break;
	return Intrinsic::hexagon_A4_cmpbeq; // "__builtin_HEXAG
	ON_A4_cmpbeq"
	case 'g': // 1 string to match.
	if (BuiltinName[26] != 't')
	break;
	return Intrinsic::hexagon_A4_cmpbgt; // "__builtin_HEXAG
	ON_A4_cmpbgt"
	}
	break;
	case 'h': // 2 strings to match.
	switch (BuiltinName[25]) {
	default: break;
	case 'e': // 1 string to match.
	if (BuiltinName[26] != 'q')
	break;
	return Intrinsic::hexagon_A4_cmpheq; // "__builtin_HEXAG
	ON_A4_cmpheq"
	case 'g': // 1 string to match.
	if (BuiltinName[26] != 't')
	break;		break;
	return Intrinsic::hexagon_A4_cmphgt; // "__builtin_HEXAG ON_A4_cmphgt"		return Intrinsic::hexagon_M2_mpy_up_s1; // "__builtin_HEXAG ON_M2_mpy_up_s1"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'r': // 1 string to match.		case 'v': // 10 strings to match.
	if (memcmp(BuiltinName.data()+22, "cmpeq", 5))		switch (BuiltinName[22]) {
	break;
	return Intrinsic::hexagon_A4_rcmpeq; // "__builtin_HEXAGON_A4_rc
	mpeq"
	case 'v': // 4 strings to match.
	if (memcmp(BuiltinName.data()+22, "rm", 2))
	break;
	switch (BuiltinName[24]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'a': // 2 strings to match.
	if (BuiltinName[25] != 'x')		if (memcmp(BuiltinName.data()+23, "bsdiff", 6))
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[29]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::hexagon_A4_vrmaxh; // "__builtin_HEXAG ON_A4_vrmaxh"		return Intrinsic::hexagon_M2_vabsdiffh; // "__builtin_HEXAG ON_M2_vabsdiffh"
	case 'w': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::hexagon_A4_vrmaxw; // "__builtin_HEXAG ON_A4_vrmaxw"		return Intrinsic::hexagon_M2_vabsdiffw; // "__builtin_HEXAG ON_M2_vabsdiffw"
	}		}
	break;		break;
	case 'i': // 2 strings to match.		case 'd': // 4 strings to match.
	if (BuiltinName[25] != 'n')		if (BuiltinName[23] != 'm')
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[24]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'a': // 2 strings to match.
	return Intrinsic::hexagon_A4_vrminh; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+25, "cs_s", 4))
	ON_A4_vrminh"		break;
	case 'w': // 1 string to match.		switch (BuiltinName[29]) {
	return Intrinsic::hexagon_A4_vrminw; // "__builtin_HEXAG		default: break;
	ON_A4_vrminw"		case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_vdmacs_s0; // "__built
			in_HEXAGON_M2_vdmacs_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_vdmacs_s1; // "__built
			in_HEXAGON_M2_vdmacs_s1"
			}
			break;
			case 'p': // 2 strings to match.
			if (memcmp(BuiltinName.data()+25, "ys_s", 4))
			break;
			switch (BuiltinName[29]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_vdmpys_s0; // "__built
			in_HEXAGON_M2_vdmpys_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_vdmpys_s1; // "__built
			in_HEXAGON_M2_vdmpys_s1"
			}
			break;
	}		}
	break;		break;
	}		case 'm': // 4 strings to match.
	break;		switch (BuiltinName[23]) {
	}
	break;
	}
	break;
	case 'C': // 12 strings to match.
	switch (BuiltinName[19]) {
	default: break;
	case '2': // 7 strings to match.
	if (memcmp(BuiltinName.data()+20, "_cmp", 4))
	break;
	switch (BuiltinName[24]) {
	default: break;
	case 'e': // 2 strings to match.
	if (BuiltinName[25] != 'q')
	break;
	switch (BuiltinName[26]) {
	default: break;
	case 'i': // 1 string to match.
	return Intrinsic::hexagon_C2_cmpeqi; // "__builtin_HEXAG
	ON_C2_cmpeqi"
	case 'p': // 1 string to match.
	return Intrinsic::hexagon_C2_cmpeqp; // "__builtin_HEXAG
	ON_C2_cmpeqp"
	}
	break;
	case 'g': // 4 strings to match.
	switch (BuiltinName[25]) {
	default: break;
	case 'e': // 1 string to match.
	if (BuiltinName[26] != 'i')
	break;
	return Intrinsic::hexagon_C2_cmpgei; // "__builtin_HEXAG
	ON_C2_cmpgei"
	case 't': // 3 strings to match.
	switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'i': // 1 string to match.		case 'a': // 2 strings to match.
	return Intrinsic::hexagon_C2_cmpgti; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+24, "c2s_s", 5))
	ON_C2_cmpgti"		break;
	case 'p': // 1 string to match.		switch (BuiltinName[29]) {
	return Intrinsic::hexagon_C2_cmpgtp; // "__builtin_HEXAG		default: break;
	ON_C2_cmpgtp"		case '0': // 1 string to match.
	case 'u': // 1 string to match.		return Intrinsic::hexagon_M2_vmac2s_s0; // "__built
	return Intrinsic::hexagon_C2_cmpgtu; // "__builtin_HEXAG		in_HEXAGON_M2_vmac2s_s0"
	ON_C2_cmpgtu"		case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_vmac2s_s1; // "__built
			in_HEXAGON_M2_vmac2s_s1"
			}
			break;
			case 'p': // 2 strings to match.
			if (memcmp(BuiltinName.data()+24, "y2s_s", 5))
			break;
			switch (BuiltinName[29]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_vmpy2s_s0; // "__built
			in_HEXAGON_M2_vmpy2s_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_vmpy2s_s1; // "__built
			in_HEXAGON_M2_vmpy2s_s1"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "tu", 2))
	break;
	return Intrinsic::hexagon_C2_cmpltu; // "__builtin_HEXAGON_C2_cm
	pltu"
	}		}
	break;		break;
	case '4': // 5 strings to match.		case '4': // 3 strings to match.
	if (BuiltinName[20] != '_')		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "nd_or", 5))
	break;
	return Intrinsic::hexagon_C4_and_or; // "__builtin_HEXAGON_C4_an
	d_or"
	case 'c': // 2 strings to match.		case 'c': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "mp", 2))		if (memcmp(BuiltinName.data()+22, "mpy", 3))
	break;		break;
	switch (BuiltinName[24]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "te", 2))		if (memcmp(BuiltinName.data()+26, "_whc", 4))
	break;		break;
	return Intrinsic::hexagon_C4_cmplte; // "__builtin_HEXAG		return Intrinsic::hexagon_M4_cmpyi_whc; // "__builtin_HEXAG
	ON_C4_cmplte"		ON_M4_cmpyi_whc"
	case 'n': // 1 string to match.		case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "eq", 2))		if (memcmp(BuiltinName.data()+26, "_whc", 4))
	break;		break;
	return Intrinsic::hexagon_C4_cmpneq; // "__builtin_HEXAG ON_C4_cmpneq"		return Intrinsic::hexagon_M4_cmpyr_whc; // "__builtin_HEXAG ON_M4_cmpyr_whc"
	}		}
	break;		break;
	case 'o': // 2 strings to match.		case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "r_", 2))		if (memcmp(BuiltinName.data()+22, "mpyw_acc", 8))
	break;		break;
	switch (BuiltinName[24]) {		return Intrinsic::hexagon_M4_pmpyw_acc; // "__builtin_HEXAG
	default: break;		ON_M4_pmpyw_acc"
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "nd", 2))
	break;
	return Intrinsic::hexagon_C4_or_and; // "__builtin_HEXAG
	ON_C4_or_and"
	case 'o': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "rn", 2))
	break;
	return Intrinsic::hexagon_C4_or_orn; // "__builtin_HEXAG
	ON_C4_or_orn"
	}
	break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'M': // 12 strings to match.		case 'S': // 12 strings to match.
	switch (BuiltinName[19]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case '2': // 7 strings to match.		case '2': // 4 strings to match.
	if (BuiltinName[20] != '_')		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'm': // 4 strings to match.		case 'e': // 1 string to match.
	switch (BuiltinName[22]) {		if (memcmp(BuiltinName.data()+22, "xtractup", 8))
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "csi", 3))
	break;
	switch (BuiltinName[26]) {
	default: break;
	case 'n': // 1 string to match.
	return Intrinsic::hexagon_M2_macsin; // "__builtin_HEXAG
	ON_M2_macsin"
	case 'p': // 1 string to match.
	return Intrinsic::hexagon_M2_macsip; // "__builtin_HEXAG
	ON_M2_macsip"
	}
	break;
	case 'p': // 2 strings to match.
	if (BuiltinName[23] != 'y')
	break;
	switch (BuiltinName[24]) {
	default: break;
	case '_': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "up", 2))
	break;
	return Intrinsic::hexagon_M2_mpy_up; // "__builtin_HEXAG
	ON_M2_mpy_up"
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "mi", 2))
	break;
	return Intrinsic::hexagon_M2_mpysmi; // "__builtin_HEXAG
	ON_M2_mpysmi"
	}
	break;
	}
	break;
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "accii", 5))
	break;
	return Intrinsic::hexagon_M2_naccii; // "__builtin_HEXAGON_M2_na
	ccii"
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "ubacc", 5))
	break;
	return Intrinsic::hexagon_M2_subacc; // "__builtin_HEXAGON_M2_su
	bacc"
	case 'v': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "raddh", 5))
	break;		break;
	return Intrinsic::hexagon_M2_vraddh; // "__builtin_HEXAGON_M2_vr		return Intrinsic::hexagon_S2_extractup; // "__builtin_HEXAG
	addh"		ON_S2_extractup"
	}		case 'i': // 1 string to match.
	break;		if (memcmp(BuiltinName.data()+22, "nsert_rp", 8))
	case '4': // 5 strings to match.
	if (BuiltinName[20] != '_')
	break;
	switch (BuiltinName[21]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "nd_or", 5))
	break;		break;
	return Intrinsic::hexagon_M4_and_or; // "__builtin_HEXAGON_M4_an		return Intrinsic::hexagon_S2_insert_rp; // "__builtin_HEXAG
	d_or"		ON_S2_insert_rp"
	case 'o': // 2 strings to match.		case 'v': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "r_", 2))		if (memcmp(BuiltinName.data()+22, "splice", 6))
	break;		break;
	switch (BuiltinName[24]) {		switch (BuiltinName[28]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "nd", 2))		if (BuiltinName[29] != 'b')
	break;		break;
	return Intrinsic::hexagon_M4_or_and; // "__builtin_HEXAG		return Intrinsic::hexagon_S2_vspliceib; // "__builtin_HEXAG
	ON_M4_or_and"		ON_S2_vspliceib"
	case 'x': // 1 string to match.		case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "or", 2))		if (BuiltinName[29] != 'b')
	break;		break;
	return Intrinsic::hexagon_M4_or_xor; // "__builtin_HEXAG ON_M4_or_xor"		return Intrinsic::hexagon_S2_vsplicerb; // "__builtin_HEXAG ON_S2_vsplicerb"
	}		}
	break;		break;
	case 'v': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "pmpyh", 5))
	break;
	return Intrinsic::hexagon_M4_vpmpyh; // "__builtin_HEXAGON_M4_vp
	mpyh"
	case 'x': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "or_or", 5))
	break;
	return Intrinsic::hexagon_M4_xor_or; // "__builtin_HEXAGON_M4_xo
	r_or"
	}		}
	break;		break;
	}		case '4': // 7 strings to match.
	break;
	case 'S': // 11 strings to match.
	switch (BuiltinName[19]) {
	default: break;
	case '2': // 9 strings to match.
	if (BuiltinName[20] != '_')		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'i': // 1 string to match.		case 'n': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "nsert", 5))		if (memcmp(BuiltinName.data()+22, "tstbit_", 7))
	break;
	return Intrinsic::hexagon_S2_insert; // "__builtin_HEXAGON_S2_in
	sert"
	case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "ackhl", 5))
	break;		break;
	return Intrinsic::hexagon_S2_packhl; // "__builtin_HEXAGON_S2_pa		switch (BuiltinName[29]) {
	ckhl"		default: break;
	case 'v': // 7 strings to match.		case 'i': // 1 string to match.
			return Intrinsic::hexagon_S4_ntstbit_i; // "__builtin_HEXAG
			ON_S4_ntstbit_i"
			case 'r': // 1 string to match.
			return Intrinsic::hexagon_S4_ntstbit_r; // "__builtin_HEXAG
			ON_S4_ntstbit_r"
			}
			break;
			case 'v': // 5 strings to match.
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'c': // 1 string to match.		case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "negh", 4))		if (memcmp(BuiltinName.data()+23, "crotate", 7))
	break;		break;
	return Intrinsic::hexagon_S2_vcnegh; // "__builtin_HEXAG		return Intrinsic::hexagon_S4_vrcrotate; // "__builtin_HEXAG
	ON_S2_vcnegh"		ON_S4_vrcrotate"
	case 's': // 4 strings to match.		case 'x': // 4 strings to match.
	switch (BuiltinName[23]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'a': // 2 strings to match.
	if (BuiltinName[24] != 't')		if (memcmp(BuiltinName.data()+24, "ddsub", 5))
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[29]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'h': // 1 string to match.
	if (BuiltinName[26] != 'b')		return Intrinsic::hexagon_S4_vxaddsubh; // "__built
	break;		in_HEXAGON_S4_vxaddsubh"
	return Intrinsic::hexagon_S2_vsathb; // "__builtin_HEXAG
	ON_S2_vsathb"
	case 'w': // 1 string to match.		case 'w': // 1 string to match.
	if (BuiltinName[26] != 'h')		return Intrinsic::hexagon_S4_vxaddsubw; // "__built
	break;		in_HEXAGON_S4_vxaddsubw"
	return Intrinsic::hexagon_S2_vsatwh; // "__builtin_HEXAG
	ON_S2_vsatwh"
	}		}
	break;		break;
	case 'x': // 2 strings to match.		case 's': // 2 strings to match.
	if (BuiltinName[24] != 't')		if (memcmp(BuiltinName.data()+24, "ubadd", 5))
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[29]) {
	default: break;		default: break;
	case 'b': // 1 string to match.
	if (BuiltinName[26] != 'h')
	break;
	return Intrinsic::hexagon_S2_vsxtbh; // "__builtin_HEXAG
	ON_S2_vsxtbh"
	case 'h': // 1 string to match.		case 'h': // 1 string to match.
	if (BuiltinName[26] != 'w')		return Intrinsic::hexagon_S4_vxsubaddh; // "__built
	break;		in_HEXAGON_S4_vxsubaddh"
	return Intrinsic::hexagon_S2_vsxthw; // "__builtin_HEXAG		case 'w': // 1 string to match.
	ON_S2_vsxthw"		return Intrinsic::hexagon_S4_vxsubaddw; // "__built
			in_HEXAGON_S4_vxsubaddw"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'z': // 2 strings to match.		}
	if (memcmp(BuiltinName.data()+23, "xt", 2))		break;
	break;		}
	switch (BuiltinName[25]) {		break;
	default: break;		case '5': // 1 string to match.
	case 'b': // 1 string to match.		if (memcmp(BuiltinName.data()+20, "_popcountp", 10))
	if (BuiltinName[26] != 'h')		break;
	break;		return Intrinsic::hexagon_S5_popcountp; // "__builtin_HEXAG
	return Intrinsic::hexagon_S2_vzxtbh; // "__builtin_HEXAG		ON_S5_popcountp"
	ON_S2_vzxtbh"		}
	case 'h': // 1 string to match.		break;
	if (BuiltinName[26] != 'w')		}
	break;		break;
	return Intrinsic::hexagon_S2_vzxthw; // "__builtin_HEXAG		case 31: // 95 strings to match.
	ON_S2_vzxthw"		if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
	}		break;
			switch (BuiltinName[18]) {
			default: break;
			case 'A': // 4 strings to match.
			if (memcmp(BuiltinName.data()+19, "2_combine_", 10))
			break;
			switch (BuiltinName[29]) {
			default: break;
			case 'h': // 2 strings to match.
			switch (BuiltinName[30]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_A2_combine_hh; // "__builtin_HEXAG
			ON_A2_combine_hh"
			case 'l': // 1 string to match.
			return Intrinsic::hexagon_A2_combine_hl; // "__builtin_HEXAG
			ON_A2_combine_hl"
			}
			break;
			case 'l': // 2 strings to match.
			switch (BuiltinName[30]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_A2_combine_lh; // "__builtin_HEXAG
			ON_A2_combine_lh"
			case 'l': // 1 string to match.
			return Intrinsic::hexagon_A2_combine_ll; // "__builtin_HEXAG
			ON_A2_combine_ll"
			}
			break;
			}
			break;
			case 'F': // 10 strings to match.
			if (memcmp(BuiltinName.data()+19, "2_conv_", 7))
			break;
			switch (BuiltinName[26]) {
			default: break;
			case 'd': // 3 strings to match.
			if (memcmp(BuiltinName.data()+27, "f2", 2))
			break;
			switch (BuiltinName[29]) {
			default: break;
			case 's': // 1 string to match.
			if (BuiltinName[30] != 'f')
	break;		break;
			return Intrinsic::hexagon_F2_conv_df2sf; // "__builtin_HEXAG
			ON_F2_conv_df2sf"
			case 'u': // 2 strings to match.
			switch (BuiltinName[30]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::hexagon_F2_conv_df2ud; // "__builtin_HEXAG
			ON_F2_conv_df2ud"
			case 'w': // 1 string to match.
			return Intrinsic::hexagon_F2_conv_df2uw; // "__builtin_HEXAG
			ON_F2_conv_df2uw"
	}		}
	break;		break;
	}		}
	break;		break;
	case '4': // 2 strings to match.		case 's': // 3 strings to match.
	if (BuiltinName[20] != '_')		if (memcmp(BuiltinName.data()+27, "f2", 2))
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[29]) {
	default: break;		default: break;
	case 'o': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "r_ori", 5))		if (BuiltinName[30] != 'f')
	break;		break;
	return Intrinsic::hexagon_S4_or_ori; // "__builtin_HEXAGON_S4_or		return Intrinsic::hexagon_F2_conv_sf2df; // "__builtin_HEXAG
	_ori"		ON_F2_conv_sf2df"
	case 'p': // 1 string to match.		case 'u': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "arity", 5))		switch (BuiltinName[30]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::hexagon_F2_conv_sf2ud; // "__builtin_HEXAG
			ON_F2_conv_sf2ud"
			case 'w': // 1 string to match.
			return Intrinsic::hexagon_F2_conv_sf2uw; // "__builtin_HEXAG
			ON_F2_conv_sf2uw"
			}
			break;
			}
			break;
			case 'u': // 4 strings to match.
			switch (BuiltinName[27]) {
			default: break;
			case 'd': // 2 strings to match.
			if (BuiltinName[28] != '2')
	break;		break;
	return Intrinsic::hexagon_S4_parity; // "__builtin_HEXAGON_S4_pa		switch (BuiltinName[29]) {
	rity"		default: break;
			case 'd': // 1 string to match.
			if (BuiltinName[30] != 'f')
			break;
			return Intrinsic::hexagon_F2_conv_ud2df; // "__builtin_HEXAG
			ON_F2_conv_ud2df"
			case 's': // 1 string to match.
			if (BuiltinName[30] != 'f')
			break;
			return Intrinsic::hexagon_F2_conv_ud2sf; // "__builtin_HEXAG
			ON_F2_conv_ud2sf"
			}
			break;
			case 'w': // 2 strings to match.
			if (BuiltinName[28] != '2')
			break;
			switch (BuiltinName[29]) {
			default: break;
			case 'd': // 1 string to match.
			if (BuiltinName[30] != 'f')
			break;
			return Intrinsic::hexagon_F2_conv_uw2df; // "__builtin_HEXAG
			ON_F2_conv_uw2df"
			case 's': // 1 string to match.
			if (BuiltinName[30] != 'f')
			break;
			return Intrinsic::hexagon_F2_conv_uw2sf; // "__builtin_HEXAG
			ON_F2_conv_uw2sf"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'M': // 58 strings to match.
	break;
	case 28: // 103 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
	break;
	switch (BuiltinName[18]) {
	default: break;
	case 'A': // 36 strings to match.
	switch (BuiltinName[19]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case '2': // 23 strings to match.		case '2': // 49 strings to match.
	if (BuiltinName[20] != '_')		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'c': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "ddpsat", 6))		if (memcmp(BuiltinName.data()+22, "mpyrsc_s", 8))
	break;		break;
	return Intrinsic::hexagon_A2_addpsat; // "__builtin_HEXAG		switch (BuiltinName[30]) {
	ON_A2_addpsat"		default: break;
	case 's': // 4 strings to match.		case '0': // 1 string to match.
	if (BuiltinName[22] != 'v')		return Intrinsic::hexagon_M2_cmpyrsc_s0; // "__builtin_HEXAG
			ON_M2_cmpyrsc_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_cmpyrsc_s1; // "__builtin_HEXAG
			ON_M2_cmpyrsc_s1"
			}
			break;
			case 'd': // 2 strings to match.
			if (memcmp(BuiltinName.data()+22, "pmpy", 4))
	break;		break;
	switch (BuiltinName[23]) {		switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 's': // 1 string to match.
	switch (BuiltinName[24]) {		if (memcmp(BuiltinName.data()+27, "s_s0", 4))
	default: break;		break;
	case 'd': // 1 string to match.		return Intrinsic::hexagon_M2_dpmpyss_s0; // "__builtin_HEXAG
	if (memcmp(BuiltinName.data()+25, "dhs", 3))		ON_M2_dpmpyss_s0"
	break;		case 'u': // 1 string to match.
	return Intrinsic::hexagon_A2_svaddhs; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+27, "u_s0", 4))
	ON_A2_svaddhs"		break;
	case 'v': // 1 string to match.		return Intrinsic::hexagon_M2_dpmpyuu_s0; // "__builtin_HEXAG
	if (memcmp(BuiltinName.data()+25, "ghs", 3))		ON_M2_dpmpyuu_s0"
	break;		}
	return Intrinsic::hexagon_A2_svavghs; // "__builtin_HEXAG		break;
	ON_A2_svavghs"		case 'h': // 2 strings to match.
	}		if (memcmp(BuiltinName.data()+22, "mmpy", 4))
	break;		break;
	case 'n': // 1 string to match.		switch (BuiltinName[26]) {
	if (memcmp(BuiltinName.data()+24, "avgh", 4))		default: break;
			case 'h': // 1 string to match.
			if (memcmp(BuiltinName.data()+27, "_rs1", 4))
	break;		break;
	return Intrinsic::hexagon_A2_svnavgh; // "__builtin_HEXAG		return Intrinsic::hexagon_M2_hmmpyh_rs1; // "__builtin_HEXAG
	ON_A2_svnavgh"		ON_M2_hmmpyh_rs1"
	case 's': // 1 string to match.		case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "ubhs", 4))		if (memcmp(BuiltinName.data()+27, "_rs1", 4))
	break;		break;
	return Intrinsic::hexagon_A2_svsubhs; // "__builtin_HEXAG ON_A2_svsubhs"		return Intrinsic::hexagon_M2_hmmpyl_rs1; // "__builtin_HEXAG ON_M2_hmmpyl_rs1"
	}		}
	break;		break;
	case 'v': // 18 strings to match.		case 'm': // 28 strings to match.
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'a': // 7 strings to match.		case 'm': // 12 strings to match.
	switch (BuiltinName[23]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'd': // 2 strings to match.		case 'a': // 8 strings to match.
	if (memcmp(BuiltinName.data()+24, "du", 2))		if (BuiltinName[24] != 'c')
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'h': // 2 strings to match.
	if (BuiltinName[27] != 's')		if (memcmp(BuiltinName.data()+26, "s_rs", 4))
	break;		break;
	return Intrinsic::hexagon_A2_vaddubs; // "__builtin_HEXAG		switch (BuiltinName[30]) {
	ON_A2_vaddubs"		default: break;
	case 'h': // 1 string to match.		case '0': // 1 string to match.
	if (BuiltinName[27] != 's')		return Intrinsic::hexagon_M2_mmachs_rs0; // "__built
			in_HEXAGON_M2_mmachs_rs0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mmachs_rs1; // "__built
			in_HEXAGON_M2_mmachs_rs1"
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+26, "s_rs", 4))
	break;		break;
	return Intrinsic::hexagon_A2_vadduhs; // "__builtin_HEXAG		switch (BuiltinName[30]) {
	ON_A2_vadduhs"		default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mmacls_rs0; // "__built
			in_HEXAGON_M2_mmacls_rs0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mmacls_rs1; // "__built
			in_HEXAGON_M2_mmacls_rs1"
			}
			break;
			case 'u': // 4 strings to match.
			switch (BuiltinName[26]) {
			default: break;
			case 'h': // 2 strings to match.
			if (memcmp(BuiltinName.data()+27, "s_s", 3))
			break;
			switch (BuiltinName[30]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mmacuhs_s0; // "__built
			in_HEXAGON_M2_mmacuhs_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mmacuhs_s1; // "__built
			in_HEXAGON_M2_mmacuhs_s1"
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+27, "s_s", 3))
			break;
			switch (BuiltinName[30]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mmaculs_s0; // "__built
			in_HEXAGON_M2_mmaculs_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mmaculs_s1; // "__built
			in_HEXAGON_M2_mmaculs_s1"
			}
			break;
			}
			break;
	}		}
	break;		break;
	case 'v': // 5 strings to match.		case 'p': // 4 strings to match.
	if (BuiltinName[24] != 'g')		if (memcmp(BuiltinName.data()+24, "yu", 2))
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+26, "cr", 2))		if (memcmp(BuiltinName.data()+27, "_rs", 3))
	break;		break;
	return Intrinsic::hexagon_A2_vavghcr; // "__builtin_HEXAG		switch (BuiltinName[30]) {
	ON_A2_vavghcr"
	case 'u': // 3 strings to match.
	switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case '0': // 1 string to match.
	if (BuiltinName[27] != 'r')		return Intrinsic::hexagon_M2_mmpyuh_rs0; // "__built
	break;		in_HEXAGON_M2_mmpyuh_rs0"
	return Intrinsic::hexagon_A2_vavgubr; // "__built		case '1': // 1 string to match.
	in_HEXAGON_A2_vavgubr"		return Intrinsic::hexagon_M2_mmpyuh_rs1; // "__built
	case 'h': // 1 string to match.		in_HEXAGON_M2_mmpyuh_rs1"
	if (BuiltinName[27] != 'r')
	break;
	return Intrinsic::hexagon_A2_vavguhr; // "__built
	in_HEXAGON_A2_vavguhr"
	case 'w': // 1 string to match.
	if (BuiltinName[27] != 'r')
	break;
	return Intrinsic::hexagon_A2_vavguwr; // "__built
	in_HEXAGON_A2_vavguwr"
	}		}
	break;		break;
	case 'w': // 1 string to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+26, "cr", 2))		if (memcmp(BuiltinName.data()+27, "_rs", 3))
	break;		break;
	return Intrinsic::hexagon_A2_vavgwcr; // "__builtin_HEXAG		switch (BuiltinName[30]) {
	ON_A2_vavgwcr"		default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mmpyul_rs0; // "__built
			in_HEXAGON_M2_mmpyul_rs0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mmpyul_rs1; // "__built
			in_HEXAGON_M2_mmpyul_rs1"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'c': // 5 strings to match.		case 'p': // 16 strings to match.
	if (memcmp(BuiltinName.data()+23, "mp", 2))		if (BuiltinName[23] != 'y')
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[24]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'd': // 8 strings to match.
	if (memcmp(BuiltinName.data()+26, "eq", 2))		if (BuiltinName[25] != '_')
	break;		break;
	return Intrinsic::hexagon_A2_vcmpbeq; // "__builtin_HEXAG
	ON_A2_vcmpbeq"
	case 'h': // 2 strings to match.
	switch (BuiltinName[26]) {		switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'h': // 4 strings to match.
	if (BuiltinName[27] != 'q')		switch (BuiltinName[27]) {
			default: break;
			case 'h': // 2 strings to match.
			if (memcmp(BuiltinName.data()+28, "_s", 2))
			break;
			switch (BuiltinName[30]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyd_hh_s0; // "__built
			in_HEXAGON_M2_mpyd_hh_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyd_hh_s1; // "__built
			in_HEXAGON_M2_mpyd_hh_s1"
			}
	break;		break;
	return Intrinsic::hexagon_A2_vcmpheq; // "__builtin_HEXAG		case 'l': // 2 strings to match.
	ON_A2_vcmpheq"		if (memcmp(BuiltinName.data()+28, "_s", 2))
	case 'g': // 1 string to match.		break;
	if (BuiltinName[27] != 't')		switch (BuiltinName[30]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyd_hl_s0; // "__built
			in_HEXAGON_M2_mpyd_hl_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyd_hl_s1; // "__built
			in_HEXAGON_M2_mpyd_hl_s1"
			}
	break;		break;
	return Intrinsic::hexagon_A2_vcmphgt; // "__builtin_HEXAG		}
	ON_A2_vcmphgt"		break;
			case 'l': // 4 strings to match.
			switch (BuiltinName[27]) {
			default: break;
			case 'h': // 2 strings to match.
			if (memcmp(BuiltinName.data()+28, "_s", 2))
			break;
			switch (BuiltinName[30]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyd_lh_s0; // "__built
			in_HEXAGON_M2_mpyd_lh_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyd_lh_s1; // "__built
			in_HEXAGON_M2_mpyd_lh_s1"
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+28, "_s", 2))
			break;
			switch (BuiltinName[30]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyd_ll_s0; // "__built
			in_HEXAGON_M2_mpyd_ll_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyd_ll_s1; // "__built
			in_HEXAGON_M2_mpyd_ll_s1"
			}
			break;
			}
			break;
	}		}
	break;		break;
	case 'w': // 2 strings to match.		case 'u': // 8 strings to match.
			if (BuiltinName[25] != '_')
			break;
	switch (BuiltinName[26]) {		switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'h': // 4 strings to match.
	if (BuiltinName[27] != 'q')		switch (BuiltinName[27]) {
			default: break;
			case 'h': // 2 strings to match.
			if (memcmp(BuiltinName.data()+28, "_s", 2))
			break;
			switch (BuiltinName[30]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_hh_s0; // "__built
			in_HEXAGON_M2_mpyu_hh_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_hh_s1; // "__built
			in_HEXAGON_M2_mpyu_hh_s1"
			}
	break;		break;
	return Intrinsic::hexagon_A2_vcmpweq; // "__builtin_HEXAG		case 'l': // 2 strings to match.
	ON_A2_vcmpweq"		if (memcmp(BuiltinName.data()+28, "_s", 2))
	case 'g': // 1 string to match.		break;
	if (BuiltinName[27] != 't')		switch (BuiltinName[30]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_hl_s0; // "__built
			in_HEXAGON_M2_mpyu_hl_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_hl_s1; // "__built
			in_HEXAGON_M2_mpyu_hl_s1"
			}
	break;		break;
	return Intrinsic::hexagon_A2_vcmpwgt; // "__builtin_HEXAG		}
	ON_A2_vcmpwgt"
	}
	break;
	}
	break;
	case 'n': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "avg", 3))
	break;
	switch (BuiltinName[26]) {
	default: break;
	case 'h': // 1 string to match.
	if (BuiltinName[27] != 'r')
	break;
	return Intrinsic::hexagon_A2_vnavghr; // "__builtin_HEXAG
	ON_A2_vnavghr"
	case 'w': // 1 string to match.
	if (BuiltinName[27] != 'r')
	break;
	return Intrinsic::hexagon_A2_vnavgwr; // "__builtin_HEXAG
	ON_A2_vnavgwr"
	}
	break;
	case 'r': // 2 strings to match.
	switch (BuiltinName[23]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "ddub", 4))
	break;		break;
	return Intrinsic::hexagon_A2_vraddub; // "__builtin_HEXAG		case 'l': // 4 strings to match.
	ON_A2_vraddub"		switch (BuiltinName[27]) {
	case 's': // 1 string to match.		default: break;
	if (memcmp(BuiltinName.data()+24, "adub", 4))		case 'h': // 2 strings to match.
			if (memcmp(BuiltinName.data()+28, "_s", 2))
			break;
			switch (BuiltinName[30]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_lh_s0; // "__built
			in_HEXAGON_M2_mpyu_lh_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_lh_s1; // "__built
			in_HEXAGON_M2_mpyu_lh_s1"
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+28, "_s", 2))
			break;
			switch (BuiltinName[30]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_ll_s0; // "__built
			in_HEXAGON_M2_mpyu_ll_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_ll_s1; // "__built
			in_HEXAGON_M2_mpyu_ll_s1"
			}
			break;
			}
	break;		break;
	return Intrinsic::hexagon_A2_vrsadub; // "__builtin_HEXAG		}
	ON_A2_vrsadub"
	}
	break;
	case 's': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "ubu", 3))
	break;		break;
	switch (BuiltinName[26]) {
	default: break;
	case 'b': // 1 string to match.
	if (BuiltinName[27] != 's')
	break;
	return Intrinsic::hexagon_A2_vsububs; // "__builtin_HEXAG
	ON_A2_vsububs"
	case 'h': // 1 string to match.
	if (BuiltinName[27] != 's')
	break;
	return Intrinsic::hexagon_A2_vsubuhs; // "__builtin_HEXAG
	ON_A2_vsubuhs"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'v': // 15 strings to match.
	break;		switch (BuiltinName[22]) {
	case '4': // 13 strings to match.
	if (BuiltinName[20] != '_')
	break;
	switch (BuiltinName[21]) {
	default: break;
	case 'c': // 6 strings to match.
	if (memcmp(BuiltinName.data()+22, "mp", 2))
	break;
	switch (BuiltinName[24]) {
	default: break;		default: break;
	case 'b': // 3 strings to match.		case 'd': // 2 strings to match.
	switch (BuiltinName[25]) {		if (memcmp(BuiltinName.data()+23, "mpyrs_s", 7))
	default: break;
	case 'e': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "qi", 2))
	break;
	return Intrinsic::hexagon_A4_cmpbeqi; // "__builtin_HEXAG
	ON_A4_cmpbeqi"
	case 'g': // 2 strings to match.
	if (BuiltinName[26] != 't')
	break;
	switch (BuiltinName[27]) {
	default: break;
	case 'i': // 1 string to match.
	return Intrinsic::hexagon_A4_cmpbgti; // "__builtin_HEXAG
	ON_A4_cmpbgti"
	case 'u': // 1 string to match.
	return Intrinsic::hexagon_A4_cmpbgtu; // "__builtin_HEXAG
	ON_A4_cmpbgtu"
	}
	break;		break;
			switch (BuiltinName[30]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_vdmpyrs_s0; // "__builtin_HEXAG
			ON_M2_vdmpyrs_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_vdmpyrs_s1; // "__builtin_HEXAG
			ON_M2_vdmpyrs_s1"
	}		}
	break;		break;
	case 'h': // 3 strings to match.		case 'm': // 8 strings to match.
	switch (BuiltinName[25]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'a': // 4 strings to match.
	if (memcmp(BuiltinName.data()+26, "qi", 2))		if (memcmp(BuiltinName.data()+24, "c2", 2))
			break;
			switch (BuiltinName[26]) {
			default: break;
			case 'e': // 2 strings to match.
			if (memcmp(BuiltinName.data()+27, "s_s", 3))
			break;
			switch (BuiltinName[30]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_vmac2es_s0; // "__built
			in_HEXAGON_M2_vmac2es_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_vmac2es_s1; // "__built
			in_HEXAGON_M2_vmac2es_s1"
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(BuiltinName.data()+27, "u_s", 3))
			break;
			switch (BuiltinName[30]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_vmac2su_s0; // "__built
			in_HEXAGON_M2_vmac2su_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_vmac2su_s1; // "__built
			in_HEXAGON_M2_vmac2su_s1"
			}
	break;		break;
	return Intrinsic::hexagon_A4_cmpheqi; // "__builtin_HEXAG		}
	ON_A4_cmpheqi"		break;
	case 'g': // 2 strings to match.		case 'p': // 4 strings to match.
	if (BuiltinName[26] != 't')		if (memcmp(BuiltinName.data()+24, "y2", 2))
	break;		break;
	switch (BuiltinName[27]) {		switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'i': // 1 string to match.		case 'e': // 2 strings to match.
	return Intrinsic::hexagon_A4_cmphgti; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+27, "s_s", 3))
	ON_A4_cmphgti"		break;
	case 'u': // 1 string to match.		switch (BuiltinName[30]) {
	return Intrinsic::hexagon_A4_cmphgtu; // "__builtin_HEXAG		default: break;
	ON_A4_cmphgtu"		case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_vmpy2es_s0; // "__built
			in_HEXAGON_M2_vmpy2es_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_vmpy2es_s1; // "__built
			in_HEXAGON_M2_vmpy2es_s1"
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(BuiltinName.data()+27, "u_s", 3))
			break;
			switch (BuiltinName[30]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_vmpy2su_s0; // "__built
			in_HEXAGON_M2_vmpy2su_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_vmpy2su_s1; // "__built
			in_HEXAGON_M2_vmpy2su_s1"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'r': // 5 strings to match.
	break;		if (memcmp(BuiltinName.data()+23, "cm", 2))
	case 'r': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "cmp", 3))
	break;
	switch (BuiltinName[25]) {
	default: break;
	case 'e': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "qi", 2))
	break;
	return Intrinsic::hexagon_A4_rcmpeqi; // "__builtin_HEXAG
	ON_A4_rcmpeqi"
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "eq", 2))
	break;
	return Intrinsic::hexagon_A4_rcmpneq; // "__builtin_HEXAG
	ON_A4_rcmpneq"
	}
	break;
	case 'v': // 5 strings to match.
	switch (BuiltinName[22]) {
	default: break;
	case 'c': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "mpbgt", 5))
	break;
	return Intrinsic::hexagon_A4_vcmpbgt; // "__builtin_HEXAG
	ON_A4_vcmpbgt"
	case 'r': // 4 strings to match.
	if (BuiltinName[23] != 'm')
	break;		break;
	switch (BuiltinName[24]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+25, "xu", 2))		if (BuiltinName[26] != 'c')
	break;		break;
	switch (BuiltinName[27]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'i': // 1 string to match.
	return Intrinsic::hexagon_A4_vrmaxuh; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+28, "_s0", 3))
	ON_A4_vrmaxuh"		break;
	case 'w': // 1 string to match.		return Intrinsic::hexagon_M2_vrcmaci_s0; // "__built
	return Intrinsic::hexagon_A4_vrmaxuw; // "__builtin_HEXAG		in_HEXAGON_M2_vrcmaci_s0"
	ON_A4_vrmaxuw"		case 'r': // 1 string to match.
			if (memcmp(BuiltinName.data()+28, "_s0", 3))
			break;
			return Intrinsic::hexagon_M2_vrcmacr_s0; // "__built
			in_HEXAGON_M2_vrcmacr_s0"
	}		}
	break;		break;
	case 'i': // 2 strings to match.		case 'p': // 3 strings to match.
	if (memcmp(BuiltinName.data()+25, "nu", 2))		if (BuiltinName[26] != 'y')
	break;		break;
	switch (BuiltinName[27]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'i': // 1 string to match.
	return Intrinsic::hexagon_A4_vrminuh; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+28, "_s0", 3))
	ON_A4_vrminuh"		break;
	case 'w': // 1 string to match.		return Intrinsic::hexagon_M2_vrcmpyi_s0; // "__built
	return Intrinsic::hexagon_A4_vrminuw; // "__builtin_HEXAG		in_HEXAGON_M2_vrcmpyi_s0"
	ON_A4_vrminuw"		case 'r': // 1 string to match.
			if (memcmp(BuiltinName.data()+28, "_s0", 3))
			break;
			return Intrinsic::hexagon_M2_vrcmpyr_s0; // "__built
			in_HEXAGON_M2_vrcmpyr_s0"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+28, "_s1", 3))
			break;
			return Intrinsic::hexagon_M2_vrcmpys_s1; // "__built
			in_HEXAGON_M2_vrcmpys_s1"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		case '4': // 9 strings to match.
	break;
	case 'C': // 12 strings to match.
	switch (BuiltinName[19]) {
	default: break;
	case '2': // 6 strings to match.
	if (BuiltinName[20] != '_')		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'b': // 2 strings to match.		case 'm': // 4 strings to match.
	if (memcmp(BuiltinName.data()+22, "its", 3))		if (memcmp(BuiltinName.data()+22, "pyr", 3))
	break;
	switch (BuiltinName[25]) {
	default: break;
	case 'c': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "lr", 2))
	break;
	return Intrinsic::hexagon_C2_bitsclr; // "__builtin_HEXAG
	ON_C2_bitsclr"
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "et", 2))
	break;
	return Intrinsic::hexagon_C2_bitsset; // "__builtin_HEXAG
	ON_C2_bitsset"
	}
	break;
	case 'c': // 3 strings to match.
	if (memcmp(BuiltinName.data()+22, "mpg", 3))
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'i': // 2 strings to match.
	if (memcmp(BuiltinName.data()+26, "ui", 2))		if (memcmp(BuiltinName.data()+26, "_add", 4))
	break;
	return Intrinsic::hexagon_C2_cmpgeui; // "__builtin_HEXAG
	ON_C2_cmpgeui"
	case 't': // 2 strings to match.
	if (BuiltinName[26] != 'u')
	break;		break;
	switch (BuiltinName[27]) {		switch (BuiltinName[30]) {
	default: break;		default: break;
	case 'i': // 1 string to match.		case 'i': // 1 string to match.
	return Intrinsic::hexagon_C2_cmpgtui; // "__builtin_HEXAG		return Intrinsic::hexagon_M4_mpyri_addi; // "__builtin_HEXAG
	ON_C2_cmpgtui"		ON_M4_mpyri_addi"
	case 'p': // 1 string to match.		case 'r': // 1 string to match.
	return Intrinsic::hexagon_C2_cmpgtup; // "__builtin_HEXAG		return Intrinsic::hexagon_M4_mpyri_addr; // "__builtin_HEXAG
	ON_C2_cmpgtup"		ON_M4_mpyri_addr"
	}		}
	break;		break;
	}		case 'r': // 2 strings to match.
	break;		if (memcmp(BuiltinName.data()+26, "_add", 4))
	case 'v': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "itpack", 6))
	break;
	return Intrinsic::hexagon_C2_vitpack; // "__builtin_HEXAG
	ON_C2_vitpack"
	}
	break;
	case '4': // 6 strings to match.
	if (BuiltinName[20] != '_')
	break;
	switch (BuiltinName[21]) {
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "nd_", 3))
	break;
	switch (BuiltinName[25]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "nd", 2))
	break;
	return Intrinsic::hexagon_C4_and_and; // "__builtin_HEXAG
	ON_C4_and_and"
	case 'o': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "rn", 2))
	break;
	return Intrinsic::hexagon_C4_and_orn; // "__builtin_HEXAG
	ON_C4_and_orn"
	}
	break;
	case 'c': // 3 strings to match.
	if (memcmp(BuiltinName.data()+22, "mp", 2))
	break;
	switch (BuiltinName[24]) {
	default: break;
	case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+25, "te", 2))
	break;		break;
	switch (BuiltinName[27]) {		switch (BuiltinName[30]) {
	default: break;		default: break;
	case 'i': // 1 string to match.		case 'i': // 1 string to match.
	return Intrinsic::hexagon_C4_cmpltei; // "__builtin_HEXAG		return Intrinsic::hexagon_M4_mpyrr_addi; // "__builtin_HEXAG
	ON_C4_cmpltei"		ON_M4_mpyrr_addi"
	case 'u': // 1 string to match.		case 'r': // 1 string to match.
	return Intrinsic::hexagon_C4_cmplteu; // "__builtin_HEXAG		return Intrinsic::hexagon_M4_mpyrr_addr; // "__builtin_HEXAG
	ON_C4_cmplteu"		ON_M4_mpyrr_addr"
	}		}
	break;		break;
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "eqi", 3))
	break;
	return Intrinsic::hexagon_C4_cmpneqi; // "__builtin_HEXAG
	ON_C4_cmpneqi"
	}		}
	break;		break;
	case 'o': // 1 string to match.		case 'v': // 5 strings to match.
	if (memcmp(BuiltinName.data()+22, "r_andn", 6))		switch (BuiltinName[22]) {
	break;
	return Intrinsic::hexagon_C4_or_andn; // "__builtin_HEXAG
	ON_C4_or_andn"
	}
	break;
	}
	break;
	case 'F': // 14 strings to match.
	if (memcmp(BuiltinName.data()+19, "2_", 2))
	break;
	switch (BuiltinName[21]) {
	default: break;
	case 'd': // 7 strings to match.
	if (BuiltinName[22] != 'f')
	break;
	switch (BuiltinName[23]) {
	default: break;
	case 'c': // 5 strings to match.
	switch (BuiltinName[24]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "ass", 3))		if (memcmp(BuiltinName.data()+23, "mpyh_acc", 8))
	break;		break;
	return Intrinsic::hexagon_F2_dfclass; // "__builtin_HEXAG		return Intrinsic::hexagon_M4_vpmpyh_acc; // "__builtin_HEXAG
	ON_F2_dfclass"		ON_M4_vpmpyh_acc"
	case 'm': // 4 strings to match.		case 'r': // 4 strings to match.
	if (BuiltinName[25] != 'p')		if (memcmp(BuiltinName.data()+23, "mpy", 3))
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'e': // 2 strings to match.
	if (BuiltinName[27] != 'q')		if (memcmp(BuiltinName.data()+27, "h_s", 3))
	break;		break;
	return Intrinsic::hexagon_F2_dfcmpeq; // "__builtin_HEXAG		switch (BuiltinName[30]) {
	ON_F2_dfcmpeq"
	case 'g': // 2 strings to match.
	switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_F2_dfcmpge; // "__builtin_HEXAG		return Intrinsic::hexagon_M4_vrmpyeh_s0; // "__built
	ON_F2_dfcmpge"		in_HEXAGON_M4_vrmpyeh_s0"
	case 't': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_F2_dfcmpgt; // "__builtin_HEXAG		return Intrinsic::hexagon_M4_vrmpyeh_s1; // "__built
	ON_F2_dfcmpgt"		in_HEXAGON_M4_vrmpyeh_s1"
	}		}
	break;		break;
	case 'u': // 1 string to match.		case 'o': // 2 strings to match.
	if (BuiltinName[27] != 'o')		if (memcmp(BuiltinName.data()+27, "h_s", 3))
	break;
	return Intrinsic::hexagon_F2_dfcmpuo; // "__builtin_HEXAG
	ON_F2_dfcmpuo"
	}
	break;
	}
	break;
	case 'i': // 2 strings to match.
	if (memcmp(BuiltinName.data()+24, "mm_", 3))
	break;
	switch (BuiltinName[27]) {
	default: break;
	case 'n': // 1 string to match.
	return Intrinsic::hexagon_F2_dfimm_n; // "__builtin_HEXAG
	ON_F2_dfimm_n"
	case 'p': // 1 string to match.
	return Intrinsic::hexagon_F2_dfimm_p; // "__builtin_HEXAG
	ON_F2_dfimm_p"
	}
	break;
	}
	break;
	case 's': // 7 strings to match.
	if (BuiltinName[22] != 'f')
	break;
	switch (BuiltinName[23]) {
	default: break;
	case 'c': // 5 strings to match.
	switch (BuiltinName[24]) {
	default: break;
	case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "ass", 3))
	break;
	return Intrinsic::hexagon_F2_sfclass; // "__builtin_HEXAG
	ON_F2_sfclass"
	case 'm': // 4 strings to match.
	if (BuiltinName[25] != 'p')
	break;
	switch (BuiltinName[26]) {
	default: break;
	case 'e': // 1 string to match.
	if (BuiltinName[27] != 'q')
	break;		break;
	return Intrinsic::hexagon_F2_sfcmpeq; // "__builtin_HEXAG		switch (BuiltinName[30]) {
	ON_F2_sfcmpeq"
	case 'g': // 2 strings to match.
	switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_F2_sfcmpge; // "__builtin_HEXAG		return Intrinsic::hexagon_M4_vrmpyoh_s0; // "__built
	ON_F2_sfcmpge"		in_HEXAGON_M4_vrmpyoh_s0"
	case 't': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_F2_sfcmpgt; // "__builtin_HEXAG		return Intrinsic::hexagon_M4_vrmpyoh_s1; // "__built
	ON_F2_sfcmpgt"		in_HEXAGON_M4_vrmpyoh_s1"
	}		}
	break;		break;
	case 'u': // 1 string to match.
	if (BuiltinName[27] != 'o')
	break;
	return Intrinsic::hexagon_F2_sfcmpuo; // "__builtin_HEXAG
	ON_F2_sfcmpuo"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'i': // 2 strings to match.
	if (memcmp(BuiltinName.data()+24, "mm_", 3))
	break;
	switch (BuiltinName[27]) {
	default: break;
	case 'n': // 1 string to match.
	return Intrinsic::hexagon_F2_sfimm_n; // "__builtin_HEXAG
	ON_F2_sfimm_n"
	case 'p': // 1 string to match.
	return Intrinsic::hexagon_F2_sfimm_p; // "__builtin_HEXAG
	ON_F2_sfimm_p"
	}
	break;
	}
	break;
	}
	break;
	case 'M': // 11 strings to match.
	switch (BuiltinName[19]) {
	default: break;
	case '2': // 3 strings to match.
	if (BuiltinName[20] != '_')
	break;
	switch (BuiltinName[21]) {
	default: break;
	case 'm': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "pyu_up", 6))
	break;
	return Intrinsic::hexagon_M2_mpyu_up; // "__builtin_HEXAG
	ON_M2_mpyu_up"
	case 'v': // 2 strings to match.
	switch (BuiltinName[22]) {
	default: break;
	case 'm': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "ac2es", 5))
	break;
	return Intrinsic::hexagon_M2_vmac2es; // "__builtin_HEXAG
	ON_M2_vmac2es"
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "adduh", 5))
	break;
	return Intrinsic::hexagon_M2_vradduh; // "__builtin_HEXAG
	ON_M2_vradduh"
	}
	break;
	}
	break;
	case '4': // 4 strings to match.
	if (BuiltinName[20] != '_')
	break;
	switch (BuiltinName[21]) {
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "nd_", 3))
	break;
	switch (BuiltinName[25]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "nd", 2))
	break;
	return Intrinsic::hexagon_M4_and_and; // "__builtin_HEXAG
	ON_M4_and_and"
	case 'x': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "or", 2))
	break;
	return Intrinsic::hexagon_M4_and_xor; // "__builtin_HEXAG
	ON_M4_and_xor"
	}
	break;
	case 'o': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "r_andn", 6))
	break;
	return Intrinsic::hexagon_M4_or_andn; // "__builtin_HEXAG
	ON_M4_or_andn"
	case 'x': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "or_and", 6))
	break;
	return Intrinsic::hexagon_M4_xor_and; // "__builtin_HEXAG
	ON_M4_xor_and"
	}
	break;
	case '5': // 4 strings to match.
	if (memcmp(BuiltinName.data()+20, "_vm", 3))
	break;
	switch (BuiltinName[23]) {
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+24, "cb", 2))
	break;
	switch (BuiltinName[26]) {
	default: break;
	case 's': // 1 string to match.
	if (BuiltinName[27] != 'u')
	break;
	return Intrinsic::hexagon_M5_vmacbsu; // "__builtin_HEXAG
	ON_M5_vmacbsu"
	case 'u': // 1 string to match.
	if (BuiltinName[27] != 'u')
	break;
	return Intrinsic::hexagon_M5_vmacbuu; // "__builtin_HEXAG
	ON_M5_vmacbuu"
	}
	break;
	case 'p': // 2 strings to match.
	if (memcmp(BuiltinName.data()+24, "yb", 2))
	break;
	switch (BuiltinName[26]) {
	default: break;
	case 's': // 1 string to match.
	if (BuiltinName[27] != 'u')
	break;
	return Intrinsic::hexagon_M5_vmpybsu; // "__builtin_HEXAG
	ON_M5_vmpybsu"
	case 'u': // 1 string to match.
	if (BuiltinName[27] != 'u')
	break;
	return Intrinsic::hexagon_M5_vmpybuu; // "__builtin_HEXAG
	ON_M5_vmpybuu"
	}
	break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'S': // 30 strings to match.		case 'S': // 23 strings to match.
	switch (BuiltinName[19]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case '2': // 25 strings to match.		case '2': // 17 strings to match.
	if (BuiltinName[20] != '_')		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'a': // 8 strings to match.		case 'a': // 8 strings to match.
	if (BuiltinName[22] != 's')		if (BuiltinName[22] != 's')
	break;		break;
	switch (BuiltinName[23]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'l': // 4 strings to match.		case 'l': // 4 strings to match.
	if (BuiltinName[24] != '_')		if (BuiltinName[24] != '_')
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'i': // 2 strings to match.		case 'i': // 2 strings to match.
	if (BuiltinName[26] != '_')		if (BuiltinName[26] != '_')
	break;		break;
	switch (BuiltinName[27]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'p': // 1 string to match.
	return Intrinsic::hexagon_S2_asl_i_p; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+28, "_or", 3))
	ON_S2_asl_i_p"		break;
			return Intrinsic::hexagon_S2_asl_i_p_or; // "__built
			in_HEXAGON_S2_asl_i_p_or"
	case 'r': // 1 string to match.		case 'r': // 1 string to match.
	return Intrinsic::hexagon_S2_asl_i_r; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+28, "_or", 3))
	ON_S2_asl_i_r"		break;
			return Intrinsic::hexagon_S2_asl_i_r_or; // "__built
			in_HEXAGON_S2_asl_i_r_or"
	}		}
	break;		break;
	case 'r': // 2 strings to match.		case 'r': // 2 strings to match.
	if (BuiltinName[26] != '_')		if (BuiltinName[26] != '_')
	break;		break;
	switch (BuiltinName[27]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'p': // 1 string to match.
	return Intrinsic::hexagon_S2_asl_r_p; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+28, "_or", 3))
	ON_S2_asl_r_p"		break;
			return Intrinsic::hexagon_S2_asl_r_p_or; // "__built
			in_HEXAGON_S2_asl_r_p_or"
	case 'r': // 1 string to match.		case 'r': // 1 string to match.
	return Intrinsic::hexagon_S2_asl_r_r; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+28, "_or", 3))
	ON_S2_asl_r_r"		break;
			return Intrinsic::hexagon_S2_asl_r_r_or; // "__built
			in_HEXAGON_S2_asl_r_r_or"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'r': // 4 strings to match.		case 'r': // 4 strings to match.
	if (BuiltinName[24] != '_')		if (BuiltinName[24] != '_')
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'i': // 2 strings to match.		case 'i': // 2 strings to match.
	if (BuiltinName[26] != '_')		if (BuiltinName[26] != '_')
	break;		break;
	switch (BuiltinName[27]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'p': // 1 string to match.
	return Intrinsic::hexagon_S2_asr_i_p; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+28, "_or", 3))
	ON_S2_asr_i_p"		break;
			return Intrinsic::hexagon_S2_asr_i_p_or; // "__built
			in_HEXAGON_S2_asr_i_p_or"
	case 'r': // 1 string to match.		case 'r': // 1 string to match.
	return Intrinsic::hexagon_S2_asr_i_r; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+28, "_or", 3))
	ON_S2_asr_i_r"		break;
			return Intrinsic::hexagon_S2_asr_i_r_or; // "__built
			in_HEXAGON_S2_asr_i_r_or"
	}		}
	break;		break;
	case 'r': // 2 strings to match.		case 'r': // 2 strings to match.
	if (BuiltinName[26] != '_')		if (BuiltinName[26] != '_')
	break;		break;
	switch (BuiltinName[27]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'p': // 1 string to match.
	return Intrinsic::hexagon_S2_asr_r_p; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+28, "_or", 3))
	ON_S2_asr_r_p"		break;
			return Intrinsic::hexagon_S2_asr_r_p_or; // "__built
			in_HEXAGON_S2_asr_r_p_or"
	case 'r': // 1 string to match.		case 'r': // 1 string to match.
	return Intrinsic::hexagon_S2_asr_r_r; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+28, "_or", 3))
	ON_S2_asr_r_r"		break;
			return Intrinsic::hexagon_S2_asr_r_r_or; // "__built
			in_HEXAGON_S2_asr_r_r_or"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'c': // 1 string to match.		case 'i': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "lbnorm", 6))		if (BuiltinName[22] != 'n')
	break;
	return Intrinsic::hexagon_S2_clbnorm; // "__builtin_HEXAG
	ON_S2_clbnorm"
	case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "nsertp", 6))
	break;		break;
	return Intrinsic::hexagon_S2_insertp; // "__builtin_HEXAG		switch (BuiltinName[23]) {
	ON_S2_insertp"		default: break;
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "ertp_rp", 7))
			break;
			return Intrinsic::hexagon_S2_insertp_rp; // "__builtin_HEXAG
			ON_S2_insertp_rp"
			case 't': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "erleave", 7))
			break;
			return Intrinsic::hexagon_S2_interleave; // "__builtin_HEXAG
			ON_S2_interleave"
			}
			break;
	case 'l': // 6 strings to match.		case 'l': // 6 strings to match.
	if (BuiltinName[22] != 's')		if (BuiltinName[22] != 's')
	break;		break;
	switch (BuiltinName[23]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'l': // 2 strings to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+24, "_r_", 3))		if (memcmp(BuiltinName.data()+24, "_r_", 3))
	break;		break;
	switch (BuiltinName[27]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'p': // 1 string to match.
	return Intrinsic::hexagon_S2_lsl_r_p; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+28, "_or", 3))
	ON_S2_lsl_r_p"
	case 'r': // 1 string to match.
	return Intrinsic::hexagon_S2_lsl_r_r; // "__builtin_HEXAG
	ON_S2_lsl_r_r"
	}
	break;
	case 'r': // 4 strings to match.
	if (BuiltinName[24] != '_')
	break;
	switch (BuiltinName[25]) {
	default: break;
	case 'i': // 2 strings to match.
	if (BuiltinName[26] != '_')
	break;		break;
	switch (BuiltinName[27]) {		return Intrinsic::hexagon_S2_lsl_r_p_or; // "__builtin_HEXAG
	default: break;		ON_S2_lsl_r_p_or"
	case 'p': // 1 string to match.		case 'r': // 1 string to match.
	return Intrinsic::hexagon_S2_lsr_i_p; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+28, "_or", 3))
	ON_S2_lsr_i_p"
	case 'r': // 1 string to match.
	return Intrinsic::hexagon_S2_lsr_i_r; // "__builtin_HEXAG
	ON_S2_lsr_i_r"
	}
	break;
	case 'r': // 2 strings to match.
	if (BuiltinName[26] != '_')
	break;		break;
	switch (BuiltinName[27]) {		return Intrinsic::hexagon_S2_lsl_r_r_or; // "__builtin_HEXAG
	default: break;		ON_S2_lsl_r_r_or"
	case 'p': // 1 string to match.		}
	return Intrinsic::hexagon_S2_lsr_r_p; // "__builtin_HEXAG		break;
	ON_S2_lsr_r_p"		case 'r': // 4 strings to match.
	case 'r': // 1 string to match.		if (BuiltinName[24] != '_')
	return Intrinsic::hexagon_S2_lsr_r_r; // "__builtin_HEXAG
	ON_S2_lsr_r_r"
	}
	break;
	}
	break;
	}
	break;
	case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "arityp", 6))
	break;
	return Intrinsic::hexagon_S2_parityp; // "__builtin_HEXAG
	ON_S2_parityp"
	case 's': // 5 strings to match.
	switch (BuiltinName[22]) {
	default: break;
	case 'h': // 4 strings to match.
	if (memcmp(BuiltinName.data()+23, "uff", 3))
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'e': // 2 strings to match.		case 'i': // 2 strings to match.
			if (BuiltinName[26] != '_')
			break;
	switch (BuiltinName[27]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'p': // 1 string to match.
	return Intrinsic::hexagon_S2_shuffeb; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+28, "_or", 3))
	ON_S2_shuffeb"		break;
	case 'h': // 1 string to match.		return Intrinsic::hexagon_S2_lsr_i_p_or; // "__built
	return Intrinsic::hexagon_S2_shuffeh; // "__builtin_HEXAG		in_HEXAGON_S2_lsr_i_p_or"
	ON_S2_shuffeh"		case 'r': // 1 string to match.
			if (memcmp(BuiltinName.data()+28, "_or", 3))
			break;
			return Intrinsic::hexagon_S2_lsr_i_r_or; // "__built
			in_HEXAGON_S2_lsr_i_r_or"
	}		}
	break;		break;
	case 'o': // 2 strings to match.		case 'r': // 2 strings to match.
			if (BuiltinName[26] != '_')
			break;
	switch (BuiltinName[27]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'p': // 1 string to match.
	return Intrinsic::hexagon_S2_shuffob; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+28, "_or", 3))
	ON_S2_shuffob"		break;
	case 'h': // 1 string to match.		return Intrinsic::hexagon_S2_lsr_r_p_or; // "__built
	return Intrinsic::hexagon_S2_shuffoh; // "__builtin_HEXAG		in_HEXAGON_S2_lsr_r_p_or"
	ON_S2_shuffoh"		case 'r': // 1 string to match.
			if (memcmp(BuiltinName.data()+28, "_or", 3))
			break;
			return Intrinsic::hexagon_S2_lsr_r_r_or; // "__built
			in_HEXAGON_S2_lsr_r_r_or"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'v': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "sathb", 5))
	break;
	return Intrinsic::hexagon_S2_svsathb; // "__builtin_HEXAG
	ON_S2_svsathb"
	}		}
	break;		break;
	case 'v': // 3 strings to match.		case 'v': // 1 string to match.
	switch (BuiltinName[22]) {		if (memcmp(BuiltinName.data()+22, "rndpackwh", 9))
	default: break;
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "cnegh", 5))
	break;
	return Intrinsic::hexagon_S2_vrcnegh; // "__builtin_HEXAG
	ON_S2_vrcnegh"
	case 's': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "at", 2))
	break;
	switch (BuiltinName[25]) {
	default: break;
	case 'h': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "ub", 2))
	break;
	return Intrinsic::hexagon_S2_vsathub; // "__builtin_HEXAG
	ON_S2_vsathub"
	case 'w': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "uh", 2))
	break;
	return Intrinsic::hexagon_S2_vsatwuh; // "__builtin_HEXAG
	ON_S2_vsatwuh"
	}
	break;		break;
	}		return Intrinsic::hexagon_S2_vrndpackwh; // "__builtin_HEXAG
	break;		ON_S2_vrndpackwh"
	}		}
	break;		break;
	case '4': // 5 strings to match.		case '4': // 5 strings to match.
	if (BuiltinName[20] != '_')		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "ddaddi", 6))
	break;
	return Intrinsic::hexagon_S4_addaddi; // "__builtin_HEXAG
	ON_S4_addaddi"
	case 'c': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "lbaddi", 6))
	break;
	return Intrinsic::hexagon_S4_clbaddi; // "__builtin_HEXAG
	ON_S4_clbaddi"
	case 'e': // 1 string to match.		case 'e': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "xtract", 6))		if (memcmp(BuiltinName.data()+22, "xtract_rp", 9))
	break;		break;
	return Intrinsic::hexagon_S4_extract; // "__builtin_HEXAG		return Intrinsic::hexagon_S4_extract_rp; // "__builtin_HEXAG
	ON_S4_extract"		ON_S4_extract_rp"
	case 'o': // 1 string to match.		case 'o': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "r_andi", 6))		if (memcmp(BuiltinName.data()+22, "ri_", 3))
	break;		break;
	return Intrinsic::hexagon_S4_or_andi; // "__builtin_HEXAG		switch (BuiltinName[25]) {
	ON_S4_or_andi"		default: break;
	case 's': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "ubaddi", 6))		if (memcmp(BuiltinName.data()+26, "sl_ri", 5))
			break;
			return Intrinsic::hexagon_S4_ori_asl_ri; // "__builtin_HEXAG
			ON_S4_ori_asl_ri"
			case 'l': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "sr_ri", 5))
			break;
			return Intrinsic::hexagon_S4_ori_lsr_ri; // "__builtin_HEXAG
			ON_S4_ori_lsr_ri"
			}
			break;
			case 'v': // 2 strings to match.
			if (BuiltinName[22] != 'x')
	break;		break;
	return Intrinsic::hexagon_S4_subaddi; // "__builtin_HEXAG		switch (BuiltinName[23]) {
	ON_S4_subaddi"		default: break;
			case 'a': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "ddsubhr", 7))
			break;
			return Intrinsic::hexagon_S4_vxaddsubhr; // "__builtin_HEXAG
			ON_S4_vxaddsubhr"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "ubaddhr", 7))
			break;
			return Intrinsic::hexagon_S4_vxsubaddhr; // "__builtin_HEXAG
			ON_S4_vxsubaddhr"
			}
			break;
	}		}
	break;		break;
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "_asrhub_sat", 11))
			break;
			return Intrinsic::hexagon_S5_asrhub_sat; // "__builtin_HEXAG
			ON_S5_asrhub_sat"
	}		}
	break;		break;
	}		}
	break;		break;
	case 29: // 103 strings to match.		case 32: // 96 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))		if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
	break;		break;
	switch (BuiltinName[18]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'A': // 26 strings to match.		case 'A': // 16 strings to match.
	switch (BuiltinName[19]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case '2': // 11 strings to match.		case '2': // 14 strings to match.
	if (BuiltinName[20] != '_')		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'c': // 1 string to match.		case 'a': // 6 strings to match.
	if (memcmp(BuiltinName.data()+22, "ombinew", 7))		if (memcmp(BuiltinName.data()+22, "ddh_", 4))
	break;
	return Intrinsic::hexagon_A2_combinew; // "__builtin_HEXAG
	ON_A2_combinew"
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "oundsat", 7))
	break;
	return Intrinsic::hexagon_A2_roundsat; // "__builtin_HEXAG
	ON_A2_roundsat"
	case 's': // 2 strings to match.
	if (BuiltinName[22] != 'v')
	break;		break;
	switch (BuiltinName[23]) {		switch (BuiltinName[26]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "dduhs", 5))
	break;
	return Intrinsic::hexagon_A2_svadduhs; // "__builtin_HEXAG
	ON_A2_svadduhs"
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "ubuhs", 5))
	break;
	return Intrinsic::hexagon_A2_svsubuhs; // "__builtin_HEXAG
	ON_A2_svsubuhs"
	}
	break;
	case 'v': // 7 strings to match.
	switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'h': // 4 strings to match.
	if (memcmp(BuiltinName.data()+23, "bs", 2))		if (memcmp(BuiltinName.data()+27, "16_", 3))
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[30]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+26, "sat", 3))		switch (BuiltinName[31]) {
	break;		default: break;
	return Intrinsic::hexagon_A2_vabshsat; // "__builtin_HEXAG		case 'h': // 1 string to match.
	ON_A2_vabshsat"		return Intrinsic::hexagon_A2_addh_h16_hh; // "__built
	case 'w': // 1 string to match.		in_HEXAGON_A2_addh_h16_hh"
	if (memcmp(BuiltinName.data()+26, "sat", 3))		case 'l': // 1 string to match.
	break;		return Intrinsic::hexagon_A2_addh_h16_hl; // "__built
	return Intrinsic::hexagon_A2_vabswsat; // "__builtin_HEXAG		in_HEXAGON_A2_addh_h16_hl"
	ON_A2_vabswsat"		}
	}		break;
	break;		case 'l': // 2 strings to match.
	case 'c': // 3 strings to match.		switch (BuiltinName[31]) {
	if (memcmp(BuiltinName.data()+23, "mp", 2))		default: break;
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_A2_addh_h16_lh; // "__built
			in_HEXAGON_A2_addh_h16_lh"
			case 'l': // 1 string to match.
			return Intrinsic::hexagon_A2_addh_h16_ll; // "__built
			in_HEXAGON_A2_addh_h16_ll"
			}
	break;		break;
	switch (BuiltinName[25]) {
	default: break;
	case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "gtu", 3))
	break;
	return Intrinsic::hexagon_A2_vcmpbgtu; // "__builtin_HEXAG
	ON_A2_vcmpbgtu"
	case 'h': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "gtu", 3))
	break;
	return Intrinsic::hexagon_A2_vcmphgtu; // "__builtin_HEXAG
	ON_A2_vcmphgtu"
	case 'w': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "gtu", 3))
	break;
	return Intrinsic::hexagon_A2_vcmpwgtu; // "__builtin_HEXAG
	ON_A2_vcmpwgtu"
	}		}
	break;		break;
	case 'n': // 2 strings to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "avg", 3))		if (memcmp(BuiltinName.data()+27, "16_", 3))
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[30]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'h': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "cr", 2))		if (BuiltinName[31] != 'l')
	break;		break;
	return Intrinsic::hexagon_A2_vnavghcr; // "__builtin_HEXAG		return Intrinsic::hexagon_A2_addh_l16_hl; // "__built
	ON_A2_vnavghcr"		in_HEXAGON_A2_addh_l16_hl"
	case 'w': // 1 string to match.		case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "cr", 2))		if (BuiltinName[31] != 'l')
	break;		break;
	return Intrinsic::hexagon_A2_vnavgwcr; // "__builtin_HEXAG ON_A2_vnavgwcr"		return Intrinsic::hexagon_A2_addh_l16_ll; // "__built in_HEXAGON_A2_addh_l16_ll"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 's': // 6 strings to match.
	break;		if (memcmp(BuiltinName.data()+22, "ubh_", 4))
	case '4': // 14 strings to match.
	if (BuiltinName[20] != '_')
	break;
	switch (BuiltinName[21]) {
	default: break;
	case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "itsplit", 7))
	break;
	return Intrinsic::hexagon_A4_bitsplit; // "__builtin_HEXAG
	ON_A4_bitsplit"
	case 'c': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "mp", 2))
	break;		break;
	switch (BuiltinName[24]) {		switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'h': // 4 strings to match.
	if (memcmp(BuiltinName.data()+25, "gtui", 4))		if (memcmp(BuiltinName.data()+27, "16_", 3))
	break;
	return Intrinsic::hexagon_A4_cmpbgtui; // "__builtin_HEXAG
	ON_A4_cmpbgtui"
	case 'h': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "gtui", 4))
	break;		break;
	return Intrinsic::hexagon_A4_cmphgtui; // "__builtin_HEXAG		switch (BuiltinName[30]) {
	ON_A4_cmphgtui"		default: break;
	}		case 'h': // 2 strings to match.
	break;		switch (BuiltinName[31]) {
	case 'm': // 1 string to match.		default: break;
	if (memcmp(BuiltinName.data()+22, "odwrapu", 7))		case 'h': // 1 string to match.
	break;		return Intrinsic::hexagon_A2_subh_h16_hh; // "__built
	return Intrinsic::hexagon_A4_modwrapu; // "__builtin_HEXAG		in_HEXAGON_A2_subh_h16_hh"
	ON_A4_modwrapu"		case 'l': // 1 string to match.
	case 'r': // 3 strings to match.		return Intrinsic::hexagon_A2_subh_h16_hl; // "__built
	switch (BuiltinName[22]) {		in_HEXAGON_A2_subh_h16_hl"
	default: break;		}
	case 'c': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "mpneqi", 6))
	break;		break;
	return Intrinsic::hexagon_A4_rcmpneqi; // "__builtin_HEXAG		case 'l': // 2 strings to match.
	ON_A4_rcmpneqi"		switch (BuiltinName[31]) {
	case 'o': // 2 strings to match.		default: break;
	if (memcmp(BuiltinName.data()+23, "und_r", 5))		case 'h': // 1 string to match.
			return Intrinsic::hexagon_A2_subh_h16_lh; // "__built
			in_HEXAGON_A2_subh_h16_lh"
			case 'l': // 1 string to match.
			return Intrinsic::hexagon_A2_subh_h16_ll; // "__built
			in_HEXAGON_A2_subh_h16_ll"
			}
	break;		break;
	switch (BuiltinName[28]) {
	default: break;
	case 'i': // 1 string to match.
	return Intrinsic::hexagon_A4_round_ri; // "__builtin_HEXAG
	ON_A4_round_ri"
	case 'r': // 1 string to match.
	return Intrinsic::hexagon_A4_round_rr; // "__builtin_HEXAG
	ON_A4_round_rr"
	}
	break;
	}
	break;
	case 't': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "lbmatch", 7))
	break;
	return Intrinsic::hexagon_A4_tlbmatch; // "__builtin_HEXAG
	ON_A4_tlbmatch"
	case 'v': // 6 strings to match.
	if (memcmp(BuiltinName.data()+22, "cmp", 3))
	break;
	switch (BuiltinName[25]) {
	default: break;
	case 'b': // 2 strings to match.
	switch (BuiltinName[26]) {
	default: break;
	case 'e': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "qi", 2))
	break;
	return Intrinsic::hexagon_A4_vcmpbeqi; // "__builtin_HEXAG
	ON_A4_vcmpbeqi"
	case 'g': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "ti", 2))
	break;
	return Intrinsic::hexagon_A4_vcmpbgti; // "__builtin_HEXAG
	ON_A4_vcmpbgti"
	}		}
	break;		break;
	case 'h': // 2 strings to match.		case 'l': // 2 strings to match.
	switch (BuiltinName[26]) {		if (memcmp(BuiltinName.data()+27, "16_", 3))
	default: break;		break;
	case 'e': // 1 string to match.		switch (BuiltinName[30]) {
	if (memcmp(BuiltinName.data()+27, "qi", 2))
	break;
	return Intrinsic::hexagon_A4_vcmpheqi; // "__builtin_HEXAG
	ON_A4_vcmpheqi"
	case 'g': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "ti", 2))
	break;
	return Intrinsic::hexagon_A4_vcmphgti; // "__builtin_HEXAG
	ON_A4_vcmphgti"
	}
	break;
	case 'w': // 2 strings to match.
	switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'h': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "qi", 2))		if (BuiltinName[31] != 'l')
	break;		break;
	return Intrinsic::hexagon_A4_vcmpweqi; // "__builtin_HEXAG		return Intrinsic::hexagon_A2_subh_l16_hl; // "__built
	ON_A4_vcmpweqi"		in_HEXAGON_A2_subh_l16_hl"
	case 'g': // 1 string to match.		case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "ti", 2))		if (BuiltinName[31] != 'l')
	break;		break;
	return Intrinsic::hexagon_A4_vcmpwgti; // "__builtin_HEXAG ON_A4_vcmpwgti"		return Intrinsic::hexagon_A2_subh_l16_ll; // "__built in_HEXAGON_A2_subh_l16_ll"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'v': // 2 strings to match.
	break;		if (BuiltinName[22] != 'r')
	case '5': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "_vaddhubs", 9))
	break;
	return Intrinsic::hexagon_A5_vaddhubs; // "__builtin_HEXAGON_A5_va
	ddhubs"
	}
	break;
	case 'C': // 5 strings to match.
	switch (BuiltinName[19]) {
	default: break;
	case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "_bitsclri", 9))
	break;
	return Intrinsic::hexagon_C2_bitsclri; // "__builtin_HEXAGON_C2_bi
	tsclri"
	case '4': // 4 strings to match.
	if (BuiltinName[20] != '_')
	break;
	switch (BuiltinName[21]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "nd_andn", 7))
	break;
	return Intrinsic::hexagon_C4_and_andn; // "__builtin_HEXAG
	ON_C4_and_andn"
	case 'c': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "mplteui", 7))
	break;
	return Intrinsic::hexagon_C4_cmplteui; // "__builtin_HEXAG
	ON_C4_cmplteui"
	case 'n': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "bits", 4))
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'c': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "lr", 2))		if (memcmp(BuiltinName.data()+24, "ddub_acc", 8))
	break;		break;
	return Intrinsic::hexagon_C4_nbitsclr; // "__builtin_HEXAG ON_C4_nbitsclr"		return Intrinsic::hexagon_A2_vraddub_acc; // "__builtin_HEXAG ON_A2_vraddub_acc"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "et", 2))		if (memcmp(BuiltinName.data()+24, "adub_acc", 8))
	break;		break;
	return Intrinsic::hexagon_C4_nbitsset; // "__builtin_HEXAG		return Intrinsic::hexagon_A2_vrsadub_acc; // "__builtin_HEXAG
	ON_C4_nbitsset"		ON_A2_vrsadub_acc"
	}
	break;
	}
	break;
	}
	break;
	case 'F': // 8 strings to match.
	if (memcmp(BuiltinName.data()+19, "2_", 2))
	break;
	switch (BuiltinName[21]) {
	default: break;
	case 'd': // 4 strings to match.
	if (memcmp(BuiltinName.data()+22, "ff", 2))
	break;
	switch (BuiltinName[24]) {
	default: break;
	case 'i': // 3 strings to match.
	if (memcmp(BuiltinName.data()+25, "xup", 3))
	break;
	switch (BuiltinName[28]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::hexagon_F2_dffixupd; // "__builtin_HEXAG
	ON_F2_dffixupd"
	case 'n': // 1 string to match.
	return Intrinsic::hexagon_F2_dffixupn; // "__builtin_HEXAG
	ON_F2_dffixupn"
	case 'r': // 1 string to match.
	return Intrinsic::hexagon_F2_dffixupr; // "__builtin_HEXAG
	ON_F2_dffixupr"
	}		}
	break;		break;
	case 'm': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "a_sc", 4))
	break;
	return Intrinsic::hexagon_F2_dffma_sc; // "__builtin_HEXAG
	ON_F2_dffma_sc"
	}		}
	break;		break;
	case 's': // 4 strings to match.		case '4': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "ff", 2))		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[24]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'i': // 3 strings to match.		case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "xup", 3))		if (memcmp(BuiltinName.data()+22, "oundscheck", 10))
	break;		break;
	switch (BuiltinName[28]) {		return Intrinsic::hexagon_A4_boundscheck; // "__builtin_HEXAG
	default: break;		ON_A4_boundscheck"
	case 'd': // 1 string to match.		case 'v': // 1 string to match.
	return Intrinsic::hexagon_F2_sffixupd; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+22, "cmpbeq_any", 10))
	ON_F2_sffixupd"
	case 'n': // 1 string to match.
	return Intrinsic::hexagon_F2_sffixupn; // "__builtin_HEXAG
	ON_F2_sffixupn"
	case 'r': // 1 string to match.
	return Intrinsic::hexagon_F2_sffixupr; // "__builtin_HEXAG
	ON_F2_sffixupr"
	}
	break;
	case 'm': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "a_sc", 4))
	break;		break;
	return Intrinsic::hexagon_F2_sffma_sc; // "__builtin_HEXAG ON_F2_sffma_sc"		return Intrinsic::hexagon_A4_vcmpbeq_any; // "__builtin_HEXAG ON_A4_vcmpbeq_any"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'M': // 29 strings to match.		case 'C': // 1 string to match.
	switch (BuiltinName[19]) {		if (memcmp(BuiltinName.data()+19, "4_fastcorner9", 13))
			break;
			return Intrinsic::hexagon_C4_fastcorner9; // "__builtin_HEXAG
			ON_C4_fastcorner9"
			case 'M': // 16 strings to match.
			if (memcmp(BuiltinName.data()+19, "2_", 2))
			break;
			switch (BuiltinName[21]) {
	default: break;		default: break;
	case '2': // 18 strings to match.		case 'm': // 12 strings to match.
	if (BuiltinName[20] != '_')		switch (BuiltinName[22]) {
	break;
	switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'c': // 10 strings to match.		case 'm': // 4 strings to match.
	switch (BuiltinName[22]) {		if (memcmp(BuiltinName.data()+23, "acu", 3))
	default: break;		break;
	case 'm': // 8 strings to match.		switch (BuiltinName[26]) {
	switch (BuiltinName[23]) {		default: break;
	default: break;		case 'h': // 2 strings to match.
	case 'a': // 4 strings to match.		if (memcmp(BuiltinName.data()+27, "s_rs", 4))
	if (BuiltinName[24] != 'c')
	break;
	switch (BuiltinName[25]) {
	default: break;
	case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "_s0", 3))
	break;
	return Intrinsic::hexagon_M2_cmaci_s0; // "__builtin_HEXAG
	ON_M2_cmaci_s0"
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "_s0", 3))
	break;
	return Intrinsic::hexagon_M2_cmacr_s0; // "__builtin_HEXAG
	ON_M2_cmacr_s0"
	case 's': // 2 strings to match.
	if (memcmp(BuiltinName.data()+26, "_s", 2))
	break;
	switch (BuiltinName[28]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_cmacs_s0; // "__built
	in_HEXAGON_M2_cmacs_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_cmacs_s1; // "__built
	in_HEXAGON_M2_cmacs_s1"
	}
	break;
	}
	break;
	case 'p': // 4 strings to match.
	if (BuiltinName[24] != 'y')
	break;
	switch (BuiltinName[25]) {
	default: break;
	case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "_s0", 3))
	break;
	return Intrinsic::hexagon_M2_cmpyi_s0; // "__builtin_HEXAG
	ON_M2_cmpyi_s0"
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "_s0", 3))
	break;
	return Intrinsic::hexagon_M2_cmpyr_s0; // "__builtin_HEXAG
	ON_M2_cmpyr_s0"
	case 's': // 2 strings to match.
	if (memcmp(BuiltinName.data()+26, "_s", 2))
	break;
	switch (BuiltinName[28]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_cmpys_s0; // "__built
	in_HEXAGON_M2_cmpys_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_cmpys_s1; // "__built
	in_HEXAGON_M2_cmpys_s1"
	}
	break;
	}
	break;		break;
			switch (BuiltinName[31]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mmacuhs_rs0; // "__built
			in_HEXAGON_M2_mmacuhs_rs0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mmacuhs_rs1; // "__built
			in_HEXAGON_M2_mmacuhs_rs1"
	}		}
	break;		break;
	case 'n': // 2 strings to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "acs_s", 5))		if (memcmp(BuiltinName.data()+27, "s_rs", 4))
	break;		break;
	switch (BuiltinName[28]) {		switch (BuiltinName[31]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_cnacs_s0; // "__builtin_HEXAG ON_M2_cnacs_s0"		return Intrinsic::hexagon_M2_mmaculs_rs0; // "__built in_HEXAGON_M2_mmaculs_rs0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_cnacs_s1; // "__builtin_HEXAG ON_M2_cnacs_s1"		return Intrinsic::hexagon_M2_mmaculs_rs1; // "__built in_HEXAGON_M2_mmaculs_rs1"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'm': // 5 strings to match.		case 'p': // 8 strings to match.
	switch (BuiltinName[22]) {		if (memcmp(BuiltinName.data()+23, "yud_", 4))
			break;
			switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'm': // 4 strings to match.		case 'h': // 4 strings to match.
	if (memcmp(BuiltinName.data()+23, "py", 2))		switch (BuiltinName[28]) {
	break;
	switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+26, "_s", 2))		if (memcmp(BuiltinName.data()+29, "_s", 2))
	break;		break;
	switch (BuiltinName[28]) {		switch (BuiltinName[31]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mmpyh_s0; // "__builtin_HEXAG ON_M2_mmpyh_s0"		return Intrinsic::hexagon_M2_mpyud_hh_s0; // "__built in_HEXAGON_M2_mpyud_hh_s0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mmpyh_s1; // "__builtin_HEXAG ON_M2_mmpyh_s1"		return Intrinsic::hexagon_M2_mpyud_hh_s1; // "__built in_HEXAGON_M2_mpyud_hh_s1"
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+26, "_s", 2))		if (memcmp(BuiltinName.data()+29, "_s", 2))
	break;		break;
	switch (BuiltinName[28]) {		switch (BuiltinName[31]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mmpyl_s0; // "__builtin_HEXAG ON_M2_mmpyl_s0"		return Intrinsic::hexagon_M2_mpyud_hl_s0; // "__built in_HEXAGON_M2_mpyud_hl_s0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mmpyl_s1; // "__builtin_HEXAG ON_M2_mmpyl_s1"		return Intrinsic::hexagon_M2_mpyud_hl_s1; // "__built in_HEXAGON_M2_mpyud_hl_s1"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'p': // 1 string to match.		case 'l': // 4 strings to match.
	if (memcmp(BuiltinName.data()+23, "ysu_up", 6))		switch (BuiltinName[28]) {
	break;		default: break;
	return Intrinsic::hexagon_M2_mpysu_up; // "__builtin_HEXAG		case 'h': // 2 strings to match.
	ON_M2_mpysu_up"		if (memcmp(BuiltinName.data()+29, "_s", 2))
	}		break;
	break;		switch (BuiltinName[31]) {
	case 'v': // 2 strings to match.		default: break;
	if (memcmp(BuiltinName.data()+22, "rm", 2))		case '0': // 1 string to match.
	break;		return Intrinsic::hexagon_M2_mpyud_lh_s0; // "__built
	switch (BuiltinName[24]) {		in_HEXAGON_M2_mpyud_lh_s0"
	default: break;		case '1': // 1 string to match.
	case 'a': // 1 string to match.		return Intrinsic::hexagon_M2_mpyud_lh_s1; // "__built
	if (memcmp(BuiltinName.data()+25, "c_s0", 4))		in_HEXAGON_M2_mpyud_lh_s1"
			}
	break;		break;
	return Intrinsic::hexagon_M2_vrmac_s0; // "__builtin_HEXAG		case 'l': // 2 strings to match.
	ON_M2_vrmac_s0"		if (memcmp(BuiltinName.data()+29, "_s", 2))
	case 'p': // 1 string to match.		break;
	if (memcmp(BuiltinName.data()+25, "y_s0", 4))		switch (BuiltinName[31]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyud_ll_s0; // "__built
			in_HEXAGON_M2_mpyud_ll_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyud_ll_s1; // "__built
			in_HEXAGON_M2_mpyud_ll_s1"
			}
	break;		break;
	return Intrinsic::hexagon_M2_vrmpy_s0; // "__builtin_HEXAG		}
	ON_M2_vrmpy_s0"		break;
	}		}
	break;		break;
	case 'x': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "or_xacc", 7))
	break;
	return Intrinsic::hexagon_M2_xor_xacc; // "__builtin_HEXAG
	ON_M2_xor_xacc"
	}		}
	break;		break;
	case '4': // 5 strings to match.		case 'v': // 4 strings to match.
	if (BuiltinName[20] != '_')		if (memcmp(BuiltinName.data()+22, "rcm", 3))
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "nd_andn", 7))		if (BuiltinName[26] != 'c')
	break;
	return Intrinsic::hexagon_M4_and_andn; // "__builtin_HEXAG
	ON_M4_and_andn"
	case 'c': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "mpy", 3))
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'i': // 1 string to match.		case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "_wh", 3))		if (memcmp(BuiltinName.data()+28, "_s0c", 4))
	break;		break;
	return Intrinsic::hexagon_M4_cmpyi_wh; // "__builtin_HEXAG ON_M4_cmpyi_wh"		return Intrinsic::hexagon_M2_vrcmaci_s0c; // "__builtin_HEXAG ON_M2_vrcmaci_s0c"
	case 'r': // 1 string to match.		case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "_wh", 3))		if (memcmp(BuiltinName.data()+28, "_s0c", 4))
	break;
	return Intrinsic::hexagon_M4_cmpyr_wh; // "__builtin_HEXAG
	ON_M4_cmpyr_wh"
	}
	break;
	case 'x': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "or_", 3))
	break;
	switch (BuiltinName[25]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "ndn", 3))
	break;
	return Intrinsic::hexagon_M4_xor_andn; // "__builtin_HEXAG
	ON_M4_xor_andn"
	case 'x': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "acc", 3))
	break;
	return Intrinsic::hexagon_M4_xor_xacc; // "__builtin_HEXAG
	ON_M4_xor_xacc"
	}
	break;
	}
	break;
	case '5': // 6 strings to match.
	if (memcmp(BuiltinName.data()+20, "_v", 2))
	break;
	switch (BuiltinName[22]) {
	default: break;
	case 'd': // 2 strings to match.
	if (BuiltinName[23] != 'm')
	break;
	switch (BuiltinName[24]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "cbsu", 4))
	break;
	return Intrinsic::hexagon_M5_vdmacbsu; // "__builtin_HEXAG
	ON_M5_vdmacbsu"
	case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "ybsu", 4))
	break;		break;
	return Intrinsic::hexagon_M5_vdmpybsu; // "__builtin_HEXAG ON_M5_vdmpybsu"		return Intrinsic::hexagon_M2_vrcmacr_s0c; // "__builtin_HEXAG ON_M2_vrcmacr_s0c"
	}		}
	break;		break;
	case 'r': // 4 strings to match.		case 'p': // 2 strings to match.
	if (BuiltinName[23] != 'm')		if (BuiltinName[26] != 'y')
	break;		break;
	switch (BuiltinName[24]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "cb", 2))		if (memcmp(BuiltinName.data()+28, "_s0c", 4))
	break;		break;
	switch (BuiltinName[27]) {		return Intrinsic::hexagon_M2_vrcmpyi_s0c; // "__builtin_HEXAG
	default: break;		ON_M2_vrcmpyi_s0c"
	case 's': // 1 string to match.		case 'r': // 1 string to match.
	if (BuiltinName[28] != 'u')		if (memcmp(BuiltinName.data()+28, "_s0c", 4))
	break;
	return Intrinsic::hexagon_M5_vrmacbsu; // "__builtin_HEXAG
	ON_M5_vrmacbsu"
	case 'u': // 1 string to match.
	if (BuiltinName[28] != 'u')
	break;
	return Intrinsic::hexagon_M5_vrmacbuu; // "__builtin_HEXAG
	ON_M5_vrmacbuu"
	}
	break;
	case 'p': // 2 strings to match.
	if (memcmp(BuiltinName.data()+25, "yb", 2))
	break;		break;
	switch (BuiltinName[27]) {		return Intrinsic::hexagon_M2_vrcmpyr_s0c; // "__builtin_HEXAG
	default: break;		ON_M2_vrcmpyr_s0c"
	case 's': // 1 string to match.
	if (BuiltinName[28] != 'u')
	break;
	return Intrinsic::hexagon_M5_vrmpybsu; // "__builtin_HEXAG
	ON_M5_vrmpybsu"
	case 'u': // 1 string to match.
	if (BuiltinName[28] != 'u')
	break;
	return Intrinsic::hexagon_M5_vrmpybuu; // "__builtin_HEXAG
	ON_M5_vrmpybuu"
	}
	break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'S': // 35 strings to match.		case 'S': // 63 strings to match.
	switch (BuiltinName[19]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case '2': // 31 strings to match.		case '2': // 56 strings to match.
	if (BuiltinName[20] != '_')		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'a': // 8 strings to match.		case 'a': // 32 strings to match.
	if (BuiltinName[22] != 's')		switch (BuiltinName[22]) {
	break;
	switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'l': // 4 strings to match.		case 'd': // 1 string to match.
	if (BuiltinName[24] != '_')		if (memcmp(BuiltinName.data()+23, "dasl_rrri", 9))
	break;		break;
	switch (BuiltinName[25]) {		return Intrinsic::hexagon_S2_addasl_rrri; // "__builtin_HEXAG
			ON_S2_addasl_rrri"
			case 's': // 31 strings to match.
			switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'i': // 2 strings to match.		case 'l': // 15 strings to match.
	if (memcmp(BuiltinName.data()+26, "_v", 2))		if (BuiltinName[24] != '_')
	break;		break;
	switch (BuiltinName[28]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'i': // 7 strings to match.
	return Intrinsic::hexagon_S2_asl_i_vh; // "__builtin_HEXAG		if (BuiltinName[26] != '_')
	ON_S2_asl_i_vh"		break;
	case 'w': // 1 string to match.		switch (BuiltinName[27]) {
	return Intrinsic::hexagon_S2_asl_i_vw; // "__builtin_HEXAG		default: break;
	ON_S2_asl_i_vw"		case 'p': // 3 strings to match.
	}		if (BuiltinName[28] != '_')
	break;		break;
	case 'r': // 2 strings to match.		switch (BuiltinName[29]) {
	if (memcmp(BuiltinName.data()+26, "_v", 2))		default: break;
			case 'a': // 2 strings to match.
			switch (BuiltinName[30]) {
			default: break;
			case 'c': // 1 string to match.
			if (BuiltinName[31] != 'c')
			break;
			return Intrinsic::hexagon_S2_asl_i_p_acc; //
			"__builtin_HEXAGON_S2_asl_i_p_acc"
			case 'n': // 1 string to match.
			if (BuiltinName[31] != 'd')
			break;
			return Intrinsic::hexagon_S2_asl_i_p_and; //
			"__builtin_HEXAGON_S2_asl_i_p_and"
			}
			break;
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "ac", 2))
			break;
			return Intrinsic::hexagon_S2_asl_i_p_nac; // "__built
			in_HEXAGON_S2_asl_i_p_nac"
			}
			break;
			case 'r': // 4 strings to match.
			if (BuiltinName[28] != '_')
			break;
			switch (BuiltinName[29]) {
			default: break;
			case 'a': // 2 strings to match.
			switch (BuiltinName[30]) {
			default: break;
			case 'c': // 1 string to match.
			if (BuiltinName[31] != 'c')
			break;
			return Intrinsic::hexagon_S2_asl_i_r_acc; //
			"__builtin_HEXAGON_S2_asl_i_r_acc"
			case 'n': // 1 string to match.
			if (BuiltinName[31] != 'd')
			break;
			return Intrinsic::hexagon_S2_asl_i_r_and; //
			"__builtin_HEXAGON_S2_asl_i_r_and"
			}
			break;
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "ac", 2))
			break;
			return Intrinsic::hexagon_S2_asl_i_r_nac; // "__built
			in_HEXAGON_S2_asl_i_r_nac"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "at", 2))
			break;
			return Intrinsic::hexagon_S2_asl_i_r_sat; // "__built
			in_HEXAGON_S2_asl_i_r_sat"
			}
			break;
			}
	break;		break;
	switch (BuiltinName[28]) {		case 'r': // 8 strings to match.
	default: break;		if (BuiltinName[26] != '_')
	case 'h': // 1 string to match.		break;
	return Intrinsic::hexagon_S2_asl_r_vh; // "__builtin_HEXAG		switch (BuiltinName[27]) {
	ON_S2_asl_r_vh"		default: break;
	case 'w': // 1 string to match.		case 'p': // 4 strings to match.
	return Intrinsic::hexagon_S2_asl_r_vw; // "__builtin_HEXAG		if (BuiltinName[28] != '_')
	ON_S2_asl_r_vw"		break;
	}		switch (BuiltinName[29]) {
	break;		default: break;
	}		case 'a': // 2 strings to match.
	break;		switch (BuiltinName[30]) {
	case 'r': // 4 strings to match.		default: break;
	if (BuiltinName[24] != '_')		case 'c': // 1 string to match.
	break;		if (BuiltinName[31] != 'c')
	switch (BuiltinName[25]) {		break;
	default: break;		return Intrinsic::hexagon_S2_asl_r_p_acc; //
	case 'i': // 2 strings to match.		"__builtin_HEXAGON_S2_asl_r_p_acc"
	if (memcmp(BuiltinName.data()+26, "_v", 2))		case 'n': // 1 string to match.
			if (BuiltinName[31] != 'd')
			break;
			return Intrinsic::hexagon_S2_asl_r_p_and; //
			"__builtin_HEXAGON_S2_asl_r_p_and"
			}
			break;
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "ac", 2))
			break;
			return Intrinsic::hexagon_S2_asl_r_p_nac; // "__built
			in_HEXAGON_S2_asl_r_p_nac"
			case 'x': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "or", 2))
			break;
			return Intrinsic::hexagon_S2_asl_r_p_xor; // "__built
			in_HEXAGON_S2_asl_r_p_xor"
			}
			break;
			case 'r': // 4 strings to match.
			if (BuiltinName[28] != '_')
			break;
			switch (BuiltinName[29]) {
			default: break;
			case 'a': // 2 strings to match.
			switch (BuiltinName[30]) {
			default: break;
			case 'c': // 1 string to match.
			if (BuiltinName[31] != 'c')
			break;
			return Intrinsic::hexagon_S2_asl_r_r_acc; //
			"__builtin_HEXAGON_S2_asl_r_r_acc"
			case 'n': // 1 string to match.
			if (BuiltinName[31] != 'd')
			break;
			return Intrinsic::hexagon_S2_asl_r_r_and; //
			"__builtin_HEXAGON_S2_asl_r_r_and"
			}
			break;
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "ac", 2))
			break;
			return Intrinsic::hexagon_S2_asl_r_r_nac; // "__built
			in_HEXAGON_S2_asl_r_r_nac"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "at", 2))
			break;
			return Intrinsic::hexagon_S2_asl_r_r_sat; // "__built
			in_HEXAGON_S2_asl_r_r_sat"
			}
			break;
			}
	break;		break;
	switch (BuiltinName[28]) {
	default: break;
	case 'h': // 1 string to match.
	return Intrinsic::hexagon_S2_asr_i_vh; // "__builtin_HEXAG
	ON_S2_asr_i_vh"
	case 'w': // 1 string to match.
	return Intrinsic::hexagon_S2_asr_i_vw; // "__builtin_HEXAG
	ON_S2_asr_i_vw"
	}		}
	break;		break;
	case 'r': // 2 strings to match.		case 'r': // 16 strings to match.
	if (memcmp(BuiltinName.data()+26, "_v", 2))		if (BuiltinName[24] != '_')
	break;		break;
	switch (BuiltinName[28]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'i': // 8 strings to match.
	return Intrinsic::hexagon_S2_asr_r_vh; // "__builtin_HEXAG		if (BuiltinName[26] != '_')
	ON_S2_asr_r_vh"		break;
	case 'w': // 1 string to match.		switch (BuiltinName[27]) {
	return Intrinsic::hexagon_S2_asr_r_vw; // "__builtin_HEXAG		default: break;
	ON_S2_asr_r_vw"		case 'p': // 4 strings to match.
			if (BuiltinName[28] != '_')
			break;
			switch (BuiltinName[29]) {
			default: break;
			case 'a': // 2 strings to match.
			switch (BuiltinName[30]) {
			default: break;
			case 'c': // 1 string to match.
			if (BuiltinName[31] != 'c')
			break;
			return Intrinsic::hexagon_S2_asr_i_p_acc; //
			"__builtin_HEXAGON_S2_asr_i_p_acc"
			case 'n': // 1 string to match.
			if (BuiltinName[31] != 'd')
			break;
			return Intrinsic::hexagon_S2_asr_i_p_and; //
			"__builtin_HEXAGON_S2_asr_i_p_and"
			}
			break;
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "ac", 2))
			break;
			return Intrinsic::hexagon_S2_asr_i_p_nac; // "__built
			in_HEXAGON_S2_asr_i_p_nac"
			case 'r': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "nd", 2))
			break;
			return Intrinsic::hexagon_S2_asr_i_p_rnd; // "__built
			in_HEXAGON_S2_asr_i_p_rnd"
			}
			break;
			case 'r': // 4 strings to match.
			if (BuiltinName[28] != '_')
			break;
			switch (BuiltinName[29]) {
			default: break;
			case 'a': // 2 strings to match.
			switch (BuiltinName[30]) {
			default: break;
			case 'c': // 1 string to match.
			if (BuiltinName[31] != 'c')
			break;
			return Intrinsic::hexagon_S2_asr_i_r_acc; //
			"__builtin_HEXAGON_S2_asr_i_r_acc"
			case 'n': // 1 string to match.
			if (BuiltinName[31] != 'd')
			break;
			return Intrinsic::hexagon_S2_asr_i_r_and; //
			"__builtin_HEXAGON_S2_asr_i_r_and"
			}
			break;
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "ac", 2))
			break;
			return Intrinsic::hexagon_S2_asr_i_r_nac; // "__built
			in_HEXAGON_S2_asr_i_r_nac"
			case 'r': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "nd", 2))
			break;
			return Intrinsic::hexagon_S2_asr_i_r_rnd; // "__built
			in_HEXAGON_S2_asr_i_r_rnd"
			}
			break;
			}
			break;
			case 'r': // 8 strings to match.
			if (BuiltinName[26] != '_')
			break;
			switch (BuiltinName[27]) {
			default: break;
			case 'p': // 4 strings to match.
			if (BuiltinName[28] != '_')
			break;
			switch (BuiltinName[29]) {
			default: break;
			case 'a': // 2 strings to match.
			switch (BuiltinName[30]) {
			default: break;
			case 'c': // 1 string to match.
			if (BuiltinName[31] != 'c')
			break;
			return Intrinsic::hexagon_S2_asr_r_p_acc; //
			"__builtin_HEXAGON_S2_asr_r_p_acc"
			case 'n': // 1 string to match.
			if (BuiltinName[31] != 'd')
			break;
			return Intrinsic::hexagon_S2_asr_r_p_and; //
			"__builtin_HEXAGON_S2_asr_r_p_and"
			}
			break;
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "ac", 2))
			break;
			return Intrinsic::hexagon_S2_asr_r_p_nac; // "__built
			in_HEXAGON_S2_asr_r_p_nac"
			case 'x': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "or", 2))
			break;
			return Intrinsic::hexagon_S2_asr_r_p_xor; // "__built
			in_HEXAGON_S2_asr_r_p_xor"
			}
			break;
			case 'r': // 4 strings to match.
			if (BuiltinName[28] != '_')
			break;
			switch (BuiltinName[29]) {
			default: break;
			case 'a': // 2 strings to match.
			switch (BuiltinName[30]) {
			default: break;
			case 'c': // 1 string to match.
			if (BuiltinName[31] != 'c')
			break;
			return Intrinsic::hexagon_S2_asr_r_r_acc; //
			"__builtin_HEXAGON_S2_asr_r_r_acc"
			case 'n': // 1 string to match.
			if (BuiltinName[31] != 'd')
			break;
			return Intrinsic::hexagon_S2_asr_r_r_and; //
			"__builtin_HEXAGON_S2_asr_r_r_and"
			}
			break;
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "ac", 2))
			break;
			return Intrinsic::hexagon_S2_asr_r_r_nac; // "__built
			in_HEXAGON_S2_asr_r_r_nac"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "at", 2))
			break;
			return Intrinsic::hexagon_S2_asr_r_r_sat; // "__built
			in_HEXAGON_S2_asr_r_r_sat"
			}
			break;
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'c': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "lrbit_", 6))
	break;
	switch (BuiltinName[28]) {
	default: break;
	case 'i': // 1 string to match.
	return Intrinsic::hexagon_S2_clrbit_i; // "__builtin_HEXAG
	ON_S2_clrbit_i"
	case 'r': // 1 string to match.
	return Intrinsic::hexagon_S2_clrbit_r; // "__builtin_HEXAG
	ON_S2_clrbit_r"
	}
	break;
	case 'e': // 1 string to match.		case 'e': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "xtractu", 7))		if (memcmp(BuiltinName.data()+22, "xtractu_rp", 10))
	break;		break;
	return Intrinsic::hexagon_S2_extractu; // "__builtin_HEXAG		return Intrinsic::hexagon_S2_extractu_rp; // "__builtin_HEXAG
	ON_S2_extractu"		ON_S2_extractu_rp"
	case 'l': // 6 strings to match.		case 'l': // 20 strings to match.
	if (BuiltinName[22] != 's')		if (BuiltinName[22] != 's')
	break;		break;
	switch (BuiltinName[23]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'l': // 2 strings to match.		case 'l': // 7 strings to match.
	if (memcmp(BuiltinName.data()+24, "_r_v", 4))		if (memcmp(BuiltinName.data()+24, "_r_", 3))
	break;
	switch (BuiltinName[28]) {
	default: break;
	case 'h': // 1 string to match.
	return Intrinsic::hexagon_S2_lsl_r_vh; // "__builtin_HEXAG
	ON_S2_lsl_r_vh"
	case 'w': // 1 string to match.
	return Intrinsic::hexagon_S2_lsl_r_vw; // "__builtin_HEXAG
	ON_S2_lsl_r_vw"
	}
	break;
	case 'r': // 4 strings to match.
	if (BuiltinName[24] != '_')
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'i': // 2 strings to match.		case 'p': // 4 strings to match.
	if (memcmp(BuiltinName.data()+26, "_v", 2))		if (BuiltinName[28] != '_')
	break;		break;
	switch (BuiltinName[28]) {		switch (BuiltinName[29]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'a': // 2 strings to match.
	return Intrinsic::hexagon_S2_lsr_i_vh; // "__builtin_HEXAG		switch (BuiltinName[30]) {
	ON_S2_lsr_i_vh"		default: break;
	case 'w': // 1 string to match.		case 'c': // 1 string to match.
	return Intrinsic::hexagon_S2_lsr_i_vw; // "__builtin_HEXAG		if (BuiltinName[31] != 'c')
	ON_S2_lsr_i_vw"		break;
			return Intrinsic::hexagon_S2_lsl_r_p_acc; // "__built
			in_HEXAGON_S2_lsl_r_p_acc"
			case 'n': // 1 string to match.
			if (BuiltinName[31] != 'd')
			break;
			return Intrinsic::hexagon_S2_lsl_r_p_and; // "__built
			in_HEXAGON_S2_lsl_r_p_and"
			}
			break;
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "ac", 2))
			break;
			return Intrinsic::hexagon_S2_lsl_r_p_nac; // "__built
			in_HEXAGON_S2_lsl_r_p_nac"
			case 'x': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "or", 2))
			break;
			return Intrinsic::hexagon_S2_lsl_r_p_xor; // "__built
			in_HEXAGON_S2_lsl_r_p_xor"
	}		}
	break;		break;
	case 'r': // 2 strings to match.		case 'r': // 3 strings to match.
	if (memcmp(BuiltinName.data()+26, "_v", 2))		if (BuiltinName[28] != '_')
	break;		break;
	switch (BuiltinName[28]) {		switch (BuiltinName[29]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'a': // 2 strings to match.
	return Intrinsic::hexagon_S2_lsr_r_vh; // "__builtin_HEXAG		switch (BuiltinName[30]) {
	ON_S2_lsr_r_vh"		default: break;
	case 'w': // 1 string to match.		case 'c': // 1 string to match.
	return Intrinsic::hexagon_S2_lsr_r_vw; // "__builtin_HEXAG		if (BuiltinName[31] != 'c')
	ON_S2_lsr_r_vw"		break;
			return Intrinsic::hexagon_S2_lsl_r_r_acc; // "__built
			in_HEXAGON_S2_lsl_r_r_acc"
			case 'n': // 1 string to match.
			if (BuiltinName[31] != 'd')
			break;
			return Intrinsic::hexagon_S2_lsl_r_r_and; // "__built
			in_HEXAGON_S2_lsl_r_r_and"
			}
			break;
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "ac", 2))
			break;
			return Intrinsic::hexagon_S2_lsl_r_r_nac; // "__built
			in_HEXAGON_S2_lsl_r_r_nac"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'r': // 13 strings to match.
	break;		if (BuiltinName[24] != '_')
	case 's': // 3 strings to match.
	switch (BuiltinName[22]) {
	default: break;
	case 'e': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "tbit_", 5))
	break;
	switch (BuiltinName[28]) {
	default: break;
	case 'i': // 1 string to match.
	return Intrinsic::hexagon_S2_setbit_i; // "__builtin_HEXAG
	ON_S2_setbit_i"
	case 'r': // 1 string to match.
	return Intrinsic::hexagon_S2_setbit_r; // "__builtin_HEXAG
	ON_S2_setbit_r"
	}
	break;
	case 'v': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "sathub", 6))
	break;
	return Intrinsic::hexagon_S2_svsathub; // "__builtin_HEXAG
	ON_S2_svsathub"
	}
	break;
	case 't': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "stbit_", 6))
	break;
	switch (BuiltinName[28]) {
	default: break;
	case 'i': // 1 string to match.
	return Intrinsic::hexagon_S2_tstbit_i; // "__builtin_HEXAG
	ON_S2_tstbit_i"
	case 'r': // 1 string to match.
	return Intrinsic::hexagon_S2_tstbit_r; // "__builtin_HEXAG
	ON_S2_tstbit_r"
	}
	break;
	case 'v': // 9 strings to match.
	switch (BuiltinName[22]) {
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "lign", 4))
	break;		break;
	switch (BuiltinName[27]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'i': // 1 string to match.		case 'i': // 6 strings to match.
	if (BuiltinName[28] != 'b')		if (BuiltinName[26] != '_')
	break;
	return Intrinsic::hexagon_S2_valignib; // "__builtin_HEXAG
	ON_S2_valignib"
	case 'r': // 1 string to match.
	if (BuiltinName[28] != 'b')
	break;		break;
	return Intrinsic::hexagon_S2_valignrb; // "__builtin_HEXAG
	ON_S2_valignrb"
	}
	break;
	case 'c': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "rotate", 6))
	break;
	return Intrinsic::hexagon_S2_vcrotate; // "__builtin_HEXAG
	ON_S2_vcrotate"
	case 's': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "platr", 5))
	break;
	switch (BuiltinName[28]) {
	default: break;
	case 'b': // 1 string to match.
	return Intrinsic::hexagon_S2_vsplatrb; // "__builtin_HEXAG
	ON_S2_vsplatrb"
	case 'h': // 1 string to match.
	return Intrinsic::hexagon_S2_vsplatrh; // "__builtin_HEXAG
	ON_S2_vsplatrh"
	}
	break;
	case 't': // 4 strings to match.
	if (memcmp(BuiltinName.data()+23, "run", 3))
	break;
	switch (BuiltinName[26]) {
	default: break;
	case 'e': // 2 strings to match.
	switch (BuiltinName[27]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'p': // 3 strings to match.
	if (BuiltinName[28] != 'b')		if (BuiltinName[28] != '_')
	break;		break;
	return Intrinsic::hexagon_S2_vtrunehb; // "__builtin_HEXAG		switch (BuiltinName[29]) {
	ON_S2_vtrunehb"		default: break;
	case 'w': // 1 string to match.		case 'a': // 2 strings to match.
	if (BuiltinName[28] != 'h')		switch (BuiltinName[30]) {
			default: break;
			case 'c': // 1 string to match.
			if (BuiltinName[31] != 'c')
			break;
			return Intrinsic::hexagon_S2_lsr_i_p_acc; // "__built
			in_HEXAGON_S2_lsr_i_p_acc"
			case 'n': // 1 string to match.
			if (BuiltinName[31] != 'd')
			break;
			return Intrinsic::hexagon_S2_lsr_i_p_and; // "__built
			in_HEXAGON_S2_lsr_i_p_and"
			}
	break;		break;
	return Intrinsic::hexagon_S2_vtrunewh; // "__builtin_HEXAG		case 'n': // 1 string to match.
	ON_S2_vtrunewh"		if (memcmp(BuiltinName.data()+30, "ac", 2))
			break;
			return Intrinsic::hexagon_S2_lsr_i_p_nac; // "__built
			in_HEXAGON_S2_lsr_i_p_nac"
			}
			break;
			case 'r': // 3 strings to match.
			if (BuiltinName[28] != '_')
			break;
			switch (BuiltinName[29]) {
			default: break;
			case 'a': // 2 strings to match.
			switch (BuiltinName[30]) {
			default: break;
			case 'c': // 1 string to match.
			if (BuiltinName[31] != 'c')
			break;
			return Intrinsic::hexagon_S2_lsr_i_r_acc; // "__built
			in_HEXAGON_S2_lsr_i_r_acc"
			case 'n': // 1 string to match.
			if (BuiltinName[31] != 'd')
			break;
			return Intrinsic::hexagon_S2_lsr_i_r_and; // "__built
			in_HEXAGON_S2_lsr_i_r_and"
			}
			break;
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "ac", 2))
			break;
			return Intrinsic::hexagon_S2_lsr_i_r_nac; // "__built
			in_HEXAGON_S2_lsr_i_r_nac"
			}
			break;
	}		}
	break;		break;
	case 'o': // 2 strings to match.		case 'r': // 7 strings to match.
			if (BuiltinName[26] != '_')
			break;
	switch (BuiltinName[27]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'p': // 4 strings to match.
	if (BuiltinName[28] != 'b')		if (BuiltinName[28] != '_')
	break;		break;
	return Intrinsic::hexagon_S2_vtrunohb; // "__builtin_HEXAG		switch (BuiltinName[29]) {
	ON_S2_vtrunohb"		default: break;
	case 'w': // 1 string to match.		case 'a': // 2 strings to match.
	if (BuiltinName[28] != 'h')		switch (BuiltinName[30]) {
			default: break;
			case 'c': // 1 string to match.
			if (BuiltinName[31] != 'c')
			break;
			return Intrinsic::hexagon_S2_lsr_r_p_acc; // "__built
			in_HEXAGON_S2_lsr_r_p_acc"
			case 'n': // 1 string to match.
			if (BuiltinName[31] != 'd')
			break;
			return Intrinsic::hexagon_S2_lsr_r_p_and; // "__built
			in_HEXAGON_S2_lsr_r_p_and"
			}
	break;		break;
	return Intrinsic::hexagon_S2_vtrunowh; // "__builtin_HEXAG		case 'n': // 1 string to match.
	ON_S2_vtrunowh"		if (memcmp(BuiltinName.data()+30, "ac", 2))
			break;
			return Intrinsic::hexagon_S2_lsr_r_p_nac; // "__built
			in_HEXAGON_S2_lsr_r_p_nac"
			case 'x': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "or", 2))
			break;
			return Intrinsic::hexagon_S2_lsr_r_p_xor; // "__built
			in_HEXAGON_S2_lsr_r_p_xor"
			}
			break;
			case 'r': // 3 strings to match.
			if (BuiltinName[28] != '_')
			break;
			switch (BuiltinName[29]) {
			default: break;
			case 'a': // 2 strings to match.
			switch (BuiltinName[30]) {
			default: break;
			case 'c': // 1 string to match.
			if (BuiltinName[31] != 'c')
			break;
			return Intrinsic::hexagon_S2_lsr_r_r_acc; // "__built
			in_HEXAGON_S2_lsr_r_r_acc"
			case 'n': // 1 string to match.
			if (BuiltinName[31] != 'd')
			break;
			return Intrinsic::hexagon_S2_lsr_r_r_and; // "__built
			in_HEXAGON_S2_lsr_r_r_and"
			}
			break;
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "ac", 2))
			break;
			return Intrinsic::hexagon_S2_lsr_r_r_nac; // "__built
			in_HEXAGON_S2_lsr_r_r_nac"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 't': // 2 strings to match.
	break;		if (memcmp(BuiltinName.data()+22, "ogglebit_", 9))
	case '4': // 4 strings to match.
	if (BuiltinName[20] != '_')
	break;
	switch (BuiltinName[21]) {
	default: break;
	case 'c': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "lbp", 3))
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[31]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "ddi", 3))		return Intrinsic::hexagon_S2_togglebit_i; // "__builtin_HEXAG
	break;		ON_S2_togglebit_i"
	return Intrinsic::hexagon_S4_clbpaddi; // "__builtin_HEXAG		case 'r': // 1 string to match.
	ON_S4_clbpaddi"		return Intrinsic::hexagon_S2_togglebit_r; // "__builtin_HEXAG
	case 'n': // 1 string to match.		ON_S2_togglebit_r"
	if (memcmp(BuiltinName.data()+26, "orm", 3))
	break;
	return Intrinsic::hexagon_S4_clbpnorm; // "__builtin_HEXAG
	ON_S4_clbpnorm"
	}		}
	break;		break;
	case 'e': // 1 string to match.		case 'v': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "xtractp", 7))		if (memcmp(BuiltinName.data()+22, "rndpackwhs", 10))
	break;
	return Intrinsic::hexagon_S4_extractp; // "__builtin_HEXAG
	ON_S4_extractp"
	case 'o': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "r_andix", 7))
	break;
	return Intrinsic::hexagon_S4_or_andix; // "__builtin_HEXAG
	ON_S4_or_andix"
	}
	break;
	}
	break;
	}
	break;
	case 30: // 81 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
	break;
	switch (BuiltinName[18]) {
	default: break;
	case 'A': // 11 strings to match.
	switch (BuiltinName[19]) {
	default: break;
	case '2': // 3 strings to match.
	if (BuiltinName[20] != '_')
	break;
	switch (BuiltinName[21]) {
	default: break;
	case 'c': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "ombineii", 8))
	break;		break;
	return Intrinsic::hexagon_A2_combineii; // "__builtin_HEXAG		return Intrinsic::hexagon_S2_vrndpackwhs; // "__builtin_HEXAG
	ON_A2_combineii"		ON_S2_vrndpackwhs"
	case 'v': // 2 strings to match.
	switch (BuiltinName[22]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "ddb_map", 7))
	break;
	return Intrinsic::hexagon_A2_vaddb_map; // "__builtin_HEXAG
	ON_A2_vaddb_map"
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "ubb_map", 7))
	break;
	return Intrinsic::hexagon_A2_vsubb_map; // "__builtin_HEXAG
	ON_A2_vsubb_map"
	}
	break;
	}		}
	break;		break;
	case '4': // 8 strings to match.		case '4': // 7 strings to match.
	if (BuiltinName[20] != '_')		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'a': // 4 strings to match.
	if (memcmp(BuiltinName.data()+22, "itspliti", 8))
	break;
	return Intrinsic::hexagon_A4_bitspliti; // "__builtin_HEXAG
	ON_A4_bitspliti"
	case 'c': // 4 strings to match.
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'o': // 2 strings to match.		case 'd': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "mbine", 5))		if (memcmp(BuiltinName.data()+23, "di_", 3))
	break;		break;
	switch (BuiltinName[28]) {		switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'i': // 1 string to match.		case 'a': // 1 string to match.
	if (BuiltinName[29] != 'r')		if (memcmp(BuiltinName.data()+27, "sl_ri", 5))
	break;		break;
	return Intrinsic::hexagon_A4_combineir; // "__builtin_HEXAG		return Intrinsic::hexagon_S4_addi_asl_ri; // "__built
	ON_A4_combineir"		in_HEXAGON_S4_addi_asl_ri"
	case 'r': // 1 string to match.		case 'l': // 1 string to match.
	if (BuiltinName[29] != 'i')		if (memcmp(BuiltinName.data()+27, "sr_ri", 5))
	break;		break;
	return Intrinsic::hexagon_A4_combineri; // "__builtin_HEXAG ON_A4_combineri"		return Intrinsic::hexagon_S4_addi_lsr_ri; // "__built in_HEXAGON_S4_addi_lsr_ri"
	}		}
	break;		break;
	case 'r': // 2 strings to match.		case 'n': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "ound_r", 6))		if (memcmp(BuiltinName.data()+23, "di_", 3))
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'i': // 1 string to match.		case 'a': // 1 string to match.
	return Intrinsic::hexagon_A4_cround_ri; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+27, "sl_ri", 5))
	ON_A4_cround_ri"		break;
	case 'r': // 1 string to match.		return Intrinsic::hexagon_S4_andi_asl_ri; // "__built
	return Intrinsic::hexagon_A4_cround_rr; // "__builtin_HEXAG		in_HEXAGON_S4_andi_asl_ri"
	ON_A4_cround_rr"		case 'l': // 1 string to match.
			if (memcmp(BuiltinName.data()+27, "sr_ri", 5))
			break;
			return Intrinsic::hexagon_S4_andi_lsr_ri; // "__built
			in_HEXAGON_S4_andi_lsr_ri"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'v': // 3 strings to match.		case 'e': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "cmp", 3))		if (memcmp(BuiltinName.data()+22, "xtractp_rp", 10))
	break;		break;
	switch (BuiltinName[25]) {		return Intrinsic::hexagon_S4_extractp_rp; // "__builtin_HEXAG
			ON_S4_extractp_rp"
			case 's': // 2 strings to match.
			if (memcmp(BuiltinName.data()+22, "ubi_", 4))
			break;
			switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "gtui", 4))		if (memcmp(BuiltinName.data()+27, "sl_ri", 5))
	break;
	return Intrinsic::hexagon_A4_vcmpbgtui; // "__builtin_HEXAG
	ON_A4_vcmpbgtui"
	case 'h': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "gtui", 4))
	break;		break;
	return Intrinsic::hexagon_A4_vcmphgtui; // "__builtin_HEXAG		return Intrinsic::hexagon_S4_subi_asl_ri; // "__builtin_HEXAG
	ON_A4_vcmphgtui"		ON_S4_subi_asl_ri"
	case 'w': // 1 string to match.		case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "gtui", 4))		if (memcmp(BuiltinName.data()+27, "sr_ri", 5))
	break;		break;
	return Intrinsic::hexagon_A4_vcmpwgtui; // "__builtin_HEXAG ON_A4_vcmpwgtui"		return Intrinsic::hexagon_S4_subi_lsr_ri; // "__builtin_HEXAG ON_S4_subi_lsr_ri"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'C': // 2 strings to match.		}
	switch (BuiltinName[19]) {		break;
	default: break;		case 33: // 9 strings to match.
	case '2': // 1 string to match.		if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
	if (memcmp(BuiltinName.data()+20, "_pxfer_map", 10))
	break;
	return Intrinsic::hexagon_C2_pxfer_map; // "__builtin_HEXAG
	ON_C2_pxfer_map"
	case '4': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "_nbitsclri", 10))
	break;
	return Intrinsic::hexagon_C4_nbitsclri; // "__builtin_HEXAG
	ON_C4_nbitsclri"
	}
	break;		break;
	case 'F': // 12 strings to match.		switch (BuiltinName[18]) {
	if (memcmp(BuiltinName.data()+19, "2_", 2))		default: break;
			case 'A': // 2 strings to match.
			if (memcmp(BuiltinName.data()+19, "4_round_r", 9))
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[28]) {
	default: break;		default: break;
	case 'c': // 8 strings to match.		case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "onv_", 4))		if (memcmp(BuiltinName.data()+29, "_sat", 4))
	break;
	switch (BuiltinName[26]) {
	default: break;
	case 'd': // 4 strings to match.
	switch (BuiltinName[27]) {
	default: break;
	case '2': // 2 strings to match.
	switch (BuiltinName[28]) {
	default: break;
	case 'd': // 1 string to match.
	if (BuiltinName[29] != 'f')
	break;
	return Intrinsic::hexagon_F2_conv_d2df; // "__builtin_HEXAG
	ON_F2_conv_d2df"
	case 's': // 1 string to match.
	if (BuiltinName[29] != 'f')
	break;
	return Intrinsic::hexagon_F2_conv_d2sf; // "__builtin_HEXAG
	ON_F2_conv_d2sf"
	}
	break;
	case 'f': // 2 strings to match.
	if (BuiltinName[28] != '2')
	break;
	switch (BuiltinName[29]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::hexagon_F2_conv_df2d; // "__builtin_HEXAG
	ON_F2_conv_df2d"
	case 'w': // 1 string to match.
	return Intrinsic::hexagon_F2_conv_df2w; // "__builtin_HEXAG
	ON_F2_conv_df2w"
	}
	break;
	}
	break;
	case 's': // 2 strings to match.
	if (memcmp(BuiltinName.data()+27, "f2", 2))
	break;
	switch (BuiltinName[29]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::hexagon_F2_conv_sf2d; // "__builtin_HEXAG
	ON_F2_conv_sf2d"
	case 'w': // 1 string to match.
	return Intrinsic::hexagon_F2_conv_sf2w; // "__builtin_HEXAG
	ON_F2_conv_sf2w"
	}
	break;		break;
	case 'w': // 2 strings to match.		return Intrinsic::hexagon_A4_round_ri_sat; // "__builtin_HEXAG
	if (BuiltinName[27] != '2')		ON_A4_round_ri_sat"
	break;		case 'r': // 1 string to match.
	switch (BuiltinName[28]) {		if (memcmp(BuiltinName.data()+29, "_sat", 4))
	default: break;
	case 'd': // 1 string to match.
	if (BuiltinName[29] != 'f')
	break;
	return Intrinsic::hexagon_F2_conv_w2df; // "__builtin_HEXAG
	ON_F2_conv_w2df"
	case 's': // 1 string to match.
	if (BuiltinName[29] != 'f')
	break;
	return Intrinsic::hexagon_F2_conv_w2sf; // "__builtin_HEXAG
	ON_F2_conv_w2sf"
	}
	break;		break;
	}		return Intrinsic::hexagon_A4_round_rr_sat; // "__builtin_HEXAG
			ON_A4_round_rr_sat"
			}
			break;
			case 'M': // 1 string to match.
			if (memcmp(BuiltinName.data()+19, "2_vrcmpys_s1rp", 14))
	break;		break;
	case 'd': // 2 strings to match.		return Intrinsic::hexagon_M2_vrcmpys_s1rp; // "__builtin_HEXAG
	if (memcmp(BuiltinName.data()+22, "ffm", 3))		ON_M2_vrcmpys_s1rp"
			case 'S': // 6 strings to match.
			if (memcmp(BuiltinName.data()+19, "2_", 2))
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(BuiltinName.data()+22, "sl_i_", 5))
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "_lib", 4))		if (memcmp(BuiltinName.data()+28, "_xacc", 5))
	break;		break;
	return Intrinsic::hexagon_F2_dffma_lib; // "__builtin_HEXAG		return Intrinsic::hexagon_S2_asl_i_p_xacc; // "__builtin_HEXAG
	ON_F2_dffma_lib"		ON_S2_asl_i_p_xacc"
	case 's': // 1 string to match.		case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "_lib", 4))		if (memcmp(BuiltinName.data()+28, "_xacc", 5))
	break;		break;
	return Intrinsic::hexagon_F2_dffms_lib; // "__builtin_HEXAG ON_F2_dffms_lib"		return Intrinsic::hexagon_S2_asl_i_r_xacc; // "__builtin_HEXAG ON_S2_asl_i_r_xacc"
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "ffm", 3))		if (memcmp(BuiltinName.data()+22, "einterleave", 11))
	break;		break;
	switch (BuiltinName[25]) {		return Intrinsic::hexagon_S2_deinterleave; // "__builtin_HEXAG
			ON_S2_deinterleave"
			case 'e': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "xtractup_rp", 11))
			break;
			return Intrinsic::hexagon_S2_extractup_rp; // "__builtin_HEXAG
			ON_S2_extractup_rp"
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+22, "sr_i_", 5))
			break;
			switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "_lib", 4))		if (memcmp(BuiltinName.data()+28, "_xacc", 5))
	break;		break;
	return Intrinsic::hexagon_F2_sffma_lib; // "__builtin_HEXAG		return Intrinsic::hexagon_S2_lsr_i_p_xacc; // "__builtin_HEXAG
	ON_F2_sffma_lib"		ON_S2_lsr_i_p_xacc"
	case 's': // 1 string to match.		case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "_lib", 4))		if (memcmp(BuiltinName.data()+28, "_xacc", 5))
	break;		break;
	return Intrinsic::hexagon_F2_sffms_lib; // "__builtin_HEXAG ON_F2_sffms_lib"		return Intrinsic::hexagon_S2_lsr_i_r_xacc; // "__builtin_HEXAG ON_S2_lsr_i_r_xacc"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'M': // 44 strings to match.		}
			break;
			case 34: // 41 strings to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
			break;
			switch (BuiltinName[18]) {
			default: break;
			case 'M': // 38 strings to match.
	switch (BuiltinName[19]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case '2': // 41 strings to match.		case '2': // 35 strings to match.
	if (BuiltinName[20] != '_')		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'c': // 8 strings to match.		case 'm': // 33 strings to match.
	switch (BuiltinName[22]) {		if (memcmp(BuiltinName.data()+22, "py_", 3))
			break;
			switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'm': // 6 strings to match.		case 'a': // 8 strings to match.
	switch (BuiltinName[23]) {		if (memcmp(BuiltinName.data()+26, "cc_", 3))
			break;
			switch (BuiltinName[29]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'h': // 4 strings to match.
	if (memcmp(BuiltinName.data()+24, "csc_s", 5))		switch (BuiltinName[30]) {
	break;
	switch (BuiltinName[29]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'h': // 2 strings to match.
	return Intrinsic::hexagon_M2_cmacsc_s0; // "__built		if (memcmp(BuiltinName.data()+31, "_s", 2))
	in_HEXAGON_M2_cmacsc_s0"		break;
	case '1': // 1 string to match.		switch (BuiltinName[33]) {
	return Intrinsic::hexagon_M2_cmacsc_s1; // "__built		default: break;
	in_HEXAGON_M2_cmacsc_s1"		case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_acc_hh_s0; // "__built
			in_HEXAGON_M2_mpy_acc_hh_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_acc_hh_s1; // "__built
			in_HEXAGON_M2_mpy_acc_hh_s1"
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+31, "_s", 2))
			break;
			switch (BuiltinName[33]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_acc_hl_s0; // "__built
			in_HEXAGON_M2_mpy_acc_hl_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_acc_hl_s1; // "__built
			in_HEXAGON_M2_mpy_acc_hl_s1"
			}
			break;
	}		}
	break;		break;
	case 'p': // 4 strings to match.		case 'l': // 4 strings to match.
	if (BuiltinName[24] != 'y')		switch (BuiltinName[30]) {
	break;
	switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'r': // 2 strings to match.		case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+26, "s_s", 3))		if (memcmp(BuiltinName.data()+31, "_s", 2))
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[33]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_cmpyrs_s0; // "__built in_HEXAGON_M2_cmpyrs_s0"		return Intrinsic::hexagon_M2_mpy_acc_lh_s0; // "__built in_HEXAGON_M2_mpy_acc_lh_s0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_cmpyrs_s1; // "__built in_HEXAGON_M2_cmpyrs_s1"		return Intrinsic::hexagon_M2_mpy_acc_lh_s1; // "__built in_HEXAGON_M2_mpy_acc_lh_s1"
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+26, "c_s", 3))		if (memcmp(BuiltinName.data()+31, "_s", 2))
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[33]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_cmpysc_s0; // "__built in_HEXAGON_M2_cmpysc_s0"		return Intrinsic::hexagon_M2_mpy_acc_ll_s0; // "__built in_HEXAGON_M2_mpy_acc_ll_s0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_cmpysc_s1; // "__built in_HEXAGON_M2_cmpysc_s1"		return Intrinsic::hexagon_M2_mpy_acc_ll_s1; // "__built in_HEXAGON_M2_mpy_acc_ll_s1"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'n': // 2 strings to match.		case 'n': // 8 strings to match.
	if (memcmp(BuiltinName.data()+23, "acsc_s", 6))		if (memcmp(BuiltinName.data()+26, "ac_", 3))
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[29]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'h': // 4 strings to match.
	return Intrinsic::hexagon_M2_cnacsc_s0; // "__builtin_HEXAG		switch (BuiltinName[30]) {
	ON_M2_cnacsc_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_cnacsc_s1; // "__builtin_HEXAG
	ON_M2_cnacsc_s1"
	}
	break;
	}
	break;
	case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "mmpy", 4))
	break;
	switch (BuiltinName[26]) {
	default: break;
	case 'h': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "_s1", 3))
	break;
	return Intrinsic::hexagon_M2_hmmpyh_s1; // "__builtin_HEXAG
	ON_M2_hmmpyh_s1"
	case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "_s1", 3))
	break;
	return Intrinsic::hexagon_M2_hmmpyl_s1; // "__builtin_HEXAG
	ON_M2_hmmpyl_s1"
	}
	break;
	case 'm': // 21 strings to match.
	switch (BuiltinName[22]) {
	default: break;
	case 'm': // 12 strings to match.
	switch (BuiltinName[23]) {
	default: break;
	case 'a': // 4 strings to match.
	if (BuiltinName[24] != 'c')
	break;
	switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+26, "s_s", 3))		if (memcmp(BuiltinName.data()+31, "_s", 2))
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[33]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mmachs_s0; // "__built in_HEXAGON_M2_mmachs_s0"		return Intrinsic::hexagon_M2_mpy_nac_hh_s0; // "__built in_HEXAGON_M2_mpy_nac_hh_s0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mmachs_s1; // "__built in_HEXAGON_M2_mmachs_s1"		return Intrinsic::hexagon_M2_mpy_nac_hh_s1; // "__built in_HEXAGON_M2_mpy_nac_hh_s1"
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+26, "s_s", 3))		if (memcmp(BuiltinName.data()+31, "_s", 2))
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[33]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mmacls_s0; // "__built in_HEXAGON_M2_mmacls_s0"		return Intrinsic::hexagon_M2_mpy_nac_hl_s0; // "__built in_HEXAGON_M2_mpy_nac_hl_s0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mmacls_s1; // "__built in_HEXAGON_M2_mmacls_s1"		return Intrinsic::hexagon_M2_mpy_nac_hl_s1; // "__built in_HEXAGON_M2_mpy_nac_hl_s1"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'p': // 8 strings to match.		case 'l': // 4 strings to match.
	if (BuiltinName[24] != 'y')		switch (BuiltinName[30]) {
	break;
	switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+26, "_rs", 3))		if (memcmp(BuiltinName.data()+31, "_s", 2))
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[33]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mmpyh_rs0; // "__built in_HEXAGON_M2_mmpyh_rs0"		return Intrinsic::hexagon_M2_mpy_nac_lh_s0; // "__built in_HEXAGON_M2_mpy_nac_lh_s0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mmpyh_rs1; // "__built in_HEXAGON_M2_mmpyh_rs1"		return Intrinsic::hexagon_M2_mpy_nac_lh_s1; // "__built in_HEXAGON_M2_mpy_nac_lh_s1"
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+26, "_rs", 3))		if (memcmp(BuiltinName.data()+31, "_s", 2))
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[33]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mmpyl_rs0; // "__built in_HEXAGON_M2_mmpyl_rs0"		return Intrinsic::hexagon_M2_mpy_nac_ll_s0; // "__built in_HEXAGON_M2_mpy_nac_ll_s0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mmpyl_rs1; // "__built		return Intrinsic::hexagon_M2_mpy_nac_ll_s1; // "__built
	in_HEXAGON_M2_mmpyl_rs1"		in_HEXAGON_M2_mpy_nac_ll_s1"
	}
	break;
	case 'u': // 4 strings to match.
	switch (BuiltinName[26]) {
	default: break;
	case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+27, "_s", 2))
	break;
	switch (BuiltinName[29]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mmpyuh_s0; // "__built
	in_HEXAGON_M2_mmpyuh_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mmpyuh_s1; // "__built
	in_HEXAGON_M2_mmpyuh_s1"
	}
	break;
	case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+27, "_s", 2))
	break;
	switch (BuiltinName[29]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mmpyul_s0; // "__built
	in_HEXAGON_M2_mmpyul_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mmpyul_s1; // "__built
	in_HEXAGON_M2_mmpyul_s1"
	}
	break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'p': // 9 strings to match.		case 'r': // 8 strings to match.
	if (memcmp(BuiltinName.data()+23, "y_", 2))		if (memcmp(BuiltinName.data()+26, "nd_", 3))
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[29]) {
	default: break;		default: break;
	case 'h': // 4 strings to match.		case 'h': // 4 strings to match.
	switch (BuiltinName[26]) {		switch (BuiltinName[30]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+27, "_s", 2))		if (memcmp(BuiltinName.data()+31, "_s", 2))
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[33]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_hh_s0; // "__built in_HEXAGON_M2_mpy_hh_s0"		return Intrinsic::hexagon_M2_mpy_rnd_hh_s0; // "__built in_HEXAGON_M2_mpy_rnd_hh_s0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_hh_s1; // "__built in_HEXAGON_M2_mpy_hh_s1"		return Intrinsic::hexagon_M2_mpy_rnd_hh_s1; // "__built in_HEXAGON_M2_mpy_rnd_hh_s1"
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+27, "_s", 2))		if (memcmp(BuiltinName.data()+31, "_s", 2))
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[33]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_hl_s0; // "__built in_HEXAGON_M2_mpy_hl_s0"		return Intrinsic::hexagon_M2_mpy_rnd_hl_s0; // "__built in_HEXAGON_M2_mpy_rnd_hl_s0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_hl_s1; // "__built in_HEXAGON_M2_mpy_hl_s1"		return Intrinsic::hexagon_M2_mpy_rnd_hl_s1; // "__built in_HEXAGON_M2_mpy_rnd_hl_s1"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'l': // 4 strings to match.		case 'l': // 4 strings to match.
	switch (BuiltinName[26]) {		switch (BuiltinName[30]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+27, "_s", 2))		if (memcmp(BuiltinName.data()+31, "_s", 2))
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[33]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_lh_s0; // "__built in_HEXAGON_M2_mpy_lh_s0"		return Intrinsic::hexagon_M2_mpy_rnd_lh_s0; // "__built in_HEXAGON_M2_mpy_rnd_lh_s0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_lh_s1; // "__built in_HEXAGON_M2_mpy_lh_s1"		return Intrinsic::hexagon_M2_mpy_rnd_lh_s1; // "__built in_HEXAGON_M2_mpy_rnd_lh_s1"
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+27, "_s", 2))		if (memcmp(BuiltinName.data()+31, "_s", 2))
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[33]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_ll_s0; // "__built in_HEXAGON_M2_mpy_ll_s0"		return Intrinsic::hexagon_M2_mpy_rnd_ll_s0; // "__built in_HEXAGON_M2_mpy_rnd_ll_s0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_ll_s1; // "__built in_HEXAGON_M2_mpy_ll_s1"		return Intrinsic::hexagon_M2_mpy_rnd_ll_s1; // "__built in_HEXAGON_M2_mpy_rnd_ll_s1"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'u': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "p_s1", 4))
	break;
	return Intrinsic::hexagon_M2_mpy_up_s1; // "__builtin_HEXAG
	ON_M2_mpy_up_s1"
	}		}
	break;		break;
	}		case 's': // 8 strings to match.
	break;		if (memcmp(BuiltinName.data()+26, "at_", 3))
	case 'v': // 10 strings to match.
	switch (BuiltinName[22]) {
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "bsdiff", 6))
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[29]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'h': // 4 strings to match.
	return Intrinsic::hexagon_M2_vabsdiffh; // "__builtin_HEXAG		switch (BuiltinName[30]) {
	ON_M2_vabsdiffh"
	case 'w': // 1 string to match.
	return Intrinsic::hexagon_M2_vabsdiffw; // "__builtin_HEXAG
	ON_M2_vabsdiffw"
	}
	break;
	case 'd': // 4 strings to match.
	if (BuiltinName[23] != 'm')
	break;
	switch (BuiltinName[24]) {
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+25, "cs_s", 4))
	break;
	switch (BuiltinName[29]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'h': // 2 strings to match.
	return Intrinsic::hexagon_M2_vdmacs_s0; // "__built		if (memcmp(BuiltinName.data()+31, "_s", 2))
	in_HEXAGON_M2_vdmacs_s0"		break;
	case '1': // 1 string to match.		switch (BuiltinName[33]) {
	return Intrinsic::hexagon_M2_vdmacs_s1; // "__built		default: break;
	in_HEXAGON_M2_vdmacs_s1"		case '0': // 1 string to match.
	}		return Intrinsic::hexagon_M2_mpy_sat_hh_s0; // "__built
	break;		in_HEXAGON_M2_mpy_sat_hh_s0"
	case 'p': // 2 strings to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "ys_s", 4))		return Intrinsic::hexagon_M2_mpy_sat_hh_s1; // "__built
			in_HEXAGON_M2_mpy_sat_hh_s1"
			}
	break;		break;
	switch (BuiltinName[29]) {		case 'l': // 2 strings to match.
	default: break;		if (memcmp(BuiltinName.data()+31, "_s", 2))
	case '0': // 1 string to match.		break;
	return Intrinsic::hexagon_M2_vdmpys_s0; // "__built		switch (BuiltinName[33]) {
	in_HEXAGON_M2_vdmpys_s0"		default: break;
	case '1': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_vdmpys_s1; // "__built		return Intrinsic::hexagon_M2_mpy_sat_hl_s0; // "__built
	in_HEXAGON_M2_vdmpys_s1"		in_HEXAGON_M2_mpy_sat_hl_s0"
	}		case '1': // 1 string to match.
	break;		return Intrinsic::hexagon_M2_mpy_sat_hl_s1; // "__built
	}		in_HEXAGON_M2_mpy_sat_hl_s1"
	break;		}
	case 'm': // 4 strings to match.
	switch (BuiltinName[23]) {
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+24, "c2s_s", 5))
	break;		break;
	switch (BuiltinName[29]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_vmac2s_s0; // "__built
	in_HEXAGON_M2_vmac2s_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_vmac2s_s1; // "__built
	in_HEXAGON_M2_vmac2s_s1"
	}		}
	break;		break;
	case 'p': // 2 strings to match.		case 'l': // 4 strings to match.
	if (memcmp(BuiltinName.data()+24, "y2s_s", 5))		switch (BuiltinName[30]) {
	break;
	switch (BuiltinName[29]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'h': // 2 strings to match.
	return Intrinsic::hexagon_M2_vmpy2s_s0; // "__built		if (memcmp(BuiltinName.data()+31, "_s", 2))
	in_HEXAGON_M2_vmpy2s_s0"		break;
	case '1': // 1 string to match.		switch (BuiltinName[33]) {
	return Intrinsic::hexagon_M2_vmpy2s_s1; // "__built		default: break;
	in_HEXAGON_M2_vmpy2s_s1"		case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_sat_lh_s0; // "__built
			in_HEXAGON_M2_mpy_sat_lh_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_sat_lh_s1; // "__built
			in_HEXAGON_M2_mpy_sat_lh_s1"
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+31, "_s", 2))
			break;
			switch (BuiltinName[33]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_sat_ll_s0; // "__built
			in_HEXAGON_M2_mpy_sat_ll_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_sat_ll_s1; // "__built
			in_HEXAGON_M2_mpy_sat_ll_s1"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
			case 'u': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "p_s1_sat", 8))
			break;
			return Intrinsic::hexagon_M2_mpy_up_s1_sat; // "__built
			in_HEXAGON_M2_mpy_up_s1_sat"
			}
			break;
			case 'v': // 2 strings to match.
			if (memcmp(BuiltinName.data()+22, "mpy2s_s", 7))
			break;
			switch (BuiltinName[29]) {
			default: break;
			case '0': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "pack", 4))
			break;
			return Intrinsic::hexagon_M2_vmpy2s_s0pack; // "__built
			in_HEXAGON_M2_vmpy2s_s0pack"
			case '1': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "pack", 4))
			break;
			return Intrinsic::hexagon_M2_vmpy2s_s1pack; // "__built
			in_HEXAGON_M2_vmpy2s_s1pack"
	}		}
	break;		break;
	}		}
	break;		break;
	case '4': // 3 strings to match.		case '4': // 3 strings to match.
	if (BuiltinName[20] != '_')		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'c': // 2 strings to match.		case 'm': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "mpy", 3))		switch (BuiltinName[22]) {
	break;
	switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'i': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "_whc", 4))		if (memcmp(BuiltinName.data()+23, "c_up_s1_sat", 11))
	break;		break;
	return Intrinsic::hexagon_M4_cmpyi_whc; // "__builtin_HEXAG		return Intrinsic::hexagon_M4_mac_up_s1_sat; // "__built
	ON_M4_cmpyi_whc"		in_HEXAGON_M4_mac_up_s1_sat"
	case 'r': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "_whc", 4))		if (memcmp(BuiltinName.data()+23, "yri_addr_u2", 11))
	break;		break;
	return Intrinsic::hexagon_M4_cmpyr_whc; // "__builtin_HEXAG ON_M4_cmpyr_whc"		return Intrinsic::hexagon_M4_mpyri_addr_u2; // "__built in_HEXAGON_M4_mpyri_addr_u2"
	}		}
	break;		break;
	case 'p': // 1 string to match.		case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "mpyw_acc", 8))		if (memcmp(BuiltinName.data()+22, "ac_up_s1_sat", 12))
	break;		break;
	return Intrinsic::hexagon_M4_pmpyw_acc; // "__builtin_HEXAG ON_M4_pmpyw_acc"		return Intrinsic::hexagon_M4_nac_up_s1_sat; // "__builtin_HEXAG ON_M4_nac_up_s1_sat"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'S': // 12 strings to match.		case 'S': // 3 strings to match.
	switch (BuiltinName[19]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case '2': // 4 strings to match.		case '2': // 2 strings to match.
	if (BuiltinName[20] != '_')		if (memcmp(BuiltinName.data()+20, "_vsat", 5))
	break;
	switch (BuiltinName[21]) {
	default: break;
	case 'e': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "xtractup", 8))
	break;
	return Intrinsic::hexagon_S2_extractup; // "__builtin_HEXAG
	ON_S2_extractup"
	case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "nsert_rp", 8))
	break;
	return Intrinsic::hexagon_S2_insert_rp; // "__builtin_HEXAG
	ON_S2_insert_rp"
	case 'v': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "splice", 6))
	break;
	switch (BuiltinName[28]) {
	default: break;
	case 'i': // 1 string to match.
	if (BuiltinName[29] != 'b')
	break;
	return Intrinsic::hexagon_S2_vspliceib; // "__builtin_HEXAG
	ON_S2_vspliceib"
	case 'r': // 1 string to match.
	if (BuiltinName[29] != 'b')
	break;
	return Intrinsic::hexagon_S2_vsplicerb; // "__builtin_HEXAG
	ON_S2_vsplicerb"
	}
	break;
	}
	break;
	case '4': // 7 strings to match.
	if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'n': // 2 strings to match.		case 'h': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "tstbit_", 7))		if (memcmp(BuiltinName.data()+26, "b_nopack", 8))
	break;		break;
	switch (BuiltinName[29]) {		return Intrinsic::hexagon_S2_vsathb_nopack; // "__builtin_HEXAG
	default: break;		ON_S2_vsathb_nopack"
	case 'i': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::hexagon_S4_ntstbit_i; // "__builtin_HEXAG		if (memcmp(BuiltinName.data()+26, "h_nopack", 8))
	ON_S4_ntstbit_i"
	case 'r': // 1 string to match.
	return Intrinsic::hexagon_S4_ntstbit_r; // "__builtin_HEXAG
	ON_S4_ntstbit_r"
	}
	break;
	case 'v': // 5 strings to match.
	switch (BuiltinName[22]) {
	default: break;
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "crotate", 7))
	break;
	return Intrinsic::hexagon_S4_vrcrotate; // "__builtin_HEXAG
	ON_S4_vrcrotate"
	case 'x': // 4 strings to match.
	switch (BuiltinName[23]) {
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+24, "ddsub", 5))
	break;
	switch (BuiltinName[29]) {
	default: break;
	case 'h': // 1 string to match.
	return Intrinsic::hexagon_S4_vxaddsubh; // "__built
	in_HEXAGON_S4_vxaddsubh"
	case 'w': // 1 string to match.
	return Intrinsic::hexagon_S4_vxaddsubw; // "__built
	in_HEXAGON_S4_vxaddsubw"
	}
	break;
	case 's': // 2 strings to match.
	if (memcmp(BuiltinName.data()+24, "ubadd", 5))
	break;
	switch (BuiltinName[29]) {
	default: break;
	case 'h': // 1 string to match.
	return Intrinsic::hexagon_S4_vxsubaddh; // "__built
	in_HEXAGON_S4_vxsubaddh"
	case 'w': // 1 string to match.
	return Intrinsic::hexagon_S4_vxsubaddw; // "__built
	in_HEXAGON_S4_vxsubaddw"
	}
	break;
	}
	break;		break;
	}		return Intrinsic::hexagon_S2_vsatwh_nopack; // "__builtin_HEXAG
	break;		ON_S2_vsatwh_nopack"
	}		}
	break;		break;
	case '5': // 1 string to match.		case '4': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "_popcountp", 10))		if (memcmp(BuiltinName.data()+20, "_vrcrotate_acc", 14))
	break;		break;
	return Intrinsic::hexagon_S5_popcountp; // "__builtin_HEXAG ON_S5_popcountp"		return Intrinsic::hexagon_S4_vrcrotate_acc; // "__builtin_HEXAG ON_S4_vrcrotate_acc"
	}		}
	break;		break;
	}		}
	break;		break;
	case 31: // 95 strings to match.		case 35: // 64 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))		if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
	break;		break;
	switch (BuiltinName[18]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'A': // 4 strings to match.		case 'F': // 4 strings to match.
	if (memcmp(BuiltinName.data()+19, "2_combine_", 10))
	break;
	switch (BuiltinName[29]) {
	default: break;
	case 'h': // 2 strings to match.
	switch (BuiltinName[30]) {
	default: break;
	case 'h': // 1 string to match.
	return Intrinsic::hexagon_A2_combine_hh; // "__builtin_HEXAG
	ON_A2_combine_hh"
	case 'l': // 1 string to match.
	return Intrinsic::hexagon_A2_combine_hl; // "__builtin_HEXAG
	ON_A2_combine_hl"
	}
	break;
	case 'l': // 2 strings to match.
	switch (BuiltinName[30]) {
	default: break;
	case 'h': // 1 string to match.
	return Intrinsic::hexagon_A2_combine_lh; // "__builtin_HEXAG
	ON_A2_combine_lh"
	case 'l': // 1 string to match.
	return Intrinsic::hexagon_A2_combine_ll; // "__builtin_HEXAG
	ON_A2_combine_ll"
	}
	break;
	}
	break;
	case 'F': // 10 strings to match.
	if (memcmp(BuiltinName.data()+19, "2_conv_", 7))		if (memcmp(BuiltinName.data()+19, "2_conv_", 7))
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'd': // 3 strings to match.		case 'd': // 2 strings to match.
	if (memcmp(BuiltinName.data()+27, "f2", 2))		if (memcmp(BuiltinName.data()+27, "f2", 2))
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[29]) {
	default: break;		default: break;
	case 's': // 1 string to match.		case 'd': // 1 string to match.
	if (BuiltinName[30] != 'f')		if (memcmp(BuiltinName.data()+30, "_chop", 5))
	break;		break;
	return Intrinsic::hexagon_F2_conv_df2sf; // "__builtin_HEXAG		return Intrinsic::hexagon_F2_conv_df2d_chop; // "__builtin_HEXAG
	ON_F2_conv_df2sf"		ON_F2_conv_df2d_chop"
	case 'u': // 2 strings to match.		case 'w': // 1 string to match.
	switch (BuiltinName[30]) {		if (memcmp(BuiltinName.data()+30, "_chop", 5))
	default: break;		break;
	case 'd': // 1 string to match.		return Intrinsic::hexagon_F2_conv_df2w_chop; // "__builtin_HEXAG
	return Intrinsic::hexagon_F2_conv_df2ud; // "__builtin_HEXAG		ON_F2_conv_df2w_chop"
	ON_F2_conv_df2ud"
	case 'w': // 1 string to match.
	return Intrinsic::hexagon_F2_conv_df2uw; // "__builtin_HEXAG
	ON_F2_conv_df2uw"
	}
	break;
	}		}
	break;		break;
	case 's': // 3 strings to match.		case 's': // 2 strings to match.
	if (memcmp(BuiltinName.data()+27, "f2", 2))		if (memcmp(BuiltinName.data()+27, "f2", 2))
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[29]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (BuiltinName[30] != 'f')		if (memcmp(BuiltinName.data()+30, "_chop", 5))
	break;
	return Intrinsic::hexagon_F2_conv_sf2df; // "__builtin_HEXAG
	ON_F2_conv_sf2df"
	case 'u': // 2 strings to match.
	switch (BuiltinName[30]) {
	default: break;
	case 'd': // 1 string to match.
	return Intrinsic::hexagon_F2_conv_sf2ud; // "__builtin_HEXAG
	ON_F2_conv_sf2ud"
	case 'w': // 1 string to match.
	return Intrinsic::hexagon_F2_conv_sf2uw; // "__builtin_HEXAG
	ON_F2_conv_sf2uw"
	}
	break;
	}
	break;
	case 'u': // 4 strings to match.
	switch (BuiltinName[27]) {
	default: break;
	case 'd': // 2 strings to match.
	if (BuiltinName[28] != '2')
	break;		break;
	switch (BuiltinName[29]) {		return Intrinsic::hexagon_F2_conv_sf2d_chop; // "__builtin_HEXAG
	default: break;		ON_F2_conv_sf2d_chop"
	case 'd': // 1 string to match.		case 'w': // 1 string to match.
	if (BuiltinName[30] != 'f')		if (memcmp(BuiltinName.data()+30, "_chop", 5))
	break;
	return Intrinsic::hexagon_F2_conv_ud2df; // "__builtin_HEXAG
	ON_F2_conv_ud2df"
	case 's': // 1 string to match.
	if (BuiltinName[30] != 'f')
	break;
	return Intrinsic::hexagon_F2_conv_ud2sf; // "__builtin_HEXAG
	ON_F2_conv_ud2sf"
	}
	break;
	case 'w': // 2 strings to match.
	if (BuiltinName[28] != '2')
	break;		break;
	switch (BuiltinName[29]) {		return Intrinsic::hexagon_F2_conv_sf2w_chop; // "__builtin_HEXAG
	default: break;		ON_F2_conv_sf2w_chop"
	case 'd': // 1 string to match.
	if (BuiltinName[30] != 'f')
	break;
	return Intrinsic::hexagon_F2_conv_uw2df; // "__builtin_HEXAG
	ON_F2_conv_uw2df"
	case 's': // 1 string to match.
	if (BuiltinName[30] != 'f')
	break;
	return Intrinsic::hexagon_F2_conv_uw2sf; // "__builtin_HEXAG
	ON_F2_conv_uw2sf"
	}
	break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'M': // 58 strings to match.		case 'M': // 56 strings to match.
	switch (BuiltinName[19]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case '2': // 49 strings to match.		case '2': // 52 strings to match.
	if (BuiltinName[20] != '_')		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'c': // 2 strings to match.		case 'd': // 5 strings to match.
	if (memcmp(BuiltinName.data()+22, "mpyrsc_s", 8))
	break;
	switch (BuiltinName[30]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_cmpyrsc_s0; // "__builtin_HEXAG
	ON_M2_cmpyrsc_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_cmpyrsc_s1; // "__builtin_HEXAG
	ON_M2_cmpyrsc_s1"
	}
	break;
	case 'd': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "pmpy", 4))		if (memcmp(BuiltinName.data()+22, "pmpy", 4))
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[26]) {
	default: break;		default: break;
	case 's': // 1 string to match.		case 's': // 3 strings to match.
	if (memcmp(BuiltinName.data()+27, "s_s0", 4))		if (memcmp(BuiltinName.data()+27, "s_", 2))
	break;		break;
	return Intrinsic::hexagon_M2_dpmpyss_s0; // "__builtin_HEXAG		switch (BuiltinName[29]) {
	ON_M2_dpmpyss_s0"		default: break;
	case 'u': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "u_s0", 4))		if (memcmp(BuiltinName.data()+30, "cc_s0", 5))
			break;
			return Intrinsic::hexagon_M2_dpmpyss_acc_s0; // "__built
			in_HEXAGON_M2_dpmpyss_acc_s0"
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "ac_s0", 5))
			break;
			return Intrinsic::hexagon_M2_dpmpyss_nac_s0; // "__built
			in_HEXAGON_M2_dpmpyss_nac_s0"
			case 'r': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "nd_s0", 5))
			break;
			return Intrinsic::hexagon_M2_dpmpyss_rnd_s0; // "__built
			in_HEXAGON_M2_dpmpyss_rnd_s0"
			}
			break;
			case 'u': // 2 strings to match.
			if (memcmp(BuiltinName.data()+27, "u_", 2))
	break;		break;
	return Intrinsic::hexagon_M2_dpmpyuu_s0; // "__builtin_HEXAG		switch (BuiltinName[29]) {
	ON_M2_dpmpyuu_s0"		default: break;
			case 'a': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "cc_s0", 5))
			break;
			return Intrinsic::hexagon_M2_dpmpyuu_acc_s0; // "__built
			in_HEXAGON_M2_dpmpyuu_acc_s0"
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "ac_s0", 5))
			break;
			return Intrinsic::hexagon_M2_dpmpyuu_nac_s0; // "__built
			in_HEXAGON_M2_dpmpyuu_nac_s0"
			}
			break;
	}		}
	break;		break;
	case 'h': // 2 strings to match.		case 'm': // 40 strings to match.
	if (memcmp(BuiltinName.data()+22, "mmpy", 4))		if (memcmp(BuiltinName.data()+22, "py", 2))
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[24]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'd': // 24 strings to match.
	if (memcmp(BuiltinName.data()+27, "_rs1", 4))		if (BuiltinName[25] != '_')
	break;
	return Intrinsic::hexagon_M2_hmmpyh_rs1; // "__builtin_HEXAG
	ON_M2_hmmpyh_rs1"
	case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "_rs1", 4))
	break;		break;
	return Intrinsic::hexagon_M2_hmmpyl_rs1; // "__builtin_HEXAG		switch (BuiltinName[26]) {
	ON_M2_hmmpyl_rs1"
	}
	break;
	case 'm': // 28 strings to match.
	switch (BuiltinName[22]) {
	default: break;
	case 'm': // 12 strings to match.
	switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'a': // 8 strings to match.		case 'a': // 8 strings to match.
	if (BuiltinName[24] != 'c')		if (memcmp(BuiltinName.data()+27, "cc_", 3))
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[30]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'h': // 4 strings to match.
	if (memcmp(BuiltinName.data()+26, "s_rs", 4))		switch (BuiltinName[31]) {
	break;
	switch (BuiltinName[30]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mmachs_rs0; // "__built
	in_HEXAGON_M2_mmachs_rs0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mmachs_rs1; // "__built
	in_HEXAGON_M2_mmachs_rs1"
	}
	break;
	case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+26, "s_rs", 4))
	break;
	switch (BuiltinName[30]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mmacls_rs0; // "__built
	in_HEXAGON_M2_mmacls_rs0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mmacls_rs1; // "__built
	in_HEXAGON_M2_mmacls_rs1"
	}
	break;
	case 'u': // 4 strings to match.
	switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+27, "s_s", 3))		if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;		break;
	switch (BuiltinName[30]) {		switch (BuiltinName[34]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mmacuhs_s0; // "__built in_HEXAGON_M2_mmacuhs_s0"		return Intrinsic::hexagon_M2_mpyd_acc_hh_s0; // "__builtin_HEXAGON_M2_mpyd_acc_hh_s0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mmacuhs_s1; // "__built in_HEXAGON_M2_mmacuhs_s1"		return Intrinsic::hexagon_M2_mpyd_acc_hh_s1; // "__builtin_HEXAGON_M2_mpyd_acc_hh_s1"
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+27, "s_s", 3))		if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;		break;
	switch (BuiltinName[30]) {		switch (BuiltinName[34]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mmaculs_s0; // "__built in_HEXAGON_M2_mmaculs_s0"		return Intrinsic::hexagon_M2_mpyd_acc_hl_s0; // "__builtin_HEXAGON_M2_mpyd_acc_hl_s0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mmaculs_s1; // "__built in_HEXAGON_M2_mmaculs_s1"		return Intrinsic::hexagon_M2_mpyd_acc_hl_s1; // "__builtin_HEXAGON_M2_mpyd_acc_hl_s1"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'l': // 4 strings to match.
	break;		switch (BuiltinName[31]) {
	case 'p': // 4 strings to match.
	if (memcmp(BuiltinName.data()+24, "yu", 2))
	break;
	switch (BuiltinName[26]) {
	default: break;
	case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+27, "_rs", 3))
	break;
	switch (BuiltinName[30]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'h': // 2 strings to match.
	return Intrinsic::hexagon_M2_mmpyuh_rs0; // "__built		if (memcmp(BuiltinName.data()+32, "_s", 2))
	in_HEXAGON_M2_mmpyuh_rs0"		break;
	case '1': // 1 string to match.		switch (BuiltinName[34]) {
	return Intrinsic::hexagon_M2_mmpyuh_rs1; // "__built		default: break;
	in_HEXAGON_M2_mmpyuh_rs1"		case '0': // 1 string to match.
	}		return Intrinsic::hexagon_M2_mpyd_acc_lh_s0; //
	break;		"__builtin_HEXAGON_M2_mpyd_acc_lh_s0"
	case 'l': // 2 strings to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "_rs", 3))		return Intrinsic::hexagon_M2_mpyd_acc_lh_s1; //
			"__builtin_HEXAGON_M2_mpyd_acc_lh_s1"
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+32, "_s", 2))
			break;
			switch (BuiltinName[34]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyd_acc_ll_s0; //
			"__builtin_HEXAGON_M2_mpyd_acc_ll_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyd_acc_ll_s1; //
			"__builtin_HEXAGON_M2_mpyd_acc_ll_s1"
			}
	break;		break;
	switch (BuiltinName[30]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mmpyul_rs0; // "__built
	in_HEXAGON_M2_mmpyul_rs0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mmpyul_rs1; // "__built
	in_HEXAGON_M2_mmpyul_rs1"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'n': // 8 strings to match.
	break;		if (memcmp(BuiltinName.data()+27, "ac_", 3))
	case 'p': // 16 strings to match.
	if (BuiltinName[23] != 'y')
	break;
	switch (BuiltinName[24]) {
	default: break;
	case 'd': // 8 strings to match.
	if (BuiltinName[25] != '_')
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[30]) {
	default: break;		default: break;
	case 'h': // 4 strings to match.		case 'h': // 4 strings to match.
	switch (BuiltinName[27]) {		switch (BuiltinName[31]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+28, "_s", 2))		if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;		break;
	switch (BuiltinName[30]) {		switch (BuiltinName[34]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_hh_s0; // "__built in_HEXAGON_M2_mpyd_hh_s0"		return Intrinsic::hexagon_M2_mpyd_nac_hh_s0; // "__builtin_HEXAGON_M2_mpyd_nac_hh_s0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_hh_s1; // "__built in_HEXAGON_M2_mpyd_hh_s1"		return Intrinsic::hexagon_M2_mpyd_nac_hh_s1; // "__builtin_HEXAGON_M2_mpyd_nac_hh_s1"
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+28, "_s", 2))		if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;		break;
	switch (BuiltinName[30]) {		switch (BuiltinName[34]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_hl_s0; // "__built in_HEXAGON_M2_mpyd_hl_s0"		return Intrinsic::hexagon_M2_mpyd_nac_hl_s0; // "__builtin_HEXAGON_M2_mpyd_nac_hl_s0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_hl_s1; // "__built in_HEXAGON_M2_mpyd_hl_s1"		return Intrinsic::hexagon_M2_mpyd_nac_hl_s1; // "__builtin_HEXAGON_M2_mpyd_nac_hl_s1"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'l': // 4 strings to match.		case 'l': // 4 strings to match.
	switch (BuiltinName[27]) {		switch (BuiltinName[31]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+28, "_s", 2))		if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;		break;
	switch (BuiltinName[30]) {		switch (BuiltinName[34]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_lh_s0; // "__built in_HEXAGON_M2_mpyd_lh_s0"		return Intrinsic::hexagon_M2_mpyd_nac_lh_s0; // "__builtin_HEXAGON_M2_mpyd_nac_lh_s0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_lh_s1; // "__built in_HEXAGON_M2_mpyd_lh_s1"		return Intrinsic::hexagon_M2_mpyd_nac_lh_s1; // "__builtin_HEXAGON_M2_mpyd_nac_lh_s1"
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+28, "_s", 2))		if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;		break;
	switch (BuiltinName[30]) {		switch (BuiltinName[34]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_ll_s0; // "__built in_HEXAGON_M2_mpyd_ll_s0"		return Intrinsic::hexagon_M2_mpyd_nac_ll_s0; // "__builtin_HEXAGON_M2_mpyd_nac_ll_s0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_ll_s1; // "__built in_HEXAGON_M2_mpyd_ll_s1"		return Intrinsic::hexagon_M2_mpyd_nac_ll_s1; // "__builtin_HEXAGON_M2_mpyd_nac_ll_s1"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'u': // 8 strings to match.		case 'r': // 8 strings to match.
	if (BuiltinName[25] != '_')		if (memcmp(BuiltinName.data()+27, "nd_", 3))
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[30]) {
	default: break;		default: break;
	case 'h': // 4 strings to match.		case 'h': // 4 strings to match.
	switch (BuiltinName[27]) {		switch (BuiltinName[31]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+28, "_s", 2))		if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;		break;
	switch (BuiltinName[30]) {		switch (BuiltinName[34]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyu_hh_s0; // "__built in_HEXAGON_M2_mpyu_hh_s0"		return Intrinsic::hexagon_M2_mpyd_rnd_hh_s0; // "__builtin_HEXAGON_M2_mpyd_rnd_hh_s0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyu_hh_s1; // "__built in_HEXAGON_M2_mpyu_hh_s1"		return Intrinsic::hexagon_M2_mpyd_rnd_hh_s1; // "__builtin_HEXAGON_M2_mpyd_rnd_hh_s1"
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+28, "_s", 2))		if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;		break;
	switch (BuiltinName[30]) {		switch (BuiltinName[34]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyu_hl_s0; // "__built in_HEXAGON_M2_mpyu_hl_s0"		return Intrinsic::hexagon_M2_mpyd_rnd_hl_s0; // "__builtin_HEXAGON_M2_mpyd_rnd_hl_s0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyu_hl_s1; // "__built in_HEXAGON_M2_mpyu_hl_s1"		return Intrinsic::hexagon_M2_mpyd_rnd_hl_s1; // "__builtin_HEXAGON_M2_mpyd_rnd_hl_s1"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'l': // 4 strings to match.		case 'l': // 4 strings to match.
	switch (BuiltinName[27]) {		switch (BuiltinName[31]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+28, "_s", 2))		if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;		break;
	switch (BuiltinName[30]) {		switch (BuiltinName[34]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyu_lh_s0; // "__built in_HEXAGON_M2_mpyu_lh_s0"		return Intrinsic::hexagon_M2_mpyd_rnd_lh_s0; // "__builtin_HEXAGON_M2_mpyd_rnd_lh_s0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyu_lh_s1; // "__built in_HEXAGON_M2_mpyu_lh_s1"		return Intrinsic::hexagon_M2_mpyd_rnd_lh_s1; // "__builtin_HEXAGON_M2_mpyd_rnd_lh_s1"
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+28, "_s", 2))		if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;		break;
	switch (BuiltinName[30]) {		switch (BuiltinName[34]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyu_ll_s0; // "__built in_HEXAGON_M2_mpyu_ll_s0"		return Intrinsic::hexagon_M2_mpyd_rnd_ll_s0; // "__builtin_HEXAGON_M2_mpyd_rnd_ll_s0"
	case '1': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyu_ll_s1; // "__built in_HEXAGON_M2_mpyu_ll_s1"		return Intrinsic::hexagon_M2_mpyd_rnd_ll_s1; // "__builtin_HEXAGON_M2_mpyd_rnd_ll_s1"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'u': // 16 strings to match.
	break;		if (BuiltinName[25] != '_')
	case 'v': // 15 strings to match.
	switch (BuiltinName[22]) {
	default: break;
	case 'd': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "mpyrs_s", 7))
	break;		break;
	switch (BuiltinName[30]) {		switch (BuiltinName[26]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_vdmpyrs_s0; // "__builtin_HEXAG
	ON_M2_vdmpyrs_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_vdmpyrs_s1; // "__builtin_HEXAG
	ON_M2_vdmpyrs_s1"
	}
	break;
	case 'm': // 8 strings to match.
	switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'a': // 4 strings to match.		case 'a': // 8 strings to match.
	if (memcmp(BuiltinName.data()+24, "c2", 2))		if (memcmp(BuiltinName.data()+27, "cc_", 3))
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[30]) {
	default: break;		default: break;
	case 'e': // 2 strings to match.		case 'h': // 4 strings to match.
	if (memcmp(BuiltinName.data()+27, "s_s", 3))		switch (BuiltinName[31]) {
	break;
	switch (BuiltinName[30]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'h': // 2 strings to match.
	return Intrinsic::hexagon_M2_vmac2es_s0; // "__built		if (memcmp(BuiltinName.data()+32, "_s", 2))
	in_HEXAGON_M2_vmac2es_s0"		break;
	case '1': // 1 string to match.		switch (BuiltinName[34]) {
	return Intrinsic::hexagon_M2_vmac2es_s1; // "__built		default: break;
	in_HEXAGON_M2_vmac2es_s1"		case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_acc_hh_s0; //
			"__builtin_HEXAGON_M2_mpyu_acc_hh_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_acc_hh_s1; //
			"__builtin_HEXAGON_M2_mpyu_acc_hh_s1"
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+32, "_s", 2))
			break;
			switch (BuiltinName[34]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_acc_hl_s0; //
			"__builtin_HEXAGON_M2_mpyu_acc_hl_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_acc_hl_s1; //
			"__builtin_HEXAGON_M2_mpyu_acc_hl_s1"
			}
			break;
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 'l': // 4 strings to match.
	if (memcmp(BuiltinName.data()+27, "u_s", 3))		switch (BuiltinName[31]) {
	break;
	switch (BuiltinName[30]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'h': // 2 strings to match.
	return Intrinsic::hexagon_M2_vmac2su_s0; // "__built		if (memcmp(BuiltinName.data()+32, "_s", 2))
	in_HEXAGON_M2_vmac2su_s0"		break;
	case '1': // 1 string to match.		switch (BuiltinName[34]) {
	return Intrinsic::hexagon_M2_vmac2su_s1; // "__built		default: break;
	in_HEXAGON_M2_vmac2su_s1"		case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_acc_lh_s0; //
			"__builtin_HEXAGON_M2_mpyu_acc_lh_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_acc_lh_s1; //
			"__builtin_HEXAGON_M2_mpyu_acc_lh_s1"
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+32, "_s", 2))
			break;
			switch (BuiltinName[34]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_acc_ll_s0; //
			"__builtin_HEXAGON_M2_mpyu_acc_ll_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_acc_ll_s1; //
			"__builtin_HEXAGON_M2_mpyu_acc_ll_s1"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'p': // 4 strings to match.		case 'n': // 8 strings to match.
	if (memcmp(BuiltinName.data()+24, "y2", 2))		if (memcmp(BuiltinName.data()+27, "ac_", 3))
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[30]) {
	default: break;		default: break;
	case 'e': // 2 strings to match.		case 'h': // 4 strings to match.
	if (memcmp(BuiltinName.data()+27, "s_s", 3))		switch (BuiltinName[31]) {
	break;
	switch (BuiltinName[30]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'h': // 2 strings to match.
	return Intrinsic::hexagon_M2_vmpy2es_s0; // "__built		if (memcmp(BuiltinName.data()+32, "_s", 2))
	in_HEXAGON_M2_vmpy2es_s0"		break;
	case '1': // 1 string to match.		switch (BuiltinName[34]) {
	return Intrinsic::hexagon_M2_vmpy2es_s1; // "__built		default: break;
	in_HEXAGON_M2_vmpy2es_s1"		case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_nac_hh_s0; //
			"__builtin_HEXAGON_M2_mpyu_nac_hh_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_nac_hh_s1; //
			"__builtin_HEXAGON_M2_mpyu_nac_hh_s1"
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+32, "_s", 2))
			break;
			switch (BuiltinName[34]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_nac_hl_s0; //
			"__builtin_HEXAGON_M2_mpyu_nac_hl_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_nac_hl_s1; //
			"__builtin_HEXAGON_M2_mpyu_nac_hl_s1"
			}
			break;
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 'l': // 4 strings to match.
	if (memcmp(BuiltinName.data()+27, "u_s", 3))		switch (BuiltinName[31]) {
			default: break;
			case 'h': // 2 strings to match.
			if (memcmp(BuiltinName.data()+32, "_s", 2))
			break;
			switch (BuiltinName[34]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_nac_lh_s0; //
			"__builtin_HEXAGON_M2_mpyu_nac_lh_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_nac_lh_s1; //
			"__builtin_HEXAGON_M2_mpyu_nac_lh_s1"
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+32, "_s", 2))
			break;
			switch (BuiltinName[34]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_nac_ll_s0; //
			"__builtin_HEXAGON_M2_mpyu_nac_ll_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyu_nac_ll_s1; //
			"__builtin_HEXAGON_M2_mpyu_nac_ll_s1"
			}
	break;		break;
	switch (BuiltinName[30]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_vmpy2su_s0; // "__built
	in_HEXAGON_M2_vmpy2su_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_vmpy2su_s1; // "__built
	in_HEXAGON_M2_vmpy2su_s1"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'r': // 5 strings to match.		}
	if (memcmp(BuiltinName.data()+23, "cm", 2))		break;
			case 'v': // 7 strings to match.
			switch (BuiltinName[22]) {
			default: break;
			case 'c': // 6 strings to match.
			if (BuiltinName[23] != 'm')
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[24]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'a': // 2 strings to match.
	if (BuiltinName[26] != 'c')		if (memcmp(BuiltinName.data()+25, "c_s0_sat_", 9))
	break;		break;
	switch (BuiltinName[27]) {		switch (BuiltinName[34]) {
	default: break;		default: break;
	case 'i': // 1 string to match.		case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "_s0", 3))		return Intrinsic::hexagon_M2_vcmac_s0_sat_i; // "__built
	break;		in_HEXAGON_M2_vcmac_s0_sat_i"
	return Intrinsic::hexagon_M2_vrcmaci_s0; // "__built
	in_HEXAGON_M2_vrcmaci_s0"
	case 'r': // 1 string to match.		case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "_s0", 3))		return Intrinsic::hexagon_M2_vcmac_s0_sat_r; // "__built
	break;		in_HEXAGON_M2_vcmac_s0_sat_r"
	return Intrinsic::hexagon_M2_vrcmacr_s0; // "__built
	in_HEXAGON_M2_vrcmacr_s0"
	}		}
	break;		break;
	case 'p': // 3 strings to match.		case 'p': // 4 strings to match.
	if (BuiltinName[26] != 'y')		if (memcmp(BuiltinName.data()+25, "y_s", 3))
	break;		break;
	switch (BuiltinName[27]) {		switch (BuiltinName[28]) {
	default: break;		default: break;
	case 'i': // 1 string to match.		case '0': // 2 strings to match.
	if (memcmp(BuiltinName.data()+28, "_s0", 3))		if (memcmp(BuiltinName.data()+29, "_sat_", 5))
	break;
	return Intrinsic::hexagon_M2_vrcmpyi_s0; // "__built
	in_HEXAGON_M2_vrcmpyi_s0"
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "_s0", 3))
	break;		break;
	return Intrinsic::hexagon_M2_vrcmpyr_s0; // "__built		switch (BuiltinName[34]) {
	in_HEXAGON_M2_vrcmpyr_s0"		default: break;
	case 's': // 1 string to match.		case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "_s1", 3))		return Intrinsic::hexagon_M2_vcmpy_s0_sat_i; // "__built
			in_HEXAGON_M2_vcmpy_s0_sat_i"
			case 'r': // 1 string to match.
			return Intrinsic::hexagon_M2_vcmpy_s0_sat_r; // "__built
			in_HEXAGON_M2_vcmpy_s0_sat_r"
			}
			break;
			case '1': // 2 strings to match.
			if (memcmp(BuiltinName.data()+29, "_sat_", 5))
	break;		break;
	return Intrinsic::hexagon_M2_vrcmpys_s1; // "__built		switch (BuiltinName[34]) {
	in_HEXAGON_M2_vrcmpys_s1"		default: break;
			case 'i': // 1 string to match.
			return Intrinsic::hexagon_M2_vcmpy_s1_sat_i; // "__built
			in_HEXAGON_M2_vcmpy_s1_sat_i"
			case 'r': // 1 string to match.
			return Intrinsic::hexagon_M2_vcmpy_s1_sat_r; // "__built
			in_HEXAGON_M2_vcmpy_s1_sat_r"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
			case 'r': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "cmpys_acc_s1", 12))
			break;
			return Intrinsic::hexagon_M2_vrcmpys_acc_s1; // "__built
			in_HEXAGON_M2_vrcmpys_acc_s1"
	}		}
	break;		break;
	}		}
	break;		break;
	case '4': // 9 strings to match.		case '4': // 4 strings to match.
	if (BuiltinName[20] != '_')		if (memcmp(BuiltinName.data()+20, "_vrmpy", 6))
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'm': // 4 strings to match.		case 'e': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "pyr", 3))		if (memcmp(BuiltinName.data()+27, "h_acc_s", 7))
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[34]) {
	default: break;		default: break;
	case 'i': // 2 strings to match.		case '0': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "_add", 4))		return Intrinsic::hexagon_M4_vrmpyeh_acc_s0; // "__built
			in_HEXAGON_M4_vrmpyeh_acc_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M4_vrmpyeh_acc_s1; // "__built
			in_HEXAGON_M4_vrmpyeh_acc_s1"
			}
			break;
			case 'o': // 2 strings to match.
			if (memcmp(BuiltinName.data()+27, "h_acc_s", 7))
			break;
			switch (BuiltinName[34]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M4_vrmpyoh_acc_s0; // "__built
			in_HEXAGON_M4_vrmpyoh_acc_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M4_vrmpyoh_acc_s1; // "__built
			in_HEXAGON_M4_vrmpyoh_acc_s1"
			}
			break;
			}
			break;
			}
			break;
			case 'S': // 4 strings to match.
			if (memcmp(BuiltinName.data()+19, "2_", 2))
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(BuiltinName.data()+22, "sr_", 3))
			break;
			switch (BuiltinName[25]) {
			default: break;
			case 'i': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "_svw_trun", 9))
			break;
			return Intrinsic::hexagon_S2_asr_i_svw_trun; // "__builtin_HEXAG
			ON_S2_asr_i_svw_trun"
			case 'r': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "_svw_trun", 9))
			break;
			return Intrinsic::hexagon_S2_asr_r_svw_trun; // "__builtin_HEXAG
			ON_S2_asr_r_svw_trun"
			}
			break;
			case 'v': // 2 strings to match.
			if (memcmp(BuiltinName.data()+22, "sat", 3))
			break;
			switch (BuiltinName[25]) {
			default: break;
			case 'h': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "ub_nopack", 9))
			break;
			return Intrinsic::hexagon_S2_vsathub_nopack; // "__builtin_HEXAG
			ON_S2_vsathub_nopack"
			case 'w': // 1 string to match.
			if (memcmp(BuiltinName.data()+26, "uh_nopack", 9))
			break;
			return Intrinsic::hexagon_S2_vsatwuh_nopack; // "__builtin_HEXAG
			ON_S2_vsatwuh_nopack"
			}
			break;
			}
			break;
			}
			break;
			case 36: // 33 strings to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
			break;
			switch (BuiltinName[18]) {
			default: break;
			case 'A': // 12 strings to match.
			if (memcmp(BuiltinName.data()+19, "2_", 2))
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'a': // 6 strings to match.
			if (memcmp(BuiltinName.data()+22, "ddh_", 4))
			break;
			switch (BuiltinName[26]) {
			default: break;
			case 'h': // 4 strings to match.
			if (memcmp(BuiltinName.data()+27, "16_sat_", 7))
			break;
			switch (BuiltinName[34]) {
			default: break;
			case 'h': // 2 strings to match.
			switch (BuiltinName[35]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_A2_addh_h16_sat_hh; // "__built
			in_HEXAGON_A2_addh_h16_sat_hh"
			case 'l': // 1 string to match.
			return Intrinsic::hexagon_A2_addh_h16_sat_hl; // "__built
			in_HEXAGON_A2_addh_h16_sat_hl"
			}
			break;
			case 'l': // 2 strings to match.
			switch (BuiltinName[35]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_A2_addh_h16_sat_lh; // "__built
			in_HEXAGON_A2_addh_h16_sat_lh"
			case 'l': // 1 string to match.
			return Intrinsic::hexagon_A2_addh_h16_sat_ll; // "__built
			in_HEXAGON_A2_addh_h16_sat_ll"
			}
			break;
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+27, "16_sat_", 7))
			break;
			switch (BuiltinName[34]) {
			default: break;
			case 'h': // 1 string to match.
			if (BuiltinName[35] != 'l')
	break;		break;
	switch (BuiltinName[30]) {		return Intrinsic::hexagon_A2_addh_l16_sat_hl; // "__built
			in_HEXAGON_A2_addh_l16_sat_hl"
			case 'l': // 1 string to match.
			if (BuiltinName[35] != 'l')
			break;
			return Intrinsic::hexagon_A2_addh_l16_sat_ll; // "__built
			in_HEXAGON_A2_addh_l16_sat_ll"
			}
			break;
			}
			break;
			case 's': // 6 strings to match.
			if (memcmp(BuiltinName.data()+22, "ubh_", 4))
			break;
			switch (BuiltinName[26]) {
			default: break;
			case 'h': // 4 strings to match.
			if (memcmp(BuiltinName.data()+27, "16_sat_", 7))
			break;
			switch (BuiltinName[34]) {
			default: break;
			case 'h': // 2 strings to match.
			switch (BuiltinName[35]) {
	default: break;		default: break;
	case 'i': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::hexagon_M4_mpyri_addi; // "__builtin_HEXAG		return Intrinsic::hexagon_A2_subh_h16_sat_hh; // "__built
	ON_M4_mpyri_addi"		in_HEXAGON_A2_subh_h16_sat_hh"
	case 'r': // 1 string to match.		case 'l': // 1 string to match.
	return Intrinsic::hexagon_M4_mpyri_addr; // "__builtin_HEXAG		return Intrinsic::hexagon_A2_subh_h16_sat_hl; // "__built
	ON_M4_mpyri_addr"		in_HEXAGON_A2_subh_h16_sat_hl"
	}		}
	break;		break;
	case 'r': // 2 strings to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+26, "_add", 4))		switch (BuiltinName[35]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::hexagon_A2_subh_h16_sat_lh; // "__built
			in_HEXAGON_A2_subh_h16_sat_lh"
			case 'l': // 1 string to match.
			return Intrinsic::hexagon_A2_subh_h16_sat_ll; // "__built
			in_HEXAGON_A2_subh_h16_sat_ll"
			}
			break;
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+27, "16_sat_", 7))
			break;
			switch (BuiltinName[34]) {
			default: break;
			case 'h': // 1 string to match.
			if (BuiltinName[35] != 'l')
	break;		break;
	switch (BuiltinName[30]) {		return Intrinsic::hexagon_A2_subh_l16_sat_hl; // "__built
			in_HEXAGON_A2_subh_l16_sat_hl"
			case 'l': // 1 string to match.
			if (BuiltinName[35] != 'l')
			break;
			return Intrinsic::hexagon_A2_subh_l16_sat_ll; // "__built
			in_HEXAGON_A2_subh_l16_sat_ll"
			}
			break;
			}
			break;
			}
			break;
			case 'C': // 1 string to match.
			if (memcmp(BuiltinName.data()+19, "4_fastcorner9_not", 17))
			break;
			return Intrinsic::hexagon_C4_fastcorner9_not; // "__builtin_HEXAG
			ON_C4_fastcorner9_not"
			case 'F': // 4 strings to match.
			if (memcmp(BuiltinName.data()+19, "2_conv_", 7))
			break;
			switch (BuiltinName[26]) {
			default: break;
			case 'd': // 2 strings to match.
			if (memcmp(BuiltinName.data()+27, "f2u", 3))
			break;
			switch (BuiltinName[30]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+31, "_chop", 5))
			break;
			return Intrinsic::hexagon_F2_conv_df2ud_chop; // "__built
			in_HEXAGON_F2_conv_df2ud_chop"
			case 'w': // 1 string to match.
			if (memcmp(BuiltinName.data()+31, "_chop", 5))
			break;
			return Intrinsic::hexagon_F2_conv_df2uw_chop; // "__built
			in_HEXAGON_F2_conv_df2uw_chop"
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(BuiltinName.data()+27, "f2u", 3))
			break;
			switch (BuiltinName[30]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+31, "_chop", 5))
			break;
			return Intrinsic::hexagon_F2_conv_sf2ud_chop; // "__built
			in_HEXAGON_F2_conv_sf2ud_chop"
			case 'w': // 1 string to match.
			if (memcmp(BuiltinName.data()+31, "_chop", 5))
			break;
			return Intrinsic::hexagon_F2_conv_sf2uw_chop; // "__built
			in_HEXAGON_F2_conv_sf2uw_chop"
			}
			break;
			}
			break;
			case 'M': // 16 strings to match.
			if (memcmp(BuiltinName.data()+19, "2_mpyud_", 8))
			break;
			switch (BuiltinName[27]) {
			default: break;
			case 'a': // 8 strings to match.
			if (memcmp(BuiltinName.data()+28, "cc_", 3))
			break;
			switch (BuiltinName[31]) {
			default: break;
			case 'h': // 4 strings to match.
			switch (BuiltinName[32]) {
			default: break;
			case 'h': // 2 strings to match.
			if (memcmp(BuiltinName.data()+33, "_s", 2))
			break;
			switch (BuiltinName[35]) {
	default: break;		default: break;
	case 'i': // 1 string to match.		case '0': // 1 string to match.
	return Intrinsic::hexagon_M4_mpyrr_addi; // "__builtin_HEXAG		return Intrinsic::hexagon_M2_mpyud_acc_hh_s0; // "__built
	ON_M4_mpyrr_addi"		in_HEXAGON_M2_mpyud_acc_hh_s0"
	case 'r': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M4_mpyrr_addr; // "__builtin_HEXAG		return Intrinsic::hexagon_M2_mpyud_acc_hh_s1; // "__built
	ON_M4_mpyrr_addr"		in_HEXAGON_M2_mpyud_acc_hh_s1"
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+33, "_s", 2))
			break;
			switch (BuiltinName[35]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyud_acc_hl_s0; // "__built
			in_HEXAGON_M2_mpyud_acc_hl_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyud_acc_hl_s1; // "__built
			in_HEXAGON_M2_mpyud_acc_hl_s1"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'v': // 5 strings to match.		case 'l': // 4 strings to match.
	switch (BuiltinName[22]) {		switch (BuiltinName[32]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "mpyh_acc", 8))		if (memcmp(BuiltinName.data()+33, "_s", 2))
	break;		break;
	return Intrinsic::hexagon_M4_vpmpyh_acc; // "__builtin_HEXAG		switch (BuiltinName[35]) {
	ON_M4_vpmpyh_acc"		default: break;
	case 'r': // 4 strings to match.		case '0': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "mpy", 3))		return Intrinsic::hexagon_M2_mpyud_acc_lh_s0; // "__built
			in_HEXAGON_M2_mpyud_acc_lh_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyud_acc_lh_s1; // "__built
			in_HEXAGON_M2_mpyud_acc_lh_s1"
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+33, "_s", 2))
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[35]) {
	default: break;		default: break;
	case 'e': // 2 strings to match.		case '0': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "h_s", 3))		return Intrinsic::hexagon_M2_mpyud_acc_ll_s0; // "__built
	break;		in_HEXAGON_M2_mpyud_acc_ll_s0"
	switch (BuiltinName[30]) {		case '1': // 1 string to match.
	default: break;		return Intrinsic::hexagon_M2_mpyud_acc_ll_s1; // "__built
	case '0': // 1 string to match.		in_HEXAGON_M2_mpyud_acc_ll_s1"
	return Intrinsic::hexagon_M4_vrmpyeh_s0; // "__built		}
	in_HEXAGON_M4_vrmpyeh_s0"		break;
	case '1': // 1 string to match.		}
	return Intrinsic::hexagon_M4_vrmpyeh_s1; // "__built		break;
	in_HEXAGON_M4_vrmpyeh_s1"		}
	}		break;
			case 'n': // 8 strings to match.
			if (memcmp(BuiltinName.data()+28, "ac_", 3))
			break;
			switch (BuiltinName[31]) {
			default: break;
			case 'h': // 4 strings to match.
			switch (BuiltinName[32]) {
			default: break;
			case 'h': // 2 strings to match.
			if (memcmp(BuiltinName.data()+33, "_s", 2))
	break;		break;
	case 'o': // 2 strings to match.		switch (BuiltinName[35]) {
	if (memcmp(BuiltinName.data()+27, "h_s", 3))		default: break;
	break;		case '0': // 1 string to match.
	switch (BuiltinName[30]) {		return Intrinsic::hexagon_M2_mpyud_nac_hh_s0; // "__built
	default: break;		in_HEXAGON_M2_mpyud_nac_hh_s0"
	case '0': // 1 string to match.		case '1': // 1 string to match.
	return Intrinsic::hexagon_M4_vrmpyoh_s0; // "__built		return Intrinsic::hexagon_M2_mpyud_nac_hh_s1; // "__built
	in_HEXAGON_M4_vrmpyoh_s0"		in_HEXAGON_M2_mpyud_nac_hh_s1"
	case '1': // 1 string to match.		}
	return Intrinsic::hexagon_M4_vrmpyoh_s1; // "__built		break;
	in_HEXAGON_M4_vrmpyoh_s1"		case 'l': // 2 strings to match.
	}		if (memcmp(BuiltinName.data()+33, "_s", 2))
			break;
			switch (BuiltinName[35]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyud_nac_hl_s0; // "__built
			in_HEXAGON_M2_mpyud_nac_hl_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyud_nac_hl_s1; // "__built
			in_HEXAGON_M2_mpyud_nac_hl_s1"
			}
			break;
			}
			break;
			case 'l': // 4 strings to match.
			switch (BuiltinName[32]) {
			default: break;
			case 'h': // 2 strings to match.
			if (memcmp(BuiltinName.data()+33, "_s", 2))
			break;
			switch (BuiltinName[35]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyud_nac_lh_s0; // "__built
			in_HEXAGON_M2_mpyud_nac_lh_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyud_nac_lh_s1; // "__built
			in_HEXAGON_M2_mpyud_nac_lh_s1"
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+33, "_s", 2))
	break;		break;
			switch (BuiltinName[35]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyud_nac_ll_s0; // "__built
			in_HEXAGON_M2_mpyud_nac_ll_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpyud_nac_ll_s1; // "__built
			in_HEXAGON_M2_mpyud_nac_ll_s1"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'S': // 23 strings to match.		}
	switch (BuiltinName[19]) {		break;
			case 38: // 24 strings to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_M2_mpy_", 25))
			break;
			switch (BuiltinName[25]) {
			default: break;
			case 'a': // 8 strings to match.
			if (memcmp(BuiltinName.data()+26, "cc_sat_", 7))
			break;
			switch (BuiltinName[33]) {
			default: break;
			case 'h': // 4 strings to match.
			switch (BuiltinName[34]) {
			default: break;
			case 'h': // 2 strings to match.
			if (memcmp(BuiltinName.data()+35, "_s", 2))
			break;
			switch (BuiltinName[37]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_acc_sat_hh_s0; // "__built
			in_HEXAGON_M2_mpy_acc_sat_hh_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_acc_sat_hh_s1; // "__built
			in_HEXAGON_M2_mpy_acc_sat_hh_s1"
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+35, "_s", 2))
			break;
			switch (BuiltinName[37]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_acc_sat_hl_s0; // "__built
			in_HEXAGON_M2_mpy_acc_sat_hl_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_acc_sat_hl_s1; // "__built
			in_HEXAGON_M2_mpy_acc_sat_hl_s1"
			}
			break;
			}
			break;
			case 'l': // 4 strings to match.
			switch (BuiltinName[34]) {
			default: break;
			case 'h': // 2 strings to match.
			if (memcmp(BuiltinName.data()+35, "_s", 2))
			break;
			switch (BuiltinName[37]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_acc_sat_lh_s0; // "__built
			in_HEXAGON_M2_mpy_acc_sat_lh_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_acc_sat_lh_s1; // "__built
			in_HEXAGON_M2_mpy_acc_sat_lh_s1"
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+35, "_s", 2))
			break;
			switch (BuiltinName[37]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_acc_sat_ll_s0; // "__built
			in_HEXAGON_M2_mpy_acc_sat_ll_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_acc_sat_ll_s1; // "__built
			in_HEXAGON_M2_mpy_acc_sat_ll_s1"
			}
			break;
			}
			break;
			}
			break;
			case 'n': // 8 strings to match.
			if (memcmp(BuiltinName.data()+26, "ac_sat_", 7))
			break;
			switch (BuiltinName[33]) {
	default: break;		default: break;
	case '2': // 17 strings to match.		case 'h': // 4 strings to match.
	if (BuiltinName[20] != '_')		switch (BuiltinName[34]) {
	break;
	switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'a': // 8 strings to match.		case 'h': // 2 strings to match.
	if (BuiltinName[22] != 's')		if (memcmp(BuiltinName.data()+35, "_s", 2))
	break;		break;
	switch (BuiltinName[23]) {		switch (BuiltinName[37]) {
	default: break;		default: break;
	case 'l': // 4 strings to match.		case '0': // 1 string to match.
	if (BuiltinName[24] != '_')		return Intrinsic::hexagon_M2_mpy_nac_sat_hh_s0; // "__built
	break;		in_HEXAGON_M2_mpy_nac_sat_hh_s0"
	switch (BuiltinName[25]) {		case '1': // 1 string to match.
	default: break;		return Intrinsic::hexagon_M2_mpy_nac_sat_hh_s1; // "__built
	case 'i': // 2 strings to match.		in_HEXAGON_M2_mpy_nac_sat_hh_s1"
	if (BuiltinName[26] != '_')
	break;
	switch (BuiltinName[27]) {
	default: break;
	case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "_or", 3))
	break;
	return Intrinsic::hexagon_S2_asl_i_p_or; // "__built
	in_HEXAGON_S2_asl_i_p_or"
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "_or", 3))
	break;
	return Intrinsic::hexagon_S2_asl_i_r_or; // "__built
	in_HEXAGON_S2_asl_i_r_or"
	}
	break;
	case 'r': // 2 strings to match.
	if (BuiltinName[26] != '_')
	break;
	switch (BuiltinName[27]) {
	default: break;
	case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "_or", 3))
	break;
	return Intrinsic::hexagon_S2_asl_r_p_or; // "__built
	in_HEXAGON_S2_asl_r_p_or"
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "_or", 3))
	break;
	return Intrinsic::hexagon_S2_asl_r_r_or; // "__built
	in_HEXAGON_S2_asl_r_r_or"
	}
	break;
	}
	break;
	case 'r': // 4 strings to match.
	if (BuiltinName[24] != '_')
	break;
	switch (BuiltinName[25]) {
	default: break;
	case 'i': // 2 strings to match.
	if (BuiltinName[26] != '_')
	break;
	switch (BuiltinName[27]) {
	default: break;
	case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "_or", 3))
	break;
	return Intrinsic::hexagon_S2_asr_i_p_or; // "__built
	in_HEXAGON_S2_asr_i_p_or"
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "_or", 3))
	break;
	return Intrinsic::hexagon_S2_asr_i_r_or; // "__built
	in_HEXAGON_S2_asr_i_r_or"
	}
	break;
	case 'r': // 2 strings to match.
	if (BuiltinName[26] != '_')
	break;
	switch (BuiltinName[27]) {
	default: break;
	case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "_or", 3))
	break;
	return Intrinsic::hexagon_S2_asr_r_p_or; // "__built
	in_HEXAGON_S2_asr_r_p_or"
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "_or", 3))
	break;
	return Intrinsic::hexagon_S2_asr_r_r_or; // "__built
	in_HEXAGON_S2_asr_r_r_or"
	}
	break;
	}
	break;
	}		}
	break;		break;
	case 'i': // 2 strings to match.		case 'l': // 2 strings to match.
	if (BuiltinName[22] != 'n')		if (memcmp(BuiltinName.data()+35, "_s", 2))
	break;		break;
	switch (BuiltinName[23]) {		switch (BuiltinName[37]) {
	default: break;		default: break;
	case 's': // 1 string to match.		case '0': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "ertp_rp", 7))		return Intrinsic::hexagon_M2_mpy_nac_sat_hl_s0; // "__built
	break;		in_HEXAGON_M2_mpy_nac_sat_hl_s0"
	return Intrinsic::hexagon_S2_insertp_rp; // "__builtin_HEXAG		case '1': // 1 string to match.
	ON_S2_insertp_rp"		return Intrinsic::hexagon_M2_mpy_nac_sat_hl_s1; // "__built
	case 't': // 1 string to match.		in_HEXAGON_M2_mpy_nac_sat_hl_s1"
	if (memcmp(BuiltinName.data()+24, "erleave", 7))
	break;
	return Intrinsic::hexagon_S2_interleave; // "__builtin_HEXAG
	ON_S2_interleave"
	}		}
	break;		break;
	case 'l': // 6 strings to match.		}
	if (BuiltinName[22] != 's')		break;
			case 'l': // 4 strings to match.
			switch (BuiltinName[34]) {
			default: break;
			case 'h': // 2 strings to match.
			if (memcmp(BuiltinName.data()+35, "_s", 2))
	break;		break;
	switch (BuiltinName[23]) {		switch (BuiltinName[37]) {
	default: break;		default: break;
	case 'l': // 2 strings to match.		case '0': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "_r_", 3))		return Intrinsic::hexagon_M2_mpy_nac_sat_lh_s0; // "__built
	break;		in_HEXAGON_M2_mpy_nac_sat_lh_s0"
	switch (BuiltinName[27]) {		case '1': // 1 string to match.
	default: break;		return Intrinsic::hexagon_M2_mpy_nac_sat_lh_s1; // "__built
	case 'p': // 1 string to match.		in_HEXAGON_M2_mpy_nac_sat_lh_s1"
	if (memcmp(BuiltinName.data()+28, "_or", 3))		}
	break;		break;
	return Intrinsic::hexagon_S2_lsl_r_p_or; // "__builtin_HEXAG		case 'l': // 2 strings to match.
	ON_S2_lsl_r_p_or"		if (memcmp(BuiltinName.data()+35, "_s", 2))
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "_or", 3))
	break;
	return Intrinsic::hexagon_S2_lsl_r_r_or; // "__builtin_HEXAG
	ON_S2_lsl_r_r_or"
	}
	break;		break;
	case 'r': // 4 strings to match.		switch (BuiltinName[37]) {
	if (BuiltinName[24] != '_')		default: break;
	break;		case '0': // 1 string to match.
	switch (BuiltinName[25]) {		return Intrinsic::hexagon_M2_mpy_nac_sat_ll_s0; // "__built
	default: break;		in_HEXAGON_M2_mpy_nac_sat_ll_s0"
	case 'i': // 2 strings to match.		case '1': // 1 string to match.
	if (BuiltinName[26] != '_')		return Intrinsic::hexagon_M2_mpy_nac_sat_ll_s1; // "__built
	break;		in_HEXAGON_M2_mpy_nac_sat_ll_s1"
	switch (BuiltinName[27]) {		}
	default: break;		break;
	case 'p': // 1 string to match.		}
	if (memcmp(BuiltinName.data()+28, "_or", 3))		break;
	break;		}
	return Intrinsic::hexagon_S2_lsr_i_p_or; // "__built		break;
	in_HEXAGON_S2_lsr_i_p_or"		case 's': // 8 strings to match.
	case 'r': // 1 string to match.		if (memcmp(BuiltinName.data()+26, "at_rnd_", 7))
	if (memcmp(BuiltinName.data()+28, "_or", 3))		break;
	break;		switch (BuiltinName[33]) {
	return Intrinsic::hexagon_S2_lsr_i_r_or; // "__built		default: break;
	in_HEXAGON_S2_lsr_i_r_or"		case 'h': // 4 strings to match.
	}		switch (BuiltinName[34]) {
	break;		default: break;
	case 'r': // 2 strings to match.		case 'h': // 2 strings to match.
	if (BuiltinName[26] != '_')		if (memcmp(BuiltinName.data()+35, "_s", 2))
	break;
	switch (BuiltinName[27]) {
	default: break;
	case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "_or", 3))
	break;
	return Intrinsic::hexagon_S2_lsr_r_p_or; // "__built
	in_HEXAGON_S2_lsr_r_p_or"
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "_or", 3))
	break;
	return Intrinsic::hexagon_S2_lsr_r_r_or; // "__built
	in_HEXAGON_S2_lsr_r_r_or"
	}
	break;
	}
	break;		break;
			switch (BuiltinName[37]) {
			default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s0; // "__built
			in_HEXAGON_M2_mpy_sat_rnd_hh_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s1; // "__built
			in_HEXAGON_M2_mpy_sat_rnd_hh_s1"
	}		}
	break;		break;
	case 'v': // 1 string to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "rndpackwh", 9))		if (memcmp(BuiltinName.data()+35, "_s", 2))
	break;		break;
	return Intrinsic::hexagon_S2_vrndpackwh; // "__builtin_HEXAG		switch (BuiltinName[37]) {
	ON_S2_vrndpackwh"		default: break;
			case '0': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s0; // "__built
			in_HEXAGON_M2_mpy_sat_rnd_hl_s0"
			case '1': // 1 string to match.
			return Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s1; // "__built
			in_HEXAGON_M2_mpy_sat_rnd_hl_s1"
			}
			break;
	}		}
	break;		break;
	case '4': // 5 strings to match.		case 'l': // 4 strings to match.
	if (BuiltinName[20] != '_')		switch (BuiltinName[34]) {
	break;
	switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "xtract_rp", 9))		if (memcmp(BuiltinName.data()+35, "_s", 2))
	break;
	return Intrinsic::hexagon_S4_extract_rp; // "__builtin_HEXAG
	ON_S4_extract_rp"
	case 'o': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "ri_", 3))
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[37]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case '0': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "sl_ri", 5))		return Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s0; // "__built
	break;		in_HEXAGON_M2_mpy_sat_rnd_lh_s0"
	return Intrinsic::hexagon_S4_ori_asl_ri; // "__builtin_HEXAG		case '1': // 1 string to match.
	ON_S4_ori_asl_ri"		return Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s1; // "__built
	case 'l': // 1 string to match.		in_HEXAGON_M2_mpy_sat_rnd_lh_s1"
	if (memcmp(BuiltinName.data()+26, "sr_ri", 5))
	break;
	return Intrinsic::hexagon_S4_ori_lsr_ri; // "__builtin_HEXAG
	ON_S4_ori_lsr_ri"
	}		}
	break;		break;
	case 'v': // 2 strings to match.		case 'l': // 2 strings to match.
	if (BuiltinName[22] != 'x')		if (memcmp(BuiltinName.data()+35, "_s", 2))
	break;		break;
	switch (BuiltinName[23]) {		switch (BuiltinName[37]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case '0': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "ddsubhr", 7))		return Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s0; // "__built
	break;		in_HEXAGON_M2_mpy_sat_rnd_ll_s0"
	return Intrinsic::hexagon_S4_vxaddsubhr; // "__builtin_HEXAG		case '1': // 1 string to match.
	ON_S4_vxaddsubhr"		return Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s1; // "__built
	case 's': // 1 string to match.		in_HEXAGON_M2_mpy_sat_rnd_ll_s1"
	if (memcmp(BuiltinName.data()+24, "ubaddhr", 7))
	break;
	return Intrinsic::hexagon_S4_vxsubaddhr; // "__builtin_HEXAG
	ON_S4_vxsubaddhr"
	}		}
	break;		break;
	}		}
	break;		break;
	case '5': // 1 string to match.		}
	if (memcmp(BuiltinName.data()+20, "_asrhub_sat", 11))		break;
			}
			break;
			case 40: // 1 string to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_S5_vasrhrnd_goodsyn
			tax", 40))
			break;
			return Intrinsic::hexagon_S5_vasrhrnd_goodsyntax; // "__builtin_HEXAG
			ON_S5_vasrhrnd_goodsyntax"
			case 41: // 4 strings to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_S2_tableidx", 29))
			break;
			switch (BuiltinName[29]) {
			default: break;
			case 'b': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "_goodsyntax", 11))
			break;
			return Intrinsic::hexagon_S2_tableidxb_goodsyntax; // "__built
			in_HEXAGON_S2_tableidxb_goodsyntax"
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "_goodsyntax", 11))
			break;
			return Intrinsic::hexagon_S2_tableidxd_goodsyntax; // "__built
			in_HEXAGON_S2_tableidxd_goodsyntax"
			case 'h': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "_goodsyntax", 11))
			break;
			return Intrinsic::hexagon_S2_tableidxh_goodsyntax; // "__built
			in_HEXAGON_S2_tableidxh_goodsyntax"
			case 'w': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "_goodsyntax", 11))
			break;
			return Intrinsic::hexagon_S2_tableidxw_goodsyntax; // "__built
			in_HEXAGON_S2_tableidxw_goodsyntax"
			}
			break;
			case 43: // 2 strings to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_S2_asr_i_", 27))
			break;
			switch (BuiltinName[27]) {
			default: break;
			case 'p': // 1 string to match.
			if (memcmp(BuiltinName.data()+28, "_rnd_goodsyntax", 15))
			break;
			return Intrinsic::hexagon_S2_asr_i_p_rnd_goodsyntax; // "__built
			in_HEXAGON_S2_asr_i_p_rnd_goodsyntax"
			case 'r': // 1 string to match.
			if (memcmp(BuiltinName.data()+28, "_rnd_goodsyntax", 15))
			break;
			return Intrinsic::hexagon_S2_asr_i_r_rnd_goodsyntax; // "__built
			in_HEXAGON_S2_asr_i_r_rnd_goodsyntax"
			}
			break;
			case 46: // 1 string to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_S5_asrhub_rnd_sat_g
			oodsyntax", 46))
			break;
			return Intrinsic::hexagon_S5_asrhub_rnd_sat_goodsyntax; // "__built
			in_HEXAGON_S5_asrhub_rnd_sat_goodsyntax"
			}
			}
			if (TargetPrefix == "mips") {
			switch (BuiltinName.size()) {
			default: break;
			case 18: // 17 strings to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_m", 11))
			break;
			switch (BuiltinName[11]) {
			default: break;
			case 'i': // 3 strings to match.
			if (memcmp(BuiltinName.data()+12, "ps_l", 4))
			break;
			switch (BuiltinName[16]) {
			default: break;
			case 'h': // 1 string to match.
			if (BuiltinName[17] != 'x')
	break;		break;
	return Intrinsic::hexagon_S5_asrhub_sat; // "__builtin_HEXAG		return Intrinsic::mips_lhx; // "__builtin_mips_lhx"
	ON_S5_asrhub_sat"		case 's': // 1 string to match.
			if (BuiltinName[17] != 'a')
			break;
			return Intrinsic::mips_lsa; // "__builtin_mips_lsa"
			case 'w': // 1 string to match.
			if (BuiltinName[17] != 'x')
			break;
			return Intrinsic::mips_lwx; // "__builtin_mips_lwx"
			}
			break;
			case 's': // 14 strings to match.
			if (memcmp(BuiltinName.data()+12, "a_", 2))
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'b': // 5 strings to match.
			if (memcmp(BuiltinName.data()+15, "z_", 2))
			break;
			switch (BuiltinName[17]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_bz_b; // "__builtin_msa_bz_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_bz_d; // "__builtin_msa_bz_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_bz_h; // "__builtin_msa_bz_h"
			case 'v': // 1 string to match.
			return Intrinsic::mips_bz_v; // "__builtin_msa_bz_v"
			case 'w': // 1 string to match.
			return Intrinsic::mips_bz_w; // "__builtin_msa_bz_w"
			}
			break;
			case 'l': // 4 strings to match.
			if (memcmp(BuiltinName.data()+15, "d_", 2))
			break;
			switch (BuiltinName[17]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_ld_b; // "__builtin_msa_ld_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_ld_d; // "__builtin_msa_ld_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_ld_h; // "__builtin_msa_ld_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ld_w; // "__builtin_msa_ld_w"
			}
			break;
			case 'o': // 1 string to match.
			if (memcmp(BuiltinName.data()+15, "r_v", 3))
			break;
			return Intrinsic::mips_or_v; // "__builtin_msa_or_v"
			case 's': // 4 strings to match.
			if (memcmp(BuiltinName.data()+15, "t_", 2))
			break;
			switch (BuiltinName[17]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_st_b; // "__builtin_msa_st_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_st_d; // "__builtin_msa_st_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_st_h; // "__builtin_msa_st_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_st_w; // "__builtin_msa_st_w"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 32: // 96 strings to match.		case 19: // 45 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))		if (memcmp(BuiltinName.data()+0, "__builtin_m", 11))
	break;		break;
	switch (BuiltinName[18]) {		switch (BuiltinName[11]) {
	default: break;		default: break;
	case 'A': // 16 strings to match.		case 'i': // 6 strings to match.
	switch (BuiltinName[19]) {		if (memcmp(BuiltinName.data()+12, "ps_", 3))
			break;
			switch (BuiltinName[15]) {
	default: break;		default: break;
	case '2': // 14 strings to match.		case 'e': // 1 string to match.
	if (BuiltinName[20] != '_')		if (memcmp(BuiltinName.data()+16, "xtp", 3))
	break;		break;
	switch (BuiltinName[21]) {		return Intrinsic::mips_extp; // "__builtin_mips_extp"
			case 'i': // 1 string to match.
			if (memcmp(BuiltinName.data()+16, "nsv", 3))
			break;
			return Intrinsic::mips_insv; // "__builtin_mips_insv"
			case 'l': // 1 string to match.
			if (memcmp(BuiltinName.data()+16, "bux", 3))
			break;
			return Intrinsic::mips_lbux; // "__builtin_mips_lbux"
			case 'm': // 3 strings to match.
			switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'a': // 6 strings to match.		case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "ddh_", 4))		if (memcmp(BuiltinName.data()+17, "dd", 2))
	break;		break;
	switch (BuiltinName[26]) {		return Intrinsic::mips_madd; // "__builtin_mips_madd"
	default: break;		case 's': // 1 string to match.
	case 'h': // 4 strings to match.		if (memcmp(BuiltinName.data()+17, "ub", 2))
	if (memcmp(BuiltinName.data()+27, "16_", 3))
	break;
	switch (BuiltinName[30]) {
	default: break;
	case 'h': // 2 strings to match.
	switch (BuiltinName[31]) {
	default: break;
	case 'h': // 1 string to match.
	return Intrinsic::hexagon_A2_addh_h16_hh; // "__built
	in_HEXAGON_A2_addh_h16_hh"
	case 'l': // 1 string to match.
	return Intrinsic::hexagon_A2_addh_h16_hl; // "__built
	in_HEXAGON_A2_addh_h16_hl"
	}
	break;
	case 'l': // 2 strings to match.
	switch (BuiltinName[31]) {
	default: break;
	case 'h': // 1 string to match.
	return Intrinsic::hexagon_A2_addh_h16_lh; // "__built
	in_HEXAGON_A2_addh_h16_lh"
	case 'l': // 1 string to match.
	return Intrinsic::hexagon_A2_addh_h16_ll; // "__built
	in_HEXAGON_A2_addh_h16_ll"
	}
	break;
	}
	break;		break;
	case 'l': // 2 strings to match.		return Intrinsic::mips_msub; // "__builtin_mips_msub"
	if (memcmp(BuiltinName.data()+27, "16_", 3))		case 'u': // 1 string to match.
	break;		if (memcmp(BuiltinName.data()+17, "lt", 2))
	switch (BuiltinName[30]) {		break;
	default: break;		return Intrinsic::mips_mult; // "__builtin_mips_mult"
	case 'h': // 1 string to match.		}
	if (BuiltinName[31] != 'l')		break;
	break;		}
	return Intrinsic::hexagon_A2_addh_l16_hl; // "__built		break;
	in_HEXAGON_A2_addh_l16_hl"		case 's': // 39 strings to match.
	case 'l': // 1 string to match.		if (memcmp(BuiltinName.data()+12, "a_", 2))
	if (BuiltinName[31] != 'l')		break;
	break;		switch (BuiltinName[14]) {
	return Intrinsic::hexagon_A2_addh_l16_ll; // "__built		default: break;
	in_HEXAGON_A2_addh_l16_ll"		case 'a': // 1 string to match.
	}		if (memcmp(BuiltinName.data()+15, "nd_v", 4))
			break;
			return Intrinsic::mips_and_v; // "__builtin_msa_and_v"
			case 'b': // 6 strings to match.
			switch (BuiltinName[15]) {
			default: break;
			case 'm': // 1 string to match.
			if (memcmp(BuiltinName.data()+16, "z_v", 3))
	break;		break;
			return Intrinsic::mips_bmz_v; // "__builtin_msa_bmz_v"
			case 'n': // 5 strings to match.
			if (memcmp(BuiltinName.data()+16, "z_", 2))
			break;
			switch (BuiltinName[18]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_bnz_b; // "__builtin_msa_bnz_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_bnz_d; // "__builtin_msa_bnz_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_bnz_h; // "__builtin_msa_bnz_h"
			case 'v': // 1 string to match.
			return Intrinsic::mips_bnz_v; // "__builtin_msa_bnz_v"
			case 'w': // 1 string to match.
			return Intrinsic::mips_bnz_w; // "__builtin_msa_bnz_w"
	}		}
	break;		break;
	case 's': // 6 strings to match.		}
	if (memcmp(BuiltinName.data()+22, "ubh_", 4))		break;
			case 'c': // 4 strings to match.
			if (memcmp(BuiltinName.data()+15, "eq_", 3))
			break;
			switch (BuiltinName[18]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_ceq_b; // "__builtin_msa_ceq_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_ceq_d; // "__builtin_msa_ceq_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_ceq_h; // "__builtin_msa_ceq_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ceq_w; // "__builtin_msa_ceq_w"
			}
			break;
			case 'f': // 2 strings to match.
			if (memcmp(BuiltinName.data()+15, "tq_", 3))
			break;
			switch (BuiltinName[18]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::mips_ftq_h; // "__builtin_msa_ftq_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ftq_w; // "__builtin_msa_ftq_w"
			}
			break;
			case 'l': // 4 strings to match.
			if (memcmp(BuiltinName.data()+15, "di_", 3))
			break;
			switch (BuiltinName[18]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_ldi_b; // "__builtin_msa_ldi_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_ldi_d; // "__builtin_msa_ldi_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_ldi_h; // "__builtin_msa_ldi_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ldi_w; // "__builtin_msa_ldi_w"
			}
			break;
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+15, "or_v", 4))
			break;
			return Intrinsic::mips_nor_v; // "__builtin_msa_nor_v"
			case 'o': // 1 string to match.
			if (memcmp(BuiltinName.data()+15, "ri_b", 4))
			break;
			return Intrinsic::mips_ori_b; // "__builtin_msa_ori_b"
			case 's': // 19 strings to match.
			switch (BuiltinName[15]) {
			default: break;
			case 'h': // 3 strings to match.
			if (memcmp(BuiltinName.data()+16, "f_", 2))
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[18]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_shf_b; // "__builtin_msa_shf_b"
			case 'h': // 1 string to match.
			return Intrinsic::mips_shf_h; // "__builtin_msa_shf_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_shf_w; // "__builtin_msa_shf_w"
			}
			break;
			case 'l': // 8 strings to match.
			switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'h': // 4 strings to match.		case 'd': // 4 strings to match.
	if (memcmp(BuiltinName.data()+27, "16_", 3))		if (BuiltinName[17] != '_')
	break;		break;
	switch (BuiltinName[30]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'b': // 1 string to match.
	switch (BuiltinName[31]) {		return Intrinsic::mips_sld_b; // "__builtin_msa_sld_b"
	default: break;		case 'd': // 1 string to match.
	case 'h': // 1 string to match.		return Intrinsic::mips_sld_d; // "__builtin_msa_sld_d"
	return Intrinsic::hexagon_A2_subh_h16_hh; // "__built		case 'h': // 1 string to match.
	in_HEXAGON_A2_subh_h16_hh"		return Intrinsic::mips_sld_h; // "__builtin_msa_sld_h"
	case 'l': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::hexagon_A2_subh_h16_hl; // "__built		return Intrinsic::mips_sld_w; // "__builtin_msa_sld_w"
	in_HEXAGON_A2_subh_h16_hl"
	}
	break;
	case 'l': // 2 strings to match.
	switch (BuiltinName[31]) {
	default: break;
	case 'h': // 1 string to match.
	return Intrinsic::hexagon_A2_subh_h16_lh; // "__built
	in_HEXAGON_A2_subh_h16_lh"
	case 'l': // 1 string to match.
	return Intrinsic::hexagon_A2_subh_h16_ll; // "__built
	in_HEXAGON_A2_subh_h16_ll"
	}
	break;
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'l': // 4 strings to match.
	if (memcmp(BuiltinName.data()+27, "16_", 3))		if (BuiltinName[17] != '_')
	break;		break;
	switch (BuiltinName[30]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_sll_b; // "__builtin_msa_sll_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_sll_d; // "__builtin_msa_sll_d"
	case 'h': // 1 string to match.		case 'h': // 1 string to match.
	if (BuiltinName[31] != 'l')		return Intrinsic::mips_sll_h; // "__builtin_msa_sll_h"
	break;		case 'w': // 1 string to match.
	return Intrinsic::hexagon_A2_subh_l16_hl; // "__built		return Intrinsic::mips_sll_w; // "__builtin_msa_sll_w"
	in_HEXAGON_A2_subh_l16_hl"
	case 'l': // 1 string to match.
	if (BuiltinName[31] != 'l')
	break;
	return Intrinsic::hexagon_A2_subh_l16_ll; // "__built
	in_HEXAGON_A2_subh_l16_ll"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'v': // 2 strings to match.		case 'r': // 8 strings to match.
	if (BuiltinName[22] != 'r')		switch (BuiltinName[16]) {
	break;
	switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'a': // 4 strings to match.
	if (memcmp(BuiltinName.data()+24, "ddub_acc", 8))		if (BuiltinName[17] != '_')
	break;		break;
	return Intrinsic::hexagon_A2_vraddub_acc; // "__builtin_HEXAG		switch (BuiltinName[18]) {
	ON_A2_vraddub_acc"		default: break;
	case 's': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "adub_acc", 8))		return Intrinsic::mips_sra_b; // "__builtin_msa_sra_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_sra_d; // "__builtin_msa_sra_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_sra_h; // "__builtin_msa_sra_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_sra_w; // "__builtin_msa_sra_w"
			}
			break;
			case 'l': // 4 strings to match.
			if (BuiltinName[17] != '_')
	break;		break;
	return Intrinsic::hexagon_A2_vrsadub_acc; // "__builtin_HEXAG		switch (BuiltinName[18]) {
	ON_A2_vrsadub_acc"		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_srl_b; // "__builtin_msa_srl_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_srl_d; // "__builtin_msa_srl_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_srl_h; // "__builtin_msa_srl_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_srl_w; // "__builtin_msa_srl_w"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case '4': // 2 strings to match.		case 'x': // 1 string to match.
	if (BuiltinName[20] != '_')		if (memcmp(BuiltinName.data()+15, "or_v", 4))
	break;		break;
	switch (BuiltinName[21]) {		return Intrinsic::mips_xor_v; // "__builtin_msa_xor_v"
			}
			break;
			}
			break;
			case 20: // 143 strings to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_m", 11))
			break;
			switch (BuiltinName[11]) {
			default: break;
			case 'i': // 8 strings to match.
			if (memcmp(BuiltinName.data()+12, "ps_", 3))
			break;
			switch (BuiltinName[15]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(BuiltinName.data()+16, "dd", 2))
			break;
			switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "oundscheck", 10))		if (BuiltinName[19] != 'c')
	break;		break;
	return Intrinsic::hexagon_A4_boundscheck; // "__builtin_HEXAG		return Intrinsic::mips_addsc; // "__builtin_mips_addsc"
	ON_A4_boundscheck"		case 'w': // 1 string to match.
	case 'v': // 1 string to match.		if (BuiltinName[19] != 'c')
	if (memcmp(BuiltinName.data()+22, "cmpbeq_any", 10))
	break;		break;
	return Intrinsic::hexagon_A4_vcmpbeq_any; // "__builtin_HEXAG		return Intrinsic::mips_addwc; // "__builtin_mips_addwc"
	ON_A4_vcmpbeq_any"		}
			break;
			case 'm': // 3 strings to match.
			switch (BuiltinName[16]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(BuiltinName.data()+17, "ddu", 3))
			break;
			return Intrinsic::mips_maddu; // "__builtin_mips_maddu"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+17, "ubu", 3))
			break;
			return Intrinsic::mips_msubu; // "__builtin_mips_msubu"
			case 'u': // 1 string to match.
			if (memcmp(BuiltinName.data()+17, "ltu", 3))
			break;
			return Intrinsic::mips_multu; // "__builtin_mips_multu"
	}		}
	break;		break;
			case 'r': // 1 string to match.
			if (memcmp(BuiltinName.data()+16, "ddsp", 4))
			break;
			return Intrinsic::mips_rddsp; // "__builtin_mips_rddsp"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+16, "hilo", 4))
			break;
			return Intrinsic::mips_shilo; // "__builtin_mips_shilo"
			case 'w': // 1 string to match.
			if (memcmp(BuiltinName.data()+16, "rdsp", 4))
			break;
			return Intrinsic::mips_wrdsp; // "__builtin_mips_wrdsp"
	}		}
	break;		break;
	case 'C': // 1 string to match.		case 's': // 135 strings to match.
	if (memcmp(BuiltinName.data()+19, "4_fastcorner9", 13))		if (memcmp(BuiltinName.data()+12, "a_", 2))
	break;		break;
	return Intrinsic::hexagon_C4_fastcorner9; // "__builtin_HEXAG		switch (BuiltinName[14]) {
	ON_C4_fastcorner9"
	case 'M': // 16 strings to match.
	if (memcmp(BuiltinName.data()+19, "2_", 2))
	break;
	switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'm': // 12 strings to match.		case 'a': // 5 strings to match.
	switch (BuiltinName[22]) {		switch (BuiltinName[15]) {
	default: break;		default: break;
	case 'm': // 4 strings to match.		case 'd': // 4 strings to match.
	if (memcmp(BuiltinName.data()+23, "acu", 3))		if (memcmp(BuiltinName.data()+16, "dv_", 3))
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "s_rs", 4))		return Intrinsic::mips_addv_b; // "__builtin_msa_addv_b"
	break;		case 'd': // 1 string to match.
	switch (BuiltinName[31]) {		return Intrinsic::mips_addv_d; // "__builtin_msa_addv_d"
	default: break;		case 'h': // 1 string to match.
	case '0': // 1 string to match.		return Intrinsic::mips_addv_h; // "__builtin_msa_addv_h"
	return Intrinsic::hexagon_M2_mmacuhs_rs0; // "__built		case 'w': // 1 string to match.
	in_HEXAGON_M2_mmacuhs_rs0"		return Intrinsic::mips_addv_w; // "__builtin_msa_addv_w"
	case '1': // 1 string to match.		}
	return Intrinsic::hexagon_M2_mmacuhs_rs1; // "__built		break;
	in_HEXAGON_M2_mmacuhs_rs1"		case 'n': // 1 string to match.
	}		if (memcmp(BuiltinName.data()+16, "di_b", 4))
	break;		break;
	case 'l': // 2 strings to match.		return Intrinsic::mips_andi_b; // "__builtin_msa_andi_b"
	if (memcmp(BuiltinName.data()+27, "s_rs", 4))		}
	break;		break;
	switch (BuiltinName[31]) {		case 'b': // 15 strings to match.
	default: break;		switch (BuiltinName[15]) {
	case '0': // 1 string to match.		default: break;
	return Intrinsic::hexagon_M2_mmaculs_rs0; // "__built		case 'c': // 4 strings to match.
	in_HEXAGON_M2_mmaculs_rs0"		if (memcmp(BuiltinName.data()+16, "lr_", 3))
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mmaculs_rs1; // "__built
	in_HEXAGON_M2_mmaculs_rs1"
	}
	break;		break;
			switch (BuiltinName[19]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_bclr_b; // "__builtin_msa_bclr_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_bclr_d; // "__builtin_msa_bclr_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_bclr_h; // "__builtin_msa_bclr_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_bclr_w; // "__builtin_msa_bclr_w"
	}		}
	break;		break;
	case 'p': // 8 strings to match.		case 'm': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "yud_", 4))		switch (BuiltinName[16]) {
	break;
	switch (BuiltinName[27]) {
	default: break;		default: break;
	case 'h': // 4 strings to match.		case 'n': // 1 string to match.
	switch (BuiltinName[28]) {		if (memcmp(BuiltinName.data()+17, "z_v", 3))
	default: break;
	case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+29, "_s", 2))
	break;
	switch (BuiltinName[31]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyud_hh_s0; // "__built
	in_HEXAGON_M2_mpyud_hh_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyud_hh_s1; // "__built
	in_HEXAGON_M2_mpyud_hh_s1"
	}
	break;		break;
	case 'l': // 2 strings to match.		return Intrinsic::mips_bmnz_v; // "__builtin_msa_bmnz_v"
	if (memcmp(BuiltinName.data()+29, "_s", 2))		case 'z': // 1 string to match.
	break;		if (memcmp(BuiltinName.data()+17, "i_b", 3))
	switch (BuiltinName[31]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyud_hl_s0; // "__built
	in_HEXAGON_M2_mpyud_hl_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyud_hl_s1; // "__built
	in_HEXAGON_M2_mpyud_hl_s1"
	}
	break;		break;
	}		return Intrinsic::mips_bmzi_b; // "__builtin_msa_bmzi_b"
			}
			break;
			case 'n': // 4 strings to match.
			if (memcmp(BuiltinName.data()+16, "eg_", 3))
	break;		break;
	case 'l': // 4 strings to match.		switch (BuiltinName[19]) {
	switch (BuiltinName[28]) {		default: break;
	default: break;		case 'b': // 1 string to match.
	case 'h': // 2 strings to match.		return Intrinsic::mips_bneg_b; // "__builtin_msa_bneg_b"
	if (memcmp(BuiltinName.data()+29, "_s", 2))		case 'd': // 1 string to match.
	break;		return Intrinsic::mips_bneg_d; // "__builtin_msa_bneg_d"
	switch (BuiltinName[31]) {		case 'h': // 1 string to match.
	default: break;		return Intrinsic::mips_bneg_h; // "__builtin_msa_bneg_h"
	case '0': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyud_lh_s0; // "__built		return Intrinsic::mips_bneg_w; // "__builtin_msa_bneg_w"
	in_HEXAGON_M2_mpyud_lh_s0"		}
	case '1': // 1 string to match.		break;
	return Intrinsic::hexagon_M2_mpyud_lh_s1; // "__built		case 's': // 5 strings to match.
	in_HEXAGON_M2_mpyud_lh_s1"		if (BuiltinName[16] != 'e')
	}		break;
			switch (BuiltinName[17]) {
			default: break;
			case 'l': // 1 string to match.
			if (memcmp(BuiltinName.data()+18, "_v", 2))
	break;		break;
	case 'l': // 2 strings to match.		return Intrinsic::mips_bsel_v; // "__builtin_msa_bsel_v"
	if (memcmp(BuiltinName.data()+29, "_s", 2))		case 't': // 4 strings to match.
	break;		if (BuiltinName[18] != '_')
	switch (BuiltinName[31]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyud_ll_s0; // "__built
	in_HEXAGON_M2_mpyud_ll_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyud_ll_s1; // "__built
	in_HEXAGON_M2_mpyud_ll_s1"
	}
	break;		break;
			switch (BuiltinName[19]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_bset_b; // "__builtin_msa_bset_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_bset_d; // "__builtin_msa_bset_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_bset_h; // "__builtin_msa_bset_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_bset_w; // "__builtin_msa_bset_w"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'v': // 4 strings to match.		case 'c': // 6 strings to match.
	if (memcmp(BuiltinName.data()+22, "rcm", 3))		switch (BuiltinName[15]) {
	break;
	switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'e': // 4 strings to match.
	if (BuiltinName[26] != 'c')		if (memcmp(BuiltinName.data()+16, "qi_", 3))
	break;		break;
	switch (BuiltinName[27]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'i': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "_s0c", 4))		return Intrinsic::mips_ceqi_b; // "__builtin_msa_ceqi_b"
	break;		case 'd': // 1 string to match.
	return Intrinsic::hexagon_M2_vrcmaci_s0c; // "__builtin_HEXAG		return Intrinsic::mips_ceqi_d; // "__builtin_msa_ceqi_d"
	ON_M2_vrcmaci_s0c"		case 'h': // 1 string to match.
	case 'r': // 1 string to match.		return Intrinsic::mips_ceqi_h; // "__builtin_msa_ceqi_h"
	if (memcmp(BuiltinName.data()+28, "_s0c", 4))		case 'w': // 1 string to match.
	break;		return Intrinsic::mips_ceqi_w; // "__builtin_msa_ceqi_w"
	return Intrinsic::hexagon_M2_vrcmacr_s0c; // "__builtin_HEXAG
	ON_M2_vrcmacr_s0c"
	}		}
	break;		break;
	case 'p': // 2 strings to match.		case 'f': // 1 string to match.
	if (BuiltinName[26] != 'y')		if (memcmp(BuiltinName.data()+16, "cmsa", 4))
	break;		break;
	switch (BuiltinName[27]) {		return Intrinsic::mips_cfcmsa; // "__builtin_msa_cfcmsa"
	default: break;		case 't': // 1 string to match.
	case 'i': // 1 string to match.		if (memcmp(BuiltinName.data()+16, "cmsa", 4))
	if (memcmp(BuiltinName.data()+28, "_s0c", 4))		break;
	break;		return Intrinsic::mips_ctcmsa; // "__builtin_msa_ctcmsa"
	return Intrinsic::hexagon_M2_vrcmpyi_s0c; // "__builtin_HEXAG
	ON_M2_vrcmpyi_s0c"
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "_s0c", 4))
	break;
	return Intrinsic::hexagon_M2_vrcmpyr_s0c; // "__builtin_HEXAG
	ON_M2_vrcmpyr_s0c"
	}
	break;
	}		}
	break;		break;
	}		case 'f': // 50 strings to match.
	break;		switch (BuiltinName[15]) {
	case 'S': // 63 strings to match.
	switch (BuiltinName[19]) {
	default: break;
	case '2': // 56 strings to match.
	if (BuiltinName[20] != '_')
	break;
	switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'a': // 32 strings to match.		case 'a': // 2 strings to match.
	switch (BuiltinName[22]) {		if (memcmp(BuiltinName.data()+16, "dd_", 3))
			break;
			switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "dasl_rrri", 9))		return Intrinsic::mips_fadd_d; // "__builtin_msa_fadd_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fadd_w; // "__builtin_msa_fadd_w"
			}
			break;
			case 'c': // 14 strings to match.
			switch (BuiltinName[16]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(BuiltinName.data()+17, "f_", 2))
	break;		break;
	return Intrinsic::hexagon_S2_addasl_rrri; // "__builtin_HEXAG		switch (BuiltinName[19]) {
	ON_S2_addasl_rrri"
	case 's': // 31 strings to match.
	switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'l': // 15 strings to match.		case 'd': // 1 string to match.
	if (BuiltinName[24] != '_')		return Intrinsic::mips_fcaf_d; // "__builtin_msa_fcaf_d"
	break;		case 'w': // 1 string to match.
	switch (BuiltinName[25]) {		return Intrinsic::mips_fcaf_w; // "__builtin_msa_fcaf_w"
	default: break;		}
	case 'i': // 7 strings to match.		break;
	if (BuiltinName[26] != '_')		case 'e': // 2 strings to match.
	break;		if (memcmp(BuiltinName.data()+17, "q_", 2))
	switch (BuiltinName[27]) {
	default: break;
	case 'p': // 3 strings to match.
	if (BuiltinName[28] != '_')
	break;
	switch (BuiltinName[29]) {
	default: break;
	case 'a': // 2 strings to match.
	switch (BuiltinName[30]) {
	default: break;
	case 'c': // 1 string to match.
	if (BuiltinName[31] != 'c')
	break;
	return Intrinsic::hexagon_S2_asl_i_p_acc; //
	"__builtin_HEXAGON_S2_asl_i_p_acc"
	case 'n': // 1 string to match.
	if (BuiltinName[31] != 'd')
	break;
	return Intrinsic::hexagon_S2_asl_i_p_and; //
	"__builtin_HEXAGON_S2_asl_i_p_and"
	}
	break;
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "ac", 2))
	break;
	return Intrinsic::hexagon_S2_asl_i_p_nac; // "__built
	in_HEXAGON_S2_asl_i_p_nac"
	}
	break;
	case 'r': // 4 strings to match.
	if (BuiltinName[28] != '_')
	break;
	switch (BuiltinName[29]) {
	default: break;
	case 'a': // 2 strings to match.
	switch (BuiltinName[30]) {
	default: break;
	case 'c': // 1 string to match.
	if (BuiltinName[31] != 'c')
	break;
	return Intrinsic::hexagon_S2_asl_i_r_acc; //
	"__builtin_HEXAGON_S2_asl_i_r_acc"
	case 'n': // 1 string to match.
	if (BuiltinName[31] != 'd')
	break;
	return Intrinsic::hexagon_S2_asl_i_r_and; //
	"__builtin_HEXAGON_S2_asl_i_r_and"
	}
	break;
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "ac", 2))
	break;
	return Intrinsic::hexagon_S2_asl_i_r_nac; // "__built
	in_HEXAGON_S2_asl_i_r_nac"
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "at", 2))
	break;
	return Intrinsic::hexagon_S2_asl_i_r_sat; // "__built
	in_HEXAGON_S2_asl_i_r_sat"
	}
	break;
	}
	break;
	case 'r': // 8 strings to match.
	if (BuiltinName[26] != '_')
	break;
	switch (BuiltinName[27]) {
	default: break;
	case 'p': // 4 strings to match.
	if (BuiltinName[28] != '_')
	break;
	switch (BuiltinName[29]) {
	default: break;
	case 'a': // 2 strings to match.
	switch (BuiltinName[30]) {
	default: break;
	case 'c': // 1 string to match.
	if (BuiltinName[31] != 'c')
	break;
	return Intrinsic::hexagon_S2_asl_r_p_acc; //
	"__builtin_HEXAGON_S2_asl_r_p_acc"
	case 'n': // 1 string to match.
	if (BuiltinName[31] != 'd')
	break;
	return Intrinsic::hexagon_S2_asl_r_p_and; //
	"__builtin_HEXAGON_S2_asl_r_p_and"
	}
	break;
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "ac", 2))
	break;
	return Intrinsic::hexagon_S2_asl_r_p_nac; // "__built
	in_HEXAGON_S2_asl_r_p_nac"
	case 'x': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "or", 2))
	break;
	return Intrinsic::hexagon_S2_asl_r_p_xor; // "__built
	in_HEXAGON_S2_asl_r_p_xor"
	}
	break;
	case 'r': // 4 strings to match.
	if (BuiltinName[28] != '_')
	break;
	switch (BuiltinName[29]) {
	default: break;
	case 'a': // 2 strings to match.
	switch (BuiltinName[30]) {
	default: break;
	case 'c': // 1 string to match.
	if (BuiltinName[31] != 'c')
	break;
	return Intrinsic::hexagon_S2_asl_r_r_acc; //
	"__builtin_HEXAGON_S2_asl_r_r_acc"
	case 'n': // 1 string to match.
	if (BuiltinName[31] != 'd')
	break;
	return Intrinsic::hexagon_S2_asl_r_r_and; //
	"__builtin_HEXAGON_S2_asl_r_r_and"
	}
	break;
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "ac", 2))
	break;
	return Intrinsic::hexagon_S2_asl_r_r_nac; // "__built
	in_HEXAGON_S2_asl_r_r_nac"
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "at", 2))
	break;
	return Intrinsic::hexagon_S2_asl_r_r_sat; // "__built
	in_HEXAGON_S2_asl_r_r_sat"
	}
	break;
	}
	break;
	}
	break;		break;
	case 'r': // 16 strings to match.		switch (BuiltinName[19]) {
	if (BuiltinName[24] != '_')		default: break;
	break;		case 'd': // 1 string to match.
	switch (BuiltinName[25]) {		return Intrinsic::mips_fceq_d; // "__builtin_msa_fceq_d"
	default: break;		case 'w': // 1 string to match.
	case 'i': // 8 strings to match.		return Intrinsic::mips_fceq_w; // "__builtin_msa_fceq_w"
	if (BuiltinName[26] != '_')		}
	break;		break;
	switch (BuiltinName[27]) {		case 'l': // 4 strings to match.
	default: break;		switch (BuiltinName[17]) {
	case 'p': // 4 strings to match.		default: break;
	if (BuiltinName[28] != '_')		case 'e': // 2 strings to match.
	break;		if (BuiltinName[18] != '_')
	switch (BuiltinName[29]) {
	default: break;
	case 'a': // 2 strings to match.
	switch (BuiltinName[30]) {
	default: break;
	case 'c': // 1 string to match.
	if (BuiltinName[31] != 'c')
	break;
	return Intrinsic::hexagon_S2_asr_i_p_acc; //
	"__builtin_HEXAGON_S2_asr_i_p_acc"
	case 'n': // 1 string to match.
	if (BuiltinName[31] != 'd')
	break;
	return Intrinsic::hexagon_S2_asr_i_p_and; //
	"__builtin_HEXAGON_S2_asr_i_p_and"
	}
	break;
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "ac", 2))
	break;
	return Intrinsic::hexagon_S2_asr_i_p_nac; // "__built
	in_HEXAGON_S2_asr_i_p_nac"
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "nd", 2))
	break;
	return Intrinsic::hexagon_S2_asr_i_p_rnd; // "__built
	in_HEXAGON_S2_asr_i_p_rnd"
	}
	break;
	case 'r': // 4 strings to match.
	if (BuiltinName[28] != '_')
	break;
	switch (BuiltinName[29]) {
	default: break;
	case 'a': // 2 strings to match.
	switch (BuiltinName[30]) {
	default: break;
	case 'c': // 1 string to match.
	if (BuiltinName[31] != 'c')
	break;
	return Intrinsic::hexagon_S2_asr_i_r_acc; //
	"__builtin_HEXAGON_S2_asr_i_r_acc"
	case 'n': // 1 string to match.
	if (BuiltinName[31] != 'd')
	break;
	return Intrinsic::hexagon_S2_asr_i_r_and; //
	"__builtin_HEXAGON_S2_asr_i_r_and"
	}
	break;
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "ac", 2))
	break;
	return Intrinsic::hexagon_S2_asr_i_r_nac; // "__built
	in_HEXAGON_S2_asr_i_r_nac"
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "nd", 2))
	break;
	return Intrinsic::hexagon_S2_asr_i_r_rnd; // "__built
	in_HEXAGON_S2_asr_i_r_rnd"
	}
	break;
	}
	break;		break;
	case 'r': // 8 strings to match.		switch (BuiltinName[19]) {
	if (BuiltinName[26] != '_')		default: break;
	break;		case 'd': // 1 string to match.
	switch (BuiltinName[27]) {		return Intrinsic::mips_fcle_d; // "__builtin_msa_fcle_d"
	default: break;		case 'w': // 1 string to match.
	case 'p': // 4 strings to match.		return Intrinsic::mips_fcle_w; // "__builtin_msa_fcle_w"
	if (BuiltinName[28] != '_')		}
	break;		break;
	switch (BuiltinName[29]) {		case 't': // 2 strings to match.
	default: break;		if (BuiltinName[18] != '_')
	case 'a': // 2 strings to match.
	switch (BuiltinName[30]) {
	default: break;
	case 'c': // 1 string to match.
	if (BuiltinName[31] != 'c')
	break;
	return Intrinsic::hexagon_S2_asr_r_p_acc; //
	"__builtin_HEXAGON_S2_asr_r_p_acc"
	case 'n': // 1 string to match.
	if (BuiltinName[31] != 'd')
	break;
	return Intrinsic::hexagon_S2_asr_r_p_and; //
	"__builtin_HEXAGON_S2_asr_r_p_and"
	}
	break;
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "ac", 2))
	break;
	return Intrinsic::hexagon_S2_asr_r_p_nac; // "__built
	in_HEXAGON_S2_asr_r_p_nac"
	case 'x': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "or", 2))
	break;
	return Intrinsic::hexagon_S2_asr_r_p_xor; // "__built
	in_HEXAGON_S2_asr_r_p_xor"
	}
	break;
	case 'r': // 4 strings to match.
	if (BuiltinName[28] != '_')
	break;
	switch (BuiltinName[29]) {
	default: break;
	case 'a': // 2 strings to match.
	switch (BuiltinName[30]) {
	default: break;
	case 'c': // 1 string to match.
	if (BuiltinName[31] != 'c')
	break;
	return Intrinsic::hexagon_S2_asr_r_r_acc; //
	"__builtin_HEXAGON_S2_asr_r_r_acc"
	case 'n': // 1 string to match.
	if (BuiltinName[31] != 'd')
	break;
	return Intrinsic::hexagon_S2_asr_r_r_and; //
	"__builtin_HEXAGON_S2_asr_r_r_and"
	}
	break;
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "ac", 2))
	break;
	return Intrinsic::hexagon_S2_asr_r_r_nac; // "__built
	in_HEXAGON_S2_asr_r_r_nac"
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "at", 2))
	break;
	return Intrinsic::hexagon_S2_asr_r_r_sat; // "__built
	in_HEXAGON_S2_asr_r_r_sat"
	}
	break;
	}
	break;		break;
			switch (BuiltinName[19]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fclt_d; // "__builtin_msa_fclt_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fclt_w; // "__builtin_msa_fclt_w"
	}		}
	break;		break;
	}		}
	break;		break;
			case 'n': // 2 strings to match.
			if (memcmp(BuiltinName.data()+17, "e_", 2))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fcne_d; // "__builtin_msa_fcne_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fcne_w; // "__builtin_msa_fcne_w"
			}
			break;
			case 'o': // 2 strings to match.
			if (memcmp(BuiltinName.data()+17, "r_", 2))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fcor_d; // "__builtin_msa_fcor_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fcor_w; // "__builtin_msa_fcor_w"
			}
			break;
			case 'u': // 2 strings to match.
			if (memcmp(BuiltinName.data()+17, "n_", 2))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fcun_d; // "__builtin_msa_fcun_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fcun_w; // "__builtin_msa_fcun_w"
			}
			break;
	}		}
	break;		break;
	case 'e': // 1 string to match.		case 'd': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "xtractu_rp", 10))		if (memcmp(BuiltinName.data()+16, "iv_", 3))
	break;		break;
	return Intrinsic::hexagon_S2_extractu_rp; // "__builtin_HEXAG		switch (BuiltinName[19]) {
	ON_S2_extractu_rp"		default: break;
	case 'l': // 20 strings to match.		case 'd': // 1 string to match.
	if (BuiltinName[22] != 's')		return Intrinsic::mips_fdiv_d; // "__builtin_msa_fdiv_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fdiv_w; // "__builtin_msa_fdiv_w"
			}
			break;
			case 'f': // 4 strings to match.
			if (BuiltinName[16] != 'q')
	break;		break;
	switch (BuiltinName[23]) {		switch (BuiltinName[17]) {
	default: break;		default: break;
	case 'l': // 7 strings to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+24, "_r_", 3))		if (BuiltinName[18] != '_')
	break;		break;
	switch (BuiltinName[27]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'p': // 4 strings to match.		case 'd': // 1 string to match.
	if (BuiltinName[28] != '_')		return Intrinsic::mips_ffql_d; // "__builtin_msa_ffql_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ffql_w; // "__builtin_msa_ffql_w"
			}
			break;
			case 'r': // 2 strings to match.
			if (BuiltinName[18] != '_')
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_ffqr_d; // "__builtin_msa_ffqr_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ffqr_w; // "__builtin_msa_ffqr_w"
			}
			break;
			}
			break;
			case 'i': // 4 strings to match.
			if (memcmp(BuiltinName.data()+16, "ll_", 3))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_fill_b; // "__builtin_msa_fill_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_fill_d; // "__builtin_msa_fill_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_fill_h; // "__builtin_msa_fill_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fill_w; // "__builtin_msa_fill_w"
			}
			break;
			case 'm': // 6 strings to match.
			switch (BuiltinName[16]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(BuiltinName.data()+17, "x_", 2))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fmax_d; // "__builtin_msa_fmax_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fmax_w; // "__builtin_msa_fmax_w"
			}
			break;
			case 'i': // 2 strings to match.
			if (memcmp(BuiltinName.data()+17, "n_", 2))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fmin_d; // "__builtin_msa_fmin_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fmin_w; // "__builtin_msa_fmin_w"
			}
			break;
			case 'u': // 2 strings to match.
			if (memcmp(BuiltinName.data()+17, "l_", 2))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fmul_d; // "__builtin_msa_fmul_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fmul_w; // "__builtin_msa_fmul_w"
			}
			break;
			}
			break;
			case 'r': // 2 strings to match.
			if (memcmp(BuiltinName.data()+16, "cp_", 3))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_frcp_d; // "__builtin_msa_frcp_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_frcp_w; // "__builtin_msa_frcp_w"
			}
			break;
			case 's': // 16 strings to match.
			switch (BuiltinName[16]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(BuiltinName.data()+17, "f_", 2))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fsaf_d; // "__builtin_msa_fsaf_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fsaf_w; // "__builtin_msa_fsaf_w"
			}
			break;
			case 'e': // 2 strings to match.
			if (memcmp(BuiltinName.data()+17, "q_", 2))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fseq_d; // "__builtin_msa_fseq_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fseq_w; // "__builtin_msa_fseq_w"
			}
			break;
			case 'l': // 4 strings to match.
			switch (BuiltinName[17]) {
			default: break;
			case 'e': // 2 strings to match.
			if (BuiltinName[18] != '_')
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'd': // 1 string to match.
	switch (BuiltinName[30]) {		return Intrinsic::mips_fsle_d; // "__builtin_msa_fsle_d"
	default: break;		case 'w': // 1 string to match.
	case 'c': // 1 string to match.		return Intrinsic::mips_fsle_w; // "__builtin_msa_fsle_w"
	if (BuiltinName[31] != 'c')
	break;
	return Intrinsic::hexagon_S2_lsl_r_p_acc; // "__built
	in_HEXAGON_S2_lsl_r_p_acc"
	case 'n': // 1 string to match.
	if (BuiltinName[31] != 'd')
	break;
	return Intrinsic::hexagon_S2_lsl_r_p_and; // "__built
	in_HEXAGON_S2_lsl_r_p_and"
	}
	break;
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "ac", 2))
	break;
	return Intrinsic::hexagon_S2_lsl_r_p_nac; // "__built
	in_HEXAGON_S2_lsl_r_p_nac"
	case 'x': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "or", 2))
	break;
	return Intrinsic::hexagon_S2_lsl_r_p_xor; // "__built
	in_HEXAGON_S2_lsl_r_p_xor"
	}		}
	break;		break;
	case 'r': // 3 strings to match.		case 't': // 2 strings to match.
	if (BuiltinName[28] != '_')		if (BuiltinName[18] != '_')
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'd': // 1 string to match.
	switch (BuiltinName[30]) {		return Intrinsic::mips_fslt_d; // "__builtin_msa_fslt_d"
	default: break;		case 'w': // 1 string to match.
	case 'c': // 1 string to match.		return Intrinsic::mips_fslt_w; // "__builtin_msa_fslt_w"
	if (BuiltinName[31] != 'c')
	break;
	return Intrinsic::hexagon_S2_lsl_r_r_acc; // "__built
	in_HEXAGON_S2_lsl_r_r_acc"
	case 'n': // 1 string to match.
	if (BuiltinName[31] != 'd')
	break;
	return Intrinsic::hexagon_S2_lsl_r_r_and; // "__built
	in_HEXAGON_S2_lsl_r_r_and"
	}
	break;
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "ac", 2))
	break;
	return Intrinsic::hexagon_S2_lsl_r_r_nac; // "__built
	in_HEXAGON_S2_lsl_r_r_nac"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'r': // 13 strings to match.		case 'n': // 2 strings to match.
	if (BuiltinName[24] != '_')		if (memcmp(BuiltinName.data()+17, "e_", 2))
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'i': // 6 strings to match.		case 'd': // 1 string to match.
	if (BuiltinName[26] != '_')		return Intrinsic::mips_fsne_d; // "__builtin_msa_fsne_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fsne_w; // "__builtin_msa_fsne_w"
			}
			break;
			case 'o': // 2 strings to match.
			if (memcmp(BuiltinName.data()+17, "r_", 2))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fsor_d; // "__builtin_msa_fsor_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fsor_w; // "__builtin_msa_fsor_w"
			}
			break;
			case 'u': // 4 strings to match.
			switch (BuiltinName[17]) {
			default: break;
			case 'b': // 2 strings to match.
			if (BuiltinName[18] != '_')
	break;		break;
	switch (BuiltinName[27]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'p': // 3 strings to match.		case 'd': // 1 string to match.
	if (BuiltinName[28] != '_')		return Intrinsic::mips_fsub_d; // "__builtin_msa_fsub_d"
	break;		case 'w': // 1 string to match.
	switch (BuiltinName[29]) {		return Intrinsic::mips_fsub_w; // "__builtin_msa_fsub_w"
	default: break;
	case 'a': // 2 strings to match.
	switch (BuiltinName[30]) {
	default: break;
	case 'c': // 1 string to match.
	if (BuiltinName[31] != 'c')
	break;
	return Intrinsic::hexagon_S2_lsr_i_p_acc; // "__built
	in_HEXAGON_S2_lsr_i_p_acc"
	case 'n': // 1 string to match.
	if (BuiltinName[31] != 'd')
	break;
	return Intrinsic::hexagon_S2_lsr_i_p_and; // "__built
	in_HEXAGON_S2_lsr_i_p_and"
	}
	break;
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "ac", 2))
	break;
	return Intrinsic::hexagon_S2_lsr_i_p_nac; // "__built
	in_HEXAGON_S2_lsr_i_p_nac"
	}
	break;
	case 'r': // 3 strings to match.
	if (BuiltinName[28] != '_')
	break;
	switch (BuiltinName[29]) {
	default: break;
	case 'a': // 2 strings to match.
	switch (BuiltinName[30]) {
	default: break;
	case 'c': // 1 string to match.
	if (BuiltinName[31] != 'c')
	break;
	return Intrinsic::hexagon_S2_lsr_i_r_acc; // "__built
	in_HEXAGON_S2_lsr_i_r_acc"
	case 'n': // 1 string to match.
	if (BuiltinName[31] != 'd')
	break;
	return Intrinsic::hexagon_S2_lsr_i_r_and; // "__built
	in_HEXAGON_S2_lsr_i_r_and"
	}
	break;
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "ac", 2))
	break;
	return Intrinsic::hexagon_S2_lsr_i_r_nac; // "__built
	in_HEXAGON_S2_lsr_i_r_nac"
	}
	break;
	}		}
	break;		break;
	case 'r': // 7 strings to match.		case 'n': // 2 strings to match.
	if (BuiltinName[26] != '_')		if (BuiltinName[18] != '_')
	break;		break;
	switch (BuiltinName[27]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'p': // 4 strings to match.		case 'd': // 1 string to match.
	if (BuiltinName[28] != '_')		return Intrinsic::mips_fsun_d; // "__builtin_msa_fsun_d"
	break;		case 'w': // 1 string to match.
	switch (BuiltinName[29]) {		return Intrinsic::mips_fsun_w; // "__builtin_msa_fsun_w"
	default: break;		}
	case 'a': // 2 strings to match.		break;
	switch (BuiltinName[30]) {		}
	default: break;		break;
	case 'c': // 1 string to match.		}
	if (BuiltinName[31] != 'c')		break;
	break;		}
	return Intrinsic::hexagon_S2_lsr_r_p_acc; // "__built		break;
	in_HEXAGON_S2_lsr_r_p_acc"		case 'i': // 8 strings to match.
	case 'n': // 1 string to match.		if (memcmp(BuiltinName.data()+15, "lv", 2))
	if (BuiltinName[31] != 'd')		break;
	break;		switch (BuiltinName[17]) {
	return Intrinsic::hexagon_S2_lsr_r_p_and; // "__built		default: break;
	in_HEXAGON_S2_lsr_r_p_and"		case 'l': // 4 strings to match.
	}		if (BuiltinName[18] != '_')
	break;		break;
	case 'n': // 1 string to match.		switch (BuiltinName[19]) {
	if (memcmp(BuiltinName.data()+30, "ac", 2))		default: break;
	break;		case 'b': // 1 string to match.
	return Intrinsic::hexagon_S2_lsr_r_p_nac; // "__built		return Intrinsic::mips_ilvl_b; // "__builtin_msa_ilvl_b"
	in_HEXAGON_S2_lsr_r_p_nac"		case 'd': // 1 string to match.
	case 'x': // 1 string to match.		return Intrinsic::mips_ilvl_d; // "__builtin_msa_ilvl_d"
	if (memcmp(BuiltinName.data()+30, "or", 2))		case 'h': // 1 string to match.
	break;		return Intrinsic::mips_ilvl_h; // "__builtin_msa_ilvl_h"
	return Intrinsic::hexagon_S2_lsr_r_p_xor; // "__built		case 'w': // 1 string to match.
	in_HEXAGON_S2_lsr_r_p_xor"		return Intrinsic::mips_ilvl_w; // "__builtin_msa_ilvl_w"
	}		}
			break;
			case 'r': // 4 strings to match.
			if (BuiltinName[18] != '_')
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_ilvr_b; // "__builtin_msa_ilvr_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_ilvr_d; // "__builtin_msa_ilvr_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_ilvr_h; // "__builtin_msa_ilvr_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ilvr_w; // "__builtin_msa_ilvr_w"
			}
			break;
			}
			break;
			case 'm': // 5 strings to match.
			switch (BuiltinName[15]) {
			default: break;
			case 'o': // 1 string to match.
			if (memcmp(BuiltinName.data()+16, "ve_v", 4))
			break;
			return Intrinsic::mips_move_v; // "__builtin_msa_move_v"
			case 'u': // 4 strings to match.
			if (memcmp(BuiltinName.data()+16, "lv_", 3))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_mulv_b; // "__builtin_msa_mulv_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_mulv_d; // "__builtin_msa_mulv_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_mulv_h; // "__builtin_msa_mulv_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_mulv_w; // "__builtin_msa_mulv_w"
			}
			break;
			}
			break;
			case 'n': // 9 strings to match.
			switch (BuiltinName[15]) {
			default: break;
			case 'l': // 8 strings to match.
			switch (BuiltinName[16]) {
			default: break;
			case 'o': // 4 strings to match.
			if (memcmp(BuiltinName.data()+17, "c_", 2))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_nloc_b; // "__builtin_msa_nloc_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_nloc_d; // "__builtin_msa_nloc_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_nloc_h; // "__builtin_msa_nloc_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_nloc_w; // "__builtin_msa_nloc_w"
			}
			break;
			case 'z': // 4 strings to match.
			if (memcmp(BuiltinName.data()+17, "c_", 2))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_nlzc_b; // "__builtin_msa_nlzc_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_nlzc_d; // "__builtin_msa_nlzc_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_nlzc_h; // "__builtin_msa_nlzc_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_nlzc_w; // "__builtin_msa_nlzc_w"
			}
			break;
			}
			break;
			case 'o': // 1 string to match.
			if (memcmp(BuiltinName.data()+16, "ri_b", 4))
			break;
			return Intrinsic::mips_nori_b; // "__builtin_msa_nori_b"
			}
			break;
			case 'p': // 4 strings to match.
			if (memcmp(BuiltinName.data()+15, "cnt_", 4))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_pcnt_b; // "__builtin_msa_pcnt_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_pcnt_d; // "__builtin_msa_pcnt_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_pcnt_h; // "__builtin_msa_pcnt_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_pcnt_w; // "__builtin_msa_pcnt_w"
			}
			break;
			case 's': // 28 strings to match.
			switch (BuiltinName[15]) {
			default: break;
			case 'l': // 8 strings to match.
			switch (BuiltinName[16]) {
			default: break;
			case 'd': // 4 strings to match.
			if (memcmp(BuiltinName.data()+17, "i_", 2))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_sldi_b; // "__builtin_msa_sldi_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_sldi_d; // "__builtin_msa_sldi_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_sldi_h; // "__builtin_msa_sldi_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_sldi_w; // "__builtin_msa_sldi_w"
			}
			break;
			case 'l': // 4 strings to match.
			if (memcmp(BuiltinName.data()+17, "i_", 2))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_slli_b; // "__builtin_msa_slli_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_slli_d; // "__builtin_msa_slli_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_slli_h; // "__builtin_msa_slli_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_slli_w; // "__builtin_msa_slli_w"
			}
			break;
			}
			break;
			case 'r': // 16 strings to match.
			switch (BuiltinName[16]) {
			default: break;
			case 'a': // 8 strings to match.
			switch (BuiltinName[17]) {
			default: break;
			case 'i': // 4 strings to match.
			if (BuiltinName[18] != '_')
	break;		break;
	case 'r': // 3 strings to match.		switch (BuiltinName[19]) {
	if (BuiltinName[28] != '_')		default: break;
	break;		case 'b': // 1 string to match.
	switch (BuiltinName[29]) {		return Intrinsic::mips_srai_b; // "__builtin_msa_srai_b"
	default: break;		case 'd': // 1 string to match.
	case 'a': // 2 strings to match.		return Intrinsic::mips_srai_d; // "__builtin_msa_srai_d"
	switch (BuiltinName[30]) {		case 'h': // 1 string to match.
	default: break;		return Intrinsic::mips_srai_h; // "__builtin_msa_srai_h"
	case 'c': // 1 string to match.		case 'w': // 1 string to match.
	if (BuiltinName[31] != 'c')		return Intrinsic::mips_srai_w; // "__builtin_msa_srai_w"
	break;		}
	return Intrinsic::hexagon_S2_lsr_r_r_acc; // "__built		break;
	in_HEXAGON_S2_lsr_r_r_acc"		case 'r': // 4 strings to match.
	case 'n': // 1 string to match.		if (BuiltinName[18] != '_')
	if (BuiltinName[31] != 'd')		break;
	break;		switch (BuiltinName[19]) {
	return Intrinsic::hexagon_S2_lsr_r_r_and; // "__built		default: break;
	in_HEXAGON_S2_lsr_r_r_and"		case 'b': // 1 string to match.
	}		return Intrinsic::mips_srar_b; // "__builtin_msa_srar_b"
	break;		case 'd': // 1 string to match.
	case 'n': // 1 string to match.		return Intrinsic::mips_srar_d; // "__builtin_msa_srar_d"
	if (memcmp(BuiltinName.data()+30, "ac", 2))		case 'h': // 1 string to match.
	break;		return Intrinsic::mips_srar_h; // "__builtin_msa_srar_h"
	return Intrinsic::hexagon_S2_lsr_r_r_nac; // "__built		case 'w': // 1 string to match.
	in_HEXAGON_S2_lsr_r_r_nac"		return Intrinsic::mips_srar_w; // "__builtin_msa_srar_w"
	}		}
			break;
			}
			break;
			case 'l': // 8 strings to match.
			switch (BuiltinName[17]) {
			default: break;
			case 'i': // 4 strings to match.
			if (BuiltinName[18] != '_')
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_srli_b; // "__builtin_msa_srli_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_srli_d; // "__builtin_msa_srli_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_srli_h; // "__builtin_msa_srli_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_srli_w; // "__builtin_msa_srli_w"
			}
			break;
			case 'r': // 4 strings to match.
			if (BuiltinName[18] != '_')
	break;		break;
			switch (BuiltinName[19]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_srlr_b; // "__builtin_msa_srlr_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_srlr_d; // "__builtin_msa_srlr_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_srlr_h; // "__builtin_msa_srlr_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_srlr_w; // "__builtin_msa_srlr_w"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 't': // 2 strings to match.		case 'u': // 4 strings to match.
	if (memcmp(BuiltinName.data()+22, "ogglebit_", 9))		if (memcmp(BuiltinName.data()+16, "bv_", 3))
	break;		break;
	switch (BuiltinName[31]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'i': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::hexagon_S2_togglebit_i; // "__builtin_HEXAG		return Intrinsic::mips_subv_b; // "__builtin_msa_subv_b"
	ON_S2_togglebit_i"		case 'd': // 1 string to match.
	case 'r': // 1 string to match.		return Intrinsic::mips_subv_d; // "__builtin_msa_subv_d"
	return Intrinsic::hexagon_S2_togglebit_r; // "__builtin_HEXAG		case 'h': // 1 string to match.
	ON_S2_togglebit_r"		return Intrinsic::mips_subv_h; // "__builtin_msa_subv_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_subv_w; // "__builtin_msa_subv_w"
	}		}
	break;		break;
	case 'v': // 1 string to match.		}
	if (memcmp(BuiltinName.data()+22, "rndpackwhs", 10))		break;
			case 'v': // 4 strings to match.
			if (memcmp(BuiltinName.data()+15, "shf_", 4))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_vshf_b; // "__builtin_msa_vshf_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_vshf_d; // "__builtin_msa_vshf_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_vshf_h; // "__builtin_msa_vshf_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_vshf_w; // "__builtin_msa_vshf_w"
			}
			break;
			case 'x': // 1 string to match.
			if (memcmp(BuiltinName.data()+15, "ori_b", 5))
			break;
			return Intrinsic::mips_xori_b; // "__builtin_msa_xori_b"
			}
			break;
			}
			break;
			case 21: // 186 strings to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_m", 11))
			break;
			switch (BuiltinName[11]) {
			default: break;
			case 'i': // 8 strings to match.
			if (memcmp(BuiltinName.data()+12, "ps_", 3))
			break;
			switch (BuiltinName[15]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(BuiltinName.data()+16, "ppend", 5))
			break;
			return Intrinsic::mips_append; // "__builtin_mips_append"
			case 'b': // 2 strings to match.
			switch (BuiltinName[16]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(BuiltinName.data()+17, "lign", 4))
	break;		break;
	return Intrinsic::hexagon_S2_vrndpackwhs; // "__builtin_HEXAG		return Intrinsic::mips_balign; // "__builtin_mips_balign"
	ON_S2_vrndpackwhs"		case 'i': // 1 string to match.
			if (memcmp(BuiltinName.data()+17, "trev", 4))
			break;
			return Intrinsic::mips_bitrev; // "__builtin_mips_bitrev"
	}		}
	break;		break;
	case '4': // 7 strings to match.		case 'e': // 2 strings to match.
	if (BuiltinName[20] != '_')		if (memcmp(BuiltinName.data()+16, "xt", 2))
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'a': // 4 strings to match.		case 'p': // 1 string to match.
	switch (BuiltinName[22]) {		if (memcmp(BuiltinName.data()+19, "dp", 2))
			break;
			return Intrinsic::mips_extpdp; // "__builtin_mips_extpdp"
			case 'r': // 1 string to match.
			if (memcmp(BuiltinName.data()+19, "_w", 2))
			break;
			return Intrinsic::mips_extr_w; // "__builtin_mips_extr_w"
			}
			break;
			case 'm': // 3 strings to match.
			switch (BuiltinName[16]) {
			default: break;
			case 'o': // 1 string to match.
			if (memcmp(BuiltinName.data()+17, "dsub", 4))
			break;
			return Intrinsic::mips_modsub; // "__builtin_mips_modsub"
			case 't': // 1 string to match.
			if (memcmp(BuiltinName.data()+17, "hlip", 4))
			break;
			return Intrinsic::mips_mthlip; // "__builtin_mips_mthlip"
			case 'u': // 1 string to match.
			if (memcmp(BuiltinName.data()+17, "l_ph", 4))
			break;
			return Intrinsic::mips_mul_ph; // "__builtin_mips_mul_ph"
			}
			break;
			}
			break;
			case 's': // 178 strings to match.
			if (memcmp(BuiltinName.data()+12, "a_", 2))
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'a': // 16 strings to match.
			switch (BuiltinName[15]) {
			default: break;
			case 'd': // 8 strings to match.
			if (BuiltinName[16] != 'd')
			break;
			switch (BuiltinName[17]) {
	default: break;		default: break;
	case 'd': // 2 strings to match.		case '_': // 4 strings to match.
	if (memcmp(BuiltinName.data()+23, "di_", 3))		if (memcmp(BuiltinName.data()+18, "a_", 2))
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "sl_ri", 5))		return Intrinsic::mips_add_a_b; // "__builtin_msa_add_a_b"
	break;		case 'd': // 1 string to match.
	return Intrinsic::hexagon_S4_addi_asl_ri; // "__built		return Intrinsic::mips_add_a_d; // "__builtin_msa_add_a_d"
	in_HEXAGON_S4_addi_asl_ri"		case 'h': // 1 string to match.
	case 'l': // 1 string to match.		return Intrinsic::mips_add_a_h; // "__builtin_msa_add_a_h"
	if (memcmp(BuiltinName.data()+27, "sr_ri", 5))		case 'w': // 1 string to match.
	break;		return Intrinsic::mips_add_a_w; // "__builtin_msa_add_a_w"
	return Intrinsic::hexagon_S4_addi_lsr_ri; // "__built
	in_HEXAGON_S4_addi_lsr_ri"
	}		}
	break;		break;
	case 'n': // 2 strings to match.		case 'v': // 4 strings to match.
	if (memcmp(BuiltinName.data()+23, "di_", 3))		if (memcmp(BuiltinName.data()+18, "i_", 2))
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "sl_ri", 5))		return Intrinsic::mips_addvi_b; // "__builtin_msa_addvi_b"
	break;		case 'd': // 1 string to match.
	return Intrinsic::hexagon_S4_andi_asl_ri; // "__built		return Intrinsic::mips_addvi_d; // "__builtin_msa_addvi_d"
	in_HEXAGON_S4_andi_asl_ri"		case 'h': // 1 string to match.
	case 'l': // 1 string to match.		return Intrinsic::mips_addvi_h; // "__builtin_msa_addvi_h"
	if (memcmp(BuiltinName.data()+27, "sr_ri", 5))		case 'w': // 1 string to match.
	break;		return Intrinsic::mips_addvi_w; // "__builtin_msa_addvi_w"
	return Intrinsic::hexagon_S4_andi_lsr_ri; // "__built
	in_HEXAGON_S4_andi_lsr_ri"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'e': // 1 string to match.		case 'v': // 8 strings to match.
	if (memcmp(BuiltinName.data()+22, "xtractp_rp", 10))		if (memcmp(BuiltinName.data()+16, "e_", 2))
	break;
	return Intrinsic::hexagon_S4_extractp_rp; // "__builtin_HEXAG
	ON_S4_extractp_rp"
	case 's': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "ubi_", 4))
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 's': // 4 strings to match.
	if (memcmp(BuiltinName.data()+27, "sl_ri", 5))		if (BuiltinName[19] != '_')
	break;		break;
	return Intrinsic::hexagon_S4_subi_asl_ri; // "__builtin_HEXAG		switch (BuiltinName[20]) {
	ON_S4_subi_asl_ri"		default: break;
	case 'l': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "sr_ri", 5))		return Intrinsic::mips_ave_s_b; // "__builtin_msa_ave_s_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_ave_s_d; // "__builtin_msa_ave_s_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_ave_s_h; // "__builtin_msa_ave_s_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ave_s_w; // "__builtin_msa_ave_s_w"
			}
			break;
			case 'u': // 4 strings to match.
			if (BuiltinName[19] != '_')
	break;		break;
	return Intrinsic::hexagon_S4_subi_lsr_ri; // "__builtin_HEXAG		switch (BuiltinName[20]) {
	ON_S4_subi_lsr_ri"		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_ave_u_b; // "__builtin_msa_ave_u_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_ave_u_d; // "__builtin_msa_ave_u_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_ave_u_h; // "__builtin_msa_ave_u_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ave_u_w; // "__builtin_msa_ave_u_w"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'b': // 22 strings to match.
	break;		switch (BuiltinName[15]) {
	}		default: break;
	break;		case 'c': // 4 strings to match.
	case 33: // 9 strings to match.		if (memcmp(BuiltinName.data()+16, "lri_", 4))
	if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))		break;
	break;		switch (BuiltinName[20]) {
	switch (BuiltinName[18]) {		default: break;
	default: break;		case 'b': // 1 string to match.
	case 'A': // 2 strings to match.		return Intrinsic::mips_bclri_b; // "__builtin_msa_bclri_b"
	if (memcmp(BuiltinName.data()+19, "4_round_r", 9))		case 'd': // 1 string to match.
	break;		return Intrinsic::mips_bclri_d; // "__builtin_msa_bclri_d"
	switch (BuiltinName[28]) {		case 'h': // 1 string to match.
	default: break;		return Intrinsic::mips_bclri_h; // "__builtin_msa_bclri_h"
	case 'i': // 1 string to match.		case 'w': // 1 string to match.
	if (memcmp(BuiltinName.data()+29, "_sat", 4))		return Intrinsic::mips_bclri_w; // "__builtin_msa_bclri_w"
			}
	break;		break;
	return Intrinsic::hexagon_A4_round_ri_sat; // "__builtin_HEXAG		case 'i': // 8 strings to match.
	ON_A4_round_ri_sat"		if (memcmp(BuiltinName.data()+16, "ns", 2))
	case 'r': // 1 string to match.		break;
	if (memcmp(BuiltinName.data()+29, "_sat", 4))		switch (BuiltinName[18]) {
			default: break;
			case 'l': // 4 strings to match.
			if (BuiltinName[19] != '_')
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_binsl_b; // "__builtin_msa_binsl_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_binsl_d; // "__builtin_msa_binsl_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_binsl_h; // "__builtin_msa_binsl_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_binsl_w; // "__builtin_msa_binsl_w"
			}
			break;
			case 'r': // 4 strings to match.
			if (BuiltinName[19] != '_')
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_binsr_b; // "__builtin_msa_binsr_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_binsr_d; // "__builtin_msa_binsr_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_binsr_h; // "__builtin_msa_binsr_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_binsr_w; // "__builtin_msa_binsr_w"
			}
			break;
			}
	break;		break;
	return Intrinsic::hexagon_A4_round_rr_sat; // "__builtin_HEXAG		case 'm': // 1 string to match.
	ON_A4_round_rr_sat"		if (memcmp(BuiltinName.data()+16, "nzi_b", 5))
	}		break;
	break;		return Intrinsic::mips_bmnzi_b; // "__builtin_msa_bmnzi_b"
	case 'M': // 1 string to match.		case 'n': // 4 strings to match.
	if (memcmp(BuiltinName.data()+19, "2_vrcmpys_s1rp", 14))		if (memcmp(BuiltinName.data()+16, "egi_", 4))
	break;		break;
	return Intrinsic::hexagon_M2_vrcmpys_s1rp; // "__builtin_HEXAG		switch (BuiltinName[20]) {
	ON_M2_vrcmpys_s1rp"		default: break;
	case 'S': // 6 strings to match.		case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+19, "2_", 2))		return Intrinsic::mips_bnegi_b; // "__builtin_msa_bnegi_b"
	break;		case 'd': // 1 string to match.
	switch (BuiltinName[21]) {		return Intrinsic::mips_bnegi_d; // "__builtin_msa_bnegi_d"
	default: break;		case 'h': // 1 string to match.
	case 'a': // 2 strings to match.		return Intrinsic::mips_bnegi_h; // "__builtin_msa_bnegi_h"
	if (memcmp(BuiltinName.data()+22, "sl_i_", 5))		case 'w': // 1 string to match.
			return Intrinsic::mips_bnegi_w; // "__builtin_msa_bnegi_w"
			}
	break;		break;
	switch (BuiltinName[27]) {		case 's': // 5 strings to match.
	default: break;		if (BuiltinName[16] != 'e')
	case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "_xacc", 5))
	break;		break;
	return Intrinsic::hexagon_S2_asl_i_p_xacc; // "__builtin_HEXAG		switch (BuiltinName[17]) {
	ON_S2_asl_i_p_xacc"		default: break;
	case 'r': // 1 string to match.		case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "_xacc", 5))		if (memcmp(BuiltinName.data()+18, "i_b", 3))
			break;
			return Intrinsic::mips_bseli_b; // "__builtin_msa_bseli_b"
			case 't': // 4 strings to match.
			if (memcmp(BuiltinName.data()+18, "i_", 2))
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_bseti_b; // "__builtin_msa_bseti_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_bseti_d; // "__builtin_msa_bseti_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_bseti_h; // "__builtin_msa_bseti_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_bseti_w; // "__builtin_msa_bseti_w"
			}
	break;		break;
	return Intrinsic::hexagon_S2_asl_i_r_xacc; // "__builtin_HEXAG		}
	ON_S2_asl_i_r_xacc"		break;
	}		}
	break;		break;
	case 'd': // 1 string to match.		case 'c': // 16 strings to match.
	if (memcmp(BuiltinName.data()+22, "einterleave", 11))		if (BuiltinName[15] != 'l')
	break;		break;
	return Intrinsic::hexagon_S2_deinterleave; // "__builtin_HEXAG		switch (BuiltinName[16]) {
	ON_S2_deinterleave"		default: break;
	case 'e': // 1 string to match.		case 'e': // 8 strings to match.
	if (memcmp(BuiltinName.data()+22, "xtractup_rp", 11))		if (BuiltinName[17] != '_')
			break;
			switch (BuiltinName[18]) {
			default: break;
			case 's': // 4 strings to match.
			if (BuiltinName[19] != '_')
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_cle_s_b; // "__builtin_msa_cle_s_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_cle_s_d; // "__builtin_msa_cle_s_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_cle_s_h; // "__builtin_msa_cle_s_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_cle_s_w; // "__builtin_msa_cle_s_w"
			}
			break;
			case 'u': // 4 strings to match.
			if (BuiltinName[19] != '_')
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_cle_u_b; // "__builtin_msa_cle_u_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_cle_u_d; // "__builtin_msa_cle_u_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_cle_u_h; // "__builtin_msa_cle_u_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_cle_u_w; // "__builtin_msa_cle_u_w"
			}
			break;
			}
	break;		break;
	return Intrinsic::hexagon_S2_extractup_rp; // "__builtin_HEXAG		case 't': // 8 strings to match.
	ON_S2_extractup_rp"		if (BuiltinName[17] != '_')
	case 'l': // 2 strings to match.		break;
	if (memcmp(BuiltinName.data()+22, "sr_i_", 5))		switch (BuiltinName[18]) {
			default: break;
			case 's': // 4 strings to match.
			if (BuiltinName[19] != '_')
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_clt_s_b; // "__builtin_msa_clt_s_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_clt_s_d; // "__builtin_msa_clt_s_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_clt_s_h; // "__builtin_msa_clt_s_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_clt_s_w; // "__builtin_msa_clt_s_w"
			}
			break;
			case 'u': // 4 strings to match.
			if (BuiltinName[19] != '_')
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_clt_u_b; // "__builtin_msa_clt_u_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_clt_u_d; // "__builtin_msa_clt_u_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_clt_u_h; // "__builtin_msa_clt_u_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_clt_u_w; // "__builtin_msa_clt_u_w"
			}
			break;
			}
	break;		break;
	switch (BuiltinName[27]) {		}
			break;
			case 'd': // 8 strings to match.
			if (memcmp(BuiltinName.data()+15, "iv_", 3))
			break;
			switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 's': // 4 strings to match.
	if (memcmp(BuiltinName.data()+28, "_xacc", 5))		if (BuiltinName[19] != '_')
	break;		break;
	return Intrinsic::hexagon_S2_lsr_i_p_xacc; // "__builtin_HEXAG		switch (BuiltinName[20]) {
	ON_S2_lsr_i_p_xacc"		default: break;
	case 'r': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "_xacc", 5))		return Intrinsic::mips_div_s_b; // "__builtin_msa_div_s_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_div_s_d; // "__builtin_msa_div_s_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_div_s_h; // "__builtin_msa_div_s_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_div_s_w; // "__builtin_msa_div_s_w"
			}
			break;
			case 'u': // 4 strings to match.
			if (BuiltinName[19] != '_')
	break;		break;
	return Intrinsic::hexagon_S2_lsr_i_r_xacc; // "__builtin_HEXAG		switch (BuiltinName[20]) {
	ON_S2_lsr_i_r_xacc"		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_div_u_b; // "__builtin_msa_div_u_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_div_u_d; // "__builtin_msa_div_u_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_div_u_h; // "__builtin_msa_div_u_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_div_u_w; // "__builtin_msa_div_u_w"
			}
			break;
	}		}
	break;		break;
	}		case 'f': // 30 strings to match.
	break;		switch (BuiltinName[15]) {
	}
	break;
	case 34: // 41 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))
	break;
	switch (BuiltinName[18]) {
	default: break;
	case 'M': // 38 strings to match.
	switch (BuiltinName[19]) {
	default: break;
	case '2': // 35 strings to match.
	if (BuiltinName[20] != '_')
	break;
	switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'm': // 33 strings to match.		case 'c': // 8 strings to match.
	if (memcmp(BuiltinName.data()+22, "py_", 3))		if (BuiltinName[16] != 'u')
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[17]) {
	default: break;		default: break;
	case 'a': // 8 strings to match.		case 'e': // 2 strings to match.
	if (memcmp(BuiltinName.data()+26, "cc_", 3))		if (memcmp(BuiltinName.data()+18, "q_", 2))
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'h': // 4 strings to match.		case 'd': // 1 string to match.
	switch (BuiltinName[30]) {		return Intrinsic::mips_fcueq_d; // "__builtin_msa_fcueq_d"
	default: break;		case 'w': // 1 string to match.
	case 'h': // 2 strings to match.		return Intrinsic::mips_fcueq_w; // "__builtin_msa_fcueq_w"
	if (memcmp(BuiltinName.data()+31, "_s", 2))		}
	break;		break;
	switch (BuiltinName[33]) {		case 'l': // 4 strings to match.
	default: break;		switch (BuiltinName[18]) {
	case '0': // 1 string to match.		default: break;
	return Intrinsic::hexagon_M2_mpy_acc_hh_s0; // "__built		case 'e': // 2 strings to match.
	in_HEXAGON_M2_mpy_acc_hh_s0"		if (BuiltinName[19] != '_')
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_acc_hh_s1; // "__built
	in_HEXAGON_M2_mpy_acc_hh_s1"
	}
	break;
	case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+31, "_s", 2))
	break;
	switch (BuiltinName[33]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_acc_hl_s0; // "__built
	in_HEXAGON_M2_mpy_acc_hl_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_acc_hl_s1; // "__built
	in_HEXAGON_M2_mpy_acc_hl_s1"
	}
	break;		break;
			switch (BuiltinName[20]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fcule_d; // "__builtin_msa_f
			cule_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fcule_w; // "__builtin_msa_f
			cule_w"
	}		}
	break;		break;
	case 'l': // 4 strings to match.		case 't': // 2 strings to match.
	switch (BuiltinName[30]) {		if (BuiltinName[19] != '_')
	default: break;
	case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+31, "_s", 2))
	break;
	switch (BuiltinName[33]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_acc_lh_s0; // "__built
	in_HEXAGON_M2_mpy_acc_lh_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_acc_lh_s1; // "__built
	in_HEXAGON_M2_mpy_acc_lh_s1"
	}
	break;
	case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+31, "_s", 2))
	break;
	switch (BuiltinName[33]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_acc_ll_s0; // "__built
	in_HEXAGON_M2_mpy_acc_ll_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_acc_ll_s1; // "__built
	in_HEXAGON_M2_mpy_acc_ll_s1"
	}
	break;		break;
			switch (BuiltinName[20]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fcult_d; // "__builtin_msa_f
			cult_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fcult_w; // "__builtin_msa_f
			cult_w"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'n': // 8 strings to match.		case 'n': // 2 strings to match.
	if (memcmp(BuiltinName.data()+26, "ac_", 3))		if (memcmp(BuiltinName.data()+18, "e_", 2))
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fcune_d; // "__builtin_msa_fcune_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fcune_w; // "__builtin_msa_fcune_w"
			}
			break;
			}
			break;
			case 'e': // 4 strings to match.
			if (BuiltinName[16] != 'x')
			break;
			switch (BuiltinName[17]) {
			default: break;
			case 'd': // 2 strings to match.
			if (memcmp(BuiltinName.data()+18, "o_", 2))
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::mips_fexdo_h; // "__builtin_msa_fexdo_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fexdo_w; // "__builtin_msa_fexdo_w"
			}
			break;
			case 'p': // 2 strings to match.
			if (memcmp(BuiltinName.data()+18, "2_", 2))
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fexp2_d; // "__builtin_msa_fexp2_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fexp2_w; // "__builtin_msa_fexp2_w"
			}
			break;
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+16, "og2_", 4))
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_flog2_d; // "__builtin_msa_flog2_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_flog2_w; // "__builtin_msa_flog2_w"
			}
			break;
			case 'm': // 4 strings to match.
			switch (BuiltinName[16]) {
			default: break;
			case 'a': // 2 strings to match.
			if (memcmp(BuiltinName.data()+17, "dd_", 3))
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fmadd_d; // "__builtin_msa_fmadd_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fmadd_w; // "__builtin_msa_fmadd_w"
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(BuiltinName.data()+17, "ub_", 3))
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'h': // 4 strings to match.		case 'd': // 1 string to match.
	switch (BuiltinName[30]) {		return Intrinsic::mips_fmsub_d; // "__builtin_msa_fmsub_d"
	default: break;		case 'w': // 1 string to match.
	case 'h': // 2 strings to match.		return Intrinsic::mips_fmsub_w; // "__builtin_msa_fmsub_w"
	if (memcmp(BuiltinName.data()+31, "_s", 2))		}
	break;		break;
	switch (BuiltinName[33]) {		}
	default: break;		break;
	case '0': // 1 string to match.		case 'r': // 2 strings to match.
	return Intrinsic::hexagon_M2_mpy_nac_hh_s0; // "__built		if (memcmp(BuiltinName.data()+16, "int_", 4))
	in_HEXAGON_M2_mpy_nac_hh_s0"		break;
	case '1': // 1 string to match.		switch (BuiltinName[20]) {
	return Intrinsic::hexagon_M2_mpy_nac_hh_s1; // "__built		default: break;
	in_HEXAGON_M2_mpy_nac_hh_s1"		case 'd': // 1 string to match.
	}		return Intrinsic::mips_frint_d; // "__builtin_msa_frint_d"
	break;		case 'w': // 1 string to match.
	case 'l': // 2 strings to match.		return Intrinsic::mips_frint_w; // "__builtin_msa_frint_w"
	if (memcmp(BuiltinName.data()+31, "_s", 2))		}
	break;		break;
	switch (BuiltinName[33]) {		case 's': // 10 strings to match.
	default: break;		switch (BuiltinName[16]) {
	case '0': // 1 string to match.		default: break;
	return Intrinsic::hexagon_M2_mpy_nac_hl_s0; // "__built		case 'q': // 2 strings to match.
	in_HEXAGON_M2_mpy_nac_hl_s0"		if (memcmp(BuiltinName.data()+17, "rt_", 3))
	case '1': // 1 string to match.		break;
	return Intrinsic::hexagon_M2_mpy_nac_hl_s1; // "__built		switch (BuiltinName[20]) {
	in_HEXAGON_M2_mpy_nac_hl_s1"		default: break;
	}		case 'd': // 1 string to match.
			return Intrinsic::mips_fsqrt_d; // "__builtin_msa_fsqrt_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fsqrt_w; // "__builtin_msa_fsqrt_w"
			}
			break;
			case 'u': // 8 strings to match.
			switch (BuiltinName[17]) {
			default: break;
			case 'e': // 2 strings to match.
			if (memcmp(BuiltinName.data()+18, "q_", 2))
	break;		break;
			switch (BuiltinName[20]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fsueq_d; // "__builtin_msa_f
			sueq_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fsueq_w; // "__builtin_msa_f
			sueq_w"
	}		}
	break;		break;
	case 'l': // 4 strings to match.		case 'l': // 4 strings to match.
	switch (BuiltinName[30]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'e': // 2 strings to match.
	if (memcmp(BuiltinName.data()+31, "_s", 2))		if (BuiltinName[19] != '_')
	break;		break;
	switch (BuiltinName[33]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_nac_lh_s0; // "__built		return Intrinsic::mips_fsule_d; // "__builtin_msa_f
	in_HEXAGON_M2_mpy_nac_lh_s0"		sule_d"
	case '1': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_nac_lh_s1; // "__built		return Intrinsic::mips_fsule_w; // "__builtin_msa_f
	in_HEXAGON_M2_mpy_nac_lh_s1"		sule_w"
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 't': // 2 strings to match.
	if (memcmp(BuiltinName.data()+31, "_s", 2))		if (BuiltinName[19] != '_')
	break;		break;
	switch (BuiltinName[33]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_nac_ll_s0; // "__built		return Intrinsic::mips_fsult_d; // "__builtin_msa_f
	in_HEXAGON_M2_mpy_nac_ll_s0"		sult_d"
	case '1': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_nac_ll_s1; // "__built		return Intrinsic::mips_fsult_w; // "__builtin_msa_f
	in_HEXAGON_M2_mpy_nac_ll_s1"		sult_w"
	}		}
	break;		break;
	}		}
	break;		break;
			case 'n': // 2 strings to match.
			if (memcmp(BuiltinName.data()+18, "e_", 2))
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fsune_d; // "__builtin_msa_f
			sune_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fsune_w; // "__builtin_msa_f
			sune_w"
			}
			break;
	}		}
	break;		break;
	case 'r': // 8 strings to match.		}
	if (memcmp(BuiltinName.data()+26, "nd_", 3))		break;
			}
			break;
			case 'i': // 12 strings to match.
			switch (BuiltinName[15]) {
			default: break;
			case 'l': // 8 strings to match.
			if (BuiltinName[16] != 'v')
			break;
			switch (BuiltinName[17]) {
			default: break;
			case 'e': // 4 strings to match.
			if (memcmp(BuiltinName.data()+18, "v_", 2))
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'h': // 4 strings to match.		case 'b': // 1 string to match.
	switch (BuiltinName[30]) {		return Intrinsic::mips_ilvev_b; // "__builtin_msa_ilvev_b"
	default: break;		case 'd': // 1 string to match.
	case 'h': // 2 strings to match.		return Intrinsic::mips_ilvev_d; // "__builtin_msa_ilvev_d"
	if (memcmp(BuiltinName.data()+31, "_s", 2))		case 'h': // 1 string to match.
	break;		return Intrinsic::mips_ilvev_h; // "__builtin_msa_ilvev_h"
	switch (BuiltinName[33]) {		case 'w': // 1 string to match.
	default: break;		return Intrinsic::mips_ilvev_w; // "__builtin_msa_ilvev_w"
	case '0': // 1 string to match.		}
	return Intrinsic::hexagon_M2_mpy_rnd_hh_s0; // "__built		break;
	in_HEXAGON_M2_mpy_rnd_hh_s0"		case 'o': // 4 strings to match.
	case '1': // 1 string to match.		if (memcmp(BuiltinName.data()+18, "d_", 2))
	return Intrinsic::hexagon_M2_mpy_rnd_hh_s1; // "__built
	in_HEXAGON_M2_mpy_rnd_hh_s1"
	}
	break;
	case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+31, "_s", 2))
	break;
	switch (BuiltinName[33]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_rnd_hl_s0; // "__built
	in_HEXAGON_M2_mpy_rnd_hl_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_rnd_hl_s1; // "__built
	in_HEXAGON_M2_mpy_rnd_hl_s1"
	}
	break;
	}
	break;		break;
	case 'l': // 4 strings to match.		switch (BuiltinName[20]) {
	switch (BuiltinName[30]) {		default: break;
	default: break;		case 'b': // 1 string to match.
	case 'h': // 2 strings to match.		return Intrinsic::mips_ilvod_b; // "__builtin_msa_ilvod_b"
	if (memcmp(BuiltinName.data()+31, "_s", 2))		case 'd': // 1 string to match.
	break;		return Intrinsic::mips_ilvod_d; // "__builtin_msa_ilvod_d"
	switch (BuiltinName[33]) {		case 'h': // 1 string to match.
	default: break;		return Intrinsic::mips_ilvod_h; // "__builtin_msa_ilvod_h"
	case '0': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_rnd_lh_s0; // "__built		return Intrinsic::mips_ilvod_w; // "__builtin_msa_ilvod_w"
	in_HEXAGON_M2_mpy_rnd_lh_s0"		}
	case '1': // 1 string to match.		break;
	return Intrinsic::hexagon_M2_mpy_rnd_lh_s1; // "__built		}
	in_HEXAGON_M2_mpy_rnd_lh_s1"		break;
	}		case 'n': // 4 strings to match.
	break;		if (memcmp(BuiltinName.data()+16, "sve_", 4))
	case 'l': // 2 strings to match.		break;
	if (memcmp(BuiltinName.data()+31, "_s", 2))		switch (BuiltinName[20]) {
	break;		default: break;
	switch (BuiltinName[33]) {		case 'b': // 1 string to match.
	default: break;		return Intrinsic::mips_insve_b; // "__builtin_msa_insve_b"
	case '0': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_rnd_ll_s0; // "__built		return Intrinsic::mips_insve_d; // "__builtin_msa_insve_d"
	in_HEXAGON_M2_mpy_rnd_ll_s0"		case 'h': // 1 string to match.
	case '1': // 1 string to match.		return Intrinsic::mips_insve_h; // "__builtin_msa_insve_h"
	return Intrinsic::hexagon_M2_mpy_rnd_ll_s1; // "__built		case 'w': // 1 string to match.
	in_HEXAGON_M2_mpy_rnd_ll_s1"		return Intrinsic::mips_insve_w; // "__builtin_msa_insve_w"
	}		}
	break;		break;
	}		}
			break;
			case 'm': // 42 strings to match.
			switch (BuiltinName[15]) {
			default: break;
			case 'a': // 16 strings to match.
			switch (BuiltinName[16]) {
			default: break;
			case 'd': // 4 strings to match.
			if (memcmp(BuiltinName.data()+17, "dv_", 3))
	break;		break;
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_maddv_b; // "__builtin_msa_maddv_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_maddv_d; // "__builtin_msa_maddv_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_maddv_h; // "__builtin_msa_maddv_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_maddv_w; // "__builtin_msa_maddv_w"
	}		}
	break;		break;
	case 's': // 8 strings to match.		case 'x': // 12 strings to match.
	if (memcmp(BuiltinName.data()+26, "at_", 3))		if (BuiltinName[17] != '_')
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'h': // 4 strings to match.		case 'a': // 4 strings to match.
	switch (BuiltinName[30]) {		if (BuiltinName[19] != '_')
	default: break;
	case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+31, "_s", 2))
	break;
	switch (BuiltinName[33]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_sat_hh_s0; // "__built
	in_HEXAGON_M2_mpy_sat_hh_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_sat_hh_s1; // "__built
	in_HEXAGON_M2_mpy_sat_hh_s1"
	}
	break;
	case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+31, "_s", 2))
	break;
	switch (BuiltinName[33]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_sat_hl_s0; // "__built
	in_HEXAGON_M2_mpy_sat_hl_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_sat_hl_s1; // "__built
	in_HEXAGON_M2_mpy_sat_hl_s1"
	}
	break;		break;
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_max_a_b; // "__builtin_msa_m
			ax_a_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_max_a_d; // "__builtin_msa_m
			ax_a_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_max_a_h; // "__builtin_msa_m
			ax_a_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_max_a_w; // "__builtin_msa_m
			ax_a_w"
	}		}
	break;		break;
	case 'l': // 4 strings to match.		case 's': // 4 strings to match.
	switch (BuiltinName[30]) {		if (BuiltinName[19] != '_')
	default: break;
	case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+31, "_s", 2))
	break;
	switch (BuiltinName[33]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_sat_lh_s0; // "__built
	in_HEXAGON_M2_mpy_sat_lh_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_sat_lh_s1; // "__built
	in_HEXAGON_M2_mpy_sat_lh_s1"
	}
	break;		break;
	case 'l': // 2 strings to match.		switch (BuiltinName[20]) {
	if (memcmp(BuiltinName.data()+31, "_s", 2))		default: break;
	break;		case 'b': // 1 string to match.
	switch (BuiltinName[33]) {		return Intrinsic::mips_max_s_b; // "__builtin_msa_m
	default: break;		ax_s_b"
	case '0': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_sat_ll_s0; // "__built		return Intrinsic::mips_max_s_d; // "__builtin_msa_m
	in_HEXAGON_M2_mpy_sat_ll_s0"		ax_s_d"
	case '1': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_sat_ll_s1; // "__built		return Intrinsic::mips_max_s_h; // "__builtin_msa_m
	in_HEXAGON_M2_mpy_sat_ll_s1"		ax_s_h"
	}		case 'w': // 1 string to match.
			return Intrinsic::mips_max_s_w; // "__builtin_msa_m
			ax_s_w"
			}
			break;
			case 'u': // 4 strings to match.
			if (BuiltinName[19] != '_')
	break;		break;
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_max_u_b; // "__builtin_msa_m
			ax_u_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_max_u_d; // "__builtin_msa_m
			ax_u_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_max_u_h; // "__builtin_msa_m
			ax_u_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_max_u_w; // "__builtin_msa_m
			ax_u_w"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'u': // 1 string to match.		}
	if (memcmp(BuiltinName.data()+26, "p_s1_sat", 8))		break;
			case 'i': // 12 strings to match.
			if (memcmp(BuiltinName.data()+16, "n_", 2))
			break;
			switch (BuiltinName[18]) {
			default: break;
			case 'a': // 4 strings to match.
			if (BuiltinName[19] != '_')
	break;		break;
	return Intrinsic::hexagon_M2_mpy_up_s1_sat; // "__built		switch (BuiltinName[20]) {
	in_HEXAGON_M2_mpy_up_s1_sat"		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_min_a_b; // "__builtin_msa_min_a_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_min_a_d; // "__builtin_msa_min_a_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_min_a_h; // "__builtin_msa_min_a_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_min_a_w; // "__builtin_msa_min_a_w"
			}
			break;
			case 's': // 4 strings to match.
			if (BuiltinName[19] != '_')
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_min_s_b; // "__builtin_msa_min_s_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_min_s_d; // "__builtin_msa_min_s_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_min_s_h; // "__builtin_msa_min_s_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_min_s_w; // "__builtin_msa_min_s_w"
			}
			break;
			case 'u': // 4 strings to match.
			if (BuiltinName[19] != '_')
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_min_u_b; // "__builtin_msa_min_u_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_min_u_d; // "__builtin_msa_min_u_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_min_u_h; // "__builtin_msa_min_u_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_min_u_w; // "__builtin_msa_min_u_w"
			}
			break;
	}		}
	break;		break;
	case 'v': // 2 strings to match.		case 'o': // 8 strings to match.
	if (memcmp(BuiltinName.data()+22, "mpy2s_s", 7))		if (memcmp(BuiltinName.data()+16, "d_", 2))
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 's': // 4 strings to match.
	if (memcmp(BuiltinName.data()+30, "pack", 4))		if (BuiltinName[19] != '_')
	break;		break;
	return Intrinsic::hexagon_M2_vmpy2s_s0pack; // "__built		switch (BuiltinName[20]) {
	in_HEXAGON_M2_vmpy2s_s0pack"		default: break;
	case '1': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "pack", 4))		return Intrinsic::mips_mod_s_b; // "__builtin_msa_mod_s_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_mod_s_d; // "__builtin_msa_mod_s_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_mod_s_h; // "__builtin_msa_mod_s_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_mod_s_w; // "__builtin_msa_mod_s_w"
			}
			break;
			case 'u': // 4 strings to match.
			if (BuiltinName[19] != '_')
	break;		break;
	return Intrinsic::hexagon_M2_vmpy2s_s1pack; // "__built		switch (BuiltinName[20]) {
	in_HEXAGON_M2_vmpy2s_s1pack"		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_mod_u_b; // "__builtin_msa_mod_u_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_mod_u_d; // "__builtin_msa_mod_u_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_mod_u_h; // "__builtin_msa_mod_u_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_mod_u_w; // "__builtin_msa_mod_u_w"
			}
			break;
			}
			break;
			case 's': // 4 strings to match.
			if (memcmp(BuiltinName.data()+16, "ubv_", 4))
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_msubv_b; // "__builtin_msa_msubv_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_msubv_d; // "__builtin_msa_msubv_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_msubv_h; // "__builtin_msa_msubv_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_msubv_w; // "__builtin_msa_msubv_w"
			}
			break;
			case 'u': // 2 strings to match.
			if (memcmp(BuiltinName.data()+16, "l_q_", 4))
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::mips_mul_q_h; // "__builtin_msa_mul_q_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_mul_q_w; // "__builtin_msa_mul_q_w"
	}		}
	break;		break;
	}		}
	break;		break;
	case '4': // 3 strings to match.		case 'p': // 8 strings to match.
	if (BuiltinName[20] != '_')		if (memcmp(BuiltinName.data()+15, "ck", 2))
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[17]) {
	default: break;		default: break;
	case 'm': // 2 strings to match.		case 'e': // 4 strings to match.
	switch (BuiltinName[22]) {		if (memcmp(BuiltinName.data()+18, "v_", 2))
			break;
			switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "c_up_s1_sat", 11))		return Intrinsic::mips_pckev_b; // "__builtin_msa_pckev_b"
	break;		case 'd': // 1 string to match.
	return Intrinsic::hexagon_M4_mac_up_s1_sat; // "__built		return Intrinsic::mips_pckev_d; // "__builtin_msa_pckev_d"
	in_HEXAGON_M4_mac_up_s1_sat"		case 'h': // 1 string to match.
	case 'p': // 1 string to match.		return Intrinsic::mips_pckev_h; // "__builtin_msa_pckev_h"
	if (memcmp(BuiltinName.data()+23, "yri_addr_u2", 11))		case 'w': // 1 string to match.
	break;		return Intrinsic::mips_pckev_w; // "__builtin_msa_pckev_w"
	return Intrinsic::hexagon_M4_mpyri_addr_u2; // "__built
	in_HEXAGON_M4_mpyri_addr_u2"
	}		}
	break;		break;
	case 'n': // 1 string to match.		case 'o': // 4 strings to match.
	if (memcmp(BuiltinName.data()+22, "ac_up_s1_sat", 12))		if (memcmp(BuiltinName.data()+18, "d_", 2))
	break;		break;
	return Intrinsic::hexagon_M4_nac_up_s1_sat; // "__builtin_HEXAG		switch (BuiltinName[20]) {
	ON_M4_nac_up_s1_sat"		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_pckod_b; // "__builtin_msa_pckod_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_pckod_d; // "__builtin_msa_pckod_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_pckod_h; // "__builtin_msa_pckod_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_pckod_w; // "__builtin_msa_pckod_w"
			}
			break;
	}		}
	break;		break;
	}		case 's': // 24 strings to match.
	break;		switch (BuiltinName[15]) {
	case 'S': // 3 strings to match.
	switch (BuiltinName[19]) {
	default: break;
	case '2': // 2 strings to match.
	if (memcmp(BuiltinName.data()+20, "_vsat", 5))
	break;
	switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'a': // 8 strings to match.
	if (memcmp(BuiltinName.data()+26, "b_nopack", 8))		if (memcmp(BuiltinName.data()+16, "t_", 2))
	break;		break;
	return Intrinsic::hexagon_S2_vsathb_nopack; // "__builtin_HEXAG		switch (BuiltinName[18]) {
	ON_S2_vsathb_nopack"		default: break;
	case 'w': // 1 string to match.		case 's': // 4 strings to match.
	if (memcmp(BuiltinName.data()+26, "h_nopack", 8))		if (BuiltinName[19] != '_')
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_sat_s_b; // "__builtin_msa_sat_s_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_sat_s_d; // "__builtin_msa_sat_s_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_sat_s_h; // "__builtin_msa_sat_s_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_sat_s_w; // "__builtin_msa_sat_s_w"
			}
	break;		break;
	return Intrinsic::hexagon_S2_vsatwh_nopack; // "__builtin_HEXAG		case 'u': // 4 strings to match.
	ON_S2_vsatwh_nopack"		if (BuiltinName[19] != '_')
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_sat_u_b; // "__builtin_msa_sat_u_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_sat_u_d; // "__builtin_msa_sat_u_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_sat_u_h; // "__builtin_msa_sat_u_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_sat_u_w; // "__builtin_msa_sat_u_w"
			}
			break;
			}
			break;
			case 'p': // 4 strings to match.
			if (memcmp(BuiltinName.data()+16, "lat_", 4))
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_splat_b; // "__builtin_msa_splat_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_splat_d; // "__builtin_msa_splat_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_splat_h; // "__builtin_msa_splat_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_splat_w; // "__builtin_msa_splat_w"
			}
			break;
			case 'r': // 8 strings to match.
			switch (BuiltinName[16]) {
			default: break;
			case 'a': // 4 strings to match.
			if (memcmp(BuiltinName.data()+17, "ri_", 3))
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_srari_b; // "__builtin_msa_srari_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_srari_d; // "__builtin_msa_srari_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_srari_h; // "__builtin_msa_srari_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_srari_w; // "__builtin_msa_srari_w"
			}
			break;
			case 'l': // 4 strings to match.
			if (memcmp(BuiltinName.data()+17, "ri_", 3))
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_srlri_b; // "__builtin_msa_srlri_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_srlri_d; // "__builtin_msa_srlri_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_srlri_h; // "__builtin_msa_srlri_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_srlri_w; // "__builtin_msa_srlri_w"
			}
			break;
			}
			break;
			case 'u': // 4 strings to match.
			if (memcmp(BuiltinName.data()+16, "bvi_", 4))
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_subvi_b; // "__builtin_msa_subvi_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_subvi_d; // "__builtin_msa_subvi_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_subvi_h; // "__builtin_msa_subvi_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_subvi_w; // "__builtin_msa_subvi_w"
			}
			break;
	}		}
	break;		break;
	case '4': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "_vrcrotate_acc", 14))
	break;
	return Intrinsic::hexagon_S4_vrcrotate_acc; // "__builtin_HEXAG
	ON_S4_vrcrotate_acc"
	}		}
	break;		break;
	}		}
	break;		break;
	case 35: // 64 strings to match.		case 22: // 147 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))		if (memcmp(BuiltinName.data()+0, "__builtin_m", 11))
	break;		break;
	switch (BuiltinName[18]) {		switch (BuiltinName[11]) {
	default: break;		default: break;
	case 'F': // 4 strings to match.		case 'i': // 19 strings to match.
	if (memcmp(BuiltinName.data()+19, "2_conv_", 7))		if (memcmp(BuiltinName.data()+12, "ps_", 3))
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[15]) {
	default: break;		default: break;
	case 'd': // 2 strings to match.		case 'a': // 4 strings to match.
	if (memcmp(BuiltinName.data()+27, "f2", 2))		if (memcmp(BuiltinName.data()+16, "dd", 2))
			break;
			switch (BuiltinName[18]) {
			default: break;
			case 'q': // 2 strings to match.
			switch (BuiltinName[19]) {
			default: break;
			case '_': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "ph", 2))
			break;
			return Intrinsic::mips_addq_ph; // "__builtin_mips_addq_ph"
			case 'h': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "_w", 2))
			break;
			return Intrinsic::mips_addqh_w; // "__builtin_mips_addqh_w"
			}
	break;		break;
	switch (BuiltinName[29]) {		case 'u': // 2 strings to match.
			if (BuiltinName[19] != '_')
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'p': // 1 string to match.
			if (BuiltinName[21] != 'h')
			break;
			return Intrinsic::mips_addu_ph; // "__builtin_mips_addu_ph"
			case 'q': // 1 string to match.
			if (BuiltinName[21] != 'b')
			break;
			return Intrinsic::mips_addu_qb; // "__builtin_mips_addu_qb"
			}
			break;
			}
			break;
			case 'p': // 3 strings to match.
			switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'i': // 2 strings to match.
	if (memcmp(BuiltinName.data()+30, "_chop", 5))		if (memcmp(BuiltinName.data()+17, "ck_", 3))
	break;		break;
	return Intrinsic::hexagon_F2_conv_df2d_chop; // "__builtin_HEXAG		switch (BuiltinName[20]) {
	ON_F2_conv_df2d_chop"		default: break;
	case 'w': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "_chop", 5))		if (BuiltinName[21] != 'h')
			break;
			return Intrinsic::mips_pick_ph; // "__builtin_mips_pick_ph"
			case 'q': // 1 string to match.
			if (BuiltinName[21] != 'b')
			break;
			return Intrinsic::mips_pick_qb; // "__builtin_mips_pick_qb"
			}
			break;
			case 'r': // 1 string to match.
			if (memcmp(BuiltinName.data()+17, "epend", 5))
	break;		break;
	return Intrinsic::hexagon_F2_conv_df2w_chop; // "__builtin_HEXAG ON_F2_conv_df2w_chop"		return Intrinsic::mips_prepend; // "__builtin_mips_prepend"
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 'r': // 2 strings to match.
	if (memcmp(BuiltinName.data()+27, "f2", 2))		if (memcmp(BuiltinName.data()+16, "epl_", 4))
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "_chop", 5))		if (BuiltinName[21] != 'h')
	break;		break;
	return Intrinsic::hexagon_F2_conv_sf2d_chop; // "__builtin_HEXAG		return Intrinsic::mips_repl_ph; // "__builtin_mips_repl_ph"
	ON_F2_conv_sf2d_chop"		case 'q': // 1 string to match.
	case 'w': // 1 string to match.		if (BuiltinName[21] != 'b')
	if (memcmp(BuiltinName.data()+30, "_chop", 5))
	break;		break;
	return Intrinsic::hexagon_F2_conv_sf2w_chop; // "__builtin_HEXAG ON_F2_conv_sf2w_chop"		return Intrinsic::mips_repl_qb; // "__builtin_mips_repl_qb"
	}		}
	break;		break;
	}		case 's': // 10 strings to match.
	break;		switch (BuiltinName[16]) {
	case 'M': // 56 strings to match.
	switch (BuiltinName[19]) {
	default: break;
	case '2': // 52 strings to match.
	if (BuiltinName[20] != '_')
	break;
	switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'd': // 5 strings to match.		case 'h': // 6 strings to match.
	if (memcmp(BuiltinName.data()+22, "pmpy", 4))		switch (BuiltinName[17]) {
	break;
	switch (BuiltinName[26]) {
	default: break;		default: break;
	case 's': // 3 strings to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+27, "s_", 2))		if (memcmp(BuiltinName.data()+18, "l_", 2))
	break;
	switch (BuiltinName[29]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "cc_s0", 5))
	break;
	return Intrinsic::hexagon_M2_dpmpyss_acc_s0; // "__built
	in_HEXAGON_M2_dpmpyss_acc_s0"
	case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "ac_s0", 5))
	break;
	return Intrinsic::hexagon_M2_dpmpyss_nac_s0; // "__built
	in_HEXAGON_M2_dpmpyss_nac_s0"
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "nd_s0", 5))
	break;
	return Intrinsic::hexagon_M2_dpmpyss_rnd_s0; // "__built
	in_HEXAGON_M2_dpmpyss_rnd_s0"
	}
	break;
	case 'u': // 2 strings to match.
	if (memcmp(BuiltinName.data()+27, "u_", 2))
	break;		break;
	switch (BuiltinName[29]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "cc_s0", 5))		if (BuiltinName[21] != 'h')
	break;		break;
	return Intrinsic::hexagon_M2_dpmpyuu_acc_s0; // "__built		return Intrinsic::mips_shll_ph; // "__builtin_mips_shll_ph"
	in_HEXAGON_M2_dpmpyuu_acc_s0"		case 'q': // 1 string to match.
	case 'n': // 1 string to match.		if (BuiltinName[21] != 'b')
	if (memcmp(BuiltinName.data()+30, "ac_s0", 5))
	break;		break;
	return Intrinsic::hexagon_M2_dpmpyuu_nac_s0; // "__built in_HEXAGON_M2_dpmpyuu_nac_s0"		return Intrinsic::mips_shll_qb; // "__builtin_mips_shll_qb"
	}		}
	break;		break;
	}		case 'r': // 4 strings to match.
	break;		switch (BuiltinName[18]) {
	case 'm': // 40 strings to match.
	if (memcmp(BuiltinName.data()+22, "py", 2))
	break;
	switch (BuiltinName[24]) {
	default: break;
	case 'd': // 24 strings to match.
	if (BuiltinName[25] != '_')
	break;
	switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'a': // 8 strings to match.		case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+27, "cc_", 3))		if (BuiltinName[19] != '_')
	break;		break;
	switch (BuiltinName[30]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'h': // 4 strings to match.		case 'p': // 1 string to match.
	switch (BuiltinName[31]) {		if (BuiltinName[21] != 'h')
	default: break;
	case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;
	switch (BuiltinName[34]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_acc_hh_s0; //
	"__builtin_HEXAGON_M2_mpyd_acc_hh_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_acc_hh_s1; //
	"__builtin_HEXAGON_M2_mpyd_acc_hh_s1"
	}
	break;
	case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;
	switch (BuiltinName[34]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_acc_hl_s0; //
	"__builtin_HEXAGON_M2_mpyd_acc_hl_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_acc_hl_s1; //
	"__builtin_HEXAGON_M2_mpyd_acc_hl_s1"
	}
	break;
	}
	break;
	case 'l': // 4 strings to match.
	switch (BuiltinName[31]) {
	default: break;
	case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;
	switch (BuiltinName[34]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_acc_lh_s0; //
	"__builtin_HEXAGON_M2_mpyd_acc_lh_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_acc_lh_s1; //
	"__builtin_HEXAGON_M2_mpyd_acc_lh_s1"
	}
	break;		break;
	case 'l': // 2 strings to match.		return Intrinsic::mips_shra_ph; // "__builtin_mips_
	if (memcmp(BuiltinName.data()+32, "_s", 2))		shra_ph"
	break;		case 'q': // 1 string to match.
	switch (BuiltinName[34]) {		if (BuiltinName[21] != 'b')
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_acc_ll_s0; //
	"__builtin_HEXAGON_M2_mpyd_acc_ll_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_acc_ll_s1; //
	"__builtin_HEXAGON_M2_mpyd_acc_ll_s1"
	}
	break;		break;
	}		return Intrinsic::mips_shra_qb; // "__builtin_mips_
	break;		shra_qb"
	}		}
	break;		break;
	case 'n': // 8 strings to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+27, "ac_", 3))		if (BuiltinName[19] != '_')
	break;		break;
	switch (BuiltinName[30]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'h': // 4 strings to match.		case 'p': // 1 string to match.
	switch (BuiltinName[31]) {		if (BuiltinName[21] != 'h')
	default: break;
	case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;
	switch (BuiltinName[34]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_nac_hh_s0; //
	"__builtin_HEXAGON_M2_mpyd_nac_hh_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_nac_hh_s1; //
	"__builtin_HEXAGON_M2_mpyd_nac_hh_s1"
	}
	break;
	case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;
	switch (BuiltinName[34]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_nac_hl_s0; //
	"__builtin_HEXAGON_M2_mpyd_nac_hl_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_nac_hl_s1; //
	"__builtin_HEXAGON_M2_mpyd_nac_hl_s1"
	}
	break;
	}
	break;
	case 'l': // 4 strings to match.
	switch (BuiltinName[31]) {
	default: break;
	case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;
	switch (BuiltinName[34]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_nac_lh_s0; //
	"__builtin_HEXAGON_M2_mpyd_nac_lh_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_nac_lh_s1; //
	"__builtin_HEXAGON_M2_mpyd_nac_lh_s1"
	}
	break;		break;
	case 'l': // 2 strings to match.		return Intrinsic::mips_shrl_ph; // "__builtin_mips_
	if (memcmp(BuiltinName.data()+32, "_s", 2))		shrl_ph"
	break;		case 'q': // 1 string to match.
	switch (BuiltinName[34]) {		if (BuiltinName[21] != 'b')
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_nac_ll_s0; //
	"__builtin_HEXAGON_M2_mpyd_nac_ll_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_nac_ll_s1; //
	"__builtin_HEXAGON_M2_mpyd_nac_ll_s1"
	}
	break;		break;
	}		return Intrinsic::mips_shrl_qb; // "__builtin_mips_
	break;		shrl_qb"
	}		}
	break;		break;
	case 'r': // 8 strings to match.		}
	if (memcmp(BuiltinName.data()+27, "nd_", 3))		break;
	break;		}
	switch (BuiltinName[30]) {		break;
	default: break;		case 'u': // 4 strings to match.
	case 'h': // 4 strings to match.		if (BuiltinName[17] != 'b')
	switch (BuiltinName[31]) {		break;
	default: break;		switch (BuiltinName[18]) {
	case 'h': // 2 strings to match.		default: break;
	if (memcmp(BuiltinName.data()+32, "_s", 2))		case 'q': // 2 strings to match.
	break;		switch (BuiltinName[19]) {
	switch (BuiltinName[34]) {		default: break;
	default: break;		case '_': // 1 string to match.
	case '0': // 1 string to match.		if (memcmp(BuiltinName.data()+20, "ph", 2))
	return Intrinsic::hexagon_M2_mpyd_rnd_hh_s0; //
	"__builtin_HEXAGON_M2_mpyd_rnd_hh_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_rnd_hh_s1; //
	"__builtin_HEXAGON_M2_mpyd_rnd_hh_s1"
	}
	break;
	case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;
	switch (BuiltinName[34]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_rnd_hl_s0; //
	"__builtin_HEXAGON_M2_mpyd_rnd_hl_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_rnd_hl_s1; //
	"__builtin_HEXAGON_M2_mpyd_rnd_hl_s1"
	}
	break;
	}
	break;		break;
	case 'l': // 4 strings to match.		return Intrinsic::mips_subq_ph; // "__builtin_mips_subq_ph"
	switch (BuiltinName[31]) {		case 'h': // 1 string to match.
	default: break;		if (memcmp(BuiltinName.data()+20, "_w", 2))
	case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;
	switch (BuiltinName[34]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_rnd_lh_s0; //
	"__builtin_HEXAGON_M2_mpyd_rnd_lh_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_rnd_lh_s1; //
	"__builtin_HEXAGON_M2_mpyd_rnd_lh_s1"
	}
	break;
	case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;
	switch (BuiltinName[34]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_rnd_ll_s0; //
	"__builtin_HEXAGON_M2_mpyd_rnd_ll_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyd_rnd_ll_s1; //
	"__builtin_HEXAGON_M2_mpyd_rnd_ll_s1"
	}
	break;
	}
	break;		break;
	}		return Intrinsic::mips_subqh_w; // "__builtin_mips_subqh_w"
	break;
	}		}
	break;		break;
	case 'u': // 16 strings to match.		case 'u': // 2 strings to match.
	if (BuiltinName[25] != '_')		if (BuiltinName[19] != '_')
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'a': // 8 strings to match.		case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "cc_", 3))		if (BuiltinName[21] != 'h')
	break;
	switch (BuiltinName[30]) {
	default: break;
	case 'h': // 4 strings to match.
	switch (BuiltinName[31]) {
	default: break;
	case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;
	switch (BuiltinName[34]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyu_acc_hh_s0; //
	"__builtin_HEXAGON_M2_mpyu_acc_hh_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyu_acc_hh_s1; //
	"__builtin_HEXAGON_M2_mpyu_acc_hh_s1"
	}
	break;
	case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;
	switch (BuiltinName[34]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyu_acc_hl_s0; //
	"__builtin_HEXAGON_M2_mpyu_acc_hl_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyu_acc_hl_s1; //
	"__builtin_HEXAGON_M2_mpyu_acc_hl_s1"
	}
	break;
	}
	break;		break;
	case 'l': // 4 strings to match.		return Intrinsic::mips_subu_ph; // "__builtin_mips_subu_ph"
	switch (BuiltinName[31]) {		case 'q': // 1 string to match.
	default: break;		if (BuiltinName[21] != 'b')
	case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;
	switch (BuiltinName[34]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyu_acc_lh_s0; //
	"__builtin_HEXAGON_M2_mpyu_acc_lh_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyu_acc_lh_s1; //
	"__builtin_HEXAGON_M2_mpyu_acc_lh_s1"
	}
	break;
	case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+32, "_s", 2))
	break;
	switch (BuiltinName[34]) {
	default: break;
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyu_acc_ll_s0; //
	"__builtin_HEXAGON_M2_mpyu_acc_ll_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyu_acc_ll_s1; //
	"__builtin_HEXAGON_M2_mpyu_acc_ll_s1"
	}
	break;
	}
	break;		break;
	}		return Intrinsic::mips_subu_qb; // "__builtin_mips_subu_qb"
			}
			break;
			}
			break;
			}
			break;
			}
			break;
			case 's': // 128 strings to match.
			if (memcmp(BuiltinName.data()+12, "a_", 2))
			break;
			switch (BuiltinName[14]) {
			default: break;
			case 'a': // 28 strings to match.
			switch (BuiltinName[15]) {
			default: break;
			case 'd': // 12 strings to match.
			if (memcmp(BuiltinName.data()+16, "ds_", 3))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'a': // 4 strings to match.
			if (BuiltinName[20] != '_')
	break;		break;
	case 'n': // 8 strings to match.		switch (BuiltinName[21]) {
	if (memcmp(BuiltinName.data()+27, "ac_", 3))		default: break;
	break;		case 'b': // 1 string to match.
	switch (BuiltinName[30]) {		return Intrinsic::mips_adds_a_b; // "__builtin_msa_adds_a_b"
	default: break;		case 'd': // 1 string to match.
	case 'h': // 4 strings to match.		return Intrinsic::mips_adds_a_d; // "__builtin_msa_adds_a_d"
	switch (BuiltinName[31]) {		case 'h': // 1 string to match.
	default: break;		return Intrinsic::mips_adds_a_h; // "__builtin_msa_adds_a_h"
	case 'h': // 2 strings to match.		case 'w': // 1 string to match.
	if (memcmp(BuiltinName.data()+32, "_s", 2))		return Intrinsic::mips_adds_a_w; // "__builtin_msa_adds_a_w"
	break;		}
	switch (BuiltinName[34]) {		break;
	default: break;		case 's': // 4 strings to match.
	case '0': // 1 string to match.		if (BuiltinName[20] != '_')
	return Intrinsic::hexagon_M2_mpyu_nac_hh_s0; //		break;
	"__builtin_HEXAGON_M2_mpyu_nac_hh_s0"		switch (BuiltinName[21]) {
	case '1': // 1 string to match.		default: break;
	return Intrinsic::hexagon_M2_mpyu_nac_hh_s1; //		case 'b': // 1 string to match.
	"__builtin_HEXAGON_M2_mpyu_nac_hh_s1"		return Intrinsic::mips_adds_s_b; // "__builtin_msa_adds_s_b"
	}		case 'd': // 1 string to match.
	break;		return Intrinsic::mips_adds_s_d; // "__builtin_msa_adds_s_d"
	case 'l': // 2 strings to match.		case 'h': // 1 string to match.
	if (memcmp(BuiltinName.data()+32, "_s", 2))		return Intrinsic::mips_adds_s_h; // "__builtin_msa_adds_s_h"
	break;		case 'w': // 1 string to match.
	switch (BuiltinName[34]) {		return Intrinsic::mips_adds_s_w; // "__builtin_msa_adds_s_w"
	default: break;		}
	case '0': // 1 string to match.		break;
	return Intrinsic::hexagon_M2_mpyu_nac_hl_s0; //		case 'u': // 4 strings to match.
	"__builtin_HEXAGON_M2_mpyu_nac_hl_s0"		if (BuiltinName[20] != '_')
	case '1': // 1 string to match.		break;
	return Intrinsic::hexagon_M2_mpyu_nac_hl_s1; //		switch (BuiltinName[21]) {
	"__builtin_HEXAGON_M2_mpyu_nac_hl_s1"		default: break;
	}		case 'b': // 1 string to match.
	break;		return Intrinsic::mips_adds_u_b; // "__builtin_msa_adds_u_b"
	}		case 'd': // 1 string to match.
	break;		return Intrinsic::mips_adds_u_d; // "__builtin_msa_adds_u_d"
	case 'l': // 4 strings to match.		case 'h': // 1 string to match.
	switch (BuiltinName[31]) {		return Intrinsic::mips_adds_u_h; // "__builtin_msa_adds_u_h"
	default: break;		case 'w': // 1 string to match.
	case 'h': // 2 strings to match.		return Intrinsic::mips_adds_u_w; // "__builtin_msa_adds_u_w"
	if (memcmp(BuiltinName.data()+32, "_s", 2))		}
	break;		break;
	switch (BuiltinName[34]) {		}
	default: break;		break;
	case '0': // 1 string to match.		case 's': // 8 strings to match.
	return Intrinsic::hexagon_M2_mpyu_nac_lh_s0; //		if (memcmp(BuiltinName.data()+16, "ub_", 3))
	"__builtin_HEXAGON_M2_mpyu_nac_lh_s0"		break;
	case '1': // 1 string to match.		switch (BuiltinName[19]) {
	return Intrinsic::hexagon_M2_mpyu_nac_lh_s1; //		default: break;
	"__builtin_HEXAGON_M2_mpyu_nac_lh_s1"		case 's': // 4 strings to match.
	}		if (BuiltinName[20] != '_')
	break;		break;
	case 'l': // 2 strings to match.		switch (BuiltinName[21]) {
	if (memcmp(BuiltinName.data()+32, "_s", 2))		default: break;
	break;		case 'b': // 1 string to match.
	switch (BuiltinName[34]) {		return Intrinsic::mips_asub_s_b; // "__builtin_msa_asub_s_b"
	default: break;		case 'd': // 1 string to match.
	case '0': // 1 string to match.		return Intrinsic::mips_asub_s_d; // "__builtin_msa_asub_s_d"
	return Intrinsic::hexagon_M2_mpyu_nac_ll_s0; //		case 'h': // 1 string to match.
	"__builtin_HEXAGON_M2_mpyu_nac_ll_s0"		return Intrinsic::mips_asub_s_h; // "__builtin_msa_asub_s_h"
	case '1': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyu_nac_ll_s1; //		return Intrinsic::mips_asub_s_w; // "__builtin_msa_asub_s_w"
	"__builtin_HEXAGON_M2_mpyu_nac_ll_s1"		}
	}		break;
	break;		case 'u': // 4 strings to match.
	}		if (BuiltinName[20] != '_')
	break;		break;
	}		switch (BuiltinName[21]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_asub_u_b; // "__builtin_msa_asub_u_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_asub_u_d; // "__builtin_msa_asub_u_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_asub_u_h; // "__builtin_msa_asub_u_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_asub_u_w; // "__builtin_msa_asub_u_w"
			}
			break;
			}
			break;
			case 'v': // 8 strings to match.
			if (memcmp(BuiltinName.data()+16, "er_", 3))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 's': // 4 strings to match.
			if (BuiltinName[20] != '_')
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_aver_s_b; // "__builtin_msa_aver_s_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_aver_s_d; // "__builtin_msa_aver_s_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_aver_s_h; // "__builtin_msa_aver_s_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_aver_s_w; // "__builtin_msa_aver_s_w"
			}
			break;
			case 'u': // 4 strings to match.
			if (BuiltinName[20] != '_')
	break;		break;
			switch (BuiltinName[21]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_aver_u_b; // "__builtin_msa_aver_u_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_aver_u_d; // "__builtin_msa_aver_u_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_aver_u_h; // "__builtin_msa_aver_u_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_aver_u_w; // "__builtin_msa_aver_u_w"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'v': // 7 strings to match.		}
	switch (BuiltinName[22]) {		break;
			case 'b': // 8 strings to match.
			if (memcmp(BuiltinName.data()+15, "ins", 3))
			break;
			switch (BuiltinName[18]) {
			default: break;
			case 'l': // 4 strings to match.
			if (memcmp(BuiltinName.data()+19, "i_", 2))
			break;
			switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'c': // 6 strings to match.		case 'b': // 1 string to match.
	if (BuiltinName[23] != 'm')		return Intrinsic::mips_binsli_b; // "__builtin_msa_binsli_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_binsli_d; // "__builtin_msa_binsli_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_binsli_h; // "__builtin_msa_binsli_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_binsli_w; // "__builtin_msa_binsli_w"
			}
			break;
			case 'r': // 4 strings to match.
			if (memcmp(BuiltinName.data()+19, "i_", 2))
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_binsri_b; // "__builtin_msa_binsri_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_binsri_d; // "__builtin_msa_binsri_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_binsri_h; // "__builtin_msa_binsri_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_binsri_w; // "__builtin_msa_binsri_w"
			}
			break;
			}
			break;
			case 'c': // 24 strings to match.
			switch (BuiltinName[15]) {
			default: break;
			case 'l': // 16 strings to match.
			switch (BuiltinName[16]) {
			default: break;
			case 'e': // 8 strings to match.
			if (memcmp(BuiltinName.data()+17, "i_", 2))
	break;		break;
	switch (BuiltinName[24]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 's': // 4 strings to match.
	if (memcmp(BuiltinName.data()+25, "c_s0_sat_", 9))		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[34]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'i': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::hexagon_M2_vcmac_s0_sat_i; // "__built		return Intrinsic::mips_clei_s_b; // "__builtin_msa_c
	in_HEXAGON_M2_vcmac_s0_sat_i"		lei_s_b"
	case 'r': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::hexagon_M2_vcmac_s0_sat_r; // "__built		return Intrinsic::mips_clei_s_d; // "__builtin_msa_c
	in_HEXAGON_M2_vcmac_s0_sat_r"		lei_s_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_clei_s_h; // "__builtin_msa_c
			lei_s_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_clei_s_w; // "__builtin_msa_c
			lei_s_w"
	}		}
	break;		break;
	case 'p': // 4 strings to match.		case 'u': // 4 strings to match.
	if (memcmp(BuiltinName.data()+25, "y_s", 3))		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[28]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case '0': // 2 strings to match.		case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+29, "_sat_", 5))		return Intrinsic::mips_clei_u_b; // "__builtin_msa_c
	break;		lei_u_b"
	switch (BuiltinName[34]) {		case 'd': // 1 string to match.
	default: break;		return Intrinsic::mips_clei_u_d; // "__builtin_msa_c
	case 'i': // 1 string to match.		lei_u_d"
	return Intrinsic::hexagon_M2_vcmpy_s0_sat_i; // "__built		case 'h': // 1 string to match.
	in_HEXAGON_M2_vcmpy_s0_sat_i"		return Intrinsic::mips_clei_u_h; // "__builtin_msa_c
	case 'r': // 1 string to match.		lei_u_h"
	return Intrinsic::hexagon_M2_vcmpy_s0_sat_r; // "__built		case 'w': // 1 string to match.
	in_HEXAGON_M2_vcmpy_s0_sat_r"		return Intrinsic::mips_clei_u_w; // "__builtin_msa_c
	}		lei_u_w"
			}
			break;
			}
			break;
			case 't': // 8 strings to match.
			if (memcmp(BuiltinName.data()+17, "i_", 2))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 's': // 4 strings to match.
			if (BuiltinName[20] != '_')
	break;		break;
	case '1': // 2 strings to match.		switch (BuiltinName[21]) {
	if (memcmp(BuiltinName.data()+29, "_sat_", 5))		default: break;
	break;		case 'b': // 1 string to match.
	switch (BuiltinName[34]) {		return Intrinsic::mips_clti_s_b; // "__builtin_msa_c
	default: break;		lti_s_b"
	case 'i': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::hexagon_M2_vcmpy_s1_sat_i; // "__built		return Intrinsic::mips_clti_s_d; // "__builtin_msa_c
	in_HEXAGON_M2_vcmpy_s1_sat_i"		lti_s_d"
	case 'r': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::hexagon_M2_vcmpy_s1_sat_r; // "__built		return Intrinsic::mips_clti_s_h; // "__builtin_msa_c
	in_HEXAGON_M2_vcmpy_s1_sat_r"		lti_s_h"
	}		case 'w': // 1 string to match.
			return Intrinsic::mips_clti_s_w; // "__builtin_msa_c
			lti_s_w"
			}
			break;
			case 'u': // 4 strings to match.
			if (BuiltinName[20] != '_')
	break;		break;
			switch (BuiltinName[21]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_clti_u_b; // "__builtin_msa_c
			lti_u_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_clti_u_d; // "__builtin_msa_c
			lti_u_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_clti_u_h; // "__builtin_msa_c
			lti_u_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_clti_u_w; // "__builtin_msa_c
			lti_u_w"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'r': // 1 string to match.		}
	if (memcmp(BuiltinName.data()+23, "cmpys_acc_s1", 12))		break;
			case 'o': // 8 strings to match.
			if (memcmp(BuiltinName.data()+16, "py_", 3))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 's': // 4 strings to match.
			if (BuiltinName[20] != '_')
	break;		break;
	return Intrinsic::hexagon_M2_vrcmpys_acc_s1; // "__built		switch (BuiltinName[21]) {
	in_HEXAGON_M2_vrcmpys_acc_s1"		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_copy_s_b; // "__builtin_msa_copy_s_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_copy_s_d; // "__builtin_msa_copy_s_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_copy_s_h; // "__builtin_msa_copy_s_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_copy_s_w; // "__builtin_msa_copy_s_w"
			}
			break;
			case 'u': // 4 strings to match.
			if (BuiltinName[20] != '_')
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_copy_u_b; // "__builtin_msa_copy_u_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_copy_u_d; // "__builtin_msa_copy_u_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_copy_u_h; // "__builtin_msa_copy_u_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_copy_u_w; // "__builtin_msa_copy_u_w"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case '4': // 4 strings to match.		case 'd': // 6 strings to match.
	if (memcmp(BuiltinName.data()+20, "_vrmpy", 6))		if (memcmp(BuiltinName.data()+15, "otp_", 4))
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'e': // 2 strings to match.		case 's': // 3 strings to match.
	if (memcmp(BuiltinName.data()+27, "h_acc_s", 7))		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[34]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::hexagon_M4_vrmpyeh_acc_s0; // "__built		return Intrinsic::mips_dotp_s_d; // "__builtin_msa_dotp_s_d"
	in_HEXAGON_M4_vrmpyeh_acc_s0"		case 'h': // 1 string to match.
	case '1': // 1 string to match.		return Intrinsic::mips_dotp_s_h; // "__builtin_msa_dotp_s_h"
	return Intrinsic::hexagon_M4_vrmpyeh_acc_s1; // "__built		case 'w': // 1 string to match.
	in_HEXAGON_M4_vrmpyeh_acc_s1"		return Intrinsic::mips_dotp_s_w; // "__builtin_msa_dotp_s_w"
	}		}
	break;		break;
	case 'o': // 2 strings to match.		case 'u': // 3 strings to match.
	if (memcmp(BuiltinName.data()+27, "h_acc_s", 7))		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[34]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::hexagon_M4_vrmpyoh_acc_s0; // "__built		return Intrinsic::mips_dotp_u_d; // "__builtin_msa_dotp_u_d"
	in_HEXAGON_M4_vrmpyoh_acc_s0"		case 'h': // 1 string to match.
	case '1': // 1 string to match.		return Intrinsic::mips_dotp_u_h; // "__builtin_msa_dotp_u_h"
	return Intrinsic::hexagon_M4_vrmpyoh_acc_s1; // "__built		case 'w': // 1 string to match.
	in_HEXAGON_M4_vrmpyoh_acc_s1"		return Intrinsic::mips_dotp_u_w; // "__builtin_msa_dotp_u_w"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'f': // 12 strings to match.
	break;		switch (BuiltinName[15]) {
	case 'S': // 4 strings to match.
	if (memcmp(BuiltinName.data()+19, "2_", 2))
	break;
	switch (BuiltinName[21]) {
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "sr_", 3))
	break;
	switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'i': // 1 string to match.		case 'c': // 2 strings to match.
	if (memcmp(BuiltinName.data()+26, "_svw_trun", 9))		if (memcmp(BuiltinName.data()+16, "lass_", 5))
	break;
	return Intrinsic::hexagon_S2_asr_i_svw_trun; // "__builtin_HEXAG
	ON_S2_asr_i_svw_trun"
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "_svw_trun", 9))
	break;		break;
	return Intrinsic::hexagon_S2_asr_r_svw_trun; // "__builtin_HEXAG		switch (BuiltinName[21]) {
	ON_S2_asr_r_svw_trun"		default: break;
	}		case 'd': // 1 string to match.
	break;		return Intrinsic::mips_fclass_d; // "__builtin_msa_fclass_d"
	case 'v': // 2 strings to match.		case 'w': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "sat", 3))		return Intrinsic::mips_fclass_w; // "__builtin_msa_fclass_w"
			}
	break;		break;
	switch (BuiltinName[25]) {		case 'e': // 4 strings to match.
	default: break;		if (memcmp(BuiltinName.data()+16, "xup", 3))
	case 'h': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "ub_nopack", 9))
	break;		break;
	return Intrinsic::hexagon_S2_vsathub_nopack; // "__builtin_HEXAG		switch (BuiltinName[19]) {
	ON_S2_vsathub_nopack"		default: break;
	case 'w': // 1 string to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+26, "uh_nopack", 9))		if (BuiltinName[20] != '_')
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_fexupl_d; // "__builtin_msa_fexupl_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_fexupl_w; // "__builtin_msa_fexupl_w"
			}
	break;		break;
	return Intrinsic::hexagon_S2_vsatwuh_nopack; // "__builtin_HEXAG		case 'r': // 2 strings to match.
	ON_S2_vsatwuh_nopack"		if (BuiltinName[20] != '_')
	}		break;
	break;		switch (BuiltinName[21]) {
	}		default: break;
	break;		case 'd': // 1 string to match.
	}		return Intrinsic::mips_fexupr_d; // "__builtin_msa_fexupr_d"
	break;		case 'w': // 1 string to match.
	case 36: // 33 strings to match.		return Intrinsic::mips_fexupr_w; // "__builtin_msa_fexupr_w"
	if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_", 18))		}
	break;
	switch (BuiltinName[18]) {
	default: break;
	case 'A': // 12 strings to match.
	if (memcmp(BuiltinName.data()+19, "2_", 2))
	break;
	switch (BuiltinName[21]) {
	default: break;
	case 'a': // 6 strings to match.
	if (memcmp(BuiltinName.data()+22, "ddh_", 4))
	break;
	switch (BuiltinName[26]) {
	default: break;
	case 'h': // 4 strings to match.
	if (memcmp(BuiltinName.data()+27, "16_sat_", 7))
	break;		break;
	switch (BuiltinName[34]) {		}
			break;
			case 'm': // 4 strings to match.
			switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'a': // 2 strings to match.
	switch (BuiltinName[35]) {		if (memcmp(BuiltinName.data()+17, "x_a_", 4))
			break;
			switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::hexagon_A2_addh_h16_sat_hh; // "__built		return Intrinsic::mips_fmax_a_d; // "__builtin_msa_fmax_a_d"
	in_HEXAGON_A2_addh_h16_sat_hh"		case 'w': // 1 string to match.
	case 'l': // 1 string to match.		return Intrinsic::mips_fmax_a_w; // "__builtin_msa_fmax_a_w"
	return Intrinsic::hexagon_A2_addh_h16_sat_hl; // "__built
	in_HEXAGON_A2_addh_h16_sat_hl"
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'i': // 2 strings to match.
	switch (BuiltinName[35]) {		if (memcmp(BuiltinName.data()+17, "n_a_", 4))
			break;
			switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::hexagon_A2_addh_h16_sat_lh; // "__built		return Intrinsic::mips_fmin_a_d; // "__builtin_msa_fmin_a_d"
	in_HEXAGON_A2_addh_h16_sat_lh"		case 'w': // 1 string to match.
	case 'l': // 1 string to match.		return Intrinsic::mips_fmin_a_w; // "__builtin_msa_fmin_a_w"
	return Intrinsic::hexagon_A2_addh_h16_sat_ll; // "__built
	in_HEXAGON_A2_addh_h16_sat_ll"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'r': // 2 strings to match.
	if (memcmp(BuiltinName.data()+27, "16_sat_", 7))		if (memcmp(BuiltinName.data()+16, "sqrt_", 5))
	break;		break;
	switch (BuiltinName[34]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'd': // 1 string to match.
	if (BuiltinName[35] != 'l')		return Intrinsic::mips_frsqrt_d; // "__builtin_msa_frsqrt_d"
	break;		case 'w': // 1 string to match.
	return Intrinsic::hexagon_A2_addh_l16_sat_hl; // "__built		return Intrinsic::mips_frsqrt_w; // "__builtin_msa_frsqrt_w"
	in_HEXAGON_A2_addh_l16_sat_hl"
	case 'l': // 1 string to match.
	if (BuiltinName[35] != 'l')
	break;
	return Intrinsic::hexagon_A2_addh_l16_sat_ll; // "__built
	in_HEXAGON_A2_addh_l16_sat_ll"
	}		}
	break;		break;
	}		}
	break;		break;
	case 's': // 6 strings to match.		case 'h': // 12 strings to match.
	if (memcmp(BuiltinName.data()+22, "ubh_", 4))		switch (BuiltinName[15]) {
	break;
	switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'h': // 4 strings to match.		case 'a': // 6 strings to match.
	if (memcmp(BuiltinName.data()+27, "16_sat_", 7))		if (memcmp(BuiltinName.data()+16, "dd_", 3))
	break;		break;
	switch (BuiltinName[34]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 's': // 3 strings to match.
	switch (BuiltinName[35]) {		if (BuiltinName[20] != '_')
			break;
			switch (BuiltinName[21]) {
	default: break;		default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_hadd_s_d; // "__builtin_msa_hadd_s_d"
	case 'h': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::hexagon_A2_subh_h16_sat_hh; // "__built		return Intrinsic::mips_hadd_s_h; // "__builtin_msa_hadd_s_h"
	in_HEXAGON_A2_subh_h16_sat_hh"		case 'w': // 1 string to match.
	case 'l': // 1 string to match.		return Intrinsic::mips_hadd_s_w; // "__builtin_msa_hadd_s_w"
	return Intrinsic::hexagon_A2_subh_h16_sat_hl; // "__built
	in_HEXAGON_A2_subh_h16_sat_hl"
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'u': // 3 strings to match.
	switch (BuiltinName[35]) {		if (BuiltinName[20] != '_')
			break;
			switch (BuiltinName[21]) {
	default: break;		default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_hadd_u_d; // "__builtin_msa_hadd_u_d"
	case 'h': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::hexagon_A2_subh_h16_sat_lh; // "__built		return Intrinsic::mips_hadd_u_h; // "__builtin_msa_hadd_u_h"
	in_HEXAGON_A2_subh_h16_sat_lh"		case 'w': // 1 string to match.
	case 'l': // 1 string to match.		return Intrinsic::mips_hadd_u_w; // "__builtin_msa_hadd_u_w"
	return Intrinsic::hexagon_A2_subh_h16_sat_ll; // "__built
	in_HEXAGON_A2_subh_h16_sat_ll"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 's': // 6 strings to match.
	if (memcmp(BuiltinName.data()+27, "16_sat_", 7))		if (memcmp(BuiltinName.data()+16, "ub_", 3))
	break;		break;
	switch (BuiltinName[34]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 's': // 3 strings to match.
	if (BuiltinName[35] != 'l')		if (BuiltinName[20] != '_')
	break;		break;
	return Intrinsic::hexagon_A2_subh_l16_sat_hl; // "__built		switch (BuiltinName[21]) {
	in_HEXAGON_A2_subh_l16_sat_hl"		default: break;
	case 'l': // 1 string to match.		case 'd': // 1 string to match.
	if (BuiltinName[35] != 'l')		return Intrinsic::mips_hsub_s_d; // "__builtin_msa_hsub_s_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_hsub_s_h; // "__builtin_msa_hsub_s_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_hsub_s_w; // "__builtin_msa_hsub_s_w"
			}
			break;
			case 'u': // 3 strings to match.
			if (BuiltinName[20] != '_')
	break;		break;
	return Intrinsic::hexagon_A2_subh_l16_sat_ll; // "__built		switch (BuiltinName[21]) {
	in_HEXAGON_A2_subh_l16_sat_ll"		default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_hsub_u_d; // "__builtin_msa_hsub_u_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_hsub_u_h; // "__builtin_msa_hsub_u_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_hsub_u_w; // "__builtin_msa_hsub_u_w"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'i': // 4 strings to match.
	break;		if (memcmp(BuiltinName.data()+15, "nsert_", 6))
	case 'C': // 1 string to match.
	if (memcmp(BuiltinName.data()+19, "4_fastcorner9_not", 17))
	break;
	return Intrinsic::hexagon_C4_fastcorner9_not; // "__builtin_HEXAG
	ON_C4_fastcorner9_not"
	case 'F': // 4 strings to match.
	if (memcmp(BuiltinName.data()+19, "2_conv_", 7))
	break;
	switch (BuiltinName[26]) {
	default: break;
	case 'd': // 2 strings to match.
	if (memcmp(BuiltinName.data()+27, "f2u", 3))
	break;
	switch (BuiltinName[30]) {
	default: break;
	case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+31, "_chop", 5))
	break;
	return Intrinsic::hexagon_F2_conv_df2ud_chop; // "__built
	in_HEXAGON_F2_conv_df2ud_chop"
	case 'w': // 1 string to match.
	if (memcmp(BuiltinName.data()+31, "_chop", 5))
	break;
	return Intrinsic::hexagon_F2_conv_df2uw_chop; // "__built
	in_HEXAGON_F2_conv_df2uw_chop"
	}
	break;
	case 's': // 2 strings to match.
	if (memcmp(BuiltinName.data()+27, "f2u", 3))
	break;		break;
	switch (BuiltinName[30]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_insert_b; // "__builtin_msa_insert_b"
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+31, "_chop", 5))		return Intrinsic::mips_insert_d; // "__builtin_msa_insert_d"
	break;		case 'h': // 1 string to match.
	return Intrinsic::hexagon_F2_conv_sf2ud_chop; // "__built		return Intrinsic::mips_insert_h; // "__builtin_msa_insert_h"
	in_HEXAGON_F2_conv_sf2ud_chop"
	case 'w': // 1 string to match.		case 'w': // 1 string to match.
	if (memcmp(BuiltinName.data()+31, "_chop", 5))		return Intrinsic::mips_insert_w; // "__builtin_msa_insert_w"
	break;
	return Intrinsic::hexagon_F2_conv_sf2uw_chop; // "__built
	in_HEXAGON_F2_conv_sf2uw_chop"
	}		}
	break;		break;
	}		case 'm': // 22 strings to match.
	break;		switch (BuiltinName[15]) {
	case 'M': // 16 strings to match.
	if (memcmp(BuiltinName.data()+19, "2_mpyud_", 8))
	break;
	switch (BuiltinName[27]) {
	default: break;
	case 'a': // 8 strings to match.
	if (memcmp(BuiltinName.data()+28, "cc_", 3))
	break;
	switch (BuiltinName[31]) {
	default: break;		default: break;
	case 'h': // 4 strings to match.		case 'a': // 10 strings to match.
	switch (BuiltinName[32]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'd': // 2 strings to match.
	if (memcmp(BuiltinName.data()+33, "_s", 2))		if (memcmp(BuiltinName.data()+17, "d_q_", 4))
	break;		break;
	switch (BuiltinName[35]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'h': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyud_acc_hh_s0; // "__built		return Intrinsic::mips_madd_q_h; // "__builtin_msa_madd_q_h"
	in_HEXAGON_M2_mpyud_acc_hh_s0"		case 'w': // 1 string to match.
	case '1': // 1 string to match.		return Intrinsic::mips_madd_q_w; // "__builtin_msa_madd_q_w"
	return Intrinsic::hexagon_M2_mpyud_acc_hh_s1; // "__built
	in_HEXAGON_M2_mpyud_acc_hh_s1"
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'x': // 8 strings to match.
	if (memcmp(BuiltinName.data()+33, "_s", 2))		if (memcmp(BuiltinName.data()+17, "i_", 2))
	break;		break;
	switch (BuiltinName[35]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 's': // 4 strings to match.
	return Intrinsic::hexagon_M2_mpyud_acc_hl_s0; // "__built		if (BuiltinName[20] != '_')
	in_HEXAGON_M2_mpyud_acc_hl_s0"		break;
	case '1': // 1 string to match.		switch (BuiltinName[21]) {
	return Intrinsic::hexagon_M2_mpyud_acc_hl_s1; // "__built		default: break;
	in_HEXAGON_M2_mpyud_acc_hl_s1"		case 'b': // 1 string to match.
			return Intrinsic::mips_maxi_s_b; // "__builtin_msa_m
			axi_s_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_maxi_s_d; // "__builtin_msa_m
			axi_s_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_maxi_s_h; // "__builtin_msa_m
			axi_s_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_maxi_s_w; // "__builtin_msa_m
			axi_s_w"
			}
			break;
			case 'u': // 4 strings to match.
			if (BuiltinName[20] != '_')
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_maxi_u_b; // "__builtin_msa_m
			axi_u_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_maxi_u_d; // "__builtin_msa_m
			axi_u_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_maxi_u_h; // "__builtin_msa_m
			axi_u_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_maxi_u_w; // "__builtin_msa_m
			axi_u_w"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'l': // 4 strings to match.		case 'i': // 8 strings to match.
	switch (BuiltinName[32]) {		if (memcmp(BuiltinName.data()+16, "ni_", 3))
			break;
			switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 's': // 4 strings to match.
	if (memcmp(BuiltinName.data()+33, "_s", 2))		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[35]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyud_acc_lh_s0; // "__built		return Intrinsic::mips_mini_s_b; // "__builtin_msa_mini_s_b"
	in_HEXAGON_M2_mpyud_acc_lh_s0"		case 'd': // 1 string to match.
	case '1': // 1 string to match.		return Intrinsic::mips_mini_s_d; // "__builtin_msa_mini_s_d"
	return Intrinsic::hexagon_M2_mpyud_acc_lh_s1; // "__built		case 'h': // 1 string to match.
	in_HEXAGON_M2_mpyud_acc_lh_s1"		return Intrinsic::mips_mini_s_h; // "__builtin_msa_mini_s_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_mini_s_w; // "__builtin_msa_mini_s_w"
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'u': // 4 strings to match.
	if (memcmp(BuiltinName.data()+33, "_s", 2))		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[35]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyud_acc_ll_s0; // "__built		return Intrinsic::mips_mini_u_b; // "__builtin_msa_mini_u_b"
	in_HEXAGON_M2_mpyud_acc_ll_s0"		case 'd': // 1 string to match.
	case '1': // 1 string to match.		return Intrinsic::mips_mini_u_d; // "__builtin_msa_mini_u_d"
	return Intrinsic::hexagon_M2_mpyud_acc_ll_s1; // "__built		case 'h': // 1 string to match.
	in_HEXAGON_M2_mpyud_acc_ll_s1"		return Intrinsic::mips_mini_u_h; // "__builtin_msa_mini_u_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_mini_u_w; // "__builtin_msa_mini_u_w"
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 's': // 2 strings to match.
	break;		if (memcmp(BuiltinName.data()+16, "ub_q_", 5))
	case 'n': // 8 strings to match.		break;
	if (memcmp(BuiltinName.data()+28, "ac_", 3))		switch (BuiltinName[21]) {
	break;
	switch (BuiltinName[31]) {
	default: break;
	case 'h': // 4 strings to match.
	switch (BuiltinName[32]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'h': // 1 string to match.
	if (memcmp(BuiltinName.data()+33, "_s", 2))		return Intrinsic::mips_msub_q_h; // "__builtin_msa_msub_q_h"
	break;		case 'w': // 1 string to match.
	switch (BuiltinName[35]) {		return Intrinsic::mips_msub_q_w; // "__builtin_msa_msub_q_w"
	default: break;		}
	case '0': // 1 string to match.		break;
	return Intrinsic::hexagon_M2_mpyud_nac_hh_s0; // "__built		case 'u': // 2 strings to match.
	in_HEXAGON_M2_mpyud_nac_hh_s0"		if (memcmp(BuiltinName.data()+16, "lr_q_", 5))
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyud_nac_hh_s1; // "__built
	in_HEXAGON_M2_mpyud_nac_hh_s1"
	}
	break;		break;
	case 'l': // 2 strings to match.		switch (BuiltinName[21]) {
	if (memcmp(BuiltinName.data()+33, "_s", 2))		default: break;
	break;		case 'h': // 1 string to match.
	switch (BuiltinName[35]) {		return Intrinsic::mips_mulr_q_h; // "__builtin_msa_mulr_q_h"
	default: break;		case 'w': // 1 string to match.
	case '0': // 1 string to match.		return Intrinsic::mips_mulr_q_w; // "__builtin_msa_mulr_q_w"
	return Intrinsic::hexagon_M2_mpyud_nac_hl_s0; // "__built		}
	in_HEXAGON_M2_mpyud_nac_hl_s0"		break;
	case '1': // 1 string to match.		}
	return Intrinsic::hexagon_M2_mpyud_nac_hl_s1; // "__built		break;
	in_HEXAGON_M2_mpyud_nac_hl_s1"		case 's': // 12 strings to match.
	}		switch (BuiltinName[15]) {
			default: break;
			case 'p': // 4 strings to match.
			if (memcmp(BuiltinName.data()+16, "lati_", 5))
	break;		break;
			switch (BuiltinName[21]) {
			default: break;
			case 'b': // 1 string to match.
			return Intrinsic::mips_splati_b; // "__builtin_msa_splati_b"
			case 'd': // 1 string to match.
			return Intrinsic::mips_splati_d; // "__builtin_msa_splati_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_splati_h; // "__builtin_msa_splati_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_splati_w; // "__builtin_msa_splati_w"
	}		}
	break;		break;
	case 'l': // 4 strings to match.		case 'u': // 8 strings to match.
	switch (BuiltinName[32]) {		if (memcmp(BuiltinName.data()+16, "bs_", 3))
			break;
			switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 's': // 4 strings to match.
	if (memcmp(BuiltinName.data()+33, "_s", 2))		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[35]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyud_nac_lh_s0; // "__built		return Intrinsic::mips_subs_s_b; // "__builtin_msa_subs_s_b"
	in_HEXAGON_M2_mpyud_nac_lh_s0"		case 'd': // 1 string to match.
	case '1': // 1 string to match.		return Intrinsic::mips_subs_s_d; // "__builtin_msa_subs_s_d"
	return Intrinsic::hexagon_M2_mpyud_nac_lh_s1; // "__built		case 'h': // 1 string to match.
	in_HEXAGON_M2_mpyud_nac_lh_s1"		return Intrinsic::mips_subs_s_h; // "__builtin_msa_subs_s_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_subs_s_w; // "__builtin_msa_subs_s_w"
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'u': // 4 strings to match.
	if (memcmp(BuiltinName.data()+33, "_s", 2))		if (BuiltinName[20] != '_')
	break;		break;
	switch (BuiltinName[35]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::hexagon_M2_mpyud_nac_ll_s0; // "__built		return Intrinsic::mips_subs_u_b; // "__builtin_msa_subs_u_b"
	in_HEXAGON_M2_mpyud_nac_ll_s0"		case 'd': // 1 string to match.
	case '1': // 1 string to match.		return Intrinsic::mips_subs_u_d; // "__builtin_msa_subs_u_d"
	return Intrinsic::hexagon_M2_mpyud_nac_ll_s1; // "__built		case 'h': // 1 string to match.
	in_HEXAGON_M2_mpyud_nac_ll_s1"		return Intrinsic::mips_subs_u_h; // "__builtin_msa_subs_u_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_subs_u_w; // "__builtin_msa_subs_u_w"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 38: // 24 strings to match.		case 23: // 40 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_M2_mpy_", 25))		if (memcmp(BuiltinName.data()+0, "__builtin_m", 11))
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[11]) {
	default: break;		default: break;
	case 'a': // 8 strings to match.		case 'i': // 16 strings to match.
	if (memcmp(BuiltinName.data()+26, "cc_sat_", 7))		if (memcmp(BuiltinName.data()+12, "ps_", 3))
	break;		break;
	switch (BuiltinName[33]) {		switch (BuiltinName[15]) {
	default: break;		default: break;
	case 'h': // 4 strings to match.		case 'a': // 4 strings to match.
	switch (BuiltinName[34]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+35, "_s", 2))		if (memcmp(BuiltinName.data()+17, "sq_s_w", 6))
	break;		break;
	switch (BuiltinName[37]) {		return Intrinsic::mips_absq_s_w; // "__builtin_mips_absq_s_w
	default: break;		"
	case '0': // 1 string to match.		case 'd': // 3 strings to match.
	return Intrinsic::hexagon_M2_mpy_acc_sat_hh_s0; // "__built		if (BuiltinName[17] != 'd')
	in_HEXAGON_M2_mpy_acc_sat_hh_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_acc_sat_hh_s1; // "__built
	in_HEXAGON_M2_mpy_acc_sat_hh_s1"
	}
	break;
	case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+35, "_s", 2))
	break;		break;
	switch (BuiltinName[37]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'q': // 2 strings to match.
	return Intrinsic::hexagon_M2_mpy_acc_sat_hl_s0; // "__built		switch (BuiltinName[19]) {
	in_HEXAGON_M2_mpy_acc_sat_hl_s0"		default: break;
	case '1': // 1 string to match.		case '_': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_acc_sat_hl_s1; // "__built		if (memcmp(BuiltinName.data()+20, "s_w", 3))
	in_HEXAGON_M2_mpy_acc_sat_hl_s1"		break;
			return Intrinsic::mips_addq_s_w; // "__builtin_mips_addq_s_w
			"
			case 'h': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "_ph", 3))
			break;
			return Intrinsic::mips_addqh_ph; // "__builtin_mips_addqh_ph
			"
			}
			break;
			case 'u': // 1 string to match.
			if (memcmp(BuiltinName.data()+19, "h_qb", 4))
			break;
			return Intrinsic::mips_adduh_qb; // "__builtin_mips_adduh_qb
			"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'l': // 4 strings to match.		case 'b': // 1 string to match.
	switch (BuiltinName[34]) {		if (memcmp(BuiltinName.data()+16, "posge32", 7))
			break;
			return Intrinsic::mips_bposge32; // "__builtin_mips_bposge32
			"
			case 'd': // 2 strings to match.
			if (BuiltinName[16] != 'p')
			break;
			switch (BuiltinName[17]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+35, "_s", 2))		if (memcmp(BuiltinName.data()+18, "_w_ph", 5))
	break;		break;
	switch (BuiltinName[37]) {		return Intrinsic::mips_dpa_w_ph; // "__builtin_mips_dpa_w_ph
	default: break;		"
	case '0': // 1 string to match.		case 's': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_acc_sat_lh_s0; // "__built		if (memcmp(BuiltinName.data()+18, "_w_ph", 5))
	in_HEXAGON_M2_mpy_acc_sat_lh_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_acc_sat_lh_s1; // "__built
	in_HEXAGON_M2_mpy_acc_sat_lh_s1"
	}
	break;
	case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+35, "_s", 2))
	break;		break;
	switch (BuiltinName[37]) {		return Intrinsic::mips_dps_w_ph; // "__builtin_mips_dps_w_ph
	default: break;		"
	case '0': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_acc_sat_ll_s0; // "__built
	in_HEXAGON_M2_mpy_acc_sat_ll_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_acc_sat_ll_s1; // "__built
	in_HEXAGON_M2_mpy_acc_sat_ll_s1"
	}
	break;
	}		}
	break;		break;
	}		case 'e': // 2 strings to match.
	break;		if (memcmp(BuiltinName.data()+16, "xtr_", 4))
	case 'n': // 8 strings to match.		break;
	if (memcmp(BuiltinName.data()+26, "ac_sat_", 7))		switch (BuiltinName[20]) {
	break;
	switch (BuiltinName[33]) {
	default: break;
	case 'h': // 4 strings to match.
	switch (BuiltinName[34]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+35, "_s", 2))		if (memcmp(BuiltinName.data()+21, "_w", 2))
	break;		break;
	switch (BuiltinName[37]) {		return Intrinsic::mips_extr_r_w; // "__builtin_mips_extr_r_w
	default: break;		"
	case '0': // 1 string to match.		case 's': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_nac_sat_hh_s0; // "__built		if (memcmp(BuiltinName.data()+21, "_h", 2))
	in_HEXAGON_M2_mpy_nac_sat_hh_s0"
	case '1': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_nac_sat_hh_s1; // "__built
	in_HEXAGON_M2_mpy_nac_sat_hh_s1"
	}
	break;
	case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+35, "_s", 2))
	break;		break;
	switch (BuiltinName[37]) {		return Intrinsic::mips_extr_s_h; // "__builtin_mips_extr_s_h
	default: break;		"
	case '0': // 1 string to match.		}
	return Intrinsic::hexagon_M2_mpy_nac_sat_hl_s0; // "__built		break;
	in_HEXAGON_M2_mpy_nac_sat_hl_s0"		case 'm': // 2 strings to match.
	case '1': // 1 string to match.		if (memcmp(BuiltinName.data()+16, "ul", 2))
	return Intrinsic::hexagon_M2_mpy_nac_sat_hl_s1; // "__built
	in_HEXAGON_M2_mpy_nac_sat_hl_s1"
	}
	break;		break;
			switch (BuiltinName[18]) {
			default: break;
			case '_': // 1 string to match.
			if (memcmp(BuiltinName.data()+19, "s_ph", 4))
			break;
			return Intrinsic::mips_mul_s_ph; // "__builtin_mips_mul_s_ph
			"
			case 'q': // 1 string to match.
			if (memcmp(BuiltinName.data()+19, "_s_w", 4))
			break;
			return Intrinsic::mips_mulq_s_w; // "__builtin_mips_mulq_s_w
			"
	}		}
	break;		break;
	case 'l': // 4 strings to match.		case 's': // 5 strings to match.
	switch (BuiltinName[34]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+35, "_s", 2))		switch (BuiltinName[17]) {
	break;
	switch (BuiltinName[37]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'l': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_nac_sat_lh_s0; // "__built		if (memcmp(BuiltinName.data()+18, "l_s_w", 5))
	in_HEXAGON_M2_mpy_nac_sat_lh_s0"		break;
	case '1': // 1 string to match.		return Intrinsic::mips_shll_s_w; // "__builtin_mips_shll_s_w
	return Intrinsic::hexagon_M2_mpy_nac_sat_lh_s1; // "__built		"
	in_HEXAGON_M2_mpy_nac_sat_lh_s1"		case 'r': // 1 string to match.
			if (memcmp(BuiltinName.data()+18, "a_r_w", 5))
			break;
			return Intrinsic::mips_shra_r_w; // "__builtin_mips_shra_r_w
			"
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'u': // 3 strings to match.
	if (memcmp(BuiltinName.data()+35, "_s", 2))		if (BuiltinName[17] != 'b')
	break;		break;
	switch (BuiltinName[37]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 'q': // 2 strings to match.
	return Intrinsic::hexagon_M2_mpy_nac_sat_ll_s0; // "__built		switch (BuiltinName[19]) {
	in_HEXAGON_M2_mpy_nac_sat_ll_s0"		default: break;
	case '1': // 1 string to match.		case '_': // 1 string to match.
	return Intrinsic::hexagon_M2_mpy_nac_sat_ll_s1; // "__built		if (memcmp(BuiltinName.data()+20, "s_w", 3))
	in_HEXAGON_M2_mpy_nac_sat_ll_s1"		break;
			return Intrinsic::mips_subq_s_w; // "__builtin_mips_subq_s_w
			"
			case 'h': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "_ph", 3))
			break;
			return Intrinsic::mips_subqh_ph; // "__builtin_mips_subqh_ph
			"
			}
			break;
			case 'u': // 1 string to match.
			if (memcmp(BuiltinName.data()+19, "h_qb", 4))
			break;
			return Intrinsic::mips_subuh_qb; // "__builtin_mips_subuh_qb
			"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 's': // 8 strings to match.		case 's': // 24 strings to match.
	if (memcmp(BuiltinName.data()+26, "at_rnd_", 7))		if (memcmp(BuiltinName.data()+12, "a_", 2))
	break;		break;
	switch (BuiltinName[33]) {		switch (BuiltinName[14]) {
	default: break;		default: break;
	case 'h': // 4 strings to match.		case 'd': // 12 strings to match.
	switch (BuiltinName[34]) {		if (BuiltinName[15] != 'p')
			break;
			switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'a': // 6 strings to match.
	if (memcmp(BuiltinName.data()+35, "_s", 2))		if (memcmp(BuiltinName.data()+17, "dd_", 3))
	break;		break;
	switch (BuiltinName[37]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 's': // 3 strings to match.
	return Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s0; // "__built		if (BuiltinName[21] != '_')
	in_HEXAGON_M2_mpy_sat_rnd_hh_s0"		break;
	case '1': // 1 string to match.		switch (BuiltinName[22]) {
	return Intrinsic::hexagon_M2_mpy_sat_rnd_hh_s1; // "__built		default: break;
	in_HEXAGON_M2_mpy_sat_rnd_hh_s1"		case 'd': // 1 string to match.
			return Intrinsic::mips_dpadd_s_d; // "__builtin_msa_d
			padd_s_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_dpadd_s_h; // "__builtin_msa_d
			padd_s_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_dpadd_s_w; // "__builtin_msa_d
			padd_s_w"
			}
			break;
			case 'u': // 3 strings to match.
			if (BuiltinName[21] != '_')
			break;
			switch (BuiltinName[22]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_dpadd_u_d; // "__builtin_msa_d
			padd_u_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_dpadd_u_h; // "__builtin_msa_d
			padd_u_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_dpadd_u_w; // "__builtin_msa_d
			padd_u_w"
			}
			break;
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 's': // 6 strings to match.
	if (memcmp(BuiltinName.data()+35, "_s", 2))		if (memcmp(BuiltinName.data()+17, "ub_", 3))
	break;		break;
	switch (BuiltinName[37]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 's': // 3 strings to match.
	return Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s0; // "__built		if (BuiltinName[21] != '_')
	in_HEXAGON_M2_mpy_sat_rnd_hl_s0"		break;
	case '1': // 1 string to match.		switch (BuiltinName[22]) {
	return Intrinsic::hexagon_M2_mpy_sat_rnd_hl_s1; // "__built		default: break;
	in_HEXAGON_M2_mpy_sat_rnd_hl_s1"		case 'd': // 1 string to match.
			return Intrinsic::mips_dpsub_s_d; // "__builtin_msa_d
			psub_s_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_dpsub_s_h; // "__builtin_msa_d
			psub_s_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_dpsub_s_w; // "__builtin_msa_d
			psub_s_w"
			}
			break;
			case 'u': // 3 strings to match.
			if (BuiltinName[21] != '_')
			break;
			switch (BuiltinName[22]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_dpsub_u_d; // "__builtin_msa_d
			psub_u_d"
			case 'h': // 1 string to match.
			return Intrinsic::mips_dpsub_u_h; // "__builtin_msa_d
			psub_u_h"
			case 'w': // 1 string to match.
			return Intrinsic::mips_dpsub_u_w; // "__builtin_msa_d
			psub_u_w"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'l': // 4 strings to match.		case 'f': // 8 strings to match.
	switch (BuiltinName[34]) {		switch (BuiltinName[15]) {
	default: break;		default: break;
	case 'h': // 2 strings to match.		case 'f': // 4 strings to match.
	if (memcmp(BuiltinName.data()+35, "_s", 2))		if (memcmp(BuiltinName.data()+16, "int_", 4))
	break;		break;
	switch (BuiltinName[37]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 's': // 2 strings to match.
	return Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s0; // "__built		if (BuiltinName[21] != '_')
	in_HEXAGON_M2_mpy_sat_rnd_lh_s0"		break;
	case '1': // 1 string to match.		switch (BuiltinName[22]) {
	return Intrinsic::hexagon_M2_mpy_sat_rnd_lh_s1; // "__built		default: break;
	in_HEXAGON_M2_mpy_sat_rnd_lh_s1"		case 'd': // 1 string to match.
			return Intrinsic::mips_ffint_s_d; // "__builtin_msa_f
			fint_s_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ffint_s_w; // "__builtin_msa_f
			fint_s_w"
			}
			break;
			case 'u': // 2 strings to match.
			if (BuiltinName[21] != '_')
			break;
			switch (BuiltinName[22]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_ffint_u_d; // "__builtin_msa_f
			fint_u_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ffint_u_w; // "__builtin_msa_f
			fint_u_w"
			}
			break;
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 't': // 4 strings to match.
	if (memcmp(BuiltinName.data()+35, "_s", 2))		if (memcmp(BuiltinName.data()+16, "int_", 4))
	break;		break;
	switch (BuiltinName[37]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case '0': // 1 string to match.		case 's': // 2 strings to match.
	return Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s0; // "__built		if (BuiltinName[21] != '_')
	in_HEXAGON_M2_mpy_sat_rnd_ll_s0"		break;
	case '1': // 1 string to match.		switch (BuiltinName[22]) {
	return Intrinsic::hexagon_M2_mpy_sat_rnd_ll_s1; // "__built		default: break;
	in_HEXAGON_M2_mpy_sat_rnd_ll_s1"		case 'd': // 1 string to match.
	}		return Intrinsic::mips_ftint_s_d; // "__builtin_msa_f
	break;		tint_s_d"
	}		case 'w': // 1 string to match.
	break;		return Intrinsic::mips_ftint_s_w; // "__builtin_msa_f
	}		tint_s_w"
	break;		}
	}
	break;
	case 40: // 1 string to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_S5_vasrhrnd_goodsyn
	tax", 40))
	break;
	return Intrinsic::hexagon_S5_vasrhrnd_goodsyntax; // "__builtin_HEXAG
	ON_S5_vasrhrnd_goodsyntax"
	case 41: // 4 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_S2_tableidx", 29))
	break;
	switch (BuiltinName[29]) {
	default: break;
	case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "_goodsyntax", 11))
	break;
	return Intrinsic::hexagon_S2_tableidxb_goodsyntax; // "__built
	in_HEXAGON_S2_tableidxb_goodsyntax"
	case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "_goodsyntax", 11))
	break;
	return Intrinsic::hexagon_S2_tableidxd_goodsyntax; // "__built
	in_HEXAGON_S2_tableidxd_goodsyntax"
	case 'h': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "_goodsyntax", 11))
	break;
	return Intrinsic::hexagon_S2_tableidxh_goodsyntax; // "__built
	in_HEXAGON_S2_tableidxh_goodsyntax"
	case 'w': // 1 string to match.
	if (memcmp(BuiltinName.data()+30, "_goodsyntax", 11))
	break;
	return Intrinsic::hexagon_S2_tableidxw_goodsyntax; // "__built
	in_HEXAGON_S2_tableidxw_goodsyntax"
	}
	break;
	case 43: // 2 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_S2_asr_i_", 27))
	break;
	switch (BuiltinName[27]) {
	default: break;
	case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "_rnd_goodsyntax", 15))
	break;
	return Intrinsic::hexagon_S2_asr_i_p_rnd_goodsyntax; // "__built
	in_HEXAGON_S2_asr_i_p_rnd_goodsyntax"
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "_rnd_goodsyntax", 15))
	break;
	return Intrinsic::hexagon_S2_asr_i_r_rnd_goodsyntax; // "__built
	in_HEXAGON_S2_asr_i_r_rnd_goodsyntax"
	}
	break;
	case 46: // 1 string to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_HEXAGON_S5_asrhub_rnd_sat_g
	oodsyntax", 46))
	break;
	return Intrinsic::hexagon_S5_asrhub_rnd_sat_goodsyntax; // "__built
	in_HEXAGON_S5_asrhub_rnd_sat_goodsyntax"
	}
	}
	if (TargetPrefix == "mips") {
	switch (BuiltinName.size()) {
	default: break;
	case 18: // 2 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_mips_l", 16))
	break;
	switch (BuiltinName[16]) {
	default: break;
	case 'h': // 1 string to match.
	if (BuiltinName[17] != 'x')
	break;
	return Intrinsic::mips_lhx; // "__builtin_mips_lhx"
	case 'w': // 1 string to match.
	if (BuiltinName[17] != 'x')
	break;
	return Intrinsic::mips_lwx; // "__builtin_mips_lwx"
	}
	break;
	case 19: // 6 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_mips_", 15))
	break;
	switch (BuiltinName[15]) {
	default: break;
	case 'e': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "xtp", 3))
	break;
	return Intrinsic::mips_extp; // "__builtin_mips_extp"
	case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "nsv", 3))
	break;
	return Intrinsic::mips_insv; // "__builtin_mips_insv"
	case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "bux", 3))
	break;
	return Intrinsic::mips_lbux; // "__builtin_mips_lbux"
	case 'm': // 3 strings to match.
	switch (BuiltinName[16]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+17, "dd", 2))
	break;
	return Intrinsic::mips_madd; // "__builtin_mips_madd"
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+17, "ub", 2))
	break;
	return Intrinsic::mips_msub; // "__builtin_mips_msub"
	case 'u': // 1 string to match.
	if (memcmp(BuiltinName.data()+17, "lt", 2))
	break;
	return Intrinsic::mips_mult; // "__builtin_mips_mult"
	}
	break;
	}
	break;
	case 20: // 8 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_mips_", 15))
	break;
	switch (BuiltinName[15]) {
	default: break;
	case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+16, "dd", 2))
	break;
	switch (BuiltinName[18]) {
	default: break;
	case 's': // 1 string to match.
	if (BuiltinName[19] != 'c')
	break;
	return Intrinsic::mips_addsc; // "__builtin_mips_addsc"
	case 'w': // 1 string to match.
	if (BuiltinName[19] != 'c')
	break;
	return Intrinsic::mips_addwc; // "__builtin_mips_addwc"
	}
	break;
	case 'm': // 3 strings to match.
	switch (BuiltinName[16]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+17, "ddu", 3))
	break;
	return Intrinsic::mips_maddu; // "__builtin_mips_maddu"
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+17, "ubu", 3))
	break;
	return Intrinsic::mips_msubu; // "__builtin_mips_msubu"
	case 'u': // 1 string to match.
	if (memcmp(BuiltinName.data()+17, "ltu", 3))
	break;
	return Intrinsic::mips_multu; // "__builtin_mips_multu"
	}
	break;
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "ddsp", 4))
	break;
	return Intrinsic::mips_rddsp; // "__builtin_mips_rddsp"
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "hilo", 4))
	break;
	return Intrinsic::mips_shilo; // "__builtin_mips_shilo"
	case 'w': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "rdsp", 4))
	break;
	return Intrinsic::mips_wrdsp; // "__builtin_mips_wrdsp"
	}
	break;
	case 21: // 8 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_mips_", 15))
	break;
	switch (BuiltinName[15]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "ppend", 5))
	break;
	return Intrinsic::mips_append; // "__builtin_mips_append"
	case 'b': // 2 strings to match.
	switch (BuiltinName[16]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+17, "lign", 4))
	break;
	return Intrinsic::mips_balign; // "__builtin_mips_balign"
	case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+17, "trev", 4))
	break;
	return Intrinsic::mips_bitrev; // "__builtin_mips_bitrev"
	}
	break;
	case 'e': // 2 strings to match.
	if (memcmp(BuiltinName.data()+16, "xt", 2))
	break;
	switch (BuiltinName[18]) {
	default: break;
	case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+19, "dp", 2))
	break;
	return Intrinsic::mips_extpdp; // "__builtin_mips_extpdp"
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+19, "_w", 2))
	break;
	return Intrinsic::mips_extr_w; // "__builtin_mips_extr_w"
	}
	break;
	case 'm': // 3 strings to match.
	switch (BuiltinName[16]) {
	default: break;
	case 'o': // 1 string to match.
	if (memcmp(BuiltinName.data()+17, "dsub", 4))
	break;
	return Intrinsic::mips_modsub; // "__builtin_mips_modsub"
	case 't': // 1 string to match.
	if (memcmp(BuiltinName.data()+17, "hlip", 4))
	break;
	return Intrinsic::mips_mthlip; // "__builtin_mips_mthlip"
	case 'u': // 1 string to match.
	if (memcmp(BuiltinName.data()+17, "l_ph", 4))
	break;
	return Intrinsic::mips_mul_ph; // "__builtin_mips_mul_ph"
	}
	break;
	}
	break;
	case 22: // 19 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_mips_", 15))
	break;
	switch (BuiltinName[15]) {
	default: break;
	case 'a': // 4 strings to match.
	if (memcmp(BuiltinName.data()+16, "dd", 2))
	break;
	switch (BuiltinName[18]) {
	default: break;
	case 'q': // 2 strings to match.
	switch (BuiltinName[19]) {
	default: break;
	case '_': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "ph", 2))
	break;		break;
	return Intrinsic::mips_addq_ph; // "__builtin_mips_addq_ph"		case 'u': // 2 strings to match.
	case 'h': // 1 string to match.		if (BuiltinName[21] != '_')
	if (memcmp(BuiltinName.data()+20, "_w", 2))		break;
			switch (BuiltinName[22]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::mips_ftint_u_d; // "__builtin_msa_f
			tint_u_d"
			case 'w': // 1 string to match.
			return Intrinsic::mips_ftint_u_w; // "__builtin_msa_f
			tint_u_w"
			}
	break;		break;
	return Intrinsic::mips_addqh_w; // "__builtin_mips_addqh_w"		}
	}
	break;
	case 'u': // 2 strings to match.
	if (BuiltinName[19] != '_')
	break;		break;
	switch (BuiltinName[20]) {
	default: break;
	case 'p': // 1 string to match.
	if (BuiltinName[21] != 'h')
	break;
	return Intrinsic::mips_addu_ph; // "__builtin_mips_addu_ph"
	case 'q': // 1 string to match.
	if (BuiltinName[21] != 'b')
	break;
	return Intrinsic::mips_addu_qb; // "__builtin_mips_addu_qb"
	}		}
	break;		break;
	}		case 'm': // 4 strings to match.
	break;		switch (BuiltinName[15]) {
	case 'p': // 3 strings to match.
	switch (BuiltinName[16]) {
	default: break;
	case 'i': // 2 strings to match.
	if (memcmp(BuiltinName.data()+17, "ck_", 3))
	break;
	switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'a': // 2 strings to match.
	if (BuiltinName[21] != 'h')		if (memcmp(BuiltinName.data()+16, "ddr_q_", 6))
	break;		break;
	return Intrinsic::mips_pick_ph; // "__builtin_mips_pick_ph"		switch (BuiltinName[22]) {
	case 'q': // 1 string to match.		default: break;
	if (BuiltinName[21] != 'b')		case 'h': // 1 string to match.
			return Intrinsic::mips_maddr_q_h; // "__builtin_msa_maddr_q_h
			"
			case 'w': // 1 string to match.
			return Intrinsic::mips_maddr_q_w; // "__builtin_msa_maddr_q_w
			"
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(BuiltinName.data()+16, "ubr_q_", 6))
	break;		break;
	return Intrinsic::mips_pick_qb; // "__builtin_mips_pick_qb"		switch (BuiltinName[22]) {
			default: break;
			case 'h': // 1 string to match.
			return Intrinsic::mips_msubr_q_h; // "__builtin_msa_msubr_q_h
			"
			case 'w': // 1 string to match.
			return Intrinsic::mips_msubr_q_w; // "__builtin_msa_msubr_q_w
			"
			}
			break;
	}		}
	break;		break;
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+17, "epend", 5))
	break;
	return Intrinsic::mips_prepend; // "__builtin_mips_prepend"
	}		}
	break;		break;
	case 'r': // 2 strings to match.		}
	if (memcmp(BuiltinName.data()+16, "epl_", 4))		break;
	break;		case 24: // 34 strings to match.
	switch (BuiltinName[20]) {		if (memcmp(BuiltinName.data()+0, "__builtin_m", 11))
	default: break;
	case 'p': // 1 string to match.
	if (BuiltinName[21] != 'h')
	break;
	return Intrinsic::mips_repl_ph; // "__builtin_mips_repl_ph"
	case 'q': // 1 string to match.
	if (BuiltinName[21] != 'b')
	break;
	return Intrinsic::mips_repl_qb; // "__builtin_mips_repl_qb"
	}
	break;		break;
	case 's': // 10 strings to match.		switch (BuiltinName[11]) {
	switch (BuiltinName[16]) {		default: break;
			case 'i': // 22 strings to match.
			if (memcmp(BuiltinName.data()+12, "ps_", 3))
			break;
			switch (BuiltinName[15]) {
	default: break;		default: break;
	case 'h': // 6 strings to match.		case 'a': // 6 strings to match.
	switch (BuiltinName[17]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'l': // 2 strings to match.		case 'b': // 2 strings to match.
	if (memcmp(BuiltinName.data()+18, "l_", 2))		if (memcmp(BuiltinName.data()+17, "sq_s_", 5))
	break;		break;
	switch (BuiltinName[20]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'p': // 1 string to match.
	if (BuiltinName[21] != 'h')		if (BuiltinName[23] != 'h')
	break;		break;
	return Intrinsic::mips_shll_ph; // "__builtin_mips_shll_ph"		return Intrinsic::mips_absq_s_ph; // "__builtin_mips_absq_s_p h"
	case 'q': // 1 string to match.		case 'q': // 1 string to match.
	if (BuiltinName[21] != 'b')		if (BuiltinName[23] != 'b')
	break;		break;
	return Intrinsic::mips_shll_qb; // "__builtin_mips_shll_qb"		return Intrinsic::mips_absq_s_qb; // "__builtin_mips_absq_s_q b"
	}		}
	break;		break;
	case 'r': // 4 strings to match.		case 'd': // 4 strings to match.
			if (BuiltinName[17] != 'd')
			break;
	switch (BuiltinName[18]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'q': // 2 strings to match.
	if (BuiltinName[19] != '_')		switch (BuiltinName[19]) {
	break;
	switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case '_': // 1 string to match.
	if (BuiltinName[21] != 'h')		if (memcmp(BuiltinName.data()+20, "s_ph", 4))
	break;		break;
	return Intrinsic::mips_shra_ph; // "__builtin_mips_shra_ph"		return Intrinsic::mips_addq_s_ph; // "__builtin_mips_
	case 'q': // 1 string to match.		addq_s_ph"
	if (BuiltinName[21] != 'b')		case 'h': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "_r_w", 4))
	break;		break;
	return Intrinsic::mips_shra_qb; // "__builtin_mips_shra_qb"		return Intrinsic::mips_addqh_r_w; // "__builtin_mips_ addqh_r_w"
	}		}
	break;		break;
	case 'l': // 2 strings to match.		case 'u': // 2 strings to match.
	if (BuiltinName[19] != '_')		if (memcmp(BuiltinName.data()+19, "_s_", 3))
	break;		break;
	switch (BuiltinName[20]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'p': // 1 string to match.
	if (BuiltinName[21] != 'h')		if (BuiltinName[23] != 'h')
	break;		break;
	return Intrinsic::mips_shrl_ph; // "__builtin_mips_shrl_ph"		return Intrinsic::mips_addu_s_ph; // "__builtin_mips_ addu_s_ph"
	case 'q': // 1 string to match.		case 'q': // 1 string to match.
	if (BuiltinName[21] != 'b')		if (BuiltinName[23] != 'b')
	break;		break;
	return Intrinsic::mips_shrl_qb; // "__builtin_mips_shrl_qb"		return Intrinsic::mips_addu_s_qb; // "__builtin_mips_ addu_s_qb"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'u': // 4 strings to match.		case 'c': // 3 strings to match.
	if (BuiltinName[17] != 'b')		if (memcmp(BuiltinName.data()+16, "mp_", 3))
	break;		break;
	switch (BuiltinName[18]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'q': // 2 strings to match.		case 'e': // 1 string to match.
	switch (BuiltinName[19]) {		if (memcmp(BuiltinName.data()+20, "q_ph", 4))
	default: break;
	case '_': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "ph", 2))
	break;
	return Intrinsic::mips_subq_ph; // "__builtin_mips_subq_ph"
	case 'h': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "_w", 2))
	break;
	return Intrinsic::mips_subqh_w; // "__builtin_mips_subqh_w"
	}
	break;
	case 'u': // 2 strings to match.
	if (BuiltinName[19] != '_')
	break;		break;
			return Intrinsic::mips_cmp_eq_ph; // "__builtin_mips_cmp_eq_p
			h"
			case 'l': // 2 strings to match.
	switch (BuiltinName[20]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'e': // 1 string to match.
	if (BuiltinName[21] != 'h')		if (memcmp(BuiltinName.data()+21, "_ph", 3))
	break;
	return Intrinsic::mips_subu_ph; // "__builtin_mips_subu_ph"
	case 'q': // 1 string to match.
	if (BuiltinName[21] != 'b')
	break;
	return Intrinsic::mips_subu_qb; // "__builtin_mips_subu_qb"
	}
	break;
	}
	break;
	}
	break;
	}
	break;
	case 23: // 16 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_mips_", 15))
	break;
	switch (BuiltinName[15]) {
	default: break;
	case 'a': // 4 strings to match.
	switch (BuiltinName[16]) {
	default: break;
	case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+17, "sq_s_w", 6))
	break;
	return Intrinsic::mips_absq_s_w; // "__builtin_mips_absq_s_w
	"
	case 'd': // 3 strings to match.
	if (BuiltinName[17] != 'd')
	break;
	switch (BuiltinName[18]) {
	default: break;
	case 'q': // 2 strings to match.
	switch (BuiltinName[19]) {
	default: break;
	case '_': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "s_w", 3))
	break;		break;
	return Intrinsic::mips_addq_s_w; // "__builtin_mips_addq_s_w		return Intrinsic::mips_cmp_le_ph; // "__builtin_mips_cmp_le_p
	"		h"
	case 'h': // 1 string to match.		case 't': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "_ph", 3))		if (memcmp(BuiltinName.data()+21, "_ph", 3))
	break;		break;
	return Intrinsic::mips_addqh_ph; // "__builtin_mips_addqh_ph "		return Intrinsic::mips_cmp_lt_ph; // "__builtin_mips_cmp_lt_p h"
	}		}
	break;		break;
	case 'u': // 1 string to match.
	if (memcmp(BuiltinName.data()+19, "h_qb", 4))
	break;
	return Intrinsic::mips_adduh_qb; // "__builtin_mips_adduh_qb
	"
	}		}
	break;		break;
	}		case 'd': // 2 strings to match.
	break;		if (BuiltinName[16] != 'p')
	case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "posge32", 7))
	break;
	return Intrinsic::mips_bposge32; // "__builtin_mips_bposge32"
	case 'd': // 2 strings to match.
	if (BuiltinName[16] != 'p')
	break;
	switch (BuiltinName[17]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+18, "_w_ph", 5))
	break;
	return Intrinsic::mips_dpa_w_ph; // "__builtin_mips_dpa_w_ph
	"
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+18, "_w_ph", 5))
	break;
	return Intrinsic::mips_dps_w_ph; // "__builtin_mips_dps_w_ph
	"
	}
	break;
	case 'e': // 2 strings to match.
	if (memcmp(BuiltinName.data()+16, "xtr_", 4))
	break;
	switch (BuiltinName[20]) {
	default: break;
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+21, "_w", 2))
	break;
	return Intrinsic::mips_extr_r_w; // "__builtin_mips_extr_r_w
	"
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+21, "_h", 2))
	break;
	return Intrinsic::mips_extr_s_h; // "__builtin_mips_extr_s_h
	"
	}
	break;
	case 'm': // 2 strings to match.
	if (memcmp(BuiltinName.data()+16, "ul", 2))
	break;
	switch (BuiltinName[18]) {
	default: break;
	case '_': // 1 string to match.
	if (memcmp(BuiltinName.data()+19, "s_ph", 4))
	break;
	return Intrinsic::mips_mul_s_ph; // "__builtin_mips_mul_s_ph
	"
	case 'q': // 1 string to match.
	if (memcmp(BuiltinName.data()+19, "_s_w", 4))
	break;		break;
	return Intrinsic::mips_mulq_s_w; // "__builtin_mips_mulq_s_w
	"
	}
	break;
	case 's': // 5 strings to match.
	switch (BuiltinName[16]) {
	default: break;
	case 'h': // 2 strings to match.
	switch (BuiltinName[17]) {		switch (BuiltinName[17]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+18, "l_s_w", 5))		if (memcmp(BuiltinName.data()+18, "x_w_ph", 6))
	break;		break;
	return Intrinsic::mips_shll_s_w; // "__builtin_mips_shll_s_w		return Intrinsic::mips_dpax_w_ph; // "__builtin_mips_dpax_w_p
	"		h"
	case 'r': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+18, "a_r_w", 5))		if (memcmp(BuiltinName.data()+18, "x_w_ph", 6))
	break;		break;
	return Intrinsic::mips_shra_r_w; // "__builtin_mips_shra_r_w "		return Intrinsic::mips_dpsx_w_ph; // "__builtin_mips_dpsx_w_p h"
	}		}
	break;		break;
	case 'u': // 3 strings to match.		case 'e': // 1 string to match.
	if (BuiltinName[17] != 'b')		if (memcmp(BuiltinName.data()+16, "xtr_rs_w", 8))
	break;
	switch (BuiltinName[18]) {
	default: break;
	case 'q': // 2 strings to match.
	switch (BuiltinName[19]) {
	default: break;
	case '_': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "s_w", 3))
	break;
	return Intrinsic::mips_subq_s_w; // "__builtin_mips_subq_s_w
	"
	case 'h': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "_ph", 3))
	break;
	return Intrinsic::mips_subqh_ph; // "__builtin_mips_subqh_ph
	"
	}
	break;		break;
	case 'u': // 1 string to match.		return Intrinsic::mips_extr_rs_w; // "__builtin_mips_extr_rs_
	if (memcmp(BuiltinName.data()+19, "h_qb", 4))		w"
	break;		case 'm': // 2 strings to match.
	return Intrinsic::mips_subuh_qb; // "__builtin_mips_subuh_qb		if (memcmp(BuiltinName.data()+16, "ulq_", 4))
	"
	}
	break;
	}
	break;
	}
	break;
	case 24: // 22 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_mips_", 15))
	break;
	switch (BuiltinName[15]) {
	default: break;
	case 'a': // 6 strings to match.
	switch (BuiltinName[16]) {
	default: break;
	case 'b': // 2 strings to match.
	if (memcmp(BuiltinName.data()+17, "sq_s_", 5))
	break;		break;
	switch (BuiltinName[22]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'r': // 1 string to match.
	if (BuiltinName[23] != 'h')		if (memcmp(BuiltinName.data()+21, "s_w", 3))
	break;		break;
	return Intrinsic::mips_absq_s_ph; // "__builtin_mips_absq_s_p		return Intrinsic::mips_mulq_rs_w; // "__builtin_mips_mulq_rs_
	h"		w"
	case 'q': // 1 string to match.		case 's': // 1 string to match.
	if (BuiltinName[23] != 'b')		if (memcmp(BuiltinName.data()+21, "_ph", 3))
	break;		break;
	return Intrinsic::mips_absq_s_qb; // "__builtin_mips_absq_s_q b"		return Intrinsic::mips_mulq_s_ph; // "__builtin_mips_mulq_s_p h"
	}		}
	break;		break;
	case 'd': // 4 strings to match.		case 'p': // 1 string to match.
	if (BuiltinName[17] != 'd')		if (memcmp(BuiltinName.data()+16, "ackrl_ph", 8))
	break;		break;
	switch (BuiltinName[18]) {		return Intrinsic::mips_packrl_ph; // "__builtin_mips_packrl_p
			h"
			case 's': // 7 strings to match.
			switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'q': // 2 strings to match.		case 'h': // 3 strings to match.
	switch (BuiltinName[19]) {		switch (BuiltinName[17]) {
	default: break;		default: break;
	case '_': // 1 string to match.		case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "s_ph", 4))		if (memcmp(BuiltinName.data()+18, "l_s_ph", 6))
	break;		break;
	return Intrinsic::mips_addq_s_ph; // "__builtin_mips_addq_s_p		return Intrinsic::mips_shll_s_ph; // "__builtin_mips_shll_s_p
	h"		h"
	case 'h': // 1 string to match.		case 'r': // 2 strings to match.
	if (memcmp(BuiltinName.data()+20, "_r_w", 4))		if (memcmp(BuiltinName.data()+18, "a_r_", 4))
	break;		break;
	return Intrinsic::mips_addqh_r_w; // "__builtin_mips_addqh_r_		switch (BuiltinName[22]) {
	w"		default: break;
			case 'p': // 1 string to match.
			if (BuiltinName[23] != 'h')
			break;
			return Intrinsic::mips_shra_r_ph; // "__builtin_mips_
			shra_r_ph"
			case 'q': // 1 string to match.
			if (BuiltinName[23] != 'b')
			break;
			return Intrinsic::mips_shra_r_qb; // "__builtin_mips_
			shra_r_qb"
			}
			break;
	}		}
	break;		break;
	case 'u': // 2 strings to match.		case 'u': // 4 strings to match.
	if (memcmp(BuiltinName.data()+19, "_s_", 3))		if (BuiltinName[17] != 'b')
	break;		break;
	switch (BuiltinName[22]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'q': // 2 strings to match.
	if (BuiltinName[23] != 'h')		switch (BuiltinName[19]) {
	break;		default: break;
	return Intrinsic::mips_addu_s_ph; // "__builtin_mips_addu_s_p		case '_': // 1 string to match.
	h"		if (memcmp(BuiltinName.data()+20, "s_ph", 4))
	case 'q': // 1 string to match.		break;
	if (BuiltinName[23] != 'b')		return Intrinsic::mips_subq_s_ph; // "__builtin_mips_
			subq_s_ph"
			case 'h': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "_r_w", 4))
			break;
			return Intrinsic::mips_subqh_r_w; // "__builtin_mips_
			subqh_r_w"
			}
			break;
			case 'u': // 2 strings to match.
			if (memcmp(BuiltinName.data()+19, "_s_", 3))
	break;		break;
	return Intrinsic::mips_addu_s_qb; // "__builtin_mips_addu_s_q		switch (BuiltinName[22]) {
	b"		default: break;
			case 'p': // 1 string to match.
			if (BuiltinName[23] != 'h')
			break;
			return Intrinsic::mips_subu_s_ph; // "__builtin_mips_
			subu_s_ph"
			case 'q': // 1 string to match.
			if (BuiltinName[23] != 'b')
			break;
			return Intrinsic::mips_subu_s_qb; // "__builtin_mips_
			subu_s_qb"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'c': // 3 strings to match.		case 's': // 12 strings to match.
	if (memcmp(BuiltinName.data()+16, "mp_", 3))		if (memcmp(BuiltinName.data()+12, "a_", 2))
	break;		break;
	switch (BuiltinName[19]) {		switch (BuiltinName[14]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'f': // 4 strings to match.
	if (memcmp(BuiltinName.data()+20, "q_ph", 4))		if (memcmp(BuiltinName.data()+15, "trunc_", 6))
	break;		break;
	return Intrinsic::mips_cmp_eq_ph; // "__builtin_mips_cmp_eq_p		switch (BuiltinName[21]) {
	h"
	case 'l': // 2 strings to match.
	switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 's': // 2 strings to match.
	if (memcmp(BuiltinName.data()+21, "_ph", 3))		if (BuiltinName[22] != '_')
	break;
	return Intrinsic::mips_cmp_le_ph; // "__builtin_mips_cmp_le_p
	h"
	case 't': // 1 string to match.
	if (memcmp(BuiltinName.data()+21, "_ph", 3))
	break;		break;
	return Intrinsic::mips_cmp_lt_ph; // "__builtin_mips_cmp_lt_p		switch (BuiltinName[23]) {
	h"		default: break;
	}		case 'd': // 1 string to match.
	break;		return Intrinsic::mips_ftrunc_s_d; // "__builtin_msa_ftrunc_s_
	}		d"
	break;		case 'w': // 1 string to match.
	case 'd': // 2 strings to match.		return Intrinsic::mips_ftrunc_s_w; // "__builtin_msa_ftrunc_s_
	if (BuiltinName[16] != 'p')		w"
	break;		}
	switch (BuiltinName[17]) {
	default: break;
	case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+18, "x_w_ph", 6))
	break;
	return Intrinsic::mips_dpax_w_ph; // "__builtin_mips_dpax_w_p
	h"
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+18, "x_w_ph", 6))
	break;
	return Intrinsic::mips_dpsx_w_ph; // "__builtin_mips_dpsx_w_p
	h"
	}
	break;
	case 'e': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "xtr_rs_w", 8))
	break;
	return Intrinsic::mips_extr_rs_w; // "__builtin_mips_extr_rs_
	w"
	case 'm': // 2 strings to match.
	if (memcmp(BuiltinName.data()+16, "ulq_", 4))
	break;
	switch (BuiltinName[20]) {
	default: break;
	case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+21, "s_w", 3))
	break;
	return Intrinsic::mips_mulq_rs_w; // "__builtin_mips_mulq_rs_
	w"
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+21, "_ph", 3))
	break;		break;
	return Intrinsic::mips_mulq_s_ph; // "__builtin_mips_mulq_s_p		case 'u': // 2 strings to match.
	h"		if (BuiltinName[22] != '_')
	}
	break;
	case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "ackrl_ph", 8))
	break;
	return Intrinsic::mips_packrl_ph; // "__builtin_mips_packrl_p
	h"
	case 's': // 7 strings to match.
	switch (BuiltinName[16]) {
	default: break;
	case 'h': // 3 strings to match.
	switch (BuiltinName[17]) {
	default: break;
	case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+18, "l_s_ph", 6))
	break;
	return Intrinsic::mips_shll_s_ph; // "__builtin_mips_shll_s_p
	h"
	case 'r': // 2 strings to match.
	if (memcmp(BuiltinName.data()+18, "a_r_", 4))
	break;		break;
	switch (BuiltinName[22]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'd': // 1 string to match.
	if (BuiltinName[23] != 'h')		return Intrinsic::mips_ftrunc_u_d; // "__builtin_msa_ftrunc_u_
	break;		d"
	return Intrinsic::mips_shra_r_ph; // "__builtin_mips_shra_r_p		case 'w': // 1 string to match.
	h"		return Intrinsic::mips_ftrunc_u_w; // "__builtin_msa_ftrunc_u_
	case 'q': // 1 string to match.		w"
	if (BuiltinName[23] != 'b')
	break;
	return Intrinsic::mips_shra_r_qb; // "__builtin_mips_shra_r_q
	b"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'u': // 4 strings to match.		case 's': // 8 strings to match.
	if (BuiltinName[17] != 'b')		if (memcmp(BuiltinName.data()+15, "ubsu", 4))
	break;		break;
	switch (BuiltinName[18]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'q': // 2 strings to match.		case 's': // 4 strings to match.
	switch (BuiltinName[19]) {		if (memcmp(BuiltinName.data()+20, "_u_", 3))
			break;
			switch (BuiltinName[23]) {
	default: break;		default: break;
	case '_': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "s_ph", 4))		return Intrinsic::mips_subsus_u_b; // "__builtin_msa_subsus_u_
	break;		b"
	return Intrinsic::mips_subq_s_ph; // "__builtin_mips_subq_s_p		case 'd': // 1 string to match.
	h"		return Intrinsic::mips_subsus_u_d; // "__builtin_msa_subsus_u_
			d"
	case 'h': // 1 string to match.		case 'h': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "_r_w", 4))		return Intrinsic::mips_subsus_u_h; // "__builtin_msa_subsus_u_
	break;		h"
	return Intrinsic::mips_subqh_r_w; // "__builtin_mips_subqh_r_		case 'w': // 1 string to match.
	w"		return Intrinsic::mips_subsus_u_w; // "__builtin_msa_subsus_u_
			w"
	}		}
	break;		break;
	case 'u': // 2 strings to match.		case 'u': // 4 strings to match.
	if (memcmp(BuiltinName.data()+19, "_s_", 3))		if (memcmp(BuiltinName.data()+20, "_s_", 3))
	break;		break;
	switch (BuiltinName[22]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'p': // 1 string to match.		case 'b': // 1 string to match.
	if (BuiltinName[23] != 'h')		return Intrinsic::mips_subsuu_s_b; // "__builtin_msa_subsuu_s_
	break;		b"
	return Intrinsic::mips_subu_s_ph; // "__builtin_mips_subu_s_p		case 'd': // 1 string to match.
	h"		return Intrinsic::mips_subsuu_s_d; // "__builtin_msa_subsuu_s_
	case 'q': // 1 string to match.		d"
	if (BuiltinName[23] != 'b')		case 'h': // 1 string to match.
	break;		return Intrinsic::mips_subsuu_s_h; // "__builtin_msa_subsuu_s_
	return Intrinsic::mips_subu_s_qb; // "__builtin_mips_subu_s_q		h"
	b"		case 'w': // 1 string to match.
			return Intrinsic::mips_subsuu_s_w; // "__builtin_msa_subsuu_s_
			w"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 25: // 14 strings to match.		case 25: // 14 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_mips_", 15))		if (memcmp(BuiltinName.data()+0, "__builtin_mips_", 15))
	skipping to change at line 38626		skipping to change at line 49581
	break;		break;
	}		}
	}		}
	if (TargetPrefix == "x86") {		if (TargetPrefix == "x86") {
	switch (BuiltinName.size()) {		switch (BuiltinName.size()) {
	default: break;		default: break;
	case 18: // 1 string to match.		case 18: // 1 string to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_ia32_por", 18))		if (memcmp(BuiltinName.data()+0, "__builtin_ia32_por", 18))
	break;		break;
	return Intrinsic::x86_mmx_por; // "__builtin_ia32_por"		return Intrinsic::x86_mmx_por; // "__builtin_ia32_por"
	case 19: // 6 strings to match.		case 19: // 7 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))		if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
	break;		break;
	switch (BuiltinName[15]) {		switch (BuiltinName[15]) {
	default: break;		default: break;
	case 'd': // 2 strings to match.		case 'd': // 2 strings to match.
	if (memcmp(BuiltinName.data()+16, "pp", 2))		if (memcmp(BuiltinName.data()+16, "pp", 2))
	break;		break;
	switch (BuiltinName[18]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_dppd; // "__builtin_ia32_dppd"		return Intrinsic::x86_sse41_dppd; // "__builtin_ia32_dppd"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	return Intrinsic::x86_sse41_dpps; // "__builtin_ia32_dpps"		return Intrinsic::x86_sse41_dpps; // "__builtin_ia32_dpps"
	}		}
	break;		break;
	case 'e': // 1 string to match.		case 'e': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "mms", 3))		if (memcmp(BuiltinName.data()+16, "mms", 3))
	break;		break;
	return Intrinsic::x86_mmx_emms; // "__builtin_ia32_emms"		return Intrinsic::x86_mmx_emms; // "__builtin_ia32_emms"
			case 'k': // 1 string to match.
			if (memcmp(BuiltinName.data()+16, "orw", 3))
			break;
			return Intrinsic::x86_kor_v16i1; // "__builtin_ia32_korw"
	case 'p': // 2 strings to match.		case 'p': // 2 strings to match.
	switch (BuiltinName[16]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+17, "nd", 2))		if (memcmp(BuiltinName.data()+17, "nd", 2))
	break;		break;
	return Intrinsic::x86_mmx_pand; // "__builtin_ia32_pand"		return Intrinsic::x86_mmx_pand; // "__builtin_ia32_pand"
	case 'x': // 1 string to match.		case 'x': // 1 string to match.
	if (memcmp(BuiltinName.data()+17, "or", 2))		if (memcmp(BuiltinName.data()+17, "or", 2))
	break;		break;
	return Intrinsic::x86_mmx_pxor; // "__builtin_ia32_pxor"		return Intrinsic::x86_mmx_pxor; // "__builtin_ia32_pxor"
	}		}
	break;		break;
	case 'x': // 1 string to match.		case 'x': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "end", 3))		if (memcmp(BuiltinName.data()+16, "end", 3))
	break;		break;
	return Intrinsic::x86_xend; // "__builtin_ia32_xend"		return Intrinsic::x86_xend; // "__builtin_ia32_xend"
	}		}
	break;		break;
	case 20: // 60 strings to match.		case 20: // 64 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))		if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
	break;		break;
	switch (BuiltinName[15]) {		switch (BuiltinName[15]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+16, "dds", 3))		if (memcmp(BuiltinName.data()+16, "dds", 3))
	break;		break;
	switch (BuiltinName[19]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	skipping to change at line 38725		skipping to change at line 49684
	}		}
	break;		break;
	case 'e': // 1 string to match.		case 'e': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "xtrq", 4))		if (memcmp(BuiltinName.data()+16, "xtrq", 4))
	break;		break;
	return Intrinsic::x86_sse4a_extrq; // "__builtin_ia32_extrq"		return Intrinsic::x86_sse4a_extrq; // "__builtin_ia32_extrq"
	case 'f': // 1 string to match.		case 'f': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "emms", 4))		if (memcmp(BuiltinName.data()+16, "emms", 4))
	break;		break;
	return Intrinsic::x86_mmx_femms; // "__builtin_ia32_femms"		return Intrinsic::x86_mmx_femms; // "__builtin_ia32_femms"
			case 'k': // 4 strings to match.
			switch (BuiltinName[16]) {
			default: break;
			case 'a': // 2 strings to match.
			switch (BuiltinName[17]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+18, "dw", 2))
			break;
			return Intrinsic::x86_kadd_v16i1; // "__builtin_ia32_kaddw"
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+18, "dw", 2))
			break;
			return Intrinsic::x86_kand_v16i1; // "__builtin_ia32_kandw"
			}
			break;
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+17, "otw", 3))
			break;
			return Intrinsic::x86_knot_v16i1; // "__builtin_ia32_knotw"
			case 'x': // 1 string to match.
			if (memcmp(BuiltinName.data()+17, "orw", 3))
			break;
			return Intrinsic::x86_kxor_v16i1; // "__builtin_ia32_kxorw"
			}
			break;
	case 'l': // 1 string to match.		case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "ddqu", 4))		if (memcmp(BuiltinName.data()+16, "ddqu", 4))
	break;		break;
	return Intrinsic::x86_sse3_ldu_dq; // "__builtin_ia32_lddqu"		return Intrinsic::x86_sse3_ldu_dq; // "__builtin_ia32_lddqu"
	case 'm': // 11 strings to match.		case 'm': // 11 strings to match.
	switch (BuiltinName[16]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'a': // 4 strings to match.		case 'a': // 4 strings to match.
	if (BuiltinName[17] != 'x')		if (BuiltinName[17] != 'x')
	break;		break;
	skipping to change at line 39007		skipping to change at line 49992
	case 's': // 1 string to match.		case 's': // 1 string to match.
	return Intrinsic::x86_sse_sub_ss; // "__builtin_ia32_subss"		return Intrinsic::x86_sse_sub_ss; // "__builtin_ia32_subss"
	}		}
	break;		break;
	case 'x': // 1 string to match.		case 'x': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "test", 4))		if (memcmp(BuiltinName.data()+16, "test", 4))
	break;		break;
	return Intrinsic::x86_xtest; // "__builtin_ia32_xtest"		return Intrinsic::x86_xtest; // "__builtin_ia32_xtest"
	}		}
	break;		break;
	case 21: // 50 strings to match.		case 21: // 52 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))		if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
	break;		break;
	switch (BuiltinName[15]) {		switch (BuiltinName[15]) {
	default: break;		default: break;
	case 'c': // 5 strings to match.		case 'c': // 5 strings to match.
	if (memcmp(BuiltinName.data()+16, "omi", 3))		if (memcmp(BuiltinName.data()+16, "omi", 3))
	break;		break;
	switch (BuiltinName[19]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'e': // 1 string to match.
	skipping to change at line 39072		skipping to change at line 50057
	switch (BuiltinName[20]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::x86_sse3_hsub_pd; // "__builtin_ia32_hsubpd"		return Intrinsic::x86_sse3_hsub_pd; // "__builtin_ia32_hsubpd"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	return Intrinsic::x86_sse3_hsub_ps; // "__builtin_ia32_hsubps"		return Intrinsic::x86_sse3_hsub_ps; // "__builtin_ia32_hsubps"
	}		}
	break;		break;
	}		}
	break;		break;
			case 'k': // 2 strings to match.
			switch (BuiltinName[16]) {
			default: break;
			case 'a': // 1 string to match.
			if (memcmp(BuiltinName.data()+17, "ndnw", 4))
			break;
			return Intrinsic::x86_kandn_v16i1; // "__builtin_ia32_kandnw"
			case 'x': // 1 string to match.
			if (memcmp(BuiltinName.data()+17, "norw", 4))
			break;
			return Intrinsic::x86_kxnor_v16i1; // "__builtin_ia32_kxnorw"
			}
			break;
	case 'l': // 1 string to match.		case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "fence", 5))		if (memcmp(BuiltinName.data()+16, "fence", 5))
	break;		break;
	return Intrinsic::x86_sse2_lfence; // "__builtin_ia32_lfence"		return Intrinsic::x86_sse2_lfence; // "__builtin_ia32_lfence"
	case 'm': // 2 strings to match.		case 'm': // 2 strings to match.
	switch (BuiltinName[16]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'f': // 1 string to match.		case 'f': // 1 string to match.
	if (memcmp(BuiltinName.data()+17, "ence", 4))		if (memcmp(BuiltinName.data()+17, "ence", 4))
	break;		break;
	skipping to change at line 39342		skipping to change at line 50340
	break;		break;
	return Intrinsic::x86_xabort; // "__builtin_ia32_xabort"		return Intrinsic::x86_xabort; // "__builtin_ia32_xabort"
	case 'b': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+17, "egin", 4))		if (memcmp(BuiltinName.data()+17, "egin", 4))
	break;		break;
	return Intrinsic::x86_xbegin; // "__builtin_ia32_xbegin"		return Intrinsic::x86_xbegin; // "__builtin_ia32_xbegin"
	}		}
	break;		break;
	}		}
	break;		break;
	case 22: // 53 strings to match.		case 22: // 57 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))		if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
	break;		break;
	switch (BuiltinName[15]) {		switch (BuiltinName[15]) {
	default: break;		default: break;
	case 'b': // 4 strings to match.		case 'b': // 4 strings to match.
	switch (BuiltinName[16]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'l': // 2 strings to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+17, "endp", 4))		if (memcmp(BuiltinName.data()+17, "endp", 4))
	break;		break;
	skipping to change at line 39626		skipping to change at line 50624
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'b': // 1 string to match.
	return Intrinsic::x86_mmx_psubus_b; // "__builtin_ia32_psubusb"		return Intrinsic::x86_mmx_psubus_b; // "__builtin_ia32_psubusb"
	case 'w': // 1 string to match.		case 'w': // 1 string to match.
	return Intrinsic::x86_mmx_psubus_w; // "__builtin_ia32_psubusw"		return Intrinsic::x86_mmx_psubus_w; // "__builtin_ia32_psubusw"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'r': // 6 strings to match.		case 'r': // 10 strings to match.
	switch (BuiltinName[16]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
			case 'c': // 4 strings to match.
			if (BuiltinName[17] != 'p')
			break;
			switch (BuiltinName[18]) {
			default: break;
			case '1': // 2 strings to match.
			if (memcmp(BuiltinName.data()+19, "4s", 2))
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx512_rcp14_sd; // "__builtin_ia32_
			rcp14sd"
			case 's': // 1 string to match.
			return Intrinsic::x86_avx512_rcp14_ss; // "__builtin_ia32_
			rcp14ss"
			}
			break;
			case '2': // 2 strings to match.
			if (memcmp(BuiltinName.data()+19, "8s", 2))
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx512_rcp28_sd; // "__builtin_ia32_
			rcp28sd"
			case 's': // 1 string to match.
			return Intrinsic::x86_avx512_rcp28_ss; // "__builtin_ia32_
			rcp28ss"
			}
			break;
			}
			break;
	case 'o': // 4 strings to match.		case 'o': // 4 strings to match.
	if (memcmp(BuiltinName.data()+17, "und", 3))		if (memcmp(BuiltinName.data()+17, "und", 3))
	break;		break;
	switch (BuiltinName[20]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'p': // 2 strings to match.		case 'p': // 2 strings to match.
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_round_pd; // "__builtin_ia32_ roundpd"		return Intrinsic::x86_sse41_round_pd; // "__builtin_ia32_ roundpd"
	skipping to change at line 39702		skipping to change at line 50729
	case 'e': // 1 string to match.		case 'e': // 1 string to match.
	return Intrinsic::x86_sse_ucomile_ss; // "__builtin_ia32_ ucomile"		return Intrinsic::x86_sse_ucomile_ss; // "__builtin_ia32_ ucomile"
	case 't': // 1 string to match.		case 't': // 1 string to match.
	return Intrinsic::x86_sse_ucomilt_ss; // "__builtin_ia32_ ucomilt"		return Intrinsic::x86_sse_ucomilt_ss; // "__builtin_ia32_ ucomilt"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 23: // 99 strings to match.		case 23: // 109 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))		if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
	break;		break;
	switch (BuiltinName[15]) {		switch (BuiltinName[15]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'a': // 3 strings to match.
	if (memcmp(BuiltinName.data()+16, "ddsubp", 6))		switch (BuiltinName[16]) {
	break;
	switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 2 strings to match.
	return Intrinsic::x86_sse3_addsub_pd; // "__builtin_ia32_addsubpd		if (memcmp(BuiltinName.data()+17, "dsubp", 5))
	"		break;
	case 's': // 1 string to match.		switch (BuiltinName[22]) {
	return Intrinsic::x86_sse3_addsub_ps; // "__builtin_ia32_addsubps		default: break;
	"		case 'd': // 1 string to match.
			return Intrinsic::x86_sse3_addsub_pd; // "__builtin_ia32_
			addsubpd"
			case 's': // 1 string to match.
			return Intrinsic::x86_sse3_addsub_ps; // "__builtin_ia32_
			addsubps"
			}
			break;
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+17, "dpi512", 6))
			break;
			return Intrinsic::x86_avx512_and_pi; // "__builtin_ia32_andpi512
			"
	}		}
	break;		break;
	case 'b': // 2 strings to match.		case 'b': // 2 strings to match.
	if (memcmp(BuiltinName.data()+16, "lendvp", 6))		if (memcmp(BuiltinName.data()+16, "lendvp", 6))
	break;		break;
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::x86_sse41_blendvpd; // "__builtin_ia32_blendvpd "		return Intrinsic::x86_sse41_blendvpd; // "__builtin_ia32_blendvpd "
	case 's': // 1 string to match.		case 's': // 1 string to match.
	skipping to change at line 39894		skipping to change at line 50930
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'i': // 1 string to match.		case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "nsertqi", 7))		if (memcmp(BuiltinName.data()+16, "nsertqi", 7))
	break;		break;
	return Intrinsic::x86_sse4a_insertqi; // "__builtin_ia32_insertqi "		return Intrinsic::x86_sse4a_insertqi; // "__builtin_ia32_insertqi "
			case 'k': // 3 strings to match.
			switch (BuiltinName[16]) {
			default: break;
			case 'o': // 2 strings to match.
			if (memcmp(BuiltinName.data()+17, "rtest", 5))
			break;
			switch (BuiltinName[22]) {
			default: break;
			case 'c': // 1 string to match.
			return Intrinsic::x86_avx512_kortestc; // "__builtin_ia32_
			kortestc"
			case 'z': // 1 string to match.
			return Intrinsic::x86_avx512_kortestz; // "__builtin_ia32_
			kortestz"
			}
			break;
			case 'u': // 1 string to match.
			if (memcmp(BuiltinName.data()+17, "npckbw", 6))
			break;
			return Intrinsic::x86_kunpck_v16i1; // "__builtin_ia32_kunpckbw
			"
			}
			break;
	case 'l': // 1 string to match.		case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "ddqu256", 7))		if (memcmp(BuiltinName.data()+16, "ddqu256", 7))
	break;		break;
	return Intrinsic::x86_avx_ldu_dq_256; // "__builtin_ia32_lddqu256 "		return Intrinsic::x86_avx_ldu_dq_256; // "__builtin_ia32_lddqu256 "
	case 'm': // 8 strings to match.		case 'm': // 12 strings to match.
	switch (BuiltinName[16]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'a': // 3 strings to match.		case 'a': // 5 strings to match.
	switch (BuiltinName[17]) {		switch (BuiltinName[17]) {
	default: break;		default: break;
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+18, "kmovq", 5))		if (memcmp(BuiltinName.data()+18, "kmovq", 5))
	break;		break;
	return Intrinsic::x86_mmx_maskmovq; // "__builtin_ia32_maskmovq "		return Intrinsic::x86_mmx_maskmovq; // "__builtin_ia32_maskmovq "
	case 'x': // 2 strings to match.		case 'x': // 4 strings to match.
	if (BuiltinName[18] != 'p')		if (BuiltinName[18] != 'p')
	break;		break;
	switch (BuiltinName[19]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 2 strings to match.
	if (memcmp(BuiltinName.data()+20, "256", 3))		switch (BuiltinName[20]) {
	break;		default: break;
	return Intrinsic::x86_avx_max_pd_256; // "__builtin_ia32_		case '2': // 1 string to match.
	maxpd256"		if (memcmp(BuiltinName.data()+21, "56", 2))
	case 's': // 1 string to match.		break;
	if (memcmp(BuiltinName.data()+20, "256", 3))		return Intrinsic::x86_avx_max_pd_256; // "__builtin_ia32_
	break;		maxpd256"
	return Intrinsic::x86_avx_max_ps_256; // "__builtin_ia32_		case '5': // 1 string to match.
	maxps256"		if (memcmp(BuiltinName.data()+21, "12", 2))
			break;
			return Intrinsic::x86_avx512_max_pd_512; // "__builtin_ia32_
			maxpd512"
			}
			break;
			case 's': // 2 strings to match.
			switch (BuiltinName[20]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(BuiltinName.data()+21, "56", 2))
			break;
			return Intrinsic::x86_avx_max_ps_256; // "__builtin_ia32_
			maxps256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+21, "12", 2))
			break;
			return Intrinsic::x86_avx512_max_ps_512; // "__builtin_ia32_
			maxps512"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'i': // 2 strings to match.		case 'i': // 4 strings to match.
	if (memcmp(BuiltinName.data()+17, "np", 2))		if (memcmp(BuiltinName.data()+17, "np", 2))
	break;		break;
	switch (BuiltinName[19]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 2 strings to match.
	if (memcmp(BuiltinName.data()+20, "256", 3))		switch (BuiltinName[20]) {
	break;		default: break;
	return Intrinsic::x86_avx_min_pd_256; // "__builtin_ia32_		case '2': // 1 string to match.
	minpd256"		if (memcmp(BuiltinName.data()+21, "56", 2))
	case 's': // 1 string to match.		break;
	if (memcmp(BuiltinName.data()+20, "256", 3))		return Intrinsic::x86_avx_min_pd_256; // "__builtin_ia32_
	break;		minpd256"
	return Intrinsic::x86_avx_min_ps_256; // "__builtin_ia32_		case '5': // 1 string to match.
	minps256"		if (memcmp(BuiltinName.data()+21, "12", 2))
			break;
			return Intrinsic::x86_avx512_min_pd_512; // "__builtin_ia32_
			minpd512"
			}
			break;
			case 's': // 2 strings to match.
			switch (BuiltinName[20]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(BuiltinName.data()+21, "56", 2))
			break;
			return Intrinsic::x86_avx_min_ps_256; // "__builtin_ia32_
			minps256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+21, "12", 2))
			break;
			return Intrinsic::x86_avx512_min_ps_512; // "__builtin_ia32_
			minps512"
			}
			break;
	}		}
	break;		break;
	case 'o': // 3 strings to match.		case 'o': // 3 strings to match.
	if (BuiltinName[17] != 'v')		if (BuiltinName[17] != 'v')
	break;		break;
	switch (BuiltinName[18]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'm': // 2 strings to match.		case 'm': // 2 strings to match.
	if (memcmp(BuiltinName.data()+19, "skp", 3))		if (memcmp(BuiltinName.data()+19, "skp", 3))
	break;		break;
	skipping to change at line 40314		skipping to change at line 51406
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'r': // 1 string to match.		case 'r': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "cpps256", 7))		if (memcmp(BuiltinName.data()+16, "cpps256", 7))
	break;		break;
	return Intrinsic::x86_avx_rcp_ps_256; // "__builtin_ia32_rcpps256 "		return Intrinsic::x86_avx_rcp_ps_256; // "__builtin_ia32_rcpps256 "
	case 's': // 3 strings to match.		case 's': // 5 strings to match.
	if (memcmp(BuiltinName.data()+16, "tore", 4))		switch (BuiltinName[16]) {
	break;
	switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+21, "qu", 2))		if (memcmp(BuiltinName.data()+17, "a1msg", 5))
	break;
	return Intrinsic::x86_sse2_storeu_dq; // "__builtin_ia32_storedqu
	"
	case 'u': // 2 strings to match.
	if (BuiltinName[21] != 'p')
	break;		break;
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
			case '1': // 1 string to match.
			return Intrinsic::x86_sha1msg1; // "__builtin_ia32_sha1msg1
			"
			case '2': // 1 string to match.
			return Intrinsic::x86_sha1msg2; // "__builtin_ia32_sha1msg2
			"
			}
			break;
			case 't': // 3 strings to match.
			if (memcmp(BuiltinName.data()+17, "ore", 3))
			break;
			switch (BuiltinName[20]) {
			default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::x86_sse2_storeu_pd; // "__builtin_ia32_		if (memcmp(BuiltinName.data()+21, "qu", 2))
	storeupd"		break;
	case 's': // 1 string to match.		return Intrinsic::x86_sse2_storeu_dq; // "__builtin_ia32_
	return Intrinsic::x86_sse_storeu_ps; // "__builtin_ia32_storeups		storedqu"
	"		case 'u': // 2 strings to match.
			if (BuiltinName[21] != 'p')
			break;
			switch (BuiltinName[22]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_sse2_storeu_pd; // "__builtin_ia32_
			storeupd"
			case 's': // 1 string to match.
			return Intrinsic::x86_sse_storeu_ps; // "__builtin_ia32_
			storeups"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'u': // 1 string to match.		case 'u': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "comineq", 7))		if (memcmp(BuiltinName.data()+16, "comineq", 7))
	break;		break;
	return Intrinsic::x86_sse_ucomineq_ss; // "__builtin_ia32_ucomineq "		return Intrinsic::x86_sse_ucomineq_ss; // "__builtin_ia32_ucomineq "
	case 'v': // 13 strings to match.		case 'v': // 13 strings to match.
	switch (BuiltinName[16]) {		switch (BuiltinName[16]) {
	skipping to change at line 40437		skipping to change at line 51545
	}		}
	break;		break;
	case 'z': // 1 string to match.		case 'z': // 1 string to match.
	if (memcmp(BuiltinName.data()+17, "eroall", 6))		if (memcmp(BuiltinName.data()+17, "eroall", 6))
	break;		break;
	return Intrinsic::x86_avx_vzeroall; // "__builtin_ia32_vzeroall "		return Intrinsic::x86_avx_vzeroall; // "__builtin_ia32_vzeroall "
	}		}
	break;		break;
	}		}
	break;		break;
	case 24: // 121 strings to match.		case 24: // 145 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))		if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
	break;		break;
	switch (BuiltinName[15]) {		switch (BuiltinName[15]) {
	default: break;		default: break;
	case 'a': // 3 strings to match.		case 'a': // 3 strings to match.
	if (memcmp(BuiltinName.data()+16, "es", 2))		if (memcmp(BuiltinName.data()+16, "es", 2))
	break;		break;
	switch (BuiltinName[18]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	skipping to change at line 40476		skipping to change at line 51584
	case '3': // 1 string to match.		case '3': // 1 string to match.
	if (BuiltinName[23] != '2')		if (BuiltinName[23] != '2')
	break;		break;
	return Intrinsic::x86_bmi_bextr_32; // "__builtin_ia32_bextr_u3 2"		return Intrinsic::x86_bmi_bextr_32; // "__builtin_ia32_bextr_u3 2"
	case '6': // 1 string to match.		case '6': // 1 string to match.
	if (BuiltinName[23] != '4')		if (BuiltinName[23] != '4')
	break;		break;
	return Intrinsic::x86_bmi_bextr_64; // "__builtin_ia32_bextr_u6 4"		return Intrinsic::x86_bmi_bextr_64; // "__builtin_ia32_bextr_u6 4"
	}		}
	break;		break;
	case 'c': // 7 strings to match.		case 'c': // 11 strings to match.
	switch (BuiltinName[16]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'o': // 1 string to match.		case 'o': // 1 string to match.
	if (memcmp(BuiltinName.data()+17, "misdneq", 7))		if (memcmp(BuiltinName.data()+17, "misdneq", 7))
	break;		break;
	return Intrinsic::x86_sse2_comineq_sd; // "__builtin_ia32_comisdne q"		return Intrinsic::x86_sse2_comineq_sd; // "__builtin_ia32_comisdne q"
	case 'v': // 6 strings to match.		case 'v': // 10 strings to match.
	if (memcmp(BuiltinName.data()+17, "tt", 2))		if (BuiltinName[17] != 't')
	break;		break;
	switch (BuiltinName[19]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'p': // 4 strings to match.		case 's': // 2 strings to match.
	switch (BuiltinName[20]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'd': // 2 strings to match.		case 'd': // 1 string to match.
	if (BuiltinName[21] != '2')		if (memcmp(BuiltinName.data()+20, "2usi", 4))
	break;		break;
	switch (BuiltinName[22]) {		return Intrinsic::x86_avx512_cvtsd2usi; // "__builtin_ia32_
			cvtsd2usi"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "2usi", 4))
			break;
			return Intrinsic::x86_avx512_cvtss2usi; // "__builtin_ia32_
			cvtss2usi"
			}
			break;
			case 't': // 6 strings to match.
			switch (BuiltinName[19]) {
			default: break;
			case 'p': // 4 strings to match.
			switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 2 strings to match.
	if (BuiltinName[23] != 'q')		if (BuiltinName[21] != '2')
	break;		break;
	return Intrinsic::x86_sse2_cvttpd2dq; // "__builtin_ia32_		switch (BuiltinName[22]) {
	cvttpd2dq"		default: break;
	case 'p': // 1 string to match.		case 'd': // 1 string to match.
	if (BuiltinName[23] != 'i')		if (BuiltinName[23] != 'q')
			break;
			return Intrinsic::x86_sse2_cvttpd2dq; // "__builtin_ia32_
			cvttpd2dq"
			case 'p': // 1 string to match.
			if (BuiltinName[23] != 'i')
			break;
			return Intrinsic::x86_sse_cvttpd2pi; // "__builtin_ia32_
			cvttpd2pi"
			}
			break;
			case 's': // 2 strings to match.
			if (BuiltinName[21] != '2')
	break;		break;
	return Intrinsic::x86_sse_cvttpd2pi; // "__builtin_ia32_		switch (BuiltinName[22]) {
	cvttpd2pi"		default: break;
			case 'd': // 1 string to match.
			if (BuiltinName[23] != 'q')
			break;
			return Intrinsic::x86_sse2_cvttps2dq; // "__builtin_ia32_
			cvttps2dq"
			case 'p': // 1 string to match.
			if (BuiltinName[23] != 'i')
			break;
			return Intrinsic::x86_sse_cvttps2pi; // "__builtin_ia32_
			cvttps2pi"
			}
			break;
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 's': // 2 strings to match.
	if (BuiltinName[21] != '2')		switch (BuiltinName[20]) {
	break;
	switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (BuiltinName[23] != 'q')		if (memcmp(BuiltinName.data()+21, "2si", 3))
	break;		break;
	return Intrinsic::x86_sse2_cvttps2dq; // "__builtin_ia32_		return Intrinsic::x86_sse2_cvttsd2si; // "__builtin_ia32_
	cvttps2dq"		cvttsd2si"
	case 'p': // 1 string to match.		case 's': // 1 string to match.
	if (BuiltinName[23] != 'i')		if (memcmp(BuiltinName.data()+21, "2si", 3))
	break;		break;
	return Intrinsic::x86_sse_cvttps2pi; // "__builtin_ia32_ cvttps2pi"		return Intrinsic::x86_sse_cvttss2si; // "__builtin_ia32_ cvttss2si"
	}		}
	break;		break;
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 'u': // 2 strings to match.
	switch (BuiltinName[20]) {		if (memcmp(BuiltinName.data()+19, "si2s", 4))
			break;
			switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+21, "2si", 3))		return Intrinsic::x86_avx512_cvtusi2sd; // "__builtin_ia32_
	break;		cvtusi2sd"
	return Intrinsic::x86_sse2_cvttsd2si; // "__builtin_ia32_
	cvttsd2si"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+21, "2si", 3))		return Intrinsic::x86_avx512_cvtusi2ss; // "__builtin_ia32_
	break;		cvtusi2ss"
	return Intrinsic::x86_sse_cvttss2si; // "__builtin_ia32_
	cvttss2si"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'g': // 4 strings to match.		case 'g': // 4 strings to match.
	if (memcmp(BuiltinName.data()+16, "ather", 5))		if (memcmp(BuiltinName.data()+16, "ather", 5))
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	skipping to change at line 40604		skipping to change at line 51741
	break;		break;
	return Intrinsic::x86_avx_hsub_pd_256; // "__builtin_ia32_ hsubpd256"		return Intrinsic::x86_avx_hsub_pd_256; // "__builtin_ia32_ hsubpd256"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+21, "256", 3))		if (memcmp(BuiltinName.data()+21, "256", 3))
	break;		break;
	return Intrinsic::x86_avx_hsub_ps_256; // "__builtin_ia32_ hsubps256"		return Intrinsic::x86_avx_hsub_ps_256; // "__builtin_ia32_ hsubps256"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'm': // 2 strings to match.		case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "askload", 7))		if (memcmp(BuiltinName.data()+16, "nt2maskw", 8))
	break;		break;
	switch (BuiltinName[23]) {		return Intrinsic::x86_int2mask_v16i1; // "__builtin_ia32_int2mask
			w"
			case 'm': // 3 strings to match.
			if (memcmp(BuiltinName.data()+16, "ask", 3))
			break;
			switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case '2': // 1 string to match.
	return Intrinsic::x86_avx2_maskload_d; // "__builtin_ia32_maskload		if (memcmp(BuiltinName.data()+20, "intw", 4))
	d"		break;
	case 'q': // 1 string to match.		return Intrinsic::x86_mask2int_v16i1; // "__builtin_ia32_mask2int
	return Intrinsic::x86_avx2_maskload_q; // "__builtin_ia32_maskload		w"
	q"		case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+20, "oad", 3))
			break;
			switch (BuiltinName[23]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx2_maskload_d; // "__builtin_ia32_
			maskloadd"
			case 'q': // 1 string to match.
			return Intrinsic::x86_avx2_maskload_q; // "__builtin_ia32_
			maskloadq"
			}
			break;
	}		}
	break;		break;
	case 'p': // 82 strings to match.		case 'p': // 90 strings to match.
	switch (BuiltinName[16]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'a': // 4 strings to match.		case 'a': // 4 strings to match.
	if (memcmp(BuiltinName.data()+17, "dds", 3))		if (memcmp(BuiltinName.data()+17, "dds", 3))
	break;		break;
	switch (BuiltinName[20]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'b': // 2 strings to match.		case 'b': // 2 strings to match.
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	skipping to change at line 40726		skipping to change at line 51878
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "56", 2))		if (memcmp(BuiltinName.data()+22, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_phsub_w; // "__builtin_ia32_ phsubw256"		return Intrinsic::x86_avx2_phsub_w; // "__builtin_ia32_ phsubw256"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'm': // 29 strings to match.		case 'm': // 37 strings to match.
	switch (BuiltinName[17]) {		switch (BuiltinName[17]) {
	default: break;		default: break;
	case 'a': // 13 strings to match.		case 'a': // 17 strings to match.
	switch (BuiltinName[18]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+19, "dubsw", 5))		if (memcmp(BuiltinName.data()+19, "dubsw", 5))
	break;		break;
	return Intrinsic::x86_ssse3_pmadd_ub_sw; // "__builtin_ia32_ pmaddubsw"		return Intrinsic::x86_ssse3_pmadd_ub_sw; // "__builtin_ia32_ pmaddubsw"
	case 'x': // 12 strings to match.		case 'x': // 16 strings to match.
	switch (BuiltinName[19]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 's': // 6 strings to match.		case 's': // 8 strings to match.
	switch (BuiltinName[20]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'b': // 2 strings to match.		case 'b': // 2 strings to match.
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "28", 2))		if (memcmp(BuiltinName.data()+22, "28", 2))
	break;		break;
	return Intrinsic::x86_sse41_pmaxsb; // "__builtin_ia32_ pmaxsb128"		return Intrinsic::x86_sse41_pmaxsb; // "__builtin_ia32_ pmaxsb128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "56", 2))		if (memcmp(BuiltinName.data()+22, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pmaxs_b; // "__builtin_ia32_ pmaxsb256"		return Intrinsic::x86_avx2_pmaxs_b; // "__builtin_ia32_ pmaxsb256"
	}		}
	break;		break;
	case 'd': // 2 strings to match.		case 'd': // 3 strings to match.
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "28", 2))		if (memcmp(BuiltinName.data()+22, "28", 2))
	break;		break;
	return Intrinsic::x86_sse41_pmaxsd; // "__builtin_ia32_ pmaxsd128"		return Intrinsic::x86_sse41_pmaxsd; // "__builtin_ia32_ pmaxsd128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "56", 2))		if (memcmp(BuiltinName.data()+22, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pmaxs_d; // "__builtin_ia32_ pmaxsd256"		return Intrinsic::x86_avx2_pmaxs_d; // "__builtin_ia32_ pmaxsd256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "12", 2))
			break;
			return Intrinsic::x86_avx512_pmaxs_d; // "__built
			in_ia32_pmaxsd512"
	}		}
	break;		break;
			case 'q': // 1 string to match.
			if (memcmp(BuiltinName.data()+21, "512", 3))
			break;
			return Intrinsic::x86_avx512_pmaxs_q; // "__builtin_ia32_
			pmaxsq512"
	case 'w': // 2 strings to match.		case 'w': // 2 strings to match.
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "28", 2))		if (memcmp(BuiltinName.data()+22, "28", 2))
	break;		break;
	return Intrinsic::x86_sse2_pmaxs_w; // "__builtin_ia32_ pmaxsw128"		return Intrinsic::x86_sse2_pmaxs_w; // "__builtin_ia32_ pmaxsw128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "56", 2))		if (memcmp(BuiltinName.data()+22, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pmaxs_w; // "__builtin_ia32_ pmaxsw256"		return Intrinsic::x86_avx2_pmaxs_w; // "__builtin_ia32_ pmaxsw256"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'u': // 6 strings to match.		case 'u': // 8 strings to match.
	switch (BuiltinName[20]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'b': // 2 strings to match.		case 'b': // 2 strings to match.
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "28", 2))		if (memcmp(BuiltinName.data()+22, "28", 2))
	break;		break;
	return Intrinsic::x86_sse2_pmaxu_b; // "__builtin_ia32_ pmaxub128"		return Intrinsic::x86_sse2_pmaxu_b; // "__builtin_ia32_ pmaxub128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "56", 2))		if (memcmp(BuiltinName.data()+22, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pmaxu_b; // "__builtin_ia32_ pmaxub256"		return Intrinsic::x86_avx2_pmaxu_b; // "__builtin_ia32_ pmaxub256"
	}		}
	break;		break;
	case 'd': // 2 strings to match.		case 'd': // 3 strings to match.
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "28", 2))		if (memcmp(BuiltinName.data()+22, "28", 2))
	break;		break;
	return Intrinsic::x86_sse41_pmaxud; // "__builtin_ia32_ pmaxud128"		return Intrinsic::x86_sse41_pmaxud; // "__builtin_ia32_ pmaxud128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "56", 2))		if (memcmp(BuiltinName.data()+22, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pmaxu_d; // "__builtin_ia32_ pmaxud256"		return Intrinsic::x86_avx2_pmaxu_d; // "__builtin_ia32_ pmaxud256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "12", 2))
			break;
			return Intrinsic::x86_avx512_pmaxu_d; // "__built
			in_ia32_pmaxud512"
	}		}
	break;		break;
			case 'q': // 1 string to match.
			if (memcmp(BuiltinName.data()+21, "512", 3))
			break;
			return Intrinsic::x86_avx512_pmaxu_q; // "__builtin_ia32_
			pmaxuq512"
	case 'w': // 2 strings to match.		case 'w': // 2 strings to match.
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "28", 2))		if (memcmp(BuiltinName.data()+22, "28", 2))
	break;		break;
	return Intrinsic::x86_sse41_pmaxuw; // "__builtin_ia32_ pmaxuw128"		return Intrinsic::x86_sse41_pmaxuw; // "__builtin_ia32_ pmaxuw128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "56", 2))		if (memcmp(BuiltinName.data()+22, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pmaxu_w; // "__builtin_ia32_ pmaxuw256"		return Intrinsic::x86_avx2_pmaxu_w; // "__builtin_ia32_ pmaxuw256"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'i': // 12 strings to match.		case 'i': // 16 strings to match.
	if (BuiltinName[18] != 'n')		if (BuiltinName[18] != 'n')
	break;		break;
	switch (BuiltinName[19]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 's': // 6 strings to match.		case 's': // 8 strings to match.
	switch (BuiltinName[20]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'b': // 2 strings to match.		case 'b': // 2 strings to match.
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "28", 2))		if (memcmp(BuiltinName.data()+22, "28", 2))
	break;		break;
	return Intrinsic::x86_sse41_pminsb; // "__builtin_ia32_ pminsb128"		return Intrinsic::x86_sse41_pminsb; // "__builtin_ia32_ pminsb128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "56", 2))		if (memcmp(BuiltinName.data()+22, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pmins_b; // "__builtin_ia32_ pminsb256"		return Intrinsic::x86_avx2_pmins_b; // "__builtin_ia32_ pminsb256"
	}		}
	break;		break;
	case 'd': // 2 strings to match.		case 'd': // 3 strings to match.
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "28", 2))		if (memcmp(BuiltinName.data()+22, "28", 2))
	break;		break;
	return Intrinsic::x86_sse41_pminsd; // "__builtin_ia32_ pminsd128"		return Intrinsic::x86_sse41_pminsd; // "__builtin_ia32_ pminsd128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "56", 2))		if (memcmp(BuiltinName.data()+22, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pmins_d; // "__builtin_ia32_ pminsd256"		return Intrinsic::x86_avx2_pmins_d; // "__builtin_ia32_ pminsd256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "12", 2))
			break;
			return Intrinsic::x86_avx512_pmins_d; // "__builtin_ia32_
			pminsd512"
	}		}
	break;		break;
			case 'q': // 1 string to match.
			if (memcmp(BuiltinName.data()+21, "512", 3))
			break;
			return Intrinsic::x86_avx512_pmins_q; // "__builtin_ia32_
			pminsq512"
	case 'w': // 2 strings to match.		case 'w': // 2 strings to match.
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "28", 2))		if (memcmp(BuiltinName.data()+22, "28", 2))
	break;		break;
	return Intrinsic::x86_sse2_pmins_w; // "__builtin_ia32_ pminsw128"		return Intrinsic::x86_sse2_pmins_w; // "__builtin_ia32_ pminsw128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "56", 2))		if (memcmp(BuiltinName.data()+22, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pmins_w; // "__builtin_ia32_ pminsw256"		return Intrinsic::x86_avx2_pmins_w; // "__builtin_ia32_ pminsw256"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'u': // 6 strings to match.		case 'u': // 8 strings to match.
	switch (BuiltinName[20]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'b': // 2 strings to match.		case 'b': // 2 strings to match.
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "28", 2))		if (memcmp(BuiltinName.data()+22, "28", 2))
	break;		break;
	return Intrinsic::x86_sse2_pminu_b; // "__builtin_ia32_ pminub128"		return Intrinsic::x86_sse2_pminu_b; // "__builtin_ia32_ pminub128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "56", 2))		if (memcmp(BuiltinName.data()+22, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pminu_b; // "__builtin_ia32_ pminub256"		return Intrinsic::x86_avx2_pminu_b; // "__builtin_ia32_ pminub256"
	}		}
	break;		break;
	case 'd': // 2 strings to match.		case 'd': // 3 strings to match.
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "28", 2))		if (memcmp(BuiltinName.data()+22, "28", 2))
	break;		break;
	return Intrinsic::x86_sse41_pminud; // "__builtin_ia32_ pminud128"		return Intrinsic::x86_sse41_pminud; // "__builtin_ia32_ pminud128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "56", 2))		if (memcmp(BuiltinName.data()+22, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pminu_d; // "__builtin_ia32_ pminud256"		return Intrinsic::x86_avx2_pminu_d; // "__builtin_ia32_ pminud256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "12", 2))
			break;
			return Intrinsic::x86_avx512_pminu_d; // "__builtin_ia32_
			pminud512"
	}		}
	break;		break;
			case 'q': // 1 string to match.
			if (memcmp(BuiltinName.data()+21, "512", 3))
			break;
			return Intrinsic::x86_avx512_pminu_q; // "__builtin_ia32_
			pminuq512"
	case 'w': // 2 strings to match.		case 'w': // 2 strings to match.
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "28", 2))		if (memcmp(BuiltinName.data()+22, "28", 2))
	break;		break;
	return Intrinsic::x86_sse41_pminuw; // "__builtin_ia32_ pminuw128"		return Intrinsic::x86_sse41_pminuw; // "__builtin_ia32_ pminuw128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "56", 2))		if (memcmp(BuiltinName.data()+22, "56", 2))
	break;		break;
	skipping to change at line 41297		skipping to change at line 52481
	case 'w': // 1 string to match.		case 'w': // 1 string to match.
	if (BuiltinName[23] != 'd')		if (BuiltinName[23] != 'd')
	break;		break;
	return Intrinsic::x86_mmx_punpcklwd; // "__builtin_ia32_ punpcklwd"		return Intrinsic::x86_mmx_punpcklwd; // "__builtin_ia32_ punpcklwd"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 'r': // 4 strings to match.
	if (memcmp(BuiltinName.data()+16, "qrtp", 4))		if (memcmp(BuiltinName.data()+16, "sqrt", 4))
	break;		break;
	switch (BuiltinName[20]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case '1': // 2 strings to match.
	if (memcmp(BuiltinName.data()+21, "256", 3))		if (memcmp(BuiltinName.data()+21, "4s", 2))
	break;		break;
	return Intrinsic::x86_avx_sqrt_pd_256; // "__builtin_ia32_sqrtpd25		switch (BuiltinName[23]) {
	6"		default: break;
	case 's': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+21, "256", 3))		return Intrinsic::x86_avx512_rsqrt14_sd; // "__builtin_ia32_
			rsqrt14sd"
			case 's': // 1 string to match.
			return Intrinsic::x86_avx512_rsqrt14_ss; // "__builtin_ia32_
			rsqrt14ss"
			}
			break;
			case '2': // 2 strings to match.
			if (memcmp(BuiltinName.data()+21, "8s", 2))
			break;
			switch (BuiltinName[23]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx512_rsqrt28_sd; // "__builtin_ia32_
			rsqrt28sd"
			case 's': // 1 string to match.
			return Intrinsic::x86_avx512_rsqrt28_ss; // "__builtin_ia32_
			rsqrt28ss"
			}
			break;
			}
			break;
			case 's': // 8 strings to match.
			switch (BuiltinName[16]) {
			default: break;
			case 'h': // 2 strings to match.
			if (memcmp(BuiltinName.data()+17, "a1", 2))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'n': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "exte", 4))
			break;
			return Intrinsic::x86_sha1nexte; // "__builtin_ia32_sha1next
			e"
			case 'r': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "nds4", 4))
			break;
			return Intrinsic::x86_sha1rnds4; // "__builtin_ia32_sha1rnds
			4"
			}
			break;
			case 'q': // 6 strings to match.
			if (memcmp(BuiltinName.data()+17, "rt", 2))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'p': // 4 strings to match.
			switch (BuiltinName[20]) {
			default: break;
			case 'd': // 2 strings to match.
			switch (BuiltinName[21]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "56", 2))
			break;
			return Intrinsic::x86_avx_sqrt_pd_256; // "__builtin_ia32_
			sqrtpd256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "12", 2))
			break;
			return Intrinsic::x86_avx512_sqrt_pd_512; // "__built
			in_ia32_sqrtpd512"
			}
			break;
			case 's': // 2 strings to match.
			switch (BuiltinName[21]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "56", 2))
			break;
			return Intrinsic::x86_avx_sqrt_ps_256; // "__builtin_ia32_
			sqrtps256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "12", 2))
			break;
			return Intrinsic::x86_avx512_sqrt_ps_512; // "__built
			in_ia32_sqrtps512"
			}
			break;
			}
			break;
			case 'r': // 2 strings to match.
			if (memcmp(BuiltinName.data()+20, "nds", 3))
			break;
			switch (BuiltinName[23]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx512_sqrt_sd; // "__builtin_ia32_
			sqrtrndsd"
			case 's': // 1 string to match.
			return Intrinsic::x86_avx512_sqrt_ss; // "__builtin_ia32_
			sqrtrndss"
			}
	break;		break;
	return Intrinsic::x86_avx_sqrt_ps_256; // "__builtin_ia32_sqrtps25		}
	6"		break;
	}		}
	break;		break;
	case 'u': // 5 strings to match.		case 'u': // 5 strings to match.
	if (memcmp(BuiltinName.data()+16, "comisd", 6))		if (memcmp(BuiltinName.data()+16, "comisd", 6))
	break;		break;
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'e': // 1 string to match.
	if (BuiltinName[23] != 'q')		if (BuiltinName[23] != 'q')
	break;		break;
	skipping to change at line 41420		skipping to change at line 52687
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 25: // 59 strings to match.		case 25: // 74 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))		if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
	break;		break;
	switch (BuiltinName[15]) {		switch (BuiltinName[15]) {
	default: break;		default: break;
	case 'b': // 2 strings to match.		case 'b': // 4 strings to match.
	if (memcmp(BuiltinName.data()+16, "lendp", 5))		switch (BuiltinName[16]) {
	break;
	switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'e': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "256", 3))		if (memcmp(BuiltinName.data()+17, "xtri_u", 6))
	break;		break;
	return Intrinsic::x86_avx_blend_pd_256; // "__builtin_ia32_		switch (BuiltinName[23]) {
	blendpd256"		default: break;
	case 's': // 1 string to match.		case '3': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "256", 3))		if (BuiltinName[24] != '2')
			break;
			return Intrinsic::x86_tbm_bextri_u32; // "__builtin_ia32_
			bextri_u32"
			case '6': // 1 string to match.
			if (BuiltinName[24] != '4')
			break;
			return Intrinsic::x86_tbm_bextri_u64; // "__builtin_ia32_
			bextri_u64"
			}
			break;
			case 'l': // 2 strings to match.
			if (memcmp(BuiltinName.data()+17, "endp", 4))
	break;		break;
	return Intrinsic::x86_avx_blend_ps_256; // "__builtin_ia32_		switch (BuiltinName[21]) {
	blendps256"		default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "256", 3))
			break;
			return Intrinsic::x86_avx_blend_pd_256; // "__builtin_ia32_
			blendpd256"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "256", 3))
			break;
			return Intrinsic::x86_avx_blend_ps_256; // "__builtin_ia32_
			blendps256"
			}
			break;
	}		}
	break;		break;
	case 'c': // 4 strings to match.		case 'c': // 7 strings to match.
	if (memcmp(BuiltinName.data()+16, "vts", 3))		switch (BuiltinName[16]) {
	break;
	switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'm': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "2si64", 5))		if (memcmp(BuiltinName.data()+17, "peqpi512", 8))
	break;		break;
	return Intrinsic::x86_sse2_cvtsd2si64; // "__builtin_ia32_cvtsd2si		return Intrinsic::x86_avx512_cmpeq_pi_512; // "__builtin_ia32_
	64"		cmpeqpi512"
	case 'i': // 2 strings to match.		case 'v': // 6 strings to match.
	if (memcmp(BuiltinName.data()+20, "642s", 4))		if (BuiltinName[17] != 't')
	break;		break;
	switch (BuiltinName[24]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 's': // 4 strings to match.
	return Intrinsic::x86_sse2_cvtsi642sd; // "__builtin_ia32_		switch (BuiltinName[19]) {
	cvtsi642sd"		default: break;
	case 's': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::x86_sse_cvtsi642ss; // "__builtin_ia32_		if (memcmp(BuiltinName.data()+20, "2si64", 5))
	cvtsi642ss"		break;
			return Intrinsic::x86_sse2_cvtsd2si64; // "__builtin_ia32_
			cvtsd2si64"
			case 'i': // 2 strings to match.
			if (memcmp(BuiltinName.data()+20, "642s", 4))
			break;
			switch (BuiltinName[24]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_sse2_cvtsi642sd; // "__builtin_ia32_
			cvtsi642sd"
			case 's': // 1 string to match.
			return Intrinsic::x86_sse_cvtsi642ss; // "__builtin_ia32_
			cvtsi642ss"
			}
			break;
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "2si64", 5))
			break;
			return Intrinsic::x86_sse_cvtss2si64; // "__builtin_ia32_
			cvtss2si64"
			}
			break;
			case 't': // 2 strings to match.
			if (BuiltinName[19] != 's')
			break;
			switch (BuiltinName[20]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+21, "2usi", 4))
			break;
			return Intrinsic::x86_avx512_cvttsd2usi; // "__builtin_ia32_
			cvttsd2usi"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+21, "2usi", 4))
			break;
			return Intrinsic::x86_avx512_cvttss2usi; // "__builtin_ia32_
			cvttss2usi"
			}
			break;
	}		}
	break;		break;
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "2si64", 5))
	break;
	return Intrinsic::x86_sse_cvtss2si64; // "__builtin_ia32_cvtss2si
	64"
	}		}
	break;		break;
	case 'g': // 4 strings to match.		case 'g': // 4 strings to match.
	if (memcmp(BuiltinName.data()+16, "ather", 5))		if (memcmp(BuiltinName.data()+16, "ather", 5))
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'd': // 2 strings to match.		case 'd': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "_p", 2))		if (memcmp(BuiltinName.data()+22, "_p", 2))
	break;		break;
	skipping to change at line 41548		skipping to change at line 52864
	break;		break;
	return Intrinsic::x86_sse41_mpsadbw; // "__builtin_ia32_mpsadbw1 28"		return Intrinsic::x86_sse41_mpsadbw; // "__builtin_ia32_mpsadbw1 28"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "56", 2))		if (memcmp(BuiltinName.data()+23, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_mpsadbw; // "__builtin_ia32_mpsadbw2 56"		return Intrinsic::x86_avx2_mpsadbw; // "__builtin_ia32_mpsadbw2 56"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'p': // 26 strings to match.		case 'p': // 28 strings to match.
	switch (BuiltinName[16]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'a': // 4 strings to match.		case 'a': // 4 strings to match.
	if (memcmp(BuiltinName.data()+17, "ddus", 4))		if (memcmp(BuiltinName.data()+17, "ddus", 4))
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'b': // 2 strings to match.		case 'b': // 2 strings to match.
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	skipping to change at line 41709		skipping to change at line 53025
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "56", 2))		if (memcmp(BuiltinName.data()+23, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pmulu_dq; // "__builtin_ia32_ pmuludq256"		return Intrinsic::x86_avx2_pmulu_dq; // "__builtin_ia32_ pmuludq256"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 's': // 8 strings to match.		case 's': // 10 strings to match.
	switch (BuiltinName[17]) {		switch (BuiltinName[17]) {
	default: break;		default: break;
	case 'l': // 2 strings to match.		case 'l': // 3 strings to match.
	if (memcmp(BuiltinName.data()+18, "ldqi", 4))		if (memcmp(BuiltinName.data()+18, "ldqi", 4))
	break;		break;
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "28", 2))		if (memcmp(BuiltinName.data()+23, "28", 2))
	break;		break;
	return Intrinsic::x86_sse2_psll_dq; // "__builtin_ia32_ pslldqi128"		return Intrinsic::x86_sse2_psll_dq; // "__builtin_ia32_ pslldqi128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "56", 2))		if (memcmp(BuiltinName.data()+23, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_psll_dq; // "__builtin_ia32_ pslldqi256"		return Intrinsic::x86_avx2_psll_dq; // "__builtin_ia32_ pslldqi256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "12", 2))
			break;
			return Intrinsic::x86_avx512_psll_dq; // "__builtin_ia32_
			pslldqi512"
	}		}
	break;		break;
	case 'r': // 2 strings to match.		case 'r': // 3 strings to match.
	if (memcmp(BuiltinName.data()+18, "ldqi", 4))		if (memcmp(BuiltinName.data()+18, "ldqi", 4))
	break;		break;
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "28", 2))		if (memcmp(BuiltinName.data()+23, "28", 2))
	break;		break;
	return Intrinsic::x86_sse2_psrl_dq; // "__builtin_ia32_ psrldqi128"		return Intrinsic::x86_sse2_psrl_dq; // "__builtin_ia32_ psrldqi128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "56", 2))		if (memcmp(BuiltinName.data()+23, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_psrl_dq; // "__builtin_ia32_ psrldqi256"		return Intrinsic::x86_avx2_psrl_dq; // "__builtin_ia32_ psrldqi256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "12", 2))
			break;
			return Intrinsic::x86_avx512_psrl_dq; // "__builtin_ia32_
			psrldqi512"
	}		}
	break;		break;
	case 'u': // 4 strings to match.		case 'u': // 4 strings to match.
	if (memcmp(BuiltinName.data()+18, "bus", 3))		if (memcmp(BuiltinName.data()+18, "bus", 3))
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'b': // 2 strings to match.		case 'b': // 2 strings to match.
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	skipping to change at line 41779		skipping to change at line 53103
	break;		break;
	return Intrinsic::x86_avx2_psubus_w; // "__builtin_ia32_ psubusw256"		return Intrinsic::x86_avx2_psubus_w; // "__builtin_ia32_ psubusw256"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'r': // 7 strings to match.		case 'r': // 13 strings to match.
	switch (BuiltinName[16]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
			case 'c': // 4 strings to match.
			if (BuiltinName[17] != 'p')
			break;
			switch (BuiltinName[18]) {
			default: break;
			case '1': // 2 strings to match.
			if (memcmp(BuiltinName.data()+19, "4p", 2))
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "512", 3))
			break;
			return Intrinsic::x86_avx512_rcp14_pd_512; // "__builtin_ia32_
			rcp14pd512"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "512", 3))
			break;
			return Intrinsic::x86_avx512_rcp14_ps_512; // "__builtin_ia32_
			rcp14ps512"
			}
			break;
			case '2': // 2 strings to match.
			if (memcmp(BuiltinName.data()+19, "8p", 2))
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "512", 3))
			break;
			return Intrinsic::x86_avx512_rcp28_pd_512; // "__builtin_ia32_
			rcp28pd512"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+22, "512", 3))
			break;
			return Intrinsic::x86_avx512_rcp28_ps_512; // "__builtin_ia32_
			rcp28ps512"
			}
			break;
			}
			break;
	case 'd': // 4 strings to match.		case 'd': // 4 strings to match.
	switch (BuiltinName[17]) {		switch (BuiltinName[17]) {
	default: break;		default: break;
	case 'f': // 2 strings to match.		case 'f': // 2 strings to match.
	if (memcmp(BuiltinName.data()+18, "sbase", 5))		if (memcmp(BuiltinName.data()+18, "sbase", 5))
	break;		break;
	switch (BuiltinName[23]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case '3': // 1 string to match.		case '3': // 1 string to match.
	if (BuiltinName[24] != '2')		if (BuiltinName[24] != '2')
	skipping to change at line 41817		skipping to change at line 53178
	break;		break;
	return Intrinsic::x86_rdgsbase_32; // "__builtin_ia32_rdgsbase 32"		return Intrinsic::x86_rdgsbase_32; // "__builtin_ia32_rdgsbase 32"
	case '6': // 1 string to match.		case '6': // 1 string to match.
	if (BuiltinName[24] != '4')		if (BuiltinName[24] != '4')
	break;		break;
	return Intrinsic::x86_rdgsbase_64; // "__builtin_ia32_rdgsbase 64"		return Intrinsic::x86_rdgsbase_64; // "__builtin_ia32_rdgsbase 64"
	}		}
	break;		break;
	}		}
	break;		break;
			case 'n': // 2 strings to match.
			if (memcmp(BuiltinName.data()+17, "dscales", 7))
			break;
			switch (BuiltinName[24]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx512_rndscale_sd; // "__builtin_ia32_
			rndscalesd"
			case 's': // 1 string to match.
			return Intrinsic::x86_avx512_rndscale_ss; // "__builtin_ia32_
			rndscaless"
			}
			break;
	case 'o': // 2 strings to match.		case 'o': // 2 strings to match.
	if (memcmp(BuiltinName.data()+17, "undp", 4))		if (memcmp(BuiltinName.data()+17, "undp", 4))
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "256", 3))		if (memcmp(BuiltinName.data()+22, "256", 3))
	break;		break;
	return Intrinsic::x86_avx_round_pd_256; // "__builtin_ia32_ roundpd256"		return Intrinsic::x86_avx_round_pd_256; // "__builtin_ia32_ roundpd256"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	skipping to change at line 41838		skipping to change at line 53210
	break;		break;
	return Intrinsic::x86_avx_round_ps_256; // "__builtin_ia32_ roundps256"		return Intrinsic::x86_avx_round_ps_256; // "__builtin_ia32_ roundps256"
	}		}
	break;		break;
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+17, "qrtps256", 8))		if (memcmp(BuiltinName.data()+17, "qrtps256", 8))
	break;		break;
	return Intrinsic::x86_avx_rsqrt_ps_256; // "__builtin_ia32_ rsqrtps256"		return Intrinsic::x86_avx_rsqrt_ps_256; // "__builtin_ia32_ rsqrtps256"
	}		}
	break;		break;
	case 's': // 1 string to match.		case 's': // 3 strings to match.
	if (memcmp(BuiltinName.data()+16, "torelv4si", 9))		switch (BuiltinName[16]) {
			default: break;
			case 'h': // 2 strings to match.
			if (memcmp(BuiltinName.data()+17, "a256msg", 7))
			break;
			switch (BuiltinName[24]) {
			default: break;
			case '1': // 1 string to match.
			return Intrinsic::x86_sha256msg1; // "__builtin_ia32_sha256ms
			g1"
			case '2': // 1 string to match.
			return Intrinsic::x86_sha256msg2; // "__builtin_ia32_sha256ms
			g2"
			}
	break;		break;
	return Intrinsic::x86_sse2_storel_dq; // "__builtin_ia32_storelv4		case 't': // 1 string to match.
	si"		if (memcmp(BuiltinName.data()+17, "orelv4si", 8))
			break;
			return Intrinsic::x86_sse2_storel_dq; // "__builtin_ia32_storelv4
			si"
			}
			break;
	case 'u': // 1 string to match.		case 'u': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "comisdneq", 9))		if (memcmp(BuiltinName.data()+16, "comisdneq", 9))
	break;		break;
	return Intrinsic::x86_sse2_ucomineq_sd; // "__builtin_ia32_ucomisdn eq"		return Intrinsic::x86_sse2_ucomineq_sd; // "__builtin_ia32_ucomisdn eq"
	case 'v': // 3 strings to match.		case 'v': // 3 strings to match.
	switch (BuiltinName[16]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
	case 't': // 2 strings to match.		case 't': // 2 strings to match.
	if (memcmp(BuiltinName.data()+17, "estnzcp", 7))		if (memcmp(BuiltinName.data()+17, "estnzcp", 7))
	break;		break;
	skipping to change at line 41905		skipping to change at line 53293
	case '6': // 1 string to match.		case '6': // 1 string to match.
	if (BuiltinName[24] != '4')		if (BuiltinName[24] != '4')
	break;		break;
	return Intrinsic::x86_wrgsbase_64; // "__builtin_ia32_wrgsbase 64"		return Intrinsic::x86_wrgsbase_64; // "__builtin_ia32_wrgsbase 64"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 26: // 73 strings to match.		case 26: // 89 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))		if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
	break;		break;
	switch (BuiltinName[15]) {		switch (BuiltinName[15]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+16, "ddsubp", 6))		if (memcmp(BuiltinName.data()+16, "ddsubp", 6))
	break;		break;
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	skipping to change at line 41940		skipping to change at line 53328
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "256", 3))		if (memcmp(BuiltinName.data()+23, "256", 3))
	break;		break;
	return Intrinsic::x86_avx_blendv_pd_256; // "__builtin_ia32_ blendvpd256"		return Intrinsic::x86_avx_blendv_pd_256; // "__builtin_ia32_ blendvpd256"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "256", 3))		if (memcmp(BuiltinName.data()+23, "256", 3))
	break;		break;
	return Intrinsic::x86_avx_blendv_ps_256; // "__builtin_ia32_ blendvps256"		return Intrinsic::x86_avx_blendv_ps_256; // "__builtin_ia32_ blendvps256"
	}		}
	break;		break;
	case 'c': // 8 strings to match.		case 'c': // 14 strings to match.
	if (memcmp(BuiltinName.data()+16, "vt", 2))		if (memcmp(BuiltinName.data()+16, "vt", 2))
	break;		break;
	switch (BuiltinName[18]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'd': // 2 strings to match.		case 'd': // 3 strings to match.
	if (memcmp(BuiltinName.data()+19, "q2p", 3))		if (memcmp(BuiltinName.data()+19, "q2p", 3))
	break;		break;
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "256", 3))		if (memcmp(BuiltinName.data()+23, "256", 3))
	break;		break;
	return Intrinsic::x86_avx_cvtdq2_pd_256; // "__builtin_ia32_ cvtdq2pd256"		return Intrinsic::x86_avx_cvtdq2_pd_256; // "__builtin_ia32_ cvtdq2pd256"
	case 's': // 1 string to match.		case 's': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "256", 3))		switch (BuiltinName[23]) {
	break;		default: break;
	return Intrinsic::x86_avx_cvtdq2_ps_256; // "__builtin_ia32_		case '2': // 1 string to match.
	cvtdq2ps256"		if (memcmp(BuiltinName.data()+24, "56", 2))
			break;
			return Intrinsic::x86_avx_cvtdq2_ps_256; // "__builtin_ia32_
			cvtdq2ps256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "12", 2))
			break;
			return Intrinsic::x86_avx512_cvtdq2_ps_512; // "__built
			in_ia32_cvtdq2ps512"
			}
			break;
	}		}
	break;		break;
	case 'p': // 4 strings to match.		case 'p': // 5 strings to match.
	switch (BuiltinName[19]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'd': // 2 strings to match.		case 'd': // 2 strings to match.
	if (BuiltinName[20] != '2')		if (BuiltinName[20] != '2')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "q256", 4))		if (memcmp(BuiltinName.data()+22, "q256", 4))
	break;		break;
	return Intrinsic::x86_avx_cvt_pd2dq_256; // "__builtin_ia32_ cvtpd2dq256"		return Intrinsic::x86_avx_cvt_pd2dq_256; // "__builtin_ia32_ cvtpd2dq256"
	case 'p': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "s256", 4))		if (memcmp(BuiltinName.data()+22, "s256", 4))
	break;		break;
	return Intrinsic::x86_avx_cvt_pd2_ps_256; // "__builtin_ia32_ cvtpd2ps256"		return Intrinsic::x86_avx_cvt_pd2_ps_256; // "__builtin_ia32_ cvtpd2ps256"
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 's': // 3 strings to match.
	if (BuiltinName[20] != '2')		if (BuiltinName[20] != '2')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "q256", 4))		if (BuiltinName[22] != 'q')
	break;		break;
	return Intrinsic::x86_avx_cvt_ps2dq_256; // "__builtin_ia32_		switch (BuiltinName[23]) {
	cvtps2dq256"		default: break;
			case '2': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "56", 2))
			break;
			return Intrinsic::x86_avx_cvt_ps2dq_256; // "__builtin_ia32_
			cvtps2dq256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "12", 2))
			break;
			return Intrinsic::x86_avx512_cvt_ps2dq_512; // "__built
			in_ia32_cvtps2dq512"
			}
			break;
	case 'p': // 1 string to match.		case 'p': // 1 string to match.
	if (memcmp(BuiltinName.data()+22, "d256", 4))		if (memcmp(BuiltinName.data()+22, "d256", 4))
	break;		break;
	return Intrinsic::x86_avx_cvt_ps2_pd_256; // "__builtin_ia32_ cvtps2pd256"		return Intrinsic::x86_avx_cvt_ps2_pd_256; // "__builtin_ia32_ cvtps2pd256"
	}		}
	break;		break;
	}		}
	break;		break;
			case 's': // 2 strings to match.
			switch (BuiltinName[19]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "2usi64", 6))
			break;
			return Intrinsic::x86_avx512_cvtsd2usi64; // "__builtin_ia32_
			cvtsd2usi64"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+20, "2usi64", 6))
			break;
			return Intrinsic::x86_avx512_cvtss2usi64; // "__builtin_ia32_
			cvtss2usi64"
			}
			break;
	case 't': // 2 strings to match.		case 't': // 2 strings to match.
	if (BuiltinName[19] != 's')		if (BuiltinName[19] != 's')
	break;		break;
	switch (BuiltinName[20]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+21, "2si64", 5))		if (memcmp(BuiltinName.data()+21, "2si64", 5))
	break;		break;
	return Intrinsic::x86_sse2_cvttsd2si64; // "__builtin_ia32_ cvttsd2si64"		return Intrinsic::x86_sse2_cvttsd2si64; // "__builtin_ia32_ cvttsd2si64"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+21, "2si64", 5))		if (memcmp(BuiltinName.data()+21, "2si64", 5))
	break;		break;
	return Intrinsic::x86_sse_cvttss2si64; // "__builtin_ia32_ cvttss2si64"		return Intrinsic::x86_sse_cvttss2si64; // "__builtin_ia32_ cvttss2si64"
	}		}
	break;		break;
			case 'u': // 2 strings to match.
			if (memcmp(BuiltinName.data()+19, "si642s", 6))
			break;
			switch (BuiltinName[25]) {
			default: break;
			case 'd': // 1 string to match.
			return Intrinsic::x86_avx512_cvtusi642sd; // "__builtin_ia32_
			cvtusi642sd"
			case 's': // 1 string to match.
			return Intrinsic::x86_avx512_cvtusi642ss; // "__builtin_ia32_
			cvtusi642ss"
			}
			break;
	}		}
	break;		break;
	case 'i': // 1 string to match.		case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "nsertps128", 10))		if (memcmp(BuiltinName.data()+16, "nsertps128", 10))
	break;		break;
	return Intrinsic::x86_sse41_insertps; // "__builtin_ia32_insertps 128"		return Intrinsic::x86_sse41_insertps; // "__builtin_ia32_insertps 128"
	case 'm': // 5 strings to match.		case 'm': // 5 strings to match.
	switch (BuiltinName[16]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'a': // 2 strings to match.
	skipping to change at line 42058		skipping to change at line 53490
	}		}
	break;		break;
	case 'n': // 1 string to match.		case 'n': // 1 string to match.
	if (memcmp(BuiltinName.data()+19, "tdqa256", 7))		if (memcmp(BuiltinName.data()+19, "tdqa256", 7))
	break;		break;
	return Intrinsic::x86_avx2_movntdqa; // "__builtin_ia32_movntdqa 256"		return Intrinsic::x86_avx2_movntdqa; // "__builtin_ia32_movntdqa 256"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'p': // 40 strings to match.		case 'p': // 45 strings to match.
	switch (BuiltinName[16]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'a': // 8 strings to match.		case 'a': // 8 strings to match.
	if (memcmp(BuiltinName.data()+17, "ck", 2))		if (memcmp(BuiltinName.data()+17, "ck", 2))
	break;		break;
	switch (BuiltinName[19]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 's': // 4 strings to match.		case 's': // 4 strings to match.
	if (BuiltinName[20] != 's')		if (BuiltinName[20] != 's')
	break;		break;
	skipping to change at line 42157		skipping to change at line 53589
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "28", 2))		if (memcmp(BuiltinName.data()+24, "28", 2))
	break;		break;
	return Intrinsic::x86_sse41_pblendvb; // "__builtin_ia32_ pblendvb128"		return Intrinsic::x86_sse41_pblendvb; // "__builtin_ia32_ pblendvb128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "56", 2))		if (memcmp(BuiltinName.data()+24, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pblendvb; // "__builtin_ia32_pblendvb 256"		return Intrinsic::x86_avx2_pblendvb; // "__builtin_ia32_pblendvb 256"
	}		}
	break;		break;
	case 'm': // 28 strings to match.		case 'm': // 33 strings to match.
	switch (BuiltinName[17]) {		switch (BuiltinName[17]) {
	default: break;		default: break;
	case 'o': // 26 strings to match.		case 'o': // 31 strings to match.
	if (BuiltinName[18] != 'v')		if (BuiltinName[18] != 'v')
	break;		break;
	switch (BuiltinName[19]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'm': // 2 strings to match.		case 'm': // 2 strings to match.
	if (memcmp(BuiltinName.data()+20, "skb", 3))		if (memcmp(BuiltinName.data()+20, "skb", 3))
	break;		break;
	switch (BuiltinName[23]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	skipping to change at line 42277		skipping to change at line 53709
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "56", 2))		if (memcmp(BuiltinName.data()+24, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pmovsxwq; // "__builtin_ia32_ pmovsxwq256"		return Intrinsic::x86_avx2_pmovsxwq; // "__builtin_ia32_ pmovsxwq256"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'z': // 12 strings to match.		case 'z': // 17 strings to match.
	if (BuiltinName[20] != 'x')		if (BuiltinName[20] != 'x')
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'b': // 6 strings to match.		case 'b': // 8 strings to match.
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'd': // 2 strings to match.		case 'd': // 3 strings to match.
	switch (BuiltinName[23]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "28", 2))		if (memcmp(BuiltinName.data()+24, "28", 2))
	break;		break;
	return Intrinsic::x86_sse41_pmovzxbd; // "__built in_ia32_pmovzxbd128"		return Intrinsic::x86_sse41_pmovzxbd; // "__built in_ia32_pmovzxbd128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "56", 2))		if (memcmp(BuiltinName.data()+24, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pmovzxbd; // "__builtin_ia32_ pmovzxbd256"		return Intrinsic::x86_avx2_pmovzxbd; // "__builtin_ia32_ pmovzxbd256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "12", 2))
			break;
			return Intrinsic::x86_avx512_pmovzxbd; // "__built
			in_ia32_pmovzxbd512"
	}		}
	break;		break;
	case 'q': // 2 strings to match.		case 'q': // 3 strings to match.
	switch (BuiltinName[23]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "28", 2))		if (memcmp(BuiltinName.data()+24, "28", 2))
	break;		break;
	return Intrinsic::x86_sse41_pmovzxbq; // "__built in_ia32_pmovzxbq128"		return Intrinsic::x86_sse41_pmovzxbq; // "__built in_ia32_pmovzxbq128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "56", 2))		if (memcmp(BuiltinName.data()+24, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pmovzxbq; // "__builtin_ia32_ pmovzxbq256"		return Intrinsic::x86_avx2_pmovzxbq; // "__builtin_ia32_ pmovzxbq256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "12", 2))
			break;
			return Intrinsic::x86_avx512_pmovzxbq; // "__built
			in_ia32_pmovzxbq512"
	}		}
	break;		break;
	case 'w': // 2 strings to match.		case 'w': // 2 strings to match.
	switch (BuiltinName[23]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "28", 2))		if (memcmp(BuiltinName.data()+24, "28", 2))
	break;		break;
	return Intrinsic::x86_sse41_pmovzxbw; // "__built in_ia32_pmovzxbw128"		return Intrinsic::x86_sse41_pmovzxbw; // "__built in_ia32_pmovzxbw128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "56", 2))		if (memcmp(BuiltinName.data()+24, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pmovzxbw; // "__builtin_ia32_ pmovzxbw256"		return Intrinsic::x86_avx2_pmovzxbw; // "__builtin_ia32_ pmovzxbw256"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'd': // 2 strings to match.		case 'd': // 3 strings to match.
	if (BuiltinName[22] != 'q')		if (BuiltinName[22] != 'q')
	break;		break;
	switch (BuiltinName[23]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "28", 2))		if (memcmp(BuiltinName.data()+24, "28", 2))
	break;		break;
	return Intrinsic::x86_sse41_pmovzxdq; // "__builtin_ia32_ pmovzxdq128"		return Intrinsic::x86_sse41_pmovzxdq; // "__builtin_ia32_ pmovzxdq128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "56", 2))		if (memcmp(BuiltinName.data()+24, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pmovzxdq; // "__builtin_ia32_ pmovzxdq256"		return Intrinsic::x86_avx2_pmovzxdq; // "__builtin_ia32_ pmovzxdq256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "12", 2))
			break;
			return Intrinsic::x86_avx512_pmovzxdq; // "__builtin_ia32_
			pmovzxdq512"
	}		}
	break;		break;
	case 'w': // 4 strings to match.		case 'w': // 6 strings to match.
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'd': // 2 strings to match.		case 'd': // 3 strings to match.
	switch (BuiltinName[23]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "28", 2))		if (memcmp(BuiltinName.data()+24, "28", 2))
	break;		break;
	return Intrinsic::x86_sse41_pmovzxwd; // "__built in_ia32_pmovzxwd128"		return Intrinsic::x86_sse41_pmovzxwd; // "__built in_ia32_pmovzxwd128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "56", 2))		if (memcmp(BuiltinName.data()+24, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pmovzxwd; // "__builtin_ia32_ pmovzxwd256"		return Intrinsic::x86_avx2_pmovzxwd; // "__builtin_ia32_ pmovzxwd256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "12", 2))
			break;
			return Intrinsic::x86_avx512_pmovzxwd; // "__built
			in_ia32_pmovzxwd512"
	}		}
	break;		break;
	case 'q': // 2 strings to match.		case 'q': // 3 strings to match.
	switch (BuiltinName[23]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "28", 2))		if (memcmp(BuiltinName.data()+24, "28", 2))
	break;		break;
	return Intrinsic::x86_sse41_pmovzxwq; // "__built in_ia32_pmovzxwq128"		return Intrinsic::x86_sse41_pmovzxwq; // "__built in_ia32_pmovzxwq128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "56", 2))		if (memcmp(BuiltinName.data()+24, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pmovzxwq; // "__builtin_ia32_ pmovzxwq256"		return Intrinsic::x86_avx2_pmovzxwq; // "__builtin_ia32_ pmovzxwq256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "12", 2))
			break;
			return Intrinsic::x86_avx512_pmovzxwq; // "__built
			in_ia32_pmovzxwq512"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'u': // 2 strings to match.		case 'u': // 2 strings to match.
	if (memcmp(BuiltinName.data()+18, "lhrsw", 5))		if (memcmp(BuiltinName.data()+18, "lhrsw", 5))
	skipping to change at line 42410		skipping to change at line 53862
	break;		break;
	return Intrinsic::x86_sse41_ptestnzc; // "__builtin_ia32_ ptestnzc128"		return Intrinsic::x86_sse41_ptestnzc; // "__builtin_ia32_ ptestnzc128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "56", 2))		if (memcmp(BuiltinName.data()+24, "56", 2))
	break;		break;
	return Intrinsic::x86_avx_ptestnzc_256; // "__builtin_ia32_ ptestnzc256"		return Intrinsic::x86_avx_ptestnzc_256; // "__builtin_ia32_ ptestnzc256"
	}		}
	break;		break;
	}		}
	break;		break;
	case 's': // 3 strings to match.		case 's': // 4 strings to match.
	if (memcmp(BuiltinName.data()+16, "tore", 4))		switch (BuiltinName[16]) {
	break;
	switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'h': // 1 string to match.
	if (memcmp(BuiltinName.data()+21, "qu256", 5))		if (memcmp(BuiltinName.data()+17, "a256rnds2", 9))
	break;		break;
	return Intrinsic::x86_avx_storeu_dq_256; // "__builtin_ia32_		return Intrinsic::x86_sha256rnds2; // "__builtin_ia32_sha256rn
	storedqu256"		ds2"
	case 'u': // 2 strings to match.		case 't': // 3 strings to match.
	if (BuiltinName[21] != 'p')		if (memcmp(BuiltinName.data()+17, "ore", 3))
	break;		break;
	switch (BuiltinName[22]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "256", 3))		if (memcmp(BuiltinName.data()+21, "qu256", 5))
	break;		break;
	return Intrinsic::x86_avx_storeu_pd_256; // "__builtin_ia32_		return Intrinsic::x86_avx_storeu_dq_256; // "__builtin_ia32_
	storeupd256"		storedqu256"
	case 's': // 1 string to match.		case 'u': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "256", 3))		if (BuiltinName[21] != 'p')
	break;		break;
	return Intrinsic::x86_avx_storeu_ps_256; // "__builtin_ia32_		switch (BuiltinName[22]) {
	storeups256"		default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "256", 3))
			break;
			return Intrinsic::x86_avx_storeu_pd_256; // "__builtin_ia32_
			storeupd256"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "256", 3))
			break;
			return Intrinsic::x86_avx_storeu_ps_256; // "__builtin_ia32_
			storeups256"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'v': // 12 strings to match.		case 'v': // 16 strings to match.
	switch (BuiltinName[16]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'f': // 8 strings to match.		case 'f': // 12 strings to match.
	if (BuiltinName[17] != 'm')		if (BuiltinName[17] != 'm')
	break;		break;
	switch (BuiltinName[18]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'a': // 4 strings to match.		case 'a': // 6 strings to match.
	if (memcmp(BuiltinName.data()+19, "dd", 2))		if (memcmp(BuiltinName.data()+19, "dd", 2))
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'p': // 2 strings to match.		case 'p': // 4 strings to match.
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "256", 3))		switch (BuiltinName[23]) {
	break;		default: break;
	return Intrinsic::x86_fma_vfmadd_pd_256; // "__builtin_ia32_		case '2': // 1 string to match.
	vfmaddpd256"		if (memcmp(BuiltinName.data()+24, "56", 2))
	case 's': // 1 string to match.		break;
	if (memcmp(BuiltinName.data()+23, "256", 3))		return Intrinsic::x86_fma_vfmadd_pd_256; // "__built
	break;		in_ia32_vfmaddpd256"
	return Intrinsic::x86_fma_vfmadd_ps_256; // "__builtin_ia32_		case '5': // 1 string to match.
	vfmaddps256"		if (memcmp(BuiltinName.data()+24, "12", 2))
			break;
			return Intrinsic::x86_fma_vfmadd_pd_512; // "__built
			in_ia32_vfmaddpd512"
			}
			break;
			case 's': // 2 strings to match.
			switch (BuiltinName[23]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "56", 2))
			break;
			return Intrinsic::x86_fma_vfmadd_ps_256; // "__built
			in_ia32_vfmaddps256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "12", 2))
			break;
			return Intrinsic::x86_fma_vfmadd_ps_512; // "__built
			in_ia32_vfmaddps512"
			}
			break;
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 's': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "ubp", 3))		if (memcmp(BuiltinName.data()+22, "ubp", 3))
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::x86_fma_vfmaddsub_pd; // "__builtin_ia32_ vfmaddsubpd"		return Intrinsic::x86_fma_vfmaddsub_pd; // "__builtin_ia32_ vfmaddsubpd"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	return Intrinsic::x86_fma_vfmaddsub_ps; // "__builtin_ia32_ vfmaddsubps"		return Intrinsic::x86_fma_vfmaddsub_ps; // "__builtin_ia32_ vfmaddsubps"
	}		}
	break;		break;
	}		}
	break;		break;
	case 's': // 4 strings to match.		case 's': // 6 strings to match.
	if (memcmp(BuiltinName.data()+19, "ub", 2))		if (memcmp(BuiltinName.data()+19, "ub", 2))
	break;		break;
	switch (BuiltinName[21]) {		switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+22, "ddp", 3))		if (memcmp(BuiltinName.data()+22, "ddp", 3))
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::x86_fma_vfmsubadd_pd; // "__builtin_ia32_ vfmsubaddpd"		return Intrinsic::x86_fma_vfmsubadd_pd; // "__builtin_ia32_ vfmsubaddpd"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	return Intrinsic::x86_fma_vfmsubadd_ps; // "__builtin_ia32_ vfmsubaddps"		return Intrinsic::x86_fma_vfmsubadd_ps; // "__builtin_ia32_ vfmsubaddps"
	}		}
	break;		break;
	case 'p': // 2 strings to match.		case 'p': // 4 strings to match.
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 2 strings to match.
	if (memcmp(BuiltinName.data()+23, "256", 3))		switch (BuiltinName[23]) {
	break;		default: break;
	return Intrinsic::x86_fma_vfmsub_pd_256; // "__builtin_ia32_		case '2': // 1 string to match.
	vfmsubpd256"		if (memcmp(BuiltinName.data()+24, "56", 2))
	case 's': // 1 string to match.		break;
	if (memcmp(BuiltinName.data()+23, "256", 3))		return Intrinsic::x86_fma_vfmsub_pd_256; // "__built
	break;		in_ia32_vfmsubpd256"
	return Intrinsic::x86_fma_vfmsub_ps_256; // "__builtin_ia32_		case '5': // 1 string to match.
	vfmsubps256"		if (memcmp(BuiltinName.data()+24, "12", 2))
			break;
			return Intrinsic::x86_fma_vfmsub_pd_512; // "__built
			in_ia32_vfmsubpd512"
			}
			break;
			case 's': // 2 strings to match.
			switch (BuiltinName[23]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "56", 2))
			break;
			return Intrinsic::x86_fma_vfmsub_ps_256; // "__built
			in_ia32_vfmsubps256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "12", 2))
			break;
			return Intrinsic::x86_fma_vfmsub_ps_512; // "__built
			in_ia32_vfmsubps512"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 't': // 4 strings to match.		case 't': // 4 strings to match.
	if (memcmp(BuiltinName.data()+17, "est", 3))		if (memcmp(BuiltinName.data()+17, "est", 3))
	break;		break;
	switch (BuiltinName[20]) {		switch (BuiltinName[20]) {
			default: break;
			case 'c': // 2 strings to match.
			if (BuiltinName[21] != 'p')
			break;
			switch (BuiltinName[22]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "256", 3))
			break;
			return Intrinsic::x86_avx_vtestc_pd_256; // "__builtin_ia32_
			vtestcpd256"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "256", 3))
			break;
			return Intrinsic::x86_avx_vtestc_ps_256; // "__builtin_ia32_
			vtestcps256"
			}
			break;
			case 'z': // 2 strings to match.
			if (BuiltinName[21] != 'p')
			break;
			switch (BuiltinName[22]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "256", 3))
			break;
			return Intrinsic::x86_avx_vtestz_pd_256; // "__builtin_ia32_
			vtestzpd256"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "256", 3))
			break;
			return Intrinsic::x86_avx_vtestz_ps_256; // "__builtin_ia32_
			vtestzps256"
			}
			break;
			}
			break;
			}
			break;
			}
			break;
			case 27: // 53 strings to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
			break;
			switch (BuiltinName[15]) {
			default: break;
			case 'c': // 6 strings to match.
			switch (BuiltinName[16]) {
			default: break;
			case 'o': // 2 strings to match.
			if (memcmp(BuiltinName.data()+17, "nflict", 6))
			break;
			switch (BuiltinName[23]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "512", 3))
			break;
			return Intrinsic::x86_avx512_conflict_d_512; // "__builtin_ia32_
			conflictd512"
			case 'q': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "512", 3))
			break;
			return Intrinsic::x86_avx512_conflict_q_512; // "__builtin_ia32_
			conflictq512"
			}
			break;
			case 'v': // 4 strings to match.
			if (memcmp(BuiltinName.data()+17, "tt", 2))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case 'p': // 2 strings to match.
			switch (BuiltinName[20]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+21, "2dq256", 6))
			break;
			return Intrinsic::x86_avx_cvtt_pd2dq_256; // "__builtin_ia32_
			cvttpd2dq256"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+21, "2dq256", 6))
			break;
			return Intrinsic::x86_avx_cvtt_ps2dq_256; // "__builtin_ia32_
			cvttps2dq256"
			}
			break;
			case 's': // 2 strings to match.
			switch (BuiltinName[20]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+21, "2usi64", 6))
			break;
			return Intrinsic::x86_avx512_cvttsd2usi64; // "__builtin_ia32_
			cvttsd2usi64"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+21, "2usi64", 6))
			break;
			return Intrinsic::x86_avx512_cvttss2usi64; // "__builtin_ia32_
			cvttss2usi64"
			}
			break;
			}
			break;
			}
			break;
			case 'e': // 1 string to match.
			if (memcmp(BuiltinName.data()+16, "xtractps128", 11))
			break;
			return Intrinsic::x86_sse41_extractps; // "__builtin_ia32_extractp
			s128"
			case 'g': // 12 strings to match.
			if (memcmp(BuiltinName.data()+16, "ather", 5))
			break;
			switch (BuiltinName[21]) {
			default: break;
			case 'd': // 6 strings to match.
			switch (BuiltinName[22]) {
			default: break;
			case '_': // 2 strings to match.
			switch (BuiltinName[23]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "256", 3))
			break;
			return Intrinsic::x86_avx2_gather_d_d_256; // "__builtin_ia32_
			gatherd_d256"
			case 'q': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "256", 3))
			break;
			return Intrinsic::x86_avx2_gather_d_q_256; // "__builtin_ia32_
			gatherd_q256"
			}
			break;
			case 'p': // 4 strings to match.
			switch (BuiltinName[23]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "512", 3))
			break;
			return Intrinsic::x86_avx512_gather_dpd_512; // "__built
			in_ia32_gatherdpd512"
			case 'i': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "512", 3))
			break;
			return Intrinsic::x86_avx512_gather_dpi_512; // "__built
			in_ia32_gatherdpi512"
			case 'q': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "512", 3))
			break;
			return Intrinsic::x86_avx512_gather_dpq_512; // "__built
			in_ia32_gatherdpq512"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "512", 3))
			break;
			return Intrinsic::x86_avx512_gather_dps_512; // "__built
			in_ia32_gatherdps512"
			}
			break;
			}
			break;
			case 'q': // 6 strings to match.
			switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'c': // 2 strings to match.		case '_': // 2 strings to match.
	if (BuiltinName[21] != 'p')		switch (BuiltinName[23]) {
	break;
	switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "256", 3))		if (memcmp(BuiltinName.data()+24, "256", 3))
	break;		break;
	return Intrinsic::x86_avx_vtestc_pd_256; // "__builtin_ia32_		return Intrinsic::x86_avx2_gather_q_d_256; // "__builtin_ia32_
	vtestcpd256"		gatherq_d256"
	case 's': // 1 string to match.		case 'q': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "256", 3))		if (memcmp(BuiltinName.data()+24, "256", 3))
	break;		break;
	return Intrinsic::x86_avx_vtestc_ps_256; // "__builtin_ia32_ vtestcps256"		return Intrinsic::x86_avx2_gather_q_q_256; // "__builtin_ia32_ gatherq_q256"
	}		}
	break;		break;
	case 'z': // 2 strings to match.		case 'p': // 4 strings to match.
	if (BuiltinName[21] != 'p')		switch (BuiltinName[23]) {
	break;
	switch (BuiltinName[22]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "256", 3))		if (memcmp(BuiltinName.data()+24, "512", 3))
	break;		break;
	return Intrinsic::x86_avx_vtestz_pd_256; // "__builtin_ia32_		return Intrinsic::x86_avx512_gather_qpd_512; // "__built
	vtestzpd256"		in_ia32_gatherqpd512"
			case 'i': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "512", 3))
			break;
			return Intrinsic::x86_avx512_gather_qpi_512; // "__built
			in_ia32_gatherqpi512"
			case 'q': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "512", 3))
			break;
			return Intrinsic::x86_avx512_gather_qpq_512; // "__built
			in_ia32_gatherqpq512"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "256", 3))		if (memcmp(BuiltinName.data()+24, "512", 3))
	break;		break;
	return Intrinsic::x86_avx_vtestz_ps_256; // "__builtin_ia32_ vtestzps256"		return Intrinsic::x86_avx512_gather_qps_512; // "__built in_ia32_gatherqps512"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		case 'm': // 4 strings to match.
	break;		switch (BuiltinName[16]) {
	case 27: // 29 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
	break;
	switch (BuiltinName[15]) {
	default: break;
	case 'c': // 2 strings to match.
	if (memcmp(BuiltinName.data()+16, "vttp", 4))
	break;
	switch (BuiltinName[20]) {
	default: break;
	case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+21, "2dq256", 6))
	break;
	return Intrinsic::x86_avx_cvtt_pd2dq_256; // "__builtin_ia32_
	cvttpd2dq256"
	case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+21, "2dq256", 6))
	break;
	return Intrinsic::x86_avx_cvtt_ps2dq_256; // "__builtin_ia32_
	cvttps2dq256"
	}
	break;
	case 'e': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "xtractps128", 11))
	break;
	return Intrinsic::x86_sse41_extractps; // "__builtin_ia32_extractp
	s128"
	case 'g': // 4 strings to match.
	if (memcmp(BuiltinName.data()+16, "ather", 5))
	break;
	switch (BuiltinName[21]) {
	default: break;		default: break;
	case 'd': // 2 strings to match.		case 'a': // 2 strings to match.
	if (BuiltinName[22] != '_')		if (memcmp(BuiltinName.data()+17, "skload", 6))
	break;		break;
	switch (BuiltinName[23]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "256", 3))		if (memcmp(BuiltinName.data()+24, "256", 3))
	break;		break;
	return Intrinsic::x86_avx2_gather_d_d_256; // "__builtin_ia32_ gatherd_d256"		return Intrinsic::x86_avx2_maskload_d_256; // "__builtin_ia32_ maskloadd256"
	case 'q': // 1 string to match.		case 'q': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "256", 3))		if (memcmp(BuiltinName.data()+24, "256", 3))
	break;		break;
	return Intrinsic::x86_avx2_gather_d_q_256; // "__builtin_ia32_ gatherd_q256"		return Intrinsic::x86_avx2_maskload_q_256; // "__builtin_ia32_ maskloadq256"
	}		}
	break;		break;
	case 'q': // 2 strings to match.		case 's': // 2 strings to match.
	if (BuiltinName[22] != '_')		if (memcmp(BuiltinName.data()+17, "kblend", 6))
	break;		break;
	switch (BuiltinName[23]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "256", 3))		if (memcmp(BuiltinName.data()+24, "512", 3))
	break;		break;
	return Intrinsic::x86_avx2_gather_q_d_256; // "__builtin_ia32_ gatherq_d256"		return Intrinsic::x86_avx512_mskblend_d_512; // "__builtin_ia32_ mskblendd512"
	case 'q': // 1 string to match.		case 'q': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "256", 3))		if (memcmp(BuiltinName.data()+24, "512", 3))
	break;		break;
	return Intrinsic::x86_avx2_gather_q_q_256; // "__builtin_ia32_ gatherq_q256"		return Intrinsic::x86_avx512_mskblend_q_512; // "__builtin_ia32_ mskblendq512"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'm': // 2 strings to match.
	if (memcmp(BuiltinName.data()+16, "askload", 7))
	break;
	switch (BuiltinName[23]) {
	default: break;
	case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "256", 3))
	break;
	return Intrinsic::x86_avx2_maskload_d_256; // "__builtin_ia32_
	maskloadd256"
	case 'q': // 1 string to match.
	if (memcmp(BuiltinName.data()+24, "256", 3))
	break;
	return Intrinsic::x86_avx2_maskload_q_256; // "__builtin_ia32_
	maskloadq256"
	}
	break;
	case 'p': // 9 strings to match.		case 'p': // 9 strings to match.
	switch (BuiltinName[16]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'c': // 5 strings to match.		case 'c': // 5 strings to match.
	switch (BuiltinName[17]) {		switch (BuiltinName[17]) {
	default: break;		default: break;
	case 'l': // 1 string to match.		case 'l': // 1 string to match.
	if (memcmp(BuiltinName.data()+18, "mulqdq128", 9))		if (memcmp(BuiltinName.data()+18, "mulqdq128", 9))
	break;		break;
	return Intrinsic::x86_pclmulqdq; // "__builtin_ia32_pclmulqd q128"		return Intrinsic::x86_pclmulqdq; // "__builtin_ia32_pclmulqd q128"
	skipping to change at line 42706		skipping to change at line 54309
	break;		break;
	return Intrinsic::x86_ssse3_pmadd_ub_sw_128; // "__builtin_ia32_ pmaddubsw128"		return Intrinsic::x86_ssse3_pmadd_ub_sw_128; // "__builtin_ia32_ pmaddubsw128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "56", 2))		if (memcmp(BuiltinName.data()+25, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pmadd_ub_sw; // "__builtin_ia32_ pmaddubsw256"		return Intrinsic::x86_avx2_pmadd_ub_sw; // "__builtin_ia32_ pmaddubsw256"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'v': // 11 strings to match.		case 'r': // 4 strings to match.
			if (memcmp(BuiltinName.data()+16, "sqrt", 4))
			break;
			switch (BuiltinName[20]) {
			default: break;
			case '1': // 2 strings to match.
			if (memcmp(BuiltinName.data()+21, "4p", 2))
			break;
			switch (BuiltinName[23]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "512", 3))
			break;
			return Intrinsic::x86_avx512_rsqrt14_pd_512; // "__builtin_ia32_
			rsqrt14pd512"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "512", 3))
			break;
			return Intrinsic::x86_avx512_rsqrt14_ps_512; // "__builtin_ia32_
			rsqrt14ps512"
			}
			break;
			case '2': // 2 strings to match.
			if (memcmp(BuiltinName.data()+21, "8p", 2))
			break;
			switch (BuiltinName[23]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "512", 3))
			break;
			return Intrinsic::x86_avx512_rsqrt28_pd_512; // "__builtin_ia32_
			rsqrt28pd512"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+24, "512", 3))
			break;
			return Intrinsic::x86_avx512_rsqrt28_ps_512; // "__builtin_ia32_
			rsqrt28ps512"
			}
			break;
			}
			break;
			case 'v': // 17 strings to match.
	switch (BuiltinName[16]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'b': // 1 string to match.		case 'b': // 1 string to match.
	if (memcmp(BuiltinName.data()+17, "roadcastss", 10))		if (memcmp(BuiltinName.data()+17, "roadcastss", 10))
	break;		break;
	return Intrinsic::x86_avx_vbroadcast_ss; // "__builtin_ia32_ vbroadcastss"		return Intrinsic::x86_avx_vbroadcast_ss; // "__builtin_ia32_ vbroadcastss"
	case 'c': // 2 strings to match.		case 'c': // 4 strings to match.
	if (memcmp(BuiltinName.data()+17, "vtp", 3))		if (memcmp(BuiltinName.data()+17, "vtp", 3))
	break;		break;
	switch (BuiltinName[20]) {		switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'h': // 1 string to match.		case 'h': // 2 strings to match.
	if (memcmp(BuiltinName.data()+21, "2ps256", 6))		if (memcmp(BuiltinName.data()+21, "2ps", 3))
	break;		break;
	return Intrinsic::x86_vcvtph2ps_256; // "__builtin_ia32_vcvtph2p		switch (BuiltinName[24]) {
	s256"		default: break;
	case 's': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+21, "2ph256", 6))		if (memcmp(BuiltinName.data()+25, "56", 2))
			break;
			return Intrinsic::x86_vcvtph2ps_256; // "__builtin_ia32_
			vcvtph2ps256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "12", 2))
			break;
			return Intrinsic::x86_avx512_vcvtph2ps_512; // "__built
			in_ia32_vcvtph2ps512"
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(BuiltinName.data()+21, "2ph", 3))
	break;		break;
	return Intrinsic::x86_vcvtps2ph_256; // "__builtin_ia32_vcvtps2p		switch (BuiltinName[24]) {
	h256"		default: break;
			case '2': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "56", 2))
			break;
			return Intrinsic::x86_vcvtps2ph_256; // "__builtin_ia32_
			vcvtps2ph256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "12", 2))
			break;
			return Intrinsic::x86_avx512_vcvtps2ph_512; // "__built
			in_ia32_vcvtps2ph512"
			}
			break;
	}		}
	break;		break;
	case 'e': // 2 strings to match.		case 'e': // 2 strings to match.
	if (memcmp(BuiltinName.data()+17, "c_", 2))		if (memcmp(BuiltinName.data()+17, "c_", 2))
	break;		break;
	switch (BuiltinName[19]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'e': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "xt_v4hi", 7))		if (memcmp(BuiltinName.data()+20, "xt_v4hi", 7))
	break;		break;
	return Intrinsic::x86_mmx_pextr_w; // "__builtin_ia32_vec_ext_ v4hi"		return Intrinsic::x86_mmx_pextr_w; // "__builtin_ia32_vec_ext_ v4hi"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+20, "et_v4hi", 7))		if (memcmp(BuiltinName.data()+20, "et_v4hi", 7))
	break;		break;
	return Intrinsic::x86_mmx_pinsr_w; // "__builtin_ia32_vec_set_ v4hi"		return Intrinsic::x86_mmx_pinsr_w; // "__builtin_ia32_vec_set_ v4hi"
	}		}
	break;		break;
	case 'f': // 4 strings to match.		case 'f': // 8 strings to match.
	if (memcmp(BuiltinName.data()+17, "nm", 2))		if (memcmp(BuiltinName.data()+17, "nm", 2))
	break;		break;
	switch (BuiltinName[19]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'a': // 4 strings to match.
	if (memcmp(BuiltinName.data()+20, "ddp", 3))		if (memcmp(BuiltinName.data()+20, "ddp", 3))
	break;		break;
	switch (BuiltinName[23]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 2 strings to match.
	if (memcmp(BuiltinName.data()+24, "256", 3))		switch (BuiltinName[24]) {
	break;		default: break;
	return Intrinsic::x86_fma_vfnmadd_pd_256; // "__builtin_ia32_		case '2': // 1 string to match.
	vfnmaddpd256"		if (memcmp(BuiltinName.data()+25, "56", 2))
	case 's': // 1 string to match.		break;
	if (memcmp(BuiltinName.data()+24, "256", 3))		return Intrinsic::x86_fma_vfnmadd_pd_256; // "__built
	break;		in_ia32_vfnmaddpd256"
	return Intrinsic::x86_fma_vfnmadd_ps_256; // "__builtin_ia32_		case '5': // 1 string to match.
	vfnmaddps256"		if (memcmp(BuiltinName.data()+25, "12", 2))
			break;
			return Intrinsic::x86_fma_vfnmadd_pd_512; // "__built
			in_ia32_vfnmaddpd512"
			}
			break;
			case 's': // 2 strings to match.
			switch (BuiltinName[24]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "56", 2))
			break;
			return Intrinsic::x86_fma_vfnmadd_ps_256; // "__built
			in_ia32_vfnmaddps256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "12", 2))
			break;
			return Intrinsic::x86_fma_vfnmadd_ps_512; // "__built
			in_ia32_vfnmaddps512"
			}
			break;
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 's': // 4 strings to match.
	if (memcmp(BuiltinName.data()+20, "ubp", 3))		if (memcmp(BuiltinName.data()+20, "ubp", 3))
	break;		break;
	switch (BuiltinName[23]) {		switch (BuiltinName[23]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 2 strings to match.
	if (memcmp(BuiltinName.data()+24, "256", 3))		switch (BuiltinName[24]) {
	break;		default: break;
	return Intrinsic::x86_fma_vfnmsub_pd_256; // "__builtin_ia32_		case '2': // 1 string to match.
	vfnmsubpd256"		if (memcmp(BuiltinName.data()+25, "56", 2))
	case 's': // 1 string to match.		break;
	if (memcmp(BuiltinName.data()+24, "256", 3))		return Intrinsic::x86_fma_vfnmsub_pd_256; // "__built
	break;		in_ia32_vfnmsubpd256"
	return Intrinsic::x86_fma_vfnmsub_ps_256; // "__builtin_ia32_		case '5': // 1 string to match.
	vfnmsubps256"		if (memcmp(BuiltinName.data()+25, "12", 2))
			break;
			return Intrinsic::x86_fma_vfnmsub_pd_512; // "__built
			in_ia32_vfnmsubpd512"
			}
			break;
			case 's': // 2 strings to match.
			switch (BuiltinName[24]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "56", 2))
			break;
			return Intrinsic::x86_fma_vfnmsub_ps_256; // "__built
			in_ia32_vfnmsubps256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "12", 2))
			break;
			return Intrinsic::x86_fma_vfnmsub_ps_512; // "__built
			in_ia32_vfnmsubps512"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 'p': // 2 strings to match.		case 'p': // 2 strings to match.
	if (memcmp(BuiltinName.data()+17, "ermilvarp", 9))		if (memcmp(BuiltinName.data()+17, "ermilvarp", 9))
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	return Intrinsic::x86_avx_vpermilvar_pd; // "__builtin_ia32_ vpermilvarpd"		return Intrinsic::x86_avx_vpermilvar_pd; // "__builtin_ia32_ vpermilvarpd"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	return Intrinsic::x86_avx_vpermilvar_ps; // "__builtin_ia32_ vpermilvarps"		return Intrinsic::x86_avx_vpermilvar_ps; // "__builtin_ia32_ vpermilvarps"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 28: // 24 strings to match.		case 28: // 36 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))		if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
	break;		break;
	switch (BuiltinName[15]) {		switch (BuiltinName[15]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'a': // 2 strings to match.
	if (memcmp(BuiltinName.data()+16, "es", 2))		if (memcmp(BuiltinName.data()+16, "es", 2))
	break;		break;
	switch (BuiltinName[18]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	skipping to change at line 42856		skipping to change at line 54554
	break;		break;
	return Intrinsic::x86_avx2_gather_q_ps_256; // "__builtin_ia32_ gatherq_ps256"		return Intrinsic::x86_avx2_gather_q_ps_256; // "__builtin_ia32_ gatherq_ps256"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'i': // 1 string to match.		case 'i': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "nsert128i256", 12))		if (memcmp(BuiltinName.data()+16, "nsert128i256", 12))
	break;		break;
	return Intrinsic::x86_avx2_vinserti128; // "__builtin_ia32_insert12 8i256"		return Intrinsic::x86_avx2_vinserti128; // "__builtin_ia32_insert12 8i256"
	case 'm': // 4 strings to match.		case 'm': // 6 strings to match.
	if (memcmp(BuiltinName.data()+16, "ask", 3))		switch (BuiltinName[16]) {
	break;
	switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'l': // 2 strings to match.		case 'a': // 4 strings to match.
	if (memcmp(BuiltinName.data()+20, "oadp", 4))		if (memcmp(BuiltinName.data()+17, "sk", 2))
	break;		break;
	switch (BuiltinName[24]) {		switch (BuiltinName[19]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'l': // 2 strings to match.
	if (memcmp(BuiltinName.data()+25, "256", 3))		if (memcmp(BuiltinName.data()+20, "oadp", 4))
	break;		break;
	return Intrinsic::x86_avx_maskload_pd_256; // "__builtin_ia32_		switch (BuiltinName[24]) {
	maskloadpd256"		default: break;
	case 's': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "256", 3))		if (memcmp(BuiltinName.data()+25, "256", 3))
			break;
			return Intrinsic::x86_avx_maskload_pd_256; // "__builtin_ia32_
			maskloadpd256"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "256", 3))
			break;
			return Intrinsic::x86_avx_maskload_ps_256; // "__builtin_ia32_
			maskloadps256"
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(BuiltinName.data()+20, "tore", 4))
	break;		break;
	return Intrinsic::x86_avx_maskload_ps_256; // "__builtin_ia32_		switch (BuiltinName[24]) {
	maskloadps256"		default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "256", 3))
			break;
			return Intrinsic::x86_avx2_maskstore_d_256; // "__built
			in_ia32_maskstored256"
			case 'q': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "256", 3))
			break;
			return Intrinsic::x86_avx2_maskstore_q_256; // "__built
			in_ia32_maskstoreq256"
			}
			break;
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 's': // 2 strings to match.
	if (memcmp(BuiltinName.data()+20, "tore", 4))		if (memcmp(BuiltinName.data()+17, "kblendp", 7))
	break;		break;
	switch (BuiltinName[24]) {		switch (BuiltinName[24]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "256", 3))		if (memcmp(BuiltinName.data()+25, "512", 3))
	break;		break;
	return Intrinsic::x86_avx2_maskstore_d_256; // "__builtin_ia32_		return Intrinsic::x86_avx512_mskblend_pd_512; // "__built
	maskstored256"		in_ia32_mskblendpd512"
	case 'q': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "256", 3))		if (memcmp(BuiltinName.data()+25, "512", 3))
	break;		break;
	return Intrinsic::x86_avx2_maskstore_q_256; // "__builtin_ia32_ maskstoreq256"		return Intrinsic::x86_avx512_mskblend_ps_512; // "__built in_ia32_mskblendps512"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'p': // 11 strings to match.		case 'p': // 11 strings to match.
	switch (BuiltinName[16]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'c': // 10 strings to match.		case 'c': // 10 strings to match.
	if (memcmp(BuiltinName.data()+17, "mp", 2))		if (memcmp(BuiltinName.data()+17, "mp", 2))
	break;		break;
	skipping to change at line 42963		skipping to change at line 54681
	}		}
	break;		break;
	}		}
	break;		break;
	case 'h': // 1 string to match.		case 'h': // 1 string to match.
	if (memcmp(BuiltinName.data()+17, "minposuw128", 11))		if (memcmp(BuiltinName.data()+17, "minposuw128", 11))
	break;		break;
	return Intrinsic::x86_sse41_phminposuw; // "__builtin_ia32_ phminposuw128"		return Intrinsic::x86_sse41_phminposuw; // "__builtin_ia32_ phminposuw128"
	}		}
	break;		break;
			case 'r': // 2 strings to match.
			if (memcmp(BuiltinName.data()+16, "ndscalep", 8))
			break;
			switch (BuiltinName[24]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "512", 3))
			break;
			return Intrinsic::x86_avx512_rndscale_pd_512; // "__builtin_ia32_
			rndscalepd512"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "512", 3))
			break;
			return Intrinsic::x86_avx512_rndscale_ps_512; // "__builtin_ia32_
			rndscaleps512"
			}
			break;
			case 's': // 8 strings to match.
			if (memcmp(BuiltinName.data()+16, "catter", 6))
			break;
			switch (BuiltinName[22]) {
			default: break;
			case 'd': // 4 strings to match.
			if (BuiltinName[23] != 'p')
			break;
			switch (BuiltinName[24]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "512", 3))
			break;
			return Intrinsic::x86_avx512_scatter_dpd_512; // "__built
			in_ia32_scatterdpd512"
			case 'i': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "512", 3))
			break;
			return Intrinsic::x86_avx512_scatter_dpi_512; // "__built
			in_ia32_scatterdpi512"
			case 'q': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "512", 3))
			break;
			return Intrinsic::x86_avx512_scatter_dpq_512; // "__built
			in_ia32_scatterdpq512"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "512", 3))
			break;
			return Intrinsic::x86_avx512_scatter_dps_512; // "__built
			in_ia32_scatterdps512"
			}
			break;
			case 'q': // 4 strings to match.
			if (BuiltinName[23] != 'p')
			break;
			switch (BuiltinName[24]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "512", 3))
			break;
			return Intrinsic::x86_avx512_scatter_qpd_512; // "__built
			in_ia32_scatterqpd512"
			case 'i': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "512", 3))
			break;
			return Intrinsic::x86_avx512_scatter_qpi_512; // "__built
			in_ia32_scatterqpi512"
			case 'q': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "512", 3))
			break;
			return Intrinsic::x86_avx512_scatter_qpq_512; // "__built
			in_ia32_scatterqpq512"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+25, "512", 3))
			break;
			return Intrinsic::x86_avx512_scatter_qps_512; // "__built
			in_ia32_scatterqps512"
			}
			break;
			}
			break;
	case 'v': // 2 strings to match.		case 'v': // 2 strings to match.
	if (memcmp(BuiltinName.data()+16, "testnzcp", 8))		if (memcmp(BuiltinName.data()+16, "testnzcp", 8))
	break;		break;
	switch (BuiltinName[24]) {		switch (BuiltinName[24]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "256", 3))		if (memcmp(BuiltinName.data()+25, "256", 3))
	break;		break;
	return Intrinsic::x86_avx_vtestnzc_pd_256; // "__builtin_ia32_ vtestnzcpd256"		return Intrinsic::x86_avx_vtestnzc_pd_256; // "__builtin_ia32_ vtestnzcpd256"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+25, "256", 3))		if (memcmp(BuiltinName.data()+25, "256", 3))
	break;		break;
	return Intrinsic::x86_avx_vtestnzc_ps_256; // "__builtin_ia32_ vtestnzcps256"		return Intrinsic::x86_avx_vtestnzc_ps_256; // "__builtin_ia32_ vtestnzcps256"
	}		}
	break;		break;
	}		}
	break;		break;
	case 29: // 15 strings to match.		case 29: // 21 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))		if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
	break;		break;
	switch (BuiltinName[15]) {		switch (BuiltinName[15]) {
	default: break;		default: break;
	case 'e': // 1 string to match.		case 'e': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "xtract128i256", 13))		if (memcmp(BuiltinName.data()+16, "xtract128i256", 13))
	break;		break;
	return Intrinsic::x86_avx2_vextracti128; // "__builtin_ia32_extract1 28i256"		return Intrinsic::x86_avx2_vextracti128; // "__builtin_ia32_extract1 28i256"
	case 'm': // 2 strings to match.		case 'm': // 2 strings to match.
	if (memcmp(BuiltinName.data()+16, "askstorep", 9))		if (memcmp(BuiltinName.data()+16, "askstorep", 9))
	skipping to change at line 43004		skipping to change at line 54790
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "256", 3))		if (memcmp(BuiltinName.data()+26, "256", 3))
	break;		break;
	return Intrinsic::x86_avx_maskstore_pd_256; // "__builtin_ia32_ maskstorepd256"		return Intrinsic::x86_avx_maskstore_pd_256; // "__builtin_ia32_ maskstorepd256"
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+26, "256", 3))		if (memcmp(BuiltinName.data()+26, "256", 3))
	break;		break;
	return Intrinsic::x86_avx_maskstore_ps_256; // "__builtin_ia32_ maskstoreps256"		return Intrinsic::x86_avx_maskstore_ps_256; // "__builtin_ia32_ maskstoreps256"
	}		}
	break;		break;
	case 'p': // 8 strings to match.		case 'p': // 10 strings to match.
	if (memcmp(BuiltinName.data()+16, "broadcast", 9))		if (memcmp(BuiltinName.data()+16, "broadcast", 9))
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'b': // 2 strings to match.		case 'b': // 2 strings to match.
	switch (BuiltinName[26]) {		switch (BuiltinName[26]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "28", 2))		if (memcmp(BuiltinName.data()+27, "28", 2))
	break;		break;
	return Intrinsic::x86_avx2_pbroadcastb_128; // "__builtin_ia32_ pbroadcastb128"		return Intrinsic::x86_avx2_pbroadcastb_128; // "__builtin_ia32_ pbroadcastb128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "56", 2))		if (memcmp(BuiltinName.data()+27, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pbroadcastb_256; // "__builtin_ia32_ pbroadcastb256"		return Intrinsic::x86_avx2_pbroadcastb_256; // "__builtin_ia32_ pbroadcastb256"
	}		}
	break;		break;
	case 'd': // 2 strings to match.		case 'd': // 3 strings to match.
	switch (BuiltinName[26]) {		switch (BuiltinName[26]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "28", 2))		if (memcmp(BuiltinName.data()+27, "28", 2))
	break;		break;
	return Intrinsic::x86_avx2_pbroadcastd_128; // "__builtin_ia32_ pbroadcastd128"		return Intrinsic::x86_avx2_pbroadcastd_128; // "__builtin_ia32_ pbroadcastd128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "56", 2))		if (memcmp(BuiltinName.data()+27, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pbroadcastd_256; // "__builtin_ia32_ pbroadcastd256"		return Intrinsic::x86_avx2_pbroadcastd_256; // "__builtin_ia32_ pbroadcastd256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+27, "12", 2))
			break;
			return Intrinsic::x86_avx512_pbroadcastd_512; // "__built
			in_ia32_pbroadcastd512"
	}		}
	break;		break;
	case 'q': // 2 strings to match.		case 'q': // 3 strings to match.
	switch (BuiltinName[26]) {		switch (BuiltinName[26]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "28", 2))		if (memcmp(BuiltinName.data()+27, "28", 2))
	break;		break;
	return Intrinsic::x86_avx2_pbroadcastq_128; // "__builtin_ia32_ pbroadcastq128"		return Intrinsic::x86_avx2_pbroadcastq_128; // "__builtin_ia32_ pbroadcastq128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "56", 2))		if (memcmp(BuiltinName.data()+27, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pbroadcastq_256; // "__builtin_ia32_ pbroadcastq256"		return Intrinsic::x86_avx2_pbroadcastq_256; // "__builtin_ia32_ pbroadcastq256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+27, "12", 2))
			break;
			return Intrinsic::x86_avx512_pbroadcastq_512; // "__built
			in_ia32_pbroadcastq512"
	}		}
	break;		break;
	case 'w': // 2 strings to match.		case 'w': // 2 strings to match.
	switch (BuiltinName[26]) {		switch (BuiltinName[26]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "28", 2))		if (memcmp(BuiltinName.data()+27, "28", 2))
	break;		break;
	return Intrinsic::x86_avx2_pbroadcastw_128; // "__builtin_ia32_ pbroadcastw128"		return Intrinsic::x86_avx2_pbroadcastw_128; // "__builtin_ia32_ pbroadcastw128"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "56", 2))		if (memcmp(BuiltinName.data()+27, "56", 2))
	break;		break;
	return Intrinsic::x86_avx2_pbroadcastw_256; // "__builtin_ia32_ pbroadcastw256"		return Intrinsic::x86_avx2_pbroadcastw_256; // "__builtin_ia32_ pbroadcastw256"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'v': // 4 strings to match.		case 'v': // 8 strings to match.
	if (memcmp(BuiltinName.data()+16, "fm", 2))		if (memcmp(BuiltinName.data()+16, "fm", 2))
	break;		break;
	switch (BuiltinName[18]) {		switch (BuiltinName[18]) {
	default: break;		default: break;
	case 'a': // 2 strings to match.		case 'a': // 4 strings to match.
	if (memcmp(BuiltinName.data()+19, "ddsubp", 6))		if (memcmp(BuiltinName.data()+19, "ddsubp", 6))
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 2 strings to match.
	if (memcmp(BuiltinName.data()+26, "256", 3))		switch (BuiltinName[26]) {
	break;		default: break;
	return Intrinsic::x86_fma_vfmaddsub_pd_256; // "__builtin_ia32_		case '2': // 1 string to match.
	vfmaddsubpd256"		if (memcmp(BuiltinName.data()+27, "56", 2))
	case 's': // 1 string to match.		break;
	if (memcmp(BuiltinName.data()+26, "256", 3))		return Intrinsic::x86_fma_vfmaddsub_pd_256; // "__built
	break;		in_ia32_vfmaddsubpd256"
	return Intrinsic::x86_fma_vfmaddsub_ps_256; // "__builtin_ia32_		case '5': // 1 string to match.
	vfmaddsubps256"		if (memcmp(BuiltinName.data()+27, "12", 2))
			break;
			return Intrinsic::x86_fma_vfmaddsub_pd_512; // "__built
			in_ia32_vfmaddsubpd512"
			}
			break;
			case 's': // 2 strings to match.
			switch (BuiltinName[26]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(BuiltinName.data()+27, "56", 2))
			break;
			return Intrinsic::x86_fma_vfmaddsub_ps_256; // "__built
			in_ia32_vfmaddsubps256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+27, "12", 2))
			break;
			return Intrinsic::x86_fma_vfmaddsub_ps_512; // "__built
			in_ia32_vfmaddsubps512"
			}
			break;
	}		}
	break;		break;
	case 's': // 2 strings to match.		case 's': // 4 strings to match.
	if (memcmp(BuiltinName.data()+19, "ubaddp", 6))		if (memcmp(BuiltinName.data()+19, "ubaddp", 6))
	break;		break;
	switch (BuiltinName[25]) {		switch (BuiltinName[25]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 2 strings to match.
	if (memcmp(BuiltinName.data()+26, "256", 3))		switch (BuiltinName[26]) {
	break;		default: break;
	return Intrinsic::x86_fma_vfmsubadd_pd_256; // "__builtin_ia32_		case '2': // 1 string to match.
	vfmsubaddpd256"		if (memcmp(BuiltinName.data()+27, "56", 2))
	case 's': // 1 string to match.		break;
	if (memcmp(BuiltinName.data()+26, "256", 3))		return Intrinsic::x86_fma_vfmsubadd_pd_256; // "__built
	break;		in_ia32_vfmsubaddpd256"
	return Intrinsic::x86_fma_vfmsubadd_ps_256; // "__builtin_ia32_		case '5': // 1 string to match.
	vfmsubaddps256"		if (memcmp(BuiltinName.data()+27, "12", 2))
			break;
			return Intrinsic::x86_fma_vfmsubadd_pd_512; // "__built
			in_ia32_vfmsubaddpd512"
			}
			break;
			case 's': // 2 strings to match.
			switch (BuiltinName[26]) {
			default: break;
			case '2': // 1 string to match.
			if (memcmp(BuiltinName.data()+27, "56", 2))
			break;
			return Intrinsic::x86_fma_vfmsubadd_ps_256; // "__built
			in_ia32_vfmsubaddps256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+27, "12", 2))
			break;
			return Intrinsic::x86_fma_vfmsubadd_ps_512; // "__built
			in_ia32_vfmsubaddps512"
			}
			break;
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 30: // 6 strings to match.		case 30: // 7 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_ia32_v", 16))		if (memcmp(BuiltinName.data()+0, "__builtin_ia32_v", 16))
	break;		break;
	switch (BuiltinName[16]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'b': // 4 strings to match.		case 'b': // 5 strings to match.
	if (memcmp(BuiltinName.data()+17, "roadcasts", 9))		if (memcmp(BuiltinName.data()+17, "roadcasts", 9))
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 2 strings to match.
	if (memcmp(BuiltinName.data()+27, "256", 3))		switch (BuiltinName[27]) {
	break;		default: break;
	return Intrinsic::x86_avx_vbroadcast_sd_256; // "__builtin_ia32_		case '2': // 1 string to match.
	vbroadcastsd256"		if (memcmp(BuiltinName.data()+28, "56", 2))
	case 'i': // 1 string to match.		break;
	if (memcmp(BuiltinName.data()+27, "256", 3))		return Intrinsic::x86_avx_vbroadcast_sd_256; // "__builtin_ia32_
	break;		vbroadcastsd256"
	return Intrinsic::x86_avx2_vbroadcasti128; // "__builtin_ia32_		case '5': // 1 string to match.
	vbroadcastsi256"		if (memcmp(BuiltinName.data()+28, "12", 2))
	case 's': // 2 strings to match.		break;
			return Intrinsic::x86_avx512_vbroadcast_sd_512; // "__built
			in_ia32_vbroadcastsd512"
			}
			break;
			case 's': // 3 strings to match.
	switch (BuiltinName[27]) {		switch (BuiltinName[27]) {
	default: break;		default: break;
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "56", 2))		if (memcmp(BuiltinName.data()+28, "56", 2))
	break;		break;
	return Intrinsic::x86_avx_vbroadcast_ss_256; // "__builtin_ia32_ vbroadcastss256"		return Intrinsic::x86_avx_vbroadcast_ss_256; // "__builtin_ia32_ vbroadcastss256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+28, "12", 2))
			break;
			return Intrinsic::x86_avx512_vbroadcast_ss_512; // "__built
			in_ia32_vbroadcastss512"
	case '_': // 1 string to match.		case '_': // 1 string to match.
	if (memcmp(BuiltinName.data()+28, "ps", 2))		if (memcmp(BuiltinName.data()+28, "ps", 2))
	break;		break;
	return Intrinsic::x86_avx2_vbroadcast_ss_ps; // "__builtin_ia32_ vbroadcastss_ps"		return Intrinsic::x86_avx2_vbroadcast_ss_ps; // "__builtin_ia32_ vbroadcastss_ps"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'p': // 2 strings to match.		case 'p': // 2 strings to match.
	if (memcmp(BuiltinName.data()+17, "ermilvarp", 9))		if (memcmp(BuiltinName.data()+17, "ermilvarp", 9))
	skipping to change at line 43176		skipping to change at line 55015
	break;		break;
	return Intrinsic::x86_avx_vperm2f128_ps_256; // "__builtin_ia32_ vperm2f128_ps256"		return Intrinsic::x86_avx_vperm2f128_ps_256; // "__builtin_ia32_ vperm2f128_ps256"
	}		}
	break;		break;
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "i256", 4))		if (memcmp(BuiltinName.data()+27, "i256", 4))
	break;		break;
	return Intrinsic::x86_avx_vperm2f128_si_256; // "__builtin_ia32_ vperm2f128_si256"		return Intrinsic::x86_avx_vperm2f128_si_256; // "__builtin_ia32_ vperm2f128_si256"
	}		}
	break;		break;
	case 32: // 3 strings to match.		case 32: // 13 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_ia32_vinsertf128_", 27))		if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
	break;		break;
	switch (BuiltinName[27]) {		switch (BuiltinName[15]) {
	default: break;		default: break;
	case 'p': // 2 strings to match.		case 'm': // 10 strings to match.
	switch (BuiltinName[28]) {		if (memcmp(BuiltinName.data()+16, "ask_", 4))
			break;
			switch (BuiltinName[20]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'c': // 2 strings to match.
	if (memcmp(BuiltinName.data()+29, "256", 3))		if (memcmp(BuiltinName.data()+21, "onflict", 7))
	break;		break;
	return Intrinsic::x86_avx_vinsertf128_pd_256; // "__builtin_ia32_		switch (BuiltinName[28]) {
	vinsertf128_pd256"		default: break;
	case 's': // 1 string to match.		case 'd': // 1 string to match.
	if (memcmp(BuiltinName.data()+29, "256", 3))		if (memcmp(BuiltinName.data()+29, "512", 3))
			break;
			return Intrinsic::x86_avx512_conflict_d_mask_512; // "__built
			in_ia32_mask_conflictd512"
			case 'q': // 1 string to match.
			if (memcmp(BuiltinName.data()+29, "512", 3))
			break;
			return Intrinsic::x86_avx512_conflict_q_mask_512; // "__built
			in_ia32_mask_conflictq512"
			}
			break;
			case 'g': // 8 strings to match.
			if (memcmp(BuiltinName.data()+21, "ather", 5))
			break;
			switch (BuiltinName[26]) {
			default: break;
			case 'd': // 4 strings to match.
			if (BuiltinName[27] != 'p')
			break;
			switch (BuiltinName[28]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+29, "512", 3))
			break;
			return Intrinsic::x86_avx512_gather_dpd_mask_512; // "__built
			in_ia32_mask_gatherdpd512"
			case 'i': // 1 string to match.
			if (memcmp(BuiltinName.data()+29, "512", 3))
			break;
			return Intrinsic::x86_avx512_gather_dpi_mask_512; // "__built
			in_ia32_mask_gatherdpi512"
			case 'q': // 1 string to match.
			if (memcmp(BuiltinName.data()+29, "512", 3))
			break;
			return Intrinsic::x86_avx512_gather_dpq_mask_512; // "__built
			in_ia32_mask_gatherdpq512"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+29, "512", 3))
			break;
			return Intrinsic::x86_avx512_gather_dps_mask_512; // "__built
			in_ia32_mask_gatherdps512"
			}
			break;
			case 'q': // 4 strings to match.
			if (BuiltinName[27] != 'p')
			break;
			switch (BuiltinName[28]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+29, "512", 3))
			break;
			return Intrinsic::x86_avx512_gather_qpd_mask_512; // "__built
			in_ia32_mask_gatherqpd512"
			case 'i': // 1 string to match.
			if (memcmp(BuiltinName.data()+29, "512", 3))
			break;
			return Intrinsic::x86_avx512_gather_qpi_mask_512; // "__built
			in_ia32_mask_gatherqpi512"
			case 'q': // 1 string to match.
			if (memcmp(BuiltinName.data()+29, "512", 3))
			break;
			return Intrinsic::x86_avx512_gather_qpq_mask_512; // "__built
			in_ia32_mask_gatherqpq512"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+29, "512", 3))
			break;
			return Intrinsic::x86_avx512_gather_qps_mask_512; // "__built
			in_ia32_mask_gatherqps512"
			}
	break;		break;
	return Intrinsic::x86_avx_vinsertf128_ps_256; // "__builtin_ia32_		}
	vinsertf128_ps256"		break;
	}		}
	break;		break;
	case 's': // 1 string to match.		case 'v': // 3 strings to match.
	if (memcmp(BuiltinName.data()+28, "i256", 4))		if (memcmp(BuiltinName.data()+16, "insertf128_", 11))
			break;
			switch (BuiltinName[27]) {
			default: break;
			case 'p': // 2 strings to match.
			switch (BuiltinName[28]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+29, "256", 3))
			break;
			return Intrinsic::x86_avx_vinsertf128_pd_256; // "__built
			in_ia32_vinsertf128_pd256"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+29, "256", 3))
			break;
			return Intrinsic::x86_avx_vinsertf128_ps_256; // "__built
			in_ia32_vinsertf128_ps256"
			}
	break;		break;
	return Intrinsic::x86_avx_vinsertf128_si_256; // "__builtin_ia32_		case 's': // 1 string to match.
	vinsertf128_si256"		if (memcmp(BuiltinName.data()+28, "i256", 4))
			break;
			return Intrinsic::x86_avx_vinsertf128_si_256; // "__builtin_ia32_
			vinsertf128_si256"
			}
			break;
	}		}
	break;		break;
	case 33: // 6 strings to match.		case 33: // 18 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))		if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
	break;		break;
	switch (BuiltinName[15]) {		switch (BuiltinName[15]) {
	default: break;		default: break;
	case 'a': // 1 string to match.		case 'a': // 1 string to match.
	if (memcmp(BuiltinName.data()+16, "eskeygenassist128", 17))		if (memcmp(BuiltinName.data()+16, "eskeygenassist128", 17))
	break;		break;
	return Intrinsic::x86_aesni_aeskeygenassist; // "__builtin_ia32_ aeskeygenassist128"		return Intrinsic::x86_aesni_aeskeygenassist; // "__builtin_ia32_ aeskeygenassist128"
	case 'v': // 5 strings to match.		case 'm': // 10 strings to match.
			if (memcmp(BuiltinName.data()+16, "ask", 3))
			break;
			switch (BuiltinName[19]) {
			default: break;
			case '_': // 8 strings to match.
			if (memcmp(BuiltinName.data()+20, "scatter", 7))
			break;
			switch (BuiltinName[27]) {
			default: break;
			case 'd': // 4 strings to match.
			if (BuiltinName[28] != 'p')
			break;
			switch (BuiltinName[29]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "512", 3))
			break;
			return Intrinsic::x86_avx512_scatter_dpd_mask_512; // "__built
			in_ia32_mask_scatterdpd512"
			case 'i': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "512", 3))
			break;
			return Intrinsic::x86_avx512_scatter_dpi_mask_512; // "__built
			in_ia32_mask_scatterdpi512"
			case 'q': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "512", 3))
			break;
			return Intrinsic::x86_avx512_scatter_dpq_mask_512; // "__built
			in_ia32_mask_scatterdpq512"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "512", 3))
			break;
			return Intrinsic::x86_avx512_scatter_dps_mask_512; // "__built
			in_ia32_mask_scatterdps512"
			}
			break;
			case 'q': // 4 strings to match.
			if (BuiltinName[28] != 'p')
			break;
			switch (BuiltinName[29]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "512", 3))
			break;
			return Intrinsic::x86_avx512_scatter_qpd_mask_512; // "__built
			in_ia32_mask_scatterqpd512"
			case 'i': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "512", 3))
			break;
			return Intrinsic::x86_avx512_scatter_qpi_mask_512; // "__built
			in_ia32_mask_scatterqpi512"
			case 'q': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "512", 3))
			break;
			return Intrinsic::x86_avx512_scatter_qpq_mask_512; // "__built
			in_ia32_mask_scatterqpq512"
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "512", 3))
			break;
			return Intrinsic::x86_avx512_scatter_qps_mask_512; // "__built
			in_ia32_mask_scatterqps512"
			}
			break;
			}
			break;
			case 'z': // 2 strings to match.
			if (memcmp(BuiltinName.data()+20, "_conflict", 9))
			break;
			switch (BuiltinName[29]) {
			default: break;
			case 'd': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "512", 3))
			break;
			return Intrinsic::x86_avx512_conflict_d_maskz_512; // "__built
			in_ia32_maskz_conflictd512"
			case 'q': // 1 string to match.
			if (memcmp(BuiltinName.data()+30, "512", 3))
			break;
			return Intrinsic::x86_avx512_conflict_q_maskz_512; // "__built
			in_ia32_maskz_conflictq512"
			}
			break;
			}
			break;
			case 'v': // 7 strings to match.
	switch (BuiltinName[16]) {		switch (BuiltinName[16]) {
	default: break;		default: break;
	case 'b': // 2 strings to match.		case 'b': // 4 strings to match.
	if (memcmp(BuiltinName.data()+17, "roadcasts", 9))		if (memcmp(BuiltinName.data()+17, "roadcasts", 9))
	break;		break;
	switch (BuiltinName[26]) {		switch (BuiltinName[26]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 2 strings to match.
	if (memcmp(BuiltinName.data()+27, "_pd256", 6))		if (memcmp(BuiltinName.data()+27, "_pd", 3))
	break;		break;
	return Intrinsic::x86_avx2_vbroadcast_sd_pd_256; // "__built		switch (BuiltinName[30]) {
	in_ia32_vbroadcastsd_pd256"		default: break;
	case 's': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+27, "_ps256", 6))		if (memcmp(BuiltinName.data()+31, "56", 2))
			break;
			return Intrinsic::x86_avx2_vbroadcast_sd_pd_256; // "__built
			in_ia32_vbroadcastsd_pd256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+31, "12", 2))
			break;
			return Intrinsic::x86_avx512_vbroadcast_sd_pd_512; // "__built
			in_ia32_vbroadcastsd_pd512"
			}
			break;
			case 's': // 2 strings to match.
			if (memcmp(BuiltinName.data()+27, "_ps", 3))
	break;		break;
	return Intrinsic::x86_avx2_vbroadcast_ss_ps_256; // "__built		switch (BuiltinName[30]) {
	in_ia32_vbroadcastss_ps256"		default: break;
			case '2': // 1 string to match.
			if (memcmp(BuiltinName.data()+31, "56", 2))
			break;
			return Intrinsic::x86_avx2_vbroadcast_ss_ps_256; // "__built
			in_ia32_vbroadcastss_ps256"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+31, "12", 2))
			break;
			return Intrinsic::x86_avx512_vbroadcast_ss_ps_512; // "__built
			in_ia32_vbroadcastss_ps512"
			}
			break;
	}		}
	break;		break;
	case 'e': // 3 strings to match.		case 'e': // 3 strings to match.
	if (memcmp(BuiltinName.data()+17, "xtractf128_", 11))		if (memcmp(BuiltinName.data()+17, "xtractf128_", 11))
	break;		break;
	switch (BuiltinName[28]) {		switch (BuiltinName[28]) {
	default: break;		default: break;
	case 'p': // 2 strings to match.		case 'p': // 2 strings to match.
	switch (BuiltinName[29]) {		switch (BuiltinName[29]) {
	default: break;		default: break;
	skipping to change at line 43255		skipping to change at line 55273
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+29, "i256", 4))		if (memcmp(BuiltinName.data()+29, "i256", 4))
	break;		break;
	return Intrinsic::x86_avx_vextractf128_si_256; // "__built in_ia32_vextractf128_si256"		return Intrinsic::x86_avx_vextractf128_si_256; // "__built in_ia32_vextractf128_si256"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	break;		break;
	case 35: // 6 strings to match.		case 35: // 8 strings to match.
	if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))		if (memcmp(BuiltinName.data()+0, "__builtin_ia32_", 15))
	break;		break;
	switch (BuiltinName[15]) {		switch (BuiltinName[15]) {
	default: break;		default: break;
	case 'p': // 4 strings to match.		case 'p': // 6 strings to match.
	if (BuiltinName[16] != 's')		if (BuiltinName[16] != 's')
	break;		break;
	switch (BuiltinName[17]) {		switch (BuiltinName[17]) {
	default: break;		default: break;
	case 'l': // 2 strings to match.		case 'l': // 3 strings to match.
	if (memcmp(BuiltinName.data()+18, "ldqi", 4))		if (memcmp(BuiltinName.data()+18, "ldqi", 4))
	break;		break;
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "28_byteshift", 12))		if (memcmp(BuiltinName.data()+23, "28_byteshift", 12))
	break;		break;
	return Intrinsic::x86_sse2_psll_dq_bs; // "__builtin_ia32_ pslldqi128_byteshift"		return Intrinsic::x86_sse2_psll_dq_bs; // "__builtin_ia32_ pslldqi128_byteshift"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "56_byteshift", 12))		if (memcmp(BuiltinName.data()+23, "56_byteshift", 12))
	break;		break;
	return Intrinsic::x86_avx2_psll_dq_bs; // "__builtin_ia32_ pslldqi256_byteshift"		return Intrinsic::x86_avx2_psll_dq_bs; // "__builtin_ia32_ pslldqi256_byteshift"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "12_byteshift", 12))
			break;
			return Intrinsic::x86_avx512_psll_dq_bs; // "__builtin_ia32_
			pslldqi512_byteshift"
	}		}
	break;		break;
	case 'r': // 2 strings to match.		case 'r': // 3 strings to match.
	if (memcmp(BuiltinName.data()+18, "ldqi", 4))		if (memcmp(BuiltinName.data()+18, "ldqi", 4))
	break;		break;
	switch (BuiltinName[22]) {		switch (BuiltinName[22]) {
	default: break;		default: break;
	case '1': // 1 string to match.		case '1': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "28_byteshift", 12))		if (memcmp(BuiltinName.data()+23, "28_byteshift", 12))
	break;		break;
	return Intrinsic::x86_sse2_psrl_dq_bs; // "__builtin_ia32_ psrldqi128_byteshift"		return Intrinsic::x86_sse2_psrl_dq_bs; // "__builtin_ia32_ psrldqi128_byteshift"
	case '2': // 1 string to match.		case '2': // 1 string to match.
	if (memcmp(BuiltinName.data()+23, "56_byteshift", 12))		if (memcmp(BuiltinName.data()+23, "56_byteshift", 12))
	break;		break;
	return Intrinsic::x86_avx2_psrl_dq_bs; // "__builtin_ia32_ psrldqi256_byteshift"		return Intrinsic::x86_avx2_psrl_dq_bs; // "__builtin_ia32_ psrldqi256_byteshift"
			case '5': // 1 string to match.
			if (memcmp(BuiltinName.data()+23, "12_byteshift", 12))
			break;
			return Intrinsic::x86_avx512_psrl_dq_bs; // "__builtin_ia32_
			psrldqi512_byteshift"
	}		}
	break;		break;
	}		}
	break;		break;
	case 'v': // 2 strings to match.		case 'v': // 2 strings to match.
	if (memcmp(BuiltinName.data()+16, "broadcastf128_p", 15))		if (memcmp(BuiltinName.data()+16, "broadcastf128_p", 15))
	break;		break;
	switch (BuiltinName[31]) {		switch (BuiltinName[31]) {
	default: break;		default: break;
	case 'd': // 1 string to match.		case 'd': // 1 string to match.
	skipping to change at line 43316		skipping to change at line 55342
	case 's': // 1 string to match.		case 's': // 1 string to match.
	if (memcmp(BuiltinName.data()+32, "256", 3))		if (memcmp(BuiltinName.data()+32, "256", 3))
	break;		break;
	return Intrinsic::x86_avx_vbroadcastf128_ps_256; // "__built in_ia32_vbroadcastf128_ps256"		return Intrinsic::x86_avx_vbroadcastf128_ps_256; // "__built in_ia32_vbroadcastf128_ps256"
	}		}
	break;		break;
	}		}
	break;		break;
	}		}
	}		}
			if (TargetPrefix == "xcore") {
			switch (BuiltinName.size()) {
			default: break;
			case 15: // 3 strings to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_", 10))
			break;
			switch (BuiltinName[10]) {
			default: break;
			case 'g': // 2 strings to match.
			if (memcmp(BuiltinName.data()+11, "et", 2))
			break;
			switch (BuiltinName[13]) {
			default: break;
			case 'i': // 1 string to match.
			if (BuiltinName[14] != 'd')
			break;
			return Intrinsic::xcore_getid; // "__builtin_getid"
			case 'p': // 1 string to match.
			if (BuiltinName[14] != 's')
			break;
			return Intrinsic::xcore_getps; // "__builtin_getps"
			}
			break;
			case 's': // 1 string to match.
			if (memcmp(BuiltinName.data()+11, "etps", 4))
			break;
			return Intrinsic::xcore_setps; // "__builtin_setps"
			}
			break;
			case 16: // 1 string to match.
			if (memcmp(BuiltinName.data()+0, "__builtin_bitrev", 16))
			break;
			return Intrinsic::xcore_bitrev; // "__builtin_bitrev"
			}
			}
	return Intrinsic::not_intrinsic;		return Intrinsic::not_intrinsic;
	}		}
	#endif		#endif
	#if defined(_MSC_VER) && defined(setjmp_undefined_for_msvc)		#if defined(_MSC_VER) && defined(setjmp_undefined_for_msvc)
	// let's return it to _setjmp state		// let's return it to _setjmp state
	# pragma pop_macro("setjmp")		# pragma pop_macro("setjmp")
	# undef setjmp_undefined_for_msvc		# undef setjmp_undefined_for_msvc
	#endif		#endif
End of changes. 3170 change blocks.
	20653 lines changed or deleted		33423 lines changed or added

	Intrinsics.h		Intrinsics.h
	skipping to change at line 80		skipping to change at line 80
	Function *getDeclaration(Module *M, ID id, ArrayRef<Type*> Tys = None);		Function *getDeclaration(Module *M, ID id, ArrayRef<Type*> Tys = None);
	/// Map a GCC builtin name to an intrinsic ID.		/// Map a GCC builtin name to an intrinsic ID.
	ID getIntrinsicForGCCBuiltin(const char *Prefix, const char *BuiltinName) ;		ID getIntrinsicForGCCBuiltin(const char *Prefix, const char *BuiltinName) ;
	/// IITDescriptor - This is a type descriptor which explains the type		/// IITDescriptor - This is a type descriptor which explains the type
	/// requirements of an intrinsic. This is returned by		/// requirements of an intrinsic. This is returned by
	/// getIntrinsicInfoTableEntries.		/// getIntrinsicInfoTableEntries.
	struct IITDescriptor {		struct IITDescriptor {
	enum IITDescriptorKind {		enum IITDescriptorKind {
	Void, MMX, Metadata, Half, Float, Double,		Void, VarArg, MMX, Metadata, Half, Float, Double,
	Integer, Vector, Pointer, Struct,		Integer, Vector, Pointer, Struct,
	Argument, ExtendVecArgument, TruncVecArgument		Argument, ExtendVecArgument, TruncVecArgument
	} Kind;		} Kind;
	union {		union {
	unsigned Integer_Width;		unsigned Integer_Width;
	unsigned Float_Width;		unsigned Float_Width;
	unsigned Vector_Width;		unsigned Vector_Width;
	unsigned Pointer_AddressSpace;		unsigned Pointer_AddressSpace;
	unsigned Struct_NumElements;		unsigned Struct_NumElements;
End of changes. 1 change blocks.
	1 lines changed or deleted		1 lines changed or added

	Intrinsics.td		Intrinsics.td
	skipping to change at line 58		skipping to change at line 58
	def Commutative : IntrinsicProperty;		def Commutative : IntrinsicProperty;
	// Throws - This intrinsic can throw.		// Throws - This intrinsic can throw.
	def Throws : IntrinsicProperty;		def Throws : IntrinsicProperty;
	// NoCapture - The specified argument pointer is not captured by the intrin sic.		// NoCapture - The specified argument pointer is not captured by the intrin sic.
	class NoCapture<int argNo> : IntrinsicProperty {		class NoCapture<int argNo> : IntrinsicProperty {
	int ArgNo = argNo;		int ArgNo = argNo;
	}		}
			// ReadOnly - The specified argument pointer is not written to through the
			// pointer by the intrinsic.
			class ReadOnly<int argNo> : IntrinsicProperty {
			int ArgNo = argNo;
			}
			// ReadNone - The specified argument pointer is not dereferenced by the
			// intrinsic.
			class ReadNone<int argNo> : IntrinsicProperty {
			int ArgNo = argNo;
			}
	def IntrNoReturn : IntrinsicProperty;		def IntrNoReturn : IntrinsicProperty;
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// Types used by intrinsics.		// Types used by intrinsics.
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	class LLVMType<ValueType vt> {		class LLVMType<ValueType vt> {
	ValueType VT = vt;		ValueType VT = vt;
	}		}
	skipping to change at line 131		skipping to change at line 143
	def llvm_x86mmx_ty : LLVMType<x86mmx>;		def llvm_x86mmx_ty : LLVMType<x86mmx>;
	def llvm_ptrx86mmx_ty : LLVMPointerType<llvm_x86mmx_ty>; // <1 x i 64>*		def llvm_ptrx86mmx_ty : LLVMPointerType<llvm_x86mmx_ty>; // <1 x i 64>*
	def llvm_v2i1_ty : LLVMType<v2i1>; // 2 x i1		def llvm_v2i1_ty : LLVMType<v2i1>; // 2 x i1
	def llvm_v4i1_ty : LLVMType<v4i1>; // 4 x i1		def llvm_v4i1_ty : LLVMType<v4i1>; // 4 x i1
	def llvm_v8i1_ty : LLVMType<v8i1>; // 8 x i1		def llvm_v8i1_ty : LLVMType<v8i1>; // 8 x i1
	def llvm_v16i1_ty : LLVMType<v16i1>; // 16 x i1		def llvm_v16i1_ty : LLVMType<v16i1>; // 16 x i1
	def llvm_v32i1_ty : LLVMType<v32i1>; // 32 x i1		def llvm_v32i1_ty : LLVMType<v32i1>; // 32 x i1
	def llvm_v64i1_ty : LLVMType<v64i1>; // 64 x i1		def llvm_v64i1_ty : LLVMType<v64i1>; // 64 x i1
			def llvm_v1i8_ty : LLVMType<v1i8>; // 1 x i8
	def llvm_v2i8_ty : LLVMType<v2i8>; // 2 x i8		def llvm_v2i8_ty : LLVMType<v2i8>; // 2 x i8
	def llvm_v4i8_ty : LLVMType<v4i8>; // 4 x i8		def llvm_v4i8_ty : LLVMType<v4i8>; // 4 x i8
	def llvm_v8i8_ty : LLVMType<v8i8>; // 8 x i8		def llvm_v8i8_ty : LLVMType<v8i8>; // 8 x i8
	def llvm_v16i8_ty : LLVMType<v16i8>; // 16 x i8		def llvm_v16i8_ty : LLVMType<v16i8>; // 16 x i8
	def llvm_v32i8_ty : LLVMType<v32i8>; // 32 x i8		def llvm_v32i8_ty : LLVMType<v32i8>; // 32 x i8
	def llvm_v64i8_ty : LLVMType<v64i8>; // 64 x i8		def llvm_v64i8_ty : LLVMType<v64i8>; // 64 x i8
	def llvm_v1i16_ty : LLVMType<v1i16>; // 1 x i16		def llvm_v1i16_ty : LLVMType<v1i16>; // 1 x i16
	def llvm_v2i16_ty : LLVMType<v2i16>; // 2 x i16		def llvm_v2i16_ty : LLVMType<v2i16>; // 2 x i16
	def llvm_v4i16_ty : LLVMType<v4i16>; // 4 x i16		def llvm_v4i16_ty : LLVMType<v4i16>; // 4 x i16
	skipping to change at line 156		skipping to change at line 169
	def llvm_v2i32_ty : LLVMType<v2i32>; // 2 x i32		def llvm_v2i32_ty : LLVMType<v2i32>; // 2 x i32
	def llvm_v4i32_ty : LLVMType<v4i32>; // 4 x i32		def llvm_v4i32_ty : LLVMType<v4i32>; // 4 x i32
	def llvm_v8i32_ty : LLVMType<v8i32>; // 8 x i32		def llvm_v8i32_ty : LLVMType<v8i32>; // 8 x i32
	def llvm_v16i32_ty : LLVMType<v16i32>; // 16 x i32		def llvm_v16i32_ty : LLVMType<v16i32>; // 16 x i32
	def llvm_v1i64_ty : LLVMType<v1i64>; // 1 x i64		def llvm_v1i64_ty : LLVMType<v1i64>; // 1 x i64
	def llvm_v2i64_ty : LLVMType<v2i64>; // 2 x i64		def llvm_v2i64_ty : LLVMType<v2i64>; // 2 x i64
	def llvm_v4i64_ty : LLVMType<v4i64>; // 4 x i64		def llvm_v4i64_ty : LLVMType<v4i64>; // 4 x i64
	def llvm_v8i64_ty : LLVMType<v8i64>; // 8 x i64		def llvm_v8i64_ty : LLVMType<v8i64>; // 8 x i64
	def llvm_v16i64_ty : LLVMType<v16i64>; // 16 x i64		def llvm_v16i64_ty : LLVMType<v16i64>; // 16 x i64
			def llvm_v2f16_ty : LLVMType<v2f16>; // 2 x half (__fp16)
			def llvm_v4f16_ty : LLVMType<v4f16>; // 4 x half (__fp16)
			def llvm_v8f16_ty : LLVMType<v8f16>; // 8 x half (__fp16)
			def llvm_v1f32_ty : LLVMType<v1f32>; // 1 x float
	def llvm_v2f32_ty : LLVMType<v2f32>; // 2 x float		def llvm_v2f32_ty : LLVMType<v2f32>; // 2 x float
	def llvm_v4f32_ty : LLVMType<v4f32>; // 4 x float		def llvm_v4f32_ty : LLVMType<v4f32>; // 4 x float
	def llvm_v8f32_ty : LLVMType<v8f32>; // 8 x float		def llvm_v8f32_ty : LLVMType<v8f32>; // 8 x float
	def llvm_v16f32_ty : LLVMType<v16f32>; // 16 x float		def llvm_v16f32_ty : LLVMType<v16f32>; // 16 x float
			def llvm_v1f64_ty : LLVMType<v1f64>; // 1 x double
	def llvm_v2f64_ty : LLVMType<v2f64>; // 2 x double		def llvm_v2f64_ty : LLVMType<v2f64>; // 2 x double
	def llvm_v4f64_ty : LLVMType<v4f64>; // 4 x double		def llvm_v4f64_ty : LLVMType<v4f64>; // 4 x double
	def llvm_v8f64_ty : LLVMType<v8f64>; // 8 x double		def llvm_v8f64_ty : LLVMType<v8f64>; // 8 x double
	def llvm_vararg_ty : LLVMType<isVoid>; // this means vararg here		def llvm_vararg_ty : LLVMType<isVoid>; // this means vararg here
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// Intrinsic Definitions.		// Intrinsic Definitions.
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	skipping to change at line 247		skipping to change at line 265
	[llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty,		[llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty,
	llvm_i32_ty],		llvm_i32_ty],
	[IntrReadWriteArgMem, NoCapture<0>]>;		[IntrReadWriteArgMem, NoCapture<0>]>;
	def int_pcmarker : Intrinsic<[], [llvm_i32_ty]>;		def int_pcmarker : Intrinsic<[], [llvm_i32_ty]>;
	def int_readcyclecounter : Intrinsic<[llvm_i64_ty]>;		def int_readcyclecounter : Intrinsic<[llvm_i64_ty]>;
	// Stack Protector Intrinsic - The stackprotector intrinsic writes the stac k		// Stack Protector Intrinsic - The stackprotector intrinsic writes the stac k
	// guard to the correct place on the stack frame.		// guard to the correct place on the stack frame.
	def int_stackprotector : Intrinsic<[], [llvm_ptr_ty, llvm_ptrptr_ty], []>;		def int_stackprotector : Intrinsic<[], [llvm_ptr_ty, llvm_ptrptr_ty], []>;
			def int_stackprotectorcheck : Intrinsic<[], [llvm_ptrptr_ty],
			[IntrReadWriteArgMem]>;
	//===------------------- Standard C Library Intrinsics -------------------- ===//		//===------------------- Standard C Library Intrinsics -------------------- ===//
	//		//
	def int_memcpy : Intrinsic<[],		def int_memcpy : Intrinsic<[],
	[llvm_anyptr_ty, llvm_anyptr_ty, llvm_anyint_t y,		[llvm_anyptr_ty, llvm_anyptr_ty, llvm_anyint_t y,
	llvm_i32_ty, llvm_i1_ty],		llvm_i32_ty, llvm_i1_ty],
	[IntrReadWriteArgMem, NoCapture<0>, NoCapture<1		[IntrReadWriteArgMem, NoCapture<0>, NoCapture<1
	>]>;		>,
			ReadOnly<1>]>;
	def int_memmove : Intrinsic<[],		def int_memmove : Intrinsic<[],
	[llvm_anyptr_ty, llvm_anyptr_ty, llvm_anyint_ty ,		[llvm_anyptr_ty, llvm_anyptr_ty, llvm_anyint_ty ,
	llvm_i32_ty, llvm_i1_ty],		llvm_i32_ty, llvm_i1_ty],
	[IntrReadWriteArgMem, NoCapture<0>, NoCapture<1		[IntrReadWriteArgMem, NoCapture<0>, NoCapture<1
	>]>;		>,
			ReadOnly<1>]>;
	def int_memset : Intrinsic<[],		def int_memset : Intrinsic<[],
	[llvm_anyptr_ty, llvm_i8_ty, llvm_anyint_ty,		[llvm_anyptr_ty, llvm_i8_ty, llvm_anyint_ty,
	llvm_i32_ty, llvm_i1_ty],		llvm_i32_ty, llvm_i1_ty],
	[IntrReadWriteArgMem, NoCapture<0>]>;		[IntrReadWriteArgMem, NoCapture<0>]>;
	// These functions do not actually read memory, but they are sensitive to t he		// These functions do not actually read memory, but they are sensitive to t he
	// rounding mode. This needs to be modelled separately; in the meantime		// rounding mode. This needs to be modelled separately; in the meantime
	// declaring them as reading memory is conservatively correct.		// declaring them as reading memory is conservatively correct.
	let Properties = [IntrReadMem] in {		let Properties = [IntrReadMem] in {
	def int_sqrt : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;		def int_sqrt : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
	skipping to change at line 280		skipping to change at line 302
	def int_sin : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;		def int_sin : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
	def int_cos : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;		def int_cos : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
	def int_pow : Intrinsic<[llvm_anyfloat_ty],		def int_pow : Intrinsic<[llvm_anyfloat_ty],
	[LLVMMatchType<0>, LLVMMatchType<0>]>;		[LLVMMatchType<0>, LLVMMatchType<0>]>;
	def int_log : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;		def int_log : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
	def int_log10: Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;		def int_log10: Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
	def int_log2 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;		def int_log2 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
	def int_exp : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;		def int_exp : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
	def int_exp2 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;		def int_exp2 : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
	def int_fabs : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;		def int_fabs : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
			def int_copysign : Intrinsic<[llvm_anyfloat_ty],
			[LLVMMatchType<0>, LLVMMatchType<0>]>;
	def int_floor : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;		def int_floor : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
	def int_ceil : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;		def int_ceil : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
	def int_trunc : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;		def int_trunc : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
	def int_rint : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;		def int_rint : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
	def int_nearbyint : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;		def int_nearbyint : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
			def int_round : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>]>;
	}		}
	let Properties = [IntrNoMem] in {		let Properties = [IntrNoMem] in {
	def int_fma : Intrinsic<[llvm_anyfloat_ty],		def int_fma : Intrinsic<[llvm_anyfloat_ty],
	[LLVMMatchType<0>, LLVMMatchType<0>,		[LLVMMatchType<0>, LLVMMatchType<0>,
	LLVMMatchType<0>]>;		LLVMMatchType<0>]>;
	def int_fmuladd : Intrinsic<[llvm_anyfloat_ty],		def int_fmuladd : Intrinsic<[llvm_anyfloat_ty],
	[LLVMMatchType<0>, LLVMMatchType<0>,		[LLVMMatchType<0>, LLVMMatchType<0>,
	LLVMMatchType<0>]>;		LLVMMatchType<0>]>;
	}		}
	// NOTE: these are internal interfaces.		// NOTE: these are internal interfaces.
	def int_setjmp : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>;		def int_setjmp : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>;
	def int_longjmp : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], [IntrNoRetur n]>;		def int_longjmp : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], [IntrNoRetur n]>;
	def int_sigsetjmp : Intrinsic<[llvm_i32_ty] , [llvm_ptr_ty, llvm_i32_ty]>;		def int_sigsetjmp : Intrinsic<[llvm_i32_ty] , [llvm_ptr_ty, llvm_i32_ty]>;
	def int_siglongjmp : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], [IntrNoRetur n]>;		def int_siglongjmp : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], [IntrNoRetur n]>;
	// Internal interface for object size checking		// Internal interface for object size checking
	def int_objectsize : Intrinsic<[llvm_anyint_ty], [llvm_ptr_ty, llvm_i1_ty],		def int_objectsize : Intrinsic<[llvm_anyint_ty], [llvm_anyptr_ty, llvm_i1_t y],
	[IntrNoMem]>,		[IntrNoMem]>,
	GCCBuiltin<"__builtin_object_size">;		GCCBuiltin<"__builtin_object_size">;
	//===------------------------- Expect Intrinsics -------------------------- ===//		//===------------------------- Expect Intrinsics -------------------------- ===//
	//		//
	def int_expect : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,		def int_expect : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>,
	LLVMMatchType<0>], [IntrNoMem ]>;		LLVMMatchType<0>], [IntrNoMem ]>;
	//===-------------------- Bit Manipulation Intrinsics --------------------- ===//		//===-------------------- Bit Manipulation Intrinsics --------------------- ===//
	//		//
	skipping to change at line 348		skipping to change at line 373
	//===------------------ Exception Handling Intrinsics---------------------- ===//		//===------------------ Exception Handling Intrinsics---------------------- ===//
	//		//
	// The result of eh.typeid.for depends on the enclosing function, but insid e a		// The result of eh.typeid.for depends on the enclosing function, but insid e a
	// given function it is 'const' and may be CSE'd etc.		// given function it is 'const' and may be CSE'd etc.
	def int_eh_typeid_for : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem] >;		def int_eh_typeid_for : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem] >;
	def int_eh_return_i32 : Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty]>;		def int_eh_return_i32 : Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty]>;
	def int_eh_return_i64 : Intrinsic<[], [llvm_i64_ty, llvm_ptr_ty]>;		def int_eh_return_i64 : Intrinsic<[], [llvm_i64_ty, llvm_ptr_ty]>;
			// __builtin_unwind_init is an undocumented GCC intrinsic that causes all
			// callee-saved registers to be saved and restored (regardless of whether t
			hey
			// are used) in the calling function. It is used by libgcc_eh.
	def int_eh_unwind_init: Intrinsic<[]>,		def int_eh_unwind_init: Intrinsic<[]>,
	GCCBuiltin<"__builtin_unwind_init">;		GCCBuiltin<"__builtin_unwind_init">;
	def int_eh_dwarf_cfa : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty]>;		def int_eh_dwarf_cfa : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty]>;
	let Properties = [IntrNoMem] in {		let Properties = [IntrNoMem] in {
	def int_eh_sjlj_lsda : Intrinsic<[llvm_ptr_ty]>;		def int_eh_sjlj_lsda : Intrinsic<[llvm_ptr_ty]>;
	def int_eh_sjlj_callsite : Intrinsic<[], [llvm_i32_ty]>;		def int_eh_sjlj_callsite : Intrinsic<[], [llvm_i32_ty]>;
	}		}
	def int_eh_sjlj_functioncontext : Intrinsic<[], [llvm_ptr_ty]>;		def int_eh_sjlj_functioncontext : Intrinsic<[], [llvm_ptr_ty]>;
	skipping to change at line 428		skipping to change at line 456
	[llvm_i64_ty, llvm_ptr_ty],		[llvm_i64_ty, llvm_ptr_ty],
	[IntrReadWriteArgMem, NoCapture<1>]>;		[IntrReadWriteArgMem, NoCapture<1>]>;
	def int_invariant_start : Intrinsic<[llvm_descriptor_ty],		def int_invariant_start : Intrinsic<[llvm_descriptor_ty],
	[llvm_i64_ty, llvm_ptr_ty],		[llvm_i64_ty, llvm_ptr_ty],
	[IntrReadWriteArgMem, NoCapture<1>]>;		[IntrReadWriteArgMem, NoCapture<1>]>;
	def int_invariant_end : Intrinsic<[],		def int_invariant_end : Intrinsic<[],
	[llvm_descriptor_ty, llvm_i64_ty,		[llvm_descriptor_ty, llvm_i64_ty,
	llvm_ptr_ty],		llvm_ptr_ty],
	[IntrReadWriteArgMem, NoCapture<2>]>;		[IntrReadWriteArgMem, NoCapture<2>]>;
			//===------------------------ Stackmap Intrinsics -------------------------
			===//
			//
			def int_experimental_stackmap : Intrinsic<[],
			[llvm_i32_ty, llvm_i32_ty, llvm_vararg_ty
			]>;
			def int_experimental_patchpoint_void : Intrinsic<[],
			[llvm_i32_ty, llvm_i32_ty,
			llvm_ptr_ty, llvm_i32_ty,
			llvm_vararg_ty]>;
			def int_experimental_patchpoint_i64 : Intrinsic<[llvm_i64_ty],
			[llvm_i32_ty, llvm_i32_ty,
			llvm_ptr_ty, llvm_i32_ty,
			llvm_vararg_ty]>;
	//===-------------------------- Other Intrinsics -------------------------- ===//		//===-------------------------- Other Intrinsics -------------------------- ===//
	//		//
	def int_flt_rounds : Intrinsic<[llvm_i32_ty]>,		def int_flt_rounds : Intrinsic<[llvm_i32_ty]>,
	GCCBuiltin<"__builtin_flt_rounds">;		GCCBuiltin<"__builtin_flt_rounds">;
	def int_trap : Intrinsic<[], [], [IntrNoReturn]>,		def int_trap : Intrinsic<[], [], [IntrNoReturn]>,
	GCCBuiltin<"__builtin_trap">;		GCCBuiltin<"__builtin_trap">;
	def int_debugtrap : Intrinsic<[]>,		def int_debugtrap : Intrinsic<[]>,
	GCCBuiltin<"__builtin_debugtrap">;		GCCBuiltin<"__builtin_debugtrap">;
	// NOP: calls/invokes to this intrinsic are removed by codegen		// NOP: calls/invokes to this intrinsic are removed by codegen
	skipping to change at line 478		skipping to change at line 519
	def int_convertuu : Intrinsic<[llvm_anyint_ty],		def int_convertuu : Intrinsic<[llvm_anyint_ty],
	[llvm_anyint_ty, llvm_i32_ty, llvm_i32_ty]>;		[llvm_anyint_ty, llvm_i32_ty, llvm_i32_ty]>;
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// Target-specific intrinsics		// Target-specific intrinsics
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	include "llvm/IR/IntrinsicsPowerPC.td"		include "llvm/IR/IntrinsicsPowerPC.td"
	include "llvm/IR/IntrinsicsX86.td"		include "llvm/IR/IntrinsicsX86.td"
	include "llvm/IR/IntrinsicsARM.td"		include "llvm/IR/IntrinsicsARM.td"
			include "llvm/IR/IntrinsicsAArch64.td"
	include "llvm/IR/IntrinsicsXCore.td"		include "llvm/IR/IntrinsicsXCore.td"
	include "llvm/IR/IntrinsicsHexagon.td"		include "llvm/IR/IntrinsicsHexagon.td"
	include "llvm/IR/IntrinsicsNVVM.td"		include "llvm/IR/IntrinsicsNVVM.td"
	include "llvm/IR/IntrinsicsMips.td"		include "llvm/IR/IntrinsicsMips.td"
	include "llvm/IR/IntrinsicsR600.td"		include "llvm/IR/IntrinsicsR600.td"
End of changes. 13 change blocks.
	5 lines changed or deleted		50 lines changed or added

	IntrinsicsARM.td		IntrinsicsARM.td
	skipping to change at line 36		skipping to change at line 36
	Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],		Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
	[IntrNoMem, Commutative]>;		[IntrNoMem, Commutative]>;
	def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,		def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
	Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;		Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
	def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,		def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
	Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;		Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
	def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,		def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
	Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;		Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// Load and Store exclusive doubleword		// Load, Store and Clear exclusive
			def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
			def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>
			;
			def int_arm_clrex : Intrinsic<[]>;
	def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,		def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
	llvm_ptr_ty], [IntrReadWriteArgMem]>;		llvm_ptr_ty]>;
	def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty],		def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
	[IntrReadArgMem]>;
			//===----------------------------------------------------------------------
			===//
			// Data barrier instructions
			def int_arm_dmb : GCCBuiltin<"__builtin_arm_dmb">, Intrinsic<[], [llvm_i32_
			ty]>;
			def int_arm_dsb : GCCBuiltin<"__builtin_arm_dsb">, Intrinsic<[], [llvm_i32_
			ty]>;
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// VFP		// VFP
	def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,		def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
	Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;		Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
	def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,		def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
	Intrinsic<[], [llvm_i32_ty], []>;		Intrinsic<[], [llvm_i32_ty], []>;
	def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],		def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	skipping to change at line 91		skipping to change at line 99
	// Move from two registers to coprocessor		// Move from two registers to coprocessor
	def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,		def int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">,
	Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,		Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
	llvm_i32_ty, llvm_i32_ty], []>;		llvm_i32_ty, llvm_i32_ty], []>;
	def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,		def int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">,
	Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,		Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
	llvm_i32_ty, llvm_i32_ty], []>;		llvm_i32_ty, llvm_i32_ty], []>;
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
			// CRC32
			def int_arm_crc32b : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
			[IntrNoMem]>;
			def int_arm_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
			[IntrNoMem]>;
			def int_arm_crc32h : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
			[IntrNoMem]>;
			def int_arm_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
			[IntrNoMem]>;
			def int_arm_crc32w : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
			[IntrNoMem]>;
			def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
			[IntrNoMem]>;
			//===----------------------------------------------------------------------
			===//
			// HINT
			def int_arm_sevl : Intrinsic<[], []>;
			//===----------------------------------------------------------------------
			===//
	// Advanced SIMD (NEON)		// Advanced SIMD (NEON)
	// The following classes do not correspond directly to GCC builtins.		// The following classes do not correspond directly to GCC builtins.
	class Neon_1Arg_Intrinsic		class Neon_1Arg_Intrinsic
	: Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;		: Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
	class Neon_1Arg_Narrow_Intrinsic		class Neon_1Arg_Narrow_Intrinsic
	: Intrinsic<[llvm_anyvector_ty],		: Intrinsic<[llvm_anyvector_ty],
	[LLVMExtendedElementVectorType<0>], [IntrNoMem]>;		[LLVMExtendedElementVectorType<0>], [IntrNoMem]>;
	class Neon_2Arg_Intrinsic		class Neon_2Arg_Intrinsic
	: Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],		: Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
	skipping to change at line 126		skipping to change at line 154
	class Neon_3Arg_Long_Intrinsic		class Neon_3Arg_Long_Intrinsic
	: Intrinsic<[llvm_anyvector_ty],		: Intrinsic<[llvm_anyvector_ty],
	[LLVMMatchType<0>,		[LLVMMatchType<0>,
	LLVMTruncatedElementVectorType<0>,		LLVMTruncatedElementVectorType<0>,
	LLVMTruncatedElementVectorType<0>],		LLVMTruncatedElementVectorType<0>],
	[IntrNoMem]>;		[IntrNoMem]>;
	class Neon_CvtFxToFP_Intrinsic		class Neon_CvtFxToFP_Intrinsic
	: Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem ]>;		: Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem ]>;
	class Neon_CvtFPToFx_Intrinsic		class Neon_CvtFPToFx_Intrinsic
	: Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem ]>;		: Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem ]>;
			class Neon_CvtFPtoInt_1Arg_Intrinsic
			: Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
	// The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.		// The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
	// Besides the table, VTBL has one other v8i8 argument and VTBX has two.		// Besides the table, VTBL has one other v8i8 argument and VTBX has two.
	// Overall, the classes range from 2 to 6 v8i8 arguments.		// Overall, the classes range from 2 to 6 v8i8 arguments.
	class Neon_Tbl2Arg_Intrinsic		class Neon_Tbl2Arg_Intrinsic
	: Intrinsic<[llvm_v8i8_ty],		: Intrinsic<[llvm_v8i8_ty],
	[llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;		[llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
	class Neon_Tbl3Arg_Intrinsic		class Neon_Tbl3Arg_Intrinsic
	: Intrinsic<[llvm_v8i8_ty],		: Intrinsic<[llvm_v8i8_ty],
	[llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;		[llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
	skipping to change at line 160		skipping to change at line 190
	let Properties = [IntrNoMem, Commutative] in {		let Properties = [IntrNoMem, Commutative] in {
	// Vector Add.		// Vector Add.
	def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;		def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
	def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;		def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
	def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;		def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
	def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;		def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
	def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;		def int_arm_neon_vqadds : Neon_2Arg_Intrinsic;
	def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;		def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic;
	def int_arm_neon_vaddhn : Neon_2Arg_Narrow_Intrinsic;
	def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;		def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
	// Vector Multiply.		// Vector Multiply.
	def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;		def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
	def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;		def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
	def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;		def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
	def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;		def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
	def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;		def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
	def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;		def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
	def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;		def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
	// Vector Multiply and Accumulate/Subtract.
	def int_arm_neon_vqdmlal : Neon_3Arg_Long_Intrinsic;
	def int_arm_neon_vqdmlsl : Neon_3Arg_Long_Intrinsic;
	// Vector Maximum.		// Vector Maximum.
	def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;		def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
	def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;		def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
			def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic;
	// Vector Minimum.		// Vector Minimum.
	def int_arm_neon_vmins : Neon_2Arg_Intrinsic;		def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
	def int_arm_neon_vminu : Neon_2Arg_Intrinsic;		def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
			def int_arm_neon_vminnm : Neon_2Arg_Intrinsic;
	// Vector Reciprocal Step.		// Vector Reciprocal Step.
	def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;		def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
	// Vector Reciprocal Square Root Step.		// Vector Reciprocal Square Root Step.
	def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;		def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
	}		}
	// Vector Subtract.		// Vector Subtract.
	def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;		def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
	def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;		def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
	def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;		def int_arm_neon_vqsubs : Neon_2Arg_Intrinsic;
	def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;		def int_arm_neon_vqsubu : Neon_2Arg_Intrinsic;
	def int_arm_neon_vsubhn : Neon_2Arg_Narrow_Intrinsic;
	def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;		def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
	// Vector Absolute Compare.		// Vector Absolute Compare.
	def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],		def int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty],
	[llvm_v2f32_ty, llvm_v2f32_ty],		[llvm_v2f32_ty, llvm_v2f32_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],		def int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty],
	[llvm_v4f32_ty, llvm_v4f32_ty],		[llvm_v4f32_ty, llvm_v4f32_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],		def int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty],
	skipping to change at line 316		skipping to change at line 342
	// Vector Count One Bits.		// Vector Count One Bits.
	def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;		def int_arm_neon_vcnt : Neon_1Arg_Intrinsic;
	// Vector Reciprocal Estimate.		// Vector Reciprocal Estimate.
	def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;		def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
	// Vector Reciprocal Square Root Estimate.		// Vector Reciprocal Square Root Estimate.
	def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;		def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
			// Vector Conversions Between Floating-point and Integer
			def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic;
			def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic;
			def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic;
			def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic;
			def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic;
			def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic;
			def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic;
			def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic;
	// Vector Conversions Between Floating-point and Fixed-point.		// Vector Conversions Between Floating-point and Fixed-point.
	def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;		def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
	def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;		def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
	def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;		def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
	def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;		def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
	// Vector Conversions Between Half-Precision and Single-Precision.		// Vector Conversions Between Half-Precision and Single-Precision.
	def int_arm_neon_vcvtfp2hf		def int_arm_neon_vcvtfp2hf
	: Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;		: Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
	def int_arm_neon_vcvthf2fp		def int_arm_neon_vcvthf2fp
	skipping to change at line 349		skipping to change at line 385
	// Vector Table Extension.		// Vector Table Extension.
	// Some elements of the destination vector may not be updated, so the origi nal		// Some elements of the destination vector may not be updated, so the origi nal
	// value of that vector is passed as the first argument. The next 1-4		// value of that vector is passed as the first argument. The next 1-4
	// arguments after that are the table.		// arguments after that are the table.
	def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;		def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
	def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;		def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
	def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;		def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
	def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;		def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
			// Vector Rounding
			def int_arm_neon_vrintn : Neon_1Arg_Intrinsic;
			def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
			def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
			def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
			def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
			def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
	// De-interleaving vector loads from N-element structures.		// De-interleaving vector loads from N-element structures.
	// Source operands are the address and alignment.		// Source operands are the address and alignment.
	def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],		def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
	[llvm_ptr_ty, llvm_i32_ty],		[llvm_ptr_ty, llvm_i32_ty],
	[IntrReadArgMem]>;		[IntrReadArgMem]>;
	def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],		def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
	[llvm_ptr_ty, llvm_i32_ty],		[llvm_ptr_ty, llvm_i32_ty],
	[IntrReadArgMem]>;		[IntrReadArgMem]>;
	def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,		def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
	LLVMMatchType<0>],		LLVMMatchType<0>],
	skipping to change at line 428		skipping to change at line 472
	[llvm_ptr_ty, llvm_anyvector_ty,		[llvm_ptr_ty, llvm_anyvector_ty,
	LLVMMatchType<0>, LLVMMatchType<0>,		LLVMMatchType<0>, LLVMMatchType<0>,
	LLVMMatchType<0>, llvm_i32_ty,		LLVMMatchType<0>, llvm_i32_ty,
	llvm_i32_ty], [IntrReadWriteArgMem]> ;		llvm_i32_ty], [IntrReadWriteArgMem]> ;
	// Vector bitwise select.		// Vector bitwise select.
	def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],		def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],
	[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType< 0>],		[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType< 0>],
	[IntrNoMem]>;		[IntrNoMem]>;
			// Crypto instructions
			def int_arm_neon_aesd : Neon_2Arg_Intrinsic;
			def int_arm_neon_aese : Neon_2Arg_Intrinsic;
			def int_arm_neon_aesimc : Neon_1Arg_Intrinsic;
			def int_arm_neon_aesmc : Neon_1Arg_Intrinsic;
			def int_arm_neon_sha1h : Neon_1Arg_Intrinsic;
			def int_arm_neon_sha1su1 : Neon_2Arg_Intrinsic;
			def int_arm_neon_sha256su0 : Neon_2Arg_Intrinsic;
			def int_arm_neon_sha1c : Neon_3Arg_Intrinsic;
			def int_arm_neon_sha1m : Neon_3Arg_Intrinsic;
			def int_arm_neon_sha1p : Neon_3Arg_Intrinsic;
			def int_arm_neon_sha1su0: Neon_3Arg_Intrinsic;
			def int_arm_neon_sha256h: Neon_3Arg_Intrinsic;
			def int_arm_neon_sha256h2: Neon_3Arg_Intrinsic;
			def int_arm_neon_sha256su1: Neon_3Arg_Intrinsic;
	} // end TargetPrefix		} // end TargetPrefix
End of changes. 12 change blocks.
	10 lines changed or deleted		76 lines changed or added

	IntrinsicsMips.td		IntrinsicsMips.td
	skipping to change at line 389		skipping to change at line 389
	def int_mips_subu_ph: GCCBuiltin<"__builtin_mips_subu_ph">,		def int_mips_subu_ph: GCCBuiltin<"__builtin_mips_subu_ph">,
	Intrinsic<[llvm_v2i16_ty], [llvm_v2i16_ty, llvm_v2i16_ty], []>;		Intrinsic<[llvm_v2i16_ty], [llvm_v2i16_ty, llvm_v2i16_ty], []>;
	def int_mips_subu_s_ph: GCCBuiltin<"__builtin_mips_subu_s_ph">,		def int_mips_subu_s_ph: GCCBuiltin<"__builtin_mips_subu_s_ph">,
	Intrinsic<[llvm_v2i16_ty], [llvm_v2i16_ty, llvm_v2i16_ty], []>;		Intrinsic<[llvm_v2i16_ty], [llvm_v2i16_ty, llvm_v2i16_ty], []>;
	def int_mips_subuh_qb: GCCBuiltin<"__builtin_mips_subuh_qb">,		def int_mips_subuh_qb: GCCBuiltin<"__builtin_mips_subuh_qb">,
	Intrinsic<[llvm_v4i8_ty], [llvm_v4i8_ty, llvm_v4i8_ty], [IntrNoMem]>;		Intrinsic<[llvm_v4i8_ty], [llvm_v4i8_ty, llvm_v4i8_ty], [IntrNoMem]>;
	def int_mips_subuh_r_qb: GCCBuiltin<"__builtin_mips_subuh_r_qb">,		def int_mips_subuh_r_qb: GCCBuiltin<"__builtin_mips_subuh_r_qb">,
	Intrinsic<[llvm_v4i8_ty], [llvm_v4i8_ty, llvm_v4i8_ty], [IntrNoMem]>;		Intrinsic<[llvm_v4i8_ty], [llvm_v4i8_ty, llvm_v4i8_ty], [IntrNoMem]>;
			//===----------------------------------------------------------------------
			===//
			// MIPS MSA
			//===----------------------------------------------------------------------
			===//
			// Addition/subtraction
			def int_mips_add_a_b : GCCBuiltin<"__builtin_msa_add_a_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_add_a_h : GCCBuiltin<"__builtin_msa_add_a_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_add_a_w : GCCBuiltin<"__builtin_msa_add_a_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_add_a_d : GCCBuiltin<"__builtin_msa_add_a_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_adds_a_b : GCCBuiltin<"__builtin_msa_adds_a_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_adds_a_h : GCCBuiltin<"__builtin_msa_adds_a_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_adds_a_w : GCCBuiltin<"__builtin_msa_adds_a_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_adds_a_d : GCCBuiltin<"__builtin_msa_adds_a_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_adds_s_b : GCCBuiltin<"__builtin_msa_adds_s_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_adds_s_h : GCCBuiltin<"__builtin_msa_adds_s_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_adds_s_w : GCCBuiltin<"__builtin_msa_adds_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_adds_s_d : GCCBuiltin<"__builtin_msa_adds_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_adds_u_b : GCCBuiltin<"__builtin_msa_adds_u_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_adds_u_h : GCCBuiltin<"__builtin_msa_adds_u_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_adds_u_w : GCCBuiltin<"__builtin_msa_adds_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_adds_u_d : GCCBuiltin<"__builtin_msa_adds_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_addv_b : GCCBuiltin<"__builtin_msa_addv_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_addv_h : GCCBuiltin<"__builtin_msa_addv_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_addv_w : GCCBuiltin<"__builtin_msa_addv_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_addv_d : GCCBuiltin<"__builtin_msa_addv_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_addvi_b : GCCBuiltin<"__builtin_msa_addvi_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_addvi_h : GCCBuiltin<"__builtin_msa_addvi_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_addvi_w : GCCBuiltin<"__builtin_msa_addvi_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_addvi_d : GCCBuiltin<"__builtin_msa_addvi_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_and_v : GCCBuiltin<"__builtin_msa_and_v">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_andi_b : GCCBuiltin<"__builtin_msa_andi_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_asub_s_b : GCCBuiltin<"__builtin_msa_asub_s_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_asub_s_h : GCCBuiltin<"__builtin_msa_asub_s_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_asub_s_w : GCCBuiltin<"__builtin_msa_asub_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_asub_s_d : GCCBuiltin<"__builtin_msa_asub_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_asub_u_b : GCCBuiltin<"__builtin_msa_asub_u_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_asub_u_h : GCCBuiltin<"__builtin_msa_asub_u_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_asub_u_w : GCCBuiltin<"__builtin_msa_asub_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_asub_u_d : GCCBuiltin<"__builtin_msa_asub_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_ave_s_b : GCCBuiltin<"__builtin_msa_ave_s_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_ave_s_h : GCCBuiltin<"__builtin_msa_ave_s_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_ave_s_w : GCCBuiltin<"__builtin_msa_ave_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_ave_s_d : GCCBuiltin<"__builtin_msa_ave_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_ave_u_b : GCCBuiltin<"__builtin_msa_ave_u_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_ave_u_h : GCCBuiltin<"__builtin_msa_ave_u_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_ave_u_w : GCCBuiltin<"__builtin_msa_ave_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_ave_u_d : GCCBuiltin<"__builtin_msa_ave_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_aver_s_b : GCCBuiltin<"__builtin_msa_aver_s_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_aver_s_h : GCCBuiltin<"__builtin_msa_aver_s_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_aver_s_w : GCCBuiltin<"__builtin_msa_aver_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_aver_s_d : GCCBuiltin<"__builtin_msa_aver_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_aver_u_b : GCCBuiltin<"__builtin_msa_aver_u_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_aver_u_h : GCCBuiltin<"__builtin_msa_aver_u_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_aver_u_w : GCCBuiltin<"__builtin_msa_aver_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_aver_u_d : GCCBuiltin<"__builtin_msa_aver_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
			[Commutative, IntrNoMem]>;
			def int_mips_bclr_b : GCCBuiltin<"__builtin_msa_bclr_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_bclr_h : GCCBuiltin<"__builtin_msa_bclr_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_bclr_w : GCCBuiltin<"__builtin_msa_bclr_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_bclr_d : GCCBuiltin<"__builtin_msa_bclr_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_bclri_b : GCCBuiltin<"__builtin_msa_bclri_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_bclri_h : GCCBuiltin<"__builtin_msa_bclri_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_bclri_w : GCCBuiltin<"__builtin_msa_bclri_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_bclri_d : GCCBuiltin<"__builtin_msa_bclri_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_binsl_b : GCCBuiltin<"__builtin_msa_binsl_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
			[IntrNoMem]>;
			def int_mips_binsl_h : GCCBuiltin<"__builtin_msa_binsl_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
			[IntrNoMem]>;
			def int_mips_binsl_w : GCCBuiltin<"__builtin_msa_binsl_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
			[IntrNoMem]>;
			def int_mips_binsl_d : GCCBuiltin<"__builtin_msa_binsl_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty],
			[IntrNoMem]>;
			def int_mips_binsli_b : GCCBuiltin<"__builtin_msa_binsli_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty],
			[IntrNoMem]>;
			def int_mips_binsli_h : GCCBuiltin<"__builtin_msa_binsli_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty],
			[IntrNoMem]>;
			def int_mips_binsli_w : GCCBuiltin<"__builtin_msa_binsli_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty],
			[IntrNoMem]>;
			def int_mips_binsli_d : GCCBuiltin<"__builtin_msa_binsli_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i32_ty],
			[IntrNoMem]>;
			def int_mips_binsr_b : GCCBuiltin<"__builtin_msa_binsr_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
			[IntrNoMem]>;
			def int_mips_binsr_h : GCCBuiltin<"__builtin_msa_binsr_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
			[IntrNoMem]>;
			def int_mips_binsr_w : GCCBuiltin<"__builtin_msa_binsr_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
			[IntrNoMem]>;
			def int_mips_binsr_d : GCCBuiltin<"__builtin_msa_binsr_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty],
			[IntrNoMem]>;
			def int_mips_binsri_b : GCCBuiltin<"__builtin_msa_binsri_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty],
			[IntrNoMem]>;
			def int_mips_binsri_h : GCCBuiltin<"__builtin_msa_binsri_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_i32_ty],
			[IntrNoMem]>;
			def int_mips_binsri_w : GCCBuiltin<"__builtin_msa_binsri_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty],
			[IntrNoMem]>;
			def int_mips_binsri_d : GCCBuiltin<"__builtin_msa_binsri_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty, llvm_i32_ty],
			[IntrNoMem]>;
			def int_mips_bmnz_v : GCCBuiltin<"__builtin_msa_bmnz_v">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
			[IntrNoMem]>;
			def int_mips_bmnzi_b : GCCBuiltin<"__builtin_msa_bmnzi_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty],
			[IntrNoMem]>;
			def int_mips_bmz_v : GCCBuiltin<"__builtin_msa_bmz_v">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
			[IntrNoMem]>;
			def int_mips_bmzi_b : GCCBuiltin<"__builtin_msa_bmzi_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty],
			[IntrNoMem]>;
			def int_mips_bneg_b : GCCBuiltin<"__builtin_msa_bneg_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_bneg_h : GCCBuiltin<"__builtin_msa_bneg_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_bneg_w : GCCBuiltin<"__builtin_msa_bneg_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_bneg_d : GCCBuiltin<"__builtin_msa_bneg_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_bnegi_b : GCCBuiltin<"__builtin_msa_bnegi_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_bnegi_h : GCCBuiltin<"__builtin_msa_bnegi_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_bnegi_w : GCCBuiltin<"__builtin_msa_bnegi_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_bnegi_d : GCCBuiltin<"__builtin_msa_bnegi_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_bnz_b : GCCBuiltin<"__builtin_msa_bnz_b">,
			Intrinsic<[llvm_i32_ty], [llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_bnz_h : GCCBuiltin<"__builtin_msa_bnz_h">,
			Intrinsic<[llvm_i32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_bnz_w : GCCBuiltin<"__builtin_msa_bnz_w">,
			Intrinsic<[llvm_i32_ty], [llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_bnz_d : GCCBuiltin<"__builtin_msa_bnz_d">,
			Intrinsic<[llvm_i32_ty], [llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_bnz_v : GCCBuiltin<"__builtin_msa_bnz_v">,
			Intrinsic<[llvm_i32_ty], [llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_bsel_v : GCCBuiltin<"__builtin_msa_bsel_v">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
			[IntrNoMem]>;
			def int_mips_bseli_b : GCCBuiltin<"__builtin_msa_bseli_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty],
			[IntrNoMem]>;
			def int_mips_bset_b : GCCBuiltin<"__builtin_msa_bset_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_bset_h : GCCBuiltin<"__builtin_msa_bset_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_bset_w : GCCBuiltin<"__builtin_msa_bset_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_bset_d : GCCBuiltin<"__builtin_msa_bset_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_bseti_b : GCCBuiltin<"__builtin_msa_bseti_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_bseti_h : GCCBuiltin<"__builtin_msa_bseti_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_bseti_w : GCCBuiltin<"__builtin_msa_bseti_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_bseti_d : GCCBuiltin<"__builtin_msa_bseti_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_bz_b : GCCBuiltin<"__builtin_msa_bz_b">,
			Intrinsic<[llvm_i32_ty], [llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_bz_h : GCCBuiltin<"__builtin_msa_bz_h">,
			Intrinsic<[llvm_i32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_bz_w : GCCBuiltin<"__builtin_msa_bz_w">,
			Intrinsic<[llvm_i32_ty], [llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_bz_d : GCCBuiltin<"__builtin_msa_bz_d">,
			Intrinsic<[llvm_i32_ty], [llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_bz_v : GCCBuiltin<"__builtin_msa_bz_v">,
			Intrinsic<[llvm_i32_ty], [llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_ceq_b : GCCBuiltin<"__builtin_msa_ceq_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_ceq_h : GCCBuiltin<"__builtin_msa_ceq_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_ceq_w : GCCBuiltin<"__builtin_msa_ceq_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_ceq_d : GCCBuiltin<"__builtin_msa_ceq_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_ceqi_b : GCCBuiltin<"__builtin_msa_ceqi_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_ceqi_h : GCCBuiltin<"__builtin_msa_ceqi_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_ceqi_w : GCCBuiltin<"__builtin_msa_ceqi_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_ceqi_d : GCCBuiltin<"__builtin_msa_ceqi_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_cfcmsa : GCCBuiltin<"__builtin_msa_cfcmsa">,
			Intrinsic<[llvm_i32_ty], [llvm_i32_ty], []>;
			def int_mips_cle_s_b : GCCBuiltin<"__builtin_msa_cle_s_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_cle_s_h : GCCBuiltin<"__builtin_msa_cle_s_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_cle_s_w : GCCBuiltin<"__builtin_msa_cle_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_cle_s_d : GCCBuiltin<"__builtin_msa_cle_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_cle_u_b : GCCBuiltin<"__builtin_msa_cle_u_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_cle_u_h : GCCBuiltin<"__builtin_msa_cle_u_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_cle_u_w : GCCBuiltin<"__builtin_msa_cle_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_cle_u_d : GCCBuiltin<"__builtin_msa_cle_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_clei_s_b : GCCBuiltin<"__builtin_msa_clei_s_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_clei_s_h : GCCBuiltin<"__builtin_msa_clei_s_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_clei_s_w : GCCBuiltin<"__builtin_msa_clei_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_clei_s_d : GCCBuiltin<"__builtin_msa_clei_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_clei_u_b : GCCBuiltin<"__builtin_msa_clei_u_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_clei_u_h : GCCBuiltin<"__builtin_msa_clei_u_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_clei_u_w : GCCBuiltin<"__builtin_msa_clei_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_clei_u_d : GCCBuiltin<"__builtin_msa_clei_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_clt_s_b : GCCBuiltin<"__builtin_msa_clt_s_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_clt_s_h : GCCBuiltin<"__builtin_msa_clt_s_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_clt_s_w : GCCBuiltin<"__builtin_msa_clt_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_clt_s_d : GCCBuiltin<"__builtin_msa_clt_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_clt_u_b : GCCBuiltin<"__builtin_msa_clt_u_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_clt_u_h : GCCBuiltin<"__builtin_msa_clt_u_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_clt_u_w : GCCBuiltin<"__builtin_msa_clt_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_clt_u_d : GCCBuiltin<"__builtin_msa_clt_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_clti_s_b : GCCBuiltin<"__builtin_msa_clti_s_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_clti_s_h : GCCBuiltin<"__builtin_msa_clti_s_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_clti_s_w : GCCBuiltin<"__builtin_msa_clti_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_clti_s_d : GCCBuiltin<"__builtin_msa_clti_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_clti_u_b : GCCBuiltin<"__builtin_msa_clti_u_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_clti_u_h : GCCBuiltin<"__builtin_msa_clti_u_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_clti_u_w : GCCBuiltin<"__builtin_msa_clti_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_clti_u_d : GCCBuiltin<"__builtin_msa_clti_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_copy_s_b : GCCBuiltin<"__builtin_msa_copy_s_b">,
			Intrinsic<[llvm_i32_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_copy_s_h : GCCBuiltin<"__builtin_msa_copy_s_h">,
			Intrinsic<[llvm_i32_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_copy_s_w : GCCBuiltin<"__builtin_msa_copy_s_w">,
			Intrinsic<[llvm_i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_copy_s_d : GCCBuiltin<"__builtin_msa_copy_s_d">,
			Intrinsic<[llvm_i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_copy_u_b : GCCBuiltin<"__builtin_msa_copy_u_b">,
			Intrinsic<[llvm_i32_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_copy_u_h : GCCBuiltin<"__builtin_msa_copy_u_h">,
			Intrinsic<[llvm_i32_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_copy_u_w : GCCBuiltin<"__builtin_msa_copy_u_w">,
			Intrinsic<[llvm_i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_copy_u_d : GCCBuiltin<"__builtin_msa_copy_u_d">,
			Intrinsic<[llvm_i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_ctcmsa : GCCBuiltin<"__builtin_msa_ctcmsa">,
			Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>;
			def int_mips_div_s_b : GCCBuiltin<"__builtin_msa_div_s_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_div_s_h : GCCBuiltin<"__builtin_msa_div_s_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_div_s_w : GCCBuiltin<"__builtin_msa_div_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_div_s_d : GCCBuiltin<"__builtin_msa_div_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_div_u_b : GCCBuiltin<"__builtin_msa_div_u_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_div_u_h : GCCBuiltin<"__builtin_msa_div_u_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_div_u_w : GCCBuiltin<"__builtin_msa_div_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_div_u_d : GCCBuiltin<"__builtin_msa_div_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_dotp_s_h : GCCBuiltin<"__builtin_msa_dotp_s_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_dotp_s_w : GCCBuiltin<"__builtin_msa_dotp_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_dotp_s_d : GCCBuiltin<"__builtin_msa_dotp_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_dotp_u_h : GCCBuiltin<"__builtin_msa_dotp_u_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_dotp_u_w : GCCBuiltin<"__builtin_msa_dotp_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_dotp_u_d : GCCBuiltin<"__builtin_msa_dotp_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_dpadd_s_h : GCCBuiltin<"__builtin_msa_dpadd_s_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty],
			[IntrNoMem]>;
			def int_mips_dpadd_s_w : GCCBuiltin<"__builtin_msa_dpadd_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
			[IntrNoMem]>;
			def int_mips_dpadd_s_d : GCCBuiltin<"__builtin_msa_dpadd_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v4i32_ty, llvm_v4i32_ty],
			[IntrNoMem]>;
			def int_mips_dpadd_u_h : GCCBuiltin<"__builtin_msa_dpadd_u_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty],
			[IntrNoMem]>;
			def int_mips_dpadd_u_w : GCCBuiltin<"__builtin_msa_dpadd_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
			[IntrNoMem]>;
			def int_mips_dpadd_u_d : GCCBuiltin<"__builtin_msa_dpadd_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v4i32_ty, llvm_v4i32_ty],
			[IntrNoMem]>;
			def int_mips_dpsub_s_h : GCCBuiltin<"__builtin_msa_dpsub_s_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty],
			[IntrNoMem]>;
			def int_mips_dpsub_s_w : GCCBuiltin<"__builtin_msa_dpsub_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
			[IntrNoMem]>;
			def int_mips_dpsub_s_d : GCCBuiltin<"__builtin_msa_dpsub_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v4i32_ty, llvm_v4i32_ty],
			[IntrNoMem]>;
			def int_mips_dpsub_u_h : GCCBuiltin<"__builtin_msa_dpsub_u_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v16i8_ty, llvm_v16i8_ty],
			[IntrNoMem]>;
			def int_mips_dpsub_u_w : GCCBuiltin<"__builtin_msa_dpsub_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v8i16_ty, llvm_v8i16_ty],
			[IntrNoMem]>;
			def int_mips_dpsub_u_d : GCCBuiltin<"__builtin_msa_dpsub_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v4i32_ty, llvm_v4i32_ty],
			[IntrNoMem]>;
			def int_mips_fadd_w : GCCBuiltin<"__builtin_msa_fadd_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fadd_d : GCCBuiltin<"__builtin_msa_fadd_d">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fcaf_w : GCCBuiltin<"__builtin_msa_fcaf_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fcaf_d : GCCBuiltin<"__builtin_msa_fcaf_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fceq_w : GCCBuiltin<"__builtin_msa_fceq_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fceq_d : GCCBuiltin<"__builtin_msa_fceq_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fcle_w : GCCBuiltin<"__builtin_msa_fcle_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fcle_d : GCCBuiltin<"__builtin_msa_fcle_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fclt_w : GCCBuiltin<"__builtin_msa_fclt_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fclt_d : GCCBuiltin<"__builtin_msa_fclt_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fclass_w : GCCBuiltin<"__builtin_msa_fclass_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fclass_d : GCCBuiltin<"__builtin_msa_fclass_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fcne_w : GCCBuiltin<"__builtin_msa_fcne_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fcne_d : GCCBuiltin<"__builtin_msa_fcne_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fcor_w : GCCBuiltin<"__builtin_msa_fcor_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fcor_d : GCCBuiltin<"__builtin_msa_fcor_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fcueq_w : GCCBuiltin<"__builtin_msa_fcueq_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fcueq_d : GCCBuiltin<"__builtin_msa_fcueq_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fcule_w : GCCBuiltin<"__builtin_msa_fcule_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fcule_d : GCCBuiltin<"__builtin_msa_fcule_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fcult_w : GCCBuiltin<"__builtin_msa_fcult_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fcult_d : GCCBuiltin<"__builtin_msa_fcult_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fcun_w : GCCBuiltin<"__builtin_msa_fcun_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fcun_d : GCCBuiltin<"__builtin_msa_fcun_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fcune_w : GCCBuiltin<"__builtin_msa_fcune_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fcune_d : GCCBuiltin<"__builtin_msa_fcune_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fdiv_w : GCCBuiltin<"__builtin_msa_fdiv_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fdiv_d : GCCBuiltin<"__builtin_msa_fdiv_d">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fexdo_h : GCCBuiltin<"__builtin_msa_fexdo_h">,
			Intrinsic<[llvm_v8f16_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fexdo_w : GCCBuiltin<"__builtin_msa_fexdo_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fexp2_w : GCCBuiltin<"__builtin_msa_fexp2_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_fexp2_d : GCCBuiltin<"__builtin_msa_fexp2_d">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_fexupl_w : GCCBuiltin<"__builtin_msa_fexupl_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v8f16_ty], [IntrNoMem]>;
			def int_mips_fexupl_d : GCCBuiltin<"__builtin_msa_fexupl_d">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fexupr_w : GCCBuiltin<"__builtin_msa_fexupr_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v8f16_ty], [IntrNoMem]>;
			def int_mips_fexupr_d : GCCBuiltin<"__builtin_msa_fexupr_d">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_ffint_s_w : GCCBuiltin<"__builtin_msa_ffint_s_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_ffint_s_d : GCCBuiltin<"__builtin_msa_ffint_s_d">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_ffint_u_w : GCCBuiltin<"__builtin_msa_ffint_u_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_ffint_u_d : GCCBuiltin<"__builtin_msa_ffint_u_d">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_ffql_w : GCCBuiltin<"__builtin_msa_ffql_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_ffql_d : GCCBuiltin<"__builtin_msa_ffql_d">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_ffqr_w : GCCBuiltin<"__builtin_msa_ffqr_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_ffqr_d : GCCBuiltin<"__builtin_msa_ffqr_d">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_fill_b : GCCBuiltin<"__builtin_msa_fill_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_i32_ty], [IntrNoMem]>;
			def int_mips_fill_h : GCCBuiltin<"__builtin_msa_fill_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_i32_ty], [IntrNoMem]>;
			def int_mips_fill_w : GCCBuiltin<"__builtin_msa_fill_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_i32_ty], [IntrNoMem]>;
			def int_mips_fill_d : GCCBuiltin<"__builtin_msa_fill_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_i64_ty], [IntrNoMem]>;
			def int_mips_flog2_w : GCCBuiltin<"__builtin_msa_flog2_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_flog2_d : GCCBuiltin<"__builtin_msa_flog2_d">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fmadd_w : GCCBuiltin<"__builtin_msa_fmadd_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
			[IntrNoMem]>;
			def int_mips_fmadd_d : GCCBuiltin<"__builtin_msa_fmadd_d">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
			[IntrNoMem]>;
			def int_mips_fmax_w : GCCBuiltin<"__builtin_msa_fmax_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fmax_d : GCCBuiltin<"__builtin_msa_fmax_d">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fmax_a_w : GCCBuiltin<"__builtin_msa_fmax_a_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fmax_a_d : GCCBuiltin<"__builtin_msa_fmax_a_d">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fmin_w : GCCBuiltin<"__builtin_msa_fmin_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fmin_d : GCCBuiltin<"__builtin_msa_fmin_d">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fmin_a_w : GCCBuiltin<"__builtin_msa_fmin_a_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fmin_a_d : GCCBuiltin<"__builtin_msa_fmin_a_d">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fmsub_w : GCCBuiltin<"__builtin_msa_fmsub_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
			[IntrNoMem]>;
			def int_mips_fmsub_d : GCCBuiltin<"__builtin_msa_fmsub_d">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
			[IntrNoMem]>;
			def int_mips_fmul_w : GCCBuiltin<"__builtin_msa_fmul_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fmul_d : GCCBuiltin<"__builtin_msa_fmul_d">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_frint_w : GCCBuiltin<"__builtin_msa_frint_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_frint_d : GCCBuiltin<"__builtin_msa_frint_d">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_frcp_w : GCCBuiltin<"__builtin_msa_frcp_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_frcp_d : GCCBuiltin<"__builtin_msa_frcp_d">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_frsqrt_w : GCCBuiltin<"__builtin_msa_frsqrt_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_frsqrt_d : GCCBuiltin<"__builtin_msa_frsqrt_d">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fsaf_w : GCCBuiltin<"__builtin_msa_fsaf_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fsaf_d : GCCBuiltin<"__builtin_msa_fsaf_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fseq_w : GCCBuiltin<"__builtin_msa_fseq_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fseq_d : GCCBuiltin<"__builtin_msa_fseq_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fsle_w : GCCBuiltin<"__builtin_msa_fsle_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fsle_d : GCCBuiltin<"__builtin_msa_fsle_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fslt_w : GCCBuiltin<"__builtin_msa_fslt_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fslt_d : GCCBuiltin<"__builtin_msa_fslt_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fsne_w : GCCBuiltin<"__builtin_msa_fsne_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fsne_d : GCCBuiltin<"__builtin_msa_fsne_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fsor_w : GCCBuiltin<"__builtin_msa_fsor_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fsor_d : GCCBuiltin<"__builtin_msa_fsor_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fsqrt_w : GCCBuiltin<"__builtin_msa_fsqrt_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fsqrt_d : GCCBuiltin<"__builtin_msa_fsqrt_d">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fsub_w : GCCBuiltin<"__builtin_msa_fsub_w">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fsub_d : GCCBuiltin<"__builtin_msa_fsub_d">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fsueq_w : GCCBuiltin<"__builtin_msa_fsueq_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fsueq_d : GCCBuiltin<"__builtin_msa_fsueq_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fsule_w : GCCBuiltin<"__builtin_msa_fsule_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fsule_d : GCCBuiltin<"__builtin_msa_fsule_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fsult_w : GCCBuiltin<"__builtin_msa_fsult_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fsult_d : GCCBuiltin<"__builtin_msa_fsult_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fsun_w : GCCBuiltin<"__builtin_msa_fsun_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fsun_d : GCCBuiltin<"__builtin_msa_fsun_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_fsune_w : GCCBuiltin<"__builtin_msa_fsune_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_fsune_d : GCCBuiltin<"__builtin_msa_fsune_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_ftint_s_w : GCCBuiltin<"__builtin_msa_ftint_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_ftint_s_d : GCCBuiltin<"__builtin_msa_ftint_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_ftint_u_w : GCCBuiltin<"__builtin_msa_ftint_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_ftint_u_d : GCCBuiltin<"__builtin_msa_ftint_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_ftq_h : GCCBuiltin<"__builtin_msa_ftq_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_ftq_w : GCCBuiltin<"__builtin_msa_ftq_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v2f64_ty, llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_ftrunc_s_w : GCCBuiltin<"__builtin_msa_ftrunc_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_ftrunc_s_d : GCCBuiltin<"__builtin_msa_ftrunc_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_ftrunc_u_w : GCCBuiltin<"__builtin_msa_ftrunc_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
			def int_mips_ftrunc_u_d : GCCBuiltin<"__builtin_msa_ftrunc_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
			def int_mips_hadd_s_h : GCCBuiltin<"__builtin_msa_hadd_s_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_hadd_s_w : GCCBuiltin<"__builtin_msa_hadd_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_hadd_s_d : GCCBuiltin<"__builtin_msa_hadd_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_hadd_u_h : GCCBuiltin<"__builtin_msa_hadd_u_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_hadd_u_w : GCCBuiltin<"__builtin_msa_hadd_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_hadd_u_d : GCCBuiltin<"__builtin_msa_hadd_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_hsub_s_h : GCCBuiltin<"__builtin_msa_hsub_s_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_hsub_s_w : GCCBuiltin<"__builtin_msa_hsub_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_hsub_s_d : GCCBuiltin<"__builtin_msa_hsub_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_hsub_u_h : GCCBuiltin<"__builtin_msa_hsub_u_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_hsub_u_w : GCCBuiltin<"__builtin_msa_hsub_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_hsub_u_d : GCCBuiltin<"__builtin_msa_hsub_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_ilvev_b : GCCBuiltin<"__builtin_msa_ilvev_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_ilvev_h : GCCBuiltin<"__builtin_msa_ilvev_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_ilvev_w : GCCBuiltin<"__builtin_msa_ilvev_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_ilvev_d : GCCBuiltin<"__builtin_msa_ilvev_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_ilvl_b : GCCBuiltin<"__builtin_msa_ilvl_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_ilvl_h : GCCBuiltin<"__builtin_msa_ilvl_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_ilvl_w : GCCBuiltin<"__builtin_msa_ilvl_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_ilvl_d : GCCBuiltin<"__builtin_msa_ilvl_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_ilvod_b : GCCBuiltin<"__builtin_msa_ilvod_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_ilvod_h : GCCBuiltin<"__builtin_msa_ilvod_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_ilvod_w : GCCBuiltin<"__builtin_msa_ilvod_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_ilvod_d : GCCBuiltin<"__builtin_msa_ilvod_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_ilvr_b : GCCBuiltin<"__builtin_msa_ilvr_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_ilvr_h : GCCBuiltin<"__builtin_msa_ilvr_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_ilvr_w : GCCBuiltin<"__builtin_msa_ilvr_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_ilvr_d : GCCBuiltin<"__builtin_msa_ilvr_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_insert_b : GCCBuiltin<"__builtin_msa_insert_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty],
			[IntrNoMem]>;
			def int_mips_insert_h : GCCBuiltin<"__builtin_msa_insert_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty, llvm_i32_ty],
			[IntrNoMem]>;
			def int_mips_insert_w : GCCBuiltin<"__builtin_msa_insert_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty, llvm_i32_ty],
			[IntrNoMem]>;
			def int_mips_insert_d : GCCBuiltin<"__builtin_msa_insert_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty, llvm_i64_ty],
			[IntrNoMem]>;
			def int_mips_insve_b : GCCBuiltin<"__builtin_msa_insve_b">,
			Intrinsic<[llvm_v16i8_ty],
			[llvm_v16i8_ty, llvm_i32_ty, llvm_v16i8_ty],
			[IntrNoMem]>;
			def int_mips_insve_h : GCCBuiltin<"__builtin_msa_insve_h">,
			Intrinsic<[llvm_v8i16_ty],
			[llvm_v8i16_ty, llvm_i32_ty, llvm_v8i16_ty],
			[IntrNoMem]>;
			def int_mips_insve_w : GCCBuiltin<"__builtin_msa_insve_w">,
			Intrinsic<[llvm_v4i32_ty],
			[llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
			[IntrNoMem]>;
			def int_mips_insve_d : GCCBuiltin<"__builtin_msa_insve_d">,
			Intrinsic<[llvm_v2i64_ty],
			[llvm_v2i64_ty, llvm_i32_ty, llvm_v2i64_ty],
			[IntrNoMem]>;
			def int_mips_ld_b : GCCBuiltin<"__builtin_msa_ld_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_ptr_ty, llvm_i32_ty],
			[IntrReadArgMem]>;
			def int_mips_ld_h : GCCBuiltin<"__builtin_msa_ld_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_ptr_ty, llvm_i32_ty],
			[IntrReadArgMem]>;
			def int_mips_ld_w : GCCBuiltin<"__builtin_msa_ld_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty],
			[IntrReadArgMem]>;
			def int_mips_ld_d : GCCBuiltin<"__builtin_msa_ld_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_ptr_ty, llvm_i32_ty],
			[IntrReadArgMem]>;
			def int_mips_ldi_b : GCCBuiltin<"__builtin_msa_ldi_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_i32_ty], [IntrNoMem]>;
			def int_mips_ldi_h : GCCBuiltin<"__builtin_msa_ldi_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_i32_ty], [IntrNoMem]>;
			def int_mips_ldi_w : GCCBuiltin<"__builtin_msa_ldi_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_i32_ty], [IntrNoMem]>;
			def int_mips_ldi_d : GCCBuiltin<"__builtin_msa_ldi_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_i32_ty], [IntrNoMem]>;
			// This instruction is part of the MSA spec but it does not share the
			// __builtin_msa prefix because it operates on the GPR registers.
			def int_mips_lsa : GCCBuiltin<"__builtin_mips_lsa">,
			Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
			[IntrNoMem]>;
			def int_mips_madd_q_h : GCCBuiltin<"__builtin_msa_madd_q_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
			[IntrNoMem]>;
			def int_mips_madd_q_w : GCCBuiltin<"__builtin_msa_madd_q_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
			[IntrNoMem]>;
			def int_mips_maddr_q_h : GCCBuiltin<"__builtin_msa_maddr_q_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
			[IntrNoMem]>;
			def int_mips_maddr_q_w : GCCBuiltin<"__builtin_msa_maddr_q_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
			[IntrNoMem]>;
			def int_mips_maddv_b : GCCBuiltin<"__builtin_msa_maddv_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
			[IntrNoMem]>;
			def int_mips_maddv_h : GCCBuiltin<"__builtin_msa_maddv_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
			[IntrNoMem]>;
			def int_mips_maddv_w : GCCBuiltin<"__builtin_msa_maddv_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
			[IntrNoMem]>;
			def int_mips_maddv_d : GCCBuiltin<"__builtin_msa_maddv_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty],
			[IntrNoMem]>;
			def int_mips_max_a_b : GCCBuiltin<"__builtin_msa_max_a_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_max_a_h : GCCBuiltin<"__builtin_msa_max_a_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_max_a_w : GCCBuiltin<"__builtin_msa_max_a_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_max_a_d : GCCBuiltin<"__builtin_msa_max_a_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_max_s_b : GCCBuiltin<"__builtin_msa_max_s_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_max_s_h : GCCBuiltin<"__builtin_msa_max_s_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_max_s_w : GCCBuiltin<"__builtin_msa_max_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_max_s_d : GCCBuiltin<"__builtin_msa_max_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_max_u_b : GCCBuiltin<"__builtin_msa_max_u_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_max_u_h : GCCBuiltin<"__builtin_msa_max_u_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_max_u_w : GCCBuiltin<"__builtin_msa_max_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_max_u_d : GCCBuiltin<"__builtin_msa_max_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_maxi_s_b : GCCBuiltin<"__builtin_msa_maxi_s_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_maxi_s_h : GCCBuiltin<"__builtin_msa_maxi_s_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_maxi_s_w : GCCBuiltin<"__builtin_msa_maxi_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_maxi_s_d : GCCBuiltin<"__builtin_msa_maxi_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_maxi_u_b : GCCBuiltin<"__builtin_msa_maxi_u_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_maxi_u_h : GCCBuiltin<"__builtin_msa_maxi_u_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_maxi_u_w : GCCBuiltin<"__builtin_msa_maxi_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_maxi_u_d : GCCBuiltin<"__builtin_msa_maxi_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_min_a_b : GCCBuiltin<"__builtin_msa_min_a_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_min_a_h : GCCBuiltin<"__builtin_msa_min_a_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_min_a_w : GCCBuiltin<"__builtin_msa_min_a_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_min_a_d : GCCBuiltin<"__builtin_msa_min_a_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_min_s_b : GCCBuiltin<"__builtin_msa_min_s_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_min_s_h : GCCBuiltin<"__builtin_msa_min_s_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_min_s_w : GCCBuiltin<"__builtin_msa_min_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_min_s_d : GCCBuiltin<"__builtin_msa_min_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_min_u_b : GCCBuiltin<"__builtin_msa_min_u_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_min_u_h : GCCBuiltin<"__builtin_msa_min_u_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_min_u_w : GCCBuiltin<"__builtin_msa_min_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_min_u_d : GCCBuiltin<"__builtin_msa_min_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_mini_s_b : GCCBuiltin<"__builtin_msa_mini_s_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_mini_s_h : GCCBuiltin<"__builtin_msa_mini_s_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_mini_s_w : GCCBuiltin<"__builtin_msa_mini_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_mini_s_d : GCCBuiltin<"__builtin_msa_mini_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_mini_u_b : GCCBuiltin<"__builtin_msa_mini_u_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_mini_u_h : GCCBuiltin<"__builtin_msa_mini_u_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_mini_u_w : GCCBuiltin<"__builtin_msa_mini_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_mini_u_d : GCCBuiltin<"__builtin_msa_mini_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_mod_s_b : GCCBuiltin<"__builtin_msa_mod_s_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_mod_s_h : GCCBuiltin<"__builtin_msa_mod_s_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_mod_s_w : GCCBuiltin<"__builtin_msa_mod_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_mod_s_d : GCCBuiltin<"__builtin_msa_mod_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_mod_u_b : GCCBuiltin<"__builtin_msa_mod_u_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_mod_u_h : GCCBuiltin<"__builtin_msa_mod_u_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_mod_u_w : GCCBuiltin<"__builtin_msa_mod_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_mod_u_d : GCCBuiltin<"__builtin_msa_mod_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_move_v : GCCBuiltin<"__builtin_msa_move_v">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_msub_q_h : GCCBuiltin<"__builtin_msa_msub_q_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
			[IntrNoMem]>;
			def int_mips_msub_q_w : GCCBuiltin<"__builtin_msa_msub_q_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
			[IntrNoMem]>;
			def int_mips_msubr_q_h : GCCBuiltin<"__builtin_msa_msubr_q_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
			[IntrNoMem]>;
			def int_mips_msubr_q_w : GCCBuiltin<"__builtin_msa_msubr_q_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
			[IntrNoMem]>;
			def int_mips_msubv_b : GCCBuiltin<"__builtin_msa_msubv_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
			[IntrNoMem]>;
			def int_mips_msubv_h : GCCBuiltin<"__builtin_msa_msubv_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
			[IntrNoMem]>;
			def int_mips_msubv_w : GCCBuiltin<"__builtin_msa_msubv_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
			[IntrNoMem]>;
			def int_mips_msubv_d : GCCBuiltin<"__builtin_msa_msubv_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty],
			[IntrNoMem]>;
			def int_mips_mul_q_h : GCCBuiltin<"__builtin_msa_mul_q_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_mul_q_w : GCCBuiltin<"__builtin_msa_mul_q_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_mulr_q_h : GCCBuiltin<"__builtin_msa_mulr_q_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_mulr_q_w : GCCBuiltin<"__builtin_msa_mulr_q_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_mulv_b : GCCBuiltin<"__builtin_msa_mulv_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_mulv_h : GCCBuiltin<"__builtin_msa_mulv_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_mulv_w : GCCBuiltin<"__builtin_msa_mulv_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_mulv_d : GCCBuiltin<"__builtin_msa_mulv_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_nloc_b : GCCBuiltin<"__builtin_msa_nloc_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_nloc_h : GCCBuiltin<"__builtin_msa_nloc_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_nloc_w : GCCBuiltin<"__builtin_msa_nloc_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_nloc_d : GCCBuiltin<"__builtin_msa_nloc_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_nlzc_b : GCCBuiltin<"__builtin_msa_nlzc_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_nlzc_h : GCCBuiltin<"__builtin_msa_nlzc_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_nlzc_w : GCCBuiltin<"__builtin_msa_nlzc_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_nlzc_d : GCCBuiltin<"__builtin_msa_nlzc_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_nor_v : GCCBuiltin<"__builtin_msa_nor_v">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_nori_b : GCCBuiltin<"__builtin_msa_nori_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_or_v : GCCBuiltin<"__builtin_msa_or_v">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_ori_b : GCCBuiltin<"__builtin_msa_ori_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_pckev_b : GCCBuiltin<"__builtin_msa_pckev_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_pckev_h : GCCBuiltin<"__builtin_msa_pckev_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_pckev_w : GCCBuiltin<"__builtin_msa_pckev_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_pckev_d : GCCBuiltin<"__builtin_msa_pckev_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_pckod_b : GCCBuiltin<"__builtin_msa_pckod_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_pckod_h : GCCBuiltin<"__builtin_msa_pckod_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_pckod_w : GCCBuiltin<"__builtin_msa_pckod_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_pckod_d : GCCBuiltin<"__builtin_msa_pckod_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_pcnt_b : GCCBuiltin<"__builtin_msa_pcnt_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_pcnt_h : GCCBuiltin<"__builtin_msa_pcnt_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_pcnt_w : GCCBuiltin<"__builtin_msa_pcnt_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_pcnt_d : GCCBuiltin<"__builtin_msa_pcnt_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_sat_s_b : GCCBuiltin<"__builtin_msa_sat_s_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_sat_s_h : GCCBuiltin<"__builtin_msa_sat_s_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_sat_s_w : GCCBuiltin<"__builtin_msa_sat_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_sat_s_d : GCCBuiltin<"__builtin_msa_sat_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_sat_u_b : GCCBuiltin<"__builtin_msa_sat_u_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_sat_u_h : GCCBuiltin<"__builtin_msa_sat_u_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_sat_u_w : GCCBuiltin<"__builtin_msa_sat_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_sat_u_d : GCCBuiltin<"__builtin_msa_sat_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_shf_b : GCCBuiltin<"__builtin_msa_shf_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_shf_h : GCCBuiltin<"__builtin_msa_shf_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_shf_w : GCCBuiltin<"__builtin_msa_shf_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_sld_b : GCCBuiltin<"__builtin_msa_sld_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_sld_h : GCCBuiltin<"__builtin_msa_sld_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_sld_w : GCCBuiltin<"__builtin_msa_sld_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_sld_d : GCCBuiltin<"__builtin_msa_sld_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_sldi_b : GCCBuiltin<"__builtin_msa_sldi_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_sldi_h : GCCBuiltin<"__builtin_msa_sldi_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_sldi_w : GCCBuiltin<"__builtin_msa_sldi_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_sldi_d : GCCBuiltin<"__builtin_msa_sldi_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_sll_b : GCCBuiltin<"__builtin_msa_sll_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_sll_h : GCCBuiltin<"__builtin_msa_sll_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_sll_w : GCCBuiltin<"__builtin_msa_sll_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_sll_d : GCCBuiltin<"__builtin_msa_sll_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_slli_b : GCCBuiltin<"__builtin_msa_slli_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_slli_h : GCCBuiltin<"__builtin_msa_slli_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_slli_w : GCCBuiltin<"__builtin_msa_slli_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_slli_d : GCCBuiltin<"__builtin_msa_slli_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_splat_b : GCCBuiltin<"__builtin_msa_splat_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_splat_h : GCCBuiltin<"__builtin_msa_splat_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_splat_w : GCCBuiltin<"__builtin_msa_splat_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_splat_d : GCCBuiltin<"__builtin_msa_splat_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_splati_b : GCCBuiltin<"__builtin_msa_splati_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_splati_h : GCCBuiltin<"__builtin_msa_splati_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_splati_w : GCCBuiltin<"__builtin_msa_splati_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_splati_d : GCCBuiltin<"__builtin_msa_splati_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_sra_b : GCCBuiltin<"__builtin_msa_sra_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_sra_h : GCCBuiltin<"__builtin_msa_sra_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_sra_w : GCCBuiltin<"__builtin_msa_sra_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_sra_d : GCCBuiltin<"__builtin_msa_sra_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_srai_b : GCCBuiltin<"__builtin_msa_srai_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_srai_h : GCCBuiltin<"__builtin_msa_srai_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_srai_w : GCCBuiltin<"__builtin_msa_srai_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_srai_d : GCCBuiltin<"__builtin_msa_srai_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_srar_b : GCCBuiltin<"__builtin_msa_srar_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_srar_h : GCCBuiltin<"__builtin_msa_srar_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_srar_w : GCCBuiltin<"__builtin_msa_srar_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_srar_d : GCCBuiltin<"__builtin_msa_srar_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_srari_b : GCCBuiltin<"__builtin_msa_srari_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_srari_h : GCCBuiltin<"__builtin_msa_srari_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_srari_w : GCCBuiltin<"__builtin_msa_srari_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_srari_d : GCCBuiltin<"__builtin_msa_srari_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_srl_b : GCCBuiltin<"__builtin_msa_srl_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_srl_h : GCCBuiltin<"__builtin_msa_srl_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_srl_w : GCCBuiltin<"__builtin_msa_srl_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_srl_d : GCCBuiltin<"__builtin_msa_srl_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_srli_b : GCCBuiltin<"__builtin_msa_srli_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_srli_h : GCCBuiltin<"__builtin_msa_srli_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_srli_w : GCCBuiltin<"__builtin_msa_srli_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_srli_d : GCCBuiltin<"__builtin_msa_srli_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_srlr_b : GCCBuiltin<"__builtin_msa_srlr_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_srlr_h : GCCBuiltin<"__builtin_msa_srlr_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_srlr_w : GCCBuiltin<"__builtin_msa_srlr_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_srlr_d : GCCBuiltin<"__builtin_msa_srlr_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_srlri_b : GCCBuiltin<"__builtin_msa_srlri_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_srlri_h : GCCBuiltin<"__builtin_msa_srlri_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_srlri_w : GCCBuiltin<"__builtin_msa_srlri_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_srlri_d : GCCBuiltin<"__builtin_msa_srlri_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_st_b : GCCBuiltin<"__builtin_msa_st_b">,
			Intrinsic<[], [llvm_v16i8_ty, llvm_ptr_ty, llvm_i32_ty],
			[IntrReadWriteArgMem]>;
			def int_mips_st_h : GCCBuiltin<"__builtin_msa_st_h">,
			Intrinsic<[], [llvm_v8i16_ty, llvm_ptr_ty, llvm_i32_ty],
			[IntrReadWriteArgMem]>;
			def int_mips_st_w : GCCBuiltin<"__builtin_msa_st_w">,
			Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty, llvm_i32_ty],
			[IntrReadWriteArgMem]>;
			def int_mips_st_d : GCCBuiltin<"__builtin_msa_st_d">,
			Intrinsic<[], [llvm_v2i64_ty, llvm_ptr_ty, llvm_i32_ty],
			[IntrReadWriteArgMem]>;
			def int_mips_subs_s_b : GCCBuiltin<"__builtin_msa_subs_s_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_subs_s_h : GCCBuiltin<"__builtin_msa_subs_s_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_subs_s_w : GCCBuiltin<"__builtin_msa_subs_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_subs_s_d : GCCBuiltin<"__builtin_msa_subs_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_subs_u_b : GCCBuiltin<"__builtin_msa_subs_u_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_subs_u_h : GCCBuiltin<"__builtin_msa_subs_u_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_subs_u_w : GCCBuiltin<"__builtin_msa_subs_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_subs_u_d : GCCBuiltin<"__builtin_msa_subs_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_subsus_u_b : GCCBuiltin<"__builtin_msa_subsus_u_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_subsus_u_h : GCCBuiltin<"__builtin_msa_subsus_u_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_subsus_u_w : GCCBuiltin<"__builtin_msa_subsus_u_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_subsus_u_d : GCCBuiltin<"__builtin_msa_subsus_u_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_subsuu_s_b : GCCBuiltin<"__builtin_msa_subsuu_s_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_subsuu_s_h : GCCBuiltin<"__builtin_msa_subsuu_s_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_subsuu_s_w : GCCBuiltin<"__builtin_msa_subsuu_s_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_subsuu_s_d : GCCBuiltin<"__builtin_msa_subsuu_s_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_subv_b : GCCBuiltin<"__builtin_msa_subv_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_subv_h : GCCBuiltin<"__builtin_msa_subv_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty], [IntrNoMem]>;
			def int_mips_subv_w : GCCBuiltin<"__builtin_msa_subv_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
			def int_mips_subv_d : GCCBuiltin<"__builtin_msa_subv_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty], [IntrNoMem]>;
			def int_mips_subvi_b : GCCBuiltin<"__builtin_msa_subvi_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_subvi_h : GCCBuiltin<"__builtin_msa_subvi_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_subvi_w : GCCBuiltin<"__builtin_msa_subvi_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_subvi_d : GCCBuiltin<"__builtin_msa_subvi_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_mips_vshf_b : GCCBuiltin<"__builtin_msa_vshf_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
			[IntrNoMem]>;
			def int_mips_vshf_h : GCCBuiltin<"__builtin_msa_vshf_h">,
			Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
			[IntrNoMem]>;
			def int_mips_vshf_w : GCCBuiltin<"__builtin_msa_vshf_w">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
			[IntrNoMem]>;
			def int_mips_vshf_d : GCCBuiltin<"__builtin_msa_vshf_d">,
			Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty],
			[IntrNoMem]>;
			def int_mips_xor_v : GCCBuiltin<"__builtin_msa_xor_v">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
			def int_mips_xori_b : GCCBuiltin<"__builtin_msa_xori_b">,
			Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>;
	}		}
End of changes. 1 change blocks.
	0 lines changed or deleted		1370 lines changed or added

	IntrinsicsNVVM.td		IntrinsicsNVVM.td
	skipping to change at line 861		skipping to change at line 861
	// Used in nvvm internally to help address space opt and ptx code generatio n		// Used in nvvm internally to help address space opt and ptx code generatio n
	// This is for params that are passed to kernel functions by pointer by-val .		// This is for params that are passed to kernel functions by pointer by-val .
	def int_nvvm_ptr_gen_to_param: Intrinsic<[llvm_anyptr_ty],		def int_nvvm_ptr_gen_to_param: Intrinsic<[llvm_anyptr_ty],
	[llvm_anyptr_ty],		[llvm_anyptr_ty],
	[IntrNoMem],		[IntrNoMem],
	"llvm.nvvm.ptr.gen.to.param">;		"llvm.nvvm.ptr.gen.to.param">;
	// Move intrinsics, used in nvvm internally		// Move intrinsics, used in nvvm internally
	def int_nvvm_move_i8 : Intrinsic<[llvm_i8_ty], [llvm_i8_ty], [IntrNoMem],
	"llvm.nvvm.move.i8">;
	def int_nvvm_move_i16 : Intrinsic<[llvm_i16_ty], [llvm_i16_ty], [IntrNoMem] ,		def int_nvvm_move_i16 : Intrinsic<[llvm_i16_ty], [llvm_i16_ty], [IntrNoMem] ,
	"llvm.nvvm.move.i16">;		"llvm.nvvm.move.i16">;
	def int_nvvm_move_i32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem] ,		def int_nvvm_move_i32 : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem] ,
	"llvm.nvvm.move.i32">;		"llvm.nvvm.move.i32">;
	def int_nvvm_move_i64 : Intrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem] ,		def int_nvvm_move_i64 : Intrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem] ,
	"llvm.nvvm.move.i64">;		"llvm.nvvm.move.i64">;
	def int_nvvm_move_float : Intrinsic<[llvm_float_ty], [llvm_float_ty],		def int_nvvm_move_float : Intrinsic<[llvm_float_ty], [llvm_float_ty],
	[IntrNoMem], "llvm.nvvm.move.float">;		[IntrNoMem], "llvm.nvvm.move.float">;
	def int_nvvm_move_double : Intrinsic<[llvm_double_ty], [llvm_double_ty],		def int_nvvm_move_double : Intrinsic<[llvm_double_ty], [llvm_double_ty],
	[IntrNoMem], "llvm.nvvm.move.double">;		[IntrNoMem], "llvm.nvvm.move.double">;
End of changes. 1 change blocks.
	2 lines changed or deleted		0 lines changed or added

	IntrinsicsPowerPC.td		IntrinsicsPowerPC.td
	skipping to change at line 33		skipping to change at line 33
	def int_ppc_dcbi : Intrinsic<[], [llvm_ptr_ty], []>;		def int_ppc_dcbi : Intrinsic<[], [llvm_ptr_ty], []>;
	def int_ppc_dcbst : Intrinsic<[], [llvm_ptr_ty], []>;		def int_ppc_dcbst : Intrinsic<[], [llvm_ptr_ty], []>;
	def int_ppc_dcbt : Intrinsic<[], [llvm_ptr_ty],		def int_ppc_dcbt : Intrinsic<[], [llvm_ptr_ty],
	[IntrReadWriteArgMem, NoCapture<0>]>;		[IntrReadWriteArgMem, NoCapture<0>]>;
	def int_ppc_dcbtst: Intrinsic<[], [llvm_ptr_ty], []>;		def int_ppc_dcbtst: Intrinsic<[], [llvm_ptr_ty], []>;
	def int_ppc_dcbz : Intrinsic<[], [llvm_ptr_ty], []>;		def int_ppc_dcbz : Intrinsic<[], [llvm_ptr_ty], []>;
	def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>;		def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>;
	// sync instruction		// sync instruction
	def int_ppc_sync : Intrinsic<[], [], []>;		def int_ppc_sync : Intrinsic<[], [], []>;
			// Intrinsics used to generate ctr-based loops. These should only be
			// generated by the PowerPC backend!
			def int_ppc_mtctr : Intrinsic<[], [llvm_anyint_ty], []>;
			def int_ppc_is_decremented_ctr_nonzero : Intrinsic<[llvm_i1_ty], [], []>;
	}		}
	let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc." .		let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc." .
	/// PowerPC_Vec_Intrinsic - Base class for all altivec intrinsics.		/// PowerPC_Vec_Intrinsic - Base class for all altivec intrinsics.
	class PowerPC_Vec_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types ,		class PowerPC_Vec_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types ,
	list<LLVMType> param_types,		list<LLVMType> param_types,
	list<IntrinsicProperty> properties>		list<IntrinsicProperty> properties>
	: GCCBuiltin<!strconcat("__builtin_altivec_", GCCIntSuffix)>,		: GCCBuiltin<!strconcat("__builtin_altivec_", GCCIntSuffix)>,
	Intrinsic<ret_types, param_types, properties>;		Intrinsic<ret_types, param_types, properties>;
	}		}
End of changes. 1 change blocks.
	0 lines changed or deleted		5 lines changed or added

	IntrinsicsX86.td		IntrinsicsX86.td
	skipping to change at line 208		skipping to change at line 208
	def int_x86_sse_cvttss2si : GCCBuiltin<"__builtin_ia32_cvttss2si">,		def int_x86_sse_cvttss2si : GCCBuiltin<"__builtin_ia32_cvttss2si">,
	Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty], [IntrNoMem]>;		Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
	def int_x86_sse_cvttss2si64 : GCCBuiltin<"__builtin_ia32_cvttss2si64">,		def int_x86_sse_cvttss2si64 : GCCBuiltin<"__builtin_ia32_cvttss2si64">,
	Intrinsic<[llvm_i64_ty], [llvm_v4f32_ty], [IntrNoMem]>;		Intrinsic<[llvm_i64_ty], [llvm_v4f32_ty], [IntrNoMem]>;
	def int_x86_sse_cvtsi2ss : GCCBuiltin<"__builtin_ia32_cvtsi2ss">,		def int_x86_sse_cvtsi2ss : GCCBuiltin<"__builtin_ia32_cvtsi2ss">,
	Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,		Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
	llvm_i32_ty], [IntrNoMem]>;		llvm_i32_ty], [IntrNoMem]>;
	def int_x86_sse_cvtsi642ss : GCCBuiltin<"__builtin_ia32_cvtsi642ss">,		def int_x86_sse_cvtsi642ss : GCCBuiltin<"__builtin_ia32_cvtsi642ss">,
	Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,		Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
	llvm_i64_ty], [IntrNoMem]>;		llvm_i64_ty], [IntrNoMem]>;
	def int_x86_sse_cvtps2pi : GCCBuiltin<"__builtin_ia32_cvtps2pi">,		def int_x86_sse_cvtps2pi : GCCBuiltin<"__builtin_ia32_cvtps2pi">,
	Intrinsic<[llvm_x86mmx_ty], [llvm_v4f32_ty], [IntrNoMem]>;		Intrinsic<[llvm_x86mmx_ty], [llvm_v4f32_ty], [IntrNoMem]>;
	def int_x86_sse_cvttps2pi: GCCBuiltin<"__builtin_ia32_cvttps2pi">,		def int_x86_sse_cvttps2pi: GCCBuiltin<"__builtin_ia32_cvttps2pi">,
	Intrinsic<[llvm_x86mmx_ty], [llvm_v4f32_ty], [IntrNoMem]>;		Intrinsic<[llvm_x86mmx_ty], [llvm_v4f32_ty], [IntrNoMem]>;
	def int_x86_sse_cvtpi2ps : GCCBuiltin<"__builtin_ia32_cvtpi2ps">,		def int_x86_sse_cvtpi2ps : GCCBuiltin<"__builtin_ia32_cvtpi2ps">,
	Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,		Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
	llvm_x86mmx_ty], [IntrNoMem]>;		llvm_x86mmx_ty], [IntrNoMem]>;
	}		}
	// SIMD store ops		// SIMD store ops
	skipping to change at line 938		skipping to change at line 939
	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
	def int_x86_sse42_crc32_32_8 : GCCBuiltin<"__builtin_ia32_crc32qi"> ,		def int_x86_sse42_crc32_32_8 : GCCBuiltin<"__builtin_ia32_crc32qi"> ,
	Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i8_ty],		Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i8_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_sse42_crc32_32_16 : GCCBuiltin<"__builtin_ia32_crc32hi"> ,		def int_x86_sse42_crc32_32_16 : GCCBuiltin<"__builtin_ia32_crc32hi"> ,
	Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i16_ty],		Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i16_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_sse42_crc32_32_32 : GCCBuiltin<"__builtin_ia32_crc32si"> ,		def int_x86_sse42_crc32_32_32 : GCCBuiltin<"__builtin_ia32_crc32si"> ,
	Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],		Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_sse42_crc32_64_8 :
	Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i8_ty],
	[IntrNoMem]>;
	def int_x86_sse42_crc32_64_64 : GCCBuiltin<"__builtin_ia32_crc32di"> ,		def int_x86_sse42_crc32_64_64 : GCCBuiltin<"__builtin_ia32_crc32di"> ,
	Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],		Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	}		}
	// String/text processing ops.		// String/text processing ops.
	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
	def int_x86_sse42_pcmpistrm128 : GCCBuiltin<"__builtin_ia32_pcmpistrm128 ">,		def int_x86_sse42_pcmpistrm128 : GCCBuiltin<"__builtin_ia32_pcmpistrm128 ">,
	Intrinsic<[llvm_v16i8_ty],		Intrinsic<[llvm_v16i8_ty],
	[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty],		[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i8_ty],
	skipping to change at line 1637		skipping to change at line 1635
	def int_x86_avx2_vbroadcast_ss_ps :		def int_x86_avx2_vbroadcast_ss_ps :
	GCCBuiltin<"__builtin_ia32_vbroadcastss_ps">,		GCCBuiltin<"__builtin_ia32_vbroadcastss_ps">,
	Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;		Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
	def int_x86_avx2_vbroadcast_sd_pd_256 :		def int_x86_avx2_vbroadcast_sd_pd_256 :
	GCCBuiltin<"__builtin_ia32_vbroadcastsd_pd256">,		GCCBuiltin<"__builtin_ia32_vbroadcastsd_pd256">,
	Intrinsic<[llvm_v4f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;		Intrinsic<[llvm_v4f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
	def int_x86_avx2_vbroadcast_ss_ps_256 :		def int_x86_avx2_vbroadcast_ss_ps_256 :
	GCCBuiltin<"__builtin_ia32_vbroadcastss_ps256">,		GCCBuiltin<"__builtin_ia32_vbroadcastss_ps256">,
	Intrinsic<[llvm_v8f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;		Intrinsic<[llvm_v8f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
	def int_x86_avx2_vbroadcasti128 :		def int_x86_avx2_vbroadcasti128 :
	GCCBuiltin<"__builtin_ia32_vbroadcastsi256">,
	Intrinsic<[llvm_v4i64_ty], [llvm_ptr_ty], [IntrReadArgMem]>;		Intrinsic<[llvm_v4i64_ty], [llvm_ptr_ty], [IntrReadArgMem]>;
	def int_x86_avx2_pbroadcastb_128 :		def int_x86_avx2_pbroadcastb_128 :
	GCCBuiltin<"__builtin_ia32_pbroadcastb128">,		GCCBuiltin<"__builtin_ia32_pbroadcastb128">,
	Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;		Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
	def int_x86_avx2_pbroadcastb_256 :		def int_x86_avx2_pbroadcastb_256 :
	GCCBuiltin<"__builtin_ia32_pbroadcastb256">,		GCCBuiltin<"__builtin_ia32_pbroadcastb256">,
	Intrinsic<[llvm_v32i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;		Intrinsic<[llvm_v32i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
	def int_x86_avx2_pbroadcastw_128 :		def int_x86_avx2_pbroadcastw_128 :
	GCCBuiltin<"__builtin_ia32_pbroadcastw128">,		GCCBuiltin<"__builtin_ia32_pbroadcastw128">,
	Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty], [IntrNoMem]>;		Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty], [IntrNoMem]>;
	skipping to change at line 1869		skipping to change at line 1866
	[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],		[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_fma_vfmadd_ps_256 : GCCBuiltin<"__builtin_ia32_vfmaddps256">,		def int_x86_fma_vfmadd_ps_256 : GCCBuiltin<"__builtin_ia32_vfmaddps256">,
	Intrinsic<[llvm_v8f32_ty],		Intrinsic<[llvm_v8f32_ty],
	[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],		[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_fma_vfmadd_pd_256 : GCCBuiltin<"__builtin_ia32_vfmaddpd256">,		def int_x86_fma_vfmadd_pd_256 : GCCBuiltin<"__builtin_ia32_vfmaddpd256">,
	Intrinsic<[llvm_v4f64_ty],		Intrinsic<[llvm_v4f64_ty],
	[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],		[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
			def int_x86_fma_vfmadd_ps_512 : GCCBuiltin<"__builtin_ia32_vfmaddps512">,
			Intrinsic<[llvm_v16f32_ty],
			[llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty],
			[IntrNoMem]>;
			def int_x86_fma_vfmadd_pd_512 : GCCBuiltin<"__builtin_ia32_vfmaddpd512">,
			Intrinsic<[llvm_v8f64_ty],
			[llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty],
			[IntrNoMem]>;
	def int_x86_fma_vfmsub_ss : GCCBuiltin<"__builtin_ia32_vfmsubss">,		def int_x86_fma_vfmsub_ss : GCCBuiltin<"__builtin_ia32_vfmsubss">,
	Intrinsic<[llvm_v4f32_ty],		Intrinsic<[llvm_v4f32_ty],
	[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],		[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_fma_vfmsub_sd : GCCBuiltin<"__builtin_ia32_vfmsubsd">,		def int_x86_fma_vfmsub_sd : GCCBuiltin<"__builtin_ia32_vfmsubsd">,
	Intrinsic<[llvm_v2f64_ty],		Intrinsic<[llvm_v2f64_ty],
	[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],		[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_fma_vfmsub_ps : GCCBuiltin<"__builtin_ia32_vfmsubps">,		def int_x86_fma_vfmsub_ps : GCCBuiltin<"__builtin_ia32_vfmsubps">,
	Intrinsic<[llvm_v4f32_ty],		Intrinsic<[llvm_v4f32_ty],
	skipping to change at line 1893		skipping to change at line 1898
	[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],		[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_fma_vfmsub_ps_256 : GCCBuiltin<"__builtin_ia32_vfmsubps256">,		def int_x86_fma_vfmsub_ps_256 : GCCBuiltin<"__builtin_ia32_vfmsubps256">,
	Intrinsic<[llvm_v8f32_ty],		Intrinsic<[llvm_v8f32_ty],
	[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],		[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_fma_vfmsub_pd_256 : GCCBuiltin<"__builtin_ia32_vfmsubpd256">,		def int_x86_fma_vfmsub_pd_256 : GCCBuiltin<"__builtin_ia32_vfmsubpd256">,
	Intrinsic<[llvm_v4f64_ty],		Intrinsic<[llvm_v4f64_ty],
	[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],		[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
			def int_x86_fma_vfmsub_ps_512 : GCCBuiltin<"__builtin_ia32_vfmsubps512">,
			Intrinsic<[llvm_v16f32_ty],
			[llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty],
			[IntrNoMem]>;
			def int_x86_fma_vfmsub_pd_512 : GCCBuiltin<"__builtin_ia32_vfmsubpd512">,
			Intrinsic<[llvm_v8f64_ty],
			[llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty],
			[IntrNoMem]>;
	def int_x86_fma_vfnmadd_ss : GCCBuiltin<"__builtin_ia32_vfnmaddss">,		def int_x86_fma_vfnmadd_ss : GCCBuiltin<"__builtin_ia32_vfnmaddss">,
	Intrinsic<[llvm_v4f32_ty],		Intrinsic<[llvm_v4f32_ty],
	[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],		[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_fma_vfnmadd_sd : GCCBuiltin<"__builtin_ia32_vfnmaddsd">,		def int_x86_fma_vfnmadd_sd : GCCBuiltin<"__builtin_ia32_vfnmaddsd">,
	Intrinsic<[llvm_v2f64_ty],		Intrinsic<[llvm_v2f64_ty],
	[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],		[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_fma_vfnmadd_ps : GCCBuiltin<"__builtin_ia32_vfnmaddps">,		def int_x86_fma_vfnmadd_ps : GCCBuiltin<"__builtin_ia32_vfnmaddps">,
	Intrinsic<[llvm_v4f32_ty],		Intrinsic<[llvm_v4f32_ty],
	skipping to change at line 1917		skipping to change at line 1930
	[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],		[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_fma_vfnmadd_ps_256 : GCCBuiltin<"__builtin_ia32_vfnmaddps256" >,		def int_x86_fma_vfnmadd_ps_256 : GCCBuiltin<"__builtin_ia32_vfnmaddps256" >,
	Intrinsic<[llvm_v8f32_ty],		Intrinsic<[llvm_v8f32_ty],
	[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],		[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_fma_vfnmadd_pd_256 : GCCBuiltin<"__builtin_ia32_vfnmaddpd256" >,		def int_x86_fma_vfnmadd_pd_256 : GCCBuiltin<"__builtin_ia32_vfnmaddpd256" >,
	Intrinsic<[llvm_v4f64_ty],		Intrinsic<[llvm_v4f64_ty],
	[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],		[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
			def int_x86_fma_vfnmadd_ps_512 : GCCBuiltin<"__builtin_ia32_vfnmaddps512"
			>,
			Intrinsic<[llvm_v16f32_ty],
			[llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty],
			[IntrNoMem]>;
			def int_x86_fma_vfnmadd_pd_512 : GCCBuiltin<"__builtin_ia32_vfnmaddpd512"
			>,
			Intrinsic<[llvm_v8f64_ty],
			[llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty],
			[IntrNoMem]>;
	def int_x86_fma_vfnmsub_ss : GCCBuiltin<"__builtin_ia32_vfnmsubss">,		def int_x86_fma_vfnmsub_ss : GCCBuiltin<"__builtin_ia32_vfnmsubss">,
	Intrinsic<[llvm_v4f32_ty],		Intrinsic<[llvm_v4f32_ty],
	[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],		[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_fma_vfnmsub_sd : GCCBuiltin<"__builtin_ia32_vfnmsubsd">,		def int_x86_fma_vfnmsub_sd : GCCBuiltin<"__builtin_ia32_vfnmsubsd">,
	Intrinsic<[llvm_v2f64_ty],		Intrinsic<[llvm_v2f64_ty],
	[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],		[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_fma_vfnmsub_ps : GCCBuiltin<"__builtin_ia32_vfnmsubps">,		def int_x86_fma_vfnmsub_ps : GCCBuiltin<"__builtin_ia32_vfnmsubps">,
	Intrinsic<[llvm_v4f32_ty],		Intrinsic<[llvm_v4f32_ty],
	skipping to change at line 1941		skipping to change at line 1962
	[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],		[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_fma_vfnmsub_ps_256 : GCCBuiltin<"__builtin_ia32_vfnmsubps256" >,		def int_x86_fma_vfnmsub_ps_256 : GCCBuiltin<"__builtin_ia32_vfnmsubps256" >,
	Intrinsic<[llvm_v8f32_ty],		Intrinsic<[llvm_v8f32_ty],
	[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],		[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_fma_vfnmsub_pd_256 : GCCBuiltin<"__builtin_ia32_vfnmsubpd256" >,		def int_x86_fma_vfnmsub_pd_256 : GCCBuiltin<"__builtin_ia32_vfnmsubpd256" >,
	Intrinsic<[llvm_v4f64_ty],		Intrinsic<[llvm_v4f64_ty],
	[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],		[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
			def int_x86_fma_vfnmsub_ps_512 : GCCBuiltin<"__builtin_ia32_vfnmsubps512"
			>,
			Intrinsic<[llvm_v16f32_ty],
			[llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty],
			[IntrNoMem]>;
			def int_x86_fma_vfnmsub_pd_512 : GCCBuiltin<"__builtin_ia32_vfnmsubpd512"
			>,
			Intrinsic<[llvm_v8f64_ty],
			[llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty],
			[IntrNoMem]>;
	def int_x86_fma_vfmaddsub_ps : GCCBuiltin<"__builtin_ia32_vfmaddsubps">,		def int_x86_fma_vfmaddsub_ps : GCCBuiltin<"__builtin_ia32_vfmaddsubps">,
	Intrinsic<[llvm_v4f32_ty],		Intrinsic<[llvm_v4f32_ty],
	[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],		[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_fma_vfmaddsub_pd : GCCBuiltin<"__builtin_ia32_vfmaddsubpd">,		def int_x86_fma_vfmaddsub_pd : GCCBuiltin<"__builtin_ia32_vfmaddsubpd">,
	Intrinsic<[llvm_v2f64_ty],		Intrinsic<[llvm_v2f64_ty],
	[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],		[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_fma_vfmaddsub_ps_256 :		def int_x86_fma_vfmaddsub_ps_256 :
	GCCBuiltin<"__builtin_ia32_vfmaddsubps256">,		GCCBuiltin<"__builtin_ia32_vfmaddsubps256">,
	Intrinsic<[llvm_v8f32_ty],		Intrinsic<[llvm_v8f32_ty],
	[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],		[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_fma_vfmaddsub_pd_256 :		def int_x86_fma_vfmaddsub_pd_256 :
	GCCBuiltin<"__builtin_ia32_vfmaddsubpd256">,		GCCBuiltin<"__builtin_ia32_vfmaddsubpd256">,
	Intrinsic<[llvm_v4f64_ty],		Intrinsic<[llvm_v4f64_ty],
	[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],		[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
			def int_x86_fma_vfmaddsub_ps_512 : GCCBuiltin<"__builtin_ia32_vfmaddsubps
			512">,
			Intrinsic<[llvm_v16f32_ty],
			[llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty],
			[IntrNoMem]>;
			def int_x86_fma_vfmaddsub_pd_512 : GCCBuiltin<"__builtin_ia32_vfmaddsubpd
			512">,
			Intrinsic<[llvm_v8f64_ty],
			[llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty],
			[IntrNoMem]>;
	def int_x86_fma_vfmsubadd_ps : GCCBuiltin<"__builtin_ia32_vfmsubaddps">,		def int_x86_fma_vfmsubadd_ps : GCCBuiltin<"__builtin_ia32_vfmsubaddps">,
	Intrinsic<[llvm_v4f32_ty],		Intrinsic<[llvm_v4f32_ty],
	[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],		[llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_fma_vfmsubadd_pd : GCCBuiltin<"__builtin_ia32_vfmsubaddpd">,		def int_x86_fma_vfmsubadd_pd : GCCBuiltin<"__builtin_ia32_vfmsubaddpd">,
	Intrinsic<[llvm_v2f64_ty],		Intrinsic<[llvm_v2f64_ty],
	[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],		[llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_fma_vfmsubadd_ps_256 :		def int_x86_fma_vfmsubadd_ps_256 :
	GCCBuiltin<"__builtin_ia32_vfmsubaddps256">,		GCCBuiltin<"__builtin_ia32_vfmsubaddps256">,
	Intrinsic<[llvm_v8f32_ty],		Intrinsic<[llvm_v8f32_ty],
	[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],		[llvm_v8f32_ty, llvm_v8f32_ty, llvm_v8f32_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_fma_vfmsubadd_pd_256 :		def int_x86_fma_vfmsubadd_pd_256 :
	GCCBuiltin<"__builtin_ia32_vfmsubaddpd256">,		GCCBuiltin<"__builtin_ia32_vfmsubaddpd256">,
	Intrinsic<[llvm_v4f64_ty],		Intrinsic<[llvm_v4f64_ty],
	[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],		[llvm_v4f64_ty, llvm_v4f64_ty, llvm_v4f64_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
			def int_x86_fma_vfmsubadd_ps_512 : GCCBuiltin<"__builtin_ia32_vfmsubaddps
			512">,
			Intrinsic<[llvm_v16f32_ty],
			[llvm_v16f32_ty, llvm_v16f32_ty, llvm_v16f32_ty],
			[IntrNoMem]>;
			def int_x86_fma_vfmsubadd_pd_512 : GCCBuiltin<"__builtin_ia32_vfmsubaddpd
			512">,
			Intrinsic<[llvm_v8f64_ty],
			[llvm_v8f64_ty, llvm_v8f64_ty, llvm_v8f64_ty],
			[IntrNoMem]>;
	}		}
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// XOP		// XOP
	def int_x86_xop_vpermil2pd : GCCBuiltin<"__builtin_ia32_vpermil2pd">,		def int_x86_xop_vpermil2pd : GCCBuiltin<"__builtin_ia32_vpermil2pd">,
	Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty,		Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty,
	llvm_v2f64_ty, llvm_i8_ty],		llvm_v2f64_ty, llvm_i8_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	skipping to change at line 2552		skipping to change at line 2597
	Intrinsic<[llvm_v8f32_ty], [llvm_v8i16_ty], [IntrNoMem]>;		Intrinsic<[llvm_v8f32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
	def int_x86_vcvtps2ph_128 : GCCBuiltin<"__builtin_ia32_vcvtps2ph">,		def int_x86_vcvtps2ph_128 : GCCBuiltin<"__builtin_ia32_vcvtps2ph">,
	Intrinsic<[llvm_v8i16_ty], [llvm_v4f32_ty, llvm_i32_ty],		Intrinsic<[llvm_v8i16_ty], [llvm_v4f32_ty, llvm_i32_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_x86_vcvtps2ph_256 : GCCBuiltin<"__builtin_ia32_vcvtps2ph256">,		def int_x86_vcvtps2ph_256 : GCCBuiltin<"__builtin_ia32_vcvtps2ph256">,
	Intrinsic<[llvm_v8i16_ty], [llvm_v8f32_ty, llvm_i32_ty],		Intrinsic<[llvm_v8i16_ty], [llvm_v8f32_ty, llvm_i32_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	}		}
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
			// TBM
			let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
			def int_x86_tbm_bextri_u32 : GCCBuiltin<"__builtin_ia32_bextri_u32">,
			Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
			def int_x86_tbm_bextri_u64 : GCCBuiltin<"__builtin_ia32_bextri_u64">,
			Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
			}
			//===----------------------------------------------------------------------
			===//
	// RDRAND intrinsics - Return a random value and whether it is valid.		// RDRAND intrinsics - Return a random value and whether it is valid.
	// RDSEED intrinsics - Return a NIST SP800-90B & C compliant random value a nd		// RDSEED intrinsics - Return a NIST SP800-90B & C compliant random value a nd
	// whether it is valid.		// whether it is valid.
	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
	// These are declared side-effecting so they don't get eliminated by CSE or		// These are declared side-effecting so they don't get eliminated by CSE or
	// LICM.		// LICM.
	def int_x86_rdrand_16 : Intrinsic<[llvm_i16_ty, llvm_i32_ty], [], []>;		def int_x86_rdrand_16 : Intrinsic<[llvm_i16_ty, llvm_i32_ty], [], []>;
	def int_x86_rdrand_32 : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [], []>;		def int_x86_rdrand_32 : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [], []>;
	def int_x86_rdrand_64 : Intrinsic<[llvm_i64_ty, llvm_i32_ty], [], []>;		def int_x86_rdrand_64 : Intrinsic<[llvm_i64_ty, llvm_i32_ty], [], []>;
	skipping to change at line 2580		skipping to change at line 2635
	let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".		let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
	def int_x86_xbegin : GCCBuiltin<"__builtin_ia32_xbegin">,		def int_x86_xbegin : GCCBuiltin<"__builtin_ia32_xbegin">,
	Intrinsic<[llvm_i32_ty], [], []>;		Intrinsic<[llvm_i32_ty], [], []>;
	def int_x86_xend : GCCBuiltin<"__builtin_ia32_xend">,		def int_x86_xend : GCCBuiltin<"__builtin_ia32_xend">,
	Intrinsic<[], [], []>;		Intrinsic<[], [], []>;
	def int_x86_xabort : GCCBuiltin<"__builtin_ia32_xabort">,		def int_x86_xabort : GCCBuiltin<"__builtin_ia32_xabort">,
	Intrinsic<[], [llvm_i8_ty], [IntrNoReturn]>;		Intrinsic<[], [llvm_i8_ty], [IntrNoReturn]>;
	def int_x86_xtest : GCCBuiltin<"__builtin_ia32_xtest">,		def int_x86_xtest : GCCBuiltin<"__builtin_ia32_xtest">,
	Intrinsic<[llvm_i32_ty], [], []>;		Intrinsic<[llvm_i32_ty], [], []>;
	}		}
			//===----------------------------------------------------------------------
			===//
			// AVX512
			// Mask ops
			let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
			// Mask instructions
			// 16-bit mask
			def int_x86_kadd_v16i1 : GCCBuiltin<"__builtin_ia32_kaddw">,
			Intrinsic<[llvm_v16i1_ty], [llvm_v16i1_ty, llvm_v16i1_ty],
			[IntrNoMem]>;
			def int_x86_kand_v16i1 : GCCBuiltin<"__builtin_ia32_kandw">,
			Intrinsic<[llvm_v16i1_ty], [llvm_v16i1_ty, llvm_v16i1_ty],
			[IntrNoMem]>;
			def int_x86_kandn_v16i1 : GCCBuiltin<"__builtin_ia32_kandnw">,
			Intrinsic<[llvm_v16i1_ty], [llvm_v16i1_ty, llvm_v16i1_ty],
			[IntrNoMem]>;
			def int_x86_knot_v16i1 : GCCBuiltin<"__builtin_ia32_knotw">,
			Intrinsic<[llvm_v16i1_ty], [llvm_v16i1_ty], [IntrNoMem]>;
			def int_x86_kor_v16i1 : GCCBuiltin<"__builtin_ia32_korw">,
			Intrinsic<[llvm_v16i1_ty], [llvm_v16i1_ty, llvm_v16i1_ty],
			[IntrNoMem]>;
			def int_x86_kxor_v16i1 : GCCBuiltin<"__builtin_ia32_kxorw">,
			Intrinsic<[llvm_v16i1_ty], [llvm_v16i1_ty, llvm_v16i1_ty],
			[IntrNoMem]>;
			def int_x86_kxnor_v16i1 : GCCBuiltin<"__builtin_ia32_kxnorw">,
			Intrinsic<[llvm_v16i1_ty], [llvm_v16i1_ty, llvm_v16i1_ty],
			[IntrNoMem]>;
			def int_x86_mask2int_v16i1 : GCCBuiltin<"__builtin_ia32_mask2intw">,
			Intrinsic<[llvm_i32_ty], [llvm_v16i1_ty], [IntrNoMem]>;
			def int_x86_int2mask_v16i1 : GCCBuiltin<"__builtin_ia32_int2maskw">,
			Intrinsic<[llvm_v16i1_ty], [llvm_i32_ty], [IntrNoMem]>;
			def int_x86_kunpck_v16i1 : GCCBuiltin<"__builtin_ia32_kunpckbw">,
			Intrinsic<[llvm_v16i1_ty], [llvm_v8i1_ty, llvm_v8i1_ty],
			[IntrNoMem]>;
			def int_x86_avx512_kortestz : GCCBuiltin<"__builtin_ia32_kortestz">,
			Intrinsic<[llvm_i32_ty], [llvm_i16_ty, llvm_i16_ty],
			[IntrNoMem]>;
			def int_x86_avx512_kortestc : GCCBuiltin<"__builtin_ia32_kortestc">,
			Intrinsic<[llvm_i32_ty], [llvm_i16_ty, llvm_i16_ty],
			[IntrNoMem]>;
			}
			// Conversion ops
			let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
			def int_x86_avx512_cvtss2usi : GCCBuiltin<"__builtin_ia32_cvtss2usi">,
			Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
			def int_x86_avx512_cvtss2usi64 : GCCBuiltin<"__builtin_ia32_cvtss2usi64">
			,
			Intrinsic<[llvm_i64_ty], [llvm_v4f32_ty], [IntrNoMem]>;
			def int_x86_avx512_cvttss2usi : GCCBuiltin<"__builtin_ia32_cvttss2usi">,
			Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
			def int_x86_avx512_cvttss2usi64 : GCCBuiltin<"__builtin_ia32_cvttss2usi64
			">,
			Intrinsic<[llvm_i64_ty], [llvm_v4f32_ty], [IntrNoMem]>;
			def int_x86_avx512_cvtusi2ss : GCCBuiltin<"__builtin_ia32_cvtusi2ss">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
			llvm_i32_ty], [IntrNoMem]>;
			def int_x86_avx512_cvtusi642ss : GCCBuiltin<"__builtin_ia32_cvtusi642ss">
			,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty,
			llvm_i64_ty], [IntrNoMem]>;
			def int_x86_avx512_cvtsd2usi : GCCBuiltin<"__builtin_ia32_cvtsd2usi">,
			Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty], [IntrNoMem]>;
			def int_x86_avx512_cvtsd2usi64 : GCCBuiltin<"__builtin_ia32_cvtsd2usi64">
			,
			Intrinsic<[llvm_i64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
			def int_x86_avx512_cvttsd2usi : GCCBuiltin<"__builtin_ia32_cvttsd2usi">,
			Intrinsic<[llvm_i32_ty], [llvm_v2f64_ty], [IntrNoMem]>;
			def int_x86_avx512_cvttsd2usi64 : GCCBuiltin<"__builtin_ia32_cvttsd2usi64
			">,
			Intrinsic<[llvm_i64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
			def int_x86_avx512_cvtusi2sd : GCCBuiltin<"__builtin_ia32_cvtusi2sd">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
			llvm_i32_ty], [IntrNoMem]>;
			def int_x86_avx512_cvtusi642sd : GCCBuiltin<"__builtin_ia32_cvtusi642sd">
			,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty,
			llvm_i64_ty], [IntrNoMem]>;
			def int_x86_avx512_vcvtph2ps_512 : GCCBuiltin<"__builtin_ia32_vcvtph2ps51
			2">,
			Intrinsic<[llvm_v16f32_ty], [llvm_v16i16_ty], [IntrNoMem]>;
			def int_x86_avx512_vcvtps2ph_512 : GCCBuiltin<"__builtin_ia32_vcvtps2ph51
			2">,
			Intrinsic<[llvm_v16i16_ty], [llvm_v16f32_ty, llvm_i32_ty],
			[IntrNoMem]>;
			}
			// Vector convert
			let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
			def int_x86_avx512_cvt_ps2dq_512 : GCCBuiltin<"__builtin_ia32_cvtps2dq512
			">,
			Intrinsic<[llvm_v16i32_ty], [llvm_v16f32_ty], [IntrNoMem]>;
			def int_x86_avx512_cvtdq2_ps_512 : GCCBuiltin<"__builtin_ia32_cvtdq2ps512
			">,
			Intrinsic<[llvm_v16f32_ty], [llvm_v16i32_ty], [IntrNoMem]>;
			}
			// Vector load with broadcast
			let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
			def int_x86_avx512_vbroadcast_ss_512 :
			GCCBuiltin<"__builtin_ia32_vbroadcastss512">,
			Intrinsic<[llvm_v16f32_ty], [llvm_ptr_ty], [IntrReadArgMem]>;
			def int_x86_avx512_vbroadcast_ss_ps_512 :
			GCCBuiltin<"__builtin_ia32_vbroadcastss_ps512">,
			Intrinsic<[llvm_v16f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;
			def int_x86_avx512_vbroadcast_sd_512 :
			GCCBuiltin<"__builtin_ia32_vbroadcastsd512">,
			Intrinsic<[llvm_v8f64_ty], [llvm_ptr_ty], [IntrReadArgMem]>;
			def int_x86_avx512_vbroadcast_sd_pd_512 :
			GCCBuiltin<"__builtin_ia32_vbroadcastsd_pd512">,
			Intrinsic<[llvm_v8f64_ty], [llvm_v2f64_ty], [IntrNoMem]>;
			def int_x86_avx512_pbroadcastd_512 :
			GCCBuiltin<"__builtin_ia32_pbroadcastd512">,
			Intrinsic<[llvm_v16i32_ty], [llvm_v4i32_ty], [IntrNoMem]>;
			def int_x86_avx512_pbroadcastd_i32_512 :
			Intrinsic<[llvm_v16i32_ty], [llvm_i32_ty], [IntrNoMem]>;
			def int_x86_avx512_pbroadcastq_512 :
			GCCBuiltin<"__builtin_ia32_pbroadcastq512">,
			Intrinsic<[llvm_v8i64_ty], [llvm_v2i64_ty], [IntrNoMem]>;
			def int_x86_avx512_pbroadcastq_i64_512 :
			Intrinsic<[llvm_v8i64_ty], [llvm_i64_ty], [IntrNoMem]>;
			}
			// Vector sign and zero extend
			let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
			def int_x86_avx512_pmovzxbq : GCCBuiltin<"__builtin_ia32_pmovzxbq512">,
			Intrinsic<[llvm_v8i64_ty], [llvm_v16i8_ty],
			[IntrNoMem]>;
			def int_x86_avx512_pmovzxwd : GCCBuiltin<"__builtin_ia32_pmovzxwd512">,
			Intrinsic<[llvm_v16i32_ty], [llvm_v16i16_ty],
			[IntrNoMem]>;
			def int_x86_avx512_pmovzxbd : GCCBuiltin<"__builtin_ia32_pmovzxbd512">,
			Intrinsic<[llvm_v16i32_ty], [llvm_v16i8_ty],
			[IntrNoMem]>;
			def int_x86_avx512_pmovzxwq : GCCBuiltin<"__builtin_ia32_pmovzxwq512">,
			Intrinsic<[llvm_v8i64_ty], [llvm_v8i16_ty],
			[IntrNoMem]>;
			def int_x86_avx512_pmovzxdq : GCCBuiltin<"__builtin_ia32_pmovzxdq512">,
			Intrinsic<[llvm_v8i64_ty], [llvm_v8i32_ty],
			[IntrNoMem]>;
			}
			// Arithmetic ops
			let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
			def int_x86_avx512_min_ps_512 : GCCBuiltin<"__builtin_ia32_minps512">,
			Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty,
			llvm_v16f32_ty], [IntrNoMem]>;
			def int_x86_avx512_min_pd_512 : GCCBuiltin<"__builtin_ia32_minpd512">,
			Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty,
			llvm_v8f64_ty], [IntrNoMem]>;
			def int_x86_avx512_max_ps_512 : GCCBuiltin<"__builtin_ia32_maxps512">,
			Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty,
			llvm_v16f32_ty], [IntrNoMem]>;
			def int_x86_avx512_max_pd_512 : GCCBuiltin<"__builtin_ia32_maxpd512">,
			Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty,
			llvm_v8f64_ty], [IntrNoMem]>;
			def int_x86_avx512_pmaxu_d : GCCBuiltin<"__builtin_ia32_pmaxud512">,
			Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty,
			llvm_v16i32_ty], [IntrNoMem]>;
			def int_x86_avx512_pmaxu_q : GCCBuiltin<"__builtin_ia32_pmaxuq512">,
			Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,
			llvm_v8i64_ty], [IntrNoMem]>;
			def int_x86_avx512_pmaxs_d : GCCBuiltin<"__builtin_ia32_pmaxsd512">,
			Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty,
			llvm_v16i32_ty], [IntrNoMem]>;
			def int_x86_avx512_pmaxs_q : GCCBuiltin<"__builtin_ia32_pmaxsq512">,
			Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,
			llvm_v8i64_ty], [IntrNoMem]>;
			def int_x86_avx512_pminu_d : GCCBuiltin<"__builtin_ia32_pminud512">,
			Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty,
			llvm_v16i32_ty], [IntrNoMem]>;
			def int_x86_avx512_pminu_q : GCCBuiltin<"__builtin_ia32_pminuq512">,
			Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,
			llvm_v8i64_ty], [IntrNoMem]>;
			def int_x86_avx512_pmins_d : GCCBuiltin<"__builtin_ia32_pminsd512">,
			Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty,
			llvm_v16i32_ty], [IntrNoMem]>;
			def int_x86_avx512_pmins_q : GCCBuiltin<"__builtin_ia32_pminsq512">,
			Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,
			llvm_v8i64_ty], [IntrNoMem]>;
			def int_x86_avx512_rndscale_ss : GCCBuiltin<"__builtin_ia32_rndsca
			less">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty,
			llvm_i32_ty], [IntrNoMem]>;
			def int_x86_avx512_rndscale_sd : GCCBuiltin<"__builtin_ia32_rndsca
			lesd">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty,
			llvm_i32_ty], [IntrNoMem]>;
			def int_x86_avx512_sqrt_ss : GCCBuiltin<"__builtin_ia32_sqrtrndss"
			>,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty],
			[IntrNoMem]>;
			def int_x86_avx512_sqrt_sd : GCCBuiltin<"__builtin_ia32_sqrtrndsd"
			>,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty],
			[IntrNoMem]>;
			def int_x86_avx512_rndscale_ps_512 : GCCBuiltin<"__builtin_ia32_rn
			dscaleps512">,
			Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty,
			llvm_i32_ty], [IntrNoMem]>;
			def int_x86_avx512_rndscale_pd_512 : GCCBuiltin<"__builtin_ia32_rn
			dscalepd512">,
			Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty,
			llvm_i32_ty], [IntrNoMem]>;
			def int_x86_avx512_sqrt_pd_512 : GCCBuiltin<"__builtin_ia32_sqrtpd512">,
			Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty], [IntrNoMem]>;
			def int_x86_avx512_sqrt_ps_512 : GCCBuiltin<"__builtin_ia32_sqrtps512">,
			Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty], [IntrNoMem]>;
			def int_x86_avx512_rcp14_ps_512 : GCCBuiltin<"__builtin_ia32_rcp14ps512">
			,
			Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty],
			[IntrNoMem]>;
			def int_x86_avx512_rcp14_pd_512 : GCCBuiltin<"__builtin_ia32_rcp14pd512">
			,
			Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty],
			[IntrNoMem]>;
			def int_x86_avx512_rcp14_ss : GCCBuiltin<"__builtin_ia32_rcp14ss">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty],
			[IntrNoMem]>;
			def int_x86_avx512_rcp14_sd : GCCBuiltin<"__builtin_ia32_rcp14sd">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty],
			[IntrNoMem]>;
			def int_x86_avx512_rsqrt14_ps_512 : GCCBuiltin<"__builtin_ia32_rsqrt14ps5
			12">,
			Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty],
			[IntrNoMem]>;
			def int_x86_avx512_rsqrt14_pd_512 : GCCBuiltin<"__builtin_ia32_rsqrt14pd5
			12">,
			Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty],
			[IntrNoMem]>;
			def int_x86_avx512_rsqrt14_ss : GCCBuiltin<"__builtin_ia32_rsqrt14ss">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty],
			[IntrNoMem]>;
			def int_x86_avx512_rsqrt14_sd : GCCBuiltin<"__builtin_ia32_rsqrt14sd">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty],
			[IntrNoMem]>;
			def int_x86_avx512_rcp28_ps_512 : GCCBuiltin<"__builtin_ia32_rcp28ps512">
			,
			Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty],
			[IntrNoMem]>;
			def int_x86_avx512_rcp28_pd_512 : GCCBuiltin<"__builtin_ia32_rcp28pd512">
			,
			Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty],
			[IntrNoMem]>;
			def int_x86_avx512_rcp28_ss : GCCBuiltin<"__builtin_ia32_rcp28ss">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty],
			[IntrNoMem]>;
			def int_x86_avx512_rcp28_sd : GCCBuiltin<"__builtin_ia32_rcp28sd">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty],
			[IntrNoMem]>;
			def int_x86_avx512_rsqrt28_ps_512 : GCCBuiltin<"__builtin_ia32_rsqrt28ps5
			12">,
			Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty],
			[IntrNoMem]>;
			def int_x86_avx512_rsqrt28_pd_512 : GCCBuiltin<"__builtin_ia32_rsqrt28pd5
			12">,
			Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty],
			[IntrNoMem]>;
			def int_x86_avx512_rsqrt28_ss : GCCBuiltin<"__builtin_ia32_rsqrt28ss">,
			Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty],
			[IntrNoMem]>;
			def int_x86_avx512_rsqrt28_sd : GCCBuiltin<"__builtin_ia32_rsqrt28sd">,
			Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty],
			[IntrNoMem]>;
			}
			// Integer shift ops.
			let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
			def int_x86_avx512_psll_dq : GCCBuiltin<"__builtin_ia32_pslldqi512">,
			Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,
			llvm_i32_ty], [IntrNoMem]>;
			def int_x86_avx512_psrl_dq : GCCBuiltin<"__builtin_ia32_psrldqi512">,
			Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,
			llvm_i32_ty], [IntrNoMem]>;
			def int_x86_avx512_psll_dq_bs : GCCBuiltin<"__builtin_ia32_pslldqi512_byt
			eshift">,
			Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,
			llvm_i32_ty], [IntrNoMem]>;
			def int_x86_avx512_psrl_dq_bs : GCCBuiltin<"__builtin_ia32_psrldqi512_byt
			eshift">,
			Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,
			llvm_i32_ty], [IntrNoMem]>;
			}
			// Gather and Scatter ops
			let TargetPrefix = "x86" in {
			def int_x86_avx512_gather_dpd_mask_512 : GCCBuiltin<"__builtin_ia32_mask
			_gatherdpd512">,
			Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty, llvm_i8_ty,
			llvm_v8i32_ty, llvm_ptr_ty, llvm_i32_ty],
			[IntrReadMem]>;
			def int_x86_avx512_gather_dps_mask_512 : GCCBuiltin<"__builtin_ia32_mask
			_gatherdps512">,
			Intrinsic<[llvm_v16f32_ty], [llvm_v16f32_ty, llvm_i16_ty,
			llvm_v16i32_ty, llvm_ptr_ty, llvm_i32_ty],
			[IntrReadMem]>;
			def int_x86_avx512_gather_qpd_mask_512 : GCCBuiltin<"__builtin_ia32_mask
			_gatherqpd512">,
			Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty, llvm_i8_ty,
			llvm_v8i64_ty, llvm_ptr_ty, llvm_i32_ty],
			[IntrReadMem]>;
			def int_x86_avx512_gather_qps_mask_512 : GCCBuiltin<"__builtin_ia32_mask
			_gatherqps512">,
			Intrinsic<[llvm_v8f32_ty], [llvm_v8f32_ty, llvm_i8_ty,
			llvm_v8i64_ty, llvm_ptr_ty, llvm_i32_ty],
			[IntrReadMem]>;
			def int_x86_avx512_gather_dpd_512 : GCCBuiltin<"__builtin_ia32_gatherdpd
			512">,
			Intrinsic<[llvm_v8f64_ty], [llvm_v8i32_ty, llvm_ptr_ty,
			llvm_i32_ty],
			[IntrReadMem]>;
			def int_x86_avx512_gather_dps_512 : GCCBuiltin<"__builtin_ia32_gatherdps
			512">,
			Intrinsic<[llvm_v16f32_ty], [llvm_v16i32_ty, llvm_ptr_ty,
			llvm_i32_ty],
			[IntrReadMem]>;
			def int_x86_avx512_gather_qpd_512 : GCCBuiltin<"__builtin_ia32_gatherqpd
			512">,
			Intrinsic<[llvm_v8f64_ty], [llvm_v8i64_ty, llvm_ptr_ty,
			llvm_i32_ty],
			[IntrReadArgMem]>;
			def int_x86_avx512_gather_qps_512 : GCCBuiltin<"__builtin_ia32_gatherqps
			512">,
			Intrinsic<[llvm_v8f32_ty], [llvm_v8i64_ty, llvm_ptr_ty,
			llvm_i32_ty],
			[IntrReadMem]>;
			def int_x86_avx512_gather_dpq_mask_512 : GCCBuiltin<"__builtin_ia32_mask
			_gatherdpq512">,
			Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, llvm_i8_ty,
			llvm_v8i32_ty, llvm_ptr_ty, llvm_i32_ty],
			[IntrReadMem]>;
			def int_x86_avx512_gather_dpi_mask_512 : GCCBuiltin<"__builtin_ia32_mask
			_gatherdpi512">,
			Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty, llvm_i16_ty,
			llvm_v16i32_ty, llvm_ptr_ty, llvm_i32_ty],
			[IntrReadArgMem]>;
			def int_x86_avx512_gather_qpq_mask_512 : GCCBuiltin<"__builtin_ia32_mask
			_gatherqpq512">,
			Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, llvm_i8_ty,
			llvm_v8i64_ty, llvm_ptr_ty, llvm_i32_ty],
			[IntrReadArgMem]>;
			def int_x86_avx512_gather_qpi_mask_512 : GCCBuiltin<"__builtin_ia32_mask
			_gatherqpi512">,
			Intrinsic<[llvm_v8i32_ty], [llvm_v8i32_ty, llvm_i8_ty,
			llvm_v8i64_ty, llvm_ptr_ty, llvm_i32_ty],
			[IntrReadMem]>;
			def int_x86_avx512_gather_dpq_512 : GCCBuiltin<"__builtin_ia32_gatherdpq
			512">,
			Intrinsic<[llvm_v8i64_ty], [llvm_v8i32_ty, llvm_ptr_ty,
			llvm_i32_ty],
			[IntrReadArgMem]>;
			def int_x86_avx512_gather_dpi_512 : GCCBuiltin<"__builtin_ia32_gatherdpi
			512">,
			Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty, llvm_ptr_ty,
			llvm_i32_ty],
			[IntrReadArgMem]>;
			def int_x86_avx512_gather_qpq_512 : GCCBuiltin<"__builtin_ia32_gatherqpq
			512">,
			Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty, llvm_ptr_ty,
			llvm_i32_ty],
			[IntrReadArgMem]>;
			def int_x86_avx512_gather_qpi_512 : GCCBuiltin<"__builtin_ia32_gatherqpi
			512">,
			Intrinsic<[llvm_v8i32_ty], [llvm_v8i64_ty, llvm_ptr_ty,
			llvm_i32_ty],
			[IntrReadArgMem]>;
			// scatter
			def int_x86_avx512_scatter_dpd_mask_512 : GCCBuiltin<"__builtin_ia32_mas
			k_scatterdpd512">,
			Intrinsic<[], [llvm_ptr_ty, llvm_i8_ty,
			llvm_v8i32_ty, llvm_v8f64_ty, llvm_i32_ty],
			[IntrReadWriteArgMem]>;
			def int_x86_avx512_scatter_dps_mask_512 : GCCBuiltin<"__builtin_ia32_mas
			k_scatterdps512">,
			Intrinsic<[], [llvm_ptr_ty, llvm_i16_ty,
			llvm_v16i32_ty, llvm_v16f32_ty, llvm_i32_ty],
			[IntrReadWriteArgMem]>;
			def int_x86_avx512_scatter_qpd_mask_512 : GCCBuiltin<"__builtin_ia32_mas
			k_scatterqpd512">,
			Intrinsic<[], [llvm_ptr_ty, llvm_i8_ty,
			llvm_v8i64_ty, llvm_v8f64_ty, llvm_i32_ty],
			[IntrReadWriteArgMem]>;
			def int_x86_avx512_scatter_qps_mask_512 : GCCBuiltin<"__builtin_ia32_mas
			k_scatterqps512">,
			Intrinsic<[], [llvm_ptr_ty, llvm_i8_ty,
			llvm_v8i64_ty, llvm_v8f32_ty, llvm_i32_ty],
			[IntrReadWriteArgMem]>;
			def int_x86_avx512_scatter_dpd_512 : GCCBuiltin<"__builtin_ia32_scatterd
			pd512">,
			Intrinsic<[], [llvm_ptr_ty, llvm_v8i32_ty, llvm_v8f64_ty,
			llvm_i32_ty],
			[IntrReadWriteArgMem]>;
			def int_x86_avx512_scatter_dps_512 : GCCBuiltin<"__builtin_ia32_scatterd
			ps512">,
			Intrinsic<[], [llvm_ptr_ty, llvm_v16i32_ty, llvm_v16f32_ty,
			llvm_i32_ty],
			[IntrReadWriteArgMem]>;
			def int_x86_avx512_scatter_qpd_512 : GCCBuiltin<"__builtin_ia32_scatterq
			pd512">,
			Intrinsic<[], [llvm_ptr_ty, llvm_v8i64_ty, llvm_v8f64_ty,
			llvm_i32_ty],
			[IntrReadWriteArgMem]>;
			def int_x86_avx512_scatter_qps_512 : GCCBuiltin<"__builtin_ia32_scatterq
			ps512">,
			Intrinsic<[], [llvm_ptr_ty, llvm_v8i64_ty, llvm_v8f32_ty,
			llvm_i32_ty],
			[IntrReadWriteArgMem]>;
			def int_x86_avx512_scatter_dpq_mask_512 : GCCBuiltin<"__builtin_ia32_mas
			k_scatterdpq512">,
			Intrinsic<[], [llvm_ptr_ty, llvm_i8_ty, llvm_v8i32_ty,
			llvm_v8i64_ty, llvm_i32_ty],
			[IntrReadWriteArgMem]>;
			def int_x86_avx512_scatter_dpi_mask_512 : GCCBuiltin<"__builtin_ia32_mas
			k_scatterdpi512">,
			Intrinsic<[], [llvm_ptr_ty, llvm_i16_ty,
			llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty],
			[IntrReadWriteArgMem]>;
			def int_x86_avx512_scatter_qpq_mask_512 : GCCBuiltin<"__builtin_ia32_mas
			k_scatterqpq512">,
			Intrinsic<[], [llvm_ptr_ty, llvm_i8_ty,
			llvm_v8i64_ty, llvm_v8i64_ty, llvm_i32_ty],
			[IntrReadWriteArgMem]>;
			def int_x86_avx512_scatter_qpi_mask_512 : GCCBuiltin<"__builtin_ia32_mas
			k_scatterqpi512">,
			Intrinsic<[], [llvm_ptr_ty, llvm_i8_ty,
			llvm_v8i64_ty, llvm_v8i32_ty, llvm_i32_ty],
			[IntrReadWriteArgMem]>;
			def int_x86_avx512_scatter_dpq_512 : GCCBuiltin<"__builtin_ia32_scatterd
			pq512">,
			Intrinsic<[], [llvm_ptr_ty,
			llvm_v8i32_ty, llvm_v8i64_ty, llvm_i32_ty],
			[]>;
			def int_x86_avx512_scatter_dpi_512 : GCCBuiltin<"__builtin_ia32_scatterd
			pi512">,
			Intrinsic<[], [llvm_ptr_ty,
			llvm_v16i32_ty, llvm_v16i32_ty, llvm_i32_ty],
			[]>;
			def int_x86_avx512_scatter_qpq_512 : GCCBuiltin<"__builtin_ia32_scatterq
			pq512">,
			Intrinsic<[], [llvm_ptr_ty, llvm_v8i64_ty, llvm_v8i64_ty,
			llvm_i32_ty],
			[]>;
			def int_x86_avx512_scatter_qpi_512 : GCCBuiltin<"__builtin_ia32_scatterq
			pi512">,
			Intrinsic<[], [llvm_ptr_ty, llvm_v8i64_ty, llvm_v8i32_ty,
			llvm_i32_ty],
			[]>;
			}
			// AVX-512 conflict detection
			let TargetPrefix = "x86" in {
			def int_x86_avx512_conflict_d_512 : GCCBuiltin<"__builtin_ia32_conflictd5
			12">,
			Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty],
			[]>;
			def int_x86_avx512_conflict_d_mask_512 :
			GCCBuiltin<"__builtin_ia32_mask_conflictd512">,
			Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty,
			llvm_v16i1_ty, llvm_v16i32_ty],
			[]>;
			def int_x86_avx512_conflict_d_maskz_512:
			GCCBuiltin<"__builtin_ia32_maskz_conflictd512">,
			Intrinsic<[llvm_v16i32_ty], [llvm_v16i1_ty, llvm_v16i32_ty],
			[]>;
			def int_x86_avx512_conflict_q_512 : GCCBuiltin<"__builtin_ia32_conflictq5
			12">,
			Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty],
			[]>;
			def int_x86_avx512_conflict_q_mask_512 :
			GCCBuiltin<"__builtin_ia32_mask_conflictq512">,
			Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,
			llvm_v8i1_ty, llvm_v8i64_ty],
			[]>;
			def int_x86_avx512_conflict_q_maskz_512:
			GCCBuiltin<"__builtin_ia32_maskz_conflictq512">,
			Intrinsic<[llvm_v8i64_ty], [llvm_v8i1_ty, llvm_v8i64_ty],
			[]>;
			}
			// Vector blend
			let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
			def int_x86_avx512_mskblend_ps_512 : GCCBuiltin<"__builtin_ia32_mskblendp
			s512">,
			Intrinsic<[llvm_v16f32_ty],
			[llvm_v16i1_ty, llvm_v16f32_ty, llvm_v16f32_ty],
			[IntrNoMem]>;
			def int_x86_avx512_mskblend_pd_512 : GCCBuiltin<"__builtin_ia32_mskblendp
			d512">,
			Intrinsic<[llvm_v8f64_ty],
			[llvm_v8i1_ty, llvm_v8f64_ty, llvm_v8f64_ty],
			[IntrNoMem]>;
			def int_x86_avx512_mskblend_d_512 : GCCBuiltin<"__builtin_ia32_mskblendd5
			12">,
			Intrinsic<[llvm_v16i32_ty],
			[llvm_v16i1_ty, llvm_v16i32_ty, llvm_v16i32_ty],
			[IntrNoMem]>;
			def int_x86_avx512_mskblend_q_512 : GCCBuiltin<"__builtin_ia32_mskblendq5
			12">,
			Intrinsic<[llvm_v8i64_ty],
			[llvm_v8i1_ty, llvm_v8i64_ty, llvm_v8i64_ty],
			[IntrNoMem]>;
			}
			// Misc.
			let TargetPrefix = "x86" in {
			def int_x86_avx512_cmpeq_pi_512 : GCCBuiltin<"__builtin_ia32_cmpeqpi512">
			,
			Intrinsic<[llvm_i16_ty], [llvm_v16i32_ty, llvm_v16i32_ty],
			[IntrNoMem]>;
			def int_x86_avx512_and_pi : GCCBuiltin<"__builtin_ia32_andpi512">,
			Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty, llvm_v16i32_ty],
			[IntrNoMem]>;
			}
			//===----------------------------------------------------------------------
			===//
			// SHA intrinsics
			let TargetPrefix = "x86" in {
			def int_x86_sha1rnds4 : GCCBuiltin<"__builtin_ia32_sha1rnds4">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i8_t
			y],
			[IntrNoMem]>;
			def int_x86_sha1nexte : GCCBuiltin<"__builtin_ia32_sha1nexte">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem
			]>;
			def int_x86_sha1msg1 : GCCBuiltin<"__builtin_ia32_sha1msg1">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem
			]>;
			def int_x86_sha1msg2 : GCCBuiltin<"__builtin_ia32_sha1msg2">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem
			]>;
			def int_x86_sha256rnds2 : GCCBuiltin<"__builtin_ia32_sha256rnds2">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_
			ty],
			[IntrNoMem]>;
			def int_x86_sha256msg1 : GCCBuiltin<"__builtin_ia32_sha256msg1">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem
			]>;
			def int_x86_sha256msg2 : GCCBuiltin<"__builtin_ia32_sha256msg2">,
			Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem
			]>;
			}
End of changes. 11 change blocks.
	4 lines changed or deleted		68 lines changed or added

	IntrinsicsXCore.td		IntrinsicsXCore.td
	skipping to change at line 16		skipping to change at line 16
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This file defines all of the XCore-specific intrinsics.		// This file defines all of the XCore-specific intrinsics.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	let TargetPrefix = "xcore" in { // All intrinsics start with "llvm.xcore." .		let TargetPrefix = "xcore" in { // All intrinsics start with "llvm.xcore." .
	// Miscellaneous instructions.		// Miscellaneous instructions.
	def int_xcore_bitrev : Intrinsic<[llvm_i32_ty],[llvm_i32_ty],[IntrNoMem]>		def int_xcore_bitrev : Intrinsic<[llvm_i32_ty],[llvm_i32_ty],[IntrNoMem]>
	;		,
			GCCBuiltin<"__builtin_bitrev">;
	def int_xcore_crc8 : Intrinsic<[llvm_i32_ty, llvm_i32_ty],		def int_xcore_crc8 : Intrinsic<[llvm_i32_ty, llvm_i32_ty],
	[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],		[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_xcore_crc32 : Intrinsic<[llvm_i32_ty],		def int_xcore_crc32 : Intrinsic<[llvm_i32_ty],
	[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],		[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_xcore_sext : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],		def int_xcore_sext : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_xcore_zext : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],		def int_xcore_zext : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
	[IntrNoMem]>;		[IntrNoMem]>;
	def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>;		def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>,
	def int_xcore_getps : Intrinsic<[llvm_i32_ty],[llvm_i32_ty]>;		GCCBuiltin<"__builtin_getid">;
	def int_xcore_setps : Intrinsic<[],[llvm_i32_ty, llvm_i32_ty]>;		def int_xcore_getps : Intrinsic<[llvm_i32_ty],[llvm_i32_ty]>,
			GCCBuiltin<"__builtin_getps">;
			def int_xcore_setps : Intrinsic<[],[llvm_i32_ty, llvm_i32_ty]>,
			GCCBuiltin<"__builtin_setps">;
	def int_xcore_geted : Intrinsic<[llvm_i32_ty],[]>;		def int_xcore_geted : Intrinsic<[llvm_i32_ty],[]>;
	def int_xcore_getet : Intrinsic<[llvm_i32_ty],[]>;		def int_xcore_getet : Intrinsic<[llvm_i32_ty],[]>;
	def int_xcore_setsr : Intrinsic<[],[llvm_i32_ty]>;		def int_xcore_setsr : Intrinsic<[],[llvm_i32_ty]>;
	def int_xcore_clrsr : Intrinsic<[],[llvm_i32_ty]>;		def int_xcore_clrsr : Intrinsic<[],[llvm_i32_ty]>;
	// Resource instructions.		// Resource instructions.
	def int_xcore_getr : Intrinsic<[llvm_anyptr_ty],[llvm_i32_ty]>;		def int_xcore_getr : Intrinsic<[llvm_anyptr_ty],[llvm_i32_ty]>;
	def int_xcore_freer : Intrinsic<[],[llvm_anyptr_ty],		def int_xcore_freer : Intrinsic<[],[llvm_anyptr_ty],
	[NoCapture<0>]>;		[NoCapture<0>]>;
	def int_xcore_in : Intrinsic<[llvm_i32_ty],[llvm_anyptr_ty],[NoCapture<0> ]>;		def int_xcore_in : Intrinsic<[llvm_i32_ty],[llvm_anyptr_ty],[NoCapture<0> ]>;
End of changes. 2 change blocks.
	5 lines changed or deleted		9 lines changed or added

	JITMemoryManager.h		JITMemoryManager.h
	skipping to change at line 118		skipping to change at line 118
	/// allocateGlobal - Allocate memory for a global.		/// allocateGlobal - Allocate memory for a global.
	virtual uint8_t *allocateGlobal(uintptr_t Size, unsigned Alignment) = 0;		virtual uint8_t *allocateGlobal(uintptr_t Size, unsigned Alignment) = 0;
	/// deallocateFunctionBody - Free the specified function body. The argum ent		/// deallocateFunctionBody - Free the specified function body. The argum ent
	/// must be the return value from a call to startFunctionBody() that hasn 't		/// must be the return value from a call to startFunctionBody() that hasn 't
	/// been deallocated yet. This is never called when the JIT is currently		/// been deallocated yet. This is never called when the JIT is currently
	/// emitting a function.		/// emitting a function.
	virtual void deallocateFunctionBody(void *Body) = 0;		virtual void deallocateFunctionBody(void *Body) = 0;
	/// startExceptionTable - When we finished JITing the function, if except
	ion
	/// handling is set, we emit the exception table.
	virtual uint8_t* startExceptionTable(const Function* F,
	uintptr_t &ActualSize) = 0;
	/// endExceptionTable - This method is called when the JIT is done emitti
	ng
	/// the exception table.
	virtual void endExceptionTable(const Function *F, uint8_t *TableStart,
	uint8_t *TableEnd, uint8_t* FrameRegister)
	= 0;
	/// deallocateExceptionTable - Free the specified exception table's memor
	y.
	/// The argument must be the return value from a call to startExceptionTa
	ble()
	/// that hasn't been deallocated yet. This is never called when the JIT
	is
	/// currently emitting an exception table.
	virtual void deallocateExceptionTable(void *ET) = 0;
	/// CheckInvariants - For testing only. Return true if all internal		/// CheckInvariants - For testing only. Return true if all internal
	/// invariants are preserved, or return false and set ErrorStr to a helpf ul		/// invariants are preserved, or return false and set ErrorStr to a helpf ul
	/// error message.		/// error message.
	virtual bool CheckInvariants(std::string &) {		virtual bool CheckInvariants(std::string &) {
	return true;		return true;
	}		}
	/// GetDefaultCodeSlabSize - For testing only. Returns DefaultCodeSlabSi ze		/// GetDefaultCodeSlabSize - For testing only. Returns DefaultCodeSlabSi ze
	/// from DefaultJITMemoryManager.		/// from DefaultJITMemoryManager.
	virtual size_t GetDefaultCodeSlabSize() {		virtual size_t GetDefaultCodeSlabSize() {
End of changes. 1 change blocks.
	22 lines changed or deleted		0 lines changed or added

	LEB128.h		LEB128.h
	skipping to change at line 23		skipping to change at line 23
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_SUPPORT_LEB128_H		#ifndef LLVM_SUPPORT_LEB128_H
	#define LLVM_SUPPORT_LEB128_H		#define LLVM_SUPPORT_LEB128_H
	#include "llvm/Support/raw_ostream.h"		#include "llvm/Support/raw_ostream.h"
	namespace llvm {		namespace llvm {
	/// Utility function to encode a SLEB128 value to an output stream.		/// Utility function to encode a SLEB128 value to an output stream.
	static inline void encodeSLEB128(int64_t Value, raw_ostream &OS) {		inline void encodeSLEB128(int64_t Value, raw_ostream &OS) {
	bool More;		bool More;
	do {		do {
	uint8_t Byte = Value & 0x7f;		uint8_t Byte = Value & 0x7f;
	// NOTE: this assumes that this signed shift is an arithmetic right shi ft.		// NOTE: this assumes that this signed shift is an arithmetic right shi ft.
	Value >>= 7;		Value >>= 7;
	More = !((((Value == 0 ) && ((Byte & 0x40) == 0)) ||		More = !((((Value == 0 ) && ((Byte & 0x40) == 0)) ||
	((Value == -1) && ((Byte & 0x40) != 0))));		((Value == -1) && ((Byte & 0x40) != 0))));
	if (More)		if (More)
	Byte |= 0x80; // Mark this byte that that more bytes will follow.		Byte |= 0x80; // Mark this byte to show that more bytes will follow.
	OS << char(Byte);		OS << char(Byte);
	} while (More);		} while (More);
	}		}
	/// Utility function to encode a ULEB128 value to an output stream.		/// Utility function to encode a ULEB128 value to an output stream.
	static inline void encodeULEB128(uint64_t Value, raw_ostream &OS,		inline void encodeULEB128(uint64_t Value, raw_ostream &OS,
	unsigned Padding = 0) {		unsigned Padding = 0) {
	do {		do {
	uint8_t Byte = Value & 0x7f;		uint8_t Byte = Value & 0x7f;
	Value >>= 7;		Value >>= 7;
	if (Value != 0 || Padding != 0)		if (Value != 0 || Padding != 0)
	Byte |= 0x80; // Mark this byte that that more bytes will follow.		Byte |= 0x80; // Mark this byte to show that more bytes will follow.
	OS << char(Byte);		OS << char(Byte);
	} while (Value != 0);		} while (Value != 0);
	// Pad with 0x80 and emit a null byte at the end.		// Pad with 0x80 and emit a null byte at the end.
	if (Padding != 0) {		if (Padding != 0) {
	for (; Padding != 1; --Padding)		for (; Padding != 1; --Padding)
	OS << '\x80';		OS << '\x80';
	OS << '\x00';		OS << '\x00';
	}		}
	}		}
	/// Utility function to encode a ULEB128 value to a buffer. Returns		/// Utility function to encode a ULEB128 value to a buffer. Returns
	/// the length in bytes of the encoded value.		/// the length in bytes of the encoded value.
	static inline unsigned encodeULEB128(uint64_t Value, uint8_t *p,		inline unsigned encodeULEB128(uint64_t Value, uint8_t *p,
	unsigned Padding = 0) {		unsigned Padding = 0) {
	uint8_t *orig_p = p;		uint8_t *orig_p = p;
	do {		do {
	uint8_t Byte = Value & 0x7f;		uint8_t Byte = Value & 0x7f;
	Value >>= 7;		Value >>= 7;
	if (Value != 0 || Padding != 0)		if (Value != 0 || Padding != 0)
	Byte |= 0x80; // Mark this byte that that more bytes will follow.		Byte |= 0x80; // Mark this byte to show that more bytes will follow.
	*p++ = Byte;		*p++ = Byte;
	} while (Value != 0);		} while (Value != 0);
	// Pad with 0x80 and emit a null byte at the end.		// Pad with 0x80 and emit a null byte at the end.
	if (Padding != 0) {		if (Padding != 0) {
	for (; Padding != 1; --Padding)		for (; Padding != 1; --Padding)
	*p++ = '\x80';		*p++ = '\x80';
	*p++ = '\x00';		*p++ = '\x00';
	}		}
	return (unsigned)(p - orig_p);		return (unsigned)(p - orig_p);
	}		}
	/// Utility function to decode a ULEB128 value.		/// Utility function to decode a ULEB128 value.
	static inline uint64_t decodeULEB128(const uint8_t *p, unsigned *n = 0) {		inline uint64_t decodeULEB128(const uint8_t *p, unsigned *n = 0) {
	const uint8_t *orig_p = p;		const uint8_t *orig_p = p;
	uint64_t Value = 0;		uint64_t Value = 0;
	unsigned Shift = 0;		unsigned Shift = 0;
	do {		do {
	Value += (*p & 0x7f) << Shift;		Value += (*p & 0x7f) << Shift;
	Shift += 7;		Shift += 7;
	} while (*p++ >= 128);		} while (*p++ >= 128);
	if (n)		if (n)
	*n = (unsigned)(p - orig_p);		*n = (unsigned)(p - orig_p);
	return Value;		return Value;
End of changes. 7 change blocks.
	9 lines changed or deleted		9 lines changed or added

	LLVMBitCodes.h		LLVMBitCodes.h
	skipping to change at line 196		skipping to change at line 196
	CAST_ZEXT = 1,		CAST_ZEXT = 1,
	CAST_SEXT = 2,		CAST_SEXT = 2,
	CAST_FPTOUI = 3,		CAST_FPTOUI = 3,
	CAST_FPTOSI = 4,		CAST_FPTOSI = 4,
	CAST_UITOFP = 5,		CAST_UITOFP = 5,
	CAST_SITOFP = 6,		CAST_SITOFP = 6,
	CAST_FPTRUNC = 7,		CAST_FPTRUNC = 7,
	CAST_FPEXT = 8,		CAST_FPEXT = 8,
	CAST_PTRTOINT = 9,		CAST_PTRTOINT = 9,
	CAST_INTTOPTR = 10,		CAST_INTTOPTR = 10,
	CAST_BITCAST = 11		CAST_BITCAST = 11,
			CAST_ADDRSPACECAST = 12
	};		};
	/// BinaryOpcodes - These are values used in the bitcode files to encode which		/// BinaryOpcodes - These are values used in the bitcode files to encode which
	/// binop a CST_CODE_CE_BINOP or a XXX refers to. The values of these en ums		/// binop a CST_CODE_CE_BINOP or a XXX refers to. The values of these en ums
	/// have no fixed relation to the LLVM IR enum values. Changing these wi ll		/// have no fixed relation to the LLVM IR enum values. Changing these wi ll
	/// break compatibility with old files.		/// break compatibility with old files.
	enum BinaryOpcodes {		enum BinaryOpcodes {
	BINOP_ADD = 0,		BINOP_ADD = 0,
	BINOP_SUB = 1,		BINOP_SUB = 1,
	BINOP_MUL = 2,		BINOP_MUL = 2,
	skipping to change at line 332		skipping to change at line 333
	FUNC_CODE_INST_LANDINGPAD = 40, // LANDINGPAD: [ty,val,val,num,id0,val 0...]		FUNC_CODE_INST_LANDINGPAD = 40, // LANDINGPAD: [ty,val,val,num,id0,val 0...]
	FUNC_CODE_INST_LOADATOMIC = 41, // LOAD: [opty, op, align, vol,		FUNC_CODE_INST_LOADATOMIC = 41, // LOAD: [opty, op, align, vol,
	// ordering, synchscope]		// ordering, synchscope]
	FUNC_CODE_INST_STOREATOMIC = 42 // STORE: [ptrty,ptr,val, align, vol		FUNC_CODE_INST_STOREATOMIC = 42 // STORE: [ptrty,ptr,val, align, vol
	// ordering, synchscope]		// ordering, synchscope]
	};		};
	enum UseListCodes {		enum UseListCodes {
	USELIST_CODE_ENTRY = 1 // USELIST_CODE_ENTRY: TBD.		USELIST_CODE_ENTRY = 1 // USELIST_CODE_ENTRY: TBD.
	};		};
			enum AttributeKindCodes {
			// = 0 is unused
			ATTR_KIND_ALIGNMENT = 1,
			ATTR_KIND_ALWAYS_INLINE = 2,
			ATTR_KIND_BY_VAL = 3,
			ATTR_KIND_INLINE_HINT = 4,
			ATTR_KIND_IN_REG = 5,
			ATTR_KIND_MIN_SIZE = 6,
			ATTR_KIND_NAKED = 7,
			ATTR_KIND_NEST = 8,
			ATTR_KIND_NO_ALIAS = 9,
			ATTR_KIND_NO_BUILTIN = 10,
			ATTR_KIND_NO_CAPTURE = 11,
			ATTR_KIND_NO_DUPLICATE = 12,
			ATTR_KIND_NO_IMPLICIT_FLOAT = 13,
			ATTR_KIND_NO_INLINE = 14,
			ATTR_KIND_NON_LAZY_BIND = 15,
			ATTR_KIND_NO_RED_ZONE = 16,
			ATTR_KIND_NO_RETURN = 17,
			ATTR_KIND_NO_UNWIND = 18,
			ATTR_KIND_OPTIMIZE_FOR_SIZE = 19,
			ATTR_KIND_READ_NONE = 20,
			ATTR_KIND_READ_ONLY = 21,
			ATTR_KIND_RETURNED = 22,
			ATTR_KIND_RETURNS_TWICE = 23,
			ATTR_KIND_S_EXT = 24,
			ATTR_KIND_STACK_ALIGNMENT = 25,
			ATTR_KIND_STACK_PROTECT = 26,
			ATTR_KIND_STACK_PROTECT_REQ = 27,
			ATTR_KIND_STACK_PROTECT_STRONG = 28,
			ATTR_KIND_STRUCT_RET = 29,
			ATTR_KIND_SANITIZE_ADDRESS = 30,
			ATTR_KIND_SANITIZE_THREAD = 31,
			ATTR_KIND_SANITIZE_MEMORY = 32,
			ATTR_KIND_UW_TABLE = 33,
			ATTR_KIND_Z_EXT = 34,
			ATTR_KIND_BUILTIN = 35,
			ATTR_KIND_COLD = 36,
			ATTR_KIND_OPTIMIZE_NONE = 37
			};
	} // End bitc namespace		} // End bitc namespace
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 2 change blocks.
	1 lines changed or deleted		44 lines changed or added

	LexicalScopes.h		LexicalScopes.h
	skipping to change at line 145		skipping to change at line 145
	/// InlinedLexicalScopeMap - Tracks inlined function scopes in current fu nction.		/// InlinedLexicalScopeMap - Tracks inlined function scopes in current fu nction.
	DenseMap<DebugLoc, LexicalScope *> InlinedLexicalScopeMap;		DenseMap<DebugLoc, LexicalScope *> InlinedLexicalScopeMap;
	/// AbstractScopeMap - These scopes are not included LexicalScopeMap.		/// AbstractScopeMap - These scopes are not included LexicalScopeMap.
	/// AbstractScopes owns its LexicalScope*s.		/// AbstractScopes owns its LexicalScope*s.
	DenseMap<const MDNode *, LexicalScope *> AbstractScopeMap;		DenseMap<const MDNode *, LexicalScope *> AbstractScopeMap;
	/// AbstractScopesList - Tracks abstract scopes constructed while process ing		/// AbstractScopesList - Tracks abstract scopes constructed while process ing
	/// a function.		/// a function.
	SmallVector<LexicalScope *, 4>AbstractScopesList;		SmallVector<LexicalScope *, 4> AbstractScopesList;
	/// CurrentFnLexicalScope - Top level scope for the current function.		/// CurrentFnLexicalScope - Top level scope for the current function.
	///		///
	LexicalScope *CurrentFnLexicalScope;		LexicalScope *CurrentFnLexicalScope;
	};		};
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	/// LexicalScope - This class is used to track scope information.		/// LexicalScope - This class is used to track scope information.
	///		///
	class LexicalScope {		class LexicalScope {
	skipping to change at line 169		skipping to change at line 169
	LexicalScope(LexicalScope *P, const MDNode *D, const MDNode *I, bool A)		LexicalScope(LexicalScope *P, const MDNode *D, const MDNode *I, bool A)
	: Parent(P), Desc(D), InlinedAtLocation(I), AbstractScope(A),		: Parent(P), Desc(D), InlinedAtLocation(I), AbstractScope(A),
	LastInsn(0), FirstInsn(0), DFSIn(0), DFSOut(0) {		LastInsn(0), FirstInsn(0), DFSIn(0), DFSOut(0) {
	if (Parent)		if (Parent)
	Parent->addChild(this);		Parent->addChild(this);
	}		}
	virtual ~LexicalScope() {}		virtual ~LexicalScope() {}
	// Accessors.		// Accessors.
	LexicalScope *getParent() const { return Parent; }		LexicalScope *getParent() const { return Parent; }
	const MDNode *getDesc() const { return Desc; }		const MDNode *getDesc() const { return Desc; }
	const MDNode *getInlinedAt() const { return InlinedAtLocation;		const MDNode *getInlinedAt() const { return InlinedAtLocation
	}		; }
	const MDNode *getScopeNode() const { return Desc; }		const MDNode *getScopeNode() const { return Desc; }
	bool isAbstractScope() const { return AbstractScope; }		bool isAbstractScope() const { return AbstractScope; }
	SmallVector<LexicalScope *, 4> &getChildren() { return Children; }		SmallVectorImpl<LexicalScope *> &getChildren() { return Children; }
	SmallVector<InsnRange, 4> &getRanges() { return Ranges; }		SmallVectorImpl<InsnRange> &getRanges() { return Ranges; }
	/// addChild - Add a child scope.		/// addChild - Add a child scope.
	void addChild(LexicalScope *S) { Children.push_back(S); }		void addChild(LexicalScope *S) { Children.push_back(S); }
	/// openInsnRange - This scope covers instruction range starting from MI.		/// openInsnRange - This scope covers instruction range starting from MI.
	void openInsnRange(const MachineInstr *MI) {		void openInsnRange(const MachineInstr *MI) {
	if (!FirstInsn)		if (!FirstInsn)
	FirstInsn = MI;		FirstInsn = MI;
	if (Parent)		if (Parent)
End of changes. 2 change blocks.
	9 lines changed or deleted		9 lines changed or added

	LinkAllPasses.h		LinkAllPasses.h
	skipping to change at line 59		skipping to change at line 59
	(void) llvm::createAAEvalPass();		(void) llvm::createAAEvalPass();
	(void) llvm::createAggressiveDCEPass();		(void) llvm::createAggressiveDCEPass();
	(void) llvm::createAliasAnalysisCounterPass();		(void) llvm::createAliasAnalysisCounterPass();
	(void) llvm::createAliasDebugger();		(void) llvm::createAliasDebugger();
	(void) llvm::createArgumentPromotionPass();		(void) llvm::createArgumentPromotionPass();
	(void) llvm::createBasicAliasAnalysisPass();		(void) llvm::createBasicAliasAnalysisPass();
	(void) llvm::createLibCallAliasAnalysisPass(0);		(void) llvm::createLibCallAliasAnalysisPass(0);
	(void) llvm::createScalarEvolutionAliasAnalysisPass();		(void) llvm::createScalarEvolutionAliasAnalysisPass();
	(void) llvm::createTypeBasedAliasAnalysisPass();		(void) llvm::createTypeBasedAliasAnalysisPass();
	(void) llvm::createBlockPlacementPass();
	(void) llvm::createBoundsCheckingPass();		(void) llvm::createBoundsCheckingPass();
	(void) llvm::createBreakCriticalEdgesPass();		(void) llvm::createBreakCriticalEdgesPass();
	(void) llvm::createCallGraphPrinterPass();		(void) llvm::createCallGraphPrinterPass();
	(void) llvm::createCallGraphViewerPass();		(void) llvm::createCallGraphViewerPass();
	(void) llvm::createCFGSimplificationPass();		(void) llvm::createCFGSimplificationPass();
			(void) llvm::createStructurizeCFGPass();
	(void) llvm::createConstantMergePass();		(void) llvm::createConstantMergePass();
	(void) llvm::createConstantPropagationPass();		(void) llvm::createConstantPropagationPass();
	(void) llvm::createCostModelAnalysisPass();		(void) llvm::createCostModelAnalysisPass();
	(void) llvm::createDeadArgEliminationPass();		(void) llvm::createDeadArgEliminationPass();
	(void) llvm::createDeadCodeEliminationPass();		(void) llvm::createDeadCodeEliminationPass();
	(void) llvm::createDeadInstEliminationPass();		(void) llvm::createDeadInstEliminationPass();
	(void) llvm::createDeadStoreEliminationPass();		(void) llvm::createDeadStoreEliminationPass();
	(void) llvm::createDependenceAnalysisPass();		(void) llvm::createDependenceAnalysisPass();
	(void) llvm::createDomOnlyPrinterPass();		(void) llvm::createDomOnlyPrinterPass();
	(void) llvm::createDomPrinterPass();		(void) llvm::createDomPrinterPass();
	(void) llvm::createDomOnlyViewerPass();		(void) llvm::createDomOnlyViewerPass();
	(void) llvm::createDomViewerPass();		(void) llvm::createDomViewerPass();
	(void) llvm::createEdgeProfilerPass();
	(void) llvm::createOptimalEdgeProfilerPass();
	(void) llvm::createPathProfilerPass();
	(void) llvm::createGCOVProfilerPass();		(void) llvm::createGCOVProfilerPass();
	(void) llvm::createFunctionInliningPass();		(void) llvm::createFunctionInliningPass();
	(void) llvm::createAlwaysInlinerPass();		(void) llvm::createAlwaysInlinerPass();
	(void) llvm::createGlobalDCEPass();		(void) llvm::createGlobalDCEPass();
	(void) llvm::createGlobalOptimizerPass();		(void) llvm::createGlobalOptimizerPass();
	(void) llvm::createGlobalsModRefPass();		(void) llvm::createGlobalsModRefPass();
	(void) llvm::createIPConstantPropagationPass();		(void) llvm::createIPConstantPropagationPass();
	(void) llvm::createIPSCCPPass();		(void) llvm::createIPSCCPPass();
	(void) llvm::createIndVarSimplifyPass();		(void) llvm::createIndVarSimplifyPass();
	(void) llvm::createInstructionCombiningPass();		(void) llvm::createInstructionCombiningPass();
	(void) llvm::createInternalizePass();		(void) llvm::createInternalizePass();
	(void) llvm::createLCSSAPass();		(void) llvm::createLCSSAPass();
	(void) llvm::createLICMPass();		(void) llvm::createLICMPass();
	(void) llvm::createLazyValueInfoPass();		(void) llvm::createLazyValueInfoPass();
	(void) llvm::createLoopExtractorPass();		(void) llvm::createLoopExtractorPass();
	(void) llvm::createLoopSimplifyPass();		(void) llvm::createLoopSimplifyPass();
	(void) llvm::createLoopStrengthReducePass();		(void) llvm::createLoopStrengthReducePass();
			(void) llvm::createLoopRerollPass();
	(void) llvm::createLoopUnrollPass();		(void) llvm::createLoopUnrollPass();
	(void) llvm::createLoopUnswitchPass();		(void) llvm::createLoopUnswitchPass();
	(void) llvm::createLoopIdiomPass();		(void) llvm::createLoopIdiomPass();
	(void) llvm::createLoopRotatePass();		(void) llvm::createLoopRotatePass();
	(void) llvm::createLowerExpectIntrinsicPass();		(void) llvm::createLowerExpectIntrinsicPass();
	(void) llvm::createLowerInvokePass();		(void) llvm::createLowerInvokePass();
	(void) llvm::createLowerSwitchPass();		(void) llvm::createLowerSwitchPass();
	(void) llvm::createNoAAPass();		(void) llvm::createNoAAPass();
	(void) llvm::createNoProfileInfoPass();
	(void) llvm::createObjCARCAliasAnalysisPass();		(void) llvm::createObjCARCAliasAnalysisPass();
	(void) llvm::createObjCARCAPElimPass();		(void) llvm::createObjCARCAPElimPass();
	(void) llvm::createObjCARCExpandPass();		(void) llvm::createObjCARCExpandPass();
	(void) llvm::createObjCARCContractPass();		(void) llvm::createObjCARCContractPass();
	(void) llvm::createObjCARCOptPass();		(void) llvm::createObjCARCOptPass();
	(void) llvm::createProfileEstimatorPass();
	(void) llvm::createProfileVerifierPass();
	(void) llvm::createPathProfileVerifierPass();
	(void) llvm::createProfileLoaderPass();
	(void) llvm::createProfileMetadataLoaderPass();
	(void) llvm::createPathProfileLoaderPass();
	(void) llvm::createPromoteMemoryToRegisterPass();		(void) llvm::createPromoteMemoryToRegisterPass();
	(void) llvm::createDemoteRegisterToMemoryPass();		(void) llvm::createDemoteRegisterToMemoryPass();
	(void) llvm::createPruneEHPass();		(void) llvm::createPruneEHPass();
	(void) llvm::createPostDomOnlyPrinterPass();		(void) llvm::createPostDomOnlyPrinterPass();
	(void) llvm::createPostDomPrinterPass();		(void) llvm::createPostDomPrinterPass();
	(void) llvm::createPostDomOnlyViewerPass();		(void) llvm::createPostDomOnlyViewerPass();
	(void) llvm::createPostDomViewerPass();		(void) llvm::createPostDomViewerPass();
	(void) llvm::createReassociatePass();		(void) llvm::createReassociatePass();
	(void) llvm::createRegionInfoPass();		(void) llvm::createRegionInfoPass();
	(void) llvm::createRegionOnlyPrinterPass();		(void) llvm::createRegionOnlyPrinterPass();
	(void) llvm::createRegionOnlyViewerPass();		(void) llvm::createRegionOnlyViewerPass();
	(void) llvm::createRegionPrinterPass();		(void) llvm::createRegionPrinterPass();
	(void) llvm::createRegionViewerPass();		(void) llvm::createRegionViewerPass();
	(void) llvm::createSCCPPass();		(void) llvm::createSCCPPass();
	(void) llvm::createScalarReplAggregatesPass();		(void) llvm::createScalarReplAggregatesPass();
	(void) llvm::createSimplifyLibCallsPass();
	(void) llvm::createSingleLoopExtractorPass();		(void) llvm::createSingleLoopExtractorPass();
	(void) llvm::createStripSymbolsPass();		(void) llvm::createStripSymbolsPass();
	(void) llvm::createStripNonDebugSymbolsPass();		(void) llvm::createStripNonDebugSymbolsPass();
	(void) llvm::createStripDeadDebugInfoPass();		(void) llvm::createStripDeadDebugInfoPass();
	(void) llvm::createStripDeadPrototypesPass();		(void) llvm::createStripDeadPrototypesPass();
	(void) llvm::createTailCallEliminationPass();		(void) llvm::createTailCallEliminationPass();
	(void) llvm::createJumpThreadingPass();		(void) llvm::createJumpThreadingPass();
	(void) llvm::createUnifyFunctionExitNodesPass();		(void) llvm::createUnifyFunctionExitNodesPass();
	(void) llvm::createInstCountPass();		(void) llvm::createInstCountPass();
	(void) llvm::createCodeGenPreparePass();		(void) llvm::createCodeGenPreparePass();
	skipping to change at line 166		skipping to change at line 156
	(void) llvm::createPartialInliningPass();		(void) llvm::createPartialInliningPass();
	(void) llvm::createLintPass();		(void) llvm::createLintPass();
	(void) llvm::createSinkingPass();		(void) llvm::createSinkingPass();
	(void) llvm::createLowerAtomicPass();		(void) llvm::createLowerAtomicPass();
	(void) llvm::createCorrelatedValuePropagationPass();		(void) llvm::createCorrelatedValuePropagationPass();
	(void) llvm::createMemDepPrinter();		(void) llvm::createMemDepPrinter();
	(void) llvm::createInstructionSimplifierPass();		(void) llvm::createInstructionSimplifierPass();
	(void) llvm::createLoopVectorizePass();		(void) llvm::createLoopVectorizePass();
	(void) llvm::createSLPVectorizerPass();		(void) llvm::createSLPVectorizerPass();
	(void) llvm::createBBVectorizePass();		(void) llvm::createBBVectorizePass();
			(void) llvm::createPartiallyInlineLibCallsPass();
	(void)new llvm::IntervalPartition();		(void)new llvm::IntervalPartition();
	(void)new llvm::FindUsedTypes();		(void)new llvm::FindUsedTypes();
	(void)new llvm::ScalarEvolution();		(void)new llvm::ScalarEvolution();
	((llvm::Function*)0)->viewCFGOnly();		((llvm::Function*)0)->viewCFGOnly();
	llvm::RGPassManager RGM;		llvm::RGPassManager RGM;
	((llvm::RegionPass*)0)->runOnRegion((llvm::Region*)0, RGM);		((llvm::RegionPass*)0)->runOnRegion((llvm::Region*)0, RGM);
	llvm::AliasSetTracker X(*(llvm::AliasAnalysis*)0);		llvm::AliasSetTracker X(*(llvm::AliasAnalysis*)0);
	X.add((llvm::Value*)0, 0, 0); // for -print-alias-sets		X.add((llvm::Value*)0, 0, 0); // for -print-alias-sets
	}		}
End of changes. 8 change blocks.
	12 lines changed or deleted		3 lines changed or added

	Linker.h		Linker.h
	skipping to change at line 35		skipping to change at line 35
	/// something with it after the linking.		/// something with it after the linking.
	class Linker {		class Linker {
	public:		public:
	enum LinkerMode {		enum LinkerMode {
	DestroySource = 0, // Allow source module to be destroyed.		DestroySource = 0, // Allow source module to be destroyed.
	PreserveSource = 1 // Preserve the source module.		PreserveSource = 1 // Preserve the source module.
	};		};
	Linker(Module *M);		Linker(Module *M);
	~Linker();		~Linker();
	Module *getModule() const { return Composite; }		Module *getModule() const { return Composite; }
			void deleteModule();
	/// \brief Link \p Src into the composite. The source is destroyed if		/// \brief Link \p Src into the composite. The source is destroyed if
	/// \p Mode is DestroySource and preserved if it is PreserveSource.		/// \p Mode is DestroySource and preserved if it is PreserveSource.
	/// If \p ErrorMsg is not null, information about any error is written		/// If \p ErrorMsg is not null, information about any error is written
	/// to it.		/// to it.
	/// Returns true on error.		/// Returns true on error.
	bool linkInModule(Module *Src, unsigned Mode, std::string *ErrorMsg);		bool linkInModule(Module *Src, unsigned Mode, std::string *ErrorMsg);
	bool linkInModule(Module *Src, std::string *ErrorMsg) {		bool linkInModule(Module *Src, std::string *ErrorMsg) {
	return linkInModule(Src, Linker::DestroySource, ErrorMsg);		return linkInModule(Src, Linker::DestroySource, ErrorMsg);
	}		}
End of changes. 2 change blocks.
	0 lines changed or deleted		2 lines changed or added

	LiveInterval.h		LiveInterval.h
	skipping to change at line 12		skipping to change at line 12
	//		//
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This file implements the LiveRange and LiveInterval classes. Given some		// This file implements the LiveRange and LiveInterval classes. Given some
	// numbering of each the machine instructions an interval [i, j) is said to be a		// numbering of each the machine instructions an interval [i, j) is said to be a
	// live interval for register v if there is no instruction with number j' > = j		// live range for register v if there is no instruction with number j' >= j
	// such that v is live at j' and there is no instruction with number i' < i such		// such that v is live at j' and there is no instruction with number i' < i such
	// that v is live at i'. In this implementation intervals can have holes,		// that v is live at i'. In this implementation ranges can have holes,
	// i.e. an interval might look like [1,20), [50,65), [1000,1001). Each		// i.e. a range might look like [1,20), [50,65), [1000,1001). Each
	// individual range is represented as an instance of LiveRange, and the who		// individual segment is represented as an instance of LiveRange::Segment,
	le		// and the whole range is represented as an instance of LiveRange.
	// interval is represented as an instance of LiveInterval.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_CODEGEN_LIVEINTERVAL_H		#ifndef LLVM_CODEGEN_LIVEINTERVAL_H
	#define LLVM_CODEGEN_LIVEINTERVAL_H		#define LLVM_CODEGEN_LIVEINTERVAL_H
	#include "llvm/ADT/IntEqClasses.h"		#include "llvm/ADT/IntEqClasses.h"
	#include "llvm/CodeGen/SlotIndexes.h"		#include "llvm/CodeGen/SlotIndexes.h"
	#include "llvm/Support/AlignOf.h"		#include "llvm/Support/AlignOf.h"
	#include "llvm/Support/Allocator.h"		#include "llvm/Support/Allocator.h"
	#include <cassert>		#include <cassert>
	#include <climits>		#include <climits>
	namespace llvm {		namespace llvm {
	class CoalescerPair;		class CoalescerPair;
	class LiveIntervals;		class LiveIntervals;
	class MachineInstr;		class MachineInstr;
	class MachineRegisterInfo;		class MachineRegisterInfo;
	class TargetRegisterInfo;		class TargetRegisterInfo;
	class raw_ostream;		class raw_ostream;
			template <typename T, unsigned Small> class SmallPtrSet;
	/// VNInfo - Value Number Information.		/// VNInfo - Value Number Information.
	/// This class holds information about a machine level values, including		/// This class holds information about a machine level values, including
	/// definition and use points.		/// definition and use points.
	///		///
	class VNInfo {		class VNInfo {
	public:		public:
	typedef BumpPtrAllocator Allocator;		typedef BumpPtrAllocator Allocator;
	/// The ID number of this value.		/// The ID number of this value.
	skipping to change at line 69		skipping to change at line 70
	VNInfo(unsigned i, const VNInfo &orig)		VNInfo(unsigned i, const VNInfo &orig)
	: id(i), def(orig.def)		: id(i), def(orig.def)
	{ }		{ }
	/// Copy from the parameter into this VNInfo.		/// Copy from the parameter into this VNInfo.
	void copyFrom(VNInfo &src) {		void copyFrom(VNInfo &src) {
	def = src.def;		def = src.def;
	}		}
	/// Returns true if this value is defined by a PHI instruction (or was,		/// Returns true if this value is defined by a PHI instruction (or was,
	/// PHI instrucions may have been eliminated).		/// PHI instructions may have been eliminated).
	/// PHI-defs begin at a block boundary, all other defs begin at registe r or		/// PHI-defs begin at a block boundary, all other defs begin at registe r or
	/// EC slots.		/// EC slots.
	bool isPHIDef() const { return def.isBlock(); }		bool isPHIDef() const { return def.isBlock(); }
	/// Returns true if this value is unused.		/// Returns true if this value is unused.
	bool isUnused() const { return !def.isValid(); }		bool isUnused() const { return !def.isValid(); }
	/// Mark this value as unused.		/// Mark this value as unused.
	void markUnused() { def = SlotIndex(); }		void markUnused() { def = SlotIndex(); }
	};		};
	/// LiveRange structure - This represents a simple register range in the		/// Result of a LiveRange query. This class hides the implementation deta
	/// program, with an inclusive start point and an exclusive end point.		ils
	/// These ranges are rendered as [start,end).		/// of live ranges, and it should be used as the primary interface for
	struct LiveRange {		/// examining live ranges around instructions.
	SlotIndex start; // Start point of the interval (inclusive)		class LiveQueryResult {
	SlotIndex end; // End point of the interval (exclusive)		VNInfo *const EarlyVal;
	VNInfo *valno; // identifier for the value contained in this interval		VNInfo *const LateVal;
	.		const SlotIndex EndPoint;
			const bool Kill;
	LiveRange() : valno(0) {}
			public:
	LiveRange(SlotIndex S, SlotIndex E, VNInfo *V)		LiveQueryResult(VNInfo *EarlyVal, VNInfo *LateVal, SlotIndex EndPoint,
	: start(S), end(E), valno(V) {		bool Kill)
	assert(S < E && "Cannot create empty or backwards range");		: EarlyVal(EarlyVal), LateVal(LateVal), EndPoint(EndPoint), Kill(Kill
			)
			{}
			/// Return the value that is live-in to the instruction. This is the va
			lue
			/// that will be read by the instruction's use operands. Return NULL if
			no
			/// value is live-in.
			VNInfo *valueIn() const {
			return EarlyVal;
	}		}
	/// contains - Return true if the index is covered by this range.		/// Return true if the live-in value is killed by this instruction. Thi
	///		s
	bool contains(SlotIndex I) const {		/// means that either the live range ends at the instruction, or it cha
	return start <= I && I < end;		nges
			/// value.
			bool isKill() const {
			return Kill;
	}		}
	/// containsRange - Return true if the given range, [S, E), is covered		/// Return true if this instruction has a dead def.
	by		bool isDeadDef() const {
	/// this range.		return EndPoint.isDead();
	bool containsRange(SlotIndex S, SlotIndex E) const {
	assert((S < E) && "Backwards interval?");
	return (start <= S && S < end) && (start < E && E <= end);
	}		}
	bool operator<(const LiveRange &LR) const {		/// Return the value leaving the instruction, if any. This can be a
	return start < LR.start || (start == LR.start && end < LR.end);		/// live-through value, or a live def. A dead def returns NULL.
			VNInfo *valueOut() const {
			return isDeadDef() ? 0 : LateVal;
	}		}
	bool operator==(const LiveRange &LR) const {
	return start == LR.start && end == LR.end;		/// Return the value defined by this instruction, if any. This includes
			/// dead defs, it is the value created by the instruction's def operand
			s.
			VNInfo *valueDefined() const {
			return EarlyVal == LateVal ? 0 : LateVal;
	}		}
	void dump() const;		/// Return the end point of the last live range segment to interact wit
	void print(raw_ostream &os) const;		h
			/// the instruction, if any.
			///
			/// The end point is an invalid SlotIndex only if the live range doesn'
			t
			/// intersect the instruction at all.
			///
			/// The end point may be at or past the end of the instruction's basic
			/// block. That means the value was live out of the block.
			SlotIndex endPoint() const {
			return EndPoint;
			}
	};		};
	template <> struct isPodLike<LiveRange> { static const bool value = true;		/// This class represents the liveness of a register, stack slot, etc.
	};		/// It manages an ordered list of Segment objects.
			/// The Segments are organized in a static single assignment form: At pla
			ces
			/// where a new value is defined or different values reach a CFG join a n
			ew
			/// segment with a new value number is used.
			class LiveRange {
			public:
			/// This represents a simple continuous liveness interval for a value.
			/// The start point is inclusive, the end point exclusive. These interv
			als
			/// are rendered as [start,end).
			struct Segment {
			SlotIndex start; // Start point of the interval (inclusive)
			SlotIndex end; // End point of the interval (exclusive)
			VNInfo *valno; // identifier for the value contained in this segme
			nt.
			Segment() : valno(0) {}
			Segment(SlotIndex S, SlotIndex E, VNInfo *V)
			: start(S), end(E), valno(V) {
			assert(S < E && "Cannot create empty or backwards segment");
			}
	raw_ostream& operator<<(raw_ostream& os, const LiveRange &LR);		/// Return true if the index is covered by this segment.
			bool contains(SlotIndex I) const {
			return start <= I && I < end;
			}
	inline bool operator<(SlotIndex V, const LiveRange &LR) {		/// Return true if the given interval, [S, E), is covered by this seg
	return V < LR.start;		ment.
	}		bool containsInterval(SlotIndex S, SlotIndex E) const {
			assert((S < E) && "Backwards interval?");
			return (start <= S && S < end) && (start < E && E <= end);
			}
	inline bool operator<(const LiveRange &LR, SlotIndex V) {		bool operator<(const Segment &Other) const {
	return LR.start < V;		return start < Other.start || (start == Other.start && end < Other.
	}		end);
			}
			bool operator==(const Segment &Other) const {
			return start == Other.start && end == Other.end;
			}
	/// LiveInterval - This class represents some number of live ranges for a		void dump() const;
	/// register or value. This class also contains a bit of register alloca		};
	tor
	/// state.
	class LiveInterval {
	public:
	typedef SmallVector<LiveRange,4> Ranges;		typedef SmallVector<Segment,4> Segments;
	typedef SmallVector<VNInfo*,4> VNInfoList;		typedef SmallVector<VNInfo*,4> VNInfoList;
	const unsigned reg; // the register or stack slot of this interval.		Segments segments; // the liveness segments
	float weight; // weight of this interval
	Ranges ranges; // the ranges in which this register is live
	VNInfoList valnos; // value#'s		VNInfoList valnos; // value#'s
	struct InstrSlots {		typedef Segments::iterator iterator;
	enum {		iterator begin() { return segments.begin(); }
	LOAD = 0,		iterator end() { return segments.end(); }
	USE = 1,
	DEF = 2,		typedef Segments::const_iterator const_iterator;
	STORE = 3,		const_iterator begin() const { return segments.begin(); }
	NUM = 4		const_iterator end() const { return segments.end(); }
	};
	};
	LiveInterval(unsigned Reg, float Weight)
	: reg(Reg), weight(Weight) {}
	typedef Ranges::iterator iterator;
	iterator begin() { return ranges.begin(); }
	iterator end() { return ranges.end(); }
	typedef Ranges::const_iterator const_iterator;
	const_iterator begin() const { return ranges.begin(); }
	const_iterator end() const { return ranges.end(); }
	typedef VNInfoList::iterator vni_iterator;		typedef VNInfoList::iterator vni_iterator;
	vni_iterator vni_begin() { return valnos.begin(); }		vni_iterator vni_begin() { return valnos.begin(); }
	vni_iterator vni_end() { return valnos.end(); }		vni_iterator vni_end() { return valnos.end(); }
	typedef VNInfoList::const_iterator const_vni_iterator;		typedef VNInfoList::const_iterator const_vni_iterator;
	const_vni_iterator vni_begin() const { return valnos.begin(); }		const_vni_iterator vni_begin() const { return valnos.begin(); }
	const_vni_iterator vni_end() const { return valnos.end(); }		const_vni_iterator vni_end() const { return valnos.end(); }
	/// advanceTo - Advance the specified iterator to point to the LiveRang e		/// advanceTo - Advance the specified iterator to point to the Segment
	/// containing the specified position, or end() if the position is past the		/// containing the specified position, or end() if the position is past the
	/// end of the interval. If no LiveRange contains this position, but t he		/// end of the range. If no Segment contains this position, but the
	/// position is in a hole, this method returns an iterator pointing to the		/// position is in a hole, this method returns an iterator pointing to the
	/// LiveRange immediately after the hole.		/// Segment immediately after the hole.
	iterator advanceTo(iterator I, SlotIndex Pos) {		iterator advanceTo(iterator I, SlotIndex Pos) {
	assert(I != end());		assert(I != end());
	if (Pos >= endIndex())		if (Pos >= endIndex())
	return end();		return end();
	while (I->end <= Pos) ++I;		while (I->end <= Pos) ++I;
	return I;		return I;
	}		}
	/// find - Return an iterator pointing to the first range that ends aft er		/// find - Return an iterator pointing to the first segment that ends a fter
	/// Pos, or end(). This is the same as advanceTo(begin(), Pos), but fas ter		/// Pos, or end(). This is the same as advanceTo(begin(), Pos), but fas ter
	/// when searching large intervals.		/// when searching large ranges.
	///		///
	/// If Pos is contained in a LiveRange, that range is returned.		/// If Pos is contained in a Segment, that segment is returned.
	/// If Pos is in a hole, the following LiveRange is returned.		/// If Pos is in a hole, the following Segment is returned.
	/// If Pos is beyond endIndex, end() is returned.		/// If Pos is beyond endIndex, end() is returned.
	iterator find(SlotIndex Pos);		iterator find(SlotIndex Pos);
	const_iterator find(SlotIndex Pos) const {		const_iterator find(SlotIndex Pos) const {
	return const_cast<LiveInterval*>(this)->find(Pos);		return const_cast<LiveRange*>(this)->find(Pos);
	}		}
	void clear() {		void clear() {
	valnos.clear();		valnos.clear();
	ranges.clear();		segments.clear();
			}
			size_t size() const {
			return segments.size();
	}		}
	bool hasAtLeastOneValue() const { return !valnos.empty(); }		bool hasAtLeastOneValue() const { return !valnos.empty(); }
	bool containsOneValue() const { return valnos.size() == 1; }		bool containsOneValue() const { return valnos.size() == 1; }
	unsigned getNumValNums() const { return (unsigned)valnos.size(); }		unsigned getNumValNums() const { return (unsigned)valnos.size(); }
	/// getValNumInfo - Returns pointer to the specified val#.		/// getValNumInfo - Returns pointer to the specified val#.
	///		///
	inline VNInfo *getValNumInfo(unsigned ValNo) {		inline VNInfo *getValNumInfo(unsigned ValNo) {
	return valnos[ValNo];		return valnos[ValNo];
	}		}
	inline const VNInfo *getValNumInfo(unsigned ValNo) const {		inline const VNInfo *getValNumInfo(unsigned ValNo) const {
	return valnos[ValNo];		return valnos[ValNo];
	}		}
	/// containsValue - Returns true if VNI belongs to this interval.		/// containsValue - Returns true if VNI belongs to this range.
	bool containsValue(const VNInfo *VNI) const {		bool containsValue(const VNInfo *VNI) const {
	return VNI && VNI->id < getNumValNums() && VNI == getValNumInfo(VNI-> id);		return VNI && VNI->id < getNumValNums() && VNI == getValNumInfo(VNI-> id);
	}		}
	/// getNextValue - Create a new value number and return it. MIIdx spec ifies		/// getNextValue - Create a new value number and return it. MIIdx spec ifies
	/// the instruction that defines the value number.		/// the instruction that defines the value number.
	VNInfo *getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator) {		VNInfo *getNextValue(SlotIndex def, VNInfo::Allocator &VNInfoAllocator) {
	VNInfo *VNI =		VNInfo *VNI =
	new (VNInfoAllocator) VNInfo((unsigned)valnos.size(), def);		new (VNInfoAllocator) VNInfo((unsigned)valnos.size(), def);
	valnos.push_back(VNI);		valnos.push_back(VNI);
	return VNI;		return VNI;
	}		}
	/// createDeadDef - Make sure the interval has a value defined at Def.		/// createDeadDef - Make sure the range has a value defined at Def.
	/// If one already exists, return it. Otherwise allocate a new value an d		/// If one already exists, return it. Otherwise allocate a new value an d
	/// add liveness for a dead def.		/// add liveness for a dead def.
	VNInfo *createDeadDef(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator );		VNInfo *createDeadDef(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator );
	/// Create a copy of the given value. The new value will be identical e xcept		/// Create a copy of the given value. The new value will be identical e xcept
	/// for the Value number.		/// for the Value number.
	VNInfo *createValueCopy(const VNInfo *orig,		VNInfo *createValueCopy(const VNInfo *orig,
	VNInfo::Allocator &VNInfoAllocator) {		VNInfo::Allocator &VNInfoAllocator) {
	VNInfo *VNI =		VNInfo *VNI =
	new (VNInfoAllocator) VNInfo((unsigned)valnos.size(), *orig);		new (VNInfoAllocator) VNInfo((unsigned)valnos.size(), *orig);
	valnos.push_back(VNI);		valnos.push_back(VNI);
	return VNI;		return VNI;
	}		}
	/// RenumberValues - Renumber all values in order of appearance and rem ove		/// RenumberValues - Renumber all values in order of appearance and rem ove
	/// unused values.		/// unused values.
	void RenumberValues(LiveIntervals &lis);		void RenumberValues();
	/// MergeValueNumberInto - This method is called when two value nubmers		/// MergeValueNumberInto - This method is called when two value numbers
	/// are found to be equivalent. This eliminates V1, replacing all		/// are found to be equivalent. This eliminates V1, replacing all
	/// LiveRanges with the V1 value number with the V2 value number. This can		/// segments with the V1 value number with the V2 value number. This c an
	/// cause merging of V1/V2 values numbers and compaction of the value s pace.		/// cause merging of V1/V2 values numbers and compaction of the value s pace.
	VNInfo* MergeValueNumberInto(VNInfo *V1, VNInfo *V2);		VNInfo* MergeValueNumberInto(VNInfo *V1, VNInfo *V2);
	/// MergeValueInAsValue - Merge all of the live ranges of a specific va		/// Merge all of the live segments of a specific val# in RHS into this
	l#		live
	/// in RHS into this live interval as the specified value number.		/// range as the specified value number. The segments in RHS are allowe
	/// The LiveRanges in RHS are allowed to overlap with LiveRanges in the		d
	/// current interval, it will replace the value numbers of the overlape		/// to overlap with segments in the current range, it will replace the
	d		/// value numbers of the overlaped live segments with the specified val
	/// live ranges with the specified value number.		ue
	void MergeRangesInAsValue(const LiveInterval &RHS, VNInfo *LHSValNo);		/// number.
			void MergeSegmentsInAsValue(const LiveRange &RHS, VNInfo *LHSValNo);
	/// MergeValueInAsValue - Merge all of the live ranges of a specific va
	l#		/// MergeValueInAsValue - Merge all of the segments of a specific val#
	/// in RHS into this live interval as the specified value number.		/// in RHS into this live range as the specified value number.
	/// The LiveRanges in RHS are allowed to overlap with LiveRanges in the		/// The segments in RHS are allowed to overlap with segments in the
	/// current interval, but only if the overlapping LiveRanges have the		/// current range, but only if the overlapping segments have the
	/// specified value number.		/// specified value number.
	void MergeValueInAsValue(const LiveInterval &RHS,		void MergeValueInAsValue(const LiveRange &RHS,
	const VNInfo *RHSValNo, VNInfo *LHSValNo);		const VNInfo *RHSValNo, VNInfo *LHSValNo);
	bool empty() const { return ranges.empty(); }		bool empty() const { return segments.empty(); }
	/// beginIndex - Return the lowest numbered slot covered by interval.		/// beginIndex - Return the lowest numbered slot covered.
	SlotIndex beginIndex() const {		SlotIndex beginIndex() const {
	assert(!empty() && "Call to beginIndex() on empty interval.");		assert(!empty() && "Call to beginIndex() on empty range.");
	return ranges.front().start;		return segments.front().start;
	}		}
	/// endNumber - return the maximum point of the interval of the whole,		/// endNumber - return the maximum point of the range of the whole,
	/// exclusive.		/// exclusive.
	SlotIndex endIndex() const {		SlotIndex endIndex() const {
	assert(!empty() && "Call to endIndex() on empty interval.");		assert(!empty() && "Call to endIndex() on empty range.");
	return ranges.back().end;		return segments.back().end;
	}		}
	bool expiredAt(SlotIndex index) const {		bool expiredAt(SlotIndex index) const {
	return index >= endIndex();		return index >= endIndex();
	}		}
	bool liveAt(SlotIndex index) const {		bool liveAt(SlotIndex index) const {
	const_iterator r = find(index);		const_iterator r = find(index);
	return r != end() && r->start <= index;		return r != end() && r->start <= index;
	}		}
	/// killedAt - Return true if a live range ends at index. Note that the		/// Return the segment that contains the specified index, or null if th
	kill		ere
	/// point is not contained in the half-open live range. It is usually t		/// is none.
	he		const Segment *getSegmentContaining(SlotIndex Idx) const {
	/// getDefIndex() slot following its last use.		const_iterator I = FindSegmentContaining(Idx);
	bool killedAt(SlotIndex index) const {
	const_iterator r = find(index.getRegSlot(true));
	return r != end() && r->end == index;
	}
	/// getLiveRangeContaining - Return the live range that contains the
	/// specified index, or null if there is none.
	const LiveRange *getLiveRangeContaining(SlotIndex Idx) const {
	const_iterator I = FindLiveRangeContaining(Idx);
	return I == end() ? 0 : &*I;		return I == end() ? 0 : &*I;
	}		}
	/// getLiveRangeContaining - Return the live range that contains the		/// Return the live segment that contains the specified index, or null
	/// specified index, or null if there is none.		if
	LiveRange *getLiveRangeContaining(SlotIndex Idx) {		/// there is none.
	iterator I = FindLiveRangeContaining(Idx);		Segment *getSegmentContaining(SlotIndex Idx) {
			iterator I = FindSegmentContaining(Idx);
	return I == end() ? 0 : &*I;		return I == end() ? 0 : &*I;
	}		}
	/// getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.		/// getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
	VNInfo *getVNInfoAt(SlotIndex Idx) const {		VNInfo *getVNInfoAt(SlotIndex Idx) const {
	const_iterator I = FindLiveRangeContaining(Idx);		const_iterator I = FindSegmentContaining(Idx);
	return I == end() ? 0 : I->valno;		return I == end() ? 0 : I->valno;
	}		}
	/// getVNInfoBefore - Return the VNInfo that is live up to but not		/// getVNInfoBefore - Return the VNInfo that is live up to but not
	/// necessarilly including Idx, or NULL. Use this to find the reaching def		/// necessarilly including Idx, or NULL. Use this to find the reaching def
	/// used by an instruction at this SlotIndex position.		/// used by an instruction at this SlotIndex position.
	VNInfo *getVNInfoBefore(SlotIndex Idx) const {		VNInfo *getVNInfoBefore(SlotIndex Idx) const {
	const_iterator I = FindLiveRangeContaining(Idx.getPrevSlot());		const_iterator I = FindSegmentContaining(Idx.getPrevSlot());
	return I == end() ? 0 : I->valno;		return I == end() ? 0 : I->valno;
	}		}
	/// FindLiveRangeContaining - Return an iterator to the live range that		/// Return an iterator to the segment that contains the specified index
	/// contains the specified index, or end() if there is none.		, or
	iterator FindLiveRangeContaining(SlotIndex Idx) {		/// end() if there is none.
			iterator FindSegmentContaining(SlotIndex Idx) {
	iterator I = find(Idx);		iterator I = find(Idx);
	return I != end() && I->start <= Idx ? I : end();		return I != end() && I->start <= Idx ? I : end();
	}		}
	const_iterator FindLiveRangeContaining(SlotIndex Idx) const {		const_iterator FindSegmentContaining(SlotIndex Idx) const {
	const_iterator I = find(Idx);		const_iterator I = find(Idx);
	return I != end() && I->start <= Idx ? I : end();		return I != end() && I->start <= Idx ? I : end();
	}		}
	/// overlaps - Return true if the intersection of the two live interval s is		/// overlaps - Return true if the intersection of the two live ranges i s
	/// not empty.		/// not empty.
	bool overlaps(const LiveInterval& other) const {		bool overlaps(const LiveRange &other) const {
	if (other.empty())		if (other.empty())
	return false;		return false;
	return overlapsFrom(other, other.begin());		return overlapsFrom(other, other.begin());
	}		}
	/// overlaps - Return true if the two intervals have overlapping segmen ts		/// overlaps - Return true if the two ranges have overlapping segments
	/// that are not coalescable according to CP.		/// that are not coalescable according to CP.
	///		///
	/// Overlapping segments where one interval is defined by a coalescable		/// Overlapping segments where one range is defined by a coalescable
	/// copy are allowed.		/// copy are allowed.
	bool overlaps(const LiveInterval &Other, const CoalescerPair &CP,		bool overlaps(const LiveRange &Other, const CoalescerPair &CP,
	const SlotIndexes&) const;		const SlotIndexes&) const;
	/// overlaps - Return true if the live interval overlaps a range specif ied		/// overlaps - Return true if the live range overlaps an interval speci fied
	/// by [Start, End).		/// by [Start, End).
	bool overlaps(SlotIndex Start, SlotIndex End) const;		bool overlaps(SlotIndex Start, SlotIndex End) const;
	/// overlapsFrom - Return true if the intersection of the two live inte rvals		/// overlapsFrom - Return true if the intersection of the two live rang es
	/// is not empty. The specified iterator is a hint that we can begin		/// is not empty. The specified iterator is a hint that we can begin
	/// scanning the Other interval starting at I.		/// scanning the Other range starting at I.
	bool overlapsFrom(const LiveInterval& other, const_iterator I) const;		bool overlapsFrom(const LiveRange &Other, const_iterator I) const;
	/// addRange - Add the specified LiveRange to this interval, merging		/// Add the specified Segment to this range, merging segments as
	/// intervals as appropriate. This returns an iterator to the inserted		/// appropriate. This returns an iterator to the inserted segment (whi
	live		ch
	/// range (which may have grown since it was inserted.		/// may have grown since it was inserted).
	iterator addRange(LiveRange LR) {		iterator addSegment(Segment S) {
	return addRangeFrom(LR, ranges.begin());		return addSegmentFrom(S, segments.begin());
	}		}
	/// extendInBlock - If this interval is live before Kill in the basic b lock		/// extendInBlock - If this range is live before Kill in the basic bloc k
	/// that starts at StartIdx, extend it to be live up to Kill, and retur n		/// that starts at StartIdx, extend it to be live up to Kill, and retur n
	/// the value. If there is no live range before Kill, return NULL.		/// the value. If there is no segment before Kill, return NULL.
	VNInfo *extendInBlock(SlotIndex StartIdx, SlotIndex Kill);		VNInfo *extendInBlock(SlotIndex StartIdx, SlotIndex Kill);
	/// join - Join two live intervals (this, and other) together. This ap		/// join - Join two live ranges (this, and other) together. This appli
	plies		es
	/// mappings to the value numbers in the LHS/RHS intervals as specified		/// mappings to the value numbers in the LHS/RHS ranges as specified.
	. If		If
	/// the intervals are not joinable, this aborts.		/// the ranges are not joinable, this aborts.
	void join(LiveInterval &Other,		void join(LiveRange &Other,
	const int *ValNoAssignments,		const int *ValNoAssignments,
	const int *RHSValNoAssignments,		const int *RHSValNoAssignments,
	SmallVector<VNInfo*, 16> &NewVNInfo,		SmallVectorImpl<VNInfo *> &NewVNInfo);
	MachineRegisterInfo *MRI);
	/// isInOneLiveRange - Return true if the range specified is entirely i
	n the
	/// a single LiveRange of the live interval.
	bool isInOneLiveRange(SlotIndex Start, SlotIndex End) const {
	const_iterator r = find(Start);
	return r != end() && r->containsRange(Start, End);
	}
	/// True iff this live range is a single segment that lies between the		/// True iff this segment is a single segment that lies between the
	/// specified boundaries, exclusively. Vregs live across a backedge are not		/// specified boundaries, exclusively. Vregs live across a backedge are not
	/// considered local. The boundaries are expected to lie within an exte nded		/// considered local. The boundaries are expected to lie within an exte nded
	/// basic block, so vregs that are not live out should contain no holes .		/// basic block, so vregs that are not live out should contain no holes .
	bool isLocal(SlotIndex Start, SlotIndex End) const {		bool isLocal(SlotIndex Start, SlotIndex End) const {
	return beginIndex() > Start.getBaseIndex() &&		return beginIndex() > Start.getBaseIndex() &&
	endIndex() < End.getBoundaryIndex();		endIndex() < End.getBoundaryIndex();
	}		}
	/// removeRange - Remove the specified range from this interval. Note		/// Remove the specified segment from this range. Note that the segmen
	that		t
	/// the range must be a single LiveRange in its entirety.		/// must be a single Segment in its entirety.
	void removeRange(SlotIndex Start, SlotIndex End,		void removeSegment(SlotIndex Start, SlotIndex End,
	bool RemoveDeadValNo = false);		bool RemoveDeadValNo = false);
			void removeSegment(Segment S, bool RemoveDeadValNo = false) {
			removeSegment(S.start, S.end, RemoveDeadValNo);
			}
			/// Query Liveness at Idx.
			/// The sub-instruction slot of Idx doesn't matter, only the instructio
			n
			/// it refers to is considered.
			LiveQueryResult Query(SlotIndex Idx) const {
			// Find the segment that enters the instruction.
			const_iterator I = find(Idx.getBaseIndex());
			const_iterator E = end();
			if (I == E)
			return LiveQueryResult(0, 0, SlotIndex(), false);
	void removeRange(LiveRange LR, bool RemoveDeadValNo = false) {		// Is this an instruction live-in segment?
	removeRange(LR.start, LR.end, RemoveDeadValNo);		// If Idx is the start index of a basic block, include live-in segmen
			ts
			// that start at Idx.getBaseIndex().
			VNInfo *EarlyVal = 0;
			VNInfo *LateVal = 0;
			SlotIndex EndPoint;
			bool Kill = false;
			if (I->start <= Idx.getBaseIndex()) {
			EarlyVal = I->valno;
			EndPoint = I->end;
			// Move to the potentially live-out segment.
			if (SlotIndex::isSameInstr(Idx, I->end)) {
			Kill = true;
			if (++I == E)
			return LiveQueryResult(EarlyVal, LateVal, EndPoint, Kill);
			}
			// Special case: A PHIDef value can have its def in the middle of a
			// segment if the value happens to be live out of the layout
			// predecessor.
			// Such a value is not live-in.
			if (EarlyVal->def == Idx.getBaseIndex())
			EarlyVal = 0;
			}
			// I now points to the segment that may be live-through, or defined b
			y
			// this instr. Ignore segments starting after the current instr.
			if (!SlotIndex::isEarlierInstr(Idx, I->start)) {
			LateVal = I->valno;
			EndPoint = I->end;
			}
			return LiveQueryResult(EarlyVal, LateVal, EndPoint, Kill);
	}		}
	/// removeValNo - Remove all the ranges defined by the specified value# .		/// removeValNo - Remove all the segments defined by the specified valu e#.
	/// Also remove the value# from value# list.		/// Also remove the value# from value# list.
	void removeValNo(VNInfo *ValNo);		void removeValNo(VNInfo *ValNo);
	/// getSize - Returns the sum of sizes of all the LiveRange's.		/// Returns true if the live range is zero length, i.e. no live segment
	///		s
	unsigned getSize() const;		/// span instructions. It doesn't pay to spill such a range.
	/// Returns true if the live interval is zero length, i.e. no live rang
	es
	/// span instructions. It doesn't pay to spill such an interval.
	bool isZeroLength(SlotIndexes *Indexes) const {		bool isZeroLength(SlotIndexes *Indexes) const {
	for (const_iterator i = begin(), e = end(); i != e; ++i)		for (const_iterator i = begin(), e = end(); i != e; ++i)
	if (Indexes->getNextNonNullIndex(i->start).getBaseIndex() <		if (Indexes->getNextNonNullIndex(i->start).getBaseIndex() <
	i->end.getBaseIndex())		i->end.getBaseIndex())
	return false;		return false;
	return true;		return true;
	}		}
	/// isSpillable - Can this interval be spilled?		bool operator<(const LiveRange& other) const {
	bool isSpillable() const {
	return weight != HUGE_VALF;
	}
	/// markNotSpillable - Mark interval as not spillable
	void markNotSpillable() {
	weight = HUGE_VALF;
	}
	bool operator<(const LiveInterval& other) const {
	const SlotIndex &thisIndex = beginIndex();		const SlotIndex &thisIndex = beginIndex();
	const SlotIndex &otherIndex = other.beginIndex();		const SlotIndex &otherIndex = other.beginIndex();
	return (thisIndex < otherIndex ||		return thisIndex < otherIndex;
	(thisIndex == otherIndex && reg < other.reg));
	}		}
	void print(raw_ostream &OS) const;		void print(raw_ostream &OS) const;
	void dump() const;		void dump() const;
	/// \brief Walk the interval and assert if any invariants fail to hold.		/// \brief Walk the range and assert if any invariants fail to hold.
	///		///
	/// Note that this is a no-op when asserts are disabled.		/// Note that this is a no-op when asserts are disabled.
	#ifdef NDEBUG		#ifdef NDEBUG
	void verify() const {}		void verify() const {}
	#else		#else
	void verify() const;		void verify() const;
	#endif		#endif
	private:		private:
	Ranges::iterator addRangeFrom(LiveRange LR, Ranges::iterator From);		iterator addSegmentFrom(Segment S, iterator From);
	void extendIntervalEndTo(Ranges::iterator I, SlotIndex NewEnd);		void extendSegmentEndTo(iterator I, SlotIndex NewEnd);
	Ranges::iterator extendIntervalStartTo(Ranges::iterator I, SlotIndex Ne		iterator extendSegmentStartTo(iterator I, SlotIndex NewStr);
	wStr);
	void markValNoForDeletion(VNInfo *V);		void markValNoForDeletion(VNInfo *V);
			};
			inline raw_ostream &operator<<(raw_ostream &OS, const LiveRange &LR) {
			LR.print(OS);
			return OS;
			}
			/// LiveInterval - This class represents the liveness of a register,
			/// or stack slot.
			class LiveInterval : public LiveRange {
			public:
			typedef LiveRange super;
			const unsigned reg; // the register or stack slot of this interval.
			float weight; // weight of this interval
			LiveInterval(unsigned Reg, float Weight)
			: reg(Reg), weight(Weight) {}
			/// getSize - Returns the sum of sizes of all the LiveRange's.
			///
			unsigned getSize() const;
			/// isSpillable - Can this interval be spilled?
			bool isSpillable() const {
			return weight != llvm::huge_valf;
			}
			/// markNotSpillable - Mark interval as not spillable
			void markNotSpillable() {
			weight = llvm::huge_valf;
			}
			bool operator<(const LiveInterval& other) const {
			const SlotIndex &thisIndex = beginIndex();
			const SlotIndex &otherIndex = other.beginIndex();
			return thisIndex < otherIndex ||
			(thisIndex == otherIndex && reg < other.reg);
			}
			void print(raw_ostream &OS) const;
			void dump() const;
			private:
	LiveInterval& operator=(const LiveInterval& rhs) LLVM_DELETED_FUNCTION;		LiveInterval& operator=(const LiveInterval& rhs) LLVM_DELETED_FUNCTION;
	};		};
	inline raw_ostream &operator<<(raw_ostream &OS, const LiveInterval &LI) {		inline raw_ostream &operator<<(raw_ostream &OS, const LiveInterval &LI) {
	LI.print(OS);		LI.print(OS);
	return OS;		return OS;
	}		}
	/// Helper class for performant LiveInterval bulk updates.		raw_ostream &operator<<(raw_ostream &OS, const LiveRange::Segment &S);
			inline bool operator<(SlotIndex V, const LiveRange::Segment &S) {
			return V < S.start;
			}
			inline bool operator<(const LiveRange::Segment &S, SlotIndex V) {
			return S.start < V;
			}
			/// Helper class for performant LiveRange bulk updates.
	///		///
	/// Calling LiveInterval::addRange() repeatedly can be expensive on large		/// Calling LiveRange::addSegment() repeatedly can be expensive on large
	/// live ranges because segments after the insertion point may need to be		/// live ranges because segments after the insertion point may need to be
	/// shifted. The LiveRangeUpdater class can defer the shifting when addin g		/// shifted. The LiveRangeUpdater class can defer the shifting when addin g
	/// many segments in order.		/// many segments in order.
	///		///
	/// The LiveInterval will be in an invalid state until flush() is called.		/// The LiveRange will be in an invalid state until flush() is called.
	class LiveRangeUpdater {		class LiveRangeUpdater {
	LiveInterval *LI;		LiveRange *LR;
	SlotIndex LastStart;		SlotIndex LastStart;
	LiveInterval::iterator WriteI;		LiveRange::iterator WriteI;
	LiveInterval::iterator ReadI;		LiveRange::iterator ReadI;
	SmallVector<LiveRange, 16> Spills;		SmallVector<LiveRange::Segment, 16> Spills;
	void mergeSpills();		void mergeSpills();
	public:		public:
	/// Create a LiveRangeUpdater for adding segments to LI.		/// Create a LiveRangeUpdater for adding segments to LR.
	/// LI will temporarily be in an invalid state until flush() is called.		/// LR will temporarily be in an invalid state until flush() is called.
	LiveRangeUpdater(LiveInterval *li = 0) : LI(li) {}		LiveRangeUpdater(LiveRange *lr = 0) : LR(lr) {}
	~LiveRangeUpdater() { flush(); }		~LiveRangeUpdater() { flush(); }
	/// Add a segment to LI and coalesce when possible, just like LI.addRan		/// Add a segment to LR and coalesce when possible, just like
	ge().		/// LR.addSegment(). Segments should be added in increasing start order
	/// Segments should be added in increasing start order for best perform		for
	ance.		/// best performance.
	void add(LiveRange);		void add(LiveRange::Segment);
	void add(SlotIndex Start, SlotIndex End, VNInfo *VNI) {		void add(SlotIndex Start, SlotIndex End, VNInfo *VNI) {
	add(LiveRange(Start, End, VNI));		add(LiveRange::Segment(Start, End, VNI));
	}		}
	/// Return true if the LI is currently in an invalid state, and flush()		/// Return true if the LR is currently in an invalid state, and flush()
	/// needs to be called.		/// needs to be called.
	bool isDirty() const { return LastStart.isValid(); }		bool isDirty() const { return LastStart.isValid(); }
	/// Flush the updater state to LI so it is valid and contains all added		/// Flush the updater state to LR so it is valid and contains all added
	/// segments.		/// segments.
	void flush();		void flush();
	/// Select a different destination live range.		/// Select a different destination live range.
	void setDest(LiveInterval *li) {		void setDest(LiveRange *lr) {
	if (LI != li && isDirty())		if (LR != lr && isDirty())
	flush();		flush();
	LI = li;		LR = lr;
	}		}
	/// Get the current destination live range.		/// Get the current destination live range.
	LiveInterval *getDest() const { return LI; }		LiveRange *getDest() const { return LR; }
	void dump() const;		void dump() const;
	void print(raw_ostream&) const;		void print(raw_ostream&) const;
	};		};
	inline raw_ostream &operator<<(raw_ostream &OS, const LiveRangeUpdater &X ) {		inline raw_ostream &operator<<(raw_ostream &OS, const LiveRangeUpdater &X ) {
	X.print(OS);		X.print(OS);
	return OS;		return OS;
	}		}
	/// LiveRangeQuery - Query information about a live range around a given
	/// instruction. This class hides the implementation details of live rang
	es,
	/// and it should be used as the primary interface for examining live ran
	ges
	/// around instructions.
	///
	class LiveRangeQuery {
	VNInfo *EarlyVal;
	VNInfo *LateVal;
	SlotIndex EndPoint;
	bool Kill;
	public:
	/// Create a LiveRangeQuery for the given live range and instruction in
	dex.
	/// The sub-instruction slot of Idx doesn't matter, only the instructio
	n it
	/// refers to is considered.
	LiveRangeQuery(const LiveInterval &LI, SlotIndex Idx)
	: EarlyVal(0), LateVal(0), Kill(false) {
	// Find the segment that enters the instruction.
	LiveInterval::const_iterator I = LI.find(Idx.getBaseIndex());
	LiveInterval::const_iterator E = LI.end();
	if (I == E)
	return;
	// Is this an instruction live-in segment?
	// If Idx is the start index of a basic block, include live-in segmen
	ts
	// that start at Idx.getBaseIndex().
	if (I->start <= Idx.getBaseIndex()) {
	EarlyVal = I->valno;
	EndPoint = I->end;
	// Move to the potentially live-out segment.
	if (SlotIndex::isSameInstr(Idx, I->end)) {
	Kill = true;
	if (++I == E)
	return;
	}
	// Special case: A PHIDef value can have its def in the middle of a
	// segment if the value happens to be live out of the layout
	// predecessor.
	// Such a value is not live-in.
	if (EarlyVal->def == Idx.getBaseIndex())
	EarlyVal = 0;
	}
	// I now points to the segment that may be live-through, or defined b
	y
	// this instr. Ignore segments starting after the current instr.
	if (SlotIndex::isEarlierInstr(Idx, I->start))
	return;
	LateVal = I->valno;
	EndPoint = I->end;
	}
	/// Return the value that is live-in to the instruction. This is the va
	lue
	/// that will be read by the instruction's use operands. Return NULL if
	no
	/// value is live-in.
	VNInfo *valueIn() const {
	return EarlyVal;
	}
	/// Return true if the live-in value is killed by this instruction. Thi
	s
	/// means that either the live range ends at the instruction, or it cha
	nges
	/// value.
	bool isKill() const {
	return Kill;
	}
	/// Return true if this instruction has a dead def.
	bool isDeadDef() const {
	return EndPoint.isDead();
	}
	/// Return the value leaving the instruction, if any. This can be a
	/// live-through value, or a live def. A dead def returns NULL.
	VNInfo *valueOut() const {
	return isDeadDef() ? 0 : LateVal;
	}
	/// Return the value defined by this instruction, if any. This includes
	/// dead defs, it is the value created by the instruction's def operand
	s.
	VNInfo *valueDefined() const {
	return EarlyVal == LateVal ? 0 : LateVal;
	}
	/// Return the end point of the last live range segment to interact wit
	h
	/// the instruction, if any.
	///
	/// The end point is an invalid SlotIndex only if the live range doesn'
	t
	/// intersect the instruction at all.
	///
	/// The end point may be at or past the end of the instruction's basic
	/// block. That means the value was live out of the block.
	SlotIndex endPoint() const {
	return EndPoint;
	}
	};
	/// ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a		/// ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a
	/// LiveInterval into equivalence clases of connected components. A		/// LiveInterval into equivalence clases of connected components. A
	/// LiveInterval that has multiple connected components can be broken int o		/// LiveInterval that has multiple connected components can be broken int o
	/// multiple LiveIntervals.		/// multiple LiveIntervals.
	///		///
	/// Given a LiveInterval that may have multiple connected components, run :		/// Given a LiveInterval that may have multiple connected components, run :
	///		///
	/// unsigned numComps = ConEQ.Classify(LI);		/// unsigned numComps = ConEQ.Classify(LI);
	/// if (numComps > 1) {		/// if (numComps > 1) {
	/// // allocate numComps-1 new LiveIntervals into LIS[1..]		/// // allocate numComps-1 new LiveIntervals into LIS[1..]
End of changes. 83 change blocks.
	334 lines changed or deleted		340 lines changed or added

	LiveIntervalAnalysis.h		LiveIntervalAnalysis.h
	skipping to change at line 38		skipping to change at line 38
	#include "llvm/CodeGen/SlotIndexes.h"		#include "llvm/CodeGen/SlotIndexes.h"
	#include "llvm/Support/Allocator.h"		#include "llvm/Support/Allocator.h"
	#include "llvm/Target/TargetRegisterInfo.h"		#include "llvm/Target/TargetRegisterInfo.h"
	#include <cmath>		#include <cmath>
	#include <iterator>		#include <iterator>
	namespace llvm {		namespace llvm {
	class AliasAnalysis;		class AliasAnalysis;
	class BitVector;		class BitVector;
			class BlockFrequency;
	class LiveRangeCalc;		class LiveRangeCalc;
	class LiveVariables;		class LiveVariables;
	class MachineDominatorTree;		class MachineDominatorTree;
	class MachineLoopInfo;		class MachineLoopInfo;
	class TargetRegisterInfo;		class TargetRegisterInfo;
	class MachineRegisterInfo;		class MachineRegisterInfo;
	class TargetInstrInfo;		class TargetInstrInfo;
	class TargetRegisterClass;		class TargetRegisterClass;
	class VirtRegMap;		class VirtRegMap;
	skipping to change at line 92		skipping to change at line 93
	/// Also see the comment in LiveInterval::find().		/// Also see the comment in LiveInterval::find().
	SmallVector<const uint32_t*, 8> RegMaskBits;		SmallVector<const uint32_t*, 8> RegMaskBits;
	/// For each basic block number, keep (begin, size) pairs indexing into the		/// For each basic block number, keep (begin, size) pairs indexing into the
	/// RegMaskSlots and RegMaskBits arrays.		/// RegMaskSlots and RegMaskBits arrays.
	/// Note that basic block numbers may not be layout contiguous, that's why		/// Note that basic block numbers may not be layout contiguous, that's why
	/// we can't just keep track of the first register mask in each basic		/// we can't just keep track of the first register mask in each basic
	/// block.		/// block.
	SmallVector<std::pair<unsigned, unsigned>, 8> RegMaskBlocks;		SmallVector<std::pair<unsigned, unsigned>, 8> RegMaskBlocks;
	/// RegUnitIntervals - Keep a live interval for each register unit as a		/// Keeps a live range set for each register unit to track fixed physre
	way		g
	/// of tracking fixed physreg interference.		/// interference.
	SmallVector<LiveInterval*, 0> RegUnitIntervals;		SmallVector<LiveRange*, 0> RegUnitRanges;
	public:		public:
	static char ID; // Pass identification, replacement for typeid		static char ID; // Pass identification, replacement for typeid
	LiveIntervals();		LiveIntervals();
	virtual ~LiveIntervals();		virtual ~LiveIntervals();
	// Calculate the spill weight to assign to a single instruction.		// Calculate the spill weight to assign to a single instruction.
	static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) ;		static float getSpillWeight(bool isDef, bool isUse, BlockFrequency freq );
	LiveInterval &getInterval(unsigned Reg) {		LiveInterval &getInterval(unsigned Reg) {
	LiveInterval *LI = VirtRegIntervals[Reg];		if (hasInterval(Reg))
	assert(LI && "Interval does not exist for virtual register");		return *VirtRegIntervals[Reg];
	return *LI;		else
			return createAndComputeVirtRegInterval(Reg);
	}		}
	const LiveInterval &getInterval(unsigned Reg) const {		const LiveInterval &getInterval(unsigned Reg) const {
	return const_cast<LiveIntervals*>(this)->getInterval(Reg);		return const_cast<LiveIntervals*>(this)->getInterval(Reg);
	}		}
	bool hasInterval(unsigned Reg) const {		bool hasInterval(unsigned Reg) const {
	return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg];		return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg];
	}		}
	// Interval creation.		// Interval creation.
	LiveInterval &getOrCreateInterval(unsigned Reg) {		LiveInterval &createEmptyInterval(unsigned Reg) {
	if (!hasInterval(Reg)) {		assert(!hasInterval(Reg) && "Interval already exists!");
	VirtRegIntervals.grow(Reg);		VirtRegIntervals.grow(Reg);
	VirtRegIntervals[Reg] = createInterval(Reg);		VirtRegIntervals[Reg] = createInterval(Reg);
	}		return *VirtRegIntervals[Reg];
	return getInterval(Reg);		}
			LiveInterval &createAndComputeVirtRegInterval(unsigned Reg) {
			LiveInterval &LI = createEmptyInterval(Reg);
			computeVirtRegInterval(LI);
			return LI;
	}		}
	// Interval removal.		// Interval removal.
	void removeInterval(unsigned Reg) {		void removeInterval(unsigned Reg) {
	delete VirtRegIntervals[Reg];		delete VirtRegIntervals[Reg];
	VirtRegIntervals[Reg] = 0;		VirtRegIntervals[Reg] = 0;
	}		}
	/// addLiveRangeToEndOfBlock - Given a register and an instruction,		/// Given a register and an instruction, adds a live segment from that
	/// adds a live range from that instruction to the end of its MBB.		/// instruction to the end of its MBB.
	LiveRange addLiveRangeToEndOfBlock(unsigned reg,		LiveInterval::Segment addSegmentToEndOfBlock(unsigned reg,
	MachineInstr* startInst);		MachineInstr* startInst);
	/// shrinkToUses - After removing some uses of a register, shrink its l ive		/// shrinkToUses - After removing some uses of a register, shrink its l ive
	/// range to just the remaining uses. This method does not compute reac hing		/// range to just the remaining uses. This method does not compute reac hing
	/// defs for new uses, and it doesn't remove dead defs.		/// defs for new uses, and it doesn't remove dead defs.
	/// Dead PHIDef values are marked as unused.		/// Dead PHIDef values are marked as unused.
	/// New dead machine instructions are added to the dead vector.		/// New dead machine instructions are added to the dead vector.
	/// Return true if the interval may have been separated into multiple		/// Return true if the interval may have been separated into multiple
	/// connected components.		/// connected components.
	bool shrinkToUses(LiveInterval *li,		bool shrinkToUses(LiveInterval *li,
	SmallVectorImpl<MachineInstr*> *dead = 0);		SmallVectorImpl<MachineInstr*> *dead = 0);
	/// extendToIndices - Extend the live range of LI to reach all points i n		/// extendToIndices - Extend the live range of LI to reach all points i n
	/// Indices. The points in the Indices array must be jointly dominated by		/// Indices. The points in the Indices array must be jointly dominated by
	/// existing defs in LI. PHI-defs are added as needed to maintain SSA f orm.		/// existing defs in LI. PHI-defs are added as needed to maintain SSA f orm.
	///		///
	/// If a SlotIndex in Indices is the end index of a basic block, LI wil l be		/// If a SlotIndex in Indices is the end index of a basic block, LI wil l be
	/// extended to be live out of the basic block.		/// extended to be live out of the basic block.
	///		///
	/// See also LiveRangeCalc::extend().		/// See also LiveRangeCalc::extend().
	void extendToIndices(LiveInterval *LI, ArrayRef<SlotIndex> Indices);		void extendToIndices(LiveRange &LR, ArrayRef<SlotIndex> Indices);
	/// pruneValue - If an LI value is live at Kill, prune its live range b y		/// pruneValue - If an LI value is live at Kill, prune its live range b y
	/// removing any liveness reachable from Kill. Add live range end point s to		/// removing any liveness reachable from Kill. Add live range end point s to
	/// EndPoints such that extendToIndices(LI, EndPoints) will reconstruct the		/// EndPoints such that extendToIndices(LI, EndPoints) will reconstruct the
	/// value's live range.		/// value's live range.
	///		///
	/// Calling pruneValue() and extendToIndices() can be used to reconstru ct		/// Calling pruneValue() and extendToIndices() can be used to reconstru ct
	/// SSA form after adding defs to a virtual register.		/// SSA form after adding defs to a virtual register.
	void pruneValue(LiveInterval *LI, SlotIndex Kill,		void pruneValue(LiveInterval *LI, SlotIndex Kill,
	SmallVectorImpl<SlotIndex> *EndPoints);		SmallVectorImpl<SlotIndex> *EndPoints);
	skipping to change at line 202		skipping to change at line 209
	/// Return the first index in the given basic block.		/// Return the first index in the given basic block.
	SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {		SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
	return Indexes->getMBBStartIdx(mbb);		return Indexes->getMBBStartIdx(mbb);
	}		}
	/// Return the last index in the given basic block.		/// Return the last index in the given basic block.
	SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {		SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
	return Indexes->getMBBEndIdx(mbb);		return Indexes->getMBBEndIdx(mbb);
	}		}
	bool isLiveInToMBB(const LiveInterval &li,		bool isLiveInToMBB(const LiveRange &LR,
	const MachineBasicBlock *mbb) const {		const MachineBasicBlock *mbb) const {
	return li.liveAt(getMBBStartIdx(mbb));		return LR.liveAt(getMBBStartIdx(mbb));
	}		}
	bool isLiveOutOfMBB(const LiveInterval &li,		bool isLiveOutOfMBB(const LiveRange &LR,
	const MachineBasicBlock *mbb) const {		const MachineBasicBlock *mbb) const {
	return li.liveAt(getMBBEndIdx(mbb).getPrevSlot());		return LR.liveAt(getMBBEndIdx(mbb).getPrevSlot());
	}		}
	MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {		MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
	return Indexes->getMBBFromIndex(index);		return Indexes->getMBBFromIndex(index);
	}		}
	void insertMBBInMaps(MachineBasicBlock *MBB) {		void insertMBBInMaps(MachineBasicBlock *MBB) {
	Indexes->insertMBBInMaps(MBB);		Indexes->insertMBBInMaps(MBB);
	assert(unsigned(MBB->getNumber()) == RegMaskBlocks.size() &&		assert(unsigned(MBB->getNumber()) == RegMaskBlocks.size() &&
	"Blocks must be added in order.");		"Blocks must be added in order.");
	RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0));		RegMaskBlocks.push_back(std::make_pair(RegMaskSlots.size(), 0));
	}		}
	SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {		SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {
	return Indexes->insertMachineInstrInMaps(MI);		return Indexes->insertMachineInstrInMaps(MI);
	}		}
			void InsertMachineInstrRangeInMaps(MachineBasicBlock::iterator B,
			MachineBasicBlock::iterator E) {
			for (MachineBasicBlock::iterator I = B; I != E; ++I)
			Indexes->insertMachineInstrInMaps(I);
			}
	void RemoveMachineInstrFromMaps(MachineInstr *MI) {		void RemoveMachineInstrFromMaps(MachineInstr *MI) {
	Indexes->removeMachineInstrFromMaps(MI);		Indexes->removeMachineInstrFromMaps(MI);
	}		}
	void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {		void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
	Indexes->replaceMachineInstrInMaps(MI, NewMI);		Indexes->replaceMachineInstrInMaps(MI, NewMI);
	}		}
	bool findLiveInMBBs(SlotIndex Start, SlotIndex End,		bool findLiveInMBBs(SlotIndex Start, SlotIndex End,
	SmallVectorImpl<MachineBasicBlock*> &MBBs) const {		SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
	skipping to change at line 354		skipping to change at line 367
	// instead of virtual registers. This typically happens when passing		// instead of virtual registers. This typically happens when passing
	// arguments to a function call, or when instructions require operands in		// arguments to a function call, or when instructions require operands in
	// fixed registers.		// fixed registers.
	//		//
	// Each physreg has one or more register units, see MCRegisterInfo. We		// Each physreg has one or more register units, see MCRegisterInfo. We
	// track liveness per register unit to handle aliasing registers more		// track liveness per register unit to handle aliasing registers more
	// efficiently.		// efficiently.
	/// getRegUnit - Return the live range for Unit.		/// getRegUnit - Return the live range for Unit.
	/// It will be computed if it doesn't exist.		/// It will be computed if it doesn't exist.
	LiveInterval &getRegUnit(unsigned Unit) {		LiveRange &getRegUnit(unsigned Unit) {
	LiveInterval *LI = RegUnitIntervals[Unit];		LiveRange *LR = RegUnitRanges[Unit];
	if (!LI) {		if (!LR) {
	// Compute missing ranges on demand.		// Compute missing ranges on demand.
	RegUnitIntervals[Unit] = LI = new LiveInterval(Unit, HUGE_VALF);		RegUnitRanges[Unit] = LR = new LiveRange();
	computeRegUnitInterval(LI);		computeRegUnitRange(*LR, Unit);
	}		}
	return *LI;		return *LR;
	}		}
	/// getCachedRegUnit - Return the live range for Unit if it has already		/// getCachedRegUnit - Return the live range for Unit if it has already
	/// been computed, or NULL if it hasn't been computed yet.		/// been computed, or NULL if it hasn't been computed yet.
	LiveInterval *getCachedRegUnit(unsigned Unit) {		LiveRange *getCachedRegUnit(unsigned Unit) {
	return RegUnitIntervals[Unit];		return RegUnitRanges[Unit];
	}		}
	const LiveInterval *getCachedRegUnit(unsigned Unit) const {		const LiveRange *getCachedRegUnit(unsigned Unit) const {
	return RegUnitIntervals[Unit];		return RegUnitRanges[Unit];
	}		}
	private:		private:
	/// Compute live intervals for all virtual registers.		/// Compute live intervals for all virtual registers.
	void computeVirtRegs();		void computeVirtRegs();
	/// Compute RegMaskSlots and RegMaskBits.		/// Compute RegMaskSlots and RegMaskBits.
	void computeRegMasks();		void computeRegMasks();
	static LiveInterval* createInterval(unsigned Reg);		static LiveInterval* createInterval(unsigned Reg);
	void printInstrs(raw_ostream &O) const;		void printInstrs(raw_ostream &O) const;
	void dumpInstrs() const;		void dumpInstrs() const;
	void computeLiveInRegUnits();		void computeLiveInRegUnits();
	void computeRegUnitInterval(LiveInterval*);		void computeRegUnitRange(LiveRange&, unsigned Unit);
	void computeVirtRegInterval(LiveInterval*);		void computeVirtRegInterval(LiveInterval&);
	class HMEditor;		class HMEditor;
	};		};
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 18 change blocks.
	35 lines changed or deleted		48 lines changed or added

	LiveIntervalUnion.h		LiveIntervalUnion.h
	skipping to change at line 35		skipping to change at line 35
	class TargetRegisterInfo;		class TargetRegisterInfo;
	#ifndef NDEBUG		#ifndef NDEBUG
	// forward declaration		// forward declaration
	template <unsigned Element> class SparseBitVector;		template <unsigned Element> class SparseBitVector;
	typedef SparseBitVector<128> LiveVirtRegBitSet;		typedef SparseBitVector<128> LiveVirtRegBitSet;
	#endif		#endif
	/// Compare a live virtual register segment to a LiveIntervalUnion segment.		/// Compare a live virtual register segment to a LiveIntervalUnion segment.
	inline bool		inline bool
	overlap(const LiveRange &VRSeg,		overlap(const LiveInterval::Segment &VRSeg,
	const IntervalMap<SlotIndex, LiveInterval*>::const_iterator &LUSeg) {		const IntervalMap<SlotIndex, LiveInterval*>::const_iterator &LUSeg) {
	return VRSeg.start < LUSeg.stop() && LUSeg.start() < VRSeg.end;		return VRSeg.start < LUSeg.stop() && LUSeg.start() < VRSeg.end;
	}		}
	/// Union of live intervals that are strong candidates for coalescing into a		/// Union of live intervals that are strong candidates for coalescing into a
	/// single register (either physical or virtual depending on the context). We		/// single register (either physical or virtual depending on the context). We
	/// expect the constituent live intervals to be disjoint, although we may		/// expect the constituent live intervals to be disjoint, although we may
	/// eventually make exceptions to handle value-based interference.		/// eventually make exceptions to handle value-based interference.
	class LiveIntervalUnion {		class LiveIntervalUnion {
	// A set of live virtual register segments that supports fast insertion,		// A set of live virtual register segments that supports fast insertion,
End of changes. 1 change blocks.
	1 lines changed or deleted		1 lines changed or added

	LiveRangeEdit.h		LiveRangeEdit.h
	skipping to change at line 22		skipping to change at line 22
	//		//
	// The parent register is never changed. Instead, a number of new virtual		// The parent register is never changed. Instead, a number of new virtual
	// registers are created and added to the newRegs vector.		// registers are created and added to the newRegs vector.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_CODEGEN_LIVERANGEEDIT_H		#ifndef LLVM_CODEGEN_LIVERANGEEDIT_H
	#define LLVM_CODEGEN_LIVERANGEEDIT_H		#define LLVM_CODEGEN_LIVERANGEEDIT_H
	#include "llvm/ADT/ArrayRef.h"		#include "llvm/ADT/ArrayRef.h"
			#include "llvm/ADT/SetVector.h"
	#include "llvm/ADT/SmallPtrSet.h"		#include "llvm/ADT/SmallPtrSet.h"
	#include "llvm/CodeGen/LiveInterval.h"		#include "llvm/CodeGen/LiveInterval.h"
			#include "llvm/CodeGen/MachineRegisterInfo.h"
	#include "llvm/Target/TargetMachine.h"		#include "llvm/Target/TargetMachine.h"
	namespace llvm {		namespace llvm {
	class AliasAnalysis;		class AliasAnalysis;
	class LiveIntervals;		class LiveIntervals;
			class MachineBlockFrequencyInfo;
	class MachineLoopInfo;		class MachineLoopInfo;
	class MachineRegisterInfo;
	class VirtRegMap;		class VirtRegMap;
	class LiveRangeEdit {		class LiveRangeEdit : private MachineRegisterInfo::Delegate {
	public:		public:
	/// Callback methods for LiveRangeEdit owners.		/// Callback methods for LiveRangeEdit owners.
	class Delegate {		class Delegate {
	virtual void anchor();		virtual void anchor();
	public:		public:
	/// Called immediately before erasing a dead machine instruction.		/// Called immediately before erasing a dead machine instruction.
	virtual void LRE_WillEraseInstruction(MachineInstr *MI) {}		virtual void LRE_WillEraseInstruction(MachineInstr *MI) {}
	/// Called when a virtual register is no longer used. Return false to d efer		/// Called when a virtual register is no longer used. Return false to d efer
	/// its deletion from LiveIntervals.		/// its deletion from LiveIntervals.
	skipping to change at line 59		skipping to change at line 61
	/// Called after cloning a virtual register.		/// Called after cloning a virtual register.
	/// This is used for new registers representing connected components of Old.		/// This is used for new registers representing connected components of Old.
	virtual void LRE_DidCloneVirtReg(unsigned New, unsigned Old) {}		virtual void LRE_DidCloneVirtReg(unsigned New, unsigned Old) {}
	virtual ~Delegate() {}		virtual ~Delegate() {}
	};		};
	private:		private:
	LiveInterval *Parent;		LiveInterval *Parent;
	SmallVectorImpl<LiveInterval*> &NewRegs;		SmallVectorImpl<unsigned> &NewRegs;
	MachineRegisterInfo &MRI;		MachineRegisterInfo &MRI;
	LiveIntervals &LIS;		LiveIntervals &LIS;
	VirtRegMap *VRM;		VirtRegMap *VRM;
	const TargetInstrInfo &TII;		const TargetInstrInfo &TII;
	Delegate *const TheDelegate;		Delegate *const TheDelegate;
	/// FirstNew - Index of the first register added to NewRegs.		/// FirstNew - Index of the first register added to NewRegs.
	const unsigned FirstNew;		const unsigned FirstNew;
	/// ScannedRemattable - true when remattable values have been identified.		/// ScannedRemattable - true when remattable values have been identified.
	skipping to change at line 92		skipping to change at line 94
	/// allUsesAvailableAt - Return true if all registers used by OrigMI at		/// allUsesAvailableAt - Return true if all registers used by OrigMI at
	/// OrigIdx are also available with the same value at UseIdx.		/// OrigIdx are also available with the same value at UseIdx.
	bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,		bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
	SlotIndex UseIdx) const;		SlotIndex UseIdx) const;
	/// foldAsLoad - If LI has a single use and a single def that can be fold ed as		/// foldAsLoad - If LI has a single use and a single def that can be fold ed as
	/// a load, eliminate the register by folding the def into the use.		/// a load, eliminate the register by folding the def into the use.
	bool foldAsLoad(LiveInterval *LI, SmallVectorImpl<MachineInstr*> &Dead);		bool foldAsLoad(LiveInterval *LI, SmallVectorImpl<MachineInstr*> &Dead);
			typedef SetVector<LiveInterval*,
			SmallVector<LiveInterval*, 8>,
			SmallPtrSet<LiveInterval*, 8> > ToShrinkSet;
			/// Helper for eliminateDeadDefs.
			void eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink);
			/// MachineRegisterInfo callback to notify when new virtual
			/// registers are created.
			void MRI_NoteNewVirtualRegister(unsigned VReg);
	public:		public:
	/// Create a LiveRangeEdit for breaking down parent into smaller pieces.		/// Create a LiveRangeEdit for breaking down parent into smaller pieces.
	/// @param parent The register being spilled or split.		/// @param parent The register being spilled or split.
	/// @param newRegs List to receive any new registers created. This needn' t be		/// @param newRegs List to receive any new registers created. This needn' t be
	/// empty initially, any existing registers are ignored.		/// empty initially, any existing registers are ignored.
	/// @param MF The MachineFunction the live range edit is taking place in.		/// @param MF The MachineFunction the live range edit is taking place in.
	/// @param lis The collection of all live intervals in this function.		/// @param lis The collection of all live intervals in this function.
	/// @param vrm Map of virtual registers to physical registers for this		/// @param vrm Map of virtual registers to physical registers for this
	/// function. If NULL, no virtual register map updates will		/// function. If NULL, no virtual register map updates will
	/// be done. This could be the case if called before Regalloc .		/// be done. This could be the case if called before Regalloc .
	LiveRangeEdit(LiveInterval *parent,		LiveRangeEdit(LiveInterval *parent,
	SmallVectorImpl<LiveInterval*> &newRegs,		SmallVectorImpl<unsigned> &newRegs,
	MachineFunction &MF,		MachineFunction &MF,
	LiveIntervals &lis,		LiveIntervals &lis,
	VirtRegMap *vrm,		VirtRegMap *vrm,
	Delegate *delegate = 0)		Delegate *delegate = 0)
	: Parent(parent), NewRegs(newRegs),		: Parent(parent), NewRegs(newRegs),
	MRI(MF.getRegInfo()), LIS(lis), VRM(vrm),		MRI(MF.getRegInfo()), LIS(lis), VRM(vrm),
	TII(*MF.getTarget().getInstrInfo()),		TII(*MF.getTarget().getInstrInfo()),
	TheDelegate(delegate),		TheDelegate(delegate),
	FirstNew(newRegs.size()),		FirstNew(newRegs.size()),
	ScannedRemattable(false) {}		ScannedRemattable(false) { MRI.setDelegate(this); }
			~LiveRangeEdit() { MRI.resetDelegate(this); }
	LiveInterval &getParent() const {		LiveInterval &getParent() const {
	assert(Parent && "No parent LiveInterval");		assert(Parent && "No parent LiveInterval");
	return *Parent;		return *Parent;
	}		}
	unsigned getReg() const { return getParent().reg; }		unsigned getReg() const { return getParent().reg; }
	/// Iterator for accessing the new registers added by this edit.		/// Iterator for accessing the new registers added by this edit.
	typedef SmallVectorImpl<LiveInterval*>::const_iterator iterator;		typedef SmallVectorImpl<unsigned>::const_iterator iterator;
	iterator begin() const { return NewRegs.begin()+FirstNew; }		iterator begin() const { return NewRegs.begin()+FirstNew; }
	iterator end() const { return NewRegs.end(); }		iterator end() const { return NewRegs.end(); }
	unsigned size() const { return NewRegs.size()-FirstNew; }		unsigned size() const { return NewRegs.size()-FirstNew; }
	bool empty() const { return size() == 0; }		bool empty() const { return size() == 0; }
	LiveInterval *get(unsigned idx) const { return NewRegs[idx+FirstNew]; }		unsigned get(unsigned idx) const { return NewRegs[idx+FirstNew]; }
	ArrayRef<LiveInterval*> regs() const {		ArrayRef<unsigned> regs() const {
	return makeArrayRef(NewRegs).slice(FirstNew);		return makeArrayRef(NewRegs).slice(FirstNew);
	}		}
			/// createEmptyIntervalFrom - Create a new empty interval based on OldReg
			.
			LiveInterval &createEmptyIntervalFrom(unsigned OldReg);
	/// createFrom - Create a new virtual register based on OldReg.		/// createFrom - Create a new virtual register based on OldReg.
	LiveInterval &createFrom(unsigned OldReg);		unsigned createFrom(unsigned OldReg);
	/// create - Create a new register with the same class and original slot as		/// create - Create a new register with the same class and original slot as
	/// parent.		/// parent.
	LiveInterval &create() {		LiveInterval &createEmptyInterval() {
			return createEmptyIntervalFrom(getReg());
			}
			unsigned create() {
	return createFrom(getReg());		return createFrom(getReg());
	}		}
	/// anyRematerializable - Return true if any parent values may be		/// anyRematerializable - Return true if any parent values may be
	/// rematerializable.		/// rematerializable.
	/// This function must be called before any rematerialization is attempte d.		/// This function must be called before any rematerialization is attempte d.
	bool anyRematerializable(AliasAnalysis*);		bool anyRematerializable(AliasAnalysis*);
	/// checkRematerializable - Manually add VNI to the list of rematerializa ble		/// checkRematerializable - Manually add VNI to the list of rematerializa ble
	/// values if DefMI may be rematerializable.		/// values if DefMI may be rematerializable.
	skipping to change at line 204		skipping to change at line 225
	/// and further dead efs to be eliminated.		/// and further dead efs to be eliminated.
	/// RegsBeingSpilled lists registers currently being spilled by the regis ter		/// RegsBeingSpilled lists registers currently being spilled by the regis ter
	/// allocator. These registers should not be split into new intervals		/// allocator. These registers should not be split into new intervals
	/// as currently those new intervals are not guaranteed to spill.		/// as currently those new intervals are not guaranteed to spill.
	void eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,		void eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
	ArrayRef<unsigned> RegsBeingSpilled = None);		ArrayRef<unsigned> RegsBeingSpilled = None);
	/// calculateRegClassAndHint - Recompute register class and hint for each new		/// calculateRegClassAndHint - Recompute register class and hint for each new
	/// register.		/// register.
	void calculateRegClassAndHint(MachineFunction&,		void calculateRegClassAndHint(MachineFunction&,
	const MachineLoopInfo&);		const MachineLoopInfo&,
			const MachineBlockFrequencyInfo&);
	};		};
	}		}
	#endif		#endif
End of changes. 16 change blocks.
	11 lines changed or deleted		34 lines changed or added

	LiveVariables.h		LiveVariables.h
	skipping to change at line 160		skipping to change at line 160
	/// HandlePhysRegKill - Add kills of Reg and its sub-registers to the		/// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
	/// uses. Pay special attention to the sub-register uses which may come b elow		/// uses. Pay special attention to the sub-register uses which may come b elow
	/// the last use of the whole register.		/// the last use of the whole register.
	bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);		bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
	/// HandleRegMask - Call HandlePhysRegKill for all registers clobbered by Mask.		/// HandleRegMask - Call HandlePhysRegKill for all registers clobbered by Mask.
	void HandleRegMask(const MachineOperand&);		void HandleRegMask(const MachineOperand&);
	void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);		void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
	void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,		void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
	SmallVector<unsigned, 4> &Defs);		SmallVectorImpl<unsigned> &Defs);
	void UpdatePhysRegDefs(MachineInstr *MI, SmallVector<unsigned, 4> &Defs);		void UpdatePhysRegDefs(MachineInstr *MI, SmallVectorImpl<unsigned> &Defs)
			;
	/// FindLastRefOrPartRef - Return the last reference or partial reference of		/// FindLastRefOrPartRef - Return the last reference or partial reference of
	/// the specified register.		/// the specified register.
	MachineInstr *FindLastRefOrPartRef(unsigned Reg);		MachineInstr *FindLastRefOrPartRef(unsigned Reg);
	/// FindLastPartialDef - Return the last partial def of the specified		/// FindLastPartialDef - Return the last partial def of the specified
	/// register. Also returns the sub-registers that're defined by the		/// register. Also returns the sub-registers that're defined by the
	/// instruction.		/// instruction.
	MachineInstr *FindLastPartialDef(unsigned Reg,		MachineInstr *FindLastPartialDef(unsigned Reg,
	SmallSet<unsigned,4> &PartDefRegs);		SmallSet<unsigned,4> &PartDefRegs);
End of changes. 1 change blocks.
	2 lines changed or deleted		3 lines changed or added

	Local.h		Local.h
	skipping to change at line 42		skipping to change at line 42
	class LoadInst;		class LoadInst;
	class Value;		class Value;
	class Pass;		class Pass;
	class PHINode;		class PHINode;
	class AllocaInst;		class AllocaInst;
	class ConstantExpr;		class ConstantExpr;
	class DataLayout;		class DataLayout;
	class TargetLibraryInfo;		class TargetLibraryInfo;
	class TargetTransformInfo;		class TargetTransformInfo;
	class DIBuilder;		class DIBuilder;
			class AliasAnalysis;
	template<typename T> class SmallVectorImpl;		template<typename T> class SmallVectorImpl;
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// Local constant propagation.		// Local constant propagation.
	//		//
	/// ConstantFoldTerminator - If a terminator instruction is predicated on a		/// ConstantFoldTerminator - If a terminator instruction is predicated on a
	/// constant value, convert it into an unconditional branch to the constant		/// constant value, convert it into an unconditional branch to the constant
	/// destination. This is a nontrivial operation because the successors of this		/// destination. This is a nontrivial operation because the successors of this
	skipping to change at line 138		skipping to change at line 139
	/// SimplifyCFG - This function is used to do simplification of a CFG. For		/// SimplifyCFG - This function is used to do simplification of a CFG. For
	/// example, it adjusts branches to branches to eliminate the extra hop, it		/// example, it adjusts branches to branches to eliminate the extra hop, it
	/// eliminates unreachable basic blocks, and does other "peephole" optimiza tion		/// eliminates unreachable basic blocks, and does other "peephole" optimiza tion
	/// of the CFG. It returns true if a modification was made, possibly delet ing		/// of the CFG. It returns true if a modification was made, possibly delet ing
	/// the basic block that was pointed to.		/// the basic block that was pointed to.
	///		///
	bool SimplifyCFG(BasicBlock *BB, const TargetTransformInfo &TTI,		bool SimplifyCFG(BasicBlock *BB, const TargetTransformInfo &TTI,
	const DataLayout *TD = 0);		const DataLayout *TD = 0);
			/// FlatternCFG - This function is used to flatten a CFG. For
			/// example, it uses parallel-and and parallel-or mode to collapse
			// if-conditions and merge if-regions with identical statements.
			///
			bool FlattenCFG(BasicBlock *BB, AliasAnalysis *AA = 0);
	/// FoldBranchToCommonDest - If this basic block is ONLY a setcc and a bran ch,		/// FoldBranchToCommonDest - If this basic block is ONLY a setcc and a bran ch,
	/// and if a predecessor branches to us and one of our successors, fold the		/// and if a predecessor branches to us and one of our successors, fold the
	/// setcc into the predecessor and use logical operations to pick the right		/// setcc into the predecessor and use logical operations to pick the right
	/// destination.		/// destination.
	bool FoldBranchToCommonDest(BranchInst *BI);		bool FoldBranchToCommonDest(BranchInst *BI);
	/// DemoteRegToStack - This function takes a virtual register computed by a n		/// DemoteRegToStack - This function takes a virtual register computed by a n
	/// Instruction and replaces it with a slot in the stack frame, allocated v ia		/// Instruction and replaces it with a slot in the stack frame, allocated v ia
	/// alloca. This allows the CFG to be changed around without fear of		/// alloca. This allows the CFG to be changed around without fear of
	/// invalidating the SSA information for the value. It returns the pointer to		/// invalidating the SSA information for the value. It returns the pointer to
	skipping to change at line 179		skipping to change at line 186
	}		}
	/// EmitGEPOffset - Given a getelementptr instruction/constantexpr, emit th e		/// EmitGEPOffset - Given a getelementptr instruction/constantexpr, emit th e
	/// code necessary to compute the offset from the base pointer (without add ing		/// code necessary to compute the offset from the base pointer (without add ing
	/// in the base pointer). Return the result as a signed integer of intptr size.		/// in the base pointer). Return the result as a signed integer of intptr size.
	/// When NoAssumptions is true, no assumptions about index computation not		/// When NoAssumptions is true, no assumptions about index computation not
	/// overflowing is made.		/// overflowing is made.
	template<typename IRBuilderTy>		template<typename IRBuilderTy>
	Value *EmitGEPOffset(IRBuilderTy *Builder, const DataLayout &TD, User *GEP,		Value *EmitGEPOffset(IRBuilderTy *Builder, const DataLayout &TD, User *GEP,
	bool NoAssumptions = false) {		bool NoAssumptions = false) {
	gep_type_iterator GTI = gep_type_begin(GEP);		GEPOperator *GEPOp = cast<GEPOperator>(GEP);
	Type *IntPtrTy = TD.getIntPtrType(GEP->getContext());		Type *IntPtrTy = TD.getIntPtrType(GEP->getType());
	Value *Result = Constant::getNullValue(IntPtrTy);		Value *Result = Constant::getNullValue(IntPtrTy);
	// If the GEP is inbounds, we know that none of the addressing operations will		// If the GEP is inbounds, we know that none of the addressing operations will
	// overflow in an unsigned sense.		// overflow in an unsigned sense.
	bool isInBounds = cast<GEPOperator>(GEP)->isInBounds() && !NoAssumptions;		bool isInBounds = GEPOp->isInBounds() && !NoAssumptions;
	// Build a mask for high order bits.		// Build a mask for high order bits.
	unsigned IntPtrWidth = TD.getPointerSizeInBits();		unsigned IntPtrWidth = IntPtrTy->getScalarType()->getIntegerBitWidth();
	uint64_t PtrSizeMask = ~0ULL >> (64-IntPtrWidth);		uint64_t PtrSizeMask = ~0ULL >> (64 - IntPtrWidth);
			gep_type_iterator GTI = gep_type_begin(GEP);
	for (User::op_iterator i = GEP->op_begin() + 1, e = GEP->op_end(); i != e ;		for (User::op_iterator i = GEP->op_begin() + 1, e = GEP->op_end(); i != e ;
	++i, ++GTI) {		++i, ++GTI) {
	Value *Op = *i;		Value *Op = *i;
	uint64_t Size = TD.getTypeAllocSize(GTI.getIndexedType()) & PtrSizeMask ;		uint64_t Size = TD.getTypeAllocSize(GTI.getIndexedType()) & PtrSizeMask ;
	if (ConstantInt *OpC = dyn_cast<ConstantInt>(Op)) {		if (Constant *OpC = dyn_cast<Constant>(Op)) {
	if (OpC->isZero()) continue;		if (OpC->isZeroValue())
			continue;
	// Handle a struct index, which adds its field offset to the pointer.		// Handle a struct index, which adds its field offset to the pointer.
	if (StructType *STy = dyn_cast<StructType>(*GTI)) {		if (StructType *STy = dyn_cast<StructType>(*GTI)) {
	Size = TD.getStructLayout(STy)->getElementOffset(OpC->getZExtValue(		if (OpC->getType()->isVectorTy())
	));		OpC = OpC->getSplatValue();
			uint64_t OpValue = cast<ConstantInt>(OpC)->getZExtValue();
			Size = TD.getStructLayout(STy)->getElementOffset(OpValue);
	if (Size)		if (Size)
	Result = Builder->CreateAdd(Result, ConstantInt::get(IntPtrTy, Si ze),		Result = Builder->CreateAdd(Result, ConstantInt::get(IntPtrTy, Si ze),
	GEP->getName()+".offs");		GEP->getName()+".offs");
	continue;		continue;
	}		}
	Constant *Scale = ConstantInt::get(IntPtrTy, Size);		Constant *Scale = ConstantInt::get(IntPtrTy, Size);
	Constant *OC = ConstantExpr::getIntegerCast(OpC, IntPtrTy, true /*SEx t*/);		Constant *OC = ConstantExpr::getIntegerCast(OpC, IntPtrTy, true /*SEx t*/);
	Scale = ConstantExpr::getMul(OC, Scale, isInBounds/*NUW*/);		Scale = ConstantExpr::getMul(OC, Scale, isInBounds/*NUW*/);
End of changes. 8 change blocks.
	9 lines changed or deleted		21 lines changed or added

	LoopInfo.h		LoopInfo.h
	skipping to change at line 53		skipping to change at line 53
	template<typename T>		template<typename T>
	inline void RemoveFromVector(std::vector<T*> &V, T *N) {		inline void RemoveFromVector(std::vector<T*> &V, T *N) {
	typename std::vector<T*>::iterator I = std::find(V.begin(), V.end(), N);		typename std::vector<T*>::iterator I = std::find(V.begin(), V.end(), N);
	assert(I != V.end() && "N is not in this list!");		assert(I != V.end() && "N is not in this list!");
	V.erase(I);		V.erase(I);
	}		}
	class DominatorTree;		class DominatorTree;
	class LoopInfo;		class LoopInfo;
	class Loop;		class Loop;
			class MDNode;
	class PHINode;		class PHINode;
	class raw_ostream;		class raw_ostream;
	template<class N, class M> class LoopInfoBase;		template<class N, class M> class LoopInfoBase;
	template<class N, class M> class LoopBase;		template<class N, class M> class LoopBase;
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	/// LoopBase class - Instances of this class are used to represent loops th at		/// LoopBase class - Instances of this class are used to represent loops th at
	/// are detected in the flow graph		/// are detected in the flow graph
	///		///
	template<class BlockT, class LoopT>		template<class BlockT, class LoopT>
	class LoopBase {		class LoopBase {
	LoopT *ParentLoop;		LoopT *ParentLoop;
	// SubLoops - Loops contained entirely within this one.		// SubLoops - Loops contained entirely within this one.
	std::vector<LoopT *> SubLoops;		std::vector<LoopT *> SubLoops;
	// Blocks - The list of blocks in this loop. First entry is the header n ode.		// Blocks - The list of blocks in this loop. First entry is the header n ode.
	std::vector<BlockT*> Blocks;		std::vector<BlockT*> Blocks;
			SmallPtrSet<const BlockT*, 8> DenseBlockSet;
	LoopBase(const LoopBase<BlockT, LoopT> &) LLVM_DELETED_FUNCTION;		LoopBase(const LoopBase<BlockT, LoopT> &) LLVM_DELETED_FUNCTION;
	const LoopBase<BlockT, LoopT>&		const LoopBase<BlockT, LoopT>&
	operator=(const LoopBase<BlockT, LoopT> &) LLVM_DELETED_FUNCTION;		operator=(const LoopBase<BlockT, LoopT> &) LLVM_DELETED_FUNCTION;
	public:		public:
	/// Loop ctor - This creates an empty loop.		/// Loop ctor - This creates an empty loop.
	LoopBase() : ParentLoop(0) {}		LoopBase() : ParentLoop(0) {}
	~LoopBase() {		~LoopBase() {
	for (size_t i = 0, e = SubLoops.size(); i != e; ++i)		for (size_t i = 0, e = SubLoops.size(); i != e; ++i)
	delete SubLoops[i];		delete SubLoops[i];
	}		}
	skipping to change at line 110		skipping to change at line 113
	///		///
	bool contains(const LoopT *L) const {		bool contains(const LoopT *L) const {
	if (L == this) return true;		if (L == this) return true;
	if (L == 0) return false;		if (L == 0) return false;
	return contains(L->getParentLoop());		return contains(L->getParentLoop());
	}		}
	/// contains - Return true if the specified basic block is in this loop.		/// contains - Return true if the specified basic block is in this loop.
	///		///
	bool contains(const BlockT *BB) const {		bool contains(const BlockT *BB) const {
	return std::find(block_begin(), block_end(), BB) != block_end();		return DenseBlockSet.count(BB);
	}		}
	/// contains - Return true if the specified instruction is in this loop.		/// contains - Return true if the specified instruction is in this loop.
	///		///
	template<class InstT>		template<class InstT>
	bool contains(const InstT *Inst) const {		bool contains(const InstT *Inst) const {
	return contains(Inst->getParent());		return contains(Inst->getParent());
	}		}
	/// iterator/begin/end - Return the loops contained entirely within this loop.		/// iterator/begin/end - Return the loops contained entirely within this loop.
	skipping to change at line 136		skipping to change at line 139
	reverse_iterator;		reverse_iterator;
	iterator begin() const { return SubLoops.begin(); }		iterator begin() const { return SubLoops.begin(); }
	iterator end() const { return SubLoops.end(); }		iterator end() const { return SubLoops.end(); }
	reverse_iterator rbegin() const { return SubLoops.rbegin(); }		reverse_iterator rbegin() const { return SubLoops.rbegin(); }
	reverse_iterator rend() const { return SubLoops.rend(); }		reverse_iterator rend() const { return SubLoops.rend(); }
	bool empty() const { return SubLoops.empty(); }		bool empty() const { return SubLoops.empty(); }
	/// getBlocks - Get a list of the basic blocks which make up this loop.		/// getBlocks - Get a list of the basic blocks which make up this loop.
	///		///
	const std::vector<BlockT*> &getBlocks() const { return Blocks; }		const std::vector<BlockT*> &getBlocks() const { return Blocks; }
	std::vector<BlockT*> &getBlocksVector() { return Blocks; }
	typedef typename std::vector<BlockT*>::const_iterator block_iterator;		typedef typename std::vector<BlockT*>::const_iterator block_iterator;
	block_iterator block_begin() const { return Blocks.begin(); }		block_iterator block_begin() const { return Blocks.begin(); }
	block_iterator block_end() const { return Blocks.end(); }		block_iterator block_end() const { return Blocks.end(); }
	/// getNumBlocks - Get the number of blocks in this loop in constant time .		/// getNumBlocks - Get the number of blocks in this loop in constant time .
	unsigned getNumBlocks() const {		unsigned getNumBlocks() const {
	return Blocks.size();		return Blocks.size();
	}		}
	/// isLoopExiting - True if terminator in the block can branch to another		/// isLoopExiting - True if terminator in the block can branch to another
	skipping to change at line 273		skipping to change at line 275
	SubLoops.erase(SubLoops.begin()+(I-begin()));		SubLoops.erase(SubLoops.begin()+(I-begin()));
	Child->ParentLoop = 0;		Child->ParentLoop = 0;
	return Child;		return Child;
	}		}
	/// addBlockEntry - This adds a basic block directly to the basic block l ist.		/// addBlockEntry - This adds a basic block directly to the basic block l ist.
	/// This should only be used by transformations that create new loops. O ther		/// This should only be used by transformations that create new loops. O ther
	/// transformations should use addBasicBlockToLoop.		/// transformations should use addBasicBlockToLoop.
	void addBlockEntry(BlockT *BB) {		void addBlockEntry(BlockT *BB) {
	Blocks.push_back(BB);		Blocks.push_back(BB);
			DenseBlockSet.insert(BB);
			}
			/// reverseBlocks - interface to reverse Blocks[from, end of loop] in thi
			s loop
			void reverseBlock(unsigned from) {
			std::reverse(Blocks.begin() + from, Blocks.end());
			}
			/// reserveBlocks- interface to do reserve() for Blocks
			void reserveBlocks(unsigned size) {
			Blocks.reserve(size);
	}		}
	/// moveToHeader - This method is used to move BB (which must be part of this		/// moveToHeader - This method is used to move BB (which must be part of this
	/// loop) to be the loop header of the loop (the block that dominates all		/// loop) to be the loop header of the loop (the block that dominates all
	/// others).		/// others).
	void moveToHeader(BlockT *BB) {		void moveToHeader(BlockT *BB) {
	if (Blocks[0] == BB) return;		if (Blocks[0] == BB) return;
	for (unsigned i = 0; ; ++i) {		for (unsigned i = 0; ; ++i) {
	assert(i != Blocks.size() && "Loop does not contain BB!");		assert(i != Blocks.size() && "Loop does not contain BB!");
	if (Blocks[i] == BB) {		if (Blocks[i] == BB) {
	skipping to change at line 295		skipping to change at line 308
	return;		return;
	}		}
	}		}
	}		}
	/// removeBlockFromLoop - This removes the specified basic block from the		/// removeBlockFromLoop - This removes the specified basic block from the
	/// current loop, updating the Blocks as appropriate. This does not upda te		/// current loop, updating the Blocks as appropriate. This does not upda te
	/// the mapping in the LoopInfo class.		/// the mapping in the LoopInfo class.
	void removeBlockFromLoop(BlockT *BB) {		void removeBlockFromLoop(BlockT *BB) {
	RemoveFromVector(Blocks, BB);		RemoveFromVector(Blocks, BB);
			DenseBlockSet.erase(BB);
	}		}
	/// verifyLoop - Verify loop structure		/// verifyLoop - Verify loop structure
	void verifyLoop() const;		void verifyLoop() const;
	/// verifyLoop - Verify loop structure of this loop and all nested loops.		/// verifyLoop - Verify loop structure of this loop and all nested loops.
	void verifyLoopNest(DenseSet<const LoopT*> *Loops) const;		void verifyLoopNest(DenseSet<const LoopT*> *Loops) const;
	void print(raw_ostream &OS, unsigned Depth = 0) const;		void print(raw_ostream &OS, unsigned Depth = 0) const;
	protected:		protected:
	friend class LoopInfoBase<BlockT, LoopT>;		friend class LoopInfoBase<BlockT, LoopT>;
	explicit LoopBase(BlockT *BB) : ParentLoop(0) {		explicit LoopBase(BlockT *BB) : ParentLoop(0) {
	Blocks.push_back(BB);		Blocks.push_back(BB);
			DenseBlockSet.insert(BB);
	}		}
	};		};
	template<class BlockT, class LoopT>		template<class BlockT, class LoopT>
	raw_ostream& operator<<(raw_ostream &OS, const LoopBase<BlockT, LoopT> &Loo p) {		raw_ostream& operator<<(raw_ostream &OS, const LoopBase<BlockT, LoopT> &Loo p) {
	Loop.print(OS);		Loop.print(OS);
	return OS;		return OS;
	}		}
	// Implementation in LoopInfoImpl.h		// Implementation in LoopInfoImpl.h
	skipping to change at line 394		skipping to change at line 409
	/// can be skipped completely when parallelizing the loop on the target		/// can be skipped completely when parallelizing the loop on the target
	/// machine. Thus, if the parallel loop information originates from the		/// machine. Thus, if the parallel loop information originates from the
	/// programmer, e.g. via the OpenMP parallel for pragma, it is the		/// programmer, e.g. via the OpenMP parallel for pragma, it is the
	/// programmer's responsibility to ensure there are no loop-carried		/// programmer's responsibility to ensure there are no loop-carried
	/// dependencies. The final execution order of the instructions across		/// dependencies. The final execution order of the instructions across
	/// iterations is not guaranteed, thus, the end result might or might not		/// iterations is not guaranteed, thus, the end result might or might not
	/// implement actual concurrent execution of instructions across multiple		/// implement actual concurrent execution of instructions across multiple
	/// iterations.		/// iterations.
	bool isAnnotatedParallel() const;		bool isAnnotatedParallel() const;
			/// Return the llvm.loop loop id metadata node for this loop if it is pre
			sent.
			///
			/// If this loop contains the same llvm.loop metadata on each branch to t
			he
			/// header then the node is returned. If any latch instruction does not
			/// contain llvm.loop or or if multiple latches contain different nodes t
			hen
			/// 0 is returned.
			MDNode *getLoopID() const;
			/// Set the llvm.loop loop id metadata for this loop.
			///
			/// The LoopID metadata node will be added to each terminator instruction
			in
			/// the loop that branches to the loop header.
			///
			/// The LoopID metadata node should have one or more operands and the fir
			st
			/// operand should should be the node itself.
			void setLoopID(MDNode *LoopID) const;
	/// hasDedicatedExits - Return true if no exit block for the loop		/// hasDedicatedExits - Return true if no exit block for the loop
	/// has a predecessor that is outside the loop.		/// has a predecessor that is outside the loop.
	bool hasDedicatedExits() const;		bool hasDedicatedExits() const;
	/// getUniqueExitBlocks - Return all unique successor blocks of this loop .		/// getUniqueExitBlocks - Return all unique successor blocks of this loop .
	/// These are the blocks _outside of the current loop_ which are branched to.		/// These are the blocks _outside of the current loop_ which are branched to.
	/// This assumes that loop exits are in canonical form.		/// This assumes that loop exits are in canonical form.
	///		///
	void getUniqueExitBlocks(SmallVectorImpl<BasicBlock *> &ExitBlocks) const ;		void getUniqueExitBlocks(SmallVectorImpl<BasicBlock *> &ExitBlocks) const ;
End of changes. 8 change blocks.
	2 lines changed or deleted		39 lines changed or added

	LoopInfoImpl.h		LoopInfoImpl.h
	skipping to change at line 34		skipping to change at line 34
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// APIs for simple analysis of the loop. See header notes.		// APIs for simple analysis of the loop. See header notes.
	/// getExitingBlocks - Return all blocks inside the loop that have successo rs		/// getExitingBlocks - Return all blocks inside the loop that have successo rs
	/// outside of the loop. These are the blocks _inside of the current loop_		/// outside of the loop. These are the blocks _inside of the current loop_
	/// which branch out. The returned list is always unique.		/// which branch out. The returned list is always unique.
	///		///
	template<class BlockT, class LoopT>		template<class BlockT, class LoopT>
	void LoopBase<BlockT, LoopT>::		void LoopBase<BlockT, LoopT>::
	getExitingBlocks(SmallVectorImpl<BlockT *> &ExitingBlocks) const {		getExitingBlocks(SmallVectorImpl<BlockT *> &ExitingBlocks) const {
	// Sort the blocks vector so that we can use binary search to do quick
	// lookups.
	SmallVector<BlockT*, 128> LoopBBs(block_begin(), block_end());
	std::sort(LoopBBs.begin(), LoopBBs.end());
	typedef GraphTraits<BlockT*> BlockTraits;		typedef GraphTraits<BlockT*> BlockTraits;
	for (block_iterator BI = block_begin(), BE = block_end(); BI != BE; ++BI)		for (block_iterator BI = block_begin(), BE = block_end(); BI != BE; ++BI)
	for (typename BlockTraits::ChildIteratorType I =		for (typename BlockTraits::ChildIteratorType I =
	BlockTraits::child_begin(*BI), E = BlockTraits::child_end(*BI);		BlockTraits::child_begin(*BI), E = BlockTraits::child_end(*BI);
	I != E; ++I)		I != E; ++I)
	if (!std::binary_search(LoopBBs.begin(), LoopBBs.end(), *I)) {		if (!contains(*I)) {
	// Not in current loop? It must be an exit block.		// Not in current loop? It must be an exit block.
	ExitingBlocks.push_back(*BI);		ExitingBlocks.push_back(*BI);
	break;		break;
	}		}
	}		}
	/// getExitingBlock - If getExitingBlocks would return exactly one block,		/// getExitingBlock - If getExitingBlocks would return exactly one block,
	/// return that block. Otherwise return null.		/// return that block. Otherwise return null.
	template<class BlockT, class LoopT>		template<class BlockT, class LoopT>
	BlockT *LoopBase<BlockT, LoopT>::getExitingBlock() const {		BlockT *LoopBase<BlockT, LoopT>::getExitingBlock() const {
	skipping to change at line 68		skipping to change at line 63
	return ExitingBlocks[0];		return ExitingBlocks[0];
	return 0;		return 0;
	}		}
	/// getExitBlocks - Return all of the successor blocks of this loop. These		/// getExitBlocks - Return all of the successor blocks of this loop. These
	/// are the blocks _outside of the current loop_ which are branched to.		/// are the blocks _outside of the current loop_ which are branched to.
	///		///
	template<class BlockT, class LoopT>		template<class BlockT, class LoopT>
	void LoopBase<BlockT, LoopT>::		void LoopBase<BlockT, LoopT>::
	getExitBlocks(SmallVectorImpl<BlockT*> &ExitBlocks) const {		getExitBlocks(SmallVectorImpl<BlockT*> &ExitBlocks) const {
	// Sort the blocks vector so that we can use binary search to do quick
	// lookups.
	SmallVector<BlockT*, 128> LoopBBs(block_begin(), block_end());
	std::sort(LoopBBs.begin(), LoopBBs.end());
	typedef GraphTraits<BlockT*> BlockTraits;		typedef GraphTraits<BlockT*> BlockTraits;
	for (block_iterator BI = block_begin(), BE = block_end(); BI != BE; ++BI)		for (block_iterator BI = block_begin(), BE = block_end(); BI != BE; ++BI)
	for (typename BlockTraits::ChildIteratorType I =		for (typename BlockTraits::ChildIteratorType I =
	BlockTraits::child_begin(*BI), E = BlockTraits::child_end(*BI);		BlockTraits::child_begin(*BI), E = BlockTraits::child_end(*BI);
	I != E; ++I)		I != E; ++I)
	if (!std::binary_search(LoopBBs.begin(), LoopBBs.end(), *I))		if (!contains(*I))
	// Not in current loop? It must be an exit block.		// Not in current loop? It must be an exit block.
	ExitBlocks.push_back(*I);		ExitBlocks.push_back(*I);
	}		}
	/// getExitBlock - If getExitBlocks would return exactly one block,		/// getExitBlock - If getExitBlocks would return exactly one block,
	/// return that block. Otherwise return null.		/// return that block. Otherwise return null.
	template<class BlockT, class LoopT>		template<class BlockT, class LoopT>
	BlockT *LoopBase<BlockT, LoopT>::getExitBlock() const {		BlockT *LoopBase<BlockT, LoopT>::getExitBlock() const {
	SmallVector<BlockT*, 8> ExitBlocks;		SmallVector<BlockT*, 8> ExitBlocks;
	getExitBlocks(ExitBlocks);		getExitBlocks(ExitBlocks);
	if (ExitBlocks.size() == 1)		if (ExitBlocks.size() == 1)
	return ExitBlocks[0];		return ExitBlocks[0];
	return 0;		return 0;
	}		}
	/// getExitEdges - Return all pairs of (_inside_block_,_outside_block_).		/// getExitEdges - Return all pairs of (_inside_block_,_outside_block_).
	template<class BlockT, class LoopT>		template<class BlockT, class LoopT>
	void LoopBase<BlockT, LoopT>::		void LoopBase<BlockT, LoopT>::
	getExitEdges(SmallVectorImpl<Edge> &ExitEdges) const {		getExitEdges(SmallVectorImpl<Edge> &ExitEdges) const {
	// Sort the blocks vector so that we can use binary search to do quick
	// lookups.
	SmallVector<BlockT*, 128> LoopBBs(block_begin(), block_end());
	array_pod_sort(LoopBBs.begin(), LoopBBs.end());
	typedef GraphTraits<BlockT*> BlockTraits;		typedef GraphTraits<BlockT*> BlockTraits;
	for (block_iterator BI = block_begin(), BE = block_end(); BI != BE; ++BI)		for (block_iterator BI = block_begin(), BE = block_end(); BI != BE; ++BI)
	for (typename BlockTraits::ChildIteratorType I =		for (typename BlockTraits::ChildIteratorType I =
	BlockTraits::child_begin(*BI), E = BlockTraits::child_end(*BI);		BlockTraits::child_begin(*BI), E = BlockTraits::child_end(*BI);
	I != E; ++I)		I != E; ++I)
	if (!std::binary_search(LoopBBs.begin(), LoopBBs.end(), *I))		if (!contains(*I))
	// Not in current loop? It must be an exit block.		// Not in current loop? It must be an exit block.
	ExitEdges.push_back(Edge(*BI, *I));		ExitEdges.push_back(Edge(*BI, *I));
	}		}
	/// getLoopPreheader - If there is a preheader for this loop, return it. A		/// getLoopPreheader - If there is a preheader for this loop, return it. A
	/// loop has a preheader if there is only one edge to the header of the loo p		/// loop has a preheader if there is only one edge to the header of the loo p
	/// from outside of the loop. If this is the case, the block branching to the		/// from outside of the loop. If this is the case, the block branching to the
	/// header of the loop is the preheader node.		/// header of the loop is the preheader node.
	///		///
	/// This method returns null if there is no preheader for the loop.		/// This method returns null if there is no preheader for the loop.
	skipping to change at line 213		skipping to change at line 198
	assert(NewBB && "Cannot add a null basic block to the loop!");		assert(NewBB && "Cannot add a null basic block to the loop!");
	assert(LIB[NewBB] == 0 && "BasicBlock already in the loop!");		assert(LIB[NewBB] == 0 && "BasicBlock already in the loop!");
	LoopT *L = static_cast<LoopT *>(this);		LoopT *L = static_cast<LoopT *>(this);
	// Add the loop mapping to the LoopInfo object...		// Add the loop mapping to the LoopInfo object...
	LIB.BBMap[NewBB] = L;		LIB.BBMap[NewBB] = L;
	// Add the basic block to this loop and all parent loops...		// Add the basic block to this loop and all parent loops...
	while (L) {		while (L) {
	L->Blocks.push_back(NewBB);		L->addBlockEntry(NewBB);
	L = L->getParentLoop();		L = L->getParentLoop();
	}		}
	}		}
	/// replaceChildLoopWith - This is used when splitting loops up. It replac es		/// replaceChildLoopWith - This is used when splitting loops up. It replac es
	/// the OldChild entry in our children list with NewChild, and updates the		/// the OldChild entry in our children list with NewChild, and updates the
	/// parent pointer of OldChild to be null and the NewChild to be this loop.		/// parent pointer of OldChild to be null and the NewChild to be this loop.
	/// This updates the loop depth of the new child.		/// This updates the loop depth of the new child.
	template<class BlockT, class LoopT>		template<class BlockT, class LoopT>
	void LoopBase<BlockT, LoopT>::		void LoopBase<BlockT, LoopT>::
	skipping to change at line 253		skipping to change at line 238
	getExitBlocks(ExitBBs);		getExitBlocks(ExitBBs);
	llvm::SmallPtrSet<BlockT*, 8> VisitSet;		llvm::SmallPtrSet<BlockT*, 8> VisitSet;
	VisitSet.insert(ExitBBs.begin(), ExitBBs.end());		VisitSet.insert(ExitBBs.begin(), ExitBBs.end());
	df_ext_iterator<BlockT*, llvm::SmallPtrSet<BlockT*, 8> >		df_ext_iterator<BlockT*, llvm::SmallPtrSet<BlockT*, 8> >
	BI = df_ext_begin(getHeader(), VisitSet),		BI = df_ext_begin(getHeader(), VisitSet),
	BE = df_ext_end(getHeader(), VisitSet);		BE = df_ext_end(getHeader(), VisitSet);
	// Keep track of the number of BBs visited.		// Keep track of the number of BBs visited.
	unsigned NumVisited = 0;		unsigned NumVisited = 0;
	// Sort the blocks vector so that we can use binary search to do quick
	// lookups.
	SmallVector<BlockT*, 128> LoopBBs(block_begin(), block_end());
	std::sort(LoopBBs.begin(), LoopBBs.end());
	// Check the individual blocks.		// Check the individual blocks.
	for ( ; BI != BE; ++BI) {		for ( ; BI != BE; ++BI) {
	BlockT *BB = *BI;		BlockT *BB = *BI;
	bool HasInsideLoopSuccs = false;		bool HasInsideLoopSuccs = false;
	bool HasInsideLoopPreds = false;		bool HasInsideLoopPreds = false;
	SmallVector<BlockT *, 2> OutsideLoopPreds;		SmallVector<BlockT *, 2> OutsideLoopPreds;
	typedef GraphTraits<BlockT*> BlockTraits;		typedef GraphTraits<BlockT*> BlockTraits;
	for (typename BlockTraits::ChildIteratorType SI =		for (typename BlockTraits::ChildIteratorType SI =
	BlockTraits::child_begin(BB), SE = BlockTraits::child_end(BB);		BlockTraits::child_begin(BB), SE = BlockTraits::child_end(BB);
	SI != SE; ++SI)		SI != SE; ++SI)
	if (std::binary_search(LoopBBs.begin(), LoopBBs.end(), *SI)) {		if (contains(*SI)) {
	HasInsideLoopSuccs = true;		HasInsideLoopSuccs = true;
	break;		break;
	}		}
	typedef GraphTraits<Inverse<BlockT*> > InvBlockTraits;		typedef GraphTraits<Inverse<BlockT*> > InvBlockTraits;
	for (typename InvBlockTraits::ChildIteratorType PI =		for (typename InvBlockTraits::ChildIteratorType PI =
	InvBlockTraits::child_begin(BB), PE = InvBlockTraits::child_end( BB);		InvBlockTraits::child_begin(BB), PE = InvBlockTraits::child_end( BB);
	PI != PE; ++PI) {		PI != PE; ++PI) {
	BlockT *N = *PI;		BlockT *N = *PI;
	if (std::binary_search(LoopBBs.begin(), LoopBBs.end(), N))		if (contains(N))
	HasInsideLoopPreds = true;		HasInsideLoopPreds = true;
	else		else
	OutsideLoopPreds.push_back(N);		OutsideLoopPreds.push_back(N);
	}		}
	if (BB == getHeader()) {		if (BB == getHeader()) {
	assert(!OutsideLoopPreds.empty() && "Loop is unreachable!");		assert(!OutsideLoopPreds.empty() && "Loop is unreachable!");
	} else if (!OutsideLoopPreds.empty()) {		} else if (!OutsideLoopPreds.empty()) {
	// A non-header loop shouldn't be reachable from outside the loop,		// A non-header loop shouldn't be reachable from outside the loop,
	// though it is permitted if the predecessor is not itself actually		// though it is permitted if the predecessor is not itself actually
	skipping to change at line 312		skipping to change at line 292
	NumVisited++;		NumVisited++;
	}		}
	assert(NumVisited == getNumBlocks() && "Unreachable block in loop");		assert(NumVisited == getNumBlocks() && "Unreachable block in loop");
	// Check the subloops.		// Check the subloops.
	for (iterator I = begin(), E = end(); I != E; ++I)		for (iterator I = begin(), E = end(); I != E; ++I)
	// Each block in each subloop should be contained within this loop.		// Each block in each subloop should be contained within this loop.
	for (block_iterator BI = (*I)->block_begin(), BE = (*I)->block_end();		for (block_iterator BI = (*I)->block_begin(), BE = (*I)->block_end();
	BI != BE; ++BI) {		BI != BE; ++BI) {
	assert(std::binary_search(LoopBBs.begin(), LoopBBs.end(), *BI) &&		assert(contains(*BI) &&
	"Loop does not contain all the blocks of a subloop!");		"Loop does not contain all the blocks of a subloop!");
	}		}
	// Check the parent loop pointer.		// Check the parent loop pointer.
	if (ParentLoop) {		if (ParentLoop) {
	assert(std::find(ParentLoop->begin(), ParentLoop->end(), this) !=		assert(std::find(ParentLoop->begin(), ParentLoop->end(), this) !=
	ParentLoop->end() &&		ParentLoop->end() &&
	"Loop is not a subloop of its parent!");		"Loop is not a subloop of its parent!");
	}		}
	#endif		#endif
	skipping to change at line 421		skipping to change at line 401
	// this loop, which we must traverse.		// this loop, which we must traverse.
	for (typename InvBlockTraits::ChildIteratorType PI =		for (typename InvBlockTraits::ChildIteratorType PI =
	InvBlockTraits::child_begin(PredBB),		InvBlockTraits::child_begin(PredBB),
	PE = InvBlockTraits::child_end(PredBB); PI != PE; ++PI) {		PE = InvBlockTraits::child_end(PredBB); PI != PE; ++PI) {
	if (LI->getLoopFor(*PI) != Subloop)		if (LI->getLoopFor(*PI) != Subloop)
	ReverseCFGWorklist.push_back(*PI);		ReverseCFGWorklist.push_back(*PI);
	}		}
	}		}
	}		}
	L->getSubLoopsVector().reserve(NumSubloops);		L->getSubLoopsVector().reserve(NumSubloops);
	L->getBlocksVector().reserve(NumBlocks);		L->reserveBlocks(NumBlocks);
	}		}
	namespace {		namespace {
	/// Populate all loop data in a stable order during a single forward DFS.		/// Populate all loop data in a stable order during a single forward DFS.
	template<class BlockT, class LoopT>		template<class BlockT, class LoopT>
	class PopulateLoopsDFS {		class PopulateLoopsDFS {
	typedef GraphTraits<BlockT*> BlockTraits;		typedef GraphTraits<BlockT*> BlockTraits;
	typedef typename BlockTraits::ChildIteratorType SuccIterTy;		typedef typename BlockTraits::ChildIteratorType SuccIterTy;
	LoopInfoBase<BlockT, LoopT> *LI;		LoopInfoBase<BlockT, LoopT> *LI;
	skipping to change at line 492		skipping to change at line 472
	if (Subloop && Block == Subloop->getHeader()) {		if (Subloop && Block == Subloop->getHeader()) {
	// We reach this point once per subloop after processing all the blocks in		// We reach this point once per subloop after processing all the blocks in
	// the subloop.		// the subloop.
	if (Subloop->getParentLoop())		if (Subloop->getParentLoop())
	Subloop->getParentLoop()->getSubLoopsVector().push_back(Subloop);		Subloop->getParentLoop()->getSubLoopsVector().push_back(Subloop);
	else		else
	LI->addTopLevelLoop(Subloop);		LI->addTopLevelLoop(Subloop);
	// For convenience, Blocks and Subloops are inserted in postorder. Reve rse		// For convenience, Blocks and Subloops are inserted in postorder. Reve rse
	// the lists, except for the loop header, which is always at the beginn ing.		// the lists, except for the loop header, which is always at the beginn ing.
	std::reverse(Subloop->getBlocksVector().begin()+1,		Subloop->reverseBlock(1);
	Subloop->getBlocksVector().end());
	std::reverse(Subloop->getSubLoopsVector().begin(),		std::reverse(Subloop->getSubLoopsVector().begin(),
	Subloop->getSubLoopsVector().end());		Subloop->getSubLoopsVector().end());
	Subloop = Subloop->getParentLoop();		Subloop = Subloop->getParentLoop();
	}		}
	for (; Subloop; Subloop = Subloop->getParentLoop())		for (; Subloop; Subloop = Subloop->getParentLoop())
	Subloop->getBlocksVector().push_back(Block);		Subloop->addBlockEntry(Block);
	}		}
	/// Analyze LoopInfo discovers loops during a postorder DominatorTree trave rsal		/// Analyze LoopInfo discovers loops during a postorder DominatorTree trave rsal
	/// interleaved with backward CFG traversals within each subloop		/// interleaved with backward CFG traversals within each subloop
	/// (discoverAndMapSubloop). The backward traversal skips inner subloops, s o		/// (discoverAndMapSubloop). The backward traversal skips inner subloops, s o
	/// this part of the algorithm is linear in the number of CFG edges. Subloo p and		/// this part of the algorithm is linear in the number of CFG edges. Subloo p and
	/// Block vectors are then populated during a single forward CFG traversal		/// Block vectors are then populated during a single forward CFG traversal
	/// (PopulateLoopDFS).		/// (PopulateLoopDFS).
	///		///
	/// During the two CFG traversals each block is seen three times:		/// During the two CFG traversals each block is seen three times:
End of changes. 14 change blocks.
	31 lines changed or deleted		10 lines changed or added

	LoopPass.h		LoopPass.h
	skipping to change at line 19		skipping to change at line 19
	//		//
	// This file defines LoopPass class. All loop optimization		// This file defines LoopPass class. All loop optimization
	// and transformation passes are derived from LoopPass.		// and transformation passes are derived from LoopPass.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_ANALYSIS_LOOPPASS_H		#ifndef LLVM_ANALYSIS_LOOPPASS_H
	#define LLVM_ANALYSIS_LOOPPASS_H		#define LLVM_ANALYSIS_LOOPPASS_H
	#include "llvm/Analysis/LoopInfo.h"		#include "llvm/Analysis/LoopInfo.h"
			#include "llvm/IR/LegacyPassManagers.h"
	#include "llvm/Pass.h"		#include "llvm/Pass.h"
	#include "llvm/PassManagers.h"
	#include <deque>		#include <deque>
	namespace llvm {		namespace llvm {
	class LPPassManager;		class LPPassManager;
	class Function;		class Function;
	class PMStack;		class PMStack;
	class LoopPass : public Pass {		class LoopPass : public Pass {
	public:		public:
End of changes. 2 change blocks.
	1 lines changed or deleted		1 lines changed or added

	MCAsmBackend.h		MCAsmBackend.h
	skipping to change at line 13		skipping to change at line 13
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_MC_MCASMBACKEND_H		#ifndef LLVM_MC_MCASMBACKEND_H
	#define LLVM_MC_MCASMBACKEND_H		#define LLVM_MC_MCASMBACKEND_H
			#include "llvm/ADT/ArrayRef.h"
	#include "llvm/MC/MCDirectives.h"		#include "llvm/MC/MCDirectives.h"
			#include "llvm/MC/MCDwarf.h"
	#include "llvm/MC/MCFixup.h"		#include "llvm/MC/MCFixup.h"
	#include "llvm/Support/DataTypes.h"		#include "llvm/Support/DataTypes.h"
	#include "llvm/Support/ErrorHandling.h"		#include "llvm/Support/ErrorHandling.h"
	namespace llvm {		namespace llvm {
	class MCAsmLayout;		class MCAsmLayout;
	class MCAssembler;		class MCAssembler;
	class MCELFObjectTargetWriter;		class MCELFObjectTargetWriter;
	struct MCFixupKindInfo;		struct MCFixupKindInfo;
	class MCFragment;		class MCFragment;
	skipping to change at line 35		skipping to change at line 37
	class MCRelaxableFragment;		class MCRelaxableFragment;
	class MCObjectWriter;		class MCObjectWriter;
	class MCSection;		class MCSection;
	class MCValue;		class MCValue;
	class raw_ostream;		class raw_ostream;
	/// MCAsmBackend - Generic interface to target specific assembler backends.		/// MCAsmBackend - Generic interface to target specific assembler backends.
	class MCAsmBackend {		class MCAsmBackend {
	MCAsmBackend(const MCAsmBackend &) LLVM_DELETED_FUNCTION;		MCAsmBackend(const MCAsmBackend &) LLVM_DELETED_FUNCTION;
	void operator=(const MCAsmBackend &) LLVM_DELETED_FUNCTION;		void operator=(const MCAsmBackend &) LLVM_DELETED_FUNCTION;
	protected: // Can only create subclasses.		protected: // Can only create subclasses.
	MCAsmBackend();		MCAsmBackend();
	unsigned HasReliableSymbolDifference : 1;		unsigned HasReliableSymbolDifference : 1;
	unsigned HasDataInCodeSupport : 1;		unsigned HasDataInCodeSupport : 1;
	public:		public:
	virtual ~MCAsmBackend();		virtual ~MCAsmBackend();
	/// lifetime management		/// lifetime management
	virtual void reset() { }		virtual void reset() {}
	/// createObjectWriter - Create a new MCObjectWriter instance for use by the		/// createObjectWriter - Create a new MCObjectWriter instance for use by the
	/// assembler backend to emit the final object file.		/// assembler backend to emit the final object file.
	virtual MCObjectWriter *createObjectWriter(raw_ostream &OS) const = 0;		virtual MCObjectWriter *createObjectWriter(raw_ostream &OS) const = 0;
	/// createELFObjectTargetWriter - Create a new ELFObjectTargetWriter to e nable		/// createELFObjectTargetWriter - Create a new ELFObjectTargetWriter to e nable
	/// non-standard ELFObjectWriters.		/// non-standard ELFObjectWriters.
	virtual MCELFObjectTargetWriter *createELFObjectTargetWriter() const {		virtual MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
	llvm_unreachable("createELFObjectTargetWriter is not supported by asm "		llvm_unreachable("createELFObjectTargetWriter is not supported by asm "
	"backend");		"backend");
	}		}
	/// hasReliableSymbolDifference - Check whether this target implements		/// hasReliableSymbolDifference - Check whether this target implements
	/// accurate relocations for differences between symbols. If not, differe nces		/// accurate relocations for differences between symbols. If not, differe nces
	/// between symbols will always be relocatable expressions and any refere nces		/// between symbols will always be relocatable expressions and any refere nces
	/// to temporary symbols will be assumed to be in the same atom, unless t hey		/// to temporary symbols will be assumed to be in the same atom, unless t hey
	/// reside in a different section.		/// reside in a different section.
	///		///
	/// This should always be true (since it results in fewer relocations wit h no		/// This should always be true (since it results in fewer relocations wit h no
	/// loss of functionality), but is currently supported as a way to mainta in		/// loss of functionality), but is currently supported as a way to mainta in
	/// exact object compatibility with Darwin 'as' (on non-x86_64). It shoul d		/// exact object compatibility with Darwin 'as' (on non-x86_64). It shoul d
	/// eventually should be eliminated.		/// eventually should be eliminated.
	bool hasReliableSymbolDifference() const {		bool hasReliableSymbolDifference() const {
	return HasReliableSymbolDifference;		return HasReliableSymbolDifference;
	}		}
	/// hasDataInCodeSupport - Check whether this target implements data-in-c ode		/// hasDataInCodeSupport - Check whether this target implements data-in-c ode
	/// markers. If not, data region directives will be ignored.		/// markers. If not, data region directives will be ignored.
	bool hasDataInCodeSupport() const {		bool hasDataInCodeSupport() const { return HasDataInCodeSupport; }
	return HasDataInCodeSupport;
	}
	/// doesSectionRequireSymbols - Check whether the given section requires that		/// doesSectionRequireSymbols - Check whether the given section requires that
	/// all symbols (even temporaries) have symbol table entries.		/// all symbols (even temporaries) have symbol table entries.
	virtual bool doesSectionRequireSymbols(const MCSection &Section) const {		virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
	return false;		return false;
	}		}
	/// isSectionAtomizable - Check whether the given section can be split in to		/// isSectionAtomizable - Check whether the given section can be split in to
	/// atoms.		/// atoms.
	///		///
	skipping to change at line 131		skipping to change at line 132
	/// @{		/// @{
	/// mayNeedRelaxation - Check whether the given instruction may need		/// mayNeedRelaxation - Check whether the given instruction may need
	/// relaxation.		/// relaxation.
	///		///
	/// \param Inst - The instruction to test.		/// \param Inst - The instruction to test.
	virtual bool mayNeedRelaxation(const MCInst &Inst) const = 0;		virtual bool mayNeedRelaxation(const MCInst &Inst) const = 0;
	/// fixupNeedsRelaxation - Target specific predicate for whether a given		/// fixupNeedsRelaxation - Target specific predicate for whether a given
	/// fixup requires the associated instruction to be relaxed.		/// fixup requires the associated instruction to be relaxed.
	virtual bool fixupNeedsRelaxation(const MCFixup &Fixup,		virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
	uint64_t Value,
	const MCRelaxableFragment *DF,		const MCRelaxableFragment *DF,
	const MCAsmLayout &Layout) const = 0;		const MCAsmLayout &Layout) const = 0;
	/// RelaxInstruction - Relax the instruction in the given fragment to the next		/// RelaxInstruction - Relax the instruction in the given fragment to the next
	/// wider instruction.		/// wider instruction.
	///		///
	/// \param Inst The instruction to relax, which may be the same as the		/// \param Inst The instruction to relax, which may be the same as the
	/// output.		/// output.
	/// \param [out] Res On return, the relaxed instruction.		/// \param [out] Res On return, the relaxed instruction.
	virtual void relaxInstruction(const MCInst &Inst, MCInst &Res) const = 0;		virtual void relaxInstruction(const MCInst &Inst, MCInst &Res) const = 0;
	skipping to change at line 163		skipping to change at line 163
	/// writeNopData - Write an (optimal) nop sequence of Count bytes to the given		/// writeNopData - Write an (optimal) nop sequence of Count bytes to the given
	/// output. If the target cannot generate such a sequence, it should retu rn an		/// output. If the target cannot generate such a sequence, it should retu rn an
	/// error.		/// error.
	///		///
	/// \return - True on success.		/// \return - True on success.
	virtual bool writeNopData(uint64_t Count, MCObjectWriter *OW) const = 0;		virtual bool writeNopData(uint64_t Count, MCObjectWriter *OW) const = 0;
	/// handleAssemblerFlag - Handle any target-specific assembler flags.		/// handleAssemblerFlag - Handle any target-specific assembler flags.
	/// By default, do nothing.		/// By default, do nothing.
	virtual void handleAssemblerFlag(MCAssemblerFlag Flag) {}		virtual void handleAssemblerFlag(MCAssemblerFlag Flag) {}
			/// \brief Generate the compact unwind encoding for the CFI instructions.
			virtual uint32_t
			generateCompactUnwindEncoding(ArrayRef<MCCFIInstruction>) const {
			return 0;
			}
	};		};
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 8 change blocks.
	7 lines changed or deleted		13 lines changed or added

	MCAsmInfo.h		MCAsmInfo.h
	skipping to change at line 20		skipping to change at line 20
	// This file contains a class to be used as the basis for target specific		// This file contains a class to be used as the basis for target specific
	// asm writers. This class primarily takes care of global printing constan ts,		// asm writers. This class primarily takes care of global printing constan ts,
	// which are used in very similar ways across all targets.		// which are used in very similar ways across all targets.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_MC_MCASMINFO_H		#ifndef LLVM_MC_MCASMINFO_H
	#define LLVM_MC_MCASMINFO_H		#define LLVM_MC_MCASMINFO_H
	#include "llvm/MC/MCDirectives.h"		#include "llvm/MC/MCDirectives.h"
			#include "llvm/MC/MCDwarf.h"
	#include "llvm/MC/MachineLocation.h"		#include "llvm/MC/MachineLocation.h"
	#include <cassert>		#include <cassert>
	#include <vector>		#include <vector>
	namespace llvm {		namespace llvm {
	class MCExpr;		class MCExpr;
	class MCSection;		class MCSection;
	class MCStreamer;		class MCStreamer;
	class MCSymbol;		class MCSymbol;
	class MCContext;		class MCContext;
	skipping to change at line 91		skipping to change at line 92
	/// LinkerRequiresNonEmptyDwarfLines - True if the linker has a bug and		/// LinkerRequiresNonEmptyDwarfLines - True if the linker has a bug and
	/// requires that the debug_line section be of a minimum size. In pract ice		/// requires that the debug_line section be of a minimum size. In pract ice
	/// such a linker requires a non empty line sequence if a file is prese nt.		/// such a linker requires a non empty line sequence if a file is prese nt.
	bool LinkerRequiresNonEmptyDwarfLines; // Default to false.		bool LinkerRequiresNonEmptyDwarfLines; // Default to false.
	/// MaxInstLength - This is the maximum possible length of an instructi on,		/// MaxInstLength - This is the maximum possible length of an instructi on,
	/// which is needed to compute the size of an inline asm.		/// which is needed to compute the size of an inline asm.
	unsigned MaxInstLength; // Defaults to 4.		unsigned MaxInstLength; // Defaults to 4.
	/// PCSymbol - The symbol used to represent the current PC. Used in PC		/// MinInstAlignment - Every possible instruction length is a multiple
	/// relative expressions.		of
	const char *PCSymbol; // Defaults to "$".		/// this value. Factored out in .debug_frame and .debug_line.
			unsigned MinInstAlignment; // Defaults to 1.
			/// DollarIsPC - The '$' token, when not referencing an identifier or
			/// constant, refers to the current PC.
			bool DollarIsPC; // Defaults to false.
	/// SeparatorString - This string, if specified, is used to separate		/// SeparatorString - This string, if specified, is used to separate
	/// instructions from each other when on the same line.		/// instructions from each other when on the same line.
	const char *SeparatorString; // Defaults to ';'		const char *SeparatorString; // Defaults to ';'
	/// CommentColumn - This indicates the comment num (zero-based) at		/// CommentColumn - This indicates the comment num (zero-based) at
	/// which asm comments should be printed.		/// which asm comments should be printed.
	unsigned CommentColumn; // Defaults to 40		unsigned CommentColumn; // Defaults to 40
	/// CommentString - This indicates the comment character used by the		/// CommentString - This indicates the comment character used by the
	skipping to change at line 142		skipping to change at line 147
	/// Code16Directive, Code32Directive, Code64Directive - These are assem bly		/// Code16Directive, Code32Directive, Code64Directive - These are assem bly
	/// directives that tells the assembler to interpret the following		/// directives that tells the assembler to interpret the following
	/// instructions differently.		/// instructions differently.
	const char *Code16Directive; // Defaults to ".code16"		const char *Code16Directive; // Defaults to ".code16"
	const char *Code32Directive; // Defaults to ".code32"		const char *Code32Directive; // Defaults to ".code32"
	const char *Code64Directive; // Defaults to ".code64"		const char *Code64Directive; // Defaults to ".code64"
	/// AssemblerDialect - Which dialect of an assembler variant to use.		/// AssemblerDialect - Which dialect of an assembler variant to use.
	unsigned AssemblerDialect; // Defaults to 0		unsigned AssemblerDialect; // Defaults to 0
	/// AllowQuotesInName - This is true if the assembler allows for comple		/// \brief This is true if the assembler allows @ characters in symbol
	x		/// names. Defaults to false.
	/// symbol names to be surrounded in quotes. This defaults to false.		bool AllowAtInName;
	bool AllowQuotesInName;
	/// AllowNameToStartWithDigit - This is true if the assembler allows sy
	mbol
	/// names to start with a digit (e.g., "0x0021"). This defaults to fal
	se.
	bool AllowNameToStartWithDigit;
	/// AllowPeriodsInName - This is true if the assembler allows periods i
	n
	/// symbol names. This defaults to true.
	bool AllowPeriodsInName;
	/// AllowUTF8 - This is true if the assembler accepts UTF-8 input.
	// FIXME: Make this a more general encoding setting?
	bool AllowUTF8;
	/// UseDataRegionDirectives - This is true if data region markers shoul d		/// UseDataRegionDirectives - This is true if data region markers shoul d
	/// be printed as ".data_region/.end_data_region" directives. If false,		/// be printed as ".data_region/.end_data_region" directives. If false,
	/// use "$d/$a" labels instead.		/// use "$d/$a" labels instead.
	bool UseDataRegionDirectives;		bool UseDataRegionDirectives;
	//===--- Data Emission Directives ------------------------------------- ===//		//===--- Data Emission Directives ------------------------------------- ===//
	/// ZeroDirective - this should be set to the directive used to get som e		/// ZeroDirective - this should be set to the directive used to get som e
	/// number of zero bytes emitted to the current section. Common cases are		/// number of zero bytes emitted to the current section. Common cases are
	skipping to change at line 198		skipping to change at line 191
	/// GPRel64Directive - if non-null, a directive that is used to emit a word		/// GPRel64Directive - if non-null, a directive that is used to emit a word
	/// which should be relocated as a 64-bit GP-relative offset, e.g. .gpd word		/// which should be relocated as a 64-bit GP-relative offset, e.g. .gpd word
	/// on Mips.		/// on Mips.
	const char *GPRel64Directive; // Defaults to NULL.		const char *GPRel64Directive; // Defaults to NULL.
	/// GPRel32Directive - if non-null, a directive that is used to emit a word		/// GPRel32Directive - if non-null, a directive that is used to emit a word
	/// which should be relocated as a 32-bit GP-relative offset, e.g. .gpw ord		/// which should be relocated as a 32-bit GP-relative offset, e.g. .gpw ord
	/// on Mips or .gprel32 on Alpha.		/// on Mips or .gprel32 on Alpha.
	const char *GPRel32Directive; // Defaults to NULL.		const char *GPRel32Directive; // Defaults to NULL.
	/// getDataASDirective - Return the directive that should be used to em
	it
	/// data of the specified size to the specified numeric address space.
	virtual const char *getDataASDirective(unsigned Size, unsigned AS) cons
	t {
	assert(AS != 0 && "Don't know the directives for default addr space")
	;
	return 0;
	}
	/// SunStyleELFSectionSwitchSyntax - This is true if this target uses " Sun		/// SunStyleELFSectionSwitchSyntax - This is true if this target uses " Sun
	/// Style" syntax for section switching ("#alloc,#write" etc) instead o f the		/// Style" syntax for section switching ("#alloc,#write" etc) instead o f the
	/// normal ELF syntax (,"a,w") in .section directives.		/// normal ELF syntax (,"a,w") in .section directives.
	bool SunStyleELFSectionSwitchSyntax; // Defaults to false.		bool SunStyleELFSectionSwitchSyntax; // Defaults to false.
	/// UsesELFSectionDirectiveForBSS - This is true if this target uses EL F		/// UsesELFSectionDirectiveForBSS - This is true if this target uses EL F
	/// '.section' directive before the '.bss' one. It's used for PPC/Linux		/// '.section' directive before the '.bss' one. It's used for PPC/Linux
	/// which doesn't support the '.bss' directive only.		/// which doesn't support the '.bss' directive only.
	bool UsesELFSectionDirectiveForBSS; // Defaults to false.		bool UsesELFSectionDirectiveForBSS; // Defaults to false.
	skipping to change at line 245		skipping to change at line 231
	/// TextAlignFillValue - If non-zero, this is used to fill the executab le		/// TextAlignFillValue - If non-zero, this is used to fill the executab le
	/// space created as the result of a alignment directive.		/// space created as the result of a alignment directive.
	unsigned TextAlignFillValue; // Defaults to 0		unsigned TextAlignFillValue; // Defaults to 0
	//===--- Global Variable Emission Directives -------------------------- ===//		//===--- Global Variable Emission Directives -------------------------- ===//
	/// GlobalDirective - This is the directive used to declare a global en tity.		/// GlobalDirective - This is the directive used to declare a global en tity.
	///		///
	const char *GlobalDirective; // Defaults to NULL.		const char *GlobalDirective; // Defaults to NULL.
	/// ExternDirective - This is the directive used to declare external
	/// globals.
	///
	const char *ExternDirective; // Defaults to NULL.
	/// HasSetDirective - True if the assembler supports the .set directive .		/// HasSetDirective - True if the assembler supports the .set directive .
	bool HasSetDirective; // Defaults to true.		bool HasSetDirective; // Defaults to true.
	/// HasAggressiveSymbolFolding - False if the assembler requires that w e use		/// HasAggressiveSymbolFolding - False if the assembler requires that w e use
	/// Lc = a - b		/// Lc = a - b
	/// .long Lc		/// .long Lc
	/// instead of		/// instead of
	/// .long a - b		/// .long a - b
	bool HasAggressiveSymbolFolding; // Defaults to true.		bool HasAggressiveSymbolFolding; // Defaults to true.
	skipping to change at line 276		skipping to change at line 257
	LCOMM::LCOMMType LCOMMDirectiveAlignmentType; // Defaults to NoAlignmen t.		LCOMM::LCOMMType LCOMMDirectiveAlignmentType; // Defaults to NoAlignmen t.
	/// HasDotTypeDotSizeDirective - True if the target has .type and .size		/// HasDotTypeDotSizeDirective - True if the target has .type and .size
	/// directives, this is true for most ELF targets.		/// directives, this is true for most ELF targets.
	bool HasDotTypeDotSizeDirective; // Defaults to true.		bool HasDotTypeDotSizeDirective; // Defaults to true.
	/// HasSingleParameterDotFile - True if the target has a single paramet er		/// HasSingleParameterDotFile - True if the target has a single paramet er
	/// .file directive, this is true for ELF targets.		/// .file directive, this is true for ELF targets.
	bool HasSingleParameterDotFile; // Defaults to true.		bool HasSingleParameterDotFile; // Defaults to true.
			/// hasIdentDirective - True if the target has a .ident directive, this
			is
			/// true for ELF targets.
			bool HasIdentDirective; // Defaults to false.
	/// HasNoDeadStrip - True if this target supports the MachO .no_dead_st rip		/// HasNoDeadStrip - True if this target supports the MachO .no_dead_st rip
	/// directive.		/// directive.
	bool HasNoDeadStrip; // Defaults to false.		bool HasNoDeadStrip; // Defaults to false.
	/// HasSymbolResolver - True if this target supports the MachO
	/// .symbol_resolver directive.
	bool HasSymbolResolver; // Defaults to false.
	/// WeakRefDirective - This directive, if non-null, is used to declare a		/// WeakRefDirective - This directive, if non-null, is used to declare a
	/// global as being a weak undefined symbol.		/// global as being a weak undefined symbol.
	const char *WeakRefDirective; // Defaults to NULL.		const char *WeakRefDirective; // Defaults to NULL.
	/// WeakDefDirective - This directive, if non-null, is used to declare a		/// WeakDefDirective - This directive, if non-null, is used to declare a
	/// global as being a weak defined symbol.		/// global as being a weak defined symbol.
	const char *WeakDefDirective; // Defaults to NULL.		const char *WeakDefDirective; // Defaults to NULL.
	/// LinkOnceDirective - This directive, if non-null is used to declare a		/// LinkOnceDirective - This directive, if non-null is used to declare a
	/// global as being a weak defined symbol. This is used on cygwin/ming w.		/// global as being a weak defined symbol. This is used on cygwin/ming w.
	skipping to change at line 320		skipping to change at line 301
	/// HasLEB128 - True if target asm supports leb128 directives.		/// HasLEB128 - True if target asm supports leb128 directives.
	bool HasLEB128; // Defaults to false.		bool HasLEB128; // Defaults to false.
	/// SupportsDebugInformation - True if target supports emission of debu gging		/// SupportsDebugInformation - True if target supports emission of debu gging
	/// information.		/// information.
	bool SupportsDebugInformation; // Defaults to false.		bool SupportsDebugInformation; // Defaults to false.
	/// SupportsExceptionHandling - True if target supports exception handl ing.		/// SupportsExceptionHandling - True if target supports exception handl ing.
	ExceptionHandling::ExceptionsType ExceptionsType; // Defaults to None		ExceptionHandling::ExceptionsType ExceptionsType; // Defaults to None
	/// DwarfUsesInlineInfoSection - True if DwarfDebugInlineSection is use
	d to
	/// encode inline subroutine information.
	bool DwarfUsesInlineInfoSection; // Defaults to false.
	/// DwarfUsesRelocationsAcrossSections - True if Dwarf2 output generall y		/// DwarfUsesRelocationsAcrossSections - True if Dwarf2 output generall y
	/// uses relocations for references to other .debug_* sections.		/// uses relocations for references to other .debug_* sections.
	bool DwarfUsesRelocationsAcrossSections;		bool DwarfUsesRelocationsAcrossSections;
	/// DwarfRegNumForCFI - True if dwarf register numbers are printed		/// DwarfRegNumForCFI - True if dwarf register numbers are printed
	/// instead of symbolic register names in .cfi_* directives.		/// instead of symbolic register names in .cfi_* directives.
	bool DwarfRegNumForCFI; // Defaults to false;		bool DwarfRegNumForCFI; // Defaults to false;
	//===--- Prologue State ----------------------------------------------= ==//		//===--- Prologue State ----------------------------------------------= ==//
	std::vector<MachineMove> InitialFrameState;		std::vector<MCCFIInstruction> InitialFrameState;
	public:		public:
	explicit MCAsmInfo();		explicit MCAsmInfo();
	virtual ~MCAsmInfo();		virtual ~MCAsmInfo();
	// FIXME: move these methods to DwarfPrinter when the JIT stops using t hem.		// FIXME: move these methods to DwarfPrinter when the JIT stops using t hem.
	static unsigned getSLEB128Size(int Value);		static unsigned getSLEB128Size(int64_t Value);
	static unsigned getULEB128Size(unsigned Value);		static unsigned getULEB128Size(uint64_t Value);
	/// getPointerSize - Get the pointer size in bytes.		/// getPointerSize - Get the pointer size in bytes.
	unsigned getPointerSize() const {		unsigned getPointerSize() const {
	return PointerSize;		return PointerSize;
	}		}
	/// getCalleeSaveStackSlotSize - Get the callee-saved register stack sl ot		/// getCalleeSaveStackSlotSize - Get the callee-saved register stack sl ot
	/// size in bytes.		/// size in bytes.
	unsigned getCalleeSaveStackSlotSize() const {		unsigned getCalleeSaveStackSlotSize() const {
	return CalleeSaveStackSlotSize;		return CalleeSaveStackSlotSize;
	skipping to change at line 369		skipping to change at line 346
	/// isStackGrowthDirectionUp - True if target stack grow up.		/// isStackGrowthDirectionUp - True if target stack grow up.
	bool isStackGrowthDirectionUp() const {		bool isStackGrowthDirectionUp() const {
	return StackGrowsUp;		return StackGrowsUp;
	}		}
	bool hasSubsectionsViaSymbols() const { return HasSubsectionsViaSymbols ; }		bool hasSubsectionsViaSymbols() const { return HasSubsectionsViaSymbols ; }
	// Data directive accessors.		// Data directive accessors.
	//		//
	const char *getData8bitsDirective(unsigned AS = 0) const {		const char *getData8bitsDirective() const {
	return AS == 0 ? Data8bitsDirective : getDataASDirective(8, AS);		return Data8bitsDirective;
	}		}
	const char *getData16bitsDirective(unsigned AS = 0) const {		const char *getData16bitsDirective() const {
	return AS == 0 ? Data16bitsDirective : getDataASDirective(16, AS);		return Data16bitsDirective;
	}		}
	const char *getData32bitsDirective(unsigned AS = 0) const {		const char *getData32bitsDirective() const {
	return AS == 0 ? Data32bitsDirective : getDataASDirective(32, AS);		return Data32bitsDirective;
	}		}
	const char *getData64bitsDirective(unsigned AS = 0) const {		const char *getData64bitsDirective() const {
	return AS == 0 ? Data64bitsDirective : getDataASDirective(64, AS);		return Data64bitsDirective;
	}		}
	const char *getGPRel64Directive() const { return GPRel64Directive; }		const char *getGPRel64Directive() const { return GPRel64Directive; }
	const char *getGPRel32Directive() const { return GPRel32Directive; }		const char *getGPRel32Directive() const { return GPRel32Directive; }
	/// getNonexecutableStackSection - Targets can implement this method to		/// getNonexecutableStackSection - Targets can implement this method to
	/// specify a section to switch to if the translation unit doesn't have any		/// specify a section to switch to if the translation unit doesn't have any
	/// trampolines that require an executable stack.		/// trampolines that require an executable stack.
	virtual const MCSection *getNonexecutableStackSection(MCContext &Ctx) c onst{		virtual const MCSection *getNonexecutableStackSection(MCContext &Ctx) c onst{
	return 0;		return 0;
	}		}
	skipping to change at line 430		skipping to change at line 407
	bool hasMachoTBSSDirective() const { return HasMachoTBSSDirective; }		bool hasMachoTBSSDirective() const { return HasMachoTBSSDirective; }
	bool hasStaticCtorDtorReferenceInStaticMode() const {		bool hasStaticCtorDtorReferenceInStaticMode() const {
	return HasStaticCtorDtorReferenceInStaticMode;		return HasStaticCtorDtorReferenceInStaticMode;
	}		}
	bool getLinkerRequiresNonEmptyDwarfLines() const {		bool getLinkerRequiresNonEmptyDwarfLines() const {
	return LinkerRequiresNonEmptyDwarfLines;		return LinkerRequiresNonEmptyDwarfLines;
	}		}
	unsigned getMaxInstLength() const {		unsigned getMaxInstLength() const {
	return MaxInstLength;		return MaxInstLength;
	}		}
	const char *getPCSymbol() const {		unsigned getMinInstAlignment() const {
	return PCSymbol;		return MinInstAlignment;
			}
			bool getDollarIsPC() const {
			return DollarIsPC;
	}		}
	const char *getSeparatorString() const {		const char *getSeparatorString() const {
	return SeparatorString;		return SeparatorString;
	}		}
	unsigned getCommentColumn() const {		unsigned getCommentColumn() const {
	return CommentColumn;		return CommentColumn;
	}		}
	const char *getCommentString() const {		const char *getCommentString() const {
	return CommentString;		return CommentString;
	}		}
	skipping to change at line 477		skipping to change at line 457
	}		}
	const char *getCode32Directive() const {		const char *getCode32Directive() const {
	return Code32Directive;		return Code32Directive;
	}		}
	const char *getCode64Directive() const {		const char *getCode64Directive() const {
	return Code64Directive;		return Code64Directive;
	}		}
	unsigned getAssemblerDialect() const {		unsigned getAssemblerDialect() const {
	return AssemblerDialect;		return AssemblerDialect;
	}		}
	bool doesAllowQuotesInName() const {		bool doesAllowAtInName() const {
	return AllowQuotesInName;		return AllowAtInName;
	}
	bool doesAllowNameToStartWithDigit() const {
	return AllowNameToStartWithDigit;
	}
	bool doesAllowPeriodsInName() const {
	return AllowPeriodsInName;
	}
	bool doesAllowUTF8() const {
	return AllowUTF8;
	}		}
	bool doesSupportDataRegionDirectives() const {		bool doesSupportDataRegionDirectives() const {
	return UseDataRegionDirectives;		return UseDataRegionDirectives;
	}		}
	const char *getZeroDirective() const {		const char *getZeroDirective() const {
	return ZeroDirective;		return ZeroDirective;
	}		}
	const char *getAsciiDirective() const {		const char *getAsciiDirective() const {
	return AsciiDirective;		return AsciiDirective;
	}		}
	skipping to change at line 513		skipping to change at line 484
	}		}
	bool getAlignmentIsInBytes() const {		bool getAlignmentIsInBytes() const {
	return AlignmentIsInBytes;		return AlignmentIsInBytes;
	}		}
	unsigned getTextAlignFillValue() const {		unsigned getTextAlignFillValue() const {
	return TextAlignFillValue;		return TextAlignFillValue;
	}		}
	const char *getGlobalDirective() const {		const char *getGlobalDirective() const {
	return GlobalDirective;		return GlobalDirective;
	}		}
	const char *getExternDirective() const {
	return ExternDirective;
	}
	bool hasSetDirective() const { return HasSetDirective; }		bool hasSetDirective() const { return HasSetDirective; }
	bool hasAggressiveSymbolFolding() const {		bool hasAggressiveSymbolFolding() const {
	return HasAggressiveSymbolFolding;		return HasAggressiveSymbolFolding;
	}		}
	bool getCOMMDirectiveAlignmentIsInBytes() const {		bool getCOMMDirectiveAlignmentIsInBytes() const {
	return COMMDirectiveAlignmentIsInBytes;		return COMMDirectiveAlignmentIsInBytes;
	}		}
	LCOMM::LCOMMType getLCOMMDirectiveAlignmentType() const {		LCOMM::LCOMMType getLCOMMDirectiveAlignmentType() const {
	return LCOMMDirectiveAlignmentType;		return LCOMMDirectiveAlignmentType;
	}		}
	bool hasDotTypeDotSizeDirective() const {return HasDotTypeDotSizeDirect ive;}		bool hasDotTypeDotSizeDirective() const {return HasDotTypeDotSizeDirect ive;}
	bool hasSingleParameterDotFile() const { return HasSingleParameterDotFi le; }		bool hasSingleParameterDotFile() const { return HasSingleParameterDotFi le; }
			bool hasIdentDirective() const { return HasIdentDirective; }
	bool hasNoDeadStrip() const { return HasNoDeadStrip; }		bool hasNoDeadStrip() const { return HasNoDeadStrip; }
	bool hasSymbolResolver() const { return HasSymbolResolver; }
	const char *getWeakRefDirective() const { return WeakRefDirective; }		const char *getWeakRefDirective() const { return WeakRefDirective; }
	const char *getWeakDefDirective() const { return WeakDefDirective; }		const char *getWeakDefDirective() const { return WeakDefDirective; }
	const char *getLinkOnceDirective() const { return LinkOnceDirective; }		const char *getLinkOnceDirective() const { return LinkOnceDirective; }
	MCSymbolAttr getHiddenVisibilityAttr() const { return HiddenVisibilityA ttr;}		MCSymbolAttr getHiddenVisibilityAttr() const { return HiddenVisibilityA ttr;}
	MCSymbolAttr getHiddenDeclarationVisibilityAttr() const {		MCSymbolAttr getHiddenDeclarationVisibilityAttr() const {
	return HiddenDeclarationVisibilityAttr;		return HiddenDeclarationVisibilityAttr;
	}		}
	MCSymbolAttr getProtectedVisibilityAttr() const {		MCSymbolAttr getProtectedVisibilityAttr() const {
	return ProtectedVisibilityAttr;		return ProtectedVisibilityAttr;
	skipping to change at line 559		skipping to change at line 527
	}		}
	ExceptionHandling::ExceptionsType getExceptionHandlingType() const {		ExceptionHandling::ExceptionsType getExceptionHandlingType() const {
	return ExceptionsType;		return ExceptionsType;
	}		}
	bool isExceptionHandlingDwarf() const {		bool isExceptionHandlingDwarf() const {
	return		return
	(ExceptionsType == ExceptionHandling::DwarfCFI ||		(ExceptionsType == ExceptionHandling::DwarfCFI ||
	ExceptionsType == ExceptionHandling::ARM ||		ExceptionsType == ExceptionHandling::ARM ||
	ExceptionsType == ExceptionHandling::Win64);		ExceptionsType == ExceptionHandling::Win64);
	}		}
	bool doesDwarfUseInlineInfoSection() const {
	return DwarfUsesInlineInfoSection;
	}
	bool doesDwarfUseRelocationsAcrossSections() const {		bool doesDwarfUseRelocationsAcrossSections() const {
	return DwarfUsesRelocationsAcrossSections;		return DwarfUsesRelocationsAcrossSections;
	}		}
	bool useDwarfRegNumForCFI() const {		bool useDwarfRegNumForCFI() const {
	return DwarfRegNumForCFI;		return DwarfRegNumForCFI;
	}		}
	void addInitialFrameState(MCSymbol *label, const MachineLocation &D,		void addInitialFrameState(const MCCFIInstruction &Inst) {
	const MachineLocation &S) {		InitialFrameState.push_back(Inst);
	InitialFrameState.push_back(MachineMove(label, D, S));
	}		}
	const std::vector<MachineMove> &getInitialFrameState() const {
			const std::vector<MCCFIInstruction> &getInitialFrameState() const {
	return InitialFrameState;		return InitialFrameState;
	}		}
	};		};
	}		}
	#endif		#endif
End of changes. 22 change blocks.
	81 lines changed or deleted		40 lines changed or added

	MCAssembler.h		MCAssembler.h
	skipping to change at line 22		skipping to change at line 22
	#include "llvm/ADT/DenseMap.h"		#include "llvm/ADT/DenseMap.h"
	#include "llvm/ADT/SmallPtrSet.h"		#include "llvm/ADT/SmallPtrSet.h"
	#include "llvm/ADT/SmallString.h"		#include "llvm/ADT/SmallString.h"
	#include "llvm/ADT/ilist.h"		#include "llvm/ADT/ilist.h"
	#include "llvm/ADT/ilist_node.h"		#include "llvm/ADT/ilist_node.h"
	#include "llvm/MC/MCFixup.h"		#include "llvm/MC/MCFixup.h"
	#include "llvm/MC/MCInst.h"		#include "llvm/MC/MCInst.h"
	#include "llvm/Support/Casting.h"		#include "llvm/Support/Casting.h"
	#include "llvm/Support/DataTypes.h"		#include "llvm/Support/DataTypes.h"
			#include <algorithm>
	#include <vector> // FIXME: Shouldn't be needed.		#include <vector> // FIXME: Shouldn't be needed.
	namespace llvm {		namespace llvm {
	class raw_ostream;		class raw_ostream;
	class MCAsmLayout;		class MCAsmLayout;
	class MCAssembler;		class MCAssembler;
	class MCContext;		class MCContext;
	class MCCodeEmitter;		class MCCodeEmitter;
	class MCExpr;		class MCExpr;
	class MCFragment;		class MCFragment;
	skipping to change at line 818		skipping to change at line 819
	public:		public:
	typedef iplist<MCSectionData> SectionDataListType;		typedef iplist<MCSectionData> SectionDataListType;
	typedef iplist<MCSymbolData> SymbolDataListType;		typedef iplist<MCSymbolData> SymbolDataListType;
	typedef SectionDataListType::const_iterator const_iterator;		typedef SectionDataListType::const_iterator const_iterator;
	typedef SectionDataListType::iterator iterator;		typedef SectionDataListType::iterator iterator;
	typedef SymbolDataListType::const_iterator const_symbol_iterator;		typedef SymbolDataListType::const_iterator const_symbol_iterator;
	typedef SymbolDataListType::iterator symbol_iterator;		typedef SymbolDataListType::iterator symbol_iterator;
			typedef std::vector<std::string> FileNameVectorType;
			typedef FileNameVectorType::const_iterator const_file_name_iterator;
	typedef std::vector<IndirectSymbolData>::const_iterator		typedef std::vector<IndirectSymbolData>::const_iterator
	const_indirect_symbol_iterator;		const_indirect_symbol_iterator;
	typedef std::vector<IndirectSymbolData>::iterator indirect_symbol_iterato r;		typedef std::vector<IndirectSymbolData>::iterator indirect_symbol_iterato r;
	typedef std::vector<DataRegionData>::const_iterator		typedef std::vector<DataRegionData>::const_iterator
	const_data_region_iterator;		const_data_region_iterator;
	typedef std::vector<DataRegionData>::iterator data_region_iterator;		typedef std::vector<DataRegionData>::iterator data_region_iterator;
	private:		private:
	MCAssembler(const MCAssembler&) LLVM_DELETED_FUNCTION;		MCAssembler(const MCAssembler&) LLVM_DELETED_FUNCTION;
	skipping to change at line 861		skipping to change at line 865
	// FIXME: Avoid this indirection?		// FIXME: Avoid this indirection?
	DenseMap<const MCSymbol*, MCSymbolData*> SymbolMap;		DenseMap<const MCSymbol*, MCSymbolData*> SymbolMap;
	std::vector<IndirectSymbolData> IndirectSymbols;		std::vector<IndirectSymbolData> IndirectSymbols;
	std::vector<DataRegionData> DataRegions;		std::vector<DataRegionData> DataRegions;
	/// The list of linker options to propagate into the object file.		/// The list of linker options to propagate into the object file.
	std::vector<std::vector<std::string> > LinkerOptions;		std::vector<std::vector<std::string> > LinkerOptions;
			/// List of declared file names
			FileNameVectorType FileNames;
	/// The set of function symbols for which a .thumb_func directive has		/// The set of function symbols for which a .thumb_func directive has
	/// been seen.		/// been seen.
	//		//
	// FIXME: We really would like this in target specific code rather than		// FIXME: We really would like this in target specific code rather than
	// here. Maybe when the relocation stuff moves to target specific,		// here. Maybe when the relocation stuff moves to target specific,
	// this can go with it? The streamer would need some target specific		// this can go with it? The streamer would need some target specific
	// refactoring too.		// refactoring too.
	SmallPtrSet<const MCSymbol*, 64> ThumbFuncs;		SmallPtrSet<const MCSymbol*, 64> ThumbFuncs;
	/// \brief The bundle alignment size currently set in the assembler.		/// \brief The bundle alignment size currently set in the assembler.
	skipping to change at line 1154		skipping to change at line 1161
	bool *Created = 0) {		bool *Created = 0) {
	MCSymbolData *&Entry = SymbolMap[&Symbol];		MCSymbolData *&Entry = SymbolMap[&Symbol];
	if (Created) *Created = !Entry;		if (Created) *Created = !Entry;
	if (!Entry)		if (!Entry)
	Entry = new MCSymbolData(Symbol, 0, 0, this);		Entry = new MCSymbolData(Symbol, 0, 0, this);
	return *Entry;		return *Entry;
	}		}
			const_file_name_iterator file_names_begin() const {
			return FileNames.begin();
			}
			const_file_name_iterator file_names_end() const {
			return FileNames.end();
			}
			void addFileName(StringRef FileName) {
			if (std::find(file_names_begin(), file_names_end(), FileName) ==
			file_names_end())
			FileNames.push_back(FileName);
			}
	/// @}		/// @}
	void dump();		void dump();
	};		};
	} // end namespace llvm		} // end namespace llvm
	#endif		#endif
End of changes. 4 change blocks.
	0 lines changed or deleted		21 lines changed or added

	MCAtom.h		MCAtom.h
	//===-- llvm/MC/MCAtom.h - MCAtom class ---------------------*- C++ -*-===/ /		//===-- llvm/MC/MCAtom.h ----------------------------------------*- C++ -*- ===//
	//		//
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This file contains the declaration of the MCAtom class, which is used to		// This file contains the declaration of the MCAtom class, which is used to
	// represent a contiguous region in a decoded object that is uniformly data or		// represent a contiguous region in a decoded object that is uniformly data or
	// instructions;		// instructions.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_MC_MCATOM_H		#ifndef LLVM_MC_MCATOM_H
	#define LLVM_MC_MCATOM_H		#define LLVM_MC_MCATOM_H
			#include "llvm/ADT/ArrayRef.h"
	#include "llvm/MC/MCInst.h"		#include "llvm/MC/MCInst.h"
	#include "llvm/Support/DataTypes.h"		#include "llvm/Support/DataTypes.h"
	#include <vector>		#include <vector>
	namespace llvm {		namespace llvm {
	class MCModule;		class MCModule;
	/// MCData - An entry in a data MCAtom.		class MCAtom;
	// NOTE: This may change to a more complex type in the future.		class MCTextAtom;
	typedef uint8_t MCData;		class MCDataAtom;
	/// MCAtom - Represents a contiguous range of either instructions (a TextAt om)		/// \brief Represents a contiguous range of either instructions (a TextAtom )
	/// or data (a DataAtom). Address ranges are expressed as _closed_ interva ls.		/// or data (a DataAtom). Address ranges are expressed as _closed_ interva ls.
	class MCAtom {		class MCAtom {
	friend class MCModule;		virtual void anchor();
	typedef enum { TextAtom, DataAtom } AtomType;		public:
			virtual ~MCAtom() {}
	AtomType Type;		enum AtomKind { TextAtom, DataAtom };
			AtomKind getKind() const { return Kind; }
			/// \brief Get the start address of the atom.
			uint64_t getBeginAddr() const { return Begin; }
			/// \brief Get the end address, i.e. the last one inside the atom.
			uint64_t getEndAddr() const { return End; }
			/// \name Atom modification methods:
			/// When modifying a TextAtom, keep instruction boundaries in mind.
			/// For instance, split must me given the start address of an instruction
			.
			/// @{
			/// \brief Splits the atom in two at a given address.
			/// \param SplitPt Address at which to start a new atom, splitting this o
			ne.
			/// \returns The newly created atom starting at \p SplitPt.
			virtual MCAtom *split(uint64_t SplitPt) = 0;
			/// \brief Truncates an atom, discarding everything after \p TruncPt.
			/// \param TruncPt Last byte address to be contained in this atom.
			virtual void truncate(uint64_t TruncPt) = 0;
			/// @}
			/// \name Naming:
			///
			/// This is mostly for display purposes, and may contain anything that hi
			nts
			/// at what the atom contains: section or symbol name, BB start address,
			..
			/// @{
			StringRef getName() const { return Name; }
			void setName(StringRef NewName) { Name = NewName.str(); }
			/// @}
			protected:
			const AtomKind Kind;
			std::string Name;
	MCModule *Parent;		MCModule *Parent;
	uint64_t Begin, End;		uint64_t Begin, End;
	std::vector<std::pair<uint64_t, MCInst> > Text;		friend class MCModule;
	std::vector<MCData> Data;		MCAtom(AtomKind K, MCModule *P, uint64_t B, uint64_t E)
			: Kind(K), Name("(unknown)"), Parent(P), Begin(B), End(E) { }
	// Private constructor - only callable by MCModule		/// \name Atom remapping helpers
	MCAtom(AtomType T, MCModule *P, uint64_t B, uint64_t E)		/// @{
	: Type(T), Parent(P), Begin(B), End(E) { }
			/// \brief Remap the atom, using the given range, updating Begin/End.
			/// One or both of the bounds can remain the same, but overlapping with o
			ther
			/// atoms in the module is still forbidden.
			void remap(uint64_t NewBegin, uint64_t NewEnd);
			/// \brief Remap the atom to prepare for a truncation at TruncPt.
			/// Equivalent to:
			/// \code
			/// // Bound checks
			/// remap(Begin, TruncPt);
			/// \endcode
			void remapForTruncate(uint64_t TruncPt);
			/// \brief Remap the atom to prepare for a split at SplitPt.
			/// The bounds for the resulting atoms are returned in {L,R}{Begin,End}.
			/// The current atom is truncated to \p LEnd.
			void remapForSplit(uint64_t SplitPt,
			uint64_t &LBegin, uint64_t &LEnd,
			uint64_t &RBegin, uint64_t &REnd);
			/// @}
			};
			/// \name Text atom
			/// @{
			/// \brief An entry in an MCTextAtom: a disassembled instruction.
			/// NOTE: Both the Address and Size field are actually redundant when taken
			in
			/// the context of the text atom, and may better be exposed in an iterator
			/// instead of stored in the atom, which would replace this class.
			class MCDecodedInst {
			public:
			MCInst Inst;
			uint64_t Address;
			uint64_t Size;
			MCDecodedInst(const MCInst &Inst, uint64_t Address, uint64_t Size)
			: Inst(Inst), Address(Address), Size(Size) {}
			};
			/// \brief An atom consisting of disassembled instructions.
			class MCTextAtom : public MCAtom {
			private:
			typedef std::vector<MCDecodedInst> InstListTy;
			InstListTy Insts;
			/// \brief The address of the next appended instruction, i.e., the
			/// address immediately after the last instruction in the atom.
			uint64_t NextInstAddress;
	public:		public:
	bool isTextAtom() const { return Type == TextAtom; }		/// Append an instruction, expanding the atom if necessary.
	bool isDataAtom() const { return Type == DataAtom; }		void addInst(const MCInst &Inst, uint64_t Size);
	void addInst(const MCInst &I, uint64_t Address, unsigned Size);		/// \name Instruction list access
			/// @{
			typedef InstListTy::const_iterator const_iterator;
			const_iterator begin() const { return Insts.begin(); }
			const_iterator end() const { return Insts.end(); }
			const MCDecodedInst &back() const { return Insts.back(); }
			const MCDecodedInst &at(size_t n) const { return Insts.at(n); }
			size_t size() const { return Insts.size(); }
			/// @}
			/// \name Atom type specific split/truncate logic.
			/// @{
			MCTextAtom *split(uint64_t SplitPt) LLVM_OVERRIDE;
			void truncate(uint64_t TruncPt) LLVM_OVERRIDE;
			/// @}
			// Class hierarchy.
			static bool classof(const MCAtom *A) { return A->getKind() == TextAtom; }
			private:
			friend class MCModule;
			// Private constructor - only callable by MCModule
			MCTextAtom(MCModule *P, uint64_t Begin, uint64_t End)
			: MCAtom(TextAtom, P, Begin, End), NextInstAddress(Begin) {}
			};
			/// @}
			/// \name Data atom
			/// @{
			/// \brief An entry in an MCDataAtom.
			// NOTE: This may change to a more complex type in the future.
			typedef uint8_t MCData;
			/// \brief An atom consising of a sequence of bytes.
			class MCDataAtom : public MCAtom {
			std::vector<MCData> Data;
			public:
			/// Append a data entry, expanding the atom if necessary.
	void addData(const MCData &D);		void addData(const MCData &D);
	/// split - Splits the atom in two at a given address, which must align w		/// Get a reference to the data in this atom.
	ith		ArrayRef<MCData> getData() const { return Data; }
	/// and instruction boundary if this is a TextAtom. Returns the newly cr
	eated		/// \name Atom type specific split/truncate logic.
	/// atom representing the high part of the split.		/// @{
	MCAtom *split(uint64_t SplitPt);		MCDataAtom *split(uint64_t SplitPt) LLVM_OVERRIDE;
			void truncate(uint64_t TruncPt) LLVM_OVERRIDE;
	/// truncate - Truncates an atom so that TruncPt is the last byte address		/// @}
	/// contained in the atom.
	void truncate(uint64_t TruncPt);		// Class hierarchy.
			static bool classof(const MCAtom *A) { return A->getKind() == DataAtom; }
			private:
			friend class MCModule;
			// Private constructor - only callable by MCModule
			MCDataAtom(MCModule *P, uint64_t Begin, uint64_t End)
			: MCAtom(DataAtom, P, Begin, End) {
			Data.reserve(End + 1 - Begin);
			}
	};		};
	}		}
	#endif		#endif
End of changes. 13 change blocks.
	27 lines changed or deleted		163 lines changed or added

	MCCodeGenInfo.h		MCCodeGenInfo.h
	skipping to change at line 45		skipping to change at line 45
	public:		public:
	void InitMCCodeGenInfo(Reloc::Model RM = Reloc::Default,		void InitMCCodeGenInfo(Reloc::Model RM = Reloc::Default,
	CodeModel::Model CM = CodeModel::Default,		CodeModel::Model CM = CodeModel::Default,
	CodeGenOpt::Level OL = CodeGenOpt::Default);		CodeGenOpt::Level OL = CodeGenOpt::Default);
	Reloc::Model getRelocationModel() const { return RelocationModel; }		Reloc::Model getRelocationModel() const { return RelocationModel; }
	CodeModel::Model getCodeModel() const { return CMModel; }		CodeModel::Model getCodeModel() const { return CMModel; }
	CodeGenOpt::Level getOptLevel() const { return OptLevel; }		CodeGenOpt::Level getOptLevel() const { return OptLevel; }
			// Allow overriding OptLevel on a per-function basis.
			void setOptLevel(CodeGenOpt::Level Level) { OptLevel = Level; }
	};		};
	} // namespace llvm		} // namespace llvm
	#endif		#endif
End of changes. 1 change blocks.
	0 lines changed or deleted		3 lines changed or added

	MCContext.h		MCContext.h
	skipping to change at line 14		skipping to change at line 14
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_MC_MCCONTEXT_H		#ifndef LLVM_MC_MCCONTEXT_H
	#define LLVM_MC_MCCONTEXT_H		#define LLVM_MC_MCCONTEXT_H
	#include "llvm/ADT/DenseMap.h"		#include "llvm/ADT/DenseMap.h"
			#include "llvm/ADT/SmallString.h"
	#include "llvm/ADT/SmallVector.h"		#include "llvm/ADT/SmallVector.h"
	#include "llvm/ADT/StringMap.h"		#include "llvm/ADT/StringMap.h"
	#include "llvm/MC/MCDwarf.h"		#include "llvm/MC/MCDwarf.h"
	#include "llvm/MC/SectionKind.h"		#include "llvm/MC/SectionKind.h"
	#include "llvm/Support/Allocator.h"		#include "llvm/Support/Allocator.h"
	#include "llvm/Support/Compiler.h"		#include "llvm/Support/Compiler.h"
	#include "llvm/Support/raw_ostream.h"		#include "llvm/Support/raw_ostream.h"
	#include <map>		#include <map>
	#include <vector> // FIXME: Shouldn't be needed.		#include <vector> // FIXME: Shouldn't be needed.
	skipping to change at line 40		skipping to change at line 41
	class MCDwarfFile;		class MCDwarfFile;
	class MCDwarfLoc;		class MCDwarfLoc;
	class MCObjectFileInfo;		class MCObjectFileInfo;
	class MCRegisterInfo;		class MCRegisterInfo;
	class MCLineSection;		class MCLineSection;
	class SMLoc;		class SMLoc;
	class StringRef;		class StringRef;
	class Twine;		class Twine;
	class MCSectionMachO;		class MCSectionMachO;
	class MCSectionELF;		class MCSectionELF;
			class MCSectionCOFF;
	/// MCContext - Context object for machine code objects. This class owns all		/// MCContext - Context object for machine code objects. This class owns all
	/// of the sections that it creates.		/// of the sections that it creates.
	///		///
	class MCContext {		class MCContext {
	MCContext(const MCContext&) LLVM_DELETED_FUNCTION;		MCContext(const MCContext&) LLVM_DELETED_FUNCTION;
	MCContext &operator=(const MCContext&) LLVM_DELETED_FUNCTION;		MCContext &operator=(const MCContext&) LLVM_DELETED_FUNCTION;
	public:		public:
	typedef StringMap<MCSymbol*, BumpPtrAllocator&> SymbolTable;		typedef StringMap<MCSymbol*, BumpPtrAllocator&> SymbolTable;
	private:		private:
	/// The SourceMgr for this object, if any.		/// The SourceMgr for this object, if any.
	const SourceMgr *SrcMgr;		const SourceMgr *SrcMgr;
	/// The MCAsmInfo for this target.		/// The MCAsmInfo for this target.
	const MCAsmInfo &MAI;		const MCAsmInfo *MAI;
	/// The MCRegisterInfo for this target.		/// The MCRegisterInfo for this target.
	const MCRegisterInfo &MRI;		const MCRegisterInfo *MRI;
	/// The MCObjectFileInfo for this target.		/// The MCObjectFileInfo for this target.
	const MCObjectFileInfo *MOFI;		const MCObjectFileInfo *MOFI;
	/// Allocator - Allocator object used for creating machine code objects .		/// Allocator - Allocator object used for creating machine code objects .
	///		///
	/// We use a bump pointer allocator to avoid the need to track all allo cated		/// We use a bump pointer allocator to avoid the need to track all allo cated
	/// objects.		/// objects.
	BumpPtrAllocator Allocator;		BumpPtrAllocator Allocator;
	skipping to change at line 100		skipping to change at line 102
	/// directive is used or it is an error.		/// directive is used or it is an error.
	char *SecureLogFile;		char *SecureLogFile;
	/// The stream that gets written to for the .secure_log_unique directiv e.		/// The stream that gets written to for the .secure_log_unique directiv e.
	raw_ostream *SecureLog;		raw_ostream *SecureLog;
	/// Boolean toggled when .secure_log_unique / .secure_log_reset is seen to		/// Boolean toggled when .secure_log_unique / .secure_log_reset is seen to
	/// catch errors if .secure_log_unique appears twice without		/// catch errors if .secure_log_unique appears twice without
	/// .secure_log_reset appearing between them.		/// .secure_log_reset appearing between them.
	bool SecureLogUsed;		bool SecureLogUsed;
	/// The compilation directory to use for DW_AT_comp_dir.		/// The compilation directory to use for DW_AT_comp_dir.
	std::string CompilationDir;		SmallString<128> CompilationDir;
	/// The main file name if passed in explicitly.		/// The main file name if passed in explicitly.
	std::string MainFileName;		std::string MainFileName;
	/// The dwarf file and directory tables from the dwarf .file directive.		/// The dwarf file and directory tables from the dwarf .file directive.
	/// We now emit a line table for each compile unit. To reduce the prolo gue		/// We now emit a line table for each compile unit. To reduce the prolo gue
	/// size of each line table, the files and directories used by each com pile		/// size of each line table, the files and directories used by each com pile
	/// unit are separated.		/// unit are separated.
	typedef std::map<unsigned, SmallVector<MCDwarfFile *, 4> > MCDwarfFiles Map;		typedef std::map<unsigned, SmallVector<MCDwarfFile *, 4> > MCDwarfFiles Map;
	MCDwarfFilesMap MCDwarfFilesCUMap;		MCDwarfFilesMap MCDwarfFilesCUMap;
	skipping to change at line 166		skipping to change at line 168
	DenseMap<unsigned, MCSymbol *> MCLineTableSymbols;		DenseMap<unsigned, MCSymbol *> MCLineTableSymbols;
	void *MachOUniquingMap, *ELFUniquingMap, *COFFUniquingMap;		void *MachOUniquingMap, *ELFUniquingMap, *COFFUniquingMap;
	/// Do automatic reset in destructor		/// Do automatic reset in destructor
	bool AutoReset;		bool AutoReset;
	MCSymbol *CreateSymbol(StringRef Name);		MCSymbol *CreateSymbol(StringRef Name);
	public:		public:
	explicit MCContext(const MCAsmInfo &MAI, const MCRegisterInfo &MRI,		explicit MCContext(const MCAsmInfo *MAI, const MCRegisterInfo *MRI,
	const MCObjectFileInfo *MOFI, const SourceMgr *Mgr = 0,		const MCObjectFileInfo *MOFI, const SourceMgr *Mgr = 0,
	bool DoAutoReset = true);		bool DoAutoReset = true);
	~MCContext();		~MCContext();
	const SourceMgr *getSourceManager() const { return SrcMgr; }		const SourceMgr *getSourceManager() const { return SrcMgr; }
	const MCAsmInfo &getAsmInfo() const { return MAI; }		const MCAsmInfo *getAsmInfo() const { return MAI; }
	const MCRegisterInfo &getRegisterInfo() const { return MRI; }		const MCRegisterInfo *getRegisterInfo() const { return MRI; }
	const MCObjectFileInfo *getObjectFileInfo() const { return MOFI; }		const MCObjectFileInfo *getObjectFileInfo() const { return MOFI; }
	void setAllowTemporaryLabels(bool Value) { AllowTemporaryLabels = Value ; }		void setAllowTemporaryLabels(bool Value) { AllowTemporaryLabels = Value ; }
	/// @name Module Lifetime Management		/// @name Module Lifetime Management
	/// @{		/// @{
	/// reset - return object to right after construction state to prepare		/// reset - return object to right after construction state to prepare
	/// to process a new module		/// to process a new module
	skipping to change at line 257		skipping to change at line 259
	const MCSectionELF *getELFSection(StringRef Section, unsigned Type,		const MCSectionELF *getELFSection(StringRef Section, unsigned Type,
	unsigned Flags, SectionKind Kind);		unsigned Flags, SectionKind Kind);
	const MCSectionELF *getELFSection(StringRef Section, unsigned Type,		const MCSectionELF *getELFSection(StringRef Section, unsigned Type,
	unsigned Flags, SectionKind Kind,		unsigned Flags, SectionKind Kind,
	unsigned EntrySize, StringRef Group);		unsigned EntrySize, StringRef Group);
	const MCSectionELF *CreateELFGroupSection();		const MCSectionELF *CreateELFGroupSection();
	const MCSection *getCOFFSection(StringRef Section, unsigned Characteris		const MCSectionCOFF *getCOFFSection(StringRef Section,
	tics,		unsigned Characteristics,
	int Selection, SectionKind Kind);		SectionKind Kind,
			StringRef COMDATSymName,
			int Selection,
			const MCSectionCOFF *Assoc = 0);
			const MCSectionCOFF *getCOFFSection(StringRef Section,
			unsigned Characteristics,
			SectionKind Kind);
	const MCSection *getCOFFSection(StringRef Section, unsigned Characteris		const MCSectionCOFF *getCOFFSection(StringRef Section);
	tics,
	SectionKind Kind) {
	return getCOFFSection (Section, Characteristics, 0, Kind);
	}
	/// @}		/// @}
	/// @name Dwarf Management		/// @name Dwarf Management
	/// @{		/// @{
	/// \brief Get the compilation directory for DW_AT_comp_dir		/// \brief Get the compilation directory for DW_AT_comp_dir
	/// This can be overridden by clients which want to control the reporte d		/// This can be overridden by clients which want to control the reporte d
	/// compilation directory and have it be something other than the curre nt		/// compilation directory and have it be something other than the curre nt
	/// working directory.		/// working directory.
	const std::string &getCompilationDir() const { return CompilationDir; }		StringRef getCompilationDir() const { return CompilationDir; }
	/// \brief Set the compilation directory for DW_AT_comp_dir		/// \brief Set the compilation directory for DW_AT_comp_dir
	/// Override the default (CWD) compilation directory.		/// Override the default (CWD) compilation directory.
	void setCompilationDir(StringRef S) { CompilationDir = S.str(); }		void setCompilationDir(StringRef S) { CompilationDir = S.str(); }
	/// \brief Get the main file name for use in error messages and debug		/// \brief Get the main file name for use in error messages and debug
	/// info. This can be set to ensure we've got the correct file name		/// info. This can be set to ensure we've got the correct file name
	/// after preprocessing or for -save-temps.		/// after preprocessing or for -save-temps.
	const std::string &getMainFileName() const { return MainFileName; }		const std::string &getMainFileName() const { return MainFileName; }
	skipping to change at line 408		skipping to change at line 415
	void setSecureLogUsed(bool Value) {		void setSecureLogUsed(bool Value) {
	SecureLogUsed = Value;		SecureLogUsed = Value;
	}		}
	void *Allocate(unsigned Size, unsigned Align = 8) {		void *Allocate(unsigned Size, unsigned Align = 8) {
	return Allocator.Allocate(Size, Align);		return Allocator.Allocate(Size, Align);
	}		}
	void Deallocate(void *Ptr) {		void Deallocate(void *Ptr) {
	}		}
	// Unrecoverable error has occured. Display the best diagnostic we can		// Unrecoverable error has occurred. Display the best diagnostic we can
	// and bail via exit(1). For now, most MC backend errors are unrecovera ble.		// and bail via exit(1). For now, most MC backend errors are unrecovera ble.
	// FIXME: We should really do something about that.		// FIXME: We should really do something about that.
	LLVM_ATTRIBUTE_NORETURN void FatalError(SMLoc L, const Twine &Msg);		LLVM_ATTRIBUTE_NORETURN void FatalError(SMLoc L, const Twine &Msg);
	};		};
	} // end namespace llvm		} // end namespace llvm
	// operator new and delete aren't allowed inside namespaces.		// operator new and delete aren't allowed inside namespaces.
	// The throw specifications are mandated by the standard.		// The throw specifications are mandated by the standard.
	/// @brief Placement new for using the MCContext's allocator.		/// @brief Placement new for using the MCContext's allocator.
End of changes. 12 change blocks.
	16 lines changed or deleted		21 lines changed or added

	MCDisassembler.h		MCDisassembler.h
	skipping to change at line 13		skipping to change at line 13
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_MC_MCDISASSEMBLER_H		#ifndef LLVM_MC_MCDISASSEMBLER_H
	#define LLVM_MC_MCDISASSEMBLER_H		#define LLVM_MC_MCDISASSEMBLER_H
	#include "llvm-c/Disassembler.h"		#include "llvm-c/Disassembler.h"
			#include "llvm/ADT/OwningPtr.h"
			#include "llvm/MC/MCSymbolizer.h"
			#include "llvm/MC/MCRelocationInfo.h"
	#include "llvm/Support/DataTypes.h"		#include "llvm/Support/DataTypes.h"
	namespace llvm {		namespace llvm {
	class MCInst;		class MCInst;
	class MCSubtargetInfo;		class MCSubtargetInfo;
	class MemoryObject;		class MemoryObject;
	class raw_ostream;		class raw_ostream;
	class MCContext;		class MCContext;
	skipping to change at line 58		skipping to change at line 61
	/// Success, SoftFail, Fail respectively.		/// Success, SoftFail, Fail respectively.
	enum DecodeStatus {		enum DecodeStatus {
	Fail = 0,		Fail = 0,
	SoftFail = 1,		SoftFail = 1,
	Success = 3		Success = 3
	};		};
	/// Constructor - Performs initial setup for the disassembler.		/// Constructor - Performs initial setup for the disassembler.
	MCDisassembler(const MCSubtargetInfo &STI) : GetOpInfo(0), SymbolLookUp(0 ),		MCDisassembler(const MCSubtargetInfo &STI) : GetOpInfo(0), SymbolLookUp(0 ),
	DisInfo(0), Ctx(0),		DisInfo(0), Ctx(0),
	STI(STI), CommentStream(0) {		STI(STI), Symbolizer(0),
	}		CommentStream(0) {}
	virtual ~MCDisassembler();		virtual ~MCDisassembler();
	/// getInstruction - Returns the disassembly of a single instruction.		/// getInstruction - Returns the disassembly of a single instruction.
	///		///
	/// @param instr - An MCInst to populate with the contents of the		/// @param instr - An MCInst to populate with the contents of the
	/// instruction.		/// instruction.
	/// @param size - A value to populate with the size of the instructio n, or		/// @param size - A value to populate with the size of the instructio n, or
	/// the number of bytes consumed while attempting to de code		/// the number of bytes consumed while attempting to de code
	/// an invalid instruction.		/// an invalid instruction.
	skipping to change at line 84		skipping to change at line 88
	/// @return - MCDisassembler::Success if the instruction is valid ,		/// @return - MCDisassembler::Success if the instruction is valid ,
	/// MCDisassembler::SoftFail if the instruction was		/// MCDisassembler::SoftFail if the instruction was
	/// disassemblable but invalid ,		/// disassemblable but invalid ,
	/// MCDisassembler::Fail if the instruction was invalid .		/// MCDisassembler::Fail if the instruction was invalid .
	virtual DecodeStatus getInstruction(MCInst& instr,		virtual DecodeStatus getInstruction(MCInst& instr,
	uint64_t& size,		uint64_t& size,
	const MemoryObject &region,		const MemoryObject &region,
	uint64_t address,		uint64_t address,
	raw_ostream &vStream,		raw_ostream &vStream,
	raw_ostream &cStream) const = 0;		raw_ostream &cStream) const = 0;
	private:		private:
	//		//
	// Hooks for symbolic disassembly via the public 'C' interface.		// Hooks for symbolic disassembly via the public 'C' interface.
	//		//
	// The function to get the symbolic information for operands.		// The function to get the symbolic information for operands.
	LLVMOpInfoCallback GetOpInfo;		LLVMOpInfoCallback GetOpInfo;
	// The function to lookup a symbol name.		// The function to lookup a symbol name.
	LLVMSymbolLookupCallback SymbolLookUp;		LLVMSymbolLookupCallback SymbolLookUp;
	// The pointer to the block of symbolic information for above call back.		// The pointer to the block of symbolic information for above call back.
	void *DisInfo;		void *DisInfo;
	// The assembly context for creating symbols and MCExprs in place of		// The assembly context for creating symbols and MCExprs in place of
	// immediate operands when there is symbolic information.		// immediate operands when there is symbolic information.
	MCContext *Ctx;		MCContext *Ctx;
	protected:		protected:
	// Subtarget information, for instruction decoding predicates if required .		// Subtarget information, for instruction decoding predicates if required .
	const MCSubtargetInfo &STI;		const MCSubtargetInfo &STI;
			OwningPtr<MCSymbolizer> Symbolizer;
	public:		public:
	void setupForSymbolicDisassembly(LLVMOpInfoCallback getOpInfo,		// Helpers around MCSymbolizer
	LLVMSymbolLookupCallback symbolLookUp,		bool tryAddingSymbolicOperand(MCInst &Inst,
	void *disInfo,		int64_t Value,
	MCContext *ctx) {		uint64_t Address, bool IsBranch,
	GetOpInfo = getOpInfo;		uint64_t Offset, uint64_t InstSize) const;
	SymbolLookUp = symbolLookUp;
	DisInfo = disInfo;		void tryAddingPcLoadReferenceComment(int64_t Value, uint64_t Address) con
	Ctx = ctx;		st;
	}
			/// Set \p Symzer as the current symbolizer.
			/// This takes ownership of \p Symzer, and deletes the previously set one
			.
			void setSymbolizer(OwningPtr<MCSymbolizer> &Symzer);
			/// Sets up an external symbolizer that uses the C API callbacks.
			void setupForSymbolicDisassembly(LLVMOpInfoCallback GetOpInfo,
			LLVMSymbolLookupCallback SymbolLookUp,
			void *DisInfo,
			MCContext *Ctx,
			OwningPtr<MCRelocationInfo> &RelInfo);
	LLVMOpInfoCallback getLLVMOpInfoCallback() const { return GetOpInfo; }		LLVMOpInfoCallback getLLVMOpInfoCallback() const { return GetOpInfo; }
	LLVMSymbolLookupCallback getLLVMSymbolLookupCallback() const {		LLVMSymbolLookupCallback getLLVMSymbolLookupCallback() const {
	return SymbolLookUp;		return SymbolLookUp;
	}		}
	void *getDisInfoBlock() const { return DisInfo; }		void *getDisInfoBlock() const { return DisInfo; }
	MCContext *getMCContext() const { return Ctx; }		MCContext *getMCContext() const { return Ctx; }
			const MCSubtargetInfo& getSubtargetInfo() const { return STI; }
	// Marked mutable because we cache it inside the disassembler, rather tha n		// Marked mutable because we cache it inside the disassembler, rather tha n
	// having to pass it around as an argument through all the autogenerated code.		// having to pass it around as an argument through all the autogenerated code.
	mutable raw_ostream *CommentStream;		mutable raw_ostream *CommentStream;
	};		};
	} // namespace llvm		} // namespace llvm
	#endif		#endif
End of changes. 7 change blocks.
	12 lines changed or deleted		30 lines changed or added

	MCDwarf.h		MCDwarf.h
	skipping to change at line 26		skipping to change at line 26
	#define LLVM_MC_MCDWARF_H		#define LLVM_MC_MCDWARF_H
	#include "llvm/ADT/StringRef.h"		#include "llvm/ADT/StringRef.h"
	#include "llvm/Support/Compiler.h"		#include "llvm/Support/Compiler.h"
	#include "llvm/Support/Dwarf.h"		#include "llvm/Support/Dwarf.h"
	#include "llvm/Support/raw_ostream.h"		#include "llvm/Support/raw_ostream.h"
	#include <map>		#include <map>
	#include <vector>		#include <vector>
	namespace llvm {		namespace llvm {
	class MCContext;		class MCAsmBackend;
	class MCObjectWriter;		class MCContext;
	class MCSection;		class MCSection;
	class MCStreamer;		class MCStreamer;
	class MCSymbol;		class MCSymbol;
	class SourceMgr;		class SourceMgr;
	class SMLoc;		class SMLoc;
	/// MCDwarfFile - Instances of this class represent the name of the dwarf		/// MCDwarfFile - Instances of this class represent the name of the dwarf
	/// .file directive and its associated dwarf file number in the MC file,		/// .file directive and its associated dwarf file number in the MC file,
	/// and MCDwarfFile's are created and unique'd by the MCContext class whe		/// and MCDwarfFile's are created and unique'd by the MCContext class where
	re		/// the file number for each is its index into the vector of DwarfFiles (no
	/// the file number for each is its index into the vector of DwarfFiles (		te
	note		/// index 0 is not used and not a valid dwarf file number).
	/// index 0 is not used and not a valid dwarf file number).		class MCDwarfFile {
	class MCDwarfFile {		// Name - the base name of the file without its directory path.
	// Name - the base name of the file without its directory path.		// The StringRef references memory allocated in the MCContext.
	// The StringRef references memory allocated in the MCContext.		StringRef Name;
	StringRef Name;
			// DirIndex - the index into the list of directory names for this file na
	// DirIndex - the index into the list of directory names for this file		me.
	name.		unsigned DirIndex;
	unsigned DirIndex;
			private: // MCContext creates and uniques these.
	private: // MCContext creates and uniques these.		friend class MCContext;
	friend class MCContext;		MCDwarfFile(StringRef name, unsigned dirIndex)
	MCDwarfFile(StringRef name, unsigned dirIndex)
	: Name(name), DirIndex(dirIndex) {}		: Name(name), DirIndex(dirIndex) {}
	MCDwarfFile(const MCDwarfFile&) LLVM_DELETED_FUNCTION;		MCDwarfFile(const MCDwarfFile &) LLVM_DELETED_FUNCTION;
	void operator=(const MCDwarfFile&) LLVM_DELETED_FUNCTION;		void operator=(const MCDwarfFile &) LLVM_DELETED_FUNCTION;
	public:
	/// getName - Get the base name of this MCDwarfFile.
	StringRef getName() const { return Name; }
	/// getDirIndex - Get the dirIndex of this MCDwarfFile.		public:
	unsigned getDirIndex() const { return DirIndex; }		/// getName - Get the base name of this MCDwarfFile.
			StringRef getName() const { return Name; }
	/// print - Print the value to the stream \p OS.
	void print(raw_ostream &OS) const;		/// getDirIndex - Get the dirIndex of this MCDwarfFile.
			unsigned getDirIndex() const { return DirIndex; }
	/// dump - Print the value to stderr.
	void dump() const;		/// print - Print the value to the stream \p OS.
	};		void print(raw_ostream &OS) const;
	inline raw_ostream &operator<<(raw_ostream &OS, const MCDwarfFile &DwarfF		/// dump - Print the value to stderr.
	ile){		void dump() const;
	DwarfFile.print(OS);		};
	return OS;
	}		inline raw_ostream &operator<<(raw_ostream &OS, const MCDwarfFile &DwarfFil
			e) {
	/// MCDwarfLoc - Instances of this class represent the information from a		DwarfFile.print(OS);
	/// dwarf .loc directive.		return OS;
	class MCDwarfLoc {		}
	// FileNum - the file number.
	unsigned FileNum;		/// MCDwarfLoc - Instances of this class represent the information from a
	// Line - the line number.		/// dwarf .loc directive.
	unsigned Line;		class MCDwarfLoc {
	// Column - the column position.		// FileNum - the file number.
	unsigned Column;		unsigned FileNum;
	// Flags (see #define's below)		// Line - the line number.
	unsigned Flags;		unsigned Line;
	// Isa		// Column - the column position.
	unsigned Isa;		unsigned Column;
	// Discriminator		// Flags (see #define's below)
	unsigned Discriminator;		unsigned Flags;
			// Isa
			unsigned Isa;
			// Discriminator
			unsigned Discriminator;
	// Flag that indicates the initial value of the is_stmt_start flag.		// Flag that indicates the initial value of the is_stmt_start flag.
	#define DWARF2_LINE_DEFAULT_IS_STMT 1		#define DWARF2_LINE_DEFAULT_IS_STMT 1
	#define DWARF2_FLAG_IS_STMT (1 << 0)		#define DWARF2_FLAG_IS_STMT (1 << 0)
	#define DWARF2_FLAG_BASIC_BLOCK (1 << 1)		#define DWARF2_FLAG_BASIC_BLOCK (1 << 1)
	#define DWARF2_FLAG_PROLOGUE_END (1 << 2)		#define DWARF2_FLAG_PROLOGUE_END (1 << 2)
	#define DWARF2_FLAG_EPILOGUE_BEGIN (1 << 3)		#define DWARF2_FLAG_EPILOGUE_BEGIN (1 << 3)
	private: // MCContext manages these		private: // MCContext manages these
	friend class MCContext;		friend class MCContext;
	friend class MCLineEntry;		friend class MCLineEntry;
	MCDwarfLoc(unsigned fileNum, unsigned line, unsigned column, unsigned f		MCDwarfLoc(unsigned fileNum, unsigned line, unsigned column, unsigned fla
	lags,		gs,
	unsigned isa, unsigned discriminator)		unsigned isa, unsigned discriminator)
	: FileNum(fileNum), Line(line), Column(column), Flags(flags), Isa(isa ),		: FileNum(fileNum), Line(line), Column(column), Flags(flags), Isa(isa ),
	Discriminator(discriminator) {}		Discriminator(discriminator) {}
	// Allow the default copy constructor and assignment operator to be use		// Allow the default copy constructor and assignment operator to be used
	d		// for an MCDwarfLoc object.
	// for an MCDwarfLoc object.
	public:		public:
	/// getFileNum - Get the FileNum of this MCDwarfLoc.		/// getFileNum - Get the FileNum of this MCDwarfLoc.
	unsigned getFileNum() const { return FileNum; }		unsigned getFileNum() const { return FileNum; }
	/// getLine - Get the Line of this MCDwarfLoc.		/// getLine - Get the Line of this MCDwarfLoc.
	unsigned getLine() const { return Line; }		unsigned getLine() const { return Line; }
	/// getColumn - Get the Column of this MCDwarfLoc.		/// getColumn - Get the Column of this MCDwarfLoc.
	unsigned getColumn() const { return Column; }		unsigned getColumn() const { return Column; }
	/// getFlags - Get the Flags of this MCDwarfLoc.		/// getFlags - Get the Flags of this MCDwarfLoc.
	unsigned getFlags() const { return Flags; }		unsigned getFlags() const { return Flags; }
	/// getIsa - Get the Isa of this MCDwarfLoc.		/// getIsa - Get the Isa of this MCDwarfLoc.
	unsigned getIsa() const { return Isa; }		unsigned getIsa() const { return Isa; }
	/// getDiscriminator - Get the Discriminator of this MCDwarfLoc.		/// getDiscriminator - Get the Discriminator of this MCDwarfLoc.
	unsigned getDiscriminator() const { return Discriminator; }		unsigned getDiscriminator() const { return Discriminator; }
	/// setFileNum - Set the FileNum of this MCDwarfLoc.		/// setFileNum - Set the FileNum of this MCDwarfLoc.
	void setFileNum(unsigned fileNum) { FileNum = fileNum; }		void setFileNum(unsigned fileNum) { FileNum = fileNum; }
	/// setLine - Set the Line of this MCDwarfLoc.		/// setLine - Set the Line of this MCDwarfLoc.
	void setLine(unsigned line) { Line = line; }		void setLine(unsigned line) { Line = line; }
	/// setColumn - Set the Column of this MCDwarfLoc.		/// setColumn - Set the Column of this MCDwarfLoc.
	void setColumn(unsigned column) { Column = column; }		void setColumn(unsigned column) { Column = column; }
	/// setFlags - Set the Flags of this MCDwarfLoc.		/// setFlags - Set the Flags of this MCDwarfLoc.
	void setFlags(unsigned flags) { Flags = flags; }		void setFlags(unsigned flags) { Flags = flags; }
	/// setIsa - Set the Isa of this MCDwarfLoc.		/// setIsa - Set the Isa of this MCDwarfLoc.
	void setIsa(unsigned isa) { Isa = isa; }		void setIsa(unsigned isa) { Isa = isa; }
	/// setDiscriminator - Set the Discriminator of this MCDwarfLoc.		/// setDiscriminator - Set the Discriminator of this MCDwarfLoc.
	void setDiscriminator(unsigned discriminator) {		void setDiscriminator(unsigned discriminator) {
	Discriminator = discriminator;		Discriminator = discriminator;
	}		}
	};		};
	/// MCLineEntry - Instances of this class represent the line information		/// MCLineEntry - Instances of this class represent the line information fo
	for		r
	/// the dwarf line table entries. Which is created after a machine		/// the dwarf line table entries. Which is created after a machine
	/// instruction is assembled and uses an address from a temporary label		/// instruction is assembled and uses an address from a temporary label
	/// created at the current address in the current section and the info fr		/// created at the current address in the current section and the info from
	om		/// the last .loc directive seen as stored in the context.
	/// the last .loc directive seen as stored in the context.		class MCLineEntry : public MCDwarfLoc {
	class MCLineEntry : public MCDwarfLoc {		MCSymbol *Label;
	MCSymbol *Label;
			private:
	private:		// Allow the default copy constructor and assignment operator to be used
	// Allow the default copy constructor and assignment operator to be use		// for an MCLineEntry object.
	d
	// for an MCLineEntry object.		public:
			// Constructor to create an MCLineEntry given a symbol and the dwarf loc.
	public:		MCLineEntry(MCSymbol *label, const MCDwarfLoc loc)
	// Constructor to create an MCLineEntry given a symbol and the dwarf lo		: MCDwarfLoc(loc), Label(label) {}
	c.
	MCLineEntry(MCSymbol *label, const MCDwarfLoc loc) : MCDwarfLoc(loc),		MCSymbol *getLabel() const { return Label; }
	Label(label) {}
			// This is called when an instruction is assembled into the specified
	MCSymbol *getLabel() const { return Label; }		// section and if there is information from the last .loc directive that
			// has yet to have a line entry made for it is made.
	// This is called when an instruction is assembled into the specified		static void Make(MCStreamer *MCOS, const MCSection *Section);
	// section and if there is information from the last .loc directive tha		};
	t
	// has yet to have a line entry made for it is made.		/// MCLineSection - Instances of this class represent the line information
	static void Make(MCStreamer *MCOS, const MCSection *Section);		/// for a section where machine instructions have been assembled after seei
	};		ng
			/// .loc directives. This is the information used to build the dwarf line
			/// table for a section.
			class MCLineSection {
			private:
			MCLineSection(const MCLineSection &) LLVM_DELETED_FUNCTION;
			void operator=(const MCLineSection &) LLVM_DELETED_FUNCTION;
			public:
			// Constructor to create an MCLineSection with an empty MCLineEntries
			// vector.
			MCLineSection() {}
			// addLineEntry - adds an entry to this MCLineSection's line entries
			void addLineEntry(const MCLineEntry &LineEntry, unsigned CUID) {
			MCLineDivisions[CUID].push_back(LineEntry);
			}
	/// MCLineSection - Instances of this class represent the line informatio		typedef std::vector<MCLineEntry> MCLineEntryCollection;
	n		typedef MCLineEntryCollection::iterator iterator;
	/// for a section where machine instructions have been assembled after se		typedef MCLineEntryCollection::const_iterator const_iterator;
	eing		typedef std::map<unsigned, MCLineEntryCollection> MCLineDivisionMap;
	/// .loc directives. This is the information used to build the dwarf lin
	e		private:
	/// table for a section.		// A collection of MCLineEntry for each Compile Unit ID.
	class MCLineSection {		MCLineDivisionMap MCLineDivisions;
	private:		public:
	MCLineSection(const MCLineSection&) LLVM_DELETED_FUNCTION;		// Returns whether MCLineSection contains entries for a given Compile
	void operator=(const MCLineSection&) LLVM_DELETED_FUNCTION;		// Unit ID.
			bool containEntriesForID(unsigned CUID) const {
	public:		return MCLineDivisions.count(CUID);
	// Constructor to create an MCLineSection with an empty MCLineEntries		}
	// vector.		// Returns the collection of MCLineEntry for a given Compile Unit ID.
	MCLineSection() {}		const MCLineEntryCollection &getMCLineEntries(unsigned CUID) const {
			MCLineDivisionMap::const_iterator CIter = MCLineDivisions.find(CUID);
	// addLineEntry - adds an entry to this MCLineSection's line entries		assert(CIter != MCLineDivisions.end());
	void addLineEntry(const MCLineEntry &LineEntry, unsigned CUID) {		return CIter->second;
	MCLineDivisions[CUID].push_back(LineEntry);		}
	}		};
	typedef std::vector<MCLineEntry> MCLineEntryCollection;
	typedef MCLineEntryCollection::iterator iterator;
	typedef MCLineEntryCollection::const_iterator const_iterator;
	typedef std::map<unsigned, MCLineEntryCollection> MCLineDivisionMap;
	private:
	// A collection of MCLineEntry for each Compile Unit ID.
	MCLineDivisionMap MCLineDivisions;
	public:
	// Returns whether MCLineSection contains entries for a given Compile
	// Unit ID.
	bool containEntriesForID(unsigned CUID) const {
	return MCLineDivisions.count(CUID);
	}
	// Returns the collection of MCLineEntry for a given Compile Unit ID.
	const MCLineEntryCollection &getMCLineEntries(unsigned CUID) const {
	MCLineDivisionMap::const_iterator CIter = MCLineDivisions.find(CUID);
	assert(CIter != MCLineDivisions.end());
	return CIter->second;
	}
	};
	class MCDwarfFileTable {		class MCDwarfFileTable {
	public:		public:
	//		//
	// This emits the Dwarf file and the line tables for all Compile Units.		// This emits the Dwarf file and the line tables for all Compile Units.
	//		//
	static const MCSymbol *Emit(MCStreamer *MCOS);		static const MCSymbol *Emit(MCStreamer *MCOS);
	//		//
	// This emits the Dwarf file and the line tables for a given Compile Un		// This emits the Dwarf file and the line tables for a given Compile Unit
	it.		.
	//		//
	static const MCSymbol *EmitCU(MCStreamer *MCOS, unsigned ID);		static const MCSymbol *EmitCU(MCStreamer *MCOS, unsigned ID);
	};		};
			class MCDwarfLineAddr {
			public:
			/// Utility function to encode a Dwarf pair of LineDelta and AddrDeltas.
			static void Encode(MCContext &Context, int64_t LineDelta, uint64_t AddrDe
			lta,
			raw_ostream &OS);
			/// Utility function to emit the encoding to a streamer.
			static void Emit(MCStreamer *MCOS, int64_t LineDelta, uint64_t AddrDelta)
			;
			};
			class MCGenDwarfInfo {
			public:
			//
			// When generating dwarf for assembly source files this emits the Dwarf
			// sections.
			//
			static void Emit(MCStreamer *MCOS, const MCSymbol *LineSectionSymbol);
			};
			// When generating dwarf for assembly source files this is the info that is
			// needed to be gathered for each symbol that will have a dwarf label.
			class MCGenDwarfLabelEntry {
			private:
			// Name of the symbol without a leading underbar, if any.
			StringRef Name;
			// The dwarf file number this symbol is in.
			unsigned FileNumber;
			// The line number this symbol is at.
			unsigned LineNumber;
			// The low_pc for the dwarf label is taken from this symbol.
			MCSymbol *Label;
			public:
			MCGenDwarfLabelEntry(StringRef name, unsigned fileNumber, unsigned lineNu
			mber,
			MCSymbol *label)
			: Name(name), FileNumber(fileNumber), LineNumber(lineNumber),
			Label(label) {}
			StringRef getName() const { return Name; }
			unsigned getFileNumber() const { return FileNumber; }
			unsigned getLineNumber() const { return LineNumber; }
			MCSymbol *getLabel() const { return Label; }
			// This is called when label is created when we are generating dwarf for
			// assembly source files.
			static void Make(MCSymbol *Symbol, MCStreamer *MCOS, SourceMgr &SrcMgr,
			SMLoc &Loc);
			};
			class MCCFIInstruction {
			public:
			enum OpType {
			OpSameValue,
			OpRememberState,
			OpRestoreState,
			OpOffset,
			OpDefCfaRegister,
			OpDefCfaOffset,
			OpDefCfa,
			OpRelOffset,
			OpAdjustCfaOffset,
			OpEscape,
			OpRestore,
			OpUndefined,
			OpRegister,
			OpWindowSave
			};
			private:
			OpType Operation;
			MCSymbol *Label;
			unsigned Register;
			union {
			int Offset;
			unsigned Register2;
			};
			std::vector<char> Values;
			MCCFIInstruction(OpType Op, MCSymbol *L, unsigned R, int O, StringRef V)
			: Operation(Op), Label(L), Register(R), Offset(O),
			Values(V.begin(), V.end()) {
			assert(Op != OpRegister);
			}
	class MCDwarfLineAddr {		MCCFIInstruction(OpType Op, MCSymbol *L, unsigned R1, unsigned R2)
	public:		: Operation(Op), Label(L), Register(R1), Register2(R2) {
	/// Utility function to encode a Dwarf pair of LineDelta and AddrDeltas		assert(Op == OpRegister);
	.		}
	static void Encode(int64_t LineDelta, uint64_t AddrDelta, raw_ostream &
	OS);
	/// Utility function to emit the encoding to a streamer.
	static void Emit(MCStreamer *MCOS,
	int64_t LineDelta,uint64_t AddrDelta);
	/// Utility function to write the encoding to an object writer.
	static void Write(MCObjectWriter *OW,
	int64_t LineDelta, uint64_t AddrDelta);
	};
	class MCGenDwarfInfo {		public:
	public:		/// \brief .cfi_def_cfa defines a rule for computing CFA as: take address
	//		from
	// When generating dwarf for assembly source files this emits the Dwarf		/// Register and add Offset to it.
	// sections.		static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register,
	//		int Offset) {
	static void Emit(MCStreamer *MCOS, const MCSymbol *LineSectionSymbol);		return MCCFIInstruction(OpDefCfa, L, Register, -Offset, "");
	};		}
	// When generating dwarf for assembly source files this is the info that		/// \brief .cfi_def_cfa_register modifies a rule for computing CFA. From
	is		now
	// needed to be gathered for each symbol that will have a dwarf label.		/// on Register will be used instead of the old one. Offset remains the s
	class MCGenDwarfLabelEntry {		ame.
	private:		static MCCFIInstruction createDefCfaRegister(MCSymbol *L, unsigned Regist
	// Name of the symbol without a leading underbar, if any.		er) {
	StringRef Name;		return MCCFIInstruction(OpDefCfaRegister, L, Register, 0, "");
	// The dwarf file number this symbol is in.		}
	unsigned FileNumber;
	// The line number this symbol is at.
	unsigned LineNumber;
	// The low_pc for the dwarf label is taken from this symbol.
	MCSymbol *Label;
	public:
	MCGenDwarfLabelEntry(StringRef name, unsigned fileNumber,
	unsigned lineNumber, MCSymbol *label) :
	Name(name), FileNumber(fileNumber), LineNumber(lineNumber), Label(lab
	el){}
	StringRef getName() const { return Name; }
	unsigned getFileNumber() const { return FileNumber; }
	unsigned getLineNumber() const { return LineNumber; }
	MCSymbol *getLabel() const { return Label; }
	// This is called when label is created when we are generating dwarf fo
	r
	// assembly source files.
	static void Make(MCSymbol *Symbol, MCStreamer *MCOS, SourceMgr &SrcMgr,
	SMLoc &Loc);
	};
	class MCCFIInstruction {		/// \brief .cfi_def_cfa_offset modifies a rule for computing CFA. Registe
	public:		r
	enum OpType { OpSameValue, OpRememberState, OpRestoreState, OpOffset,		/// remains the same, but offset is new. Note that it is the absolute off
	OpDefCfaRegister, OpDefCfaOffset, OpDefCfa, OpRelOffset,		set
	OpAdjustCfaOffset, OpEscape, OpRestore, OpUndefined,		/// that will be added to a defined register to the compute CFA address.
	OpRegister };		static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset) {
	private:		return MCCFIInstruction(OpDefCfaOffset, L, 0, -Offset, "");
	OpType Operation;		}
	MCSymbol *Label;
	unsigned Register;
	union {
	int Offset;
	unsigned Register2;
	};
	std::vector<char> Values;
	MCCFIInstruction(OpType Op, MCSymbol *L, unsigned R, int O, StringRef V
	) :
	Operation(Op), Label(L), Register(R), Offset(O),
	Values(V.begin(), V.end()) {
	assert(Op != OpRegister);
	}
	MCCFIInstruction(OpType Op, MCSymbol *L, unsigned R1, unsigned R2) :
	Operation(Op), Label(L), Register(R1), Register2(R2) {
	assert(Op == OpRegister);
	}
	public:
	static MCCFIInstruction
	createOffset(MCSymbol *L, unsigned Register, int Offset) {
	return MCCFIInstruction(OpOffset, L, Register, Offset, "");
	}
	static MCCFIInstruction
	createDefCfaRegister(MCSymbol *L, unsigned Register) {
	return MCCFIInstruction(OpDefCfaRegister, L, Register, 0, "");
	}
	static MCCFIInstruction createDefCfaOffset(MCSymbol *L, int Offset) {
	return MCCFIInstruction(OpDefCfaOffset, L, 0, -Offset, "");
	}
	static MCCFIInstruction
	createDefCfa(MCSymbol *L, unsigned Register, int Offset) {
	return MCCFIInstruction(OpDefCfa, L, Register, -Offset, "");
	}
	static MCCFIInstruction createUndefined(MCSymbol *L, unsigned Register)
	{
	return MCCFIInstruction(OpUndefined, L, Register, 0, "");
	}
	static MCCFIInstruction createRestore(MCSymbol *L, unsigned Register) {
	return MCCFIInstruction(OpRestore, L, Register, 0, "");
	}
	static MCCFIInstruction createSameValue(MCSymbol *L, unsigned Register)
	{
	return MCCFIInstruction(OpSameValue, L, Register, 0, "");
	}
	static MCCFIInstruction createRestoreState(MCSymbol *L) {
	return MCCFIInstruction(OpRestoreState, L, 0, 0, "");
	}
	static MCCFIInstruction createRememberState(MCSymbol *L) {
	return MCCFIInstruction(OpRememberState, L, 0, 0, "");
	}
	static MCCFIInstruction
	createRelOffset(MCSymbol *L, unsigned Register, int Offset) {
	return MCCFIInstruction(OpRelOffset, L, Register, Offset, "");
	}
	static MCCFIInstruction
	createAdjustCfaOffset(MCSymbol *L, int Adjustment) {
	return MCCFIInstruction(OpAdjustCfaOffset, L, 0, Adjustment, "");
	}
	static MCCFIInstruction createEscape(MCSymbol *L, StringRef Vals) {
	return MCCFIInstruction(OpEscape, L, 0, 0, Vals);
	}
	static MCCFIInstruction
	createRegister(MCSymbol *L, unsigned Register1, unsigned Register2) {
	return MCCFIInstruction(OpRegister, L, Register1, Register2);
	}
	OpType getOperation() const { return Operation; }
	MCSymbol *getLabel() const { return Label; }
	unsigned getRegister() const {
	assert(Operation == OpDefCfa || Operation == OpOffset ||
	Operation == OpRestore || Operation == OpUndefined ||
	Operation == OpSameValue || Operation == OpDefCfaRegister ||
	Operation == OpRelOffset || Operation == OpRegister);
	return Register;
	}
	unsigned getRegister2() const {
	assert(Operation == OpRegister);
	return Register2;
	}
	int getOffset() const {
	assert(Operation == OpDefCfa || Operation == OpOffset ||
	Operation == OpRelOffset || Operation == OpDefCfaOffset ||
	Operation == OpAdjustCfaOffset);
	return Offset;
	}
	const StringRef getValues() const {
	assert(Operation == OpEscape);
	return StringRef(&Values[0], Values.size());
	}
	};
	struct MCDwarfFrameInfo {		/// \brief .cfi_adjust_cfa_offset Same as .cfi_def_cfa_offset, but
	MCDwarfFrameInfo() : Begin(0), End(0), Personality(0), Lsda(0),		/// Offset is a relative value that is added/subtracted from the previous
	Function(0), Instructions(), PersonalityEncoding()		/// offset.
	,		static MCCFIInstruction createAdjustCfaOffset(MCSymbol *L, int Adjustment
	LsdaEncoding(0), CompactUnwindEncoding(0),		) {
	IsSignalFrame(false) {}		return MCCFIInstruction(OpAdjustCfaOffset, L, 0, Adjustment, "");
	MCSymbol *Begin;		}
	MCSymbol *End;
	const MCSymbol *Personality;
	const MCSymbol *Lsda;
	const MCSymbol *Function;
	std::vector<MCCFIInstruction> Instructions;
	unsigned PersonalityEncoding;
	unsigned LsdaEncoding;
	uint32_t CompactUnwindEncoding;
	bool IsSignalFrame;
	};
	class MCDwarfFrameEmitter {		/// \brief .cfi_offset Previous value of Register is saved at offset Offs
	public:		et
	//		/// from CFA.
	// This emits the frame info section.		static MCCFIInstruction createOffset(MCSymbol *L, unsigned Register,
	//		int Offset) {
	static void Emit(MCStreamer &streamer, bool usingCFI,		return MCCFIInstruction(OpOffset, L, Register, Offset, "");
	bool isEH);		}
	static void EmitAdvanceLoc(MCStreamer &Streamer, uint64_t AddrDelta);
	static void EncodeAdvanceLoc(uint64_t AddrDelta, raw_ostream &OS);		/// \brief .cfi_rel_offset Previous value of Register is saved at offset
	};		/// Offset from the current CFA register. This is transformed to .cfi_off
			set
			/// using the known displacement of the CFA register from the CFA.
			static MCCFIInstruction createRelOffset(MCSymbol *L, unsigned Register,
			int Offset) {
			return MCCFIInstruction(OpRelOffset, L, Register, Offset, "");
			}
			/// \brief .cfi_register Previous value of Register1 is saved in
			/// register Register2.
			static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1,
			unsigned Register2) {
			return MCCFIInstruction(OpRegister, L, Register1, Register2);
			}
			/// \brief .cfi_window_save SPARC register window is saved.
			static MCCFIInstruction createWindowSave(MCSymbol *L) {
			return MCCFIInstruction(OpWindowSave, L, 0, 0, "");
			}
			/// \brief .cfi_restore says that the rule for Register is now the same a
			s it
			/// was at the beginning of the function, after all initial instructions
			added
			/// by .cfi_startproc were executed.
			static MCCFIInstruction createRestore(MCSymbol *L, unsigned Register) {
			return MCCFIInstruction(OpRestore, L, Register, 0, "");
			}
			/// \brief .cfi_undefined From now on the previous value of Register can'
			t be
			/// restored anymore.
			static MCCFIInstruction createUndefined(MCSymbol *L, unsigned Register) {
			return MCCFIInstruction(OpUndefined, L, Register, 0, "");
			}
			/// \brief .cfi_same_value Current value of Register is the same as in th
			e
			/// previous frame. I.e., no restoration is needed.
			static MCCFIInstruction createSameValue(MCSymbol *L, unsigned Register) {
			return MCCFIInstruction(OpSameValue, L, Register, 0, "");
			}
			/// \brief .cfi_remember_state Save all current rules for all registers.
			static MCCFIInstruction createRememberState(MCSymbol *L) {
			return MCCFIInstruction(OpRememberState, L, 0, 0, "");
			}
			/// \brief .cfi_restore_state Restore the previously saved state.
			static MCCFIInstruction createRestoreState(MCSymbol *L) {
			return MCCFIInstruction(OpRestoreState, L, 0, 0, "");
			}
			/// \brief .cfi_escape Allows the user to add arbitrary bytes to the unwi
			nd
			/// info.
			static MCCFIInstruction createEscape(MCSymbol *L, StringRef Vals) {
			return MCCFIInstruction(OpEscape, L, 0, 0, Vals);
			}
			OpType getOperation() const { return Operation; }
			MCSymbol *getLabel() const { return Label; }
			unsigned getRegister() const {
			assert(Operation == OpDefCfa || Operation == OpOffset ||
			Operation == OpRestore || Operation == OpUndefined ||
			Operation == OpSameValue || Operation == OpDefCfaRegister ||
			Operation == OpRelOffset || Operation == OpRegister);
			return Register;
			}
			unsigned getRegister2() const {
			assert(Operation == OpRegister);
			return Register2;
			}
			int getOffset() const {
			assert(Operation == OpDefCfa || Operation == OpOffset ||
			Operation == OpRelOffset || Operation == OpDefCfaOffset ||
			Operation == OpAdjustCfaOffset);
			return Offset;
			}
			const StringRef getValues() const {
			assert(Operation == OpEscape);
			return StringRef(&Values[0], Values.size());
			}
			};
			struct MCDwarfFrameInfo {
			MCDwarfFrameInfo()
			: Begin(0), End(0), Personality(0), Lsda(0), Function(0), Instruction
			s(),
			PersonalityEncoding(), LsdaEncoding(0), CompactUnwindEncoding(0),
			IsSignalFrame(false) {}
			MCSymbol *Begin;
			MCSymbol *End;
			const MCSymbol *Personality;
			const MCSymbol *Lsda;
			const MCSymbol *Function;
			std::vector<MCCFIInstruction> Instructions;
			unsigned PersonalityEncoding;
			unsigned LsdaEncoding;
			uint32_t CompactUnwindEncoding;
			bool IsSignalFrame;
			};
			class MCDwarfFrameEmitter {
			public:
			//
			// This emits the frame info section.
			//
			static void Emit(MCStreamer &streamer, MCAsmBackend *MAB,
			bool usingCFI, bool isEH);
			static void EmitAdvanceLoc(MCStreamer &Streamer, uint64_t AddrDelta);
			static void EncodeAdvanceLoc(MCContext &Context, uint64_t AddrDelta,
			raw_ostream &OS);
			};
	} // end namespace llvm		} // end namespace llvm
	#endif		#endif
End of changes. 28 change blocks.
	388 lines changed or deleted		432 lines changed or added

	MCELFObjectWriter.h		MCELFObjectWriter.h
	skipping to change at line 45		skipping to change at line 45
	uint64_t r_addend;		uint64_t r_addend;
	const MCFixup *Fixup;		const MCFixup *Fixup;
	ELFRelocationEntry()		ELFRelocationEntry()
	: r_offset(0), Index(0), Type(0), Symbol(0), r_addend(0), Fixup(0) {}		: r_offset(0), Index(0), Type(0), Symbol(0), r_addend(0), Fixup(0) {}
	ELFRelocationEntry(uint64_t RelocOffset, int Idx, unsigned RelType,		ELFRelocationEntry(uint64_t RelocOffset, int Idx, unsigned RelType,
	const MCSymbol *Sym, uint64_t Addend, const MCFixup &F ixup)		const MCSymbol *Sym, uint64_t Addend, const MCFixup &F ixup)
	: r_offset(RelocOffset), Index(Idx), Type(RelType), Symbol(Sym),		: r_offset(RelocOffset), Index(Idx), Type(RelType), Symbol(Sym),
	r_addend(Addend), Fixup(&Fixup) {}		r_addend(Addend), Fixup(&Fixup) {}
	// Support lexicographic sorting.
	bool operator<(const ELFRelocationEntry &RE) const {
	if (RE.r_offset != r_offset)
	return RE.r_offset < r_offset;
	if (Type != RE.Type)
	return Type < RE.Type;
	if (Index != RE.Index)
	return Index < RE.Index;
	llvm_unreachable("ELFRelocs might be unstable!");
	return 0;
	}
	};		};
	class MCELFObjectTargetWriter {		class MCELFObjectTargetWriter {
	const uint8_t OSABI;		const uint8_t OSABI;
	const uint16_t EMachine;		const uint16_t EMachine;
	const unsigned HasRelocationAddend : 1;		const unsigned HasRelocationAddend : 1;
	const unsigned Is64Bit : 1;		const unsigned Is64Bit : 1;
	const unsigned IsN64 : 1;		const unsigned IsN64 : 1;
	protected:		protected:
	skipping to change at line 97		skipping to change at line 85
	bool IsPCRel, bool IsRelocWithSymbol,		bool IsPCRel, bool IsRelocWithSymbol,
	int64_t Addend) const = 0;		int64_t Addend) const = 0;
	virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm,		virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm,
	const MCValue &Target,		const MCValue &Target,
	const MCFragment &F,		const MCFragment &F,
	const MCFixup &Fixup,		const MCFixup &Fixup,
	bool IsPCRel) const;		bool IsPCRel) const;
	virtual const MCSymbol *undefinedExplicitRelSym(const MCValue &Target,		virtual const MCSymbol *undefinedExplicitRelSym(const MCValue &Target,
	const MCFixup &Fixup,		const MCFixup &Fixup,
	bool IsPCRel) const;		bool IsPCRel) const;
	virtual void adjustFixupOffset(const MCFixup &Fixup,
	uint64_t &RelocOffset);
	virtual void sortRelocs(const MCAssembler &Asm,		virtual void sortRelocs(const MCAssembler &Asm,
	std::vector<ELFRelocationEntry> &Relocs);		std::vector<ELFRelocationEntry> &Relocs);
	/// @name Accessors		/// @name Accessors
	/// @{		/// @{
	uint8_t getOSABI() const { return OSABI; }		uint8_t getOSABI() const { return OSABI; }
	uint16_t getEMachine() const { return EMachine; }		uint16_t getEMachine() const { return EMachine; }
	bool hasRelocationAddend() const { return HasRelocationAddend; }		bool hasRelocationAddend() const { return HasRelocationAddend; }
	bool is64Bit() const { return Is64Bit; }		bool is64Bit() const { return Is64Bit; }
End of changes. 2 change blocks.
	14 lines changed or deleted		0 lines changed or added

	MCELFStreamer.h		MCELFStreamer.h
	skipping to change at line 31		skipping to change at line 31
	class MCAsmBackend;		class MCAsmBackend;
	class MCAssembler;		class MCAssembler;
	class MCCodeEmitter;		class MCCodeEmitter;
	class MCExpr;		class MCExpr;
	class MCInst;		class MCInst;
	class MCSymbol;		class MCSymbol;
	class MCSymbolData;		class MCSymbolData;
	class raw_ostream;		class raw_ostream;
	class MCELFStreamer : public MCObjectStreamer {		class MCELFStreamer : public MCObjectStreamer {
	protected:
	MCELFStreamer(StreamerKind Kind, MCContext &Context, MCAsmBackend &TAB,
	raw_ostream &OS, MCCodeEmitter *Emitter)
	: MCObjectStreamer(Kind, Context, TAB, OS, Emitter) {}
	public:		public:
	MCELFStreamer(MCContext &Context, MCAsmBackend &TAB, raw_ostream &OS,		MCELFStreamer(MCContext &Context, MCTargetStreamer *TargetStreamer,
	MCCodeEmitter *Emitter)		MCAsmBackend &TAB, raw_ostream &OS, MCCodeEmitter *Emitter)
	: MCObjectStreamer(SK_ELFStreamer, Context, TAB, OS, Emitter) {}		: MCObjectStreamer(Context, TargetStreamer, TAB, OS, Emitter),
			SeenIdent(false) {}
	MCELFStreamer(MCContext &Context, MCAsmBackend &TAB, raw_ostream &OS,
	MCCodeEmitter *Emitter, MCAssembler *Assembler)		MCELFStreamer(MCContext &Context, MCTargetStreamer *TargetStreamer,
	: MCObjectStreamer(SK_ELFStreamer, Context, TAB, OS, Emitter,		MCAsmBackend &TAB, raw_ostream &OS, MCCodeEmitter *Emitter,
	Assembler) {}		MCAssembler *Assembler)
			: MCObjectStreamer(Context, TargetStreamer, TAB, OS, Emitter, Assembl
			er),
			SeenIdent(false) {}
	virtual ~MCELFStreamer();		virtual ~MCELFStreamer();
	/// @name MCStreamer Interface		/// @name MCStreamer Interface
	/// @{		/// @{
	virtual void InitSections();		virtual void InitSections();
	virtual void InitToTextSection();		virtual void InitToTextSection();
	virtual void ChangeSection(const MCSection *Section,		virtual void ChangeSection(const MCSection *Section,
	const MCExpr *Subsection);		const MCExpr *Subsection);
	virtual void EmitLabel(MCSymbol *Symbol);		virtual void EmitLabel(MCSymbol *Symbol);
	virtual void EmitDebugLabel(MCSymbol *Symbol);		virtual void EmitDebugLabel(MCSymbol *Symbol);
	virtual void EmitAssemblerFlag(MCAssemblerFlag Flag);		virtual void EmitAssemblerFlag(MCAssemblerFlag Flag);
	virtual void EmitThumbFunc(MCSymbol *Func);		virtual void EmitThumbFunc(MCSymbol *Func);
	virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol);		virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol);
	virtual void EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute );		virtual bool EmitSymbolAttribute(MCSymbol *Symbol, MCSymbolAttr Attribute );
	virtual void EmitSymbolDesc(MCSymbol *Symbol, unsigned DescValue);		virtual void EmitSymbolDesc(MCSymbol *Symbol, unsigned DescValue);
	virtual void EmitCommonSymbol(MCSymbol *Symbol, uint64_t Size,		virtual void EmitCommonSymbol(MCSymbol *Symbol, uint64_t Size,
	unsigned ByteAlignment);		unsigned ByteAlignment);
	virtual void BeginCOFFSymbolDef(const MCSymbol *Symbol);		virtual void BeginCOFFSymbolDef(const MCSymbol *Symbol);
	virtual void EmitCOFFSymbolStorageClass(int StorageClass);		virtual void EmitCOFFSymbolStorageClass(int StorageClass);
	virtual void EmitCOFFSymbolType(int Type);		virtual void EmitCOFFSymbolType(int Type);
	virtual void EndCOFFSymbolDef();		virtual void EndCOFFSymbolDef();
	virtual MCSymbolData &getOrCreateSymbolData(MCSymbol *Symbol);		virtual MCSymbolData &getOrCreateSymbolData(MCSymbol *Symbol);
	virtual void EmitELFSize(MCSymbol *Symbol, const MCExpr *Value);		virtual void EmitELFSize(MCSymbol *Symbol, const MCExpr *Value);
	virtual void EmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size,		virtual void EmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size,
	unsigned ByteAlignment);		unsigned ByteAlignment);
	virtual void EmitZerofill(const MCSection *Section, MCSymbol *Symbol = 0,		virtual void EmitZerofill(const MCSection *Section, MCSymbol *Symbol = 0,
	uint64_t Size = 0, unsigned ByteAlignment = 0);		uint64_t Size = 0, unsigned ByteAlignment = 0);
	virtual void EmitTBSSSymbol(const MCSection *Section, MCSymbol *Symbol,		virtual void EmitTBSSSymbol(const MCSection *Section, MCSymbol *Symbol,
	uint64_t Size, unsigned ByteAlignment = 0);		uint64_t Size, unsigned ByteAlignment = 0);
	virtual void EmitValueImpl(const MCExpr *Value, unsigned Size,		virtual void EmitValueImpl(const MCExpr *Value, unsigned Size);
	unsigned AddrSpace);
	virtual void EmitFileDirective(StringRef Filename);		virtual void EmitFileDirective(StringRef Filename);
	virtual void EmitTCEntry(const MCSymbol &S);		virtual void EmitIdent(StringRef IdentString);
	virtual void EmitValueToAlignment(unsigned, int64_t, unsigned, unsigned);		virtual void EmitValueToAlignment(unsigned, int64_t, unsigned, unsigned);
	virtual void FinishImpl();		virtual void Flush();
	/// @}
	static bool classof(const MCStreamer *S) {		virtual void FinishImpl();
	return S->getKind() == SK_ELFStreamer || S->getKind() == SK_ARMELFStrea
	mer;
	}
	private:		private:
	virtual void EmitInstToFragment(const MCInst &Inst);		virtual void EmitInstToFragment(const MCInst &Inst);
	virtual void EmitInstToData(const MCInst &Inst);		virtual void EmitInstToData(const MCInst &Inst);
	virtual void EmitBundleAlignMode(unsigned AlignPow2);		virtual void EmitBundleAlignMode(unsigned AlignPow2);
	virtual void EmitBundleLock(bool AlignToEnd);		virtual void EmitBundleLock(bool AlignToEnd);
	virtual void EmitBundleUnlock();		virtual void EmitBundleUnlock();
	void fixSymbolsInTLSFixups(const MCExpr *expr);		void fixSymbolsInTLSFixups(const MCExpr *expr);
			bool SeenIdent;
	struct LocalCommon {		struct LocalCommon {
	MCSymbolData *SD;		MCSymbolData *SD;
	uint64_t Size;		uint64_t Size;
	unsigned ByteAlignment;		unsigned ByteAlignment;
	};		};
	std::vector<LocalCommon> LocalCommons;		std::vector<LocalCommon> LocalCommons;
	SmallPtrSet<MCSymbol *, 16> BindingExplicitlySet;		SmallPtrSet<MCSymbol *, 16> BindingExplicitlySet;
	void SetSection(StringRef Section, unsigned Type, unsigned Flags,		void SetSection(StringRef Section, unsigned Type, unsigned Flags,
	SectionKind Kind);		SectionKind Kind);
	void SetSectionData();		void SetSectionData();
	void SetSectionText();		void SetSectionText();
	void SetSectionBss();		void SetSectionBss();
	};		};
			MCELFStreamer *createARMELFStreamer(MCContext &Context, MCAsmBackend &TAB,
			raw_ostream &OS, MCCodeEmitter *Emitter
			,
			bool RelaxAll, bool NoExecStack,
			bool IsThumb);
	} // end namespace llvm		} // end namespace llvm
	#endif		#endif
End of changes. 9 change blocks.
	23 lines changed or deleted		24 lines changed or added

	MCELFSymbolFlags.h		MCELFSymbolFlags.h
	skipping to change at line 30		skipping to change at line 30
	// 'flags' variable we need to provide shift constants per flag type.		// 'flags' variable we need to provide shift constants per flag type.
	namespace llvm {		namespace llvm {
	enum {		enum {
	ELF_STT_Shift = 0, // Shift value for STT_* flags.		ELF_STT_Shift = 0, // Shift value for STT_* flags.
	ELF_STB_Shift = 4, // Shift value for STB_* flags.		ELF_STB_Shift = 4, // Shift value for STB_* flags.
	ELF_STV_Shift = 8, // Shift value for STV_* flags.		ELF_STV_Shift = 8, // Shift value for STV_* flags.
	ELF_Other_Shift = 10 // Shift value for other flags.		ELF_Other_Shift = 10 // Shift value for other flags.
	};		};
	enum SymbolFlags {		enum ELFSymbolFlags {
	ELF_STB_Local = (ELF::STB_LOCAL << ELF_STB_Shift),		ELF_STB_Local = (ELF::STB_LOCAL << ELF_STB_Shift),
	ELF_STB_Global = (ELF::STB_GLOBAL << ELF_STB_Shift),		ELF_STB_Global = (ELF::STB_GLOBAL << ELF_STB_Shift),
	ELF_STB_Weak = (ELF::STB_WEAK << ELF_STB_Shift),		ELF_STB_Weak = (ELF::STB_WEAK << ELF_STB_Shift),
	ELF_STB_Loproc = (ELF::STB_LOPROC << ELF_STB_Shift),		ELF_STB_Loproc = (ELF::STB_LOPROC << ELF_STB_Shift),
	ELF_STB_Hiproc = (ELF::STB_HIPROC << ELF_STB_Shift),		ELF_STB_Hiproc = (ELF::STB_HIPROC << ELF_STB_Shift),
	ELF_STT_Notype = (ELF::STT_NOTYPE << ELF_STT_Shift),		ELF_STT_Notype = (ELF::STT_NOTYPE << ELF_STT_Shift),
	ELF_STT_Object = (ELF::STT_OBJECT << ELF_STT_Shift),		ELF_STT_Object = (ELF::STT_OBJECT << ELF_STT_Shift),
	ELF_STT_Func = (ELF::STT_FUNC << ELF_STT_Shift),		ELF_STT_Func = (ELF::STT_FUNC << ELF_STT_Shift),
	ELF_STT_Section = (ELF::STT_SECTION << ELF_STT_Shift),		ELF_STT_Section = (ELF::STT_SECTION << ELF_STT_Shift),
End of changes. 1 change blocks.
	1 lines changed or deleted		1 lines changed or added

	MCExpr.h		MCExpr.h
	skipping to change at line 174		skipping to change at line 174
	VK_ARM_PLT, // ARM-style PLT references. i.e., (PLT) instead of @PLT		VK_ARM_PLT, // ARM-style PLT references. i.e., (PLT) instead of @PLT
	VK_ARM_TLSGD, // ditto for TLSGD, GOT, GOTOFF, TPOFF and GOTTPOFF		VK_ARM_TLSGD, // ditto for TLSGD, GOT, GOTOFF, TPOFF and GOTTPOFF
	VK_ARM_GOT,		VK_ARM_GOT,
	VK_ARM_GOTOFF,		VK_ARM_GOTOFF,
	VK_ARM_TPOFF,		VK_ARM_TPOFF,
	VK_ARM_GOTTPOFF,		VK_ARM_GOTTPOFF,
	VK_ARM_TARGET1,		VK_ARM_TARGET1,
	VK_ARM_TARGET2,		VK_ARM_TARGET2,
	VK_ARM_PREL31,		VK_ARM_PREL31,
	VK_PPC_TOC, // TOC base		VK_PPC_LO, // symbol@l
	VK_PPC_TOC_ENTRY, // TOC entry		VK_PPC_HI, // symbol@h
	VK_PPC_DARWIN_HA16, // ha16(symbol)		VK_PPC_HA, // symbol@ha
	VK_PPC_DARWIN_LO16, // lo16(symbol)		VK_PPC_HIGHER, // symbol@higher
	VK_PPC_GAS_HA16, // symbol@ha		VK_PPC_HIGHERA, // symbol@highera
	VK_PPC_GAS_LO16, // symbol@l		VK_PPC_HIGHEST, // symbol@highest
	VK_PPC_TPREL16_HA, // symbol@tprel@ha		VK_PPC_HIGHESTA, // symbol@highesta
	VK_PPC_TPREL16_LO, // symbol@tprel@l		VK_PPC_GOT_LO, // symbol@got@l
	VK_PPC_DTPREL16_HA, // symbol@dtprel@ha		VK_PPC_GOT_HI, // symbol@got@h
	VK_PPC_DTPREL16_LO, // symbol@dtprel@l		VK_PPC_GOT_HA, // symbol@got@ha
	VK_PPC_TOC16_HA, // symbol@toc@ha		VK_PPC_TOCBASE, // symbol@tocbase
	VK_PPC_TOC16_LO, // symbol@toc@l		VK_PPC_TOC, // symbol@toc
	VK_PPC_GOT_TPREL16_HA, // symbol@got@tprel@ha		VK_PPC_TOC_LO, // symbol@toc@l
	VK_PPC_GOT_TPREL16_LO, // symbol@got@tprel@l		VK_PPC_TOC_HI, // symbol@toc@h
			VK_PPC_TOC_HA, // symbol@toc@ha
			VK_PPC_DTPMOD, // symbol@dtpmod
			VK_PPC_TPREL, // symbol@tprel
			VK_PPC_TPREL_LO, // symbol@tprel@l
			VK_PPC_TPREL_HI, // symbol@tprel@h
			VK_PPC_TPREL_HA, // symbol@tprel@ha
			VK_PPC_TPREL_HIGHER, // symbol@tprel@higher
			VK_PPC_TPREL_HIGHERA, // symbol@tprel@highera
			VK_PPC_TPREL_HIGHEST, // symbol@tprel@highest
			VK_PPC_TPREL_HIGHESTA, // symbol@tprel@highesta
			VK_PPC_DTPREL, // symbol@dtprel
			VK_PPC_DTPREL_LO, // symbol@dtprel@l
			VK_PPC_DTPREL_HI, // symbol@dtprel@h
			VK_PPC_DTPREL_HA, // symbol@dtprel@ha
			VK_PPC_DTPREL_HIGHER, // symbol@dtprel@higher
			VK_PPC_DTPREL_HIGHERA, // symbol@dtprel@highera
			VK_PPC_DTPREL_HIGHEST, // symbol@dtprel@highest
			VK_PPC_DTPREL_HIGHESTA,// symbol@dtprel@highesta
			VK_PPC_GOT_TPREL, // symbol@got@tprel
			VK_PPC_GOT_TPREL_LO, // symbol@got@tprel@l
			VK_PPC_GOT_TPREL_HI, // symbol@got@tprel@h
			VK_PPC_GOT_TPREL_HA, // symbol@got@tprel@ha
			VK_PPC_GOT_DTPREL, // symbol@got@dtprel
			VK_PPC_GOT_DTPREL_LO, // symbol@got@dtprel@l
			VK_PPC_GOT_DTPREL_HI, // symbol@got@dtprel@h
			VK_PPC_GOT_DTPREL_HA, // symbol@got@dtprel@ha
	VK_PPC_TLS, // symbol@tls		VK_PPC_TLS, // symbol@tls
	VK_PPC_GOT_TLSGD16_HA, // symbol@got@tlsgd@ha		VK_PPC_GOT_TLSGD, // symbol@got@tlsgd
	VK_PPC_GOT_TLSGD16_LO, // symbol@got@tlsgd@l		VK_PPC_GOT_TLSGD_LO, // symbol@got@tlsgd@l
			VK_PPC_GOT_TLSGD_HI, // symbol@got@tlsgd@h
			VK_PPC_GOT_TLSGD_HA, // symbol@got@tlsgd@ha
	VK_PPC_TLSGD, // symbol@tlsgd		VK_PPC_TLSGD, // symbol@tlsgd
	VK_PPC_GOT_TLSLD16_HA, // symbol@got@tlsld@ha		VK_PPC_GOT_TLSLD, // symbol@got@tlsld
	VK_PPC_GOT_TLSLD16_LO, // symbol@got@tlsld@l		VK_PPC_GOT_TLSLD_LO, // symbol@got@tlsld@l
			VK_PPC_GOT_TLSLD_HI, // symbol@got@tlsld@h
			VK_PPC_GOT_TLSLD_HA, // symbol@got@tlsld@ha
	VK_PPC_TLSLD, // symbol@tlsld		VK_PPC_TLSLD, // symbol@tlsld
	VK_Mips_GPREL,		VK_Mips_GPREL,
	VK_Mips_GOT_CALL,		VK_Mips_GOT_CALL,
	VK_Mips_GOT16,		VK_Mips_GOT16,
	VK_Mips_GOT,		VK_Mips_GOT,
	VK_Mips_ABS_HI,		VK_Mips_ABS_HI,
	VK_Mips_ABS_LO,		VK_Mips_ABS_LO,
	VK_Mips_TLSGD,		VK_Mips_TLSGD,
	VK_Mips_TLSLDM,		VK_Mips_TLSLDM,
End of changes. 3 change blocks.
	18 lines changed or deleted		48 lines changed or added

	MCInstPrinter.h		MCInstPrinter.h
	skipping to change at line 24		skipping to change at line 24
	#include "llvm/Support/Format.h"		#include "llvm/Support/Format.h"
	namespace llvm {		namespace llvm {
	class MCInst;		class MCInst;
	class raw_ostream;		class raw_ostream;
	class MCAsmInfo;		class MCAsmInfo;
	class MCInstrInfo;		class MCInstrInfo;
	class MCRegisterInfo;		class MCRegisterInfo;
	class StringRef;		class StringRef;
			namespace HexStyle {
			enum Style {
			C, ///< 0xff
			Asm ///< 0ffh
			};
			}
	/// MCInstPrinter - This is an instance of a target assembly language print er		/// MCInstPrinter - This is an instance of a target assembly language print er
	/// that converts an MCInst to valid target assembly syntax.		/// that converts an MCInst to valid target assembly syntax.
	class MCInstPrinter {		class MCInstPrinter {
	protected:		protected:
	/// CommentStream - a stream that comments can be emitted to if desired.		/// CommentStream - a stream that comments can be emitted to if desired.
	/// Each comment must end with a newline. This will be null if verbose		/// Each comment must end with a newline. This will be null if verbose
	/// assembly emission is disable.		/// assembly emission is disable.
	raw_ostream *CommentStream;		raw_ostream *CommentStream;
	const MCAsmInfo &MAI;		const MCAsmInfo &MAI;
	const MCInstrInfo &MII;		const MCInstrInfo &MII;
	const MCRegisterInfo &MRI;		const MCRegisterInfo &MRI;
	/// The current set of available features.		/// The current set of available features.
	unsigned AvailableFeatures;		uint64_t AvailableFeatures;
	/// True if we are printing marked up assembly.		/// True if we are printing marked up assembly.
	bool UseMarkup;		bool UseMarkup;
	/// True if we are printing immediates as hex.		/// True if we are printing immediates as hex.
	bool PrintImmHex;		bool PrintImmHex;
			/// Which style to use for printing hexadecimal values.
			HexStyle::Style PrintHexStyle;
	/// Utility function for printing annotations.		/// Utility function for printing annotations.
	void printAnnotation(raw_ostream &OS, StringRef Annot);		void printAnnotation(raw_ostream &OS, StringRef Annot);
	public:		public:
	MCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii,		MCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii,
	const MCRegisterInfo &mri)		const MCRegisterInfo &mri)
	: CommentStream(0), MAI(mai), MII(mii), MRI(mri), AvailableFeatures(0),		: CommentStream(0), MAI(mai), MII(mii), MRI(mri), AvailableFeatures(0),
	UseMarkup(0), PrintImmHex(0) {}		UseMarkup(0), PrintImmHex(0), PrintHexStyle(HexStyle::C) {}
	virtual ~MCInstPrinter();		virtual ~MCInstPrinter();
	/// setCommentStream - Specify a stream to emit comments to.		/// setCommentStream - Specify a stream to emit comments to.
	void setCommentStream(raw_ostream &OS) { CommentStream = &OS; }		void setCommentStream(raw_ostream &OS) { CommentStream = &OS; }
	/// printInst - Print the specified MCInst to the specified raw_ostream.		/// printInst - Print the specified MCInst to the specified raw_ostream.
	///		///
	virtual void printInst(const MCInst *MI, raw_ostream &OS,		virtual void printInst(const MCInst *MI, raw_ostream &OS,
	StringRef Annot) = 0;		StringRef Annot) = 0;
	/// getOpcodeName - Return the name of the specified opcode enum (e.g.		/// getOpcodeName - Return the name of the specified opcode enum (e.g.
	/// "MOV32ri") or empty if we can't resolve it.		/// "MOV32ri") or empty if we can't resolve it.
	StringRef getOpcodeName(unsigned Opcode) const;		StringRef getOpcodeName(unsigned Opcode) const;
	/// printRegName - Print the assembler register name.		/// printRegName - Print the assembler register name.
	virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;		virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
	unsigned getAvailableFeatures() const { return AvailableFeatures; }		uint64_t getAvailableFeatures() const { return AvailableFeatures; }
	void setAvailableFeatures(unsigned Value) { AvailableFeatures = Value; }		void setAvailableFeatures(uint64_t Value) { AvailableFeatures = Value; }
	bool getUseMarkup() const { return UseMarkup; }		bool getUseMarkup() const { return UseMarkup; }
	void setUseMarkup(bool Value) { UseMarkup = Value; }		void setUseMarkup(bool Value) { UseMarkup = Value; }
	/// Utility functions to make adding mark ups simpler.		/// Utility functions to make adding mark ups simpler.
	StringRef markup(StringRef s) const;		StringRef markup(StringRef s) const;
	StringRef markup(StringRef a, StringRef b) const;		StringRef markup(StringRef a, StringRef b) const;
	bool getPrintImmHex() const { return PrintImmHex; }		bool getPrintImmHex() const { return PrintImmHex; }
	void setPrintImmHex(bool Value) { PrintImmHex = Value; }		void setPrintImmHex(bool Value) { PrintImmHex = Value; }
			HexStyle::Style getPrintHexStyleHex() const { return PrintHexStyle; }
			void setPrintImmHex(HexStyle::Style Value) { PrintHexStyle = Value; }
	/// Utility function to print immediates in decimal or hex.		/// Utility function to print immediates in decimal or hex.
	format_object1<int64_t> formatImm(const int64_t Value) const;		format_object1<int64_t> formatImm(const int64_t Value) const { return Pri
			ntImmHex ? formatHex(Value) : formatDec(Value); }
			/// Utility functions to print decimal/hexadecimal values.
			format_object1<int64_t> formatDec(const int64_t Value) const;
			format_object1<int64_t> formatHex(const int64_t Value) const;
			format_object1<uint64_t> formatHex(const uint64_t Value) const;
	};		};
	} // namespace llvm		} // namespace llvm
	#endif		#endif
End of changes. 7 change blocks.
	5 lines changed or deleted		24 lines changed or added

	MCInstrAnalysis.h		MCInstrAnalysis.h
	skipping to change at line 55		skipping to change at line 55
	}		}
	virtual bool isCall(const MCInst &Inst) const {		virtual bool isCall(const MCInst &Inst) const {
	return Info->get(Inst.getOpcode()).isCall();		return Info->get(Inst.getOpcode()).isCall();
	}		}
	virtual bool isReturn(const MCInst &Inst) const {		virtual bool isReturn(const MCInst &Inst) const {
	return Info->get(Inst.getOpcode()).isReturn();		return Info->get(Inst.getOpcode()).isReturn();
	}		}
			virtual bool isTerminator(const MCInst &Inst) const {
			return Info->get(Inst.getOpcode()).isTerminator();
			}
	/// evaluateBranch - Given a branch instruction try to get the address th e		/// evaluateBranch - Given a branch instruction try to get the address th e
	/// branch targets. Otherwise return -1.		/// branch targets. Return true on success, and the address in Target.
	virtual uint64_t		virtual bool
	evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size) const;		evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
			uint64_t &Target) const;
	};		};
	}		}
End of changes. 2 change blocks.
	3 lines changed or deleted		8 lines changed or added

	MCInstrDesc.h		MCInstrDesc.h
	skipping to change at line 20		skipping to change at line 20
	// This file defines the MCOperandInfo and MCInstrDesc classes, which		// This file defines the MCOperandInfo and MCInstrDesc classes, which
	// are used to describe target instructions and their operands.		// are used to describe target instructions and their operands.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_MC_MCINSTRDESC_H		#ifndef LLVM_MC_MCINSTRDESC_H
	#define LLVM_MC_MCINSTRDESC_H		#define LLVM_MC_MCINSTRDESC_H
	#include "llvm/MC/MCInst.h"		#include "llvm/MC/MCInst.h"
	#include "llvm/MC/MCRegisterInfo.h"		#include "llvm/MC/MCRegisterInfo.h"
			#include "llvm/MC/MCSubtargetInfo.h"
	#include "llvm/Support/DataTypes.h"		#include "llvm/Support/DataTypes.h"
	namespace llvm {		namespace llvm {
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// Machine Operand Flags and Description		// Machine Operand Flags and Description
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	namespace MCOI {		namespace MCOI {
	// Operand constraints		// Operand constraints
	skipping to change at line 147		skipping to change at line 148
	unsigned short Opcode; // The opcode number		unsigned short Opcode; // The opcode number
	unsigned short NumOperands; // Num of args (may be more if variable_op s)		unsigned short NumOperands; // Num of args (may be more if variable_op s)
	unsigned short NumDefs; // Num of args that are definitions		unsigned short NumDefs; // Num of args that are definitions
	unsigned short SchedClass; // enum identifying instr sched class		unsigned short SchedClass; // enum identifying instr sched class
	unsigned short Size; // Number of bytes in encoding.		unsigned short Size; // Number of bytes in encoding.
	unsigned Flags; // Flags identifying machine instr class		unsigned Flags; // Flags identifying machine instr class
	uint64_t TSFlags; // Target Specific Flag values		uint64_t TSFlags; // Target Specific Flag values
	const uint16_t *ImplicitUses; // Registers implicitly read by this instr		const uint16_t *ImplicitUses; // Registers implicitly read by this instr
	const uint16_t *ImplicitDefs; // Registers implicitly defined by this in str		const uint16_t *ImplicitDefs; // Registers implicitly defined by this in str
	const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands		const MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
			uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated on
			, if any
			// A complex method to determine is a certain is deprecated or not, and r
			eturn
			// the reason for deprecation.
			bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &
			);
	/// \brief Returns the value of the specific constraint if		/// \brief Returns the value of the specific constraint if
	/// it is set. Returns -1 if it is not set.		/// it is set. Returns -1 if it is not set.
	int getOperandConstraint(unsigned OpNum,		int getOperandConstraint(unsigned OpNum,
	MCOI::OperandConstraint Constraint) const {		MCOI::OperandConstraint Constraint) const {
	if (OpNum < NumOperands &&		if (OpNum < NumOperands &&
	(OpInfo[OpNum].Constraints & (1 << Constraint))) {		(OpInfo[OpNum].Constraints & (1 << Constraint))) {
	unsigned Pos = 16 + Constraint * 4;		unsigned Pos = 16 + Constraint * 4;
	return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;		return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
	}		}
	return -1;		return -1;
	}		}
			/// \brief Returns true if a certain instruction is deprecated and if so
			/// returns the reason in \p Info.
			bool getDeprecatedInfo(MCInst &MI, MCSubtargetInfo &STI,
			std::string &Info) const {
			if (ComplexDeprecationInfo)
			return ComplexDeprecationInfo(MI, STI, Info);
			if ((DeprecatedFeatureMask & STI.getFeatureBits()) != 0) {
			// FIXME: it would be nice to include the subtarget feature here.
			Info = "deprecated";
			return true;
			}
			return false;
			}
	/// \brief Return the opcode number for this descriptor.		/// \brief Return the opcode number for this descriptor.
	unsigned getOpcode() const {		unsigned getOpcode() const {
	return Opcode;		return Opcode;
	}		}
	/// \brief Return the number of declared MachineOperands for this		/// \brief Return the number of declared MachineOperands for this
	/// MachineInstruction. Note that variadic (isVariadic() returns true)		/// MachineInstruction. Note that variadic (isVariadic() returns true)
	/// instructions may have additional operands at the end of the list, and note		/// instructions may have additional operands at the end of the list, and note
	/// that the machine instruction may include implicit register def/uses a s		/// that the machine instruction may include implicit register def/uses a s
	/// well.		/// well.
	skipping to change at line 270		skipping to change at line 289
	return isBranch() & isBarrier() & !isIndirectBranch();		return isBranch() & isBarrier() & !isIndirectBranch();
	}		}
	/// \brief Return true if this is a branch or an instruction which direct ly		/// \brief Return true if this is a branch or an instruction which direct ly
	/// writes to the program counter. Considered 'may' affect rather than		/// writes to the program counter. Considered 'may' affect rather than
	/// 'does' affect as things like predication are not taken into account.		/// 'does' affect as things like predication are not taken into account.
	bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) con st {		bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) con st {
	if (isBranch() || isCall() || isReturn() || isIndirectBranch())		if (isBranch() || isCall() || isReturn() || isIndirectBranch())
	return true;		return true;
	unsigned PC = RI.getProgramCounter();		unsigned PC = RI.getProgramCounter();
	if (PC == 0) return false;		if (PC == 0)
	return hasDefOfPhysReg(MI, PC, RI);		return false;
			if (hasDefOfPhysReg(MI, PC, RI))
			return true;
			// A variadic instruction may define PC in the variable operand list.
			// There's currently no indication of which entries in a variable
			// list are defs and which are uses. While that's the case, this functi
			on
			// needs to assume they're defs in order to be conservatively correct.
			for (int i = NumOperands, e = MI.getNumOperands(); i != e; ++i) {
			if (MI.getOperand(i).isReg() &&
			RI.isSubRegisterEq(PC, MI.getOperand(i).getReg()))
			return true;
			}
			return false;
	}		}
	/// \brief Return true if this instruction has a predicate operand		/// \brief Return true if this instruction has a predicate operand
	/// that controls execution. It may be set to 'always', or may be set to other		/// that controls execution. It may be set to 'always', or may be set to other
	/// values. There are various methods in TargetInstrInfo that can be used to		/// values. There are various methods in TargetInstrInfo that can be used to
	/// control and modify the predicate in this instruction.		/// control and modify the predicate in this instruction.
	bool isPredicable() const {		bool isPredicable() const {
	return Flags & (1 << MCID::Predicable);		return Flags & (1 << MCID::Predicable);
	}		}
End of changes. 4 change blocks.
	2 lines changed or deleted		37 lines changed or added

	MCInstrItineraries.h		MCInstrItineraries.h
	skipping to change at line 158		skipping to change at line 158
	///		///
	const InstrStage *endStage(unsigned ItinClassIndx) const {		const InstrStage *endStage(unsigned ItinClassIndx) const {
	unsigned StageIdx = Itineraries[ItinClassIndx].LastStage;		unsigned StageIdx = Itineraries[ItinClassIndx].LastStage;
	return Stages + StageIdx;		return Stages + StageIdx;
	}		}
	/// getStageLatency - Return the total stage latency of the given		/// getStageLatency - Return the total stage latency of the given
	/// class. The latency is the maximum completion time for any stage		/// class. The latency is the maximum completion time for any stage
	/// in the itinerary.		/// in the itinerary.
	///		///
	/// InstrStages override the itinerary's MinLatency property. In fact, if		/// If no stages exist, it defaults to one cycle.
	the
	/// stage latencies, which may be zero, are less than MinLatency,
	/// getStageLatency returns a value less than MinLatency.
	///
	/// If no stages exist, MinLatency is used. If MinLatency is invalid (<0)
	,
	/// then it defaults to one cycle.
	unsigned getStageLatency(unsigned ItinClassIndx) const {		unsigned getStageLatency(unsigned ItinClassIndx) const {
	// If the target doesn't provide itinerary information, use a simple		// If the target doesn't provide itinerary information, use a simple
	// non-zero default value for all instructions.		// non-zero default value for all instructions.
	if (isEmpty())		if (isEmpty())
	return SchedModel->MinLatency < 0 ? 1 : SchedModel->MinLatency;		return 1;
	// Calculate the maximum completion time for any stage.		// Calculate the maximum completion time for any stage.
	unsigned Latency = 0, StartCycle = 0;		unsigned Latency = 0, StartCycle = 0;
	for (const InstrStage *IS = beginStage(ItinClassIndx),		for (const InstrStage *IS = beginStage(ItinClassIndx),
	*E = endStage(ItinClassIndx); IS != E; ++IS) {		*E = endStage(ItinClassIndx); IS != E; ++IS) {
	Latency = std::max(Latency, StartCycle + IS->getCycles());		Latency = std::max(Latency, StartCycle + IS->getCycles());
	StartCycle += IS->getNextCycles();		StartCycle += IS->getNextCycles();
	}		}
	return Latency;		return Latency;
	}		}
	/// getOperandCycle - Return the cycle for the given class and		/// getOperandCycle - Return the cycle for the given class and
	/// operand. Return -1 if no cycle is specified for the operand.		/// operand. Return -1 if no cycle is specified for the operand.
	///		///
	int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const {		int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const {
	if (isEmpty())		if (isEmpty())
	return -1;		return -1;
End of changes. 3 change blocks.
	10 lines changed or deleted		2 lines changed or added

	MCMachOSymbolFlags.h		MCMachOSymbolFlags.h
	skipping to change at line 22		skipping to change at line 22
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_MC_MCMACHOSYMBOLFLAGS_H		#ifndef LLVM_MC_MCMACHOSYMBOLFLAGS_H
	#define LLVM_MC_MCMACHOSYMBOLFLAGS_H		#define LLVM_MC_MCMACHOSYMBOLFLAGS_H
	// These flags are mostly used in MCMachOStreamer.cpp but also needed in		// These flags are mostly used in MCMachOStreamer.cpp but also needed in
	// MachObjectWriter.cpp to test for Weak Definitions of symbols to emit		// MachObjectWriter.cpp to test for Weak Definitions of symbols to emit
	// the correct relocation information.		// the correct relocation information.
	namespace llvm {		namespace llvm {
	/// SymbolFlags - We store the value for the 'desc' symbol field in the l		/// MachOSymbolFlags - We store the value for the 'desc' symbol field in
	owest		the
	/// 16 bits of the implementation defined flags.		/// lowest 16 bits of the implementation defined flags.
	enum SymbolFlags { // See <mach-o/nlist.h>.		enum MachOSymbolFlags { // See <mach-o/nlist.h>.
	SF_DescFlagsMask = 0xFFFF,		SF_DescFlagsMask = 0xFFFF,
	// Reference type flags.		// Reference type flags.
	SF_ReferenceTypeMask = 0x0007,		SF_ReferenceTypeMask = 0x0007,
	SF_ReferenceTypeUndefinedNonLazy = 0x0000,		SF_ReferenceTypeUndefinedNonLazy = 0x0000,
	SF_ReferenceTypeUndefinedLazy = 0x0001,		SF_ReferenceTypeUndefinedLazy = 0x0001,
	SF_ReferenceTypeDefined = 0x0002,		SF_ReferenceTypeDefined = 0x0002,
	SF_ReferenceTypePrivateDefined = 0x0003,		SF_ReferenceTypePrivateDefined = 0x0003,
	SF_ReferenceTypePrivateUndefinedNonLazy = 0x0004,		SF_ReferenceTypePrivateUndefinedNonLazy = 0x0004,
	SF_ReferenceTypePrivateUndefinedLazy = 0x0005,		SF_ReferenceTypePrivateUndefinedLazy = 0x0005,
End of changes. 1 change blocks.
	4 lines changed or deleted		4 lines changed or added

	MCMachObjectWriter.h		MCMachObjectWriter.h
	skipping to change at line 18		skipping to change at line 18
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_MC_MCMACHOBJECTWRITER_H		#ifndef LLVM_MC_MCMACHOBJECTWRITER_H
	#define LLVM_MC_MCMACHOBJECTWRITER_H		#define LLVM_MC_MCMACHOBJECTWRITER_H
	#include "llvm/ADT/DenseMap.h"		#include "llvm/ADT/DenseMap.h"
	#include "llvm/ADT/OwningPtr.h"		#include "llvm/ADT/OwningPtr.h"
	#include "llvm/ADT/SmallString.h"		#include "llvm/ADT/SmallString.h"
	#include "llvm/MC/MCExpr.h"		#include "llvm/MC/MCExpr.h"
	#include "llvm/MC/MCObjectWriter.h"		#include "llvm/MC/MCObjectWriter.h"
	#include "llvm/Object/MachOFormat.h"
	#include "llvm/Support/DataTypes.h"		#include "llvm/Support/DataTypes.h"
			#include "llvm/Support/MachO.h"
	#include <vector>		#include <vector>
	namespace llvm {		namespace llvm {
	class MCSectionData;		class MCSectionData;
	class MachObjectWriter;		class MachObjectWriter;
	class MCMachObjectTargetWriter {		class MCMachObjectTargetWriter {
	const unsigned Is64Bit : 1;		const unsigned Is64Bit : 1;
	const uint32_t CPUType;		const uint32_t CPUType;
	skipping to change at line 101		skipping to change at line 101
	bool operator<(const MachSymbolData &RHS) const;		bool operator<(const MachSymbolData &RHS) const;
	};		};
	/// The target specific Mach-O writer instance.		/// The target specific Mach-O writer instance.
	llvm::OwningPtr<MCMachObjectTargetWriter> TargetObjectWriter;		llvm::OwningPtr<MCMachObjectTargetWriter> TargetObjectWriter;
	/// @name Relocation Data		/// @name Relocation Data
	/// @{		/// @{
	llvm::DenseMap<const MCSectionData*,		llvm::DenseMap<const MCSectionData*,
	std::vector<object::macho::RelocationEntry> > Relocations;		std::vector<MachO::any_relocation_info> > Relocations;
	llvm::DenseMap<const MCSectionData*, unsigned> IndirectSymBase;		llvm::DenseMap<const MCSectionData*, unsigned> IndirectSymBase;
	/// @}		/// @}
	/// @name Symbol Table Data		/// @name Symbol Table Data
	/// @{		/// @{
	SmallString<256> StringTable;		SmallString<256> StringTable;
	std::vector<MachSymbolData> LocalSymbolData;		std::vector<MachSymbolData> LocalSymbolData;
	std::vector<MachSymbolData> ExternalSymbolData;		std::vector<MachSymbolData> ExternalSymbolData;
	std::vector<MachSymbolData> UndefinedSymbolData;		std::vector<MachSymbolData> UndefinedSymbolData;
	skipping to change at line 158		skipping to change at line 158
	bool doesSymbolRequireExternRelocation(const MCSymbolData *SD);		bool doesSymbolRequireExternRelocation(const MCSymbolData *SD);
	/// @}		/// @}
	/// @name Target Writer Proxy Accessors		/// @name Target Writer Proxy Accessors
	/// @{		/// @{
	bool is64Bit() const { return TargetObjectWriter->is64Bit(); }		bool is64Bit() const { return TargetObjectWriter->is64Bit(); }
	bool isARM() const {		bool isARM() const {
	uint32_t CPUType = TargetObjectWriter->getCPUType() &		uint32_t CPUType = TargetObjectWriter->getCPUType() & ~MachO::CPU_ARCH_
	~object::mach::CTFM_ArchMask;		MASK;
	return CPUType == object::mach::CTM_ARM;		return CPUType == MachO::CPU_TYPE_ARM;
	}		}
	/// @}		/// @}
	void WriteHeader(unsigned NumLoadCommands, unsigned LoadCommandsSize,		void WriteHeader(unsigned NumLoadCommands, unsigned LoadCommandsSize,
	bool SubsectionsViaSymbols);		bool SubsectionsViaSymbols);
	/// WriteSegmentLoadCommand - Write a segment load command.		/// WriteSegmentLoadCommand - Write a segment load command.
	///		///
	/// \param NumSections The number of sections in this segment.		/// \param NumSections The number of sections in this segment.
	skipping to change at line 216		skipping to change at line 215
	//		//
	// - Relocation entry bugs, the two algorithms are unlikely to have the same		// - Relocation entry bugs, the two algorithms are unlikely to have the same
	// exact bug.		// exact bug.
	//		//
	// - Relaxation issues, where we forget to relax something.		// - Relaxation issues, where we forget to relax something.
	//		//
	// - Input errors, where something cannot be correctly encoded. 'as' all ows		// - Input errors, where something cannot be correctly encoded. 'as' all ows
	// these through in many cases.		// these through in many cases.
	void addRelocation(const MCSectionData *SD,		void addRelocation(const MCSectionData *SD,
	object::macho::RelocationEntry &MRE) {		MachO::any_relocation_info &MRE) {
	Relocations[SD].push_back(MRE);		Relocations[SD].push_back(MRE);
	}		}
	void RecordScatteredRelocation(const MCAssembler &Asm,		void RecordScatteredRelocation(const MCAssembler &Asm,
	const MCAsmLayout &Layout,		const MCAsmLayout &Layout,
	const MCFragment *Fragment,		const MCFragment *Fragment,
	const MCFixup &Fixup, MCValue Target,		const MCFixup &Fixup, MCValue Target,
	unsigned Log2Size,		unsigned Log2Size,
	uint64_t &FixedValue);		uint64_t &FixedValue);
End of changes. 5 change blocks.
	6 lines changed or deleted		6 lines changed or added

	MCModule.h		MCModule.h
	skipping to change at line 18		skipping to change at line 18
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This file contains the declaration of the MCModule class, which is used to		// This file contains the declaration of the MCModule class, which is used to
	// represent a complete, disassembled object file or executable.		// represent a complete, disassembled object file or executable.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_MC_MCMODULE_H		#ifndef LLVM_MC_MCMODULE_H
	#define LLVM_MC_MCMODULE_H		#define LLVM_MC_MCMODULE_H
	#include "llvm/ADT/DenseMap.h"		#include "llvm/ADT/StringRef.h"
	#include "llvm/ADT/IntervalMap.h"		#include "llvm/Support/Compiler.h"
	#include "llvm/ADT/SmallPtrSet.h"
	#include "llvm/Support/DataTypes.h"		#include "llvm/Support/DataTypes.h"
			#include <vector>
	namespace llvm {		namespace llvm {
	class MCAtom;		class MCAtom;
			class MCBasicBlock;
	/// MCModule - This class represent a completely disassembled object file o		class MCDataAtom;
	r		class MCFunction;
	/// executable. It comprises a list of MCAtom's, and a branch target table		class MCObjectDisassembler;
	.		class MCTextAtom;
	/// Each atom represents a contiguous range of either instructions or data.
			/// \brief A completely disassembled object file or executable.
			/// It comprises a list of MCAtom's, each representing a contiguous range o
			f
			/// either instructions or data.
			/// An MCModule is created using MCObjectDisassembler::buildModule.
	class MCModule {		class MCModule {
	/// AtomAllocationTracker - An MCModule owns its component MCAtom's, so i		/// \name Atom tracking
	t		/// @{
	/// must track them in order to ensure they are properly freed as atoms a
	re		/// \brief Atoms in this module, sorted by begin address.
	/// merged or otherwise manipulated.		/// FIXME: This doesn't handle overlapping atoms (which happen when a bas
	SmallPtrSet<MCAtom*, 8> AtomAllocationTracker;		ic
			/// block starts in the middle of an instruction of another basic block.)
	/// OffsetMap - Efficiently maps offset ranges to MCAtom's.		typedef std::vector<MCAtom*> AtomListTy;
	IntervalMap<uint64_t, MCAtom*> OffsetMap;		AtomListTy Atoms;
	/// BranchTargetMap - Maps offsets that are determined to be branches and
	/// can be statically resolved to their target offsets.
	DenseMap<uint64_t, MCAtom*> BranchTargetMap;
			// For access to map/remap.
	friend class MCAtom;		friend class MCAtom;
	/// remap - Update the interval mapping for an MCAtom.		/// \brief Remap \p Atom to the given range, and update its Begin/End fie
			lds.
			/// \param Atom An atom belonging to this module.
			/// An atom should always use this method to update its bounds, because t
			his
			/// enables the owning MCModule to keep track of its atoms.
	void remap(MCAtom *Atom, uint64_t NewBegin, uint64_t NewEnd);		void remap(MCAtom *Atom, uint64_t NewBegin, uint64_t NewEnd);
			/// \brief Insert an atom in the module, using its Begin and End addresse
			s.
			void map(MCAtom *NewAtom);
			/// @}
			/// \name Basic block tracking
			/// @{
			typedef std::vector<MCBasicBlock*> BBsByAtomTy;
			BBsByAtomTy BBsByAtom;
			// For access to basic block > atom tracking.
			friend class MCBasicBlock;
			friend class MCTextAtom;
			/// \brief Keep track of \p BBBackedByAtom as being backed by \p Atom.
			/// This is used to update succs/preds when \p Atom is split.
			void trackBBForAtom(const MCTextAtom *Atom, MCBasicBlock *BBBackedByAtom)
			;
			void splitBasicBlocksForAtom(const MCTextAtom *TA, const MCTextAtom *NewT
			A);
			/// @}
			/// \name Function tracking
			/// @{
			typedef std::vector<MCFunction*> FunctionListTy;
			FunctionListTy Functions;
			/// @}
			/// The address of the entrypoint function.
			uint64_t Entrypoint;
			MCModule (const MCModule &) LLVM_DELETED_FUNCTION;
			MCModule& operator=(const MCModule &) LLVM_DELETED_FUNCTION;
			// MCObjectDisassembler creates MCModules.
			friend class MCObjectDisassembler;
	public:		public:
	MCModule(IntervalMap<uint64_t, MCAtom*>::Allocator &A) : OffsetMap(A) { }		MCModule() : Entrypoint(0) { }
			~MCModule();
			/// \name Create a new MCAtom covering the specified offset range.
			/// @{
			MCTextAtom *createTextAtom(uint64_t Begin, uint64_t End);
			MCDataAtom *createDataAtom(uint64_t Begin, uint64_t End);
			/// @}
			/// \name Access to the owned atom list, ordered by begin address.
			/// @{
			const MCAtom *findAtomContaining(uint64_t Addr) const;
			MCAtom *findAtomContaining(uint64_t Addr);
			const MCAtom *findFirstAtomAfter(uint64_t Addr) const;
			MCAtom *findFirstAtomAfter(uint64_t Addr);
			typedef AtomListTy::const_iterator const_atom_iterator;
			typedef AtomListTy:: iterator atom_iterator;
			const_atom_iterator atom_begin() const { return Atoms.begin(); }
			atom_iterator atom_begin() { return Atoms.begin(); }
			const_atom_iterator atom_end() const { return Atoms.end(); }
			atom_iterator atom_end() { return Atoms.end(); }
			/// @}
			/// \brief Create a new MCFunction.
			MCFunction *createFunction(StringRef Name);
			/// \name Access to the owned function list.
			/// @{
			typedef FunctionListTy::const_iterator const_func_iterator;
			typedef FunctionListTy:: iterator func_iterator;
			const_func_iterator func_begin() const { return Functions.begin(); }
			func_iterator func_begin() { return Functions.begin(); }
			const_func_iterator func_end() const { return Functions.end(); }
			func_iterator func_end() { return Functions.end(); }
			/// @}
	/// createAtom - Creates a new MCAtom covering the specified offset range		/// \brief Get the address of the entrypoint function, or 0 if there is n
	.		one.
	MCAtom *createAtom(MCAtom::AtomType Type, uint64_t Begin, uint64_t End);		uint64_t getEntrypoint() const { return Entrypoint; }
	};		};
	}		}
	#endif		#endif
End of changes. 9 change blocks.
	27 lines changed or deleted		106 lines changed or added

	MCObjectFileInfo.h		MCObjectFileInfo.h
	skipping to change at line 128		skipping to change at line 128
	/// These are used for the Fission separate debug information files.		/// These are used for the Fission separate debug information files.
	const MCSection *DwarfInfoDWOSection;		const MCSection *DwarfInfoDWOSection;
	const MCSection *DwarfAbbrevDWOSection;		const MCSection *DwarfAbbrevDWOSection;
	const MCSection *DwarfStrDWOSection;		const MCSection *DwarfStrDWOSection;
	const MCSection *DwarfLineDWOSection;		const MCSection *DwarfLineDWOSection;
	const MCSection *DwarfLocDWOSection;		const MCSection *DwarfLocDWOSection;
	const MCSection *DwarfStrOffDWOSection;		const MCSection *DwarfStrOffDWOSection;
	const MCSection *DwarfAddrSection;		const MCSection *DwarfAddrSection;
			/// Sections for newer gnu pubnames and pubtypes.
			const MCSection *DwarfGnuPubNamesSection;
			const MCSection *DwarfGnuPubTypesSection;
	// Extra TLS Variable Data section. If the target needs to put additiona l		// Extra TLS Variable Data section. If the target needs to put additiona l
	// information for a TLS variable, it'll go here.		// information for a TLS variable, it'll go here.
	const MCSection *TLSExtraDataSection;		const MCSection *TLSExtraDataSection;
	/// TLSDataSection - Section directive for Thread Local data.		/// TLSDataSection - Section directive for Thread Local data.
	/// ELF, MachO and COFF.		/// ELF, MachO and COFF.
	const MCSection *TLSDataSection; // Defaults to ".tdata".		const MCSection *TLSDataSection; // Defaults to ".tdata".
	/// TLSBSSSection - Section directive for Thread Local uninitialized data .		/// TLSBSSSection - Section directive for Thread Local uninitialized data .
	/// Null if this target doesn't support a BSS section.		/// Null if this target doesn't support a BSS section.
	/// ELF and MachO only.		/// ELF and MachO only.
	const MCSection *TLSBSSSection; // Defaults to ".tbss".		const MCSection *TLSBSSSection; // Defaults to ".tbss".
			/// StackMap section.
			const MCSection *StackMapSection;
	/// EHFrameSection - EH frame section. It is initialized on demand so it		/// EHFrameSection - EH frame section. It is initialized on demand so it
	/// can be overwritten (with uniquing).		/// can be overwritten (with uniquing).
	const MCSection *EHFrameSection;		const MCSection *EHFrameSection;
	/// ELF specific sections.		/// ELF specific sections.
	///		///
	const MCSection *DataRelSection;		const MCSection *DataRelSection;
	const MCSection *DataRelLocalSection;		const MCSection *DataRelLocalSection;
	const MCSection *DataRelROSection;		const MCSection *DataRelROSection;
	const MCSection *DataRelROLocalSection;		const MCSection *DataRelROLocalSection;
	skipping to change at line 225		skipping to change at line 232
	const MCSection *getLSDASection() const { return LSDASection; }		const MCSection *getLSDASection() const { return LSDASection; }
	const MCSection *getCompactUnwindSection() const{		const MCSection *getCompactUnwindSection() const{
	return CompactUnwindSection;		return CompactUnwindSection;
	}		}
	const MCSection *getDwarfAbbrevSection() const { return DwarfAbbrevSectio n; }		const MCSection *getDwarfAbbrevSection() const { return DwarfAbbrevSectio n; }
	const MCSection *getDwarfInfoSection() const { return DwarfInfoSection; }		const MCSection *getDwarfInfoSection() const { return DwarfInfoSection; }
	const MCSection *getDwarfLineSection() const { return DwarfLineSection; }		const MCSection *getDwarfLineSection() const { return DwarfLineSection; }
	const MCSection *getDwarfFrameSection() const { return DwarfFrameSection; }		const MCSection *getDwarfFrameSection() const { return DwarfFrameSection; }
	const MCSection *getDwarfPubNamesSection() const{return DwarfPubNamesSect ion;}		const MCSection *getDwarfPubNamesSection() const{return DwarfPubNamesSect ion;}
	const MCSection *getDwarfPubTypesSection() const{return DwarfPubTypesSect ion;}		const MCSection *getDwarfPubTypesSection() const{return DwarfPubTypesSect ion;}
			const MCSection *getDwarfGnuPubNamesSection() const {
			return DwarfGnuPubNamesSection;
			}
			const MCSection *getDwarfGnuPubTypesSection() const {
			return DwarfGnuPubTypesSection;
			}
	const MCSection *getDwarfDebugInlineSection() const {		const MCSection *getDwarfDebugInlineSection() const {
	return DwarfDebugInlineSection;		return DwarfDebugInlineSection;
	}		}
	const MCSection *getDwarfStrSection() const { return DwarfStrSection; }		const MCSection *getDwarfStrSection() const { return DwarfStrSection; }
	const MCSection *getDwarfLocSection() const { return DwarfLocSection; }		const MCSection *getDwarfLocSection() const { return DwarfLocSection; }
	const MCSection *getDwarfARangesSection() const { return DwarfARangesSect ion;}		const MCSection *getDwarfARangesSection() const { return DwarfARangesSect ion;}
	const MCSection *getDwarfRangesSection() const { return DwarfRangesSectio n; }		const MCSection *getDwarfRangesSection() const { return DwarfRangesSectio n; }
	const MCSection *getDwarfMacroInfoSection() const {		const MCSection *getDwarfMacroInfoSection() const {
	return DwarfMacroInfoSection;		return DwarfMacroInfoSection;
	}		}
	skipping to change at line 277		skipping to change at line 290
	const MCSection *getDwarfAddrSection() const {		const MCSection *getDwarfAddrSection() const {
	return DwarfAddrSection;		return DwarfAddrSection;
	}		}
	const MCSection *getTLSExtraDataSection() const {		const MCSection *getTLSExtraDataSection() const {
	return TLSExtraDataSection;		return TLSExtraDataSection;
	}		}
	const MCSection *getTLSDataSection() const { return TLSDataSection; }		const MCSection *getTLSDataSection() const { return TLSDataSection; }
	const MCSection *getTLSBSSSection() const { return TLSBSSSection; }		const MCSection *getTLSBSSSection() const { return TLSBSSSection; }
			const MCSection *getStackMapSection() const { return StackMapSection; }
	/// ELF specific sections.		/// ELF specific sections.
	///		///
	const MCSection *getDataRelSection() const { return DataRelSection; }		const MCSection *getDataRelSection() const { return DataRelSection; }
	const MCSection *getDataRelLocalSection() const {		const MCSection *getDataRelLocalSection() const {
	return DataRelLocalSection;		return DataRelLocalSection;
	}		}
	const MCSection *getDataRelROSection() const { return DataRelROSection; }		const MCSection *getDataRelROSection() const { return DataRelROSection; }
	const MCSection *getDataRelROLocalSection() const {		const MCSection *getDataRelROLocalSection() const {
	return DataRelROLocalSection;		return DataRelROLocalSection;
	}		}
End of changes. 4 change blocks.
	0 lines changed or deleted		15 lines changed or added

	MCObjectStreamer.h		MCObjectStreamer.h
	skipping to change at line 43		skipping to change at line 43
	class MCObjectStreamer : public MCStreamer {		class MCObjectStreamer : public MCStreamer {
	MCAssembler *Assembler;		MCAssembler *Assembler;
	MCSectionData *CurSectionData;		MCSectionData *CurSectionData;
	MCSectionData::iterator CurInsertionPoint;		MCSectionData::iterator CurInsertionPoint;
	virtual void EmitInstToData(const MCInst &Inst) = 0;		virtual void EmitInstToData(const MCInst &Inst) = 0;
	virtual void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame);		virtual void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame);
	virtual void EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame);		virtual void EmitCFIEndProcImpl(MCDwarfFrameInfo &Frame);
	protected:		protected:
	MCObjectStreamer(StreamerKind Kind, MCContext &Context, MCAsmBackend &TAB		MCObjectStreamer(MCContext &Context, MCTargetStreamer *TargetStreamer,
	,		MCAsmBackend &TAB, raw_ostream &_OS,
	raw_ostream &_OS, MCCodeEmitter *_Emitter);		MCCodeEmitter *_Emitter);
	MCObjectStreamer(StreamerKind Kind, MCContext &Context, MCAsmBackend &TAB		MCObjectStreamer(MCContext &Context, MCTargetStreamer *TargetStreamer,
	,		MCAsmBackend &TAB, raw_ostream &_OS, MCCodeEmitter *_Emi
	raw_ostream &_OS, MCCodeEmitter *_Emitter,		tter,
	MCAssembler *_Assembler);		MCAssembler *_Assembler);
	~MCObjectStreamer();		~MCObjectStreamer();
	public:		public:
	/// state management		/// state management
	virtual void reset();		virtual void reset();
	protected:		protected:
	MCSectionData *getCurrentSectionData() const {		MCSectionData *getCurrentSectionData() const {
	return CurSectionData;		return CurSectionData;
	skipping to change at line 81		skipping to change at line 82
	public:		public:
	MCAssembler &getAssembler() { return *Assembler; }		MCAssembler &getAssembler() { return *Assembler; }
	/// @name MCStreamer Interface		/// @name MCStreamer Interface
	/// @{		/// @{
	virtual void EmitLabel(MCSymbol *Symbol);		virtual void EmitLabel(MCSymbol *Symbol);
	virtual void EmitDebugLabel(MCSymbol *Symbol);		virtual void EmitDebugLabel(MCSymbol *Symbol);
	virtual void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value);		virtual void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value);
	virtual void EmitValueImpl(const MCExpr *Value, unsigned Size,		virtual void EmitValueImpl(const MCExpr *Value, unsigned Size);
	unsigned AddrSpace);
	virtual void EmitULEB128Value(const MCExpr *Value);		virtual void EmitULEB128Value(const MCExpr *Value);
	virtual void EmitSLEB128Value(const MCExpr *Value);		virtual void EmitSLEB128Value(const MCExpr *Value);
	virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol);		virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol);
	virtual void ChangeSection(const MCSection *Section,		virtual void ChangeSection(const MCSection *Section,
	const MCExpr *Subsection);		const MCExpr *Subsection);
	virtual void EmitInstruction(const MCInst &Inst);		virtual void EmitInstruction(const MCInst &Inst);
	/// \brief Emit an instruction to a special fragment, because this instru ction		/// \brief Emit an instruction to a special fragment, because this instru ction
	/// can change its size during relaxation.		/// can change its size during relaxation.
	virtual void EmitInstToFragment(const MCInst &Inst);		virtual void EmitInstToFragment(const MCInst &Inst);
	virtual void EmitBundleAlignMode(unsigned AlignPow2);		virtual void EmitBundleAlignMode(unsigned AlignPow2);
	virtual void EmitBundleLock(bool AlignToEnd);		virtual void EmitBundleLock(bool AlignToEnd);
	virtual void EmitBundleUnlock();		virtual void EmitBundleUnlock();
	virtual void EmitBytes(StringRef Data, unsigned AddrSpace = 0);		virtual void EmitBytes(StringRef Data);
	virtual void EmitValueToAlignment(unsigned ByteAlignment,		virtual void EmitValueToAlignment(unsigned ByteAlignment,
	int64_t Value = 0,		int64_t Value = 0,
	unsigned ValueSize = 1,		unsigned ValueSize = 1,
	unsigned MaxBytesToEmit = 0);		unsigned MaxBytesToEmit = 0);
	virtual void EmitCodeAlignment(unsigned ByteAlignment,		virtual void EmitCodeAlignment(unsigned ByteAlignment,
	unsigned MaxBytesToEmit = 0);		unsigned MaxBytesToEmit = 0);
	virtual bool EmitValueToOffset(const MCExpr *Offset, unsigned char Value) ;		virtual bool EmitValueToOffset(const MCExpr *Offset, unsigned char Value) ;
			virtual void EmitDwarfLocDirective(unsigned FileNo, unsigned Line,
			unsigned Column, unsigned Flags,
			unsigned Isa, unsigned Discriminator,
			StringRef FileName);
	virtual void EmitDwarfAdvanceLineAddr(int64_t LineDelta,		virtual void EmitDwarfAdvanceLineAddr(int64_t LineDelta,
	const MCSymbol *LastLabel,		const MCSymbol *LastLabel,
	const MCSymbol *Label,		const MCSymbol *Label,
	unsigned PointerSize);		unsigned PointerSize);
	virtual void EmitDwarfAdvanceFrameAddr(const MCSymbol *LastLabel,		virtual void EmitDwarfAdvanceFrameAddr(const MCSymbol *LastLabel,
	const MCSymbol *Label);		const MCSymbol *Label);
	virtual void EmitGPRel32Value(const MCExpr *Value);		virtual void EmitGPRel32Value(const MCExpr *Value);
	virtual void EmitGPRel64Value(const MCExpr *Value);		virtual void EmitGPRel64Value(const MCExpr *Value);
	virtual void EmitFill(uint64_t NumBytes, uint8_t FillValue,		virtual void EmitFill(uint64_t NumBytes, uint8_t FillValue);
	unsigned AddrSpace = 0);		virtual void EmitZeros(uint64_t NumBytes);
	virtual void FinishImpl();		virtual void FinishImpl();
	/// @}
	static bool classof(const MCStreamer *S) {
	return S->getKind() >= SK_ELFStreamer && S->getKind() <= SK_WinCOFFStre
	amer;
	}
	};		};
	} // end namespace llvm		} // end namespace llvm
	#endif		#endif
End of changes. 6 change blocks.
	18 lines changed or deleted		14 lines changed or added

	MCRegisterInfo.h		MCRegisterInfo.h
	skipping to change at line 102		skipping to change at line 102
	/// getCopyCost - Return the cost of copying a value between two register s in		/// getCopyCost - Return the cost of copying a value between two register s in
	/// this class. A negative number means the register class is very expens ive		/// this class. A negative number means the register class is very expens ive
	/// to copy e.g. status flag register classes.		/// to copy e.g. status flag register classes.
	int getCopyCost() const { return CopyCost; }		int getCopyCost() const { return CopyCost; }
	/// isAllocatable - Return true if this register class may be used to cre ate		/// isAllocatable - Return true if this register class may be used to cre ate
	/// virtual registers.		/// virtual registers.
	bool isAllocatable() const { return Allocatable; }		bool isAllocatable() const { return Allocatable; }
	};		};
	/// MCRegisterDesc - This record contains all of the information known abou		/// MCRegisterDesc - This record contains information about a particular
	t		/// register. The SubRegs field is a zero terminated array of registers th
	/// a particular register. The Overlaps field contains a pointer to a zero		at
	/// terminated array of registers that this register aliases, starting with		/// are sub-registers of the specific register, e.g. AL, AH are sub-registe
	/// itself. This is needed for architectures like X86 which have AL alias A		rs
	X		/// of AX. The SuperRegs field is a zero terminated array of registers that
	/// alias EAX. The SubRegs field is a zero terminated array of registers th		are
	at		/// super-registers of the specific register, e.g. RAX, EAX, are
	/// are sub-registers of the specific register, e.g. AL, AH are sub-registe		/// super-registers of AX.
	rs of
	/// AX. The SuperRegs field is a zero terminated array of registers that ar
	e
	/// super-registers of the specific register, e.g. RAX, EAX, are super-regi
	sters
	/// of AX.
	///		///
	struct MCRegisterDesc {		struct MCRegisterDesc {
	uint32_t Name; // Printable name for the reg (for debugging)		uint32_t Name; // Printable name for the reg (for debugging)
	uint32_t Overlaps; // Overlapping registers, described above
	uint32_t SubRegs; // Sub-register set, described above		uint32_t SubRegs; // Sub-register set, described above
	uint32_t SuperRegs; // Super-register set, described above		uint32_t SuperRegs; // Super-register set, described above
	// Offset into MCRI::SubRegIndices of a list of sub-register indices for each		// Offset into MCRI::SubRegIndices of a list of sub-register indices for each
	// sub-register in SubRegs.		// sub-register in SubRegs.
	uint32_t SubRegIndices;		uint32_t SubRegIndices;
	// RegUnits - Points to the list of register units. The low 4 bits holds the		// RegUnits - Points to the list of register units. The low 4 bits holds the
	// Scale, the high bits hold an offset into DiffLists. See MCRegUnitItera tor.		// Scale, the high bits hold an offset into DiffLists. See MCRegUnitItera tor.
	uint32_t RegUnits;		uint32_t RegUnits;
	skipping to change at line 151		skipping to change at line 147
	typedef const MCRegisterClass *regclass_iterator;		typedef const MCRegisterClass *regclass_iterator;
	/// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings c an be		/// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings c an be
	/// performed with a binary search.		/// performed with a binary search.
	struct DwarfLLVMRegPair {		struct DwarfLLVMRegPair {
	unsigned FromReg;		unsigned FromReg;
	unsigned ToReg;		unsigned ToReg;
	bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromR eg; }		bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromR eg; }
	};		};
			/// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subre
			g
			/// index, -1 in any being invalid.
			struct SubRegCoveredBits {
			uint16_t Offset;
			uint16_t Size;
			};
	private:		private:
	const MCRegisterDesc *Desc; // Pointer to the descriptor array		const MCRegisterDesc *Desc; // Pointer to the descriptor array
	unsigned NumRegs; // Number of entries in the a rray		unsigned NumRegs; // Number of entries in the a rray
	unsigned RAReg; // Return address register		unsigned RAReg; // Return address register
	unsigned PCReg; // Program counter register		unsigned PCReg; // Program counter register
	const MCRegisterClass *Classes; // Pointer to the regclass ar ray		const MCRegisterClass *Classes; // Pointer to the regclass ar ray
	unsigned NumClasses; // Number of entries in the a rray		unsigned NumClasses; // Number of entries in the a rray
	unsigned NumRegUnits; // Number of regunits.		unsigned NumRegUnits; // Number of regunits.
	const uint16_t (*RegUnitRoots)[2]; // Pointer to regunit root ta ble.		const uint16_t (*RegUnitRoots)[2]; // Pointer to regunit root ta ble.
	const MCPhysReg *DiffLists; // Pointer to the difflists a rray		const MCPhysReg *DiffLists; // Pointer to the difflists a rray
	const char *RegStrings; // Pointer to the string tabl e.		const char *RegStrings; // Pointer to the string tabl e.
	const uint16_t *SubRegIndices; // Pointer to the subreg look up		const uint16_t *SubRegIndices; // Pointer to the subreg look up
	// array.		// array.
			const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg cove
			red
			// bit ranges array.
	unsigned NumSubRegIndices; // Number of subreg indices.		unsigned NumSubRegIndices; // Number of subreg indices.
	const uint16_t *RegEncodingTable; // Pointer to array of regist er		const uint16_t *RegEncodingTable; // Pointer to array of regist er
	// encodings.		// encodings.
	unsigned L2DwarfRegsSize;		unsigned L2DwarfRegsSize;
	unsigned EHL2DwarfRegsSize;		unsigned EHL2DwarfRegsSize;
	unsigned Dwarf2LRegsSize;		unsigned Dwarf2LRegsSize;
	unsigned EHDwarf2LRegsSize;		unsigned EHDwarf2LRegsSize;
	const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping		const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping
	const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH		const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
	skipping to change at line 229		skipping to change at line 234
	// The end of the list is encoded as a 0 differential.		// The end of the list is encoded as a 0 differential.
	if (!advance())		if (!advance())
	List = 0;		List = 0;
	}		}
	};		};
	// These iterators are allowed to sub-class DiffListIterator and access		// These iterators are allowed to sub-class DiffListIterator and access
	// internal list pointers.		// internal list pointers.
	friend class MCSubRegIterator;		friend class MCSubRegIterator;
	friend class MCSuperRegIterator;		friend class MCSuperRegIterator;
	friend class MCRegAliasIterator;
	friend class MCRegUnitIterator;		friend class MCRegUnitIterator;
	friend class MCRegUnitRootIterator;		friend class MCRegUnitRootIterator;
	/// \brief Initialize MCRegisterInfo, called by TableGen		/// \brief Initialize MCRegisterInfo, called by TableGen
	/// auto-generated routines. *DO NOT USE*.		/// auto-generated routines. *DO NOT USE*.
	void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA ,		void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA ,
	unsigned PC,		unsigned PC,
	const MCRegisterClass *C, unsigned NC,		const MCRegisterClass *C, unsigned NC,
	const uint16_t (*RURoots)[2],		const uint16_t (*RURoots)[2],
	unsigned NRU,		unsigned NRU,
	const MCPhysReg *DL,		const MCPhysReg *DL,
	const char *Strings,		const char *Strings,
	const uint16_t *SubIndices,		const uint16_t *SubIndices,
	unsigned NumIndices,		unsigned NumIndices,
			const SubRegCoveredBits *SubIdxRanges,
	const uint16_t *RET) {		const uint16_t *RET) {
	Desc = D;		Desc = D;
	NumRegs = NR;		NumRegs = NR;
	RAReg = RA;		RAReg = RA;
	PCReg = PC;		PCReg = PC;
	Classes = C;		Classes = C;
	DiffLists = DL;		DiffLists = DL;
	RegStrings = Strings;		RegStrings = Strings;
	NumClasses = NC;		NumClasses = NC;
	RegUnitRoots = RURoots;		RegUnitRoots = RURoots;
	NumRegUnits = NRU;		NumRegUnits = NRU;
	SubRegIndices = SubIndices;		SubRegIndices = SubIndices;
	NumSubRegIndices = NumIndices;		NumSubRegIndices = NumIndices;
			SubRegIdxRanges = SubIdxRanges;
	RegEncodingTable = RET;		RegEncodingTable = RET;
	}		}
	/// \brief Used to initialize LLVM register to Dwarf		/// \brief Used to initialize LLVM register to Dwarf
	/// register number mapping. Called by TableGen auto-generated routines.		/// register number mapping. Called by TableGen auto-generated routines.
	/// *DO NOT USE*.		/// *DO NOT USE*.
	void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,		void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
	bool isEH) {		bool isEH) {
	if (isEH) {		if (isEH) {
	EHL2DwarfRegs = Map;		EHL2DwarfRegs = Map;
	skipping to change at line 335		skipping to change at line 341
	/// \brief Return a super-register of the specified register		/// \brief Return a super-register of the specified register
	/// Reg so its sub-register of index SubIdx is Reg.		/// Reg so its sub-register of index SubIdx is Reg.
	unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,		unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
	const MCRegisterClass *RC) const;		const MCRegisterClass *RC) const;
	/// \brief For a given register pair, return the sub-register index		/// \brief For a given register pair, return the sub-register index
	/// if the second register is a sub-register of the first. Return zero		/// if the second register is a sub-register of the first. Return zero
	/// otherwise.		/// otherwise.
	unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;		unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
			/// \brief Get the size of the bit range covered by a sub-register index.
			/// If the index isn't continuous, return the sum of the sizes of its par
			ts.
			/// If the index is used to access subregisters of different sizes, retur
			n -1.
			unsigned getSubRegIdxSize(unsigned Idx) const;
			/// \brief Get the offset of the bit range covered by a sub-register inde
			x.
			/// If an Offset doesn't make sense (the index isn't continuous, or is us
			ed to
			/// access sub-registers at different offsets), return -1.
			unsigned getSubRegIdxOffset(unsigned Idx) const;
	/// \brief Return the human-readable symbolic target-specific name for th e		/// \brief Return the human-readable symbolic target-specific name for th e
	/// specified physical register.		/// specified physical register.
	const char *getName(unsigned RegNo) const {		const char *getName(unsigned RegNo) const {
	return RegStrings + get(RegNo).Name;		return RegStrings + get(RegNo).Name;
	}		}
	/// \brief Return the number of registers this target has (useful for		/// \brief Return the number of registers this target has (useful for
	/// sizing arrays holding per register information)		/// sizing arrays holding per register information)
	unsigned getNumRegs() const {		unsigned getNumRegs() const {
	return NumRegs;		return NumRegs;
	skipping to change at line 424		skipping to change at line 440
	};		};
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// Register List Iterators		// Register List Iterators
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// MCRegisterInfo provides lists of super-registers, sub-registers, and		// MCRegisterInfo provides lists of super-registers, sub-registers, and
	// aliasing registers. Use these iterator classes to traverse the lists.		// aliasing registers. Use these iterator classes to traverse the lists.
	/// MCSubRegIterator enumerates all sub-registers of Reg.		/// MCSubRegIterator enumerates all sub-registers of Reg.
			/// If IncludeSelf is set, Reg itself is included in the list.
	class MCSubRegIterator : public MCRegisterInfo::DiffListIterator {		class MCSubRegIterator : public MCRegisterInfo::DiffListIterator {
	public:		public:
	MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI) {		MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
			bool IncludeSelf = false) {
	init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);		init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
	++*this;		// Initially, the iterator points to Reg itself.
			if (!IncludeSelf)
			++*this;
	}		}
	};		};
	/// MCSuperRegIterator enumerates all super-registers of Reg.		/// MCSuperRegIterator enumerates all super-registers of Reg.
			/// If IncludeSelf is set, Reg itself is included in the list.
	class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator {		class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator {
	public:		public:
	MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI) {		MCSuperRegIterator() {}
			MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
			bool IncludeSelf = false) {
	init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);		init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
	++*this;
	}
	};
	/// MCRegAliasIterator enumerates all registers aliasing Reg.
	/// If IncludeSelf is set, Reg itself is included in the list.
	class MCRegAliasIterator : public MCRegisterInfo::DiffListIterator {
	public:
	MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI,
	bool IncludeSelf) {
	init(Reg, MCRI->DiffLists + MCRI->get(Reg).Overlaps);
	// Initially, the iterator points to Reg itself.		// Initially, the iterator points to Reg itself.
	if (!IncludeSelf)		if (!IncludeSelf)
	++*this;		++*this;
	}		}
	};		};
	// Definition for isSuperRegister. Put it down here since it needs the		// Definition for isSuperRegister. Put it down here since it needs the
	// iterator defined above in addition to the MCRegisterInfo class itself.		// iterator defined above in addition to the MCRegisterInfo class itself.
	inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) c onst{		inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) c onst{
	for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I)		for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I)
	skipping to change at line 481		skipping to change at line 493
	// A target with a complicated sub-register structure will typically have m any		// A target with a complicated sub-register structure will typically have m any
	// fewer register units than actual registers. MCRI::getNumRegUnits() retur ns		// fewer register units than actual registers. MCRI::getNumRegUnits() retur ns
	// the number of register units in the target.		// the number of register units in the target.
	// MCRegUnitIterator enumerates a list of register units for Reg. The list is		// MCRegUnitIterator enumerates a list of register units for Reg. The list is
	// in ascending numerical order.		// in ascending numerical order.
	class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {		class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {
	public:		public:
	/// MCRegUnitIterator - Create an iterator that traverses the register un its		/// MCRegUnitIterator - Create an iterator that traverses the register un its
	/// in Reg.		/// in Reg.
			MCRegUnitIterator() {}
	MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) {		MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
	assert(Reg && "Null register has no regunits");		assert(Reg && "Null register has no regunits");
	// Decode the RegUnits MCRegisterDesc field.		// Decode the RegUnits MCRegisterDesc field.
	unsigned RU = MCRI->get(Reg).RegUnits;		unsigned RU = MCRI->get(Reg).RegUnits;
	unsigned Scale = RU & 15;		unsigned Scale = RU & 15;
	unsigned Offset = RU >> 4;		unsigned Offset = RU >> 4;
	// Initialize the iterator to Reg * Scale, and the List pointer to		// Initialize the iterator to Reg * Scale, and the List pointer to
	// DiffLists + Offset.		// DiffLists + Offset.
	init(Reg * Scale, MCRI->DiffLists + Offset);		init(Reg * Scale, MCRI->DiffLists + Offset);
	skipping to change at line 505		skipping to change at line 518
	// unit, we can allow a 0 differential here.		// unit, we can allow a 0 differential here.
	advance();		advance();
	}		}
	};		};
	// Each register unit has one or two root registers. The complete set of		// Each register unit has one or two root registers. The complete set of
	// registers containing a register unit is the union of the roots and their		// registers containing a register unit is the union of the roots and their
	// super-registers. All registers aliasing Unit can be visited like this:		// super-registers. All registers aliasing Unit can be visited like this:
	//		//
	// for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {		// for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
	// unsigned Root = *RI;		// for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI)
	// visit(Root);
	// for (MCSuperRegIterator SI(Root, MCRI); SI.isValid(); ++SI)
	// visit(*SI);		// visit(*SI);
	// }		// }
	/// MCRegUnitRootIterator enumerates the root registers of a register unit.		/// MCRegUnitRootIterator enumerates the root registers of a register unit.
	class MCRegUnitRootIterator {		class MCRegUnitRootIterator {
	uint16_t Reg0;		uint16_t Reg0;
	uint16_t Reg1;		uint16_t Reg1;
	public:		public:
			MCRegUnitRootIterator() : Reg0(0), Reg1(0) {}
	MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {		MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
	assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");		assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
	Reg0 = MCRI->RegUnitRoots[RegUnit][0];		Reg0 = MCRI->RegUnitRoots[RegUnit][0];
	Reg1 = MCRI->RegUnitRoots[RegUnit][1];		Reg1 = MCRI->RegUnitRoots[RegUnit][1];
	}		}
	/// \brief Dereference to get the current root register.		/// \brief Dereference to get the current root register.
	unsigned operator*() const {		unsigned operator*() const {
	return Reg0;		return Reg0;
	}		}
	skipping to change at line 540		skipping to change at line 552
	}		}
	/// \brief Preincrement to move to the next root register.		/// \brief Preincrement to move to the next root register.
	void operator++() {		void operator++() {
	assert(isValid() && "Cannot move off the end of the list.");		assert(isValid() && "Cannot move off the end of the list.");
	Reg0 = Reg1;		Reg0 = Reg1;
	Reg1 = 0;		Reg1 = 0;
	}		}
	};		};
			/// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSe
			lf is
			/// set, Reg itself is included in the list. This iterator does not guaran
			tee
			/// any ordering or that entries are unique.
			class MCRegAliasIterator {
			private:
			unsigned Reg;
			const MCRegisterInfo *MCRI;
			bool IncludeSelf;
			MCRegUnitIterator RI;
			MCRegUnitRootIterator RRI;
			MCSuperRegIterator SI;
			public:
			MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI,
			bool IncludeSelf)
			: Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) {
			// Initialize the iterators.
			for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) {
			for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) {
			for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI)
			{
			if (!(!IncludeSelf && Reg == *SI))
			return;
			}
			}
			}
			}
			bool isValid() const {
			return RI.isValid();
			}
			unsigned operator*() const {
			assert (SI.isValid() && "Cannot dereference an invalid iterator.");
			return *SI;
			}
			void advance() {
			// Assuming SI is valid.
			++SI;
			if (SI.isValid()) return;
			++RRI;
			if (RRI.isValid()) {
			SI = MCSuperRegIterator(*RRI, MCRI, true);
			return;
			}
			++RI;
			if (RI.isValid()) {
			RRI = MCRegUnitRootIterator(*RI, MCRI);
			SI = MCSuperRegIterator(*RRI, MCRI, true);
			}
			}
			void operator++() {
			assert(isValid() && "Cannot move off the end of the list.");
			do advance();
			while (!IncludeSelf && isValid() && *SI == Reg);
			}
			};
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 18 change blocks.
	34 lines changed or deleted		114 lines changed or added

	MCSchedule.h		MCSchedule.h
	skipping to change at line 33		skipping to change at line 33
	struct InstrItinerary;		struct InstrItinerary;
	/// Define a kind of processor resource that will be modeled by the schedul er.		/// Define a kind of processor resource that will be modeled by the schedul er.
	struct MCProcResourceDesc {		struct MCProcResourceDesc {
	#ifndef NDEBUG		#ifndef NDEBUG
	const char *Name;		const char *Name;
	#endif		#endif
	unsigned NumUnits; // Number of resource of this kind		unsigned NumUnits; // Number of resource of this kind
	unsigned SuperIdx; // Index of the resources kind that contains this kind .		unsigned SuperIdx; // Index of the resources kind that contains this kind .
	// Buffered resources may be consumed at some indeterminate cycle after		// Number of resources that may be buffered.
	// dispatch (e.g. for instructions that may issue out-of-order). Unbuffer		//
	ed		// Buffered resources (BufferSize > 0 || BufferSize == -1) may be consume
	// resources always consume their resource some fixed number of cycles af		d at
	ter		// some indeterminate cycle after dispatch (e.g. for instructions that ma
	// dispatch (e.g. for instruction interlocking that may stall the pipelin		y
	e).		// issue out-of-order). Unbuffered resources (BufferSize == 0) always con
	bool IsBuffered;		sume
			// their resource some fixed number of cycles after dispatch (e.g. for
			// instruction interlocking that may stall the pipeline).
			int BufferSize;
	bool operator==(const MCProcResourceDesc &Other) const {		bool operator==(const MCProcResourceDesc &Other) const {
	return NumUnits == Other.NumUnits && SuperIdx == Other.SuperIdx		return NumUnits == Other.NumUnits && SuperIdx == Other.SuperIdx
	&& IsBuffered == Other.IsBuffered;		&& BufferSize == Other.BufferSize;
	}		}
	};		};
	/// Identify one of the processor resource kinds consumed by a particular		/// Identify one of the processor resource kinds consumed by a particular
	/// scheduling class for the specified number of cycles.		/// scheduling class for the specified number of cycles.
	struct MCWriteProcResEntry {		struct MCWriteProcResEntry {
	unsigned ProcResourceIdx;		unsigned ProcResourceIdx;
	unsigned Cycles;		unsigned Cycles;
	bool operator==(const MCWriteProcResEntry &Other) const {		bool operator==(const MCWriteProcResEntry &Other) const {
	skipping to change at line 124		skipping to change at line 127
	return NumMicroOps == VariantNumMicroOps;		return NumMicroOps == VariantNumMicroOps;
	}		}
	};		};
	/// Machine model for scheduling, bundling, and heuristics.		/// Machine model for scheduling, bundling, and heuristics.
	///		///
	/// The machine model directly provides basic information about the		/// The machine model directly provides basic information about the
	/// microarchitecture to the scheduler in the form of properties. It also		/// microarchitecture to the scheduler in the form of properties. It also
	/// optionally refers to scheduler resource tables and itinerary		/// optionally refers to scheduler resource tables and itinerary
	/// tables. Scheduler resource tables model the latency and cost for each		/// tables. Scheduler resource tables model the latency and cost for each
	/// instruction type. Itinerary tables are an independant mechanism that		/// instruction type. Itinerary tables are an independent mechanism that
	/// provides a detailed reservation table describing each cycle of instruct ion		/// provides a detailed reservation table describing each cycle of instruct ion
	/// execution. Subtargets may define any or all of the above categories of data		/// execution. Subtargets may define any or all of the above categories of data
	/// depending on the type of CPU and selected scheduler.		/// depending on the type of CPU and selected scheduler.
	class MCSchedModel {		class MCSchedModel {
	public:		public:
	static MCSchedModel DefaultSchedModel; // For unknown processors.		static MCSchedModel DefaultSchedModel; // For unknown processors.
	// IssueWidth is the maximum number of instructions that may be scheduled in		// IssueWidth is the maximum number of instructions that may be scheduled in
	// the same per-cycle group.		// the same per-cycle group.
	unsigned IssueWidth;		unsigned IssueWidth;
	static const unsigned DefaultIssueWidth = 1;		static const unsigned DefaultIssueWidth = 1;
	// MinLatency is the minimum latency between a register write		// MicroOpBufferSize is the number of micro-ops that the processor may bu
	// followed by a data dependent read. This determines which		ffer
	// instructions may be scheduled in the same per-cycle group. This		// for out-of-order execution.
	// is distinct from *expected* latency, which determines the likely
	// critical path but does not guarantee a pipeline
	// hazard. MinLatency can always be overridden by the number of
	// InstrStage cycles.
	//		//
	// (-1) Standard in-order processor.		// "0" means operations that are not ready in this cycle are not consider
	// Use InstrItinerary OperandCycles as MinLatency.		ed
	// If no OperandCycles exist, then use the cycle of the last InstrSt		// for scheduling (they go in the pending queue). Latency is paramount. T
	age.		his
			// may be more efficient if many instructions are pending in a schedule.
	//		//
	// (0) Out-of-order processor, or in-order with bundled dependencies.		// "1" means all instructions are considered for scheduling regardless of
	// RAW dependencies may be dispatched in the same cycle.		// whether they are ready in this cycle. Latency still causes issue stall
	// Optional InstrItinerary OperandCycles provides expected latency.		s,
			// but we balance those stalls against other heuristics.
	//		//
	// (>0) In-order processor with variable latencies.		// "> 1" means the processor is out-of-order. This is a machine independe
	// Use the greater of this value or the cycle of the last InstrStage		nt
	.		// estimate of highly machine specific characteristics such are the regis
	// Optional InstrItinerary OperandCycles provides expected latency.		ter
	// TODO: can't yet specify both min and expected latency per operand		// renaming pool and reorder buffer.
	.		unsigned MicroOpBufferSize;
	int MinLatency;		static const unsigned DefaultMicroOpBufferSize = 0;
	static const int DefaultMinLatency = -1;
	// LoadLatency is the expected latency of load instructions.		// LoadLatency is the expected latency of load instructions.
	//		//
	// If MinLatency >= 0, this may be overriden for individual load opcodes by		// If MinLatency >= 0, this may be overriden for individual load opcodes by
	// InstrItinerary OperandCycles.		// InstrItinerary OperandCycles.
	unsigned LoadLatency;		unsigned LoadLatency;
	static const unsigned DefaultLoadLatency = 4;		static const unsigned DefaultLoadLatency = 4;
	// HighLatency is the expected latency of "very high latency" operations.		// HighLatency is the expected latency of "very high latency" operations.
	// See TargetInstrInfo::isHighLatencyDef().		// See TargetInstrInfo::isHighLatencyDef().
	// By default, this is set to an arbitrarily high number of cycles		// By default, this is set to an arbitrarily high number of cycles
	// likely to have some impact on scheduling heuristics.		// likely to have some impact on scheduling heuristics.
	// If MinLatency >= 0, this may be overriden by InstrItinData OperandCycl es.		// If MinLatency >= 0, this may be overriden by InstrItinData OperandCycl es.
	unsigned HighLatency;		unsigned HighLatency;
	static const unsigned DefaultHighLatency = 10;		static const unsigned DefaultHighLatency = 10;
	// ILPWindow is the number of cycles that the scheduler effectively ignor
	es
	// before attempting to hide latency. This should be zero for in-order cp
	us to
	// always hide expected latency. For out-of-order cpus, it may be tweaked
	as
	// desired to roughly approximate instruction buffers. The actual thresho
	ld is
	// not very important for an OOO processor, as long as it isn't too high.
	A
	// nonzero value helps avoid rescheduling to hide latency when its is fai
	rly
	// obviously useless and makes register pressure heuristics more effectiv
	e.
	unsigned ILPWindow;
	static const unsigned DefaultILPWindow = 0;
	// MispredictPenalty is the typical number of extra cycles the processor		// MispredictPenalty is the typical number of extra cycles the processor
	// takes to recover from a branch misprediction.		// takes to recover from a branch misprediction.
	unsigned MispredictPenalty;		unsigned MispredictPenalty;
	static const unsigned DefaultMispredictPenalty = 10;		static const unsigned DefaultMispredictPenalty = 10;
			bool CompleteModel;
	private:		private:
	unsigned ProcID;		unsigned ProcID;
	const MCProcResourceDesc *ProcResourceTable;		const MCProcResourceDesc *ProcResourceTable;
	const MCSchedClassDesc *SchedClassTable;		const MCSchedClassDesc *SchedClassTable;
	unsigned NumProcResourceKinds;		unsigned NumProcResourceKinds;
	unsigned NumSchedClasses;		unsigned NumSchedClasses;
	// Instruction itinerary tables used by InstrItineraryData.		// Instruction itinerary tables used by InstrItineraryData.
	friend class InstrItineraryData;		friend class InstrItineraryData;
	const InstrItinerary *InstrItineraries;		const InstrItinerary *InstrItineraries;
	public:		public:
	// Default's must be specified as static const literals so that tablegene rated		// Default's must be specified as static const literals so that tablegene rated
	// target code can use it in static initializers. The defaults need to be		// target code can use it in static initializers. The defaults need to be
	// initialized in this default ctor because some clients directly instant iate		// initialized in this default ctor because some clients directly instant iate
	// MCSchedModel instead of using a generated itinerary.		// MCSchedModel instead of using a generated itinerary.
	MCSchedModel(): IssueWidth(DefaultIssueWidth),		MCSchedModel(): IssueWidth(DefaultIssueWidth),
	MinLatency(DefaultMinLatency),		MicroOpBufferSize(DefaultMicroOpBufferSize),
	LoadLatency(DefaultLoadLatency),		LoadLatency(DefaultLoadLatency),
	HighLatency(DefaultHighLatency),		HighLatency(DefaultHighLatency),
	ILPWindow(DefaultILPWindow),
	MispredictPenalty(DefaultMispredictPenalty),		MispredictPenalty(DefaultMispredictPenalty),
			CompleteModel(true),
	ProcID(0), ProcResourceTable(0), SchedClassTable(0),		ProcID(0), ProcResourceTable(0), SchedClassTable(0),
	NumProcResourceKinds(0), NumSchedClasses(0),		NumProcResourceKinds(0), NumSchedClasses(0),
	InstrItineraries(0) {		InstrItineraries(0) {
	(void)NumProcResourceKinds;		(void)NumProcResourceKinds;
	(void)NumSchedClasses;		(void)NumSchedClasses;
	}		}
	// Table-gen driven ctor.		// Table-gen driven ctor.
	MCSchedModel(unsigned iw, int ml, unsigned ll, unsigned hl, unsigned ilp,		MCSchedModel(unsigned iw, int mbs, unsigned ll, unsigned hl,
	unsigned mp, unsigned pi, const MCProcResourceDesc *pr,		unsigned mp, bool cm, unsigned pi, const MCProcResourceDesc
			*pr,
	const MCSchedClassDesc *sc, unsigned npr, unsigned nsc,		const MCSchedClassDesc *sc, unsigned npr, unsigned nsc,
	const InstrItinerary *ii):		const InstrItinerary *ii):
	IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl),		IssueWidth(iw), MicroOpBufferSize(mbs), LoadLatency(ll), HighLatency(hl
	ILPWindow(ilp), MispredictPenalty(mp), ProcID(pi), ProcResourceTable(pr		),
	),		MispredictPenalty(mp), CompleteModel(cm), ProcID(pi),
	SchedClassTable(sc), NumProcResourceKinds(npr), NumSchedClasses(nsc),		ProcResourceTable(pr), SchedClassTable(sc), NumProcResourceKinds(npr),
	InstrItineraries(ii) {}		NumSchedClasses(nsc), InstrItineraries(ii) {}
	unsigned getProcessorID() const { return ProcID; }		unsigned getProcessorID() const { return ProcID; }
	/// Does this machine model include instruction-level scheduling.		/// Does this machine model include instruction-level scheduling.
	bool hasInstrSchedModel() const { return SchedClassTable; }		bool hasInstrSchedModel() const { return SchedClassTable; }
			/// Return true if this machine model data for all instructions with a
			/// scheduling class (itinerary class or SchedRW list).
			bool isComplete() const { return CompleteModel; }
	unsigned getNumProcResourceKinds() const {		unsigned getNumProcResourceKinds() const {
	return NumProcResourceKinds;		return NumProcResourceKinds;
	}		}
	const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const {		const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const {
	assert(hasInstrSchedModel() && "No scheduling machine model");		assert(hasInstrSchedModel() && "No scheduling machine model");
	assert(ProcResourceIdx < NumProcResourceKinds && "bad proc resource idx ");		assert(ProcResourceIdx < NumProcResourceKinds && "bad proc resource idx ");
	return &ProcResourceTable[ProcResourceIdx];		return &ProcResourceTable[ProcResourceIdx];
	}		}
End of changes. 15 change blocks.
	58 lines changed or deleted		48 lines changed or added

	MCSectionCOFF.h		MCSectionCOFF.h
	skipping to change at line 22		skipping to change at line 22
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_MC_MCSECTIONCOFF_H		#ifndef LLVM_MC_MCSECTIONCOFF_H
	#define LLVM_MC_MCSECTIONCOFF_H		#define LLVM_MC_MCSECTIONCOFF_H
	#include "llvm/ADT/StringRef.h"		#include "llvm/ADT/StringRef.h"
	#include "llvm/MC/MCSection.h"		#include "llvm/MC/MCSection.h"
	#include "llvm/Support/COFF.h"		#include "llvm/Support/COFF.h"
	namespace llvm {		namespace llvm {
			class MCSymbol;
	/// MCSectionCOFF - This represents a section on Windows		/// MCSectionCOFF - This represents a section on Windows
	class MCSectionCOFF : public MCSection {		class MCSectionCOFF : public MCSection {
	// The memory for this string is stored in the same MCContext as *this.		// The memory for this string is stored in the same MCContext as *this.
	StringRef SectionName;		StringRef SectionName;
			// FIXME: The following fields should not be mutable, but are for now s
			o
			// the asm parser can honor the .linkonce directive.
	/// Characteristics - This is the Characteristics field of a section,		/// Characteristics - This is the Characteristics field of a section,
	// drawn from the enums below.		/// drawn from the enums below.
	unsigned Characteristics;		mutable unsigned Characteristics;
			/// The COMDAT symbol of this section. Only valid if this is a COMDAT
			/// section. Two COMDAT sections are merged if they have the same
			/// COMDAT symbol.
			const MCSymbol *COMDATSymbol;
	/// Selection - This is the Selection field for the section symbol, if		/// Selection - This is the Selection field for the section symbol, if
	/// it is a COMDAT section (Characteristics & IMAGE_SCN_LNK_COMDAT) != 0		/// it is a COMDAT section (Characteristics & IMAGE_SCN_LNK_COMDAT) != 0
	int Selection;		mutable int Selection;
			/// Assoc - This is name of the associated section, if it is a COMDAT
			/// section (Characteristics & IMAGE_SCN_LNK_COMDAT) != 0 with an
			/// associative Selection (IMAGE_COMDAT_SELECT_ASSOCIATIVE).
			mutable const MCSectionCOFF *Assoc;
	private:		private:
	friend class MCContext;		friend class MCContext;
	MCSectionCOFF(StringRef Section, unsigned Characteristics,		MCSectionCOFF(StringRef Section, unsigned Characteristics,
	int Selection, SectionKind K)		const MCSymbol *COMDATSymbol, int Selection,
	: MCSection(SV_COFF, K), SectionName(Section),		const MCSectionCOFF *Assoc, SectionKind K)
	Characteristics(Characteristics), Selection (Selection) {		: MCSection(SV_COFF, K), SectionName(Section),
			Characteristics(Characteristics), COMDATSymbol(COMDATSymbol),
			Selection(Selection), Assoc(Assoc) {
	assert ((Characteristics & 0x00F00000) == 0 &&		assert ((Characteristics & 0x00F00000) == 0 &&
	"alignment must not be set upon section creation");		"alignment must not be set upon section creation");
			assert ((Selection == COFF::IMAGE_COMDAT_SELECT_ASSOCIATIVE) ==
			(Assoc != 0) &&
			"associative COMDAT section must have an associated section");
	}		}
	~MCSectionCOFF();		~MCSectionCOFF();
	public:		public:
	/// ShouldOmitSectionDirective - Decides whether a '.section' directive		/// ShouldOmitSectionDirective - Decides whether a '.section' directive
	/// should be printed before the section name		/// should be printed before the section name
	bool ShouldOmitSectionDirective(StringRef Name, const MCAsmInfo &MAI) c onst;		bool ShouldOmitSectionDirective(StringRef Name, const MCAsmInfo &MAI) c onst;
	StringRef getSectionName() const { return SectionName; }		StringRef getSectionName() const { return SectionName; }
	virtual std::string getLabelBeginName() const {		virtual std::string getLabelBeginName() const {
	return SectionName.str() + "_begin";		return SectionName.str() + "_begin";
	}		}
	virtual std::string getLabelEndName() const {		virtual std::string getLabelEndName() const {
	return SectionName.str() + "_end";		return SectionName.str() + "_end";
	}		}
	unsigned getCharacteristics() const { return Characteristics; }		unsigned getCharacteristics() const { return Characteristics; }
	int getSelection () const { return Selection; }		int getSelection() const { return Selection; }
			const MCSectionCOFF *getAssocSection() const { return Assoc; }
			void setSelection(int Selection, const MCSectionCOFF *Assoc = 0) const;
	virtual void PrintSwitchToSection(const MCAsmInfo &MAI,		virtual void PrintSwitchToSection(const MCAsmInfo &MAI,
	raw_ostream &OS,		raw_ostream &OS,
	const MCExpr *Subsection) const;		const MCExpr *Subsection) const;
	virtual bool UseCodeAlign() const;		virtual bool UseCodeAlign() const;
	virtual bool isVirtualSection() const;		virtual bool isVirtualSection() const;
	static bool classof(const MCSection *S) {		static bool classof(const MCSection *S) {
	return S->getVariant() == SV_COFF;		return S->getVariant() == SV_COFF;
	}		}
End of changes. 7 change blocks.
	7 lines changed or deleted		30 lines changed or added

	MCSectionMachO.h		MCSectionMachO.h
	skipping to change at line 44		skipping to change at line 44
	/// size of stubs, for example.		/// size of stubs, for example.
	unsigned Reserved2;		unsigned Reserved2;
	MCSectionMachO(StringRef Segment, StringRef Section,		MCSectionMachO(StringRef Segment, StringRef Section,
	unsigned TAA, unsigned reserved2, SectionKind K);		unsigned TAA, unsigned reserved2, SectionKind K);
	friend class MCContext;		friend class MCContext;
	public:		public:
	/// These are the section type and attributes fields. A MachO section ca n		/// These are the section type and attributes fields. A MachO section ca n
	/// have only one Type, but can have any of the attributes specified.		/// have only one Type, but can have any of the attributes specified.
	enum {		enum LLVM_ENUM_INT_TYPE(uint32_t) {
	// TypeAndAttributes bitmasks.		// TypeAndAttributes bitmasks.
	SECTION_TYPE = 0x000000FFU,		SECTION_TYPE = 0x000000FFU,
	SECTION_ATTRIBUTES = 0xFFFFFF00U,		SECTION_ATTRIBUTES = 0xFFFFFF00U,
	// Valid section types.		// Valid section types.
	/// S_REGULAR - Regular section.		/// S_REGULAR - Regular section.
	S_REGULAR = 0x00U,		S_REGULAR = 0x00U,
	/// S_ZEROFILL - Zero fill on demand section.		/// S_ZEROFILL - Zero fill on demand section.
	S_ZEROFILL = 0x01U,		S_ZEROFILL = 0x01U,
End of changes. 1 change blocks.
	1 lines changed or deleted		1 lines changed or added

	MCStreamer.h		MCStreamer.h
	skipping to change at line 27		skipping to change at line 27
	#include "llvm/ADT/ArrayRef.h"		#include "llvm/ADT/ArrayRef.h"
	#include "llvm/ADT/SmallVector.h"		#include "llvm/ADT/SmallVector.h"
	#include "llvm/MC/MCAssembler.h"		#include "llvm/MC/MCAssembler.h"
	#include "llvm/MC/MCDirectives.h"		#include "llvm/MC/MCDirectives.h"
	#include "llvm/MC/MCDwarf.h"		#include "llvm/MC/MCDwarf.h"
	#include "llvm/MC/MCWin64EH.h"		#include "llvm/MC/MCWin64EH.h"
	#include "llvm/Support/DataTypes.h"		#include "llvm/Support/DataTypes.h"
	#include <string>		#include <string>
	namespace llvm {		namespace llvm {
	class MCAsmBackend;		class MCAsmBackend;
	class MCCodeEmitter;		class MCCodeEmitter;
	class MCContext;		class MCContext;
	class MCExpr;		class MCExpr;
	class MCInst;		class MCInst;
	class MCInstPrinter;		class MCInstPrinter;
	class MCSection;		class MCSection;
	class MCSymbol;		class MCStreamer;
	class StringRef;		class MCSymbol;
	class Twine;		class StringRef;
	class raw_ostream;		class Twine;
	class formatted_raw_ostream;		class raw_ostream;
			class formatted_raw_ostream;
	typedef std::pair<const MCSection *, const MCExpr *> MCSectionSubPair;
			typedef std::pair<const MCSection *, const MCExpr *> MCSectionSubPair;
	/// MCStreamer - Streaming machine code generation interface. This inter
	face		/// Target specific streamer interface. This is used so that targets can
	/// is intended to provide a programatic interface that is very similar t		/// implement support for target specific assembly directives.
	o the		///
	/// level that an assembler .s file provides. It has callbacks to emit b		/// If target foo wants to use this, it should implement 3 classes:
	ytes,		/// * FooTargetStreamer : public MCTargetStreamer
	/// handle directives, etc. The implementation of this interface retains		/// * FooTargetAsmSreamer : public FooTargetStreamer
	/// state to know what the current section is etc.		/// * FooTargetELFStreamer : public FooTargetStreamer
	///		///
	/// There are multiple implementations of this interface: one for writing		/// FooTargetStreamer should have a pure virtual method for each directive.
	out		For
	/// a .s file, and implementations that write out .o files of various for		/// example, for a ".bar symbol_name" directive, it should have
	mats.		/// virtual emitBar(const MCSymbol &Symbol) = 0;
	///		///
	class MCStreamer {		/// The FooTargetAsmSreamer and FooTargetELFStreamer classes implement the
	public:		/// method. The assembly streamer just prints ".bar symbol_name". The objec
	enum StreamerKind {		t
	SK_AsmStreamer,		/// streamer does whatever is needed to implement .bar in the object file.
	SK_NullStreamer,		///
	SK_RecordStreamer,		/// In the assembly printer and parser the target streamer can be used by
			/// calling getTargetStreamer and casting it to FooTargetStreamer:
	// MCObjectStreamer subclasses.		///
	SK_ELFStreamer,		/// MCTargetStreamer &TS = OutStreamer.getTargetStreamer();
	SK_ARMELFStreamer,		/// FooTargetStreamer &ATS = static_cast<FooTargetStreamer &>(TS);
	SK_MachOStreamer,		///
	SK_PureStreamer,		/// The base classes FooTargetAsmSreamer and FooTargetELFStreamer should *n
	SK_MipsELFStreamer,		ever*
	SK_WinCOFFStreamer		/// be treated differently. Callers should always talk to a FooTargetStream
	};		er.
			class MCTargetStreamer {
	private:		protected:
	const StreamerKind Kind;		MCStreamer *Streamer;
	MCContext &Context;
			public:
	MCStreamer(const MCStreamer&) LLVM_DELETED_FUNCTION;		virtual ~MCTargetStreamer();
	MCStreamer &operator=(const MCStreamer&) LLVM_DELETED_FUNCTION;		void setStreamer(MCStreamer *S) { Streamer = S; }
			};
	bool EmitEHFrame;
	bool EmitDebugFrame;		// FIXME: declared here because it is used from
			// lib/CodeGen/AsmPrinter/ARMException.cpp.
	std::vector<MCDwarfFrameInfo> FrameInfos;		class ARMTargetStreamer : public MCTargetStreamer {
	MCDwarfFrameInfo *getCurrentFrameInfo();		virtual void anchor();
	MCSymbol *EmitCFICommon();		public:
	void EnsureValidFrame();		virtual void emitFnStart() = 0;
			virtual void emitFnEnd() = 0;
	std::vector<MCWin64EHUnwindInfo *> W64UnwindInfos;		virtual void emitCantUnwind() = 0;
	MCWin64EHUnwindInfo *CurrentW64UnwindInfo;		virtual void emitPersonality(const MCSymbol *Personality) = 0;
	void setCurrentW64UnwindInfo(MCWin64EHUnwindInfo *Frame);		virtual void emitHandlerData() = 0;
	void EnsureValidW64UnwindInfo();		virtual void emitSetFP(unsigned FpReg, unsigned SpReg,
			int64_t Offset = 0) = 0;
	MCSymbol* LastSymbol;		virtual void emitPad(int64_t Offset) = 0;
			virtual void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
	/// SectionStack - This is stack of current and previous section		bool isVector) = 0;
	/// values saved by PushSection.
	SmallVector<std::pair<MCSectionSubPair, MCSectionSubPair>, 4> SectionSt		virtual void switchVendor(StringRef Vendor) = 0;
	ack;		virtual void emitAttribute(unsigned Attribute, unsigned Value) = 0;
			virtual void emitTextAttribute(unsigned Attribute, StringRef String) = 0;
	bool AutoInitSections;		virtual void emitFPU(unsigned FPU) = 0;
			virtual void finishAttributeSection() = 0;
	protected:		};
	MCStreamer(StreamerKind Kind, MCContext &Ctx);
			/// MCStreamer - Streaming machine code generation interface. This interfa
	const MCExpr *BuildSymbolDiff(MCContext &Context, const MCSymbol *A,		ce
	const MCSymbol *B);		/// is intended to provide a programatic interface that is very similar to
			the
	const MCExpr *ForceExpAbs(const MCExpr* Expr);		/// level that an assembler .s file provides. It has callbacks to emit byt
			es,
	void RecordProcStart(MCDwarfFrameInfo &Frame);		/// handle directives, etc. The implementation of this interface retains
	virtual void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame);		/// state to know what the current section is etc.
	void RecordProcEnd(MCDwarfFrameInfo &Frame);		///
	virtual void EmitCFIEndProcImpl(MCDwarfFrameInfo &CurFrame);		/// There are multiple implementations of this interface: one for writing o
	void EmitFrames(bool usingCFI);		ut
			/// a .s file, and implementations that write out .o files of various forma
	MCWin64EHUnwindInfo *getCurrentW64UnwindInfo(){return CurrentW64UnwindI		ts.
	nfo;}		///
	void EmitW64Tables();		class MCStreamer {
			MCContext &Context;
	public:		OwningPtr<MCTargetStreamer> TargetStreamer;
	virtual ~MCStreamer();
			MCStreamer(const MCStreamer &) LLVM_DELETED_FUNCTION;
	StreamerKind getKind() const { return Kind; }		MCStreamer &operator=(const MCStreamer &) LLVM_DELETED_FUNCTION;
	/// State management		bool EmitEHFrame;
	///		bool EmitDebugFrame;
	virtual void reset();
			std::vector<MCDwarfFrameInfo> FrameInfos;
			MCDwarfFrameInfo *getCurrentFrameInfo();
			MCSymbol *EmitCFICommon();
			void EnsureValidFrame();
			std::vector<MCWin64EHUnwindInfo *> W64UnwindInfos;
			MCWin64EHUnwindInfo *CurrentW64UnwindInfo;
			void setCurrentW64UnwindInfo(MCWin64EHUnwindInfo *Frame);
			void EnsureValidW64UnwindInfo();
			MCSymbol *LastSymbol;
			// SymbolOrdering - Tracks an index to represent the order
			// a symbol was emitted in. Zero means we did not emit that symbol.
			DenseMap<const MCSymbol *, unsigned> SymbolOrdering;
			/// SectionStack - This is stack of current and previous section
			/// values saved by PushSection.
			SmallVector<std::pair<MCSectionSubPair, MCSectionSubPair>, 4> SectionStac
			k;
			bool AutoInitSections;
			protected:
			MCStreamer(MCContext &Ctx, MCTargetStreamer *TargetStreamer);
			const MCExpr *BuildSymbolDiff(MCContext &Context, const MCSymbol *A,
			const MCSymbol *B);
			const MCExpr *ForceExpAbs(const MCExpr *Expr);
			void RecordProcStart(MCDwarfFrameInfo &Frame);
			virtual void EmitCFIStartProcImpl(MCDwarfFrameInfo &Frame);
			void RecordProcEnd(MCDwarfFrameInfo &Frame);
			virtual void EmitCFIEndProcImpl(MCDwarfFrameInfo &CurFrame);
			void EmitFrames(MCAsmBackend *MAB, bool usingCFI);
			MCWin64EHUnwindInfo *getCurrentW64UnwindInfo() {
			return CurrentW64UnwindInfo;
			}
			void EmitW64Tables();
	MCContext &getContext() const { return Context; }		virtual void EmitRawTextImpl(StringRef String);
	unsigned getNumFrameInfos() {		public:
	return FrameInfos.size();		virtual ~MCStreamer();
	}
	const MCDwarfFrameInfo &getFrameInfo(unsigned i) {		/// State management
	return FrameInfos[i];		///
	}		virtual void reset();
	ArrayRef<MCDwarfFrameInfo> getFrameInfos() {		MCContext &getContext() const { return Context; }
	return FrameInfos;
	}
	unsigned getNumW64UnwindInfos() {		MCTargetStreamer &getTargetStreamer() {
	return W64UnwindInfos.size();		assert(TargetStreamer);
	}		return *TargetStreamer;
			}
	MCWin64EHUnwindInfo &getW64UnwindInfo(unsigned i) {		unsigned getNumFrameInfos() { return FrameInfos.size(); }
	return *W64UnwindInfos[i];
	}
	/// @name Assembly File Formatting.		const MCDwarfFrameInfo &getFrameInfo(unsigned i) { return FrameInfos[i];
	/// @{		}
	/// isVerboseAsm - Return true if this streamer supports verbose assemb		ArrayRef<MCDwarfFrameInfo> getFrameInfos() const { return FrameInfos; }
	ly
	/// and if it is enabled.
	virtual bool isVerboseAsm() const { return false; }
	/// hasRawTextSupport - Return true if this asm streamer supports emitt
	ing
	/// unformatted text to the .s file with EmitRawText.
	virtual bool hasRawTextSupport() const { return false; }
	/// AddComment - Add a comment that can be emitted to the generated .s
	/// file if applicable as a QoI issue to make the output of the compile
	r
	/// more readable. This only affects the MCAsmStreamer, and only when
	/// verbose assembly output is enabled.
	///
	/// If the comment includes embedded \n's, they will each get the comme
	nt
	/// prefix as appropriate. The added comment should not end with a \n.
	virtual void AddComment(const Twine &T) {}
	/// GetCommentOS - Return a raw_ostream that comments can be written to
	.
	/// Unlike AddComment, you are required to terminate comments with \n i
	f you
	/// use this method.
	virtual raw_ostream &GetCommentOS();
	/// AddBlankLine - Emit a blank line to a .s file to pretty it up.
	virtual void AddBlankLine() {}
	/// @}
	/// @name Symbol & Section Management
	/// @{
	/// getCurrentSection - Return the current section that the streamer is
	/// emitting code to.
	MCSectionSubPair getCurrentSection() const {
	if (!SectionStack.empty())
	return SectionStack.back().first;
	return MCSectionSubPair();
	}
	/// getPreviousSection - Return the previous section that the streamer		unsigned getNumW64UnwindInfos() { return W64UnwindInfos.size(); }
	is
	/// emitting code to.
	MCSectionSubPair getPreviousSection() const {
	if (!SectionStack.empty())
	return SectionStack.back().second;
	return MCSectionSubPair();
	}
	/// ChangeSection - Update streamer for a new active section.		MCWin64EHUnwindInfo &getW64UnwindInfo(unsigned i) {
	///		return *W64UnwindInfos[i];
	/// This is called by PopSection and SwitchSection, if the current		}
	/// section changes.
	virtual void ChangeSection(const MCSection *, const MCExpr *) = 0;
	/// pushSection - Save the current and previous section on the
	/// section stack.
	void PushSection() {
	SectionStack.push_back(std::make_pair(getCurrentSection(),
	getPreviousSection()));
	}
	/// popSection - Restore the current and previous section from		void generateCompactUnwindEncodings(MCAsmBackend *MAB);
	/// the section stack. Calls ChangeSection as needed.
	///
	/// Returns false if the stack was empty.
	bool PopSection() {
	if (SectionStack.size() <= 1)
	return false;
	MCSectionSubPair oldSection = SectionStack.pop_back_val().first;
	MCSectionSubPair curSection = SectionStack.back().first;
	if (oldSection != curSection)
	ChangeSection(curSection.first, curSection.second);
	return true;
	}
	bool SubSection(const MCExpr *Subsection) {		/// @name Assembly File Formatting.
	if (SectionStack.empty())		/// @{
	return false;
	SwitchSection(SectionStack.back().first.first, Subsection);		/// isVerboseAsm - Return true if this streamer supports verbose assembly
	return true;		/// and if it is enabled.
	}		virtual bool isVerboseAsm() const { return false; }
	/// SwitchSection - Set the current section where code is being emitted		/// hasRawTextSupport - Return true if this asm streamer supports emittin
	to		g
	/// @p Section. This is required to update CurSection.		/// unformatted text to the .s file with EmitRawText.
	///		virtual bool hasRawTextSupport() const { return false; }
	/// This corresponds to assembler directives like .section, .text, etc.
	void SwitchSection(const MCSection *Section, const MCExpr *Subsection =
	0) {
	assert(Section && "Cannot switch to a null section!");
	MCSectionSubPair curSection = SectionStack.back().first;
	SectionStack.back().second = curSection;
	if (MCSectionSubPair(Section, Subsection) != curSection) {
	SectionStack.back().first = MCSectionSubPair(Section, Subsection);
	ChangeSection(Section, Subsection);
	}
	}
	/// SwitchSectionNoChange - Set the current section where code is being		/// AddComment - Add a comment that can be emitted to the generated .s
	/// emitted to @p Section. This is required to update CurSection. This		/// file if applicable as a QoI issue to make the output of the compiler
	/// version does not call ChangeSection.		/// more readable. This only affects the MCAsmStreamer, and only when
	void SwitchSectionNoChange(const MCSection *Section,		/// verbose assembly output is enabled.
	const MCExpr *Subsection = 0) {		///
	assert(Section && "Cannot switch to a null section!");		/// If the comment includes embedded \n's, they will each get the comment
	MCSectionSubPair curSection = SectionStack.back().first;		/// prefix as appropriate. The added comment should not end with a \n.
	SectionStack.back().second = curSection;		virtual void AddComment(const Twine &T) {}
	if (MCSectionSubPair(Section, Subsection) != curSection)
	SectionStack.back().first = MCSectionSubPair(Section, Subsection);		/// GetCommentOS - Return a raw_ostream that comments can be written to.
	}		/// Unlike AddComment, you are required to terminate comments with \n if
			you
			/// use this method.
			virtual raw_ostream &GetCommentOS();
			/// AddBlankLine - Emit a blank line to a .s file to pretty it up.
			virtual void AddBlankLine() {}
			/// @}
			/// @name Symbol & Section Management
			/// @{
			/// getCurrentSection - Return the current section that the streamer is
			/// emitting code to.
			MCSectionSubPair getCurrentSection() const {
			if (!SectionStack.empty())
			return SectionStack.back().first;
			return MCSectionSubPair();
			}
			/// getPreviousSection - Return the previous section that the streamer is
			/// emitting code to.
			MCSectionSubPair getPreviousSection() const {
			if (!SectionStack.empty())
			return SectionStack.back().second;
			return MCSectionSubPair();
			}
			/// GetSymbolOrder - Returns an index to represent the order
			/// a symbol was emitted in. (zero if we did not emit that symbol)
			unsigned GetSymbolOrder(const MCSymbol *Sym) const {
			return SymbolOrdering.lookup(Sym);
			}
	/// Initialize the streamer.		/// ChangeSection - Update streamer for a new active section.
	void InitStreamer() {		///
	if (AutoInitSections)		/// This is called by PopSection and SwitchSection, if the current
	InitSections();		/// section changes.
	}		virtual void ChangeSection(const MCSection *, const MCExpr *) = 0;
			/// pushSection - Save the current and previous section on the
			/// section stack.
			void PushSection() {
			SectionStack.push_back(
			std::make_pair(getCurrentSection(), getPreviousSection()));
			}
	/// Tell this MCStreamer to call InitSections upon initialization.		/// popSection - Restore the current and previous section from
	void setAutoInitSections(bool AutoInitSections) {		/// the section stack. Calls ChangeSection as needed.
	this->AutoInitSections = AutoInitSections;		///
	}		/// Returns false if the stack was empty.
			bool PopSection() {
			if (SectionStack.size() <= 1)
			return false;
			MCSectionSubPair oldSection = SectionStack.pop_back_val().first;
			MCSectionSubPair curSection = SectionStack.back().first;
			if (oldSection != curSection)
			ChangeSection(curSection.first, curSection.second);
			return true;
			}
			bool SubSection(const MCExpr *Subsection) {
			if (SectionStack.empty())
			return false;
			SwitchSection(SectionStack.back().first.first, Subsection);
			return true;
			}
	/// InitSections - Create the default sections and set the initial one.		/// SwitchSection - Set the current section where code is being emitted t
	virtual void InitSections() = 0;		o
			/// @p Section. This is required to update CurSection.
			///
			/// This corresponds to assembler directives like .section, .text, etc.
			void SwitchSection(const MCSection *Section, const MCExpr *Subsection = 0
			) {
			assert(Section && "Cannot switch to a null section!");
			MCSectionSubPair curSection = SectionStack.back().first;
			SectionStack.back().second = curSection;
			if (MCSectionSubPair(Section, Subsection) != curSection) {
			SectionStack.back().first = MCSectionSubPair(Section, Subsection);
			ChangeSection(Section, Subsection);
			}
			}
			/// SwitchSectionNoChange - Set the current section where code is being
			/// emitted to @p Section. This is required to update CurSection. This
			/// version does not call ChangeSection.
			void SwitchSectionNoChange(const MCSection *Section,
			const MCExpr *Subsection = 0) {
			assert(Section && "Cannot switch to a null section!");
			MCSectionSubPair curSection = SectionStack.back().first;
			SectionStack.back().second = curSection;
			if (MCSectionSubPair(Section, Subsection) != curSection)
			SectionStack.back().first = MCSectionSubPair(Section, Subsection);
			}
			/// Initialize the streamer.
			void InitStreamer() {
			if (AutoInitSections)
			InitSections();
			}
			/// Tell this MCStreamer to call InitSections upon initialization.
			void setAutoInitSections(bool AutoInitSections) {
			this->AutoInitSections = AutoInitSections;
			}
	/// InitToTextSection - Create a text section and switch the streamer t		/// InitSections - Create the default sections and set the initial one.
	o it.		virtual void InitSections() = 0;
	virtual void InitToTextSection() = 0;
	/// EmitLabel - Emit a label for @p Symbol into the current section.		/// InitToTextSection - Create a text section and switch the streamer to
	///		it.
	/// This corresponds to an assembler statement such as:		virtual void InitToTextSection() = 0;
	/// foo:
	///
	/// @param Symbol - The symbol to emit. A given symbol should only be
	/// emitted as a label once, and symbols emitted as a label should neve
	r be
	/// used in an assignment.
	virtual void EmitLabel(MCSymbol *Symbol);
	virtual void EmitDebugLabel(MCSymbol *Symbol);
	virtual void EmitEHSymAttributes(const MCSymbol *Symbol,
	MCSymbol *EHSymbol);
	/// EmitAssemblerFlag - Note in the output the specified @p Flag.
	virtual void EmitAssemblerFlag(MCAssemblerFlag Flag) = 0;
	/// EmitLinkerOptions - Emit the given list @p Options of strings as li
	nker
	/// options into the output.
	virtual void EmitLinkerOptions(ArrayRef<std::string> Kind) {}
	/// EmitDataRegion - Note in the output the specified region @p Kind.
	virtual void EmitDataRegion(MCDataRegionType Kind) {}
	/// EmitThumbFunc - Note in the output that the specified @p Func is
	/// a Thumb mode function (ARM target only).
	virtual void EmitThumbFunc(MCSymbol *Func) = 0;
	/// getOrCreateSymbolData - Get symbol data for given symbol.
	virtual MCSymbolData &getOrCreateSymbolData(MCSymbol *Symbol);
	/// EmitAssignment - Emit an assignment of @p Value to @p Symbol.
	///
	/// This corresponds to an assembler statement such as:
	/// symbol = value
	///
	/// The assignment generates no code, but has the side effect of bindin
	g the
	/// value in the current context. For the assembly streamer, this print
	s the
	/// binding into the .s file.
	///
	/// @param Symbol - The symbol being assigned to.
	/// @param Value - The value for the symbol.
	virtual void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) = 0;
	/// EmitWeakReference - Emit an weak reference from @p Alias to @p Symb
	ol.
	///
	/// This corresponds to an assembler statement such as:
	/// .weakref alias, symbol
	///
	/// @param Alias - The alias that is being created.
	/// @param Symbol - The symbol being aliased.
	virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol)
	= 0;
	/// EmitSymbolAttribute - Add the given @p Attribute to @p Symbol.
	virtual void EmitSymbolAttribute(MCSymbol *Symbol,
	MCSymbolAttr Attribute) = 0;
	/// EmitSymbolDesc - Set the @p DescValue for the @p Symbol.
	///
	/// @param Symbol - The symbol to have its n_desc field set.
	/// @param DescValue - The value to set into the n_desc field.
	virtual void EmitSymbolDesc(MCSymbol *Symbol, unsigned DescValue) = 0;
	/// BeginCOFFSymbolDef - Start emitting COFF symbol definition
	///
	/// @param Symbol - The symbol to have its External & Type fields set.
	virtual void BeginCOFFSymbolDef(const MCSymbol *Symbol) = 0;
	/// EmitCOFFSymbolStorageClass - Emit the storage class of the symbol.
	///
	/// @param StorageClass - The storage class the symbol should have.
	virtual void EmitCOFFSymbolStorageClass(int StorageClass) = 0;
	/// EmitCOFFSymbolType - Emit the type of the symbol.
	///
	/// @param Type - A COFF type identifier (see COFF::SymbolType in X86CO
	FF.h)
	virtual void EmitCOFFSymbolType(int Type) = 0;
	/// EndCOFFSymbolDef - Marks the end of the symbol definition.
	virtual void EndCOFFSymbolDef() = 0;
	/// EmitCOFFSecRel32 - Emits a COFF section relative relocation.
	///
	/// @param Symbol - Symbol the section relative realocation should poin
	t to.
	virtual void EmitCOFFSecRel32(MCSymbol const *Symbol);
	/// EmitELFSize - Emit an ELF .size directive.
	///
	/// This corresponds to an assembler statement such as:
	/// .size symbol, expression
	///
	virtual void EmitELFSize(MCSymbol *Symbol, const MCExpr *Value) = 0;
	/// EmitCommonSymbol - Emit a common symbol.
	///
	/// @param Symbol - The common symbol to emit.
	/// @param Size - The size of the common symbol.
	/// @param ByteAlignment - The alignment of the symbol if
	/// non-zero. This must be a power of 2.
	virtual void EmitCommonSymbol(MCSymbol *Symbol, uint64_t Size,
	unsigned ByteAlignment) = 0;
	/// EmitLocalCommonSymbol - Emit a local common (.lcomm) symbol.
	///
	/// @param Symbol - The common symbol to emit.
	/// @param Size - The size of the common symbol.
	/// @param ByteAlignment - The alignment of the common symbol in bytes.
	virtual void EmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size,
	unsigned ByteAlignment) = 0;
	/// EmitZerofill - Emit the zerofill section and an optional symbol.
	///
	/// @param Section - The zerofill section to create and or to put the s
	ymbol
	/// @param Symbol - The zerofill symbol to emit, if non-NULL.
	/// @param Size - The size of the zerofill symbol.
	/// @param ByteAlignment - The alignment of the zerofill symbol if
	/// non-zero. This must be a power of 2 on some targets.
	virtual void EmitZerofill(const MCSection *Section, MCSymbol *Symbol =
	0,
	uint64_t Size = 0,unsigned ByteAlignment = 0)
	= 0;
	/// EmitTBSSSymbol - Emit a thread local bss (.tbss) symbol.
	///
	/// @param Section - The thread local common section.
	/// @param Symbol - The thread local common symbol to emit.
	/// @param Size - The size of the symbol.
	/// @param ByteAlignment - The alignment of the thread local common sym
	bol
	/// if non-zero. This must be a power of 2 on some targets.
	virtual void EmitTBSSSymbol(const MCSection *Section, MCSymbol *Symbol,
	uint64_t Size, unsigned ByteAlignment = 0)
	= 0;
	/// @}
	/// @name Generating Data
	/// @{
	/// EmitBytes - Emit the bytes in \p Data into the output.
	///
	/// This is used to implement assembler directives such as .byte, .asci
	i,
	/// etc.
	virtual void EmitBytes(StringRef Data, unsigned AddrSpace = 0) = 0;
	/// EmitValue - Emit the expression @p Value into the output as a nativ
	e
	/// integer of the given @p Size bytes.
	///
	/// This is used to implement assembler directives such as .word, .quad
	,
	/// etc.
	///
	/// @param Value - The value to emit.
	/// @param Size - The size of the integer (in bytes) to emit. This must
	/// match a native machine width.
	virtual void EmitValueImpl(const MCExpr *Value, unsigned Size,
	unsigned AddrSpace) = 0;
	void EmitValue(const MCExpr *Value, unsigned Size, unsigned AddrSpace =
	0);
	/// EmitIntValue - Special case of EmitValue that avoids the client hav
	ing
	/// to pass in a MCExpr for constant integers.
	virtual void EmitIntValue(uint64_t Value, unsigned Size,
	unsigned AddrSpace = 0);
	/// EmitAbsValue - Emit the Value, but try to avoid relocations. On Mac
	hO
	/// this is done by producing
	/// foo = value
	/// .long foo
	void EmitAbsValue(const MCExpr *Value, unsigned Size,
	unsigned AddrSpace = 0);
	virtual void EmitULEB128Value(const MCExpr *Value) = 0;
	virtual void EmitSLEB128Value(const MCExpr *Value) = 0;
	/// EmitULEB128Value - Special case of EmitULEB128Value that avoids the
	/// client having to pass in a MCExpr for constant integers.
	void EmitULEB128IntValue(uint64_t Value, unsigned Padding = 0,
	unsigned AddrSpace = 0);
	/// EmitSLEB128Value - Special case of EmitSLEB128Value that avoids the
	/// client having to pass in a MCExpr for constant integers.
	void EmitSLEB128IntValue(int64_t Value, unsigned AddrSpace = 0);
	/// EmitSymbolValue - Special case of EmitValue that avoids the client
	/// having to pass in a MCExpr for MCSymbols.
	void EmitSymbolValue(const MCSymbol *Sym, unsigned Size,
	unsigned AddrSpace = 0);
	/// EmitGPRel64Value - Emit the expression @p Value into the output as
	a
	/// gprel64 (64-bit GP relative) value.
	///
	/// This is used to implement assembler directives such as .gpdword on
	/// targets that support them.
	virtual void EmitGPRel64Value(const MCExpr *Value);
	/// EmitGPRel32Value - Emit the expression @p Value into the output as
	a
	/// gprel32 (32-bit GP relative) value.
	///
	/// This is used to implement assembler directives such as .gprel32 on
	/// targets that support them.
	virtual void EmitGPRel32Value(const MCExpr *Value);
	/// EmitFill - Emit NumBytes bytes worth of the value specified by
	/// FillValue. This implements directives such as '.space'.
	virtual void EmitFill(uint64_t NumBytes, uint8_t FillValue,
	unsigned AddrSpace = 0);
	/// EmitZeros - Emit NumBytes worth of zeros. This is a convenience
	/// function that just wraps EmitFill.
	void EmitZeros(uint64_t NumBytes, unsigned AddrSpace = 0) {
	EmitFill(NumBytes, 0, AddrSpace);
	}
	/// EmitValueToAlignment - Emit some number of copies of @p Value until		/// AssignSection - Sets the symbol's section.
	/// the byte alignment @p ByteAlignment is reached.		///
	///		/// Each emitted symbol will be tracked in the ordering table,
	/// If the number of bytes need to emit for the alignment is not a mult		/// so we can sort on them later.
	iple		void AssignSection(MCSymbol *Symbol, const MCSection *Section);
	/// of @p ValueSize, then the contents of the emitted fill bytes is
	/// undefined.
	///
	/// This used to implement the .align assembler directive.
	///
	/// @param ByteAlignment - The alignment to reach. This must be a power
	of
	/// two on some targets.
	/// @param Value - The value to use when filling bytes.
	/// @param ValueSize - The size of the integer (in bytes) to emit for
	/// @p Value. This must match a native machine width.
	/// @param MaxBytesToEmit - The maximum numbers of bytes to emit, or 0.
	If
	/// the alignment cannot be reached in this many bytes, no bytes are
	/// emitted.
	virtual void EmitValueToAlignment(unsigned ByteAlignment, int64_t Value
	= 0,
	unsigned ValueSize = 1,
	unsigned MaxBytesToEmit = 0) = 0;
	/// EmitCodeAlignment - Emit nops until the byte alignment @p ByteAlign
	ment
	/// is reached.
	///
	/// This used to align code where the alignment bytes may be executed.
	This
	/// can emit different bytes for different sizes to optimize execution.
	///
	/// @param ByteAlignment - The alignment to reach. This must be a power
	of
	/// two on some targets.
	/// @param MaxBytesToEmit - The maximum numbers of bytes to emit, or 0.
	If
	/// the alignment cannot be reached in this many bytes, no bytes are
	/// emitted.
	virtual void EmitCodeAlignment(unsigned ByteAlignment,
	unsigned MaxBytesToEmit = 0) = 0;
	/// EmitValueToOffset - Emit some number of copies of @p Value until th
	e
	/// byte offset @p Offset is reached.
	///
	/// This is used to implement assembler directives such as .org.
	///
	/// @param Offset - The offset to reach. This may be an expression, but
	the
	/// expression must be associated with the current section.
	/// @param Value - The value to use when filling bytes.
	/// @return false on success, true if the offset was invalid.
	virtual bool EmitValueToOffset(const MCExpr *Offset,
	unsigned char Value = 0) = 0;
	/// @}
	/// EmitFileDirective - Switch to a new logical file. This is used to
	/// implement the '.file "foo.c"' assembler directive.
	virtual void EmitFileDirective(StringRef Filename) = 0;
	/// EmitDwarfFileDirective - Associate a filename with a specified logi
	cal
	/// file number. This implements the DWARF2 '.file 4 "foo.c"' assemble
	r
	/// directive.
	virtual bool EmitDwarfFileDirective(unsigned FileNo, StringRef Director
	y,
	StringRef Filename, unsigned CUID =
	0);
	/// EmitDwarfLocDirective - This implements the DWARF2
	// '.loc fileno lineno ...' assembler directive.
	virtual void EmitDwarfLocDirective(unsigned FileNo, unsigned Line,
	unsigned Column, unsigned Flags,
	unsigned Isa,
	unsigned Discriminator,
	StringRef FileName);
	virtual void EmitDwarfAdvanceLineAddr(int64_t LineDelta,
	const MCSymbol *LastLabel,
	const MCSymbol *Label,
	unsigned PointerSize) = 0;
	virtual void EmitDwarfAdvanceFrameAddr(const MCSymbol *LastLabel,		/// EmitLabel - Emit a label for @p Symbol into the current section.
	const MCSymbol *Label) {		///
	}		/// This corresponds to an assembler statement such as:
			/// foo:
			///
			/// @param Symbol - The symbol to emit. A given symbol should only be
			/// emitted as a label once, and symbols emitted as a label should never
			be
			/// used in an assignment.
			virtual void EmitLabel(MCSymbol *Symbol);
	void EmitDwarfSetLineAddr(int64_t LineDelta, const MCSymbol *Label,		virtual void EmitDebugLabel(MCSymbol *Symbol);
	int PointerSize);
	virtual void EmitCompactUnwindEncoding(uint32_t CompactUnwindEncoding);		virtual void EmitEHSymAttributes(const MCSymbol *Symbol, MCSymbol *EHSymb
	virtual void EmitCFISections(bool EH, bool Debug);		ol);
	void EmitCFIStartProc();
	void EmitCFIEndProc();		/// EmitAssemblerFlag - Note in the output the specified @p Flag.
	virtual void EmitCFIDefCfa(int64_t Register, int64_t Offset);		virtual void EmitAssemblerFlag(MCAssemblerFlag Flag) = 0;
	virtual void EmitCFIDefCfaOffset(int64_t Offset);
	virtual void EmitCFIDefCfaRegister(int64_t Register);		/// EmitLinkerOptions - Emit the given list @p Options of strings as link
	virtual void EmitCFIOffset(int64_t Register, int64_t Offset);		er
	virtual void EmitCFIPersonality(const MCSymbol *Sym, unsigned Encoding)		/// options into the output.
	;		virtual void EmitLinkerOptions(ArrayRef<std::string> Kind) {}
	virtual void EmitCFILsda(const MCSymbol *Sym, unsigned Encoding);
	virtual void EmitCFIRememberState();		/// EmitDataRegion - Note in the output the specified region @p Kind.
	virtual void EmitCFIRestoreState();		virtual void EmitDataRegion(MCDataRegionType Kind) {}
	virtual void EmitCFISameValue(int64_t Register);
	virtual void EmitCFIRestore(int64_t Register);		/// EmitThumbFunc - Note in the output that the specified @p Func is
	virtual void EmitCFIRelOffset(int64_t Register, int64_t Offset);		/// a Thumb mode function (ARM target only).
	virtual void EmitCFIAdjustCfaOffset(int64_t Adjustment);		virtual void EmitThumbFunc(MCSymbol *Func) = 0;
	virtual void EmitCFIEscape(StringRef Values);
	virtual void EmitCFISignalFrame();
	virtual void EmitCFIUndefined(int64_t Register);
	virtual void EmitCFIRegister(int64_t Register1, int64_t Register2);
	virtual void EmitWin64EHStartProc(const MCSymbol *Symbol);
	virtual void EmitWin64EHEndProc();
	virtual void EmitWin64EHStartChained();
	virtual void EmitWin64EHEndChained();
	virtual void EmitWin64EHHandler(const MCSymbol *Sym, bool Unwind,
	bool Except);
	virtual void EmitWin64EHHandlerData();
	virtual void EmitWin64EHPushReg(unsigned Register);
	virtual void EmitWin64EHSetFrame(unsigned Register, unsigned Offset);
	virtual void EmitWin64EHAllocStack(unsigned Size);
	virtual void EmitWin64EHSaveReg(unsigned Register, unsigned Offset);
	virtual void EmitWin64EHSaveXMM(unsigned Register, unsigned Offset);
	virtual void EmitWin64EHPushFrame(bool Code);
	virtual void EmitWin64EHEndProlog();
	/// EmitInstruction - Emit the given @p Instruction into the current
	/// section.
	virtual void EmitInstruction(const MCInst &Inst) = 0;
	/// \brief Set the bundle alignment mode from now on in the section.
	/// The argument is the power of 2 to which the alignment is set. The
	/// value 0 means turn the bundle alignment off.
	virtual void EmitBundleAlignMode(unsigned AlignPow2) = 0;
	/// \brief The following instructions are a bundle-locked group.
	///
	/// \param AlignToEnd - If true, the bundle-locked group will be aligne
	d to
	/// the end of a bundle.
	virtual void EmitBundleLock(bool AlignToEnd) = 0;
	/// \brief Ends a bundle-locked group.
	virtual void EmitBundleUnlock() = 0;
	/// EmitRawText - If this file is backed by a assembly streamer, this d
	umps
	/// the specified string in the output .s file. This capability is
	/// indicated by the hasRawTextSupport() predicate. By default this ab
	orts.
	virtual void EmitRawText(StringRef String);
	void EmitRawText(const Twine &String);
	/// ARM-related methods.
	/// FIXME: Eventually we should have some "target MC streamer" and move
	/// these methods there.
	virtual void EmitFnStart();
	virtual void EmitFnEnd();
	virtual void EmitCantUnwind();
	virtual void EmitPersonality(const MCSymbol *Personality);
	virtual void EmitHandlerData();
	virtual void EmitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset =
	0);
	virtual void EmitPad(int64_t Offset);
	virtual void EmitRegSave(const SmallVectorImpl<unsigned> &RegList,
	bool isVector);
	/// PPC-related methods.
	/// FIXME: Eventually replace it with some "target MC streamer" and mov
	e
	/// these methods there.
	virtual void EmitTCEntry(const MCSymbol &S);
	/// FinishImpl - Streamer specific finalization.
	virtual void FinishImpl() = 0;
	/// Finish - Finish emission of machine code.
	void Finish();
	};
	/// createNullStreamer - Create a dummy machine code streamer, which does
	/// nothing. This is useful for timing the assembler front end.
	MCStreamer *createNullStreamer(MCContext &Ctx);
	/// createAsmStreamer - Create a machine code streamer which will print o
	ut
	/// assembly for the native target, suitable for compiling with a native
	/// assembler.
	///
	/// \param InstPrint - If given, the instruction printer to use. If not g
	iven
	/// the MCInst representation will be printed. This method takes ownersh
	ip of
	/// InstPrint.
	///
	/// \param CE - If given, a code emitter to use to show the instruction
	/// encoding inline with the assembly. This method takes ownership of \p
	CE.
	///
	/// \param TAB - If given, a target asm backend to use to show the fixup
	/// information in conjunction with encoding information. This method tak
	es
	/// ownership of \p TAB.
	///
	/// \param ShowInst - Whether to show the MCInst representation inline wi
	th
	/// the assembly.
	MCStreamer *createAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
	bool isVerboseAsm,
	bool useLoc,
	bool useCFI,
	bool useDwarfDirectory,
	MCInstPrinter *InstPrint = 0,
	MCCodeEmitter *CE = 0,
	MCAsmBackend *TAB = 0,
	bool ShowInst = false);
	/// createMachOStreamer - Create a machine code streamer which will gener
	ate
	/// Mach-O format object files.
	///
	/// Takes ownership of \p TAB and \p CE.
	MCStreamer *createMachOStreamer(MCContext &Ctx, MCAsmBackend &TAB,
	raw_ostream &OS, MCCodeEmitter *CE,
	bool RelaxAll = false);
	/// createWinCOFFStreamer - Create a machine code streamer which will		/// getOrCreateSymbolData - Get symbol data for given symbol.
	/// generate Microsoft COFF format object files.		virtual MCSymbolData &getOrCreateSymbolData(MCSymbol *Symbol);
			/// EmitAssignment - Emit an assignment of @p Value to @p Symbol.
	///		///
	/// Takes ownership of \p TAB and \p CE.		/// This corresponds to an assembler statement such as:
	MCStreamer *createWinCOFFStreamer(MCContext &Ctx,		/// symbol = value
	MCAsmBackend &TAB,		///
	MCCodeEmitter &CE, raw_ostream &OS,		/// The assignment generates no code, but has the side effect of binding
	bool RelaxAll = false);		the
			/// value in the current context. For the assembly streamer, this prints
	/// createELFStreamer - Create a machine code streamer which will generat		the
	e		/// binding into the .s file.
	/// ELF format object files.		///
	MCStreamer *createELFStreamer(MCContext &Ctx, MCAsmBackend &TAB,		/// @param Symbol - The symbol being assigned to.
	raw_ostream &OS, MCCodeEmitter *CE,		/// @param Value - The value for the symbol.
	bool RelaxAll, bool NoExecStack);		virtual void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) = 0;
			/// EmitWeakReference - Emit an weak reference from @p Alias to @p Symbol
			.
			///
			/// This corresponds to an assembler statement such as:
			/// .weakref alias, symbol
			///
			/// @param Alias - The alias that is being created.
			/// @param Symbol - The symbol being aliased.
			virtual void EmitWeakReference(MCSymbol *Alias, const MCSymbol *Symbol) =
			0;
			/// EmitSymbolAttribute - Add the given @p Attribute to @p Symbol.
			virtual bool EmitSymbolAttribute(MCSymbol *Symbol,
			MCSymbolAttr Attribute) = 0;
			/// EmitSymbolDesc - Set the @p DescValue for the @p Symbol.
			///
			/// @param Symbol - The symbol to have its n_desc field set.
			/// @param DescValue - The value to set into the n_desc field.
			virtual void EmitSymbolDesc(MCSymbol *Symbol, unsigned DescValue) = 0;
			/// BeginCOFFSymbolDef - Start emitting COFF symbol definition
			///
			/// @param Symbol - The symbol to have its External & Type fields set.
			virtual void BeginCOFFSymbolDef(const MCSymbol *Symbol) = 0;
			/// EmitCOFFSymbolStorageClass - Emit the storage class of the symbol.
			///
			/// @param StorageClass - The storage class the symbol should have.
			virtual void EmitCOFFSymbolStorageClass(int StorageClass) = 0;
			/// EmitCOFFSymbolType - Emit the type of the symbol.
			///
			/// @param Type - A COFF type identifier (see COFF::SymbolType in X86COFF
			.h)
			virtual void EmitCOFFSymbolType(int Type) = 0;
			/// EndCOFFSymbolDef - Marks the end of the symbol definition.
			virtual void EndCOFFSymbolDef() = 0;
	/// createPureStreamer - Create a machine code streamer which will genera		/// EmitCOFFSecRel32 - Emits a COFF section relative relocation.
	te
	/// "pure" MC object files, for use with MC-JIT and testing tools.
	///		///
	/// Takes ownership of \p TAB and \p CE.		/// @param Symbol - Symbol the section relative realocation should point
	MCStreamer *createPureStreamer(MCContext &Ctx, MCAsmBackend &TAB,		to.
	raw_ostream &OS, MCCodeEmitter *CE);		virtual void EmitCOFFSecRel32(MCSymbol const *Symbol);
			/// EmitELFSize - Emit an ELF .size directive.
			///
			/// This corresponds to an assembler statement such as:
			/// .size symbol, expression
			///
			virtual void EmitELFSize(MCSymbol *Symbol, const MCExpr *Value) = 0;
			/// EmitCommonSymbol - Emit a common symbol.
			///
			/// @param Symbol - The common symbol to emit.
			/// @param Size - The size of the common symbol.
			/// @param ByteAlignment - The alignment of the symbol if
			/// non-zero. This must be a power of 2.
			virtual void EmitCommonSymbol(MCSymbol *Symbol, uint64_t Size,
			unsigned ByteAlignment) = 0;
			/// EmitLocalCommonSymbol - Emit a local common (.lcomm) symbol.
			///
			/// @param Symbol - The common symbol to emit.
			/// @param Size - The size of the common symbol.
			/// @param ByteAlignment - The alignment of the common symbol in bytes.
			virtual void EmitLocalCommonSymbol(MCSymbol *Symbol, uint64_t Size,
			unsigned ByteAlignment) = 0;
			/// EmitZerofill - Emit the zerofill section and an optional symbol.
			///
			/// @param Section - The zerofill section to create and or to put the sym
			bol
			/// @param Symbol - The zerofill symbol to emit, if non-NULL.
			/// @param Size - The size of the zerofill symbol.
			/// @param ByteAlignment - The alignment of the zerofill symbol if
			/// non-zero. This must be a power of 2 on some targets.
			virtual void EmitZerofill(const MCSection *Section, MCSymbol *Symbol = 0,
			uint64_t Size = 0, unsigned ByteAlignment = 0)
			= 0;
			/// EmitTBSSSymbol - Emit a thread local bss (.tbss) symbol.
			///
			/// @param Section - The thread local common section.
			/// @param Symbol - The thread local common symbol to emit.
			/// @param Size - The size of the symbol.
			/// @param ByteAlignment - The alignment of the thread local common symbo
			l
			/// if non-zero. This must be a power of 2 on some targets.
			virtual void EmitTBSSSymbol(const MCSection *Section, MCSymbol *Symbol,
			uint64_t Size, unsigned ByteAlignment = 0) =
			0;
			/// @}
			/// @name Generating Data
			/// @{
			/// EmitBytes - Emit the bytes in \p Data into the output.
			///
			/// This is used to implement assembler directives such as .byte, .ascii,
			/// etc.
			virtual void EmitBytes(StringRef Data) = 0;
			/// EmitValue - Emit the expression @p Value into the output as a native
			/// integer of the given @p Size bytes.
			///
			/// This is used to implement assembler directives such as .word, .quad,
			/// etc.
			///
			/// @param Value - The value to emit.
			/// @param Size - The size of the integer (in bytes) to emit. This must
			/// match a native machine width.
			virtual void EmitValueImpl(const MCExpr *Value, unsigned Size) = 0;
			void EmitValue(const MCExpr *Value, unsigned Size);
			/// EmitIntValue - Special case of EmitValue that avoids the client havin
			g
			/// to pass in a MCExpr for constant integers.
			virtual void EmitIntValue(uint64_t Value, unsigned Size);
			/// EmitAbsValue - Emit the Value, but try to avoid relocations. On MachO
			/// this is done by producing
			/// foo = value
			/// .long foo
			void EmitAbsValue(const MCExpr *Value, unsigned Size);
			virtual void EmitULEB128Value(const MCExpr *Value) = 0;
			virtual void EmitSLEB128Value(const MCExpr *Value) = 0;
			/// EmitULEB128Value - Special case of EmitULEB128Value that avoids the
			/// client having to pass in a MCExpr for constant integers.
			void EmitULEB128IntValue(uint64_t Value, unsigned Padding = 0);
			/// EmitSLEB128Value - Special case of EmitSLEB128Value that avoids the
			/// client having to pass in a MCExpr for constant integers.
			void EmitSLEB128IntValue(int64_t Value);
			/// EmitSymbolValue - Special case of EmitValue that avoids the client
			/// having to pass in a MCExpr for MCSymbols.
			void EmitSymbolValue(const MCSymbol *Sym, unsigned Size);
			/// EmitGPRel64Value - Emit the expression @p Value into the output as a
			/// gprel64 (64-bit GP relative) value.
			///
			/// This is used to implement assembler directives such as .gpdword on
			/// targets that support them.
			virtual void EmitGPRel64Value(const MCExpr *Value);
			/// EmitGPRel32Value - Emit the expression @p Value into the output as a
			/// gprel32 (32-bit GP relative) value.
			///
			/// This is used to implement assembler directives such as .gprel32 on
			/// targets that support them.
			virtual void EmitGPRel32Value(const MCExpr *Value);
			/// EmitFill - Emit NumBytes bytes worth of the value specified by
			/// FillValue. This implements directives such as '.space'.
			virtual void EmitFill(uint64_t NumBytes, uint8_t FillValue);
			/// \brief Emit NumBytes worth of zeros.
			/// This function properly handles data in virtual sections.
			virtual void EmitZeros(uint64_t NumBytes);
			/// EmitValueToAlignment - Emit some number of copies of @p Value until
			/// the byte alignment @p ByteAlignment is reached.
			///
			/// If the number of bytes need to emit for the alignment is not a multip
			le
			/// of @p ValueSize, then the contents of the emitted fill bytes is
			/// undefined.
			///
			/// This used to implement the .align assembler directive.
			///
			/// @param ByteAlignment - The alignment to reach. This must be a power o
			f
			/// two on some targets.
			/// @param Value - The value to use when filling bytes.
			/// @param ValueSize - The size of the integer (in bytes) to emit for
			/// @p Value. This must match a native machine width.
			/// @param MaxBytesToEmit - The maximum numbers of bytes to emit, or 0. I
			f
			/// the alignment cannot be reached in this many bytes, no bytes are
			/// emitted.
			virtual void EmitValueToAlignment(unsigned ByteAlignment, int64_t Value =
			0,
			unsigned ValueSize = 1,
			unsigned MaxBytesToEmit = 0) = 0;
			/// EmitCodeAlignment - Emit nops until the byte alignment @p ByteAlignme
			nt
			/// is reached.
			///
			/// This used to align code where the alignment bytes may be executed. T
			his
			/// can emit different bytes for different sizes to optimize execution.
			///
			/// @param ByteAlignment - The alignment to reach. This must be a power o
			f
			/// two on some targets.
			/// @param MaxBytesToEmit - The maximum numbers of bytes to emit, or 0. I
			f
			/// the alignment cannot be reached in this many bytes, no bytes are
			/// emitted.
			virtual void EmitCodeAlignment(unsigned ByteAlignment,
			unsigned MaxBytesToEmit = 0) = 0;
			/// EmitValueToOffset - Emit some number of copies of @p Value until the
			/// byte offset @p Offset is reached.
			///
			/// This is used to implement assembler directives such as .org.
			///
			/// @param Offset - The offset to reach. This may be an expression, but t
			he
			/// expression must be associated with the current section.
			/// @param Value - The value to use when filling bytes.
			/// @return false on success, true if the offset was invalid.
			virtual bool EmitValueToOffset(const MCExpr *Offset,
			unsigned char Value = 0) = 0;
			/// @}
			/// EmitFileDirective - Switch to a new logical file. This is used to
			/// implement the '.file "foo.c"' assembler directive.
			virtual void EmitFileDirective(StringRef Filename) = 0;
			/// Emit the "identifiers" directive. This implements the
			/// '.ident "version foo"' assembler directive.
			virtual void EmitIdent(StringRef IdentString) {}
			/// EmitDwarfFileDirective - Associate a filename with a specified logica
			l
			/// file number. This implements the DWARF2 '.file 4 "foo.c"' assembler
			/// directive.
			virtual bool EmitDwarfFileDirective(unsigned FileNo, StringRef Directory,
			StringRef Filename, unsigned CUID = 0
			);
			/// EmitDwarfLocDirective - This implements the DWARF2
			// '.loc fileno lineno ...' assembler directive.
			virtual void EmitDwarfLocDirective(unsigned FileNo, unsigned Line,
			unsigned Column, unsigned Flags,
			unsigned Isa, unsigned Discriminator,
			StringRef FileName);
			virtual void EmitDwarfAdvanceLineAddr(int64_t LineDelta,
			const MCSymbol *LastLabel,
			const MCSymbol *Label,
			unsigned PointerSize) = 0;
			virtual void EmitDwarfAdvanceFrameAddr(const MCSymbol *LastLabel,
			const MCSymbol *Label) {}
			void EmitDwarfSetLineAddr(int64_t LineDelta, const MCSymbol *Label,
			int PointerSize);
			virtual void EmitCompactUnwindEncoding(uint32_t CompactUnwindEncoding);
			virtual void EmitCFISections(bool EH, bool Debug);
			void EmitCFIStartProc();
			void EmitCFIEndProc();
			virtual void EmitCFIDefCfa(int64_t Register, int64_t Offset);
			virtual void EmitCFIDefCfaOffset(int64_t Offset);
			virtual void EmitCFIDefCfaRegister(int64_t Register);
			virtual void EmitCFIOffset(int64_t Register, int64_t Offset);
			virtual void EmitCFIPersonality(const MCSymbol *Sym, unsigned Encoding);
			virtual void EmitCFILsda(const MCSymbol *Sym, unsigned Encoding);
			virtual void EmitCFIRememberState();
			virtual void EmitCFIRestoreState();
			virtual void EmitCFISameValue(int64_t Register);
			virtual void EmitCFIRestore(int64_t Register);
			virtual void EmitCFIRelOffset(int64_t Register, int64_t Offset);
			virtual void EmitCFIAdjustCfaOffset(int64_t Adjustment);
			virtual void EmitCFIEscape(StringRef Values);
			virtual void EmitCFISignalFrame();
			virtual void EmitCFIUndefined(int64_t Register);
			virtual void EmitCFIRegister(int64_t Register1, int64_t Register2);
			virtual void EmitCFIWindowSave();
			virtual void EmitWin64EHStartProc(const MCSymbol *Symbol);
			virtual void EmitWin64EHEndProc();
			virtual void EmitWin64EHStartChained();
			virtual void EmitWin64EHEndChained();
			virtual void EmitWin64EHHandler(const MCSymbol *Sym, bool Unwind,
			bool Except);
			virtual void EmitWin64EHHandlerData();
			virtual void EmitWin64EHPushReg(unsigned Register);
			virtual void EmitWin64EHSetFrame(unsigned Register, unsigned Offset);
			virtual void EmitWin64EHAllocStack(unsigned Size);
			virtual void EmitWin64EHSaveReg(unsigned Register, unsigned Offset);
			virtual void EmitWin64EHSaveXMM(unsigned Register, unsigned Offset);
			virtual void EmitWin64EHPushFrame(bool Code);
			virtual void EmitWin64EHEndProlog();
			/// EmitInstruction - Emit the given @p Instruction into the current
			/// section.
			virtual void EmitInstruction(const MCInst &Inst) = 0;
			/// \brief Set the bundle alignment mode from now on in the section.
			/// The argument is the power of 2 to which the alignment is set. The
			/// value 0 means turn the bundle alignment off.
			virtual void EmitBundleAlignMode(unsigned AlignPow2) = 0;
			/// \brief The following instructions are a bundle-locked group.
			///
			/// \param AlignToEnd - If true, the bundle-locked group will be aligned
			to
			/// the end of a bundle.
			virtual void EmitBundleLock(bool AlignToEnd) = 0;
			/// \brief Ends a bundle-locked group.
			virtual void EmitBundleUnlock() = 0;
			/// EmitRawText - If this file is backed by a assembly streamer, this dum
			ps
			/// the specified string in the output .s file. This capability is
			/// indicated by the hasRawTextSupport() predicate. By default this abor
			ts.
			void EmitRawText(const Twine &String);
			/// Flush - Causes any cached state to be written out.
			virtual void Flush() {}
			/// FinishImpl - Streamer specific finalization.
			virtual void FinishImpl() = 0;
			/// Finish - Finish emission of machine code.
			void Finish();
			};
			/// createNullStreamer - Create a dummy machine code streamer, which does
			/// nothing. This is useful for timing the assembler front end.
			MCStreamer *createNullStreamer(MCContext &Ctx);
			/// createAsmStreamer - Create a machine code streamer which will print out
			/// assembly for the native target, suitable for compiling with a native
			/// assembler.
			///
			/// \param InstPrint - If given, the instruction printer to use. If not giv
			en
			/// the MCInst representation will be printed. This method takes ownership
			of
			/// InstPrint.
			///
			/// \param CE - If given, a code emitter to use to show the instruction
			/// encoding inline with the assembly. This method takes ownership of \p CE
			.
			///
			/// \param TAB - If given, a target asm backend to use to show the fixup
			/// information in conjunction with encoding information. This method takes
			/// ownership of \p TAB.
			///
			/// \param ShowInst - Whether to show the MCInst representation inline with
			/// the assembly.
			MCStreamer *createAsmStreamer(MCContext &Ctx, MCTargetStreamer *TargetStrea
			mer,
			formatted_raw_ostream &OS, bool isVerboseAsm,
			bool useLoc, bool useCFI, bool useDwarfDirect
			ory,
			MCInstPrinter *InstPrint = 0,
			MCCodeEmitter *CE = 0, MCAsmBackend *TAB = 0,
			bool ShowInst = false);
			/// createMachOStreamer - Create a machine code streamer which will generat
			e
			/// Mach-O format object files.
			///
			/// Takes ownership of \p TAB and \p CE.
			MCStreamer *createMachOStreamer(MCContext &Ctx, MCAsmBackend &TAB,
			raw_ostream &OS, MCCodeEmitter *CE,
			bool RelaxAll = false);
			/// createWinCOFFStreamer - Create a machine code streamer which will
			/// generate Microsoft COFF format object files.
			///
			/// Takes ownership of \p TAB and \p CE.
			MCStreamer *createWinCOFFStreamer(MCContext &Ctx, MCAsmBackend &TAB,
			MCCodeEmitter &CE, raw_ostream &OS,
			bool RelaxAll = false);
			/// createELFStreamer - Create a machine code streamer which will generate
			/// ELF format object files.
			MCStreamer *createELFStreamer(MCContext &Ctx, MCTargetStreamer *TargetStrea
			mer,
			MCAsmBackend &TAB, raw_ostream &OS,
			MCCodeEmitter *CE, bool RelaxAll,
			bool NoExecStack);
			/// createPureStreamer - Create a machine code streamer which will generate
			/// "pure" MC object files, for use with MC-JIT and testing tools.
			///
			/// Takes ownership of \p TAB and \p CE.
			MCStreamer *createPureStreamer(MCContext &Ctx, MCAsmBackend &TAB,
			raw_ostream &OS, MCCodeEmitter *CE);
	} // end namespace llvm		} // end namespace llvm
	#endif		#endif
End of changes. 29 change blocks.
	716 lines changed or deleted		733 lines changed or added

	MCSubtargetInfo.h		MCSubtargetInfo.h
	skipping to change at line 75		skipping to change at line 75
	/// getFeatureBits - Return the feature bits.		/// getFeatureBits - Return the feature bits.
	///		///
	uint64_t getFeatureBits() const {		uint64_t getFeatureBits() const {
	return FeatureBits;		return FeatureBits;
	}		}
	/// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with		/// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with
	/// feature string). Recompute feature bits and scheduling model.		/// feature string). Recompute feature bits and scheduling model.
	void InitMCProcessorInfo(StringRef CPU, StringRef FS);		void InitMCProcessorInfo(StringRef CPU, StringRef FS);
			/// InitCPUSchedModel - Recompute scheduling model based on CPU.
			void InitCPUSchedModel(StringRef CPU);
	/// ToggleFeature - Toggle a feature and returns the re-computed feature		/// ToggleFeature - Toggle a feature and returns the re-computed feature
	/// bits. This version does not change the implied bits.		/// bits. This version does not change the implied bits.
	uint64_t ToggleFeature(uint64_t FB);		uint64_t ToggleFeature(uint64_t FB);
	/// ToggleFeature - Toggle a feature and returns the re-computed feature		/// ToggleFeature - Toggle a feature and returns the re-computed feature
	/// bits. This version will also change all implied bits.		/// bits. This version will also change all implied bits.
	uint64_t ToggleFeature(StringRef FS);		uint64_t ToggleFeature(StringRef FS);
	/// getSchedModelForCPU - Get the machine model of a CPU.		/// getSchedModelForCPU - Get the machine model of a CPU.
	///		///
End of changes. 1 change blocks.
	0 lines changed or deleted		3 lines changed or added

	MCTargetAsmParser.h		MCTargetAsmParser.h
	skipping to change at line 14		skipping to change at line 14
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_MC_TARGETPARSER_H		#ifndef LLVM_MC_TARGETPARSER_H
	#define LLVM_MC_TARGETPARSER_H		#define LLVM_MC_TARGETPARSER_H
	#include "llvm/MC/MCParser/MCAsmParserExtension.h"		#include "llvm/MC/MCParser/MCAsmParserExtension.h"
			#include "llvm/MC/MCExpr.h"
	namespace llvm {		namespace llvm {
	class MCStreamer;		class MCStreamer;
	class StringRef;		class StringRef;
	class SMLoc;		class SMLoc;
	class AsmToken;		class AsmToken;
	class MCParsedAsmOperand;		class MCParsedAsmOperand;
	class MCInst;		class MCInst;
	template <typename T> class SmallVectorImpl;		template <typename T> class SmallVectorImpl;
	skipping to change at line 146		skipping to change at line 147
	/// recording any target specific work, or return true and do nothing if the		/// recording any target specific work, or return true and do nothing if the
	/// directive is not target specific. If the directive is specific for		/// directive is not target specific. If the directive is specific for
	/// the target, the entire line is parsed up to and including the		/// the target, the entire line is parsed up to and including the
	/// end-of-statement token and false is returned.		/// end-of-statement token and false is returned.
	///		///
	/// \param DirectiveID - the identifier token of the directive.		/// \param DirectiveID - the identifier token of the directive.
	virtual bool ParseDirective(AsmToken DirectiveID) = 0;		virtual bool ParseDirective(AsmToken DirectiveID) = 0;
	/// mnemonicIsValid - This returns true if this is a valid mnemonic and f alse		/// mnemonicIsValid - This returns true if this is a valid mnemonic and f alse
	/// otherwise.		/// otherwise.
	virtual bool mnemonicIsValid(StringRef Mnemonic) = 0;		virtual bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) = 0;
	/// MatchAndEmitInstruction - Recognize a series of operands of a parsed		/// MatchAndEmitInstruction - Recognize a series of operands of a parsed
	/// instruction as an actual MCInst and emit it to the specified MCStream er.		/// instruction as an actual MCInst and emit it to the specified MCStream er.
	/// This returns false on success and returns true on failure to match.		/// This returns false on success and returns true on failure to match.
	///		///
	/// On failure, the target parser is responsible for emitting a diagnosti c		/// On failure, the target parser is responsible for emitting a diagnosti c
	/// explaining the match failure.		/// explaining the match failure.
	virtual bool		virtual bool
	MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,		MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
	SmallVectorImpl<MCParsedAsmOperand*> &Operands,		SmallVectorImpl<MCParsedAsmOperand*> &Operands,
	skipping to change at line 177		skipping to change at line 178
	}		}
	/// checkTargetMatchPredicate - Validate the instruction match against		/// checkTargetMatchPredicate - Validate the instruction match against
	/// any complex target predicates not expressible via match classes.		/// any complex target predicates not expressible via match classes.
	virtual unsigned checkTargetMatchPredicate(MCInst &Inst) {		virtual unsigned checkTargetMatchPredicate(MCInst &Inst) {
	return Match_Success;		return Match_Success;
	}		}
	virtual void convertToMapAndConstraints(unsigned Kind,		virtual void convertToMapAndConstraints(unsigned Kind,
	const SmallVectorImpl<MCParsedAsmOperand*> &Operands) = 0;		const SmallVectorImpl<MCParsedAsmOperand*> &Operands) = 0;
			virtual const MCExpr *applyModifierToExpr(const MCExpr *E,
			MCSymbolRefExpr::VariantKind,
			MCContext &Ctx) {
			return 0;
			}
			virtual void onLabelParsed(MCSymbol *Symbol) { };
	};		};
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 3 change blocks.
	1 lines changed or deleted		10 lines changed or added

	MCWinCOFFObjectWriter.h		MCWinCOFFObjectWriter.h
	skipping to change at line 20		skipping to change at line 20
	#ifndef LLVM_MC_MCWINCOFFOBJECTWRITER_H		#ifndef LLVM_MC_MCWINCOFFOBJECTWRITER_H
	#define LLVM_MC_MCWINCOFFOBJECTWRITER_H		#define LLVM_MC_MCWINCOFFOBJECTWRITER_H
	namespace llvm {		namespace llvm {
	class MCFixup;		class MCFixup;
	class MCObjectWriter;		class MCObjectWriter;
	class MCValue;		class MCValue;
	class raw_ostream;		class raw_ostream;
	class MCWinCOFFObjectTargetWriter {		class MCWinCOFFObjectTargetWriter {
			virtual void anchor();
	const unsigned Machine;		const unsigned Machine;
	protected:		protected:
	MCWinCOFFObjectTargetWriter(unsigned Machine_);		MCWinCOFFObjectTargetWriter(unsigned Machine_);
	public:		public:
	virtual ~MCWinCOFFObjectTargetWriter() {}		virtual ~MCWinCOFFObjectTargetWriter() {}
	unsigned getMachine() const { return Machine; }		unsigned getMachine() const { return Machine; }
	virtual unsigned getRelocType(const MCValue &Target,		virtual unsigned getRelocType(const MCValue &Target,
End of changes. 1 change blocks.
	0 lines changed or deleted		1 lines changed or added

	MachO.h		MachO.h
	skipping to change at line 20		skipping to change at line 20
	// This file declares the MachOObjectFile class, which implement the Object File		// This file declares the MachOObjectFile class, which implement the Object File
	// interface for MachO files.		// interface for MachO files.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_OBJECT_MACHO_H		#ifndef LLVM_OBJECT_MACHO_H
	#define LLVM_OBJECT_MACHO_H		#define LLVM_OBJECT_MACHO_H
	#include "llvm/ADT/ArrayRef.h"		#include "llvm/ADT/ArrayRef.h"
	#include "llvm/ADT/SmallVector.h"		#include "llvm/ADT/SmallVector.h"
	#include "llvm/Object/MachOFormat.h"		#include "llvm/ADT/Triple.h"
	#include "llvm/Object/ObjectFile.h"		#include "llvm/Object/ObjectFile.h"
	#include "llvm/Support/MachO.h"		#include "llvm/Support/MachO.h"
	#include "llvm/Support/raw_ostream.h"
	namespace llvm {		namespace llvm {
	namespace object {		namespace object {
			/// DiceRef - This is a value type class that represents a single
			/// data in code entry in the table in a Mach-O object file.
			class DiceRef {
			DataRefImpl DicePimpl;
			const ObjectFile *OwningObject;
			public:
			DiceRef() : OwningObject(NULL) { }
			DiceRef(DataRefImpl DiceP, const ObjectFile *Owner);
			bool operator==(const DiceRef &Other) const;
			bool operator<(const DiceRef &Other) const;
			error_code getNext(DiceRef &Result) const;
			error_code getOffset(uint32_t &Result) const;
			error_code getLength(uint16_t &Result) const;
			error_code getKind(uint16_t &Result) const;
			DataRefImpl getRawDataRefImpl() const;
			const ObjectFile *getObjectFile() const;
			};
			typedef content_iterator<DiceRef> dice_iterator;
	class MachOObjectFile : public ObjectFile {		class MachOObjectFile : public ObjectFile {
	public:		public:
	struct LoadCommandInfo {		struct LoadCommandInfo {
	const char *Ptr; // Where in memory the load command is.		const char *Ptr; // Where in memory the load command is.
	macho::LoadCommand C; // The command itself.		MachO::load_command C; // The command itself.
	};		};
	MachOObjectFile(MemoryBuffer *Object, bool IsLittleEndian, bool Is64Bits,		MachOObjectFile(MemoryBuffer *Object, bool IsLittleEndian, bool Is64Bits,
	error_code &ec);		error_code &ec);
	virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const;		virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const;
	virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const;		virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const;
	virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) cons t;		virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) cons t;
	virtual error_code getSymbolFileOffset(DataRefImpl Symb, uint64_t &Res) c onst;		virtual error_code getSymbolFileOffset(DataRefImpl Symb, uint64_t &Res) c onst;
	virtual error_code getSymbolAlignment(DataRefImpl Symb, uint32_t &Res) co nst;		virtual error_code getSymbolAlignment(DataRefImpl Symb, uint32_t &Res) co nst;
	virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const;		virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const;
	virtual error_code getSymbolType(DataRefImpl Symb,		virtual error_code getSymbolType(DataRefImpl Symb,
	SymbolRef::Type &Res) const;		SymbolRef::Type &Res) const;
	virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const ;
	virtual error_code getSymbolFlags(DataRefImpl Symb, uint32_t &Res) const;		virtual error_code getSymbolFlags(DataRefImpl Symb, uint32_t &Res) const;
	virtual error_code getSymbolSection(DataRefImpl Symb,		virtual error_code getSymbolSection(DataRefImpl Symb,
	section_iterator &Res) const;		section_iterator &Res) const;
	virtual error_code getSymbolValue(DataRefImpl Symb, uint64_t &Val) const;		virtual error_code getSymbolValue(DataRefImpl Symb, uint64_t &Val) const;
	virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const ;		virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const ;
	virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const;		virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const;
	virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) cons t;		virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) cons t;
	virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const;		virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const;
	virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res) co nst;		virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res) co nst;
	skipping to change at line 68		skipping to change at line 91
	virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const;		virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const;
	virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const;		virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const;
	virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const;		virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const;
	virtual error_code isSectionRequiredForExecution(DataRefImpl Sec,		virtual error_code isSectionRequiredForExecution(DataRefImpl Sec,
	bool &Res) const;		bool &Res) const;
	virtual error_code isSectionVirtual(DataRefImpl Sec, bool &Res) const;		virtual error_code isSectionVirtual(DataRefImpl Sec, bool &Res) const;
	virtual error_code isSectionZeroInit(DataRefImpl Sec, bool &Res) const;		virtual error_code isSectionZeroInit(DataRefImpl Sec, bool &Res) const;
	virtual error_code isSectionReadOnlyData(DataRefImpl Sec, bool &Res) cons t;		virtual error_code isSectionReadOnlyData(DataRefImpl Sec, bool &Res) cons t;
	virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Sym b,		virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Sym b,
	bool &Result) const;		bool &Result) const;
	virtual relocation_iterator getSectionRelBegin(DataRefImpl Sec) const;		virtual relocation_iterator section_rel_begin(DataRefImpl Sec) const;
	virtual relocation_iterator getSectionRelEnd(DataRefImpl Sec) const;		virtual relocation_iterator section_rel_end(DataRefImpl Sec) const;
	virtual error_code getRelocationNext(DataRefImpl Rel,		virtual error_code getRelocationNext(DataRefImpl Rel,
	RelocationRef &Res) const;		RelocationRef &Res) const;
	virtual error_code getRelocationAddress(DataRefImpl Rel, uint64_t &Res) c onst;		virtual error_code getRelocationAddress(DataRefImpl Rel, uint64_t &Res) c onst;
	virtual error_code getRelocationOffset(DataRefImpl Rel, uint64_t &Res) co nst;		virtual error_code getRelocationOffset(DataRefImpl Rel, uint64_t &Res) co nst;
	virtual error_code getRelocationSymbol(DataRefImpl Rel, SymbolRef &Res) c onst;		virtual symbol_iterator getRelocationSymbol(DataRefImpl Rel) const;
	virtual error_code getRelocationType(DataRefImpl Rel, uint64_t &Res) cons t;		virtual error_code getRelocationType(DataRefImpl Rel, uint64_t &Res) cons t;
	virtual error_code getRelocationTypeName(DataRefImpl Rel,		virtual error_code getRelocationTypeName(DataRefImpl Rel,
	SmallVectorImpl<char> &Result) c onst;		SmallVectorImpl<char> &Result) c onst;
	virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,
	int64_t &Res) const;
	virtual error_code getRelocationValueString(DataRefImpl Rel,		virtual error_code getRelocationValueString(DataRefImpl Rel,
	SmallVectorImpl<char> &Result) c onst;		SmallVectorImpl<char> &Result) c onst;
	virtual error_code getRelocationHidden(DataRefImpl Rel, bool &Result) con st;		virtual error_code getRelocationHidden(DataRefImpl Rel, bool &Result) con st;
	virtual error_code getLibraryNext(DataRefImpl LibData, LibraryRef &Res) c onst;		virtual error_code getLibraryNext(DataRefImpl LibData, LibraryRef &Res) c onst;
	virtual error_code getLibraryPath(DataRefImpl LibData, StringRef &Res) co nst;		virtual error_code getLibraryPath(DataRefImpl LibData, StringRef &Res) co nst;
	// TODO: Would be useful to have an iterator based version		// TODO: Would be useful to have an iterator based version
	// of the load command interface too.		// of the load command interface too.
	skipping to change at line 110		skipping to change at line 131
	virtual library_iterator begin_libraries_needed() const;		virtual library_iterator begin_libraries_needed() const;
	virtual library_iterator end_libraries_needed() const;		virtual library_iterator end_libraries_needed() const;
	virtual uint8_t getBytesInAddress() const;		virtual uint8_t getBytesInAddress() const;
	virtual StringRef getFileFormatName() const;		virtual StringRef getFileFormatName() const;
	virtual unsigned getArch() const;		virtual unsigned getArch() const;
	virtual StringRef getLoadName() const;		virtual StringRef getLoadName() const;
	relocation_iterator getSectionRelBegin(unsigned Index) const;		relocation_iterator section_rel_begin(unsigned Index) const;
	relocation_iterator getSectionRelEnd(unsigned Index) const;		relocation_iterator section_rel_end(unsigned Index) const;
			dice_iterator begin_dices() const;
			dice_iterator end_dices() const;
	// In a MachO file, sections have a segment name. This is used in the .o		// In a MachO file, sections have a segment name. This is used in the .o
	// files. They have a single segment, but this field specifies which segm ent		// files. They have a single segment, but this field specifies which segm ent
	// a section should be put in in the final object.		// a section should be put in in the final object.
	StringRef getSectionFinalSegmentName(DataRefImpl Sec) const;		StringRef getSectionFinalSegmentName(DataRefImpl Sec) const;
	// Names are stored as 16 bytes. These returns the raw 16 bytes without		// Names are stored as 16 bytes. These returns the raw 16 bytes without
	// interpreting them as a C string.		// interpreting them as a C string.
	ArrayRef<char> getSectionRawName(DataRefImpl Sec) const;		ArrayRef<char> getSectionRawName(DataRefImpl Sec) const;
	ArrayRef<char> getSectionRawFinalSegmentName(DataRefImpl Sec) const;		ArrayRef<char> getSectionRawFinalSegmentName(DataRefImpl Sec) const;
	// MachO specific Info about relocations.		// MachO specific Info about relocations.
	bool isRelocationScattered(const macho::RelocationEntry &RE) const;		bool isRelocationScattered(const MachO::any_relocation_info &RE) const;
	unsigned getPlainRelocationSymbolNum(const macho::RelocationEntry &RE) co		unsigned getPlainRelocationSymbolNum(
	nst;		const MachO::any_relocation_info &RE) c
	bool getPlainRelocationExternal(const macho::RelocationEntry &RE) const;		onst;
	bool getScatteredRelocationScattered(const macho::RelocationEntry &RE) co		bool getPlainRelocationExternal(const MachO::any_relocation_info &RE) con
	nst;		st;
	uint32_t getScatteredRelocationValue(const macho::RelocationEntry &RE) co		bool getScatteredRelocationScattered(
	nst;		const MachO::any_relocation_info &RE) c
	unsigned getAnyRelocationAddress(const macho::RelocationEntry &RE) const;		onst;
	unsigned getAnyRelocationPCRel(const macho::RelocationEntry &RE) const;		uint32_t getScatteredRelocationValue(
	unsigned getAnyRelocationLength(const macho::RelocationEntry &RE) const;		const MachO::any_relocation_info &RE) c
	unsigned getAnyRelocationType(const macho::RelocationEntry &RE) const;		onst;
	SectionRef getRelocationSection(const macho::RelocationEntry &RE) const;		unsigned getAnyRelocationAddress(const MachO::any_relocation_info &RE) co
			nst;
			unsigned getAnyRelocationPCRel(const MachO::any_relocation_info &RE) cons
			t;
			unsigned getAnyRelocationLength(const MachO::any_relocation_info &RE) con
			st;
			unsigned getAnyRelocationType(const MachO::any_relocation_info &RE) const
			;
			SectionRef getRelocationSection(const MachO::any_relocation_info &RE) con
			st;
	// Walk load commands.		// Walk load commands.
	LoadCommandInfo getFirstLoadCommandInfo() const;		LoadCommandInfo getFirstLoadCommandInfo() const;
	LoadCommandInfo getNextLoadCommandInfo(const LoadCommandInfo &L) const;		LoadCommandInfo getNextLoadCommandInfo(const LoadCommandInfo &L) const;
	// MachO specific structures.		// MachO specific structures.
	macho::Section getSection(DataRefImpl DRI) const;		MachO::section getSection(DataRefImpl DRI) const;
	macho::Section64 getSection64(DataRefImpl DRI) const;		MachO::section_64 getSection64(DataRefImpl DRI) const;
	macho::Section getSection(const LoadCommandInfo &L, unsigned Index) const		MachO::section getSection(const LoadCommandInfo &L, unsigned Index) const
	;		;
	macho::Section64 getSection64(const LoadCommandInfo &L, unsigned Index) c		MachO::section_64 getSection64(const LoadCommandInfo &L,unsigned Index) c
	onst;		onst;
	macho::SymbolTableEntry getSymbolTableEntry(DataRefImpl DRI) const;		MachO::nlist getSymbolTableEntry(DataRefImpl DRI) const;
	macho::Symbol64TableEntry getSymbol64TableEntry(DataRefImpl DRI) const;		MachO::nlist_64 getSymbol64TableEntry(DataRefImpl DRI) const;
	macho::LinkeditDataLoadCommand		MachO::linkedit_data_command
	getLinkeditDataLoadCommand(const LoadCommandInfo &L) const;		getLinkeditDataLoadCommand(const LoadCommandInfo &L) const;
	macho::SegmentLoadCommand		MachO::segment_command
	getSegmentLoadCommand(const LoadCommandInfo &L) const;		getSegmentLoadCommand(const LoadCommandInfo &L) const;
	macho::Segment64LoadCommand		MachO::segment_command_64
	getSegment64LoadCommand(const LoadCommandInfo &L) const;		getSegment64LoadCommand(const LoadCommandInfo &L) const;
	macho::LinkerOptionsLoadCommand		MachO::linker_options_command
	getLinkerOptionsLoadCommand(const LoadCommandInfo &L) const;		getLinkerOptionsLoadCommand(const LoadCommandInfo &L) const;
	macho::RelocationEntry getRelocation(DataRefImpl Rel) const;		MachO::any_relocation_info getRelocation(DataRefImpl Rel) const;
	macho::Header getHeader() const;		MachO::data_in_code_entry getDice(DataRefImpl Rel) const;
	macho::Header64Ext getHeader64Ext() const;		MachO::mach_header getHeader() const;
	macho::IndirectSymbolTableEntry		MachO::mach_header_64 getHeader64() const;
	getIndirectSymbolTableEntry(const macho::DysymtabLoadCommand &DLC,		uint32_t
			getIndirectSymbolTableEntry(const MachO::dysymtab_command &DLC,
	unsigned Index) const;		unsigned Index) const;
	macho::DataInCodeTableEntry getDataInCodeTableEntry(uint32_t DataOffset,		MachO::data_in_code_entry getDataInCodeTableEntry(uint32_t DataOffset,
	unsigned Index) const		unsigned Index) const;
	;		MachO::symtab_command getSymtabLoadCommand() const;
	macho::SymtabLoadCommand getSymtabLoadCommand() const;		MachO::dysymtab_command getDysymtabLoadCommand() const;
	macho::DysymtabLoadCommand getDysymtabLoadCommand() const;		MachO::linkedit_data_command getDataInCodeLoadCommand() const;
	StringRef getStringTableData() const;		StringRef getStringTableData() const;
	bool is64Bit() const;		bool is64Bit() const;
	void ReadULEB128s(uint64_t Index, SmallVectorImpl<uint64_t> &Out) const;		void ReadULEB128s(uint64_t Index, SmallVectorImpl<uint64_t> &Out) const;
			static Triple::ArchType getArch(uint32_t CPUType);
	static bool classof(const Binary *v) {		static bool classof(const Binary *v) {
	return v->isMachO();		return v->isMachO();
	}		}
	private:		private:
	typedef SmallVector<const char*, 1> SectionList;		typedef SmallVector<const char*, 1> SectionList;
	SectionList Sections;		SectionList Sections;
	const char *SymtabLoadCmd;		const char *SymtabLoadCmd;
	const char *DysymtabLoadCmd;		const char *DysymtabLoadCmd;
			const char *DataInCodeLoadCmd;
	};		};
			/// DiceRef
			inline DiceRef::DiceRef(DataRefImpl DiceP, const ObjectFile *Owner)
			: DicePimpl(DiceP) , OwningObject(Owner) {}
			inline bool DiceRef::operator==(const DiceRef &Other) const {
			return DicePimpl == Other.DicePimpl;
			}
			inline bool DiceRef::operator<(const DiceRef &Other) const {
			return DicePimpl < Other.DicePimpl;
			}
			inline error_code DiceRef::getNext(DiceRef &Result) const {
			DataRefImpl Rel = DicePimpl;
			const MachO::data_in_code_entry *P =
			reinterpret_cast<const MachO::data_in_code_entry *>(Rel.p);
			Rel.p = reinterpret_cast<uintptr_t>(P + 1);
			Result = DiceRef(Rel, OwningObject);
			return object_error::success;
			}
			// Since a Mach-O data in code reference, a DiceRef, can only be created wh
			en
			// the OwningObject ObjectFile is a MachOObjectFile a static_cast<> is used
			for
			// the methods that get the values of the fields of the reference.
			inline error_code DiceRef::getOffset(uint32_t &Result) const {
			const MachOObjectFile *MachOOF =
			static_cast<const MachOObjectFile *>(OwningObject);
			MachO::data_in_code_entry Dice = MachOOF->getDice(DicePimpl);
			Result = Dice.offset;
			return object_error::success;
			}
			inline error_code DiceRef::getLength(uint16_t &Result) const {
			const MachOObjectFile *MachOOF =
			static_cast<const MachOObjectFile *>(OwningObject);
			MachO::data_in_code_entry Dice = MachOOF->getDice(DicePimpl);
			Result = Dice.length;
			return object_error::success;
			}
			inline error_code DiceRef::getKind(uint16_t &Result) const {
			const MachOObjectFile *MachOOF =
			static_cast<const MachOObjectFile *>(OwningObject);
			MachO::data_in_code_entry Dice = MachOOF->getDice(DicePimpl);
			Result = Dice.kind;
			return object_error::success;
			}
			inline DataRefImpl DiceRef::getRawDataRefImpl() const {
			return DicePimpl;
			}
			inline const ObjectFile *DiceRef::getObjectFile() const {
			return OwningObject;
			}
	}		}
	}		}
	#endif		#endif
End of changes. 20 change blocks.
	46 lines changed or deleted		142 lines changed or added

	MachineBasicBlock.h		MachineBasicBlock.h
	skipping to change at line 296		skipping to change at line 296
	return (unsigned)Successors.size();		return (unsigned)Successors.size();
	}		}
	bool succ_empty() const { return Successors.empty(); }		bool succ_empty() const { return Successors.empty(); }
	// LiveIn management methods.		// LiveIn management methods.
	/// addLiveIn - Add the specified register as a live in. Note that it		/// addLiveIn - Add the specified register as a live in. Note that it
	/// is an error to add the same register to the same set more than once.		/// is an error to add the same register to the same set more than once.
	void addLiveIn(unsigned Reg) { LiveIns.push_back(Reg); }		void addLiveIn(unsigned Reg) { LiveIns.push_back(Reg); }
			/// Add PhysReg as live in to this block, and ensure that there is a copy
			of
			/// PhysReg to a virtual register of class RC. Return the virtual registe
			r
			/// that is a copy of the live in PhysReg.
			unsigned addLiveIn(unsigned PhysReg, const TargetRegisterClass *RC);
	/// removeLiveIn - Remove the specified register from the live in set.		/// removeLiveIn - Remove the specified register from the live in set.
	///		///
	void removeLiveIn(unsigned Reg);		void removeLiveIn(unsigned Reg);
	/// isLiveIn - Return true if the specified register is in the live in se t.		/// isLiveIn - Return true if the specified register is in the live in se t.
	///		///
	bool isLiveIn(unsigned Reg) const;		bool isLiveIn(unsigned Reg) const;
	// Iteration support for live in sets. These sets are kept in sorted		// Iteration support for live in sets. These sets are kept in sorted
	// order by their register number.		// order by their register number.
	skipping to change at line 404		skipping to change at line 409
	/// that MBB need not be a successor at all, for example if this block		/// that MBB need not be a successor at all, for example if this block
	/// ends with an unconditional branch to some other block.		/// ends with an unconditional branch to some other block.
	bool isLayoutSuccessor(const MachineBasicBlock *MBB) const;		bool isLayoutSuccessor(const MachineBasicBlock *MBB) const;
	/// canFallThrough - Return true if the block can implicitly transfer		/// canFallThrough - Return true if the block can implicitly transfer
	/// control to the block after it by falling off the end of it. This sho uld		/// control to the block after it by falling off the end of it. This sho uld
	/// return false if it can reach the block after it, but it uses an expli cit		/// return false if it can reach the block after it, but it uses an expli cit
	/// branch to do so (e.g., a table jump). True is a conservative answer.		/// branch to do so (e.g., a table jump). True is a conservative answer.
	bool canFallThrough();		bool canFallThrough();
	/// Returns a pointer to the first instructon in this block that is not a		/// Returns a pointer to the first instruction in this block that is not
	/// PHINode instruction. When adding instruction to the beginning of the		a
			/// PHINode instruction. When adding instructions to the beginning of the
	/// basic block, they should be added before the returned value, not befo re		/// basic block, they should be added before the returned value, not befo re
	/// the first instruction, which might be PHI.		/// the first instruction, which might be PHI.
	/// Returns end() is there's no non-PHI instruction.		/// Returns end() is there's no non-PHI instruction.
	iterator getFirstNonPHI();		iterator getFirstNonPHI();
	/// SkipPHIsAndLabels - Return the first instruction in MBB after I that is		/// SkipPHIsAndLabels - Return the first instruction in MBB after I that is
	/// not a PHI or a label. This is the correct point to insert copies at t he		/// not a PHI or a label. This is the correct point to insert copies at t he
	/// beginning of a basic block.		/// beginning of a basic block.
	iterator SkipPHIsAndLabels(iterator I);		iterator SkipPHIsAndLabels(iterator I);
	skipping to change at line 725		skipping to change at line 730
	return G.Graph;		return G.Graph;
	}		}
	static inline ChildIteratorType child_begin(NodeType *N) {		static inline ChildIteratorType child_begin(NodeType *N) {
	return N->pred_begin();		return N->pred_begin();
	}		}
	static inline ChildIteratorType child_end(NodeType *N) {		static inline ChildIteratorType child_end(NodeType *N) {
	return N->pred_end();		return N->pred_end();
	}		}
	};		};
			/// MachineInstrSpan provides an interface to get an iteration range
			/// containing the instruction it was initialized with, along with all
			/// those instructions inserted prior to or following that instruction
			/// at some point after the MachineInstrSpan is constructed.
			class MachineInstrSpan {
			MachineBasicBlock &MBB;
			MachineBasicBlock::iterator I, B, E;
			public:
			MachineInstrSpan(MachineBasicBlock::iterator I)
			: MBB(*I->getParent()),
			I(I),
			B(I == MBB.begin() ? MBB.end() : llvm::prior(I)),
			E(llvm::next(I)) {}
			MachineBasicBlock::iterator begin() {
			return B == MBB.end() ? MBB.begin() : llvm::next(B);
			}
			MachineBasicBlock::iterator end() { return E; }
			bool empty() { return begin() == end(); }
			MachineBasicBlock::iterator getInitial() { return I; }
			};
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 3 change blocks.
	2 lines changed or deleted		33 lines changed or added

	MachineBranchProbabilityInfo.h		MachineBranchProbabilityInfo.h
	//==- MachineBranchProbabilityInfo.h - Machine Branch Probability Analysis -==//		//=- MachineBranchProbabilityInfo.h - Branch Probability Analysis -*- C++ - *-=//
	//		//
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This pass is used to evaluate branch probabilties on machine basic block s.		// This pass is used to evaluate branch probabilties on machine basic block s.
	//		//
End of changes. 1 change blocks.
	1 lines changed or deleted		1 lines changed or added

	MachineConstantPool.h		MachineConstantPool.h
	skipping to change at line 133		skipping to change at line 133
	/// function which must be spilled to memory. This is used for constants w hich		/// function which must be spilled to memory. This is used for constants w hich
	/// are unable to be used directly as operands to instructions, which typic ally		/// are unable to be used directly as operands to instructions, which typic ally
	/// include floating point and large integer constants.		/// include floating point and large integer constants.
	///		///
	/// Instructions reference the address of these constant pool constants thr ough		/// Instructions reference the address of these constant pool constants thr ough
	/// the use of MO_ConstantPoolIndex values. When emitting assembly or mach ine		/// the use of MO_ConstantPoolIndex values. When emitting assembly or mach ine
	/// code, these virtual address references are converted to refer to the		/// code, these virtual address references are converted to refer to the
	/// address of the function constant pool values.		/// address of the function constant pool values.
	/// @brief The machine constant pool.		/// @brief The machine constant pool.
	class MachineConstantPool {		class MachineConstantPool {
	const DataLayout *TD; ///< The machine's DataLayout.		const TargetMachine &TM; ///< The target machine.
	unsigned PoolAlignment; ///< The alignment for the pool.		unsigned PoolAlignment; ///< The alignment for the pool.
	std::vector<MachineConstantPoolEntry> Constants; ///< The pool of constan ts.		std::vector<MachineConstantPoolEntry> Constants; ///< The pool of constan ts.
	/// MachineConstantPoolValues that use an existing MachineConstantPoolEnt ry.		/// MachineConstantPoolValues that use an existing MachineConstantPoolEnt ry.
	DenseSet<MachineConstantPoolValue*> MachineCPVsSharingEntries;		DenseSet<MachineConstantPoolValue*> MachineCPVsSharingEntries;
			const DataLayout *getDataLayout() const;
	public:		public:
	/// @brief The only constructor.		/// @brief The only constructor.
	explicit MachineConstantPool(const DataLayout *td)		explicit MachineConstantPool(const TargetMachine &TM)
	: TD(td), PoolAlignment(1) {}		: TM(TM), PoolAlignment(1) {}
	~MachineConstantPool();		~MachineConstantPool();
	/// getConstantPoolAlignment - Return the alignment required by		/// getConstantPoolAlignment - Return the alignment required by
	/// the whole constant pool, of which the first element must be aligned.		/// the whole constant pool, of which the first element must be aligned.
	unsigned getConstantPoolAlignment() const { return PoolAlignment; }		unsigned getConstantPoolAlignment() const { return PoolAlignment; }
	/// getConstantPoolIndex - Create a new entry in the constant pool or ret urn		/// getConstantPoolIndex - Create a new entry in the constant pool or ret urn
	/// an existing one. User must specify the minimum required alignment fo r		/// an existing one. User must specify the minimum required alignment fo r
	/// the object.		/// the object.
	unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment);		unsigned getConstantPoolIndex(const Constant *C, unsigned Alignment);
End of changes. 3 change blocks.
	4 lines changed or deleted		6 lines changed or added

	MachineFrameInfo.h		MachineFrameInfo.h
	skipping to change at line 30		skipping to change at line 30
	#include <vector>		#include <vector>
	namespace llvm {		namespace llvm {
	class raw_ostream;		class raw_ostream;
	class DataLayout;		class DataLayout;
	class TargetRegisterClass;		class TargetRegisterClass;
	class Type;		class Type;
	class MachineFunction;		class MachineFunction;
	class MachineBasicBlock;		class MachineBasicBlock;
	class TargetFrameLowering;		class TargetFrameLowering;
			class TargetMachine;
	class BitVector;		class BitVector;
	class Value;		class Value;
	class AllocaInst;		class AllocaInst;
	/// The CalleeSavedInfo class tracks the information need to locate where a		/// The CalleeSavedInfo class tracks the information need to locate where a
	/// callee saved register is in the current frame.		/// callee saved register is in the current frame.
	class CalleeSavedInfo {		class CalleeSavedInfo {
	unsigned Reg;		unsigned Reg;
	int FrameIdx;		int FrameIdx;
	skipping to change at line 122		skipping to change at line 123
	// PreAllocated - If true, the object was mapped into the local frame		// PreAllocated - If true, the object was mapped into the local frame
	// block and doesn't need additional handling for allocation beyond tha t.		// block and doesn't need additional handling for allocation beyond tha t.
	bool PreAllocated;		bool PreAllocated;
	StackObject(uint64_t Sz, unsigned Al, int64_t SP, bool IM,		StackObject(uint64_t Sz, unsigned Al, int64_t SP, bool IM,
	bool isSS, bool NSP, const AllocaInst *Val)		bool isSS, bool NSP, const AllocaInst *Val)
	: SPOffset(SP), Size(Sz), Alignment(Al), isImmutable(IM),		: SPOffset(SP), Size(Sz), Alignment(Al), isImmutable(IM),
	isSpillSlot(isSS), MayNeedSP(NSP), Alloca(Val), PreAllocated(false) {}		isSpillSlot(isSS), MayNeedSP(NSP), Alloca(Val), PreAllocated(false) {}
	};		};
			const TargetMachine &TM;
	/// Objects - The list of stack objects allocated...		/// Objects - The list of stack objects allocated...
	///		///
	std::vector<StackObject> Objects;		std::vector<StackObject> Objects;
	/// NumFixedObjects - This contains the number of fixed objects contained on		/// NumFixedObjects - This contains the number of fixed objects contained on
	/// the stack. Because fixed objects are stored at a negative index in t he		/// the stack. Because fixed objects are stored at a negative index in t he
	/// Objects list, this is also the index to the 0th object in the list.		/// Objects list, this is also the index to the 0th object in the list.
	///		///
	unsigned NumFixedObjects;		unsigned NumFixedObjects;
	skipping to change at line 204		skipping to change at line 207
	/// CSInfo - The prolog/epilog code inserter fills in this vector with ea ch		/// CSInfo - The prolog/epilog code inserter fills in this vector with ea ch
	/// callee saved register saved in the frame. Beyond its use by the prol og/		/// callee saved register saved in the frame. Beyond its use by the prol og/
	/// epilog code inserter, this data used for debug info and exception		/// epilog code inserter, this data used for debug info and exception
	/// handling.		/// handling.
	std::vector<CalleeSavedInfo> CSInfo;		std::vector<CalleeSavedInfo> CSInfo;
	/// CSIValid - Has CSInfo been set yet?		/// CSIValid - Has CSInfo been set yet?
	bool CSIValid;		bool CSIValid;
	/// TargetFrameLowering - Target information about frame layout.
	///
	const TargetFrameLowering &TFI;
	/// LocalFrameObjects - References to frame indices which are mapped		/// LocalFrameObjects - References to frame indices which are mapped
	/// into the local frame allocation block. <FrameIdx, LocalOffset>		/// into the local frame allocation block. <FrameIdx, LocalOffset>
	SmallVector<std::pair<int, int64_t>, 32> LocalFrameObjects;		SmallVector<std::pair<int, int64_t>, 32> LocalFrameObjects;
	/// LocalFrameSize - Size of the pre-allocated local frame block.		/// LocalFrameSize - Size of the pre-allocated local frame block.
	int64_t LocalFrameSize;		int64_t LocalFrameSize;
	/// Required alignment of the local object blob, which is the strictest		/// Required alignment of the local object blob, which is the strictest
	/// alignment of any object in it.		/// alignment of any object in it.
	unsigned LocalFrameMaxAlign;		unsigned LocalFrameMaxAlign;
	/// Whether the local object blob needs to be allocated together. If not,		/// Whether the local object blob needs to be allocated together. If not,
	/// PEI should ignore the isPreAllocated flags on the stack objects and		/// PEI should ignore the isPreAllocated flags on the stack objects and
	/// just allocate them normally.		/// just allocate them normally.
	bool UseLocalStackAllocationBlock;		bool UseLocalStackAllocationBlock;
	/// Whether the "realign-stack" option is on.		/// Whether the "realign-stack" option is on.
	bool RealignOption;		bool RealignOption;
			const TargetFrameLowering *getFrameLowering() const;
	public:		public:
	explicit MachineFrameInfo(const TargetFrameLowering &tfi, bool RealignO		explicit MachineFrameInfo(const TargetMachine &TM, bool RealignOpt)
	pt)		: TM(TM), RealignOption(RealignOpt) {
	: TFI(tfi), RealignOption(RealignOpt) {
	StackSize = NumFixedObjects = OffsetAdjustment = MaxAlignment = 0;		StackSize = NumFixedObjects = OffsetAdjustment = MaxAlignment = 0;
	HasVarSizedObjects = false;		HasVarSizedObjects = false;
	FrameAddressTaken = false;		FrameAddressTaken = false;
	ReturnAddressTaken = false;		ReturnAddressTaken = false;
	AdjustsStack = false;		AdjustsStack = false;
	HasCalls = false;		HasCalls = false;
	StackProtectorIdx = -1;		StackProtectorIdx = -1;
	FunctionContextIdx = -1;		FunctionContextIdx = -1;
	MaxCallFrameSize = 0;		MaxCallFrameSize = 0;
	CSIValid = false;		CSIValid = false;
End of changes. 5 change blocks.
	7 lines changed or deleted		7 lines changed or added

	MachineInstr.h		MachineInstr.h
	skipping to change at line 400		skipping to change at line 400
	}		}
	/// isUnconditionalBranch - Return true if this is a branch which always		/// isUnconditionalBranch - Return true if this is a branch which always
	/// transfers control flow to some other block. The		/// transfers control flow to some other block. The
	/// TargetInstrInfo::AnalyzeBranch method can be used to get more informa tion		/// TargetInstrInfo::AnalyzeBranch method can be used to get more informa tion
	/// about this branch.		/// about this branch.
	bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {		bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
	return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);		return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
	}		}
	// isPredicable - Return true if this instruction has a predicate operand		/// Return true if this instruction has a predicate operand that
	that		/// controls execution. It may be set to 'always', or may be set to othe
	// controls execution. It may be set to 'always', or may be set to other		r
	/// values. There are various methods in TargetInstrInfo that can be us ed to		/// values. There are various methods in TargetInstrInfo that can be us ed to
	/// control and modify the predicate in this instruction.		/// control and modify the predicate in this instruction.
	bool isPredicable(QueryType Type = AllInBundle) const {		bool isPredicable(QueryType Type = AllInBundle) const {
	// If it's a bundle than all bundled instructions must be predicable fo r this		// If it's a bundle than all bundled instructions must be predicable fo r this
	// to return true.		// to return true.
	return hasProperty(MCID::Predicable, Type);		return hasProperty(MCID::Predicable, Type);
	}		}
	/// isCompare - Return true if this instruction is a comparison.		/// isCompare - Return true if this instruction is a comparison.
	bool isCompare(QueryType Type = IgnoreBundle) const {		bool isCompare(QueryType Type = IgnoreBundle) const {
	skipping to change at line 638		skipping to change at line 638
	getOpcode() == TargetOpcode::EH_LABEL ||		getOpcode() == TargetOpcode::EH_LABEL ||
	getOpcode() == TargetOpcode::GC_LABEL;		getOpcode() == TargetOpcode::GC_LABEL;
	}		}
	bool isPrologLabel() const {		bool isPrologLabel() const {
	return getOpcode() == TargetOpcode::PROLOG_LABEL;		return getOpcode() == TargetOpcode::PROLOG_LABEL;
	}		}
	bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }		bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
	bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }		bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
	bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE ; }		bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE ; }
			/// A DBG_VALUE is indirect iff the first operand is a register and
			/// the second operand is an immediate.
			bool isIndirectDebugValue() const {
			return isDebugValue()
			&& getOperand(0).isReg()
			&& getOperand(1).isImm();
			}
	bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }		bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
	bool isKill() const { return getOpcode() == TargetOpcode::KILL; }		bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
	bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_D EF; }		bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_D EF; }
	bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }		bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
	bool isMSInlineAsm() const {		bool isMSInlineAsm() const {
	return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect();		return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect();
	}		}
	bool isStackAligningInlineAsm() const;		bool isStackAligningInlineAsm() const;
	InlineAsm::AsmDialect getInlineAsmDialect() const;		InlineAsm::AsmDialect getInlineAsmDialect() const;
	skipping to change at line 887		skipping to change at line 894
	bool AddIfNotFound = false);		bool AddIfNotFound = false);
	/// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is		/// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is
	/// provided, this includes super-register kills.		/// provided, this includes super-register kills.
	void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);		void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
	/// addRegisterDead - We have determined MI defined a register without a use.		/// addRegisterDead - We have determined MI defined a register without a use.
	/// Look for the operand that defines it and mark it as IsDead. If		/// Look for the operand that defines it and mark it as IsDead. If
	/// AddIfNotFound is true, add a implicit operand if it's not found. Retu rns		/// AddIfNotFound is true, add a implicit operand if it's not found. Retu rns
	/// true if the operand exists / is added.		/// true if the operand exists / is added.
	bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegI nfo,		bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
	bool AddIfNotFound = false);		bool AddIfNotFound = false);
	/// addRegisterDefined - We have determined MI defines a register. Make s ure		/// addRegisterDefined - We have determined MI defines a register. Make s ure
	/// there is an operand defining Reg.		/// there is an operand defining Reg.
	void addRegisterDefined(unsigned IncomingReg,		void addRegisterDefined(unsigned Reg, const TargetRegisterInfo *RegInfo =
	const TargetRegisterInfo *RegInfo = 0);		0);
	/// setPhysRegsDeadExcept - Mark every physreg used by this instruction a s		/// setPhysRegsDeadExcept - Mark every physreg used by this instruction a s
	/// dead except those in the UsedRegs list.		/// dead except those in the UsedRegs list.
	///		///
	/// On instructions with register mask operands, also add implicit-def		/// On instructions with register mask operands, also add implicit-def
	/// operands for all registers in UsedRegs.		/// operands for all registers in UsedRegs.
	void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,		void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
	const TargetRegisterInfo &TRI);		const TargetRegisterInfo &TRI);
	/// isSafeToMove - Return true if it is safe to move this instruction. If		/// isSafeToMove - Return true if it is safe to move this instruction. If
	/// SawStore is set to true, it means that there is a store (or call) bet ween		/// SawStore is set to true, it means that there is a store (or call) bet ween
	/// the instruction's location and its intended destination.		/// the instruction's location and its intended destination.
	bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,		bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
	bool &SawStore) const;		bool &SawStore) const;
	/// isSafeToReMat - Return true if it's safe to rematerialize the specifi
	ed
	/// instruction which defined the specified register instead of copying i
	t.
	bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
	unsigned DstReg) const;
	/// hasOrderedMemoryRef - Return true if this instruction may have an ord ered		/// hasOrderedMemoryRef - Return true if this instruction may have an ord ered
	/// or volatile memory reference, or if the information describing the me mory		/// or volatile memory reference, or if the information describing the me mory
	/// reference is not available. Return false if it is known to have no		/// reference is not available. Return false if it is known to have no
	/// ordered or volatile memory references.		/// ordered or volatile memory references.
	bool hasOrderedMemoryRef() const;		bool hasOrderedMemoryRef() const;
	/// isInvariantLoad - Return true if this instruction is loading from a		/// isInvariantLoad - Return true if this instruction is loading from a
	/// location whose value is invariant across the function. For example,		/// location whose value is invariant across the function. For example,
	/// loading a value from the constant pool or from the argument area of		/// loading a value from the constant pool or from the argument area of
	/// a function if it does not change. This should only return true of *a ll*		/// a function if it does not change. This should only return true of *a ll*
End of changes. 5 change blocks.
	13 lines changed or deleted		13 lines changed or added

	MachineInstrBuilder.h		MachineInstrBuilder.h
	skipping to change at line 337		skipping to change at line 337
	/// instruction at the end of the given MachineBasicBlock, and sets up the first		/// instruction at the end of the given MachineBasicBlock, and sets up the first
	/// operand as a destination virtual register.		/// operand as a destination virtual register.
	///		///
	inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,		inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
	DebugLoc DL,		DebugLoc DL,
	const MCInstrDesc &MCID,		const MCInstrDesc &MCID,
	unsigned DestReg) {		unsigned DestReg) {
	return BuildMI(*BB, BB->end(), DL, MCID, DestReg);		return BuildMI(*BB, BB->end(), DL, MCID, DestReg);
	}		}
			/// BuildMI - This version of the builder builds a DBG_VALUE intrinsic
			/// for either a value in a register or a register-indirect+offset
			/// address. The convention is that a DBG_VALUE is indirect iff the
			/// second operand is an immediate.
			///
			inline MachineInstrBuilder BuildMI(MachineFunction &MF,
			DebugLoc DL,
			const MCInstrDesc &MCID,
			bool IsIndirect,
			unsigned Reg,
			unsigned Offset,
			const MDNode *MD) {
			if (IsIndirect)
			return BuildMI(MF, DL, MCID)
			.addReg(Reg, RegState::Debug)
			.addImm(Offset)
			.addMetadata(MD);
			else {
			assert(Offset == 0 && "A direct address cannot have an offset.");
			return BuildMI(MF, DL, MCID)
			.addReg(Reg, RegState::Debug)
			.addReg(0U, RegState::Debug)
			.addMetadata(MD);
			}
			}
			/// BuildMI - This version of the builder builds a DBG_VALUE intrinsic
			/// for either a value in a register or a register-indirect+offset
			/// address and inserts it at position I.
			///
			inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
			MachineBasicBlock::iterator I,
			DebugLoc DL,
			const MCInstrDesc &MCID,
			bool IsIndirect,
			unsigned Reg,
			unsigned Offset,
			const MDNode *MD) {
			MachineFunction &MF = *BB.getParent();
			MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, Reg, Offset, MD);
			BB.insert(I, MI);
			return MachineInstrBuilder(MF, MI);
			}
	inline unsigned getDefRegState(bool B) {		inline unsigned getDefRegState(bool B) {
	return B ? RegState::Define : 0;		return B ? RegState::Define : 0;
	}		}
	inline unsigned getImplRegState(bool B) {		inline unsigned getImplRegState(bool B) {
	return B ? RegState::Implicit : 0;		return B ? RegState::Implicit : 0;
	}		}
	inline unsigned getKillRegState(bool B) {		inline unsigned getKillRegState(bool B) {
	return B ? RegState::Kill : 0;		return B ? RegState::Kill : 0;
	}		}
	inline unsigned getDeadRegState(bool B) {		inline unsigned getDeadRegState(bool B) {
End of changes. 1 change blocks.
	0 lines changed or deleted		44 lines changed or added

	MachineLocation.h		MachineLocation.h
	skipping to change at line 13		skipping to change at line 13
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// The MachineLocation class is used to represent a simple location in a ma chine		// The MachineLocation class is used to represent a simple location in a ma chine
	// frame. Locations will be one of two forms; a register or an address for med		// frame. Locations will be one of two forms; a register or an address for med
	// from a base address plus an offset. Register indirection can be specifi ed by		// from a base address plus an offset. Register indirection can be specifi ed by
	// explicitly passing an offset to the constructor.		// explicitly passing an offset to the constructor.
	//
	// The MachineMove class is used to represent abstract move operations in t
	he
	// prolog/epilog of a compiled function. A collection of these objects can
	be
	// used by a debug consumer to track the location of values when unwinding
	stack
	// frames.
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_MC_MACHINELOCATION_H		#ifndef LLVM_MC_MACHINELOCATION_H
	#define LLVM_MC_MACHINELOCATION_H		#define LLVM_MC_MACHINELOCATION_H
			#include "llvm/Support/Compiler.h"
			#include "llvm/Support/DataTypes.h"
	namespace llvm {		namespace llvm {
	class MCSymbol;		class MCSymbol;
	class MachineLocation {		class MachineLocation {
	private:		private:
	bool IsRegister; // True if location is a register.		bool IsRegister; // True if location is a register.
	unsigned Register; // gcc/gdb register number.		unsigned Register; // gcc/gdb register number.
	int Offset; // Displacement if not register.		int Offset; // Displacement if not register.
	public:		public:
	enum {		enum LLVM_ENUM_INT_TYPE(uint32_t) {
	// The target register number for an abstract frame pointer. The value is		// The target register number for an abstract frame pointer. The value is
	// an arbitrary value that doesn't collide with any real target registe r.		// an arbitrary value that doesn't collide with any real target registe r.
	VirtualFP = ~0U		VirtualFP = ~0U
	};		};
	MachineLocation()		MachineLocation()
	: IsRegister(false), Register(0), Offset(0) {}		: IsRegister(false), Register(0), Offset(0) {}
	/// Create a direct register location.		/// Create a direct register location.
	explicit MachineLocation(unsigned R)		explicit MachineLocation(unsigned R)
	: IsRegister(true), Register(R), Offset(0) {}		: IsRegister(true), Register(R), Offset(0) {}
	/// Create a register-indirect location with an offset.		/// Create a register-indirect location with an offset.
	MachineLocation(unsigned R, int O)		MachineLocation(unsigned R, int O)
	: IsRegister(false), Register(R), Offset(O) {}		: IsRegister(false), Register(R), Offset(O) {}
	bool operator==(const MachineLocation &Other) const {		bool operator==(const MachineLocation &Other) const {
	return IsRegister == Other.IsRegister && Register == Other.Register & &		return IsRegister == Other.IsRegister && Register == Other.Register & &
	Offset == Other.Offset;		Offset == Other.Offset;
	}		}
	// Accessors		// Accessors.
			/// \return true iff this is a register-indirect location.
	bool isIndirect() const { return !IsRegister; }		bool isIndirect() const { return !IsRegister; }
	bool isReg() const { return IsRegister; }		bool isReg() const { return IsRegister; }
	unsigned getReg() const { return Register; }		unsigned getReg() const { return Register; }
	int getOffset() const { return Offset; }		int getOffset() const { return Offset; }
	void setIsRegister(bool Is) { IsRegister = Is; }		void setIsRegister(bool Is) { IsRegister = Is; }
	void setRegister(unsigned R) { Register = R; }		void setRegister(unsigned R) { Register = R; }
	void setOffset(int O) { Offset = O; }		void setOffset(int O) { Offset = O; }
	/// Make this location a direct register location.		/// Make this location a direct register location.
	void set(unsigned R) {		void set(unsigned R) {
	IsRegister = true;		IsRegister = true;
	skipping to change at line 76		skipping to change at line 75
	void set(unsigned R, int O) {		void set(unsigned R, int O) {
	IsRegister = false;		IsRegister = false;
	Register = R;		Register = R;
	Offset = O;		Offset = O;
	}		}
	#ifndef NDEBUG		#ifndef NDEBUG
	void dump();		void dump();
	#endif		#endif
	};		};
	/// MachineMove - This class represents the save or restore of a callee sav
	ed
	/// register that exception or debug info needs to know about.
	class MachineMove {
	private:
	/// Label - Symbol for post-instruction address when result of move takes
	/// effect.
	MCSymbol *Label;
	// Move to & from location.
	MachineLocation Destination, Source;
	public:
	MachineMove() : Label(0) {}
	MachineMove(MCSymbol *label, const MachineLocation &D,
	const MachineLocation &S)
	: Label(label), Destination(D), Source(S) {}
	// Accessors
	MCSymbol *getLabel() const { return Label; }
	const MachineLocation &getDestination() const { return Destination; }
	const MachineLocation &getSource() const { return Source; }
	};
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 5 change blocks.
	35 lines changed or deleted		6 lines changed or added

	MachineModuleInfo.h		MachineModuleInfo.h
	skipping to change at line 109		skipping to change at line 109
	MCContext Context;		MCContext Context;
	/// TheModule - This is the LLVM Module being worked on.		/// TheModule - This is the LLVM Module being worked on.
	const Module *TheModule;		const Module *TheModule;
	/// ObjFileMMI - This is the object-file-format-specific implementation o f		/// ObjFileMMI - This is the object-file-format-specific implementation o f
	/// MachineModuleInfoImpl, which lets targets accumulate whatever info th ey		/// MachineModuleInfoImpl, which lets targets accumulate whatever info th ey
	/// want.		/// want.
	MachineModuleInfoImpl *ObjFileMMI;		MachineModuleInfoImpl *ObjFileMMI;
	/// FrameMoves - List of moves done by a function's prolog. Used to cons		/// List of moves done by a function's prolog. Used to construct frame m
	truct		aps
	/// frame maps by debug and exception handling consumers.		/// by debug and exception handling consumers.
	std::vector<MachineMove> FrameMoves;		std::vector<MCCFIInstruction> FrameInstructions;
	/// CompactUnwindEncoding - If the target supports it, this is the compac t		/// CompactUnwindEncoding - If the target supports it, this is the compac t
	/// unwind encoding. It replaces a function's CIE and FDE.		/// unwind encoding. It replaces a function's CIE and FDE.
	uint32_t CompactUnwindEncoding;		uint32_t CompactUnwindEncoding;
	/// LandingPads - List of LandingPadInfo describing the landing pad		/// LandingPads - List of LandingPadInfo describing the landing pad
	/// information in the current function.		/// information in the current function.
	std::vector<LandingPadInfo> LandingPads;		std::vector<LandingPadInfo> LandingPads;
	/// LPadToCallSiteMap - Map a landing pad's EH symbol to the call site		/// LPadToCallSiteMap - Map a landing pad's EH symbol to the call site
	skipping to change at line 234		skipping to change at line 234
	void setCallsUnwindInit(bool b) { CallsUnwindInit = b; }		void setCallsUnwindInit(bool b) { CallsUnwindInit = b; }
	bool usesVAFloatArgument() const {		bool usesVAFloatArgument() const {
	return UsesVAFloatArgument;		return UsesVAFloatArgument;
	}		}
	void setUsesVAFloatArgument(bool b) {		void setUsesVAFloatArgument(bool b) {
	UsesVAFloatArgument = b;		UsesVAFloatArgument = b;
	}		}
	/// getFrameMoves - Returns a reference to a list of moves done in the cu rrent		/// \brief Returns a reference to a list of cfi instructions in the curre nt
	/// function's prologue. Used to construct frame maps for debug and exce ption		/// function's prologue. Used to construct frame maps for debug and exce ption
	/// handling comsumers.		/// handling comsumers.
	std::vector<MachineMove> &getFrameMoves() { return FrameMoves; }		const std::vector<MCCFIInstruction> &getFrameInstructions() const {
			return FrameInstructions;
			}
			void addFrameInst(const MCCFIInstruction &Inst) {
			FrameInstructions.push_back(Inst);
			}
	/// getCompactUnwindEncoding - Returns the compact unwind encoding for a		/// getCompactUnwindEncoding - Returns the compact unwind encoding for a
	/// function if the target supports the encoding. This encoding replaces a		/// function if the target supports the encoding. This encoding replaces a
	/// function's CIE and FDE.		/// function's CIE and FDE.
	uint32_t getCompactUnwindEncoding() const { return CompactUnwindEncoding; }		uint32_t getCompactUnwindEncoding() const { return CompactUnwindEncoding; }
	/// setCompactUnwindEncoding - Set the compact unwind encoding for a func tion		/// setCompactUnwindEncoding - Set the compact unwind encoding for a func tion
	/// if the target supports the encoding.		/// if the target supports the encoding.
	void setCompactUnwindEncoding(uint32_t Enc) { CompactUnwindEncoding = Enc ; }		void setCompactUnwindEncoding(uint32_t Enc) { CompactUnwindEncoding = Enc ; }
End of changes. 3 change blocks.
	6 lines changed or deleted		12 lines changed or added

	MachineOperand.h		MachineOperand.h
	skipping to change at line 392		skipping to change at line 392
	assert(isReg() && "Wrong MachineOperand accessor");		assert(isReg() && "Wrong MachineOperand accessor");
	IsInternalRead = Val;		IsInternalRead = Val;
	}		}
	void setIsEarlyClobber(bool Val = true) {		void setIsEarlyClobber(bool Val = true) {
	assert(isReg() && IsDef && "Wrong MachineOperand accessor");		assert(isReg() && IsDef && "Wrong MachineOperand accessor");
	IsEarlyClobber = Val;		IsEarlyClobber = Val;
	}		}
	void setIsDebug(bool Val = true) {		void setIsDebug(bool Val = true) {
	assert(isReg() && IsDef && "Wrong MachineOperand accessor");		assert(isReg() && !IsDef && "Wrong MachineOperand accessor");
	IsDebug = Val;		IsDebug = Val;
	}		}
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	// Accessors for various operand types.		// Accessors for various operand types.
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	int64_t getImm() const {		int64_t getImm() const {
	assert(isImm() && "Wrong MachineOperand accessor");		assert(isImm() && "Wrong MachineOperand accessor");
	return Contents.ImmVal;		return Contents.ImmVal;
	skipping to change at line 565		skipping to change at line 565
	return Op;		return Op;
	}		}
	static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = fa lse,		static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = fa lse,
	bool isKill = false, bool isDead = false,		bool isKill = false, bool isDead = false,
	bool isUndef = false,		bool isUndef = false,
	bool isEarlyClobber = false,		bool isEarlyClobber = false,
	unsigned SubReg = 0,		unsigned SubReg = 0,
	bool isDebug = false,		bool isDebug = false,
	bool isInternalRead = false) {		bool isInternalRead = false) {
			assert(!(isDead && !isDef) && "Dead flag on non-def");
			assert(!(isKill && isDef) && "Kill flag on def");
	MachineOperand Op(MachineOperand::MO_Register);		MachineOperand Op(MachineOperand::MO_Register);
	Op.IsDef = isDef;		Op.IsDef = isDef;
	Op.IsImp = isImp;		Op.IsImp = isImp;
	Op.IsKill = isKill;		Op.IsKill = isKill;
	Op.IsDead = isDead;		Op.IsDead = isDead;
	Op.IsUndef = isUndef;		Op.IsUndef = isUndef;
	Op.IsInternalRead = isInternalRead;		Op.IsInternalRead = isInternalRead;
	Op.IsEarlyClobber = isEarlyClobber;		Op.IsEarlyClobber = isEarlyClobber;
	Op.TiedTo = 0;		Op.TiedTo = 0;
	Op.IsDebug = isDebug;		Op.IsDebug = isDebug;
End of changes. 2 change blocks.
	1 lines changed or deleted		3 lines changed or added

	MachineRegisterInfo.h		MachineRegisterInfo.h
	skipping to change at line 20		skipping to change at line 20
	// This file defines the MachineRegisterInfo class.		// This file defines the MachineRegisterInfo class.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H		#ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
	#define LLVM_CODEGEN_MACHINEREGISTERINFO_H		#define LLVM_CODEGEN_MACHINEREGISTERINFO_H
	#include "llvm/ADT/BitVector.h"		#include "llvm/ADT/BitVector.h"
	#include "llvm/ADT/IndexedMap.h"		#include "llvm/ADT/IndexedMap.h"
	#include "llvm/CodeGen/MachineInstrBundle.h"		#include "llvm/CodeGen/MachineInstrBundle.h"
			#include "llvm/Target/TargetMachine.h"
	#include "llvm/Target/TargetRegisterInfo.h"		#include "llvm/Target/TargetRegisterInfo.h"
	#include <vector>		#include <vector>
	namespace llvm {		namespace llvm {
			class PSetIterator;
	/// MachineRegisterInfo - Keep track of information for virtual and physica l		/// MachineRegisterInfo - Keep track of information for virtual and physica l
	/// registers, including vreg register classes, use/def chains for register s,		/// registers, including vreg register classes, use/def chains for register s,
	/// etc.		/// etc.
	class MachineRegisterInfo {		class MachineRegisterInfo {
	const TargetRegisterInfo *const TRI;		public:
			class Delegate {
			virtual void anchor();
			public:
			virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
			virtual ~Delegate() {}
			};
			private:
			const TargetMachine &TM;
			Delegate *TheDelegate;
	/// IsSSA - True when the machine function is in SSA form and virtual		/// IsSSA - True when the machine function is in SSA form and virtual
	/// registers have a single def.		/// registers have a single def.
	bool IsSSA;		bool IsSSA;
	/// TracksLiveness - True while register liveness is being tracked accura tely.		/// TracksLiveness - True while register liveness is being tracked accura tely.
	/// Basic block live-in lists, kill flags, and implicit defs may not be		/// Basic block live-in lists, kill flags, and implicit defs may not be
	/// accurate when after this flag is cleared.		/// accurate when after this flag is cleared.
	bool TracksLiveness;		bool TracksLiveness;
	skipping to change at line 111		skipping to change at line 124
	/// Keep track of the physical registers that are live in to the function .		/// Keep track of the physical registers that are live in to the function .
	/// Live in values are typically arguments in registers. LiveIn values a re		/// Live in values are typically arguments in registers. LiveIn values a re
	/// allowed to have virtual registers associated with them, stored in the		/// allowed to have virtual registers associated with them, stored in the
	/// second element.		/// second element.
	std::vector<std::pair<unsigned, unsigned> > LiveIns;		std::vector<std::pair<unsigned, unsigned> > LiveIns;
	MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;		MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
	void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;		void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
	public:		public:
	explicit MachineRegisterInfo(const TargetRegisterInfo &TRI);		explicit MachineRegisterInfo(const TargetMachine &TM);
	~MachineRegisterInfo();		~MachineRegisterInfo();
			const TargetRegisterInfo *getTargetRegisterInfo() const {
			return TM.getRegisterInfo();
			}
			void resetDelegate(Delegate *delegate) {
			// Ensure another delegate does not take over unless the current
			// delegate first unattaches itself. If we ever need to multicast
			// notifications, we will need to change to using a list.
			assert(TheDelegate == delegate &&
			"Only the current delegate can perform reset!");
			TheDelegate = 0;
			}
			void setDelegate(Delegate *delegate) {
			assert(delegate && !TheDelegate &&
			"Attempted to set delegate to null, or to change it without "
			"first resetting it!");
			TheDelegate = delegate;
			}
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	// Function State		// Function State
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	// isSSA - Returns true when the machine function is in SSA form. Early		// isSSA - Returns true when the machine function is in SSA form. Early
	// passes require the machine function to be in SSA form where every virt ual		// passes require the machine function to be in SSA form where every virt ual
	// register has a single defining instruction.		// register has a single defining instruction.
	//		//
	// The TwoAddressInstructionPass and PHIElimination passes take the machi ne		// The TwoAddressInstructionPass and PHIElimination passes take the machi ne
	// function out of SSA form when they introduce multiple defs per virtual		// function out of SSA form when they introduce multiple defs per virtual
	skipping to change at line 297		skipping to change at line 331
	#ifndef NDEBUG		#ifndef NDEBUG
	void dumpUses(unsigned RegNo) const;		void dumpUses(unsigned RegNo) const;
	#endif		#endif
	/// isConstantPhysReg - Returns true if PhysReg is unallocatable and cons tant		/// isConstantPhysReg - Returns true if PhysReg is unallocatable and cons tant
	/// throughout the function. It is safe to move instructions that read s uch		/// throughout the function. It is safe to move instructions that read s uch
	/// a physreg.		/// a physreg.
	bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const ;		bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const ;
			/// Get an iterator over the pressure sets affected by the given physical
			or
			/// virtual register. If RegUnit is physical, it must be a register unit
			(from
			/// MCRegUnitIterator).
			PSetIterator getPressureSets(unsigned RegUnit) const;
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	// Virtual Register Info		// Virtual Register Info
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	/// getRegClass - Return the register class of the specified virtual regi ster.		/// getRegClass - Return the register class of the specified virtual regi ster.
	///		///
	const TargetRegisterClass *getRegClass(unsigned Reg) const {		const TargetRegisterClass *getRegClass(unsigned Reg) const {
	return VRegInfo[Reg].first;		return VRegInfo[Reg].first;
	}		}
	skipping to change at line 379		skipping to change at line 418
	/// isPhysRegUsed - Return true if the specified register is used in this		/// isPhysRegUsed - Return true if the specified register is used in this
	/// function. Also check for clobbered aliases and registers clobbered by		/// function. Also check for clobbered aliases and registers clobbered by
	/// function calls with register mask operands.		/// function calls with register mask operands.
	///		///
	/// This only works after register allocation. It is primarily used by		/// This only works after register allocation. It is primarily used by
	/// PrologEpilogInserter to determine which callee-saved registers need		/// PrologEpilogInserter to determine which callee-saved registers need
	/// spilling.		/// spilling.
	bool isPhysRegUsed(unsigned Reg) const {		bool isPhysRegUsed(unsigned Reg) const {
	if (UsedPhysRegMask.test(Reg))		if (UsedPhysRegMask.test(Reg))
	return true;		return true;
	for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)		for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
			Units.isValid(); ++Units)
	if (UsedRegUnits.test(*Units))		if (UsedRegUnits.test(*Units))
	return true;		return true;
	return false;		return false;
	}		}
	/// Mark the specified register unit as used in this function.		/// Mark the specified register unit as used in this function.
	/// This should only be called during and after register allocation.		/// This should only be called during and after register allocation.
	void setRegUnitUsed(unsigned RegUnit) {		void setRegUnitUsed(unsigned RegUnit) {
	UsedRegUnits.set(RegUnit);		UsedRegUnits.set(RegUnit);
	}		}
	/// setPhysRegUsed - Mark the specified register used in this function.		/// setPhysRegUsed - Mark the specified register used in this function.
	/// This should only be called during and after register allocation.		/// This should only be called during and after register allocation.
	void setPhysRegUsed(unsigned Reg) {		void setPhysRegUsed(unsigned Reg) {
	for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)		for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
			Units.isValid(); ++Units)
	UsedRegUnits.set(*Units);		UsedRegUnits.set(*Units);
	}		}
	/// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as use d.		/// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as use d.
	/// This corresponds to the bit mask attached to register mask operands.		/// This corresponds to the bit mask attached to register mask operands.
	void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {		void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
	UsedPhysRegMask.setBitsNotInMask(RegMask);		UsedPhysRegMask.setBitsNotInMask(RegMask);
	}		}
	/// setPhysRegUnused - Mark the specified register unused in this functio n.		/// setPhysRegUnused - Mark the specified register unused in this functio n.
	/// This should only be called during and after register allocation.		/// This should only be called during and after register allocation.
	void setPhysRegUnused(unsigned Reg) {		void setPhysRegUnused(unsigned Reg) {
	UsedPhysRegMask.reset(Reg);		UsedPhysRegMask.reset(Reg);
	for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)		for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
			Units.isValid(); ++Units)
	UsedRegUnits.reset(*Units);		UsedRegUnits.reset(*Units);
	}		}
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	// Reserved Register Info		// Reserved Register Info
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	//		//
	// The set of reserved registers must be invariant during register		// The set of reserved registers must be invariant during register
	// allocation. For example, the target cannot suddenly decide it needs a		// allocation. For example, the target cannot suddenly decide it needs a
	// frame pointer when the register allocator has already used the frame		// frame pointer when the register allocator has already used the frame
	skipping to change at line 467		skipping to change at line 509
	return getReservedRegs().test(PhysReg);		return getReservedRegs().test(PhysReg);
	}		}
	/// isAllocatable - Returns true when PhysReg belongs to an allocatable		/// isAllocatable - Returns true when PhysReg belongs to an allocatable
	/// register class and it hasn't been reserved.		/// register class and it hasn't been reserved.
	///		///
	/// Allocatable registers may show up in the allocation order of some vir tual		/// Allocatable registers may show up in the allocation order of some vir tual
	/// register, so a register allocator needs to track its liveness and		/// register, so a register allocator needs to track its liveness and
	/// availability.		/// availability.
	bool isAllocatable(unsigned PhysReg) const {		bool isAllocatable(unsigned PhysReg) const {
	return TRI->isInAllocatableClass(PhysReg) && !isReserved(PhysReg);		return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
			!isReserved(PhysReg);
	}		}
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	// LiveIn Management		// LiveIn Management
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	/// addLiveIn - Add the specified register as a live-in. Note that it		/// addLiveIn - Add the specified register as a live-in. Note that it
	/// is an error to add the same register to the same set more than once.		/// is an error to add the same register to the same set more than once.
	void addLiveIn(unsigned Reg, unsigned vreg = 0) {		void addLiveIn(unsigned Reg, unsigned vreg = 0) {
	LiveIns.push_back(std::make_pair(Reg, vreg));		LiveIns.push_back(std::make_pair(Reg, vreg));
	skipping to change at line 612		skipping to change at line 655
	MachineInstr &operator*() const {		MachineInstr &operator*() const {
	assert(Op && "Cannot dereference end iterator!");		assert(Op && "Cannot dereference end iterator!");
	return *Op->getParent();		return *Op->getParent();
	}		}
	MachineInstr *operator->() const {		MachineInstr *operator->() const {
	assert(Op && "Cannot dereference end iterator!");		assert(Op && "Cannot dereference end iterator!");
	return Op->getParent();		return Op->getParent();
	}		}
	};		};
			};
			/// Iterate over the pressure sets affected by the given physical or virtua
			l
			/// register. If Reg is physical, it must be a register unit (from
			/// MCRegUnitIterator).
			class PSetIterator {
			const int *PSet;
			unsigned Weight;
			public:
			PSetIterator(): PSet(0), Weight(0) {}
			PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
			const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
			if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
			const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
			PSet = TRI->getRegClassPressureSets(RC);
			Weight = TRI->getRegClassWeight(RC).RegWeight;
			}
			else {
			PSet = TRI->getRegUnitPressureSets(RegUnit);
			Weight = TRI->getRegUnitWeight(RegUnit);
			}
			if (*PSet == -1)
			PSet = 0;
			}
			bool isValid() const { return PSet; }
			unsigned getWeight() const { return Weight; }
			unsigned operator*() const { return *PSet; }
			void operator++() {
			assert(isValid() && "Invalid PSetIterator.");
			++PSet;
			if (*PSet == -1)
			PSet = 0;
			}
	};		};
			inline PSetIterator MachineRegisterInfo::
			getPressureSets(unsigned RegUnit) const {
			return PSetIterator(RegUnit, this);
			}
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 13 change blocks.
	6 lines changed or deleted		92 lines changed or added

	MachineRelocation.h		MachineRelocation.h
	skipping to change at line 60		skipping to change at line 60
	/// Offset - This is the offset from the start of the code buffer of the		/// Offset - This is the offset from the start of the code buffer of the
	/// relocation to perform.		/// relocation to perform.
	uintptr_t Offset;		uintptr_t Offset;
	/// ConstantVal - A field that may be used by the target relocation type.		/// ConstantVal - A field that may be used by the target relocation type.
	intptr_t ConstantVal;		intptr_t ConstantVal;
	union {		union {
	void *Result; // If this has been resolved to a resolved poin ter		void *Result; // If this has been resolved to a resolved poin ter
	GlobalValue *GV; // If this is a pointer to a GV or an indirect ref.		GlobalValue *GV; // If this is a pointer to a GV or an indirect ref.
	MachineBasicBlock *MBB; // If this is a pointer to a LLVM BB		MachineBasicBlock *MBB; // If this is a pointer to an LLVM BB
	const char *ExtSym; // If this is a pointer to a named symbol		const char *ExtSym; // If this is a pointer to a named symbol
	unsigned Index; // Constant pool / jump table index		unsigned Index; // Constant pool / jump table index
	unsigned GOTIndex; // Index in the GOT of this symbol/global		unsigned GOTIndex; // Index in the GOT of this symbol/global
	} Target;		} Target;
	unsigned TargetReloType : 6; // The target relocation ID		unsigned TargetReloType : 6; // The target relocation ID
	AddressType AddrType : 4; // The field of Target to use		AddressType AddrType : 4; // The field of Target to use
	bool MayNeedFarStub : 1; // True if this relocation may require a far -stub		bool MayNeedFarStub : 1; // True if this relocation may require a far -stub
	bool GOTRelative : 1; // Should this relocation be relative to the GOT?		bool GOTRelative : 1; // Should this relocation be relative to the GOT?
	bool TargetResolve : 1; // True if target should resolve the address		bool TargetResolve : 1; // True if target should resolve the address
End of changes. 1 change blocks.
	1 lines changed or deleted		1 lines changed or added

	MachineScheduler.h		MachineScheduler.h
	//==- MachineScheduler.h - MachineInstr Scheduling Pass ----------*- C++ -* -==//		//==- MachineScheduler.h - MachineInstr Scheduling Pass ----------*- C++ -* -==//
	//		//
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This file provides a MachineSchedRegistry for registering alternative ma		// This file provides an interface for customizing the standard MachineSche
	chine		duler
	// schedulers. A Target may provide an alternative scheduler implementation		// pass. Note that the entire pass may be replaced as follows:
	by		//
			// <Target>TargetMachine::createPassConfig(PassManagerBase &PM) {
			// PM.substitutePass(&MachineSchedulerID, &CustomSchedulerPassID);
			// ...}
			//
			// The MachineScheduler pass is only responsible for choosing the regions t
			o be
			// scheduled. Targets can override the DAG builder and scheduler without
			// replacing the pass as follows:
			//
			// ScheduleDAGInstrs *<Target>PassConfig::
			// createMachineScheduler(MachineSchedContext *C) {
			// return new CustomMachineScheduler(C);
			// }
			//
			// The default scheduler, ScheduleDAGMI, builds the DAG and drives list
			// scheduling while updating the instruction stream, register pressure, and
			live
			// intervals. Most targets don't need to override the DAG builder and list
			// schedulier, but subtargets that require custom scheduling heuristics may
			// plugin an alternate MachineSchedStrategy. The strategy is responsible fo
			r
			// selecting the highest priority node from the list:
			//
			// ScheduleDAGInstrs *<Target>PassConfig::
			// createMachineScheduler(MachineSchedContext *C) {
			// return new ScheduleDAGMI(C, CustomStrategy(C));
			// }
			//
			// The DAG builder can also be customized in a sense by adding DAG mutation
			s
			// that will run after DAG building and before list scheduling. DAG mutatio
			ns
			// can adjust dependencies based on target-specific knowledge or add weak e
			dges
			// to aid heuristics:
			//
			// ScheduleDAGInstrs *<Target>PassConfig::
			// createMachineScheduler(MachineSchedContext *C) {
			// ScheduleDAGMI *DAG = new ScheduleDAGMI(C, CustomStrategy(C));
			// DAG->addMutation(new CustomDependencies(DAG->TII, DAG->TRI));
			// return DAG;
			// }
			//
			// A target that supports alternative schedulers can use the
			// MachineSchedRegistry to allow command line selection. This can be done b
			y
	// implementing the following boilerplate:		// implementing the following boilerplate:
	//		//
	// static ScheduleDAGInstrs *createCustomMachineSched(MachineSchedContext * C) {		// static ScheduleDAGInstrs *createCustomMachineSched(MachineSchedContext * C) {
	// return new CustomMachineScheduler(C);		// return new CustomMachineScheduler(C);
	// }		// }
	// static MachineSchedRegistry		// static MachineSchedRegistry
	// SchedCustomRegistry("custom", "Run my target's custom scheduler",		// SchedCustomRegistry("custom", "Run my target's custom scheduler",
	// createCustomMachineSched);		// createCustomMachineSched);
	//		//
	// Inside <Target>PassConfig:		//
	// enablePass(&MachineSchedulerID);		// Finally, subtargets that don't need to implement custom heuristics but w
	// MachineSchedRegistry::setDefault(createCustomMachineSched);		ould
			// like to configure the GenericScheduler's policy for a given scheduler re
			gion,
			// including scheduling direction and register pressure tracking policy, ca
			n do
			// this:
			//
			// void <SubTarget>Subtarget::
			// overrideSchedPolicy(MachineSchedPolicy &Policy,
			// MachineInstr *begin,
			// MachineInstr *end,
			// unsigned NumRegionInstrs) const {
			// Policy.<Flag> = true;
			// }
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_CODEGEN_MACHINESCHEDULER_H		#ifndef LLVM_CODEGEN_MACHINESCHEDULER_H
	#define LLVM_CODEGEN_MACHINESCHEDULER_H		#define LLVM_CODEGEN_MACHINESCHEDULER_H
	#include "llvm/CodeGen/MachinePassRegistry.h"		#include "llvm/CodeGen/MachinePassRegistry.h"
	#include "llvm/CodeGen/RegisterPressure.h"		#include "llvm/CodeGen/RegisterPressure.h"
	#include "llvm/CodeGen/ScheduleDAGInstrs.h"		#include "llvm/CodeGen/ScheduleDAGInstrs.h"
	#include "llvm/Target/TargetInstrInfo.h"
	namespace llvm {		namespace llvm {
	extern cl::opt<bool> ForceTopDown;		extern cl::opt<bool> ForceTopDown;
	extern cl::opt<bool> ForceBottomUp;		extern cl::opt<bool> ForceBottomUp;
	class AliasAnalysis;		class AliasAnalysis;
	class LiveIntervals;		class LiveIntervals;
	class MachineDominatorTree;		class MachineDominatorTree;
	class MachineLoopInfo;		class MachineLoopInfo;
	skipping to change at line 89		skipping to change at line 138
	~MachineSchedRegistry() { Registry.Remove(this); }		~MachineSchedRegistry() { Registry.Remove(this); }
	// Accessors.		// Accessors.
	//		//
	MachineSchedRegistry *getNext() const {		MachineSchedRegistry *getNext() const {
	return (MachineSchedRegistry *)MachinePassRegistryNode::getNext();		return (MachineSchedRegistry *)MachinePassRegistryNode::getNext();
	}		}
	static MachineSchedRegistry *getList() {		static MachineSchedRegistry *getList() {
	return (MachineSchedRegistry *)Registry.getList();		return (MachineSchedRegistry *)Registry.getList();
	}		}
	static ScheduleDAGCtor getDefault() {
	return (ScheduleDAGCtor)Registry.getDefault();
	}
	static void setDefault(ScheduleDAGCtor C) {
	Registry.setDefault((MachinePassCtor)C);
	}
	static void setDefault(StringRef Name) {
	Registry.setDefault(Name);
	}
	static void setListener(MachinePassRegistryListener *L) {		static void setListener(MachinePassRegistryListener *L) {
	Registry.setListener(L);		Registry.setListener(L);
	}		}
	};		};
	class ScheduleDAGMI;		class ScheduleDAGMI;
			/// Define a generic scheduling policy for targets that don't provide their
			own
			/// MachineSchedStrategy. This can be overriden for each scheduling region
			/// before building the DAG.
			struct MachineSchedPolicy {
			// Allow the scheduler to disable register pressure tracking.
			bool ShouldTrackPressure;
			// Allow the scheduler to force top-down or bottom-up scheduling. If neit
			her
			// is true, the scheduler runs in both directions and converges.
			bool OnlyTopDown;
			bool OnlyBottomUp;
			MachineSchedPolicy():
			ShouldTrackPressure(false), OnlyTopDown(false), OnlyBottomUp(false) {}
			};
	/// MachineSchedStrategy - Interface to the scheduling algorithm used by		/// MachineSchedStrategy - Interface to the scheduling algorithm used by
	/// ScheduleDAGMI.		/// ScheduleDAGMI.
			///
			/// Initialization sequence:
			/// initPolicy -> shouldTrackPressure -> initialize(DAG) -> registerRoots
	class MachineSchedStrategy {		class MachineSchedStrategy {
			virtual void anchor();
	public:		public:
	virtual ~MachineSchedStrategy() {}		virtual ~MachineSchedStrategy() {}
			/// Optionally override the per-region scheduling policy.
			virtual void initPolicy(MachineBasicBlock::iterator Begin,
			MachineBasicBlock::iterator End,
			unsigned NumRegionInstrs) {}
			/// Check if pressure tracking is needed before building the DAG and
			/// initializing this strategy. Called after initPolicy.
			virtual bool shouldTrackPressure() const { return true; }
	/// Initialize the strategy after building the DAG for a new region.		/// Initialize the strategy after building the DAG for a new region.
	virtual void initialize(ScheduleDAGMI *DAG) = 0;		virtual void initialize(ScheduleDAGMI *DAG) = 0;
	/// Notify this strategy that all roots have been released (including tho se		/// Notify this strategy that all roots have been released (including tho se
	/// that depend on EntrySU or ExitSU).		/// that depend on EntrySU or ExitSU).
	virtual void registerRoots() {}		virtual void registerRoots() {}
	/// Pick the next node to schedule, or return NULL. Set IsTopNode to true to		/// Pick the next node to schedule, or return NULL. Set IsTopNode to true to
	/// schedule the node at the top of the unscheduled region. Otherwise it will		/// schedule the node at the top of the unscheduled region. Otherwise it will
	/// be scheduled at the bottom.		/// be scheduled at the bottom.
	skipping to change at line 197		skipping to change at line 266
	return Queue.begin() + idx;		return Queue.begin() + idx;
	}		}
	#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)		#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
	void dump();		void dump();
	#endif		#endif
	};		};
	/// Mutate the DAG as a postpass after normal DAG building.		/// Mutate the DAG as a postpass after normal DAG building.
	class ScheduleDAGMutation {		class ScheduleDAGMutation {
			virtual void anchor();
	public:		public:
	virtual ~ScheduleDAGMutation() {}		virtual ~ScheduleDAGMutation() {}
	virtual void apply(ScheduleDAGMI *DAG) = 0;		virtual void apply(ScheduleDAGMI *DAG) = 0;
	};		};
	/// ScheduleDAGMI is an implementation of ScheduleDAGInstrs that schedules		/// ScheduleDAGMI is an implementation of ScheduleDAGInstrs that schedules
	/// machine instructions while updating LiveIntervals and tracking regpress ure.		/// machine instructions while updating LiveIntervals and tracking regpress ure.
	class ScheduleDAGMI : public ScheduleDAGInstrs {		class ScheduleDAGMI : public ScheduleDAGInstrs {
	protected:		protected:
	skipping to change at line 225		skipping to change at line 295
	/// Topo - A topological ordering for SUnits which permits fast IsReachab le		/// Topo - A topological ordering for SUnits which permits fast IsReachab le
	/// and similar queries.		/// and similar queries.
	ScheduleDAGTopologicalSort Topo;		ScheduleDAGTopologicalSort Topo;
	/// Ordered list of DAG postprocessing steps.		/// Ordered list of DAG postprocessing steps.
	std::vector<ScheduleDAGMutation*> Mutations;		std::vector<ScheduleDAGMutation*> Mutations;
	MachineBasicBlock::iterator LiveRegionEnd;		MachineBasicBlock::iterator LiveRegionEnd;
	/// Register pressure in this region computed by buildSchedGraph.		// Map each SU to its summary of pressure changes. This array is updated
			for
			// liveness during bottom-up scheduling. Top-down scheduling may proceed
			but
			// has no affect on the pressure diffs.
			PressureDiffs SUPressureDiffs;
			/// Register pressure in this region computed by initRegPressure.
			bool ShouldTrackPressure;
	IntervalPressure RegPressure;		IntervalPressure RegPressure;
	RegPressureTracker RPTracker;		RegPressureTracker RPTracker;
	/// List of pressure sets that exceed the target's pressure limit before		/// List of pressure sets that exceed the target's pressure limit before
	/// scheduling, listed in increasing set ID order. Each pressure set is p aired		/// scheduling, listed in increasing set ID order. Each pressure set is p aired
	/// with its max pressure in the currently scheduled regions.		/// with its max pressure in the currently scheduled regions.
	std::vector<PressureElement> RegionCriticalPSets;		std::vector<PressureChange> RegionCriticalPSets;
	/// The top of the unscheduled zone.		/// The top of the unscheduled zone.
	MachineBasicBlock::iterator CurrentTop;		MachineBasicBlock::iterator CurrentTop;
	IntervalPressure TopPressure;		IntervalPressure TopPressure;
	RegPressureTracker TopRPTracker;		RegPressureTracker TopRPTracker;
	/// The bottom of the unscheduled zone.		/// The bottom of the unscheduled zone.
	MachineBasicBlock::iterator CurrentBottom;		MachineBasicBlock::iterator CurrentBottom;
	IntervalPressure BotPressure;		IntervalPressure BotPressure;
	RegPressureTracker BotRPTracker;		RegPressureTracker BotRPTracker;
	skipping to change at line 258		skipping to change at line 334
	#ifndef NDEBUG		#ifndef NDEBUG
	/// The number of instructions scheduled so far. Used to cut off the		/// The number of instructions scheduled so far. Used to cut off the
	/// scheduler at the point determined by misched-cutoff.		/// scheduler at the point determined by misched-cutoff.
	unsigned NumInstrsScheduled;		unsigned NumInstrsScheduled;
	#endif		#endif
	public:		public:
	ScheduleDAGMI(MachineSchedContext *C, MachineSchedStrategy *S):		ScheduleDAGMI(MachineSchedContext *C, MachineSchedStrategy *S):
	ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS) ,		ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS) ,
	AA(C->AA), RegClassInfo(C->RegClassInfo), SchedImpl(S), DFSResult(0),		AA(C->AA), RegClassInfo(C->RegClassInfo), SchedImpl(S), DFSResult(0),
	Topo(SUnits, &ExitSU), RPTracker(RegPressure), CurrentTop(),		Topo(SUnits, &ExitSU), ShouldTrackPressure(false),
	TopRPTracker(TopPressure), CurrentBottom(), BotRPTracker(BotPressure),		RPTracker(RegPressure), CurrentTop(), TopRPTracker(TopPressure),
			CurrentBottom(), BotRPTracker(BotPressure),
	NextClusterPred(NULL), NextClusterSucc(NULL) {		NextClusterPred(NULL), NextClusterSucc(NULL) {
	#ifndef NDEBUG		#ifndef NDEBUG
	NumInstrsScheduled = 0;		NumInstrsScheduled = 0;
	#endif		#endif
	}		}
	virtual ~ScheduleDAGMI();		virtual ~ScheduleDAGMI();
			/// \brief Return true if register pressure tracking is enabled.
			bool isTrackingPressure() const { return ShouldTrackPressure; }
	/// Add a postprocessing step to the DAG builder.		/// Add a postprocessing step to the DAG builder.
	/// Mutations are applied in the order that they are added after normal D AG		/// Mutations are applied in the order that they are added after normal D AG
	/// building and before MachineSchedStrategy initialization.		/// building and before MachineSchedStrategy initialization.
	///		///
	/// ScheduleDAGMI takes ownership of the Mutation object.		/// ScheduleDAGMI takes ownership of the Mutation object.
	void addMutation(ScheduleDAGMutation *Mutation) {		void addMutation(ScheduleDAGMutation *Mutation) {
	Mutations.push_back(Mutation);		Mutations.push_back(Mutation);
	}		}
	/// \brief True if an edge can be added from PredSU to SuccSU without cre ating		/// \brief True if an edge can be added from PredSU to SuccSU without cre ating
	skipping to change at line 297		skipping to change at line 377
	MachineBasicBlock::iterator top() const { return CurrentTop; }		MachineBasicBlock::iterator top() const { return CurrentTop; }
	MachineBasicBlock::iterator bottom() const { return CurrentBottom; }		MachineBasicBlock::iterator bottom() const { return CurrentBottom; }
	/// Implement the ScheduleDAGInstrs interface for handling the next sched uling		/// Implement the ScheduleDAGInstrs interface for handling the next sched uling
	/// region. This covers all instructions in a block, while schedule() may only		/// region. This covers all instructions in a block, while schedule() may only
	/// cover a subset.		/// cover a subset.
	void enterRegion(MachineBasicBlock *bb,		void enterRegion(MachineBasicBlock *bb,
	MachineBasicBlock::iterator begin,		MachineBasicBlock::iterator begin,
	MachineBasicBlock::iterator end,		MachineBasicBlock::iterator end,
	unsigned endcount);		unsigned regioninstrs) LLVM_OVERRIDE;
	/// Implement ScheduleDAGInstrs interface for scheduling a sequence of		/// Implement ScheduleDAGInstrs interface for scheduling a sequence of
	/// reorderable instructions.		/// reorderable instructions.
	virtual void schedule();		virtual void schedule();
	/// Change the position of an instruction within the basic block and upda te		/// Change the position of an instruction within the basic block and upda te
	/// live ranges and region boundary iterators.		/// live ranges and region boundary iterators.
	void moveInstruction(MachineInstr *MI, MachineBasicBlock::iterator Insert Pos);		void moveInstruction(MachineInstr *MI, MachineBasicBlock::iterator Insert Pos);
	/// Get current register pressure for the top scheduled instructions.		/// Get current register pressure for the top scheduled instructions.
	const IntervalPressure &getTopPressure() const { return TopPressure; }		const IntervalPressure &getTopPressure() const { return TopPressure; }
	const RegPressureTracker &getTopRPTracker() const { return TopRPTracker; }		const RegPressureTracker &getTopRPTracker() const { return TopRPTracker; }
	/// Get current register pressure for the bottom scheduled instructions.		/// Get current register pressure for the bottom scheduled instructions.
	const IntervalPressure &getBotPressure() const { return BotPressure; }		const IntervalPressure &getBotPressure() const { return BotPressure; }
	const RegPressureTracker &getBotRPTracker() const { return BotRPTracker; }		const RegPressureTracker &getBotRPTracker() const { return BotRPTracker; }
	/// Get register pressure for the entire scheduling region before schedul ing.		/// Get register pressure for the entire scheduling region before schedul ing.
	const IntervalPressure &getRegPressure() const { return RegPressure; }		const IntervalPressure &getRegPressure() const { return RegPressure; }
	const std::vector<PressureElement> &getRegionCriticalPSets() const {		const std::vector<PressureChange> &getRegionCriticalPSets() const {
	return RegionCriticalPSets;		return RegionCriticalPSets;
	}		}
			PressureDiff &getPressureDiff(const SUnit *SU) {
			return SUPressureDiffs[SU->NodeNum];
			}
	const SUnit *getNextClusterPred() const { return NextClusterPred; }		const SUnit *getNextClusterPred() const { return NextClusterPred; }
	const SUnit *getNextClusterSucc() const { return NextClusterSucc; }		const SUnit *getNextClusterSucc() const { return NextClusterSucc; }
	/// Compute a DFSResult after DAG building is complete, and before any		/// Compute a DFSResult after DAG building is complete, and before any
	/// queue comparisons.		/// queue comparisons.
	void computeDFSResult();		void computeDFSResult();
	/// Return a non-null DFS result if the scheduling strategy initialized i t.		/// Return a non-null DFS result if the scheduling strategy initialized i t.
	const SchedDFSResult *getDFSResult() const { return DFSResult; }		const SchedDFSResult *getDFSResult() const { return DFSResult; }
	BitVector &getScheduledTrees() { return ScheduledTrees; }		BitVector &getScheduledTrees() { return ScheduledTrees; }
			/// Compute the cyclic critical path through the DAG.
			unsigned computeCyclicCriticalPath();
	void viewGraph(const Twine &Name, const Twine &Title) LLVM_OVERRIDE;		void viewGraph(const Twine &Name, const Twine &Title) LLVM_OVERRIDE;
	void viewGraph() LLVM_OVERRIDE;		void viewGraph() LLVM_OVERRIDE;
	protected:		protected:
	// Top-Level entry points for the schedule() driver...		// Top-Level entry points for the schedule() driver...
	/// Call ScheduleDAGInstrs::buildSchedGraph with register pressure tracki ng		/// Call ScheduleDAGInstrs::buildSchedGraph with register pressure tracki ng
	/// enabled. This sets up three trackers. RPTracker will cover the entire DAG		/// enabled. This sets up three trackers. RPTracker will cover the entire DAG
	/// region, TopTracker and BottomTracker will be initialized to the top a nd		/// region, TopTracker and BottomTracker will be initialized to the top a nd
	/// bottom of the DAG region without covereing any unscheduled instructio n.		/// bottom of the DAG region without covereing any unscheduled instructio n.
	skipping to change at line 370		skipping to change at line 457
	/// Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues.		/// Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues.
	void placeDebugValues();		void placeDebugValues();
	/// \brief dump the scheduled Sequence.		/// \brief dump the scheduled Sequence.
	void dumpSchedule() const;		void dumpSchedule() const;
	// Lesser helpers...		// Lesser helpers...
	void initRegPressure();		void initRegPressure();
	void updateScheduledPressure(const std::vector<unsigned> &NewMaxPressure)		void updatePressureDiffs(ArrayRef<unsigned> LiveUses);
	;
			void updateScheduledPressure(const SUnit *SU,
			const std::vector<unsigned> &NewMaxPressure)
			;
	bool checkSchedLimit();		bool checkSchedLimit();
	void findRootsAndBiasEdges(SmallVectorImpl<SUnit*> &TopRoots,		void findRootsAndBiasEdges(SmallVectorImpl<SUnit*> &TopRoots,
	SmallVectorImpl<SUnit*> &BotRoots);		SmallVectorImpl<SUnit*> &BotRoots);
	void releaseSucc(SUnit *SU, SDep *SuccEdge);		void releaseSucc(SUnit *SU, SDep *SuccEdge);
	void releaseSuccessors(SUnit *SU);		void releaseSuccessors(SUnit *SU);
	void releasePred(SUnit *SU, SDep *PredEdge);		void releasePred(SUnit *SU, SDep *PredEdge);
	void releasePredecessors(SUnit *SU);		void releasePredecessors(SUnit *SU);
End of changes. 18 change blocks.
	25 lines changed or deleted		128 lines changed or added

	Mangler.h		Mangler.h
	skipping to change at line 20		skipping to change at line 20
	// Unified name mangler for various backends.		// Unified name mangler for various backends.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_TARGET_MANGLER_H		#ifndef LLVM_TARGET_MANGLER_H
	#define LLVM_TARGET_MANGLER_H		#define LLVM_TARGET_MANGLER_H
	#include "llvm/ADT/DenseMap.h"		#include "llvm/ADT/DenseMap.h"
	namespace llvm {		namespace llvm {
	class Twine;
	class GlobalValue;		class GlobalValue;
	template <typename T> class SmallVectorImpl;
	class MCContext;		class MCContext;
	class MCSymbol;		template <typename T> class SmallVectorImpl;
	class DataLayout;		class TargetMachine;
			class Twine;
	class Mangler {		class Mangler {
	public:		public:
	enum ManglerPrefixTy {		enum ManglerPrefixTy {
	Default, ///< Emit default string before each symbol.		Default, ///< Emit default string before each symbol.
	Private, ///< Emit "private" prefix before each symbol.		Private, ///< Emit "private" prefix before each symbol.
	LinkerPrivate ///< Emit "linker private" prefix before each sy mbol.		LinkerPrivate ///< Emit "linker private" prefix before each sy mbol.
	};		};
	private:		private:
	MCContext &Context;		const TargetMachine *TM;
	const DataLayout &TD;
	/// AnonGlobalIDs - We need to give global values the same name every tim e		/// AnonGlobalIDs - We need to give global values the same name every tim e
	/// they are mangled. This keeps track of the number we give to anonymou s		/// they are mangled. This keeps track of the number we give to anonymou s
	/// ones.		/// ones.
	///		///
	DenseMap<const GlobalValue*, unsigned> AnonGlobalIDs;		DenseMap<const GlobalValue*, unsigned> AnonGlobalIDs;
	/// NextAnonGlobalID - This simple counter is used to unique value names.		/// NextAnonGlobalID - This simple counter is used to unique value names.
	///		///
	unsigned NextAnonGlobalID;		unsigned NextAnonGlobalID;
	public:		public:
	Mangler(MCContext &context, const DataLayout &td)		Mangler(const TargetMachine *TM) : TM(TM), NextAnonGlobalID(1) {}
	: Context(context), TD(td), NextAnonGlobalID(1) {}
	/// getSymbol - Return the MCSymbol for the specified global value. This
	/// symbol is the main label that is the address of the global.
	MCSymbol *getSymbol(const GlobalValue *GV);
	/// getNameWithPrefix - Fill OutName with the name of the appropriate pre fix		/// getNameWithPrefix - Fill OutName with the name of the appropriate pre fix
	/// and the specified global variable's name. If the global variable doe sn't		/// and the specified global variable's name. If the global variable doe sn't
	/// have a name, this fills in a unique name for the global.		/// have a name, this fills in a unique name for the global.
	void getNameWithPrefix(SmallVectorImpl<char> &OutName, const GlobalValue *GV,		void getNameWithPrefix(SmallVectorImpl<char> &OutName, const GlobalValue *GV,
	bool isImplicitlyPrivate);		bool isImplicitlyPrivate, bool UseGlobalPrefix = t rue);
	/// getNameWithPrefix - Fill OutName with the name of the appropriate pre fix		/// getNameWithPrefix - Fill OutName with the name of the appropriate pre fix
	/// and the specified name as the global variable name. GVName must not be		/// and the specified name as the global variable name. GVName must not be
	/// empty.		/// empty.
	void getNameWithPrefix(SmallVectorImpl<char> &OutName, const Twine &GVNam e,		void getNameWithPrefix(SmallVectorImpl<char> &OutName, const Twine &GVNam e,
	ManglerPrefixTy PrefixTy = Mangler::Default);		ManglerPrefixTy PrefixTy = Mangler::Default,
			bool UseGlobalPrefix = true);
	};		};
	} // End llvm namespace		} // End llvm namespace
	#endif // LLVM_TARGET_MANGLER_H		#endif // LLVM_TARGET_MANGLER_H
End of changes. 7 change blocks.
	14 lines changed or deleted		9 lines changed or added

	MathExtras.h		MathExtras.h
	skipping to change at line 17		skipping to change at line 17
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This file contains some functions that are useful for math stuff.		// This file contains some functions that are useful for math stuff.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_SUPPORT_MATHEXTRAS_H		#ifndef LLVM_SUPPORT_MATHEXTRAS_H
	#define LLVM_SUPPORT_MATHEXTRAS_H		#define LLVM_SUPPORT_MATHEXTRAS_H
			#include "llvm/Support/Compiler.h"
	#include "llvm/Support/SwapByteOrder.h"		#include "llvm/Support/SwapByteOrder.h"
			#include "llvm/Support/type_traits.h"
			#include <cstring>
	#ifdef _MSC_VER		#ifdef _MSC_VER
	# include <intrin.h>		#include <intrin.h>
			#include <limits>
	#endif		#endif
	namespace llvm {		namespace llvm {
			/// \brief The behavior an operation has on an input of 0.
			enum ZeroBehavior {
			/// \brief The returned value is undefined.
			ZB_Undefined,
			/// \brief The returned value is numeric_limits<T>::max()
			ZB_Max,
			/// \brief The returned value is numeric_limits<T>::digits
			ZB_Width
			};
			/// \brief Count number of 0's from the least significant bit to the most
			/// stopping at the first 1.
			///
			/// Only unsigned integral types are allowed.
			///
			/// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined
			are
			/// valid arguments.
			template <typename T>
			typename enable_if_c<std::numeric_limits<T>::is_integer &&
			!std::numeric_limits<T>::is_signed, std::size_t>::type
			countTrailingZeros(T Val, ZeroBehavior ZB = ZB_Width) {
			(void)ZB;
			if (!Val)
			return std::numeric_limits<T>::digits;
			if (Val & 0x1)
			return 0;
			// Bisection method.
			std::size_t ZeroBits = 0;
			T Shift = std::numeric_limits<T>::digits >> 1;
			T Mask = std::numeric_limits<T>::max() >> Shift;
			while (Shift) {
			if ((Val & Mask) == 0) {
			Val >>= Shift;
			ZeroBits |= Shift;
			}
			Shift >>= 1;
			Mask >>= Shift;
			}
			return ZeroBits;
			}
			// Disable signed.
			template <typename T>
			typename enable_if_c<std::numeric_limits<T>::is_integer &&
			std::numeric_limits<T>::is_signed, std::size_t>::type
			countTrailingZeros(T Val, ZeroBehavior ZB = ZB_Width) LLVM_DELETED_FUNCTION
			;
			#if __GNUC__ >= 4 || _MSC_VER
			template <>
			inline std::size_t countTrailingZeros<uint32_t>(uint32_t Val, ZeroBehavior
			ZB) {
			if (ZB != ZB_Undefined && Val == 0)
			return 32;
			#if __has_builtin(__builtin_ctz) || __GNUC_PREREQ(4, 0)
			return __builtin_ctz(Val);
			#elif _MSC_VER
			unsigned long Index;
			_BitScanForward(&Index, Val);
			return Index;
			#endif
			}
			#if !defined(_MSC_VER) || defined(_M_X64)
			template <>
			inline std::size_t countTrailingZeros<uint64_t>(uint64_t Val, ZeroBehavior
			ZB) {
			if (ZB != ZB_Undefined && Val == 0)
			return 64;
			#if __has_builtin(__builtin_ctzll) || __GNUC_PREREQ(4, 0)
			return __builtin_ctzll(Val);
			#elif _MSC_VER
			unsigned long Index;
			_BitScanForward64(&Index, Val);
			return Index;
			#endif
			}
			#endif
			#endif
			/// \brief Count number of 0's from the most significant bit to the least
			/// stopping at the first 1.
			///
			/// Only unsigned integral types are allowed.
			///
			/// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined
			are
			/// valid arguments.
			template <typename T>
			typename enable_if_c<std::numeric_limits<T>::is_integer &&
			!std::numeric_limits<T>::is_signed, std::size_t>::type
			countLeadingZeros(T Val, ZeroBehavior ZB = ZB_Width) {
			(void)ZB;
			if (!Val)
			return std::numeric_limits<T>::digits;
			// Bisection method.
			std::size_t ZeroBits = 0;
			for (T Shift = std::numeric_limits<T>::digits >> 1; Shift; Shift >>= 1) {
			T Tmp = Val >> Shift;
			if (Tmp)
			Val = Tmp;
			else
			ZeroBits |= Shift;
			}
			return ZeroBits;
			}
			// Disable signed.
			template <typename T>
			typename enable_if_c<std::numeric_limits<T>::is_integer &&
			std::numeric_limits<T>::is_signed, std::size_t>::type
			countLeadingZeros(T Val, ZeroBehavior ZB = ZB_Width) LLVM_DELETED_FUNCTION;
			#if __GNUC__ >= 4 || _MSC_VER
			template <>
			inline std::size_t countLeadingZeros<uint32_t>(uint32_t Val, ZeroBehavior Z
			B) {
			if (ZB != ZB_Undefined && Val == 0)
			return 32;
			#if __has_builtin(__builtin_clz) || __GNUC_PREREQ(4, 0)
			return __builtin_clz(Val);
			#elif _MSC_VER
			unsigned long Index;
			_BitScanReverse(&Index, Val);
			return Index ^ 31;
			#endif
			}
			#if !defined(_MSC_VER) || defined(_M_X64)
			template <>
			inline std::size_t countLeadingZeros<uint64_t>(uint64_t Val, ZeroBehavior Z
			B) {
			if (ZB != ZB_Undefined && Val == 0)
			return 64;
			#if __has_builtin(__builtin_clzll) || __GNUC_PREREQ(4, 0)
			return __builtin_clzll(Val);
			#elif _MSC_VER
			unsigned long Index;
			_BitScanReverse64(&Index, Val);
			return Index ^ 63;
			#endif
			}
			#endif
			#endif
			/// \brief Get the index of the first set bit starting from the least
			/// significant bit.
			///
			/// Only unsigned integral types are allowed.
			///
			/// \param ZB the behavior on an input of 0. Only ZB_Max and ZB_Undefined a
			re
			/// valid arguments.
			template <typename T>
			typename enable_if_c<std::numeric_limits<T>::is_integer &&
			!std::numeric_limits<T>::is_signed, T>::type
			findFirstSet(T Val, ZeroBehavior ZB = ZB_Max) {
			if (ZB == ZB_Max && Val == 0)
			return std::numeric_limits<T>::max();
			return countTrailingZeros(Val, ZB_Undefined);
			}
			// Disable signed.
			template <typename T>
			typename enable_if_c<std::numeric_limits<T>::is_integer &&
			std::numeric_limits<T>::is_signed, T>::type
			findFirstSet(T Val, ZeroBehavior ZB = ZB_Max) LLVM_DELETED_FUNCTION;
			/// \brief Get the index of the last set bit starting from the least
			/// significant bit.
			///
			/// Only unsigned integral types are allowed.
			///
			/// \param ZB the behavior on an input of 0. Only ZB_Max and ZB_Undefined a
			re
			/// valid arguments.
			template <typename T>
			typename enable_if_c<std::numeric_limits<T>::is_integer &&
			!std::numeric_limits<T>::is_signed, T>::type
			findLastSet(T Val, ZeroBehavior ZB = ZB_Max) {
			if (ZB == ZB_Max && Val == 0)
			return std::numeric_limits<T>::max();
			// Use ^ instead of - because both gcc and llvm can remove the associated
			^
			// in the __builtin_clz intrinsic on x86.
			return countLeadingZeros(Val, ZB_Undefined) ^
			(std::numeric_limits<T>::digits - 1);
			}
			// Disable signed.
			template <typename T>
			typename enable_if_c<std::numeric_limits<T>::is_integer &&
			std::numeric_limits<T>::is_signed, T>::type
			findLastSet(T Val, ZeroBehavior ZB = ZB_Max) LLVM_DELETED_FUNCTION;
			/// \brief Macro compressed bit reversal table for 256 bits.
			///
			/// http://graphics.stanford.edu/~seander/bithacks.html#BitReverseTable
			static const unsigned char BitReverseTable256[256] = {
			#define R2(n) n, n + 2 * 64, n + 1 * 64, n + 3 * 64
			#define R4(n) R2(n), R2(n + 2 * 16), R2(n + 1 * 16), R2(n + 3 * 16)
			#define R6(n) R4(n), R4(n + 2 * 4), R4(n + 1 * 4), R4(n + 3 * 4)
			R6(0), R6(2), R6(1), R6(3)
			};
			/// \brief Reverse the bits in \p Val.
			template <typename T>
			T reverseBits(T Val) {
			unsigned char in[sizeof(Val)];
			unsigned char out[sizeof(Val)];
			std::memcpy(in, &Val, sizeof(Val));
			for (unsigned i = 0; i < sizeof(Val); ++i)
			out[(sizeof(Val) - i) - 1] = BitReverseTable256[in[i]];
			std::memcpy(&Val, out, sizeof(Val));
			return Val;
			}
	// NOTE: The following support functions use the _32/_64 extensions instead of		// NOTE: The following support functions use the _32/_64 extensions instead of
	// type overloading so that signed and unsigned integers can be used withou t		// type overloading so that signed and unsigned integers can be used withou t
	// ambiguity.		// ambiguity.
	/// Hi_32 - This function returns the high 32 bits of a 64 bit value.		/// Hi_32 - This function returns the high 32 bits of a 64 bit value.
	inline uint32_t Hi_32(uint64_t Value) {		inline uint32_t Hi_32(uint64_t Value) {
	return static_cast<uint32_t>(Value >> 32);		return static_cast<uint32_t>(Value >> 32);
	}		}
	skipping to change at line 160		skipping to change at line 382
	inline uint32_t ByteSwap_32(uint32_t Value) {		inline uint32_t ByteSwap_32(uint32_t Value) {
	return sys::SwapByteOrder_32(Value);		return sys::SwapByteOrder_32(Value);
	}		}
	/// ByteSwap_64 - This function returns a byte-swapped representation of th e		/// ByteSwap_64 - This function returns a byte-swapped representation of th e
	/// 64-bit argument, Value.		/// 64-bit argument, Value.
	inline uint64_t ByteSwap_64(uint64_t Value) {		inline uint64_t ByteSwap_64(uint64_t Value) {
	return sys::SwapByteOrder_64(Value);		return sys::SwapByteOrder_64(Value);
	}		}
	/// CountLeadingZeros_32 - this function performs the platform optimal form
	of
	/// counting the number of zeros from the most significant bit to the first
	one
	/// bit. Ex. CountLeadingZeros_32(0x00F000FF) == 8.
	/// Returns 32 if the word is zero.
	inline unsigned CountLeadingZeros_32(uint32_t Value) {
	unsigned Count; // result
	#if __GNUC__ >= 4
	// PowerPC is defined for __builtin_clz(0)
	#if !defined(__ppc__) && !defined(__ppc64__)
	if (!Value) return 32;
	#endif
	Count = __builtin_clz(Value);
	#else
	if (!Value) return 32;
	Count = 0;
	// bisection method for count leading zeros
	for (unsigned Shift = 32 >> 1; Shift; Shift >>= 1) {
	uint32_t Tmp = Value >> Shift;
	if (Tmp) {
	Value = Tmp;
	} else {
	Count |= Shift;
	}
	}
	#endif
	return Count;
	}
	/// CountLeadingOnes_32 - this function performs the operation of		/// CountLeadingOnes_32 - this function performs the operation of
	/// counting the number of ones from the most significant bit to the first zero		/// counting the number of ones from the most significant bit to the first zero
	/// bit. Ex. CountLeadingOnes_32(0xFF0FFF00) == 8.		/// bit. Ex. CountLeadingOnes_32(0xFF0FFF00) == 8.
	/// Returns 32 if the word is all ones.		/// Returns 32 if the word is all ones.
	inline unsigned CountLeadingOnes_32(uint32_t Value) {		inline unsigned CountLeadingOnes_32(uint32_t Value) {
	return CountLeadingZeros_32(~Value);		return countLeadingZeros(~Value);
	}
	/// CountLeadingZeros_64 - This function performs the platform optimal form
	/// of counting the number of zeros from the most significant bit to the fi
	rst
	/// one bit (64 bit edition.)
	/// Returns 64 if the word is zero.
	inline unsigned CountLeadingZeros_64(uint64_t Value) {
	unsigned Count; // result
	#if __GNUC__ >= 4
	// PowerPC is defined for __builtin_clzll(0)
	#if !defined(__ppc__) && !defined(__ppc64__)
	if (!Value) return 64;
	#endif
	Count = __builtin_clzll(Value);
	#else
	if (sizeof(long) == sizeof(int64_t)) {
	if (!Value) return 64;
	Count = 0;
	// bisection method for count leading zeros
	for (unsigned Shift = 64 >> 1; Shift; Shift >>= 1) {
	uint64_t Tmp = Value >> Shift;
	if (Tmp) {
	Value = Tmp;
	} else {
	Count |= Shift;
	}
	}
	} else {
	// get hi portion
	uint32_t Hi = Hi_32(Value);
	// if some bits in hi portion
	if (Hi) {
	// leading zeros in hi portion plus all bits in lo portion
	Count = CountLeadingZeros_32(Hi);
	} else {
	// get lo portion
	uint32_t Lo = Lo_32(Value);
	// same as 32 bit value
	Count = CountLeadingZeros_32(Lo)+32;
	}
	}
	#endif
	return Count;
	}		}
	/// CountLeadingOnes_64 - This function performs the operation		/// CountLeadingOnes_64 - This function performs the operation
	/// of counting the number of ones from the most significant bit to the fir st		/// of counting the number of ones from the most significant bit to the fir st
	/// zero bit (64 bit edition.)		/// zero bit (64 bit edition.)
	/// Returns 64 if the word is all ones.		/// Returns 64 if the word is all ones.
	inline unsigned CountLeadingOnes_64(uint64_t Value) {		inline unsigned CountLeadingOnes_64(uint64_t Value) {
	return CountLeadingZeros_64(~Value);		return countLeadingZeros(~Value);
	}
	/// CountTrailingZeros_32 - this function performs the platform optimal for
	m of
	/// counting the number of zeros from the least significant bit to the firs
	t one
	/// bit. Ex. CountTrailingZeros_32(0xFF00FF00) == 8.
	/// Returns 32 if the word is zero.
	inline unsigned CountTrailingZeros_32(uint32_t Value) {
	#if __GNUC__ >= 4
	return Value ? __builtin_ctz(Value) : 32;
	#else
	static const unsigned Mod37BitPosition[] = {
	32, 0, 1, 26, 2, 23, 27, 0, 3, 16, 24, 30, 28, 11, 0, 13,
	4, 7, 17, 0, 25, 22, 31, 15, 29, 10, 12, 6, 0, 21, 14, 9,
	5, 20, 8, 19, 18
	};
	// Replace "-Value" by "1+~Value" in the following commented code to avoi
	d
	// MSVC warning C4146
	// return Mod37BitPosition[(-Value & Value) % 37];
	return Mod37BitPosition[((1 + ~Value) & Value) % 37];
	#endif
	}		}
	/// CountTrailingOnes_32 - this function performs the operation of		/// CountTrailingOnes_32 - this function performs the operation of
	/// counting the number of ones from the least significant bit to the first zero		/// counting the number of ones from the least significant bit to the first zero
	/// bit. Ex. CountTrailingOnes_32(0x00FF00FF) == 8.		/// bit. Ex. CountTrailingOnes_32(0x00FF00FF) == 8.
	/// Returns 32 if the word is all ones.		/// Returns 32 if the word is all ones.
	inline unsigned CountTrailingOnes_32(uint32_t Value) {		inline unsigned CountTrailingOnes_32(uint32_t Value) {
	return CountTrailingZeros_32(~Value);		return countTrailingZeros(~Value);
	}
	/// CountTrailingZeros_64 - This function performs the platform optimal for
	m
	/// of counting the number of zeros from the least significant bit to the f
	irst
	/// one bit (64 bit edition.)
	/// Returns 64 if the word is zero.
	inline unsigned CountTrailingZeros_64(uint64_t Value) {
	#if __GNUC__ >= 4
	return Value ? __builtin_ctzll(Value) : 64;
	#else
	static const unsigned Mod67Position[] = {
	64, 0, 1, 39, 2, 15, 40, 23, 3, 12, 16, 59, 41, 19, 24, 54,
	4, 64, 13, 10, 17, 62, 60, 28, 42, 30, 20, 51, 25, 44, 55,
	47, 5, 32, 65, 38, 14, 22, 11, 58, 18, 53, 63, 9, 61, 27,
	29, 50, 43, 46, 31, 37, 21, 57, 52, 8, 26, 49, 45, 36, 56,
	7, 48, 35, 6, 34, 33, 0
	};
	// Replace "-Value" by "1+~Value" in the following commented code to avoi
	d
	// MSVC warning C4146
	// return Mod67Position[(-Value & Value) % 67];
	return Mod67Position[((1 + ~Value) & Value) % 67];
	#endif
	}		}
	/// CountTrailingOnes_64 - This function performs the operation		/// CountTrailingOnes_64 - This function performs the operation
	/// of counting the number of ones from the least significant bit to the fi rst		/// of counting the number of ones from the least significant bit to the fi rst
	/// zero bit (64 bit edition.)		/// zero bit (64 bit edition.)
	/// Returns 64 if the word is all ones.		/// Returns 64 if the word is all ones.
	inline unsigned CountTrailingOnes_64(uint64_t Value) {		inline unsigned CountTrailingOnes_64(uint64_t Value) {
	return CountTrailingZeros_64(~Value);		return countTrailingZeros(~Value);
	}		}
	/// CountPopulation_32 - this function counts the number of set bits in a v alue.		/// CountPopulation_32 - this function counts the number of set bits in a v alue.
	/// Ex. CountPopulation(0xF000F000) = 8		/// Ex. CountPopulation(0xF000F000) = 8
	/// Returns 0 if the word is zero.		/// Returns 0 if the word is zero.
	inline unsigned CountPopulation_32(uint32_t Value) {		inline unsigned CountPopulation_32(uint32_t Value) {
	#if __GNUC__ >= 4		#if __GNUC__ >= 4
	return __builtin_popcount(Value);		return __builtin_popcount(Value);
	#else		#else
	uint32_t v = Value - ((Value >> 1) & 0x55555555);		uint32_t v = Value - ((Value >> 1) & 0x55555555);
	skipping to change at line 336		skipping to change at line 444
	v = (v & 0x3333333333333333ULL) + ((v >> 2) & 0x3333333333333333ULL);		v = (v & 0x3333333333333333ULL) + ((v >> 2) & 0x3333333333333333ULL);
	v = (v + (v >> 4)) & 0x0F0F0F0F0F0F0F0FULL;		v = (v + (v >> 4)) & 0x0F0F0F0F0F0F0F0FULL;
	return unsigned((uint64_t)(v * 0x0101010101010101ULL) >> 56);		return unsigned((uint64_t)(v * 0x0101010101010101ULL) >> 56);
	#endif		#endif
	}		}
	/// Log2_32 - This function returns the floor log base 2 of the specified v alue,		/// Log2_32 - This function returns the floor log base 2 of the specified v alue,
	/// -1 if the value is zero. (32 bit edition.)		/// -1 if the value is zero. (32 bit edition.)
	/// Ex. Log2_32(32) == 5, Log2_32(1) == 0, Log2_32(0) == -1, Log2_32(6) == 2		/// Ex. Log2_32(32) == 5, Log2_32(1) == 0, Log2_32(0) == -1, Log2_32(6) == 2
	inline unsigned Log2_32(uint32_t Value) {		inline unsigned Log2_32(uint32_t Value) {
	return 31 - CountLeadingZeros_32(Value);		return 31 - countLeadingZeros(Value);
	}		}
	/// Log2_64 - This function returns the floor log base 2 of the specified v alue,		/// Log2_64 - This function returns the floor log base 2 of the specified v alue,
	/// -1 if the value is zero. (64 bit edition.)		/// -1 if the value is zero. (64 bit edition.)
	inline unsigned Log2_64(uint64_t Value) {		inline unsigned Log2_64(uint64_t Value) {
	return 63 - CountLeadingZeros_64(Value);		return 63 - countLeadingZeros(Value);
	}		}
	/// Log2_32_Ceil - This function returns the ceil log base 2 of the specifi ed		/// Log2_32_Ceil - This function returns the ceil log base 2 of the specifi ed
	/// value, 32 if the value is zero. (32 bit edition).		/// value, 32 if the value is zero. (32 bit edition).
	/// Ex. Log2_32_Ceil(32) == 5, Log2_32_Ceil(1) == 0, Log2_32_Ceil(6) == 3		/// Ex. Log2_32_Ceil(32) == 5, Log2_32_Ceil(1) == 0, Log2_32_Ceil(6) == 3
	inline unsigned Log2_32_Ceil(uint32_t Value) {		inline unsigned Log2_32_Ceil(uint32_t Value) {
	return 32-CountLeadingZeros_32(Value-1);		return 32 - countLeadingZeros(Value - 1);
	}		}
	/// Log2_64_Ceil - This function returns the ceil log base 2 of the specifi ed		/// Log2_64_Ceil - This function returns the ceil log base 2 of the specifi ed
	/// value, 64 if the value is zero. (64 bit edition.)		/// value, 64 if the value is zero. (64 bit edition.)
	inline unsigned Log2_64_Ceil(uint64_t Value) {		inline unsigned Log2_64_Ceil(uint64_t Value) {
	return 64-CountLeadingZeros_64(Value-1);		return 64 - countLeadingZeros(Value - 1);
	}		}
	/// GreatestCommonDivisor64 - Return the greatest common divisor of the two		/// GreatestCommonDivisor64 - Return the greatest common divisor of the two
	/// values using Euclid's algorithm.		/// values using Euclid's algorithm.
	inline uint64_t GreatestCommonDivisor64(uint64_t A, uint64_t B) {		inline uint64_t GreatestCommonDivisor64(uint64_t A, uint64_t B) {
	while (B) {		while (B) {
	uint64_t T = B;		uint64_t T = B;
	B = A % B;		B = A % B;
	A = T;		A = T;
	}		}
	skipping to change at line 499		skipping to change at line 607
	template <unsigned B> inline int64_t SignExtend64(uint64_t x) {		template <unsigned B> inline int64_t SignExtend64(uint64_t x) {
	return int64_t(x << (64 - B)) >> (64 - B);		return int64_t(x << (64 - B)) >> (64 - B);
	}		}
	/// \brief Sign extend number in the bottom B bits of X to a 64-bit int.		/// \brief Sign extend number in the bottom B bits of X to a 64-bit int.
	/// Requires 0 < B <= 64.		/// Requires 0 < B <= 64.
	inline int64_t SignExtend64(uint64_t X, unsigned B) {		inline int64_t SignExtend64(uint64_t X, unsigned B) {
	return int64_t(X << (64 - B)) >> (64 - B);		return int64_t(X << (64 - B)) >> (64 - B);
	}		}
			#if defined(_MSC_VER)
			// Visual Studio defines the HUGE_VAL class of macros using purposeful
			// constant arithmetic overflow, which it then warns on when encountered.
			const float huge_valf = std::numeric_limits<float>::infinity();
			#else
			const float huge_valf = HUGE_VALF;
			#endif
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 14 change blocks.
	132 lines changed or deleted		248 lines changed or added

	MemoryBuffer.h		MemoryBuffer.h
	skipping to change at line 17		skipping to change at line 17
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This file defines the MemoryBuffer interface.		// This file defines the MemoryBuffer interface.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_SUPPORT_MEMORYBUFFER_H		#ifndef LLVM_SUPPORT_MEMORYBUFFER_H
	#define LLVM_SUPPORT_MEMORYBUFFER_H		#define LLVM_SUPPORT_MEMORYBUFFER_H
	#include "llvm/ADT/StringRef.h"		#include "llvm/ADT/Twine.h"
	#include "llvm/Support/CBindingWrapping.h"		#include "llvm/Support/CBindingWrapping.h"
	#include "llvm/Support/Compiler.h"		#include "llvm/Support/Compiler.h"
	#include "llvm/Support/DataTypes.h"		#include "llvm/Support/DataTypes.h"
	#include "llvm-c/Core.h"		#include "llvm-c/Core.h"
	namespace llvm {		namespace llvm {
	class error_code;		class error_code;
	template<class T> class OwningPtr;		template<class T> class OwningPtr;
	skipping to change at line 69		skipping to change at line 69
	/// getBufferIdentifier - Return an identifier for this buffer, typically the		/// getBufferIdentifier - Return an identifier for this buffer, typically the
	/// filename it was read from.		/// filename it was read from.
	virtual const char *getBufferIdentifier() const {		virtual const char *getBufferIdentifier() const {
	return "Unknown buffer";		return "Unknown buffer";
	}		}
	/// getFile - Open the specified file as a MemoryBuffer, returning a new		/// getFile - Open the specified file as a MemoryBuffer, returning a new
	/// MemoryBuffer if successful, otherwise returning null. If FileSize is		/// MemoryBuffer if successful, otherwise returning null. If FileSize is
	/// specified, this means that the client knows that the file exists and that		/// specified, this means that the client knows that the file exists and that
	/// it has the specified size.		/// it has the specified size.
	static error_code getFile(StringRef Filename, OwningPtr<MemoryBuffer> &re		static error_code getFile(Twine Filename, OwningPtr<MemoryBuffer> &result
	sult,		,
	int64_t FileSize = -1,
	bool RequiresNullTerminator = true);
	static error_code getFile(const char *Filename,
	OwningPtr<MemoryBuffer> &result,
	int64_t FileSize = -1,		int64_t FileSize = -1,
	bool RequiresNullTerminator = true);		bool RequiresNullTerminator = true);
	/// getOpenFile - Given an already-open file descriptor, read the file an		/// Given an already-open file descriptor, map some slice of it into a
	d		/// MemoryBuffer. The slice is specified by an \p Offset and \p MapSize.
	/// return a MemoryBuffer.		/// Since this is in the middle of a file, the buffer is not null termina
			ted.
			static error_code getOpenFileSlice(int FD, const char *Filename,
			OwningPtr<MemoryBuffer> &Result,
			uint64_t MapSize, int64_t Offset);
			/// Given an already-open file descriptor, read the file and return a
			/// MemoryBuffer.
	static error_code getOpenFile(int FD, const char *Filename,		static error_code getOpenFile(int FD, const char *Filename,
	OwningPtr<MemoryBuffer> &result,		OwningPtr<MemoryBuffer> &Result,
	uint64_t FileSize = -1,		uint64_t FileSize,
	uint64_t MapSize = -1,
	int64_t Offset = 0,
	bool RequiresNullTerminator = true);		bool RequiresNullTerminator = true);
	/// getMemBuffer - Open the specified memory range as a MemoryBuffer. No te		/// getMemBuffer - Open the specified memory range as a MemoryBuffer. No te
	/// that InputData must be null terminated if RequiresNullTerminator is t rue.		/// that InputData must be null terminated if RequiresNullTerminator is t rue.
	static MemoryBuffer *getMemBuffer(StringRef InputData,		static MemoryBuffer *getMemBuffer(StringRef InputData,
	StringRef BufferName = "",		StringRef BufferName = "",
	bool RequiresNullTerminator = true);		bool RequiresNullTerminator = true);
	/// getMemBufferCopy - Open the specified memory range as a MemoryBuffer,		/// getMemBufferCopy - Open the specified memory range as a MemoryBuffer,
	/// copying the contents and taking ownership of it. InputData does not		/// copying the contents and taking ownership of it. InputData does not
	skipping to change at line 121		skipping to change at line 122
	/// getSTDIN - Read all of stdin into a file buffer, and return it.		/// getSTDIN - Read all of stdin into a file buffer, and return it.
	/// If an error occurs, this returns null and sets ec.		/// If an error occurs, this returns null and sets ec.
	static error_code getSTDIN(OwningPtr<MemoryBuffer> &result);		static error_code getSTDIN(OwningPtr<MemoryBuffer> &result);
	/// getFileOrSTDIN - Open the specified file as a MemoryBuffer, or open s tdin		/// getFileOrSTDIN - Open the specified file as a MemoryBuffer, or open s tdin
	/// if the Filename is "-". If an error occurs, this returns null and se ts		/// if the Filename is "-". If an error occurs, this returns null and se ts
	/// ec.		/// ec.
	static error_code getFileOrSTDIN(StringRef Filename,		static error_code getFileOrSTDIN(StringRef Filename,
	OwningPtr<MemoryBuffer> &result,		OwningPtr<MemoryBuffer> &result,
	int64_t FileSize = -1);		int64_t FileSize = -1);
	static error_code getFileOrSTDIN(const char *Filename,
	OwningPtr<MemoryBuffer> &result,
	int64_t FileSize = -1);
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	// Provided for performance analysis.		// Provided for performance analysis.
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	/// The kind of memory backing used to support the MemoryBuffer.		/// The kind of memory backing used to support the MemoryBuffer.
	enum BufferKind {		enum BufferKind {
	MemoryBuffer_Malloc,		MemoryBuffer_Malloc,
	MemoryBuffer_MMap		MemoryBuffer_MMap
	};		};
End of changes. 5 change blocks.
	17 lines changed or deleted		15 lines changed or added

	MemoryBuiltins.h		MemoryBuiltins.h
	skipping to change at line 66		skipping to change at line 66
	/// \brief Tests if a value is a call or invoke to a library function that		/// \brief Tests if a value is a call or invoke to a library function that
	/// allocates memory (either malloc, calloc, or strdup like).		/// allocates memory (either malloc, calloc, or strdup like).
	bool isAllocLikeFn(const Value *V, const TargetLibraryInfo *TLI,		bool isAllocLikeFn(const Value *V, const TargetLibraryInfo *TLI,
	bool LookThroughBitCast = false);		bool LookThroughBitCast = false);
	/// \brief Tests if a value is a call or invoke to a library function that		/// \brief Tests if a value is a call or invoke to a library function that
	/// reallocates memory (such as realloc).		/// reallocates memory (such as realloc).
	bool isReallocLikeFn(const Value *V, const TargetLibraryInfo *TLI,		bool isReallocLikeFn(const Value *V, const TargetLibraryInfo *TLI,
	bool LookThroughBitCast = false);		bool LookThroughBitCast = false);
			/// \brief Tests if a value is a call or invoke to a library function that
			/// allocates memory and never returns null (such as operator new).
			bool isOperatorNewLikeFn(const Value *V, const TargetLibraryInfo *TLI,
			bool LookThroughBitCast = false);
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// malloc Call Utility Functions.		// malloc Call Utility Functions.
	//		//
	/// extractMallocCall - Returns the corresponding CallInst if the instructi on		/// extractMallocCall - Returns the corresponding CallInst if the instructi on
	/// is a malloc call. Since CallInst::CreateMalloc() only creates calls, w e		/// is a malloc call. Since CallInst::CreateMalloc() only creates calls, w e
	/// ignore InvokeInst here.		/// ignore InvokeInst here.
	const CallInst *extractMallocCall(const Value *I, const TargetLibraryInfo * TLI);		const CallInst *extractMallocCall(const Value *I, const TargetLibraryInfo * TLI);
	static inline CallInst *extractMallocCall(Value *I,		static inline CallInst *extractMallocCall(Value *I,
	const TargetLibraryInfo *TLI) {		const TargetLibraryInfo *TLI) {
	return const_cast<CallInst*>(extractMallocCall((const Value*)I, TLI));		return const_cast<CallInst*>(extractMallocCall((const Value*)I, TLI));
	}		}
	/// isArrayMalloc - Returns the corresponding CallInst if the instruction		/// isArrayMalloc - Returns the corresponding CallInst if the instruction
	/// is a call to malloc whose array size can be determined and the array si ze		/// is a call to malloc whose array size can be determined and the array si ze
	/// is not constant 1. Otherwise, return NULL.		/// is not constant 1. Otherwise, return NULL.
	const CallInst *isArrayMalloc(const Value *I, const DataLayout *TD,		const CallInst *isArrayMalloc(const Value *I, const DataLayout *DL,
	const TargetLibraryInfo *TLI);		const TargetLibraryInfo *TLI);
	/// getMallocType - Returns the PointerType resulting from the malloc call.		/// getMallocType - Returns the PointerType resulting from the malloc call.
	/// The PointerType depends on the number of bitcast uses of the malloc cal l:		/// The PointerType depends on the number of bitcast uses of the malloc cal l:
	/// 0: PointerType is the malloc calls' return type.		/// 0: PointerType is the malloc calls' return type.
	/// 1: PointerType is the bitcast's result type.		/// 1: PointerType is the bitcast's result type.
	/// >1: Unique PointerType cannot be determined, return NULL.		/// >1: Unique PointerType cannot be determined, return NULL.
	PointerType *getMallocType(const CallInst *CI, const TargetLibraryInfo *TLI );		PointerType *getMallocType(const CallInst *CI, const TargetLibraryInfo *TLI );
	/// getMallocAllocatedType - Returns the Type allocated by malloc call.		/// getMallocAllocatedType - Returns the Type allocated by malloc call.
	skipping to change at line 104		skipping to change at line 109
	/// 0: PointerType is the malloc calls' return type.		/// 0: PointerType is the malloc calls' return type.
	/// 1: PointerType is the bitcast's result type.		/// 1: PointerType is the bitcast's result type.
	/// >1: Unique PointerType cannot be determined, return NULL.		/// >1: Unique PointerType cannot be determined, return NULL.
	Type *getMallocAllocatedType(const CallInst *CI, const TargetLibraryInfo *T LI);		Type *getMallocAllocatedType(const CallInst *CI, const TargetLibraryInfo *T LI);
	/// getMallocArraySize - Returns the array size of a malloc call. If the		/// getMallocArraySize - Returns the array size of a malloc call. If the
	/// argument passed to malloc is a multiple of the size of the malloced typ e,		/// argument passed to malloc is a multiple of the size of the malloced typ e,
	/// then return that multiple. For non-array mallocs, the multiple is		/// then return that multiple. For non-array mallocs, the multiple is
	/// constant 1. Otherwise, return NULL for mallocs whose array size cannot be		/// constant 1. Otherwise, return NULL for mallocs whose array size cannot be
	/// determined.		/// determined.
	Value *getMallocArraySize(CallInst *CI, const DataLayout *TD,		Value *getMallocArraySize(CallInst *CI, const DataLayout *DL,
	const TargetLibraryInfo *TLI,		const TargetLibraryInfo *TLI,
	bool LookThroughSExt = false);		bool LookThroughSExt = false);
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// calloc Call Utility Functions.		// calloc Call Utility Functions.
	//		//
	/// extractCallocCall - Returns the corresponding CallInst if the instructi on		/// extractCallocCall - Returns the corresponding CallInst if the instructi on
	/// is a calloc call.		/// is a calloc call.
	const CallInst *extractCallocCall(const Value *I, const TargetLibraryInfo * TLI);		const CallInst *extractCallocCall(const Value *I, const TargetLibraryInfo * TLI);
	skipping to change at line 141		skipping to change at line 146
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// Utility functions to compute size of objects.		// Utility functions to compute size of objects.
	//		//
	/// \brief Compute the size of the object pointed by Ptr. Returns true and the		/// \brief Compute the size of the object pointed by Ptr. Returns true and the
	/// object size in Size if successful, and false otherwise. In this context , by		/// object size in Size if successful, and false otherwise. In this context , by
	/// object we mean the region of memory starting at Ptr to the end of the		/// object we mean the region of memory starting at Ptr to the end of the
	/// underlying object pointed to by Ptr.		/// underlying object pointed to by Ptr.
	/// If RoundToAlign is true, then Size is rounded up to the aligment of all ocas,		/// If RoundToAlign is true, then Size is rounded up to the aligment of all ocas,
	/// byval arguments, and global variables.		/// byval arguments, and global variables.
	bool getObjectSize(const Value *Ptr, uint64_t &Size, const DataLayout *TD,		bool getObjectSize(const Value *Ptr, uint64_t &Size, const DataLayout *DL,
	const TargetLibraryInfo *TLI, bool RoundToAlign = false) ;		const TargetLibraryInfo *TLI, bool RoundToAlign = false) ;
	typedef std::pair<APInt, APInt> SizeOffsetType;		typedef std::pair<APInt, APInt> SizeOffsetType;
	/// \brief Evaluate the size and offset of an object ponted by a Value*		/// \brief Evaluate the size and offset of an object pointed to by a Value*
	/// statically. Fails if size or offset are not known at compile time.		/// statically. Fails if size or offset are not known at compile time.
	class ObjectSizeOffsetVisitor		class ObjectSizeOffsetVisitor
	: public InstVisitor<ObjectSizeOffsetVisitor, SizeOffsetType> {		: public InstVisitor<ObjectSizeOffsetVisitor, SizeOffsetType> {
	const DataLayout *TD;		const DataLayout *DL;
	const TargetLibraryInfo *TLI;		const TargetLibraryInfo *TLI;
	bool RoundToAlign;		bool RoundToAlign;
	unsigned IntTyBits;		unsigned IntTyBits;
	APInt Zero;		APInt Zero;
	SmallPtrSet<Instruction *, 8> SeenInsts;		SmallPtrSet<Instruction *, 8> SeenInsts;
	APInt align(APInt Size, uint64_t Align);		APInt align(APInt Size, uint64_t Align);
	SizeOffsetType unknown() {		SizeOffsetType unknown() {
	return std::make_pair(APInt(), APInt());		return std::make_pair(APInt(), APInt());
	}		}
	public:		public:
	ObjectSizeOffsetVisitor(const DataLayout *TD, const TargetLibraryInfo *TL I,		ObjectSizeOffsetVisitor(const DataLayout *DL, const TargetLibraryInfo *TL I,
	LLVMContext &Context, bool RoundToAlign = false);		LLVMContext &Context, bool RoundToAlign = false);
	SizeOffsetType compute(Value *V);		SizeOffsetType compute(Value *V);
	bool knownSize(SizeOffsetType &SizeOffset) {		bool knownSize(SizeOffsetType &SizeOffset) {
	return SizeOffset.first.getBitWidth() > 1;		return SizeOffset.first.getBitWidth() > 1;
	}		}
	bool knownOffset(SizeOffsetType &SizeOffset) {		bool knownOffset(SizeOffsetType &SizeOffset) {
	return SizeOffset.second.getBitWidth() > 1;		return SizeOffset.second.getBitWidth() > 1;
	skipping to change at line 201		skipping to change at line 206
	SizeOffsetType visitIntToPtrInst(IntToPtrInst&);		SizeOffsetType visitIntToPtrInst(IntToPtrInst&);
	SizeOffsetType visitLoadInst(LoadInst &I);		SizeOffsetType visitLoadInst(LoadInst &I);
	SizeOffsetType visitPHINode(PHINode&);		SizeOffsetType visitPHINode(PHINode&);
	SizeOffsetType visitSelectInst(SelectInst &I);		SizeOffsetType visitSelectInst(SelectInst &I);
	SizeOffsetType visitUndefValue(UndefValue&);		SizeOffsetType visitUndefValue(UndefValue&);
	SizeOffsetType visitInstruction(Instruction &I);		SizeOffsetType visitInstruction(Instruction &I);
	};		};
	typedef std::pair<Value*, Value*> SizeOffsetEvalType;		typedef std::pair<Value*, Value*> SizeOffsetEvalType;
	/// \brief Evaluate the size and offset of an object ponted by a Value*.		/// \brief Evaluate the size and offset of an object pointed to by a Value* .
	/// May create code to compute the result at run-time.		/// May create code to compute the result at run-time.
	class ObjectSizeOffsetEvaluator		class ObjectSizeOffsetEvaluator
	: public InstVisitor<ObjectSizeOffsetEvaluator, SizeOffsetEvalType> {		: public InstVisitor<ObjectSizeOffsetEvaluator, SizeOffsetEvalType> {
	typedef IRBuilder<true, TargetFolder> BuilderTy;		typedef IRBuilder<true, TargetFolder> BuilderTy;
	typedef std::pair<WeakVH, WeakVH> WeakEvalType;		typedef std::pair<WeakVH, WeakVH> WeakEvalType;
	typedef DenseMap<const Value*, WeakEvalType> CacheMapTy;		typedef DenseMap<const Value*, WeakEvalType> CacheMapTy;
	typedef SmallPtrSet<const Value*, 8> PtrSetTy;		typedef SmallPtrSet<const Value*, 8> PtrSetTy;
	const DataLayout *TD;		const DataLayout *DL;
	const TargetLibraryInfo *TLI;		const TargetLibraryInfo *TLI;
	LLVMContext &Context;		LLVMContext &Context;
	BuilderTy Builder;		BuilderTy Builder;
	IntegerType *IntTy;		IntegerType *IntTy;
	Value *Zero;		Value *Zero;
	CacheMapTy CacheMap;		CacheMapTy CacheMap;
	PtrSetTy SeenVals;		PtrSetTy SeenVals;
			bool RoundToAlign;
	SizeOffsetEvalType unknown() {		SizeOffsetEvalType unknown() {
	return std::make_pair((Value*)0, (Value*)0);		return std::make_pair((Value*)0, (Value*)0);
	}		}
	SizeOffsetEvalType compute_(Value *V);		SizeOffsetEvalType compute_(Value *V);
	public:		public:
	ObjectSizeOffsetEvaluator(const DataLayout *TD, const TargetLibraryInfo *		ObjectSizeOffsetEvaluator(const DataLayout *DL, const TargetLibraryInfo *
	TLI,		TLI,
	LLVMContext &Context);		LLVMContext &Context, bool RoundToAlign = false
			);
	SizeOffsetEvalType compute(Value *V);		SizeOffsetEvalType compute(Value *V);
	bool knownSize(SizeOffsetEvalType SizeOffset) {		bool knownSize(SizeOffsetEvalType SizeOffset) {
	return SizeOffset.first;		return SizeOffset.first;
	}		}
	bool knownOffset(SizeOffsetEvalType SizeOffset) {		bool knownOffset(SizeOffsetEvalType SizeOffset) {
	return SizeOffset.second;		return SizeOffset.second;
	}		}
End of changes. 11 change blocks.
	11 lines changed or deleted		18 lines changed or added

	MemoryObject.h		MemoryObject.h
	skipping to change at line 45		skipping to change at line 45
	///		///
	/// @result - The size of the region.		/// @result - The size of the region.
	virtual uint64_t getExtent() const = 0;		virtual uint64_t getExtent() const = 0;
	/// readByte - Tries to read a single byte from the region.		/// readByte - Tries to read a single byte from the region.
	///		///
	/// @param address - The address of the byte, in the same space as getBa se().		/// @param address - The address of the byte, in the same space as getBa se().
	/// @param ptr - A pointer to a byte to be filled in. Must be non-N ULL.		/// @param ptr - A pointer to a byte to be filled in. Must be non-N ULL.
	/// @result - 0 if successful; -1 if not. Failure may be due to a		/// @result - 0 if successful; -1 if not. Failure may be due to a
	/// bounds violation or an implementation-specific erro r.		/// bounds violation or an implementation-specific erro r.
	virtual int readByte(uint64_t address, uint8_t* ptr) const = 0;		virtual int readByte(uint64_t address, uint8_t *ptr) const = 0;
	/// readBytes - Tries to read a contiguous range of bytes from the		/// readBytes - Tries to read a contiguous range of bytes from the
	/// region, up to the end of the region.		/// region, up to the end of the region.
	/// You should override this function if there is a qui cker		/// You should override this function if there is a qui cker
	/// way than going back and forth with individual bytes .		/// way than going back and forth with individual bytes .
	///		///
	/// @param address - The address of the first byte, in the same space as		/// @param address - The address of the first byte, in the same space as
	/// getBase().		/// getBase().
	/// @param size - The maximum number of bytes to copy.		/// @param size - The number of bytes to copy.
	/// @param buf - A pointer to a buffer to be filled in. Must be non -NULL		/// @param buf - A pointer to a buffer to be filled in. Must be non -NULL
	/// and large enough to hold size bytes.		/// and large enough to hold size bytes.
	/// @param copied - A pointer to a nunber that is filled in with the nu
	mber
	/// of bytes actually read. May be NULL.
	/// @result - 0 if successful; -1 if not. Failure may be due to a		/// @result - 0 if successful; -1 if not. Failure may be due to a
	/// bounds violation or an implementation-specific erro r.		/// bounds violation or an implementation-specific erro r.
	virtual int readBytes(uint64_t address,		virtual int readBytes(uint64_t address, uint64_t size, uint8_t *buf) cons
	uint64_t size,		t;
	uint8_t* buf,
	uint64_t* copied) const;
	};		};
	}		}
	#endif		#endif
End of changes. 4 change blocks.
	9 lines changed or deleted		4 lines changed or added

	Metadata.h		Metadata.h
	skipping to change at line 25		skipping to change at line 25
	#ifndef LLVM_IR_METADATA_H		#ifndef LLVM_IR_METADATA_H
	#define LLVM_IR_METADATA_H		#define LLVM_IR_METADATA_H
	#include "llvm/ADT/ArrayRef.h"		#include "llvm/ADT/ArrayRef.h"
	#include "llvm/ADT/FoldingSet.h"		#include "llvm/ADT/FoldingSet.h"
	#include "llvm/ADT/ilist_node.h"		#include "llvm/ADT/ilist_node.h"
	#include "llvm/IR/Value.h"		#include "llvm/IR/Value.h"
	namespace llvm {		namespace llvm {
	class Constant;
	class Instruction;
	class LLVMContext;		class LLVMContext;
	class Module;		class Module;
	template <typename T> class SmallVectorImpl;
	template<typename ValueSubClass, typename ItemParentClass>		template<typename ValueSubClass, typename ItemParentClass>
	class SymbolTableListTraits;		class SymbolTableListTraits;
			enum LLVMConstants LLVM_ENUM_INT_TYPE(uint32_t) {
			DEBUG_METADATA_VERSION = 1 // Current debug info version number.
			};
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	/// MDString - a single uniqued string.		/// MDString - a single uniqued string.
	/// These are used to efficiently contain a byte sequence for metadata.		/// These are used to efficiently contain a byte sequence for metadata.
	/// MDString is always unnamed.		/// MDString is always unnamed.
	class MDString : public Value {		class MDString : public Value {
	virtual void anchor();		virtual void anchor();
	MDString(const MDString &) LLVM_DELETED_FUNCTION;		MDString(const MDString &) LLVM_DELETED_FUNCTION;
	explicit MDString(LLVMContext &C);		explicit MDString(LLVMContext &C);
	public:		public:
	skipping to change at line 140		skipping to change at line 141
	static MDNode *getTemporary(LLVMContext &Context, ArrayRef<Value*> Vals);		static MDNode *getTemporary(LLVMContext &Context, ArrayRef<Value*> Vals);
	/// deleteTemporary - Deallocate a node created by getTemporary. The		/// deleteTemporary - Deallocate a node created by getTemporary. The
	/// node must not have any users.		/// node must not have any users.
	static void deleteTemporary(MDNode *N);		static void deleteTemporary(MDNode *N);
	/// replaceOperandWith - Replace a specific operand.		/// replaceOperandWith - Replace a specific operand.
	void replaceOperandWith(unsigned i, Value *NewVal);		void replaceOperandWith(unsigned i, Value *NewVal);
	/// getOperand - Return specified operand.		/// getOperand - Return specified operand.
	Value *getOperand(unsigned i) const;		Value *getOperand(unsigned i) const LLVM_READONLY;
	/// getNumOperands - Return number of MDNode operands.		/// getNumOperands - Return number of MDNode operands.
	unsigned getNumOperands() const { return NumOperands; }		unsigned getNumOperands() const { return NumOperands; }
	/// isFunctionLocal - Return whether MDNode is local to a function.		/// isFunctionLocal - Return whether MDNode is local to a function.
	bool isFunctionLocal() const {		bool isFunctionLocal() const {
	return (getSubclassDataFromValue() & FunctionLocalBit) != 0;		return (getSubclassDataFromValue() & FunctionLocalBit) != 0;
	}		}
	// getFunction - If this metadata is function-local and recursively has a		// getFunction - If this metadata is function-local and recursively has a
	skipping to change at line 165		skipping to change at line 166
	/// Profile - calculate a unique identifier for this MDNode to collapse		/// Profile - calculate a unique identifier for this MDNode to collapse
	/// duplicates		/// duplicates
	void Profile(FoldingSetNodeID &ID) const;		void Profile(FoldingSetNodeID &ID) const;
	/// Methods for support type inquiry through isa, cast, and dyn_cast:		/// Methods for support type inquiry through isa, cast, and dyn_cast:
	static bool classof(const Value *V) {		static bool classof(const Value *V) {
	return V->getValueID() == MDNodeVal;		return V->getValueID() == MDNodeVal;
	}		}
			/// Check whether MDNode is a vtable access.
			bool isTBAAVtableAccess() const;
	/// Methods for metadata merging.		/// Methods for metadata merging.
	static MDNode *getMostGenericTBAA(MDNode *A, MDNode *B);		static MDNode *getMostGenericTBAA(MDNode *A, MDNode *B);
	static MDNode *getMostGenericFPMath(MDNode *A, MDNode *B);		static MDNode *getMostGenericFPMath(MDNode *A, MDNode *B);
	static MDNode *getMostGenericRange(MDNode *A, MDNode *B);		static MDNode *getMostGenericRange(MDNode *A, MDNode *B);
	private:		private:
	// destroy - Delete this node. Only when there are no uses.		// destroy - Delete this node. Only when there are no uses.
	void destroy();		void destroy();
	bool isNotUniqued() const {		bool isNotUniqued() const {
	return (getSubclassDataFromValue() & NotUniquedBit) != 0;		return (getSubclassDataFromValue() & NotUniquedBit) != 0;
End of changes. 5 change blocks.
	4 lines changed or deleted		8 lines changed or added

	Module.h		Module.h
	skipping to change at line 342		skipping to change at line 342
	/// null terminated list of function arguments, which makes it easier for		/// null terminated list of function arguments, which makes it easier for
	/// clients to use.		/// clients to use.
	Constant *getOrInsertFunction(StringRef Name,		Constant *getOrInsertFunction(StringRef Name,
	AttributeSet AttributeList,		AttributeSet AttributeList,
	Type *RetTy, ...) END_WITH_NULL;		Type *RetTy, ...) END_WITH_NULL;
	/// getOrInsertFunction - Same as above, but without the attributes.		/// getOrInsertFunction - Same as above, but without the attributes.
	Constant *getOrInsertFunction(StringRef Name, Type *RetTy, ...)		Constant *getOrInsertFunction(StringRef Name, Type *RetTy, ...)
	END_WITH_NULL;		END_WITH_NULL;
	Constant *getOrInsertTargetIntrinsic(StringRef Name,
	FunctionType *Ty,
	AttributeSet AttributeList);
	/// getFunction - Look up the specified function in the module symbol tab le.		/// getFunction - Look up the specified function in the module symbol tab le.
	/// If it does not exist, return null.		/// If it does not exist, return null.
	Function *getFunction(StringRef Name) const;		Function *getFunction(StringRef Name) const;
	/// @}		/// @}
	/// @name Global Variable Accessors		/// @name Global Variable Accessors
	/// @{		/// @{
	/// getGlobalVariable - Look up the specified global variable in the modu le		/// getGlobalVariable - Look up the specified global variable in the modu le
	/// symbol table. If it does not exist, return null. If AllowInternal is set		/// symbol table. If it does not exist, return null. If AllowInternal is set
	/// to true, this function will return types that have InternalLinkage. B y		/// to true, this function will return types that have InternalLinkage. B y
	/// default, these types are not returned.		/// default, these types are not returned.
	GlobalVariable *getGlobalVariable(StringRef Name,		const GlobalVariable *getGlobalVariable(StringRef Name,
	bool AllowInternal = false) const;		bool AllowInternal = false) const
			{
			return const_cast<Module *>(this)->getGlobalVariable(Name, AllowInterna
			l);
			}
			GlobalVariable *getGlobalVariable(StringRef Name, bool AllowInternal = fa
			lse);
	/// getNamedGlobal - Return the global variable in the module with the		/// getNamedGlobal - Return the global variable in the module with the
	/// specified name, of arbitrary type. This method returns null if a glo bal		/// specified name, of arbitrary type. This method returns null if a glo bal
	/// with the specified name is not found.		/// with the specified name is not found.
	GlobalVariable *getNamedGlobal(StringRef Name) const {		GlobalVariable *getNamedGlobal(StringRef Name) {
	return getGlobalVariable(Name, true);		return getGlobalVariable(Name, true);
	}		}
			const GlobalVariable *getNamedGlobal(StringRef Name) const {
			return const_cast<Module *>(this)->getNamedGlobal(Name);
			}
	/// getOrInsertGlobal - Look up the specified global in the module symbol		/// getOrInsertGlobal - Look up the specified global in the module symbol
	/// table.		/// table.
	/// 1. If it does not exist, add a declaration of the global and return it.		/// 1. If it does not exist, add a declaration of the global and return it.
	/// 2. Else, the global exists but has the wrong type: return the funct ion		/// 2. Else, the global exists but has the wrong type: return the funct ion
	/// with a constantexpr cast to the right type.		/// with a constantexpr cast to the right type.
	/// 3. Finally, if the existing global is the correct declaration, retu rn		/// 3. Finally, if the existing global is the correct declaration, retu rn
	/// the existing global.		/// the existing global.
	Constant *getOrInsertGlobal(StringRef Name, Type *Ty);		Constant *getOrInsertGlobal(StringRef Name, Type *Ty);
	skipping to change at line 390		skipping to change at line 393
	/// getNamedAlias - Return the global alias in the module with the		/// getNamedAlias - Return the global alias in the module with the
	/// specified name, of arbitrary type. This method returns null if a glo bal		/// specified name, of arbitrary type. This method returns null if a glo bal
	/// with the specified name is not found.		/// with the specified name is not found.
	GlobalAlias *getNamedAlias(StringRef Name) const;		GlobalAlias *getNamedAlias(StringRef Name) const;
	/// @}		/// @}
	/// @name Named Metadata Accessors		/// @name Named Metadata Accessors
	/// @{		/// @{
	/// getNamedMetadata - Return the NamedMDNode in the module with the		/// getNamedMetadata - Return the first NamedMDNode in the module with th e
	/// specified name. This method returns null if a NamedMDNode with the		/// specified name. This method returns null if a NamedMDNode with the
	/// specified name is not found.		/// specified name is not found.
	NamedMDNode *getNamedMetadata(const Twine &Name) const;		NamedMDNode *getNamedMetadata(const Twine &Name) const;
	/// getOrInsertNamedMetadata - Return the named MDNode in the module		/// getOrInsertNamedMetadata - Return the named MDNode in the module
	/// with the specified name. This method returns a new NamedMDNode if a		/// with the specified name. This method returns a new NamedMDNode if a
	/// NamedMDNode with the specified name is not found.		/// NamedMDNode with the specified name is not found.
	NamedMDNode *getOrInsertNamedMetadata(StringRef Name);		NamedMDNode *getOrInsertNamedMetadata(StringRef Name);
	/// eraseNamedMetadata - Remove the given NamedMDNode from this module		/// eraseNamedMetadata - Remove the given NamedMDNode from this module
	/// and delete it.		/// and delete it.
	void eraseNamedMetadata(NamedMDNode *NMD);		void eraseNamedMetadata(NamedMDNode *NMD);
	/// @}		/// @}
	/// @name Module Flags Accessors		/// @name Module Flags Accessors
	/// @{		/// @{
	/// getModuleFlagsMetadata - Returns the module flags in the provided vec tor.		/// getModuleFlagsMetadata - Returns the module flags in the provided vec tor.
	void getModuleFlagsMetadata(SmallVectorImpl<ModuleFlagEntry> &Flags) cons t;		void getModuleFlagsMetadata(SmallVectorImpl<ModuleFlagEntry> &Flags) cons t;
			/// Return the corresponding value if Key appears in module flags, otherw
			ise
			/// return null.
			Value *getModuleFlag(StringRef Key) const;
	/// getModuleFlagsMetadata - Returns the NamedMDNode in the module that		/// getModuleFlagsMetadata - Returns the NamedMDNode in the module that
	/// represents module-level flags. This method returns null if there are no		/// represents module-level flags. This method returns null if there are no
	/// module-level flags.		/// module-level flags.
	NamedMDNode *getModuleFlagsMetadata() const;		NamedMDNode *getModuleFlagsMetadata() const;
	/// getOrInsertModuleFlagsMetadata - Returns the NamedMDNode in the modul e		/// getOrInsertModuleFlagsMetadata - Returns the NamedMDNode in the modul e
	/// that represents module-level flags. If module-level flags aren't foun d,		/// that represents module-level flags. If module-level flags aren't foun d,
	/// it creates the named metadata that contains them.		/// it creates the named metadata that contains them.
	NamedMDNode *getOrInsertModuleFlagsMetadata();		NamedMDNode *getOrInsertModuleFlagsMetadata();
End of changes. 6 change blocks.
	8 lines changed or deleted		19 lines changed or added

	ModuleUtils.h		ModuleUtils.h
	skipping to change at line 21		skipping to change at line 21
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_TRANSFORMS_UTILS_MODULEUTILS_H		#ifndef LLVM_TRANSFORMS_UTILS_MODULEUTILS_H
	#define LLVM_TRANSFORMS_UTILS_MODULEUTILS_H		#define LLVM_TRANSFORMS_UTILS_MODULEUTILS_H
	namespace llvm {		namespace llvm {
	class Module;		class Module;
	class Function;		class Function;
			class GlobalValue;
			class GlobalVariable;
			template <class PtrType, unsigned SmallSize> class SmallPtrSet;
	/// Append F to the list of global ctors of module M with the given Priorit y.		/// Append F to the list of global ctors of module M with the given Priorit y.
	/// This wraps the function in the appropriate structure and stores it alon g		/// This wraps the function in the appropriate structure and stores it alon g
	/// side other global constructors. For details see		/// side other global constructors. For details see
	/// http://llvm.org/docs/LangRef.html#intg_global_ctors		/// http://llvm.org/docs/LangRef.html#intg_global_ctors
	void appendToGlobalCtors(Module &M, Function *F, int Priority);		void appendToGlobalCtors(Module &M, Function *F, int Priority);
	/// Same as appendToGlobalCtors(), but for global dtors.		/// Same as appendToGlobalCtors(), but for global dtors.
	void appendToGlobalDtors(Module &M, Function *F, int Priority);		void appendToGlobalDtors(Module &M, Function *F, int Priority);
			/// \brief Given "llvm.used" or "llvm.compiler.used" as a global name, coll
			ect
			/// the initializer elements of that global in Set and return the global it
			self.
			GlobalVariable *collectUsedGlobalVariables(Module &M,
			SmallPtrSet<GlobalValue *, 8> &S
			et,
			bool CompilerUsed);
	} // End llvm namespace		} // End llvm namespace
	#endif // LLVM_TRANSFORMS_UTILS_MODULEUTILS_H		#endif // LLVM_TRANSFORMS_UTILS_MODULEUTILS_H
End of changes. 2 change blocks.
	0 lines changed or deleted		11 lines changed or added

	ObjectBuffer.h		ObjectBuffer.h
	skipping to change at line 33		skipping to change at line 33
	namespace llvm {		namespace llvm {
	/// ObjectBuffer - This class acts as a container for the memory buffer use d during		/// ObjectBuffer - This class acts as a container for the memory buffer use d during
	/// generation and loading of executable objects using MCJIT and RuntimeDyl d. The		/// generation and loading of executable objects using MCJIT and RuntimeDyl d. The
	/// underlying memory for the object will be owned by the ObjectBuffer inst ance		/// underlying memory for the object will be owned by the ObjectBuffer inst ance
	/// throughout its lifetime. The getMemBuffer() method provides a way to c reate a		/// throughout its lifetime. The getMemBuffer() method provides a way to c reate a
	/// MemoryBuffer wrapper object instance to be owned by other classes (such as		/// MemoryBuffer wrapper object instance to be owned by other classes (such as
	/// ObjectFile) as needed, but the MemoryBuffer instance returned does not own the		/// ObjectFile) as needed, but the MemoryBuffer instance returned does not own the
	/// actual memory it points to.		/// actual memory it points to.
	class ObjectBuffer {		class ObjectBuffer {
			virtual void anchor();
	public:		public:
	ObjectBuffer() {}		ObjectBuffer() {}
	ObjectBuffer(MemoryBuffer* Buf) : Buffer(Buf) {}		ObjectBuffer(MemoryBuffer* Buf) : Buffer(Buf) {}
	virtual ~ObjectBuffer() {}		virtual ~ObjectBuffer() {}
	/// getMemBuffer - Like MemoryBuffer::getMemBuffer() this function		/// getMemBuffer - Like MemoryBuffer::getMemBuffer() this function
	/// returns a pointer to an object that is owned by the caller. However,		/// returns a pointer to an object that is owned by the caller. However,
	/// the caller does not take ownership of the underlying memory.		/// the caller does not take ownership of the underlying memory.
	MemoryBuffer *getMemBuffer() const {		MemoryBuffer *getMemBuffer() const {
	return MemoryBuffer::getMemBuffer(Buffer->getBuffer(), "", false);		return MemoryBuffer::getMemBuffer(Buffer->getBuffer(), "", false);
	}		}
	const char *getBufferStart() const { return Buffer->getBufferStart(); }		const char *getBufferStart() const { return Buffer->getBufferStart(); }
	size_t getBufferSize() const { return Buffer->getBufferSize(); }		size_t getBufferSize() const { return Buffer->getBufferSize(); }
			StringRef getBuffer() const { return Buffer->getBuffer(); }
	protected:		protected:
	// The memory contained in an ObjectBuffer		// The memory contained in an ObjectBuffer
	OwningPtr<MemoryBuffer> Buffer;		OwningPtr<MemoryBuffer> Buffer;
	};		};
	/// ObjectBufferStream - This class encapsulates the SmallVector and		/// ObjectBufferStream - This class encapsulates the SmallVector and
	/// raw_svector_ostream needed to generate an object using MC code emission		/// raw_svector_ostream needed to generate an object using MC code emission
	/// while providing a common ObjectBuffer interface for access to the		/// while providing a common ObjectBuffer interface for access to the
	/// memory once the object has been generated.		/// memory once the object has been generated.
	class ObjectBufferStream : public ObjectBuffer {		class ObjectBufferStream : public ObjectBuffer {
			virtual void anchor();
	public:		public:
	ObjectBufferStream() : OS(SV) {}		ObjectBufferStream() : OS(SV) {}
	virtual ~ObjectBufferStream() {}		virtual ~ObjectBufferStream() {}
	raw_ostream &getOStream() { return OS; }		raw_ostream &getOStream() { return OS; }
	void flush()		void flush()
	{		{
	OS.flush();		OS.flush();
	// Make the data accessible via the ObjectBuffer::Buffer		// Make the data accessible via the ObjectBuffer::Buffer
End of changes. 3 change blocks.
	0 lines changed or deleted		3 lines changed or added

	ObjectCache.h		ObjectCache.h
	//===-- ObjectCache.h - Class definition for the ObjectCache -----C++ -*-== =//		//===-- ObjectCache.h - Class definition for the ObjectCache -----C++ -*-== =//
	//		//
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_LIB_EXECUTIONENGINE_OBJECTCACHE_H		#ifndef LLVM_EXECUTIONENGINE_OBJECTCACHE_H
	#define LLVM_LIB_EXECUTIONENGINE_OBJECTCACHE_H		#define LLVM_EXECUTIONENGINE_OBJECTCACHE_H
	#include "llvm/Support/MemoryBuffer.h"		#include "llvm/Support/MemoryBuffer.h"
	namespace llvm {		namespace llvm {
	class Module;		class Module;
	/// This is the base ObjectCache type which can be provided to an		/// This is the base ObjectCache type which can be provided to an
	/// ExecutionEngine for the purpose of avoiding compilation for Modules tha t		/// ExecutionEngine for the purpose of avoiding compilation for Modules tha t
	/// have already been compiled and an object file is available.		/// have already been compiled and an object file is available.
	class ObjectCache {		class ObjectCache {
			virtual void anchor();
	public:		public:
	ObjectCache() { }		ObjectCache() { }
	virtual ~ObjectCache() { }		virtual ~ObjectCache() { }
	/// notifyObjectCompiled - Provides a pointer to compiled code for Module M.		/// notifyObjectCompiled - Provides a pointer to compiled code for Module M.
	virtual void notifyObjectCompiled(const Module *M, const MemoryBuffer *Ob j) = 0;		virtual void notifyObjectCompiled(const Module *M, const MemoryBuffer *Ob j) = 0;
	/// getObjectCopy - Returns a pointer to a newly allocated MemoryBuffer t hat		/// getObjectCopy - Returns a pointer to a newly allocated MemoryBuffer t hat
	/// contains the object which corresponds with Module M, or 0 if an objec t is		/// contains the object which corresponds with Module M, or 0 if an objec t is
	/// not available. The caller owns the MemoryBuffer returned by this func		/// not available. The caller owns both the MemoryBuffer returned by this
	tion.		/// and the memory it references.
	MemoryBuffer* getObjectCopy(const Module* M) {		virtual MemoryBuffer* getObject(const Module* M) = 0;
	const MemoryBuffer* Obj = getObject(M);
	if (Obj)
	return MemoryBuffer::getMemBufferCopy(Obj->getBuffer());
	else
	return 0;
	}
	protected:
	/// getObject - Returns a pointer to a MemoryBuffer that contains an obje
	ct
	/// that corresponds with Module M, or 0 if an object is not available.
	/// The pointer returned by this function is not suitable for loading bec
	ause
	/// the memory is read-only and owned by the ObjectCache. To retrieve an
	/// owning pointer to a MemoryBuffer (which is suitable for calling
	/// RuntimeDyld::loadObject() with) use getObjectCopy() instead.
	virtual const MemoryBuffer* getObject(const Module* M) = 0;
	};		};
	}		}
	#endif		#endif
End of changes. 3 change blocks.
	22 lines changed or deleted		6 lines changed or added

	ObjectFile.h		ObjectFile.h
	skipping to change at line 31		skipping to change at line 31
	#include "llvm/Support/MemoryBuffer.h"		#include "llvm/Support/MemoryBuffer.h"
	#include <cstring>		#include <cstring>
	#include <vector>		#include <vector>
	namespace llvm {		namespace llvm {
	namespace object {		namespace object {
	class ObjectFile;		class ObjectFile;
	union DataRefImpl {		union DataRefImpl {
	struct {		// This entire union should probably be a
	// ELF needs this for relocations. This entire union should probably be		// char[max(8, sizeof(uintptr_t))] and require the impl to cast.
	a
	// char[max(8, sizeof(uintptr_t))] and require the impl to cast.
	uint16_t a, b;
	uint32_t c;
	} w;
	struct {		struct {
	uint32_t a, b;		uint32_t a, b;
	} d;		} d;
	uintptr_t p;		uintptr_t p;
	DataRefImpl() {		DataRefImpl() {
	std::memset(this, 0, sizeof(DataRefImpl));		std::memset(this, 0, sizeof(DataRefImpl));
	}		}
	};		};
	template<class content_type>		template<class content_type>
	skipping to change at line 92		skipping to change at line 88
	return std::memcmp(&a, &b, sizeof(DataRefImpl)) == 0;		return std::memcmp(&a, &b, sizeof(DataRefImpl)) == 0;
	}		}
	inline bool operator<(const DataRefImpl &a, const DataRefImpl &b) {		inline bool operator<(const DataRefImpl &a, const DataRefImpl &b) {
	// Check bitwise identical. This is the only legal way to compare a union w/o		// Check bitwise identical. This is the only legal way to compare a union w/o
	// knowing which member is in use.		// knowing which member is in use.
	return std::memcmp(&a, &b, sizeof(DataRefImpl)) < 0;		return std::memcmp(&a, &b, sizeof(DataRefImpl)) < 0;
	}		}
	class SymbolRef;		class SymbolRef;
			typedef content_iterator<SymbolRef> symbol_iterator;
	/// RelocationRef - This is a value type class that represents a single		/// RelocationRef - This is a value type class that represents a single
	/// relocation in the list of relocations in the object file.		/// relocation in the list of relocations in the object file.
	class RelocationRef {		class RelocationRef {
	DataRefImpl RelocationPimpl;		DataRefImpl RelocationPimpl;
	const ObjectFile *OwningObject;		const ObjectFile *OwningObject;
	public:		public:
	RelocationRef() : OwningObject(NULL) { }		RelocationRef() : OwningObject(NULL) { }
	RelocationRef(DataRefImpl RelocationP, const ObjectFile *Owner);		RelocationRef(DataRefImpl RelocationP, const ObjectFile *Owner);
	bool operator==(const RelocationRef &Other) const;		bool operator==(const RelocationRef &Other) const;
	error_code getNext(RelocationRef &Result) const;		error_code getNext(RelocationRef &Result) const;
	error_code getAddress(uint64_t &Result) const;		error_code getAddress(uint64_t &Result) const;
	error_code getOffset(uint64_t &Result) const;		error_code getOffset(uint64_t &Result) const;
	error_code getSymbol(SymbolRef &Result) const;		symbol_iterator getSymbol() const;
	error_code getType(uint64_t &Result) const;		error_code getType(uint64_t &Result) const;
	/// @brief Indicates whether this relocation should hidden when listing		/// @brief Indicates whether this relocation should hidden when listing
	/// relocations, usually because it is the trailing part of a multipart		/// relocations, usually because it is the trailing part of a multipart
	/// relocation that will be printed as part of the leading relocation.		/// relocation that will be printed as part of the leading relocation.
	error_code getHidden(bool &Result) const;		error_code getHidden(bool &Result) const;
	/// @brief Get a string that represents the type of this relocation.		/// @brief Get a string that represents the type of this relocation.
	///		///
	/// This is for display purposes only.		/// This is for display purposes only.
	error_code getTypeName(SmallVectorImpl<char> &Result) const;		error_code getTypeName(SmallVectorImpl<char> &Result) const;
	error_code getAdditionalInfo(int64_t &Result) const;
	/// @brief Get a string that represents the calculation of the value of t his		/// @brief Get a string that represents the calculation of the value of t his
	/// relocation.		/// relocation.
	///		///
	/// This is for display purposes only.		/// This is for display purposes only.
	error_code getValueString(SmallVectorImpl<char> &Result) const;		error_code getValueString(SmallVectorImpl<char> &Result) const;
	DataRefImpl getRawDataRefImpl() const;		DataRefImpl getRawDataRefImpl() const;
			const ObjectFile *getObjectFile() const;
	};		};
	typedef content_iterator<RelocationRef> relocation_iterator;		typedef content_iterator<RelocationRef> relocation_iterator;
	/// SectionRef - This is a value type class that represents a single sectio n in		/// SectionRef - This is a value type class that represents a single sectio n in
	/// the list of sections in the object file.		/// the list of sections in the object file.
			class SectionRef;
			typedef content_iterator<SectionRef> section_iterator;
	class SectionRef {		class SectionRef {
	friend class SymbolRef;		friend class SymbolRef;
	DataRefImpl SectionPimpl;		DataRefImpl SectionPimpl;
	const ObjectFile *OwningObject;		const ObjectFile *OwningObject;
	public:		public:
	SectionRef() : OwningObject(NULL) { }		SectionRef() : OwningObject(NULL) { }
	SectionRef(DataRefImpl SectionP, const ObjectFile *Owner);		SectionRef(DataRefImpl SectionP, const ObjectFile *Owner);
	skipping to change at line 172		skipping to change at line 171
	error_code isBSS(bool &Result) const;		error_code isBSS(bool &Result) const;
	error_code isRequiredForExecution(bool &Result) const;		error_code isRequiredForExecution(bool &Result) const;
	error_code isVirtual(bool &Result) const;		error_code isVirtual(bool &Result) const;
	error_code isZeroInit(bool &Result) const;		error_code isZeroInit(bool &Result) const;
	error_code isReadOnlyData(bool &Result) const;		error_code isReadOnlyData(bool &Result) const;
	error_code containsSymbol(SymbolRef S, bool &Result) const;		error_code containsSymbol(SymbolRef S, bool &Result) const;
	relocation_iterator begin_relocations() const;		relocation_iterator begin_relocations() const;
	relocation_iterator end_relocations() const;		relocation_iterator end_relocations() const;
			section_iterator getRelocatedSection() const;
	DataRefImpl getRawDataRefImpl() const;		DataRefImpl getRawDataRefImpl() const;
	};		};
	typedef content_iterator<SectionRef> section_iterator;
	/// SymbolRef - This is a value type class that represents a single symbol in		/// SymbolRef - This is a value type class that represents a single symbol in
	/// the list of symbols in the object file.		/// the list of symbols in the object file.
	class SymbolRef {		class SymbolRef {
	friend class SectionRef;		friend class SectionRef;
	DataRefImpl SymbolPimpl;		DataRefImpl SymbolPimpl;
	const ObjectFile *OwningObject;		const ObjectFile *OwningObject;
	public:		public:
	SymbolRef() : OwningObject(NULL) { }		SymbolRef() : OwningObject(NULL) { }
	enum Type {		enum Type {
	ST_Unknown, // Type not specified		ST_Unknown, // Type not specified
	ST_Data,		ST_Data,
	ST_Debug,		ST_Debug,
	ST_File,		ST_File,
	ST_Function,		ST_Function,
	ST_Other		ST_Other
	};		};
	enum Flags {		enum Flags LLVM_ENUM_INT_TYPE(unsigned) {
	SF_None = 0,		SF_None = 0,
	SF_Undefined = 1U << 0, // Symbol is defined in another object f ile		SF_Undefined = 1U << 0, // Symbol is defined in another object f ile
	SF_Global = 1U << 1, // Global symbol		SF_Global = 1U << 1, // Global symbol
	SF_Weak = 1U << 2, // Weak symbol		SF_Weak = 1U << 2, // Weak symbol
	SF_Absolute = 1U << 3, // Absolute symbol		SF_Absolute = 1U << 3, // Absolute symbol
	SF_ThreadLocal = 1U << 4, // Thread local symbol		SF_ThreadLocal = 1U << 4, // Thread local symbol
	SF_Common = 1U << 5, // Symbol has common linkage		SF_Common = 1U << 5, // Symbol has common linkage
	SF_FormatSpecific = 1U << 31 // Specific to the object file format		SF_FormatSpecific = 1U << 31 // Specific to the object file format
	// (e.g. section symbols)		// (e.g. section symbols)
	};		};
	skipping to change at line 225		skipping to change at line 224
	error_code getName(StringRef &Result) const;		error_code getName(StringRef &Result) const;
	/// Returns the symbol virtual address (i.e. address at which it will be		/// Returns the symbol virtual address (i.e. address at which it will be
	/// mapped).		/// mapped).
	error_code getAddress(uint64_t &Result) const;		error_code getAddress(uint64_t &Result) const;
	error_code getFileOffset(uint64_t &Result) const;		error_code getFileOffset(uint64_t &Result) const;
	/// @brief Get the alignment of this symbol as the actual value (not log 2).		/// @brief Get the alignment of this symbol as the actual value (not log 2).
	error_code getAlignment(uint32_t &Result) const;		error_code getAlignment(uint32_t &Result) const;
	error_code getSize(uint64_t &Result) const;		error_code getSize(uint64_t &Result) const;
	error_code getType(SymbolRef::Type &Result) const;		error_code getType(SymbolRef::Type &Result) const;
	/// Returns the ascii char that should be displayed in a symbol table dum
	p via
	/// nm for this symbol.
	error_code getNMTypeChar(char &Result) const;
	/// Get symbol flags (bitwise OR of SymbolRef::Flags)		/// Get symbol flags (bitwise OR of SymbolRef::Flags)
	error_code getFlags(uint32_t &Result) const;		error_code getFlags(uint32_t &Result) const;
	/// @brief Get section this symbol is defined in reference to. Result is		/// @brief Get section this symbol is defined in reference to. Result is
	/// end_sections() if it is undefined or is an absolute symbol.		/// end_sections() if it is undefined or is an absolute symbol.
	error_code getSection(section_iterator &Result) const;		error_code getSection(section_iterator &Result) const;
	/// @brief Get value of the symbol in the symbol table.		/// @brief Get value of the symbol in the symbol table.
	error_code getValue(uint64_t &Val) const;		error_code getValue(uint64_t &Val) const;
	DataRefImpl getRawDataRefImpl() const;		DataRefImpl getRawDataRefImpl() const;
	};		};
	typedef content_iterator<SymbolRef> symbol_iterator;
	/// LibraryRef - This is a value type class that represents a single librar y in		/// LibraryRef - This is a value type class that represents a single librar y in
	/// the list of libraries needed by a shared or dynamic object.		/// the list of libraries needed by a shared or dynamic object.
	class LibraryRef {		class LibraryRef {
	friend class SectionRef;		friend class SectionRef;
	DataRefImpl LibraryPimpl;		DataRefImpl LibraryPimpl;
	const ObjectFile *OwningObject;		const ObjectFile *OwningObject;
	public:		public:
	LibraryRef() : OwningObject(NULL) { }		LibraryRef() : OwningObject(NULL) { }
	skipping to change at line 301		skipping to change at line 295
	// modified externally. It's UB otherwise.		// modified externally. It's UB otherwise.
	friend class SymbolRef;		friend class SymbolRef;
	virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const = 0;		virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const = 0;
	virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const = 0;		virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const = 0;
	virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) cons t = 0;		virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) cons t = 0;
	virtual error_code getSymbolFileOffset(DataRefImpl Symb, uint64_t &Res)co nst=0;		virtual error_code getSymbolFileOffset(DataRefImpl Symb, uint64_t &Res)co nst=0;
	virtual error_code getSymbolAlignment(DataRefImpl Symb, uint32_t &Res) co nst;		virtual error_code getSymbolAlignment(DataRefImpl Symb, uint32_t &Res) co nst;
	virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const = 0;		virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const = 0;
	virtual error_code getSymbolType(DataRefImpl Symb,		virtual error_code getSymbolType(DataRefImpl Symb,
	SymbolRef::Type &Res) const = 0;		SymbolRef::Type &Res) const = 0;
	virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const = 0;
	virtual error_code getSymbolFlags(DataRefImpl Symb,		virtual error_code getSymbolFlags(DataRefImpl Symb,
	uint32_t &Res) const = 0;		uint32_t &Res) const = 0;
	virtual error_code getSymbolSection(DataRefImpl Symb,		virtual error_code getSymbolSection(DataRefImpl Symb,
	section_iterator &Res) const = 0;		section_iterator &Res) const = 0;
	virtual error_code getSymbolValue(DataRefImpl Symb, uint64_t &Val) const = 0;		virtual error_code getSymbolValue(DataRefImpl Symb, uint64_t &Val) const = 0;
	// Same as above for SectionRef.		// Same as above for SectionRef.
	friend class SectionRef;		friend class SectionRef;
	virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const = 0;		virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const = 0;
	virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const = 0;		virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const = 0;
	skipping to change at line 327		skipping to change at line 320
	virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const = 0;		virtual error_code isSectionData(DataRefImpl Sec, bool &Res) const = 0;
	virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const = 0;		virtual error_code isSectionBSS(DataRefImpl Sec, bool &Res) const = 0;
	virtual error_code isSectionRequiredForExecution(DataRefImpl Sec,		virtual error_code isSectionRequiredForExecution(DataRefImpl Sec,
	bool &Res) const = 0;		bool &Res) const = 0;
	// A section is 'virtual' if its contents aren't present in the object im age.		// A section is 'virtual' if its contents aren't present in the object im age.
	virtual error_code isSectionVirtual(DataRefImpl Sec, bool &Res) const = 0 ;		virtual error_code isSectionVirtual(DataRefImpl Sec, bool &Res) const = 0 ;
	virtual error_code isSectionZeroInit(DataRefImpl Sec, bool &Res) const = 0;		virtual error_code isSectionZeroInit(DataRefImpl Sec, bool &Res) const = 0;
	virtual error_code isSectionReadOnlyData(DataRefImpl Sec, bool &Res) cons t =0;		virtual error_code isSectionReadOnlyData(DataRefImpl Sec, bool &Res) cons t =0;
	virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Sym b,		virtual error_code sectionContainsSymbol(DataRefImpl Sec, DataRefImpl Sym b,
	bool &Result) const = 0;		bool &Result) const = 0;
	virtual relocation_iterator getSectionRelBegin(DataRefImpl Sec) const = 0		virtual relocation_iterator section_rel_begin(DataRefImpl Sec) const = 0;
	;		virtual relocation_iterator section_rel_end(DataRefImpl Sec) const = 0;
	virtual relocation_iterator getSectionRelEnd(DataRefImpl Sec) const = 0;		virtual section_iterator getRelocatedSection(DataRefImpl Sec) const;
	// Same as above for RelocationRef.		// Same as above for RelocationRef.
	friend class RelocationRef;		friend class RelocationRef;
	virtual error_code getRelocationNext(DataRefImpl Rel,		virtual error_code getRelocationNext(DataRefImpl Rel,
	RelocationRef &Res) const = 0;		RelocationRef &Res) const = 0;
	virtual error_code getRelocationAddress(DataRefImpl Rel,		virtual error_code getRelocationAddress(DataRefImpl Rel,
	uint64_t &Res) const =0;		uint64_t &Res) const =0;
	virtual error_code getRelocationOffset(DataRefImpl Rel,		virtual error_code getRelocationOffset(DataRefImpl Rel,
	uint64_t &Res) const =0;		uint64_t &Res) const =0;
	virtual error_code getRelocationSymbol(DataRefImpl Rel,		virtual symbol_iterator getRelocationSymbol(DataRefImpl Rel) const = 0;
	SymbolRef &Res) const = 0;
	virtual error_code getRelocationType(DataRefImpl Rel,		virtual error_code getRelocationType(DataRefImpl Rel,
	uint64_t &Res) const = 0;		uint64_t &Res) const = 0;
	virtual error_code getRelocationTypeName(DataRefImpl Rel,		virtual error_code getRelocationTypeName(DataRefImpl Rel,
	SmallVectorImpl<char> &Result) const = 0;		SmallVectorImpl<char> &Result) const = 0;
	virtual error_code getRelocationAdditionalInfo(DataRefImpl Rel,
	int64_t &Res) const = 0;
	virtual error_code getRelocationValueString(DataRefImpl Rel,		virtual error_code getRelocationValueString(DataRefImpl Rel,
	SmallVectorImpl<char> &Result) const = 0;		SmallVectorImpl<char> &Result) const = 0;
	virtual error_code getRelocationHidden(DataRefImpl Rel, bool &Result) con st {		virtual error_code getRelocationHidden(DataRefImpl Rel, bool &Result) con st {
	Result = false;		Result = false;
	return object_error::success;		return object_error::success;
	}		}
	// Same for LibraryRef		// Same for LibraryRef
	friend class LibraryRef;		friend class LibraryRef;
	virtual error_code getLibraryNext(DataRefImpl Lib, LibraryRef &Res) const = 0;		virtual error_code getLibraryNext(DataRefImpl Lib, LibraryRef &Res) const = 0;
	skipping to change at line 438		skipping to change at line 429
	}		}
	inline error_code SymbolRef::getAlignment(uint32_t &Result) const {		inline error_code SymbolRef::getAlignment(uint32_t &Result) const {
	return OwningObject->getSymbolAlignment(SymbolPimpl, Result);		return OwningObject->getSymbolAlignment(SymbolPimpl, Result);
	}		}
	inline error_code SymbolRef::getSize(uint64_t &Result) const {		inline error_code SymbolRef::getSize(uint64_t &Result) const {
	return OwningObject->getSymbolSize(SymbolPimpl, Result);		return OwningObject->getSymbolSize(SymbolPimpl, Result);
	}		}
	inline error_code SymbolRef::getNMTypeChar(char &Result) const {
	return OwningObject->getSymbolNMTypeChar(SymbolPimpl, Result);
	}
	inline error_code SymbolRef::getFlags(uint32_t &Result) const {		inline error_code SymbolRef::getFlags(uint32_t &Result) const {
	return OwningObject->getSymbolFlags(SymbolPimpl, Result);		return OwningObject->getSymbolFlags(SymbolPimpl, Result);
	}		}
	inline error_code SymbolRef::getSection(section_iterator &Result) const {		inline error_code SymbolRef::getSection(section_iterator &Result) const {
	return OwningObject->getSymbolSection(SymbolPimpl, Result);		return OwningObject->getSymbolSection(SymbolPimpl, Result);
	}		}
	inline error_code SymbolRef::getType(SymbolRef::Type &Result) const {		inline error_code SymbolRef::getType(SymbolRef::Type &Result) const {
	return OwningObject->getSymbolType(SymbolPimpl, Result);		return OwningObject->getSymbolType(SymbolPimpl, Result);
	skipping to change at line 534		skipping to change at line 521
	inline error_code SectionRef::isReadOnlyData(bool &Result) const {		inline error_code SectionRef::isReadOnlyData(bool &Result) const {
	return OwningObject->isSectionReadOnlyData(SectionPimpl, Result);		return OwningObject->isSectionReadOnlyData(SectionPimpl, Result);
	}		}
	inline error_code SectionRef::containsSymbol(SymbolRef S, bool &Result) con st {		inline error_code SectionRef::containsSymbol(SymbolRef S, bool &Result) con st {
	return OwningObject->sectionContainsSymbol(SectionPimpl, S.SymbolPimpl,		return OwningObject->sectionContainsSymbol(SectionPimpl, S.SymbolPimpl,
	Result);		Result);
	}		}
	inline relocation_iterator SectionRef::begin_relocations() const {		inline relocation_iterator SectionRef::begin_relocations() const {
	return OwningObject->getSectionRelBegin(SectionPimpl);		return OwningObject->section_rel_begin(SectionPimpl);
	}		}
	inline relocation_iterator SectionRef::end_relocations() const {		inline relocation_iterator SectionRef::end_relocations() const {
	return OwningObject->getSectionRelEnd(SectionPimpl);		return OwningObject->section_rel_end(SectionPimpl);
			}
			inline section_iterator SectionRef::getRelocatedSection() const {
			return OwningObject->getRelocatedSection(SectionPimpl);
	}		}
	inline DataRefImpl SectionRef::getRawDataRefImpl() const {		inline DataRefImpl SectionRef::getRawDataRefImpl() const {
	return SectionPimpl;		return SectionPimpl;
	}		}
	/// RelocationRef		/// RelocationRef
	inline RelocationRef::RelocationRef(DataRefImpl RelocationP,		inline RelocationRef::RelocationRef(DataRefImpl RelocationP,
	const ObjectFile *Owner)		const ObjectFile *Owner)
	: RelocationPimpl(RelocationP)		: RelocationPimpl(RelocationP)
	skipping to change at line 567		skipping to change at line 558
	}		}
	inline error_code RelocationRef::getAddress(uint64_t &Result) const {		inline error_code RelocationRef::getAddress(uint64_t &Result) const {
	return OwningObject->getRelocationAddress(RelocationPimpl, Result);		return OwningObject->getRelocationAddress(RelocationPimpl, Result);
	}		}
	inline error_code RelocationRef::getOffset(uint64_t &Result) const {		inline error_code RelocationRef::getOffset(uint64_t &Result) const {
	return OwningObject->getRelocationOffset(RelocationPimpl, Result);		return OwningObject->getRelocationOffset(RelocationPimpl, Result);
	}		}
	inline error_code RelocationRef::getSymbol(SymbolRef &Result) const {		inline symbol_iterator RelocationRef::getSymbol() const {
	return OwningObject->getRelocationSymbol(RelocationPimpl, Result);		return OwningObject->getRelocationSymbol(RelocationPimpl);
	}		}
	inline error_code RelocationRef::getType(uint64_t &Result) const {		inline error_code RelocationRef::getType(uint64_t &Result) const {
	return OwningObject->getRelocationType(RelocationPimpl, Result);		return OwningObject->getRelocationType(RelocationPimpl, Result);
	}		}
	inline error_code RelocationRef::getTypeName(SmallVectorImpl<char> &Result)		inline error_code RelocationRef::getTypeName(SmallVectorImpl<char> &Result)
	const {		const {
	return OwningObject->getRelocationTypeName(RelocationPimpl, Result);		return OwningObject->getRelocationTypeName(RelocationPimpl, Result);
	}		}
	inline error_code RelocationRef::getAdditionalInfo(int64_t &Result) const {
	return OwningObject->getRelocationAdditionalInfo(RelocationPimpl, Result)
	;
	}
	inline error_code RelocationRef::getValueString(SmallVectorImpl<char> &Resu lt)		inline error_code RelocationRef::getValueString(SmallVectorImpl<char> &Resu lt)
	const {		const {
	return OwningObject->getRelocationValueString(RelocationPimpl, Result);		return OwningObject->getRelocationValueString(RelocationPimpl, Result);
	}		}
	inline error_code RelocationRef::getHidden(bool &Result) const {		inline error_code RelocationRef::getHidden(bool &Result) const {
	return OwningObject->getRelocationHidden(RelocationPimpl, Result);		return OwningObject->getRelocationHidden(RelocationPimpl, Result);
	}		}
	inline DataRefImpl RelocationRef::getRawDataRefImpl() const {		inline DataRefImpl RelocationRef::getRawDataRefImpl() const {
	return RelocationPimpl;		return RelocationPimpl;
	}		}
			inline const ObjectFile *RelocationRef::getObjectFile() const {
			return OwningObject;
			}
	// Inline function definitions.		// Inline function definitions.
	inline LibraryRef::LibraryRef(DataRefImpl LibraryP, const ObjectFile *Owner )		inline LibraryRef::LibraryRef(DataRefImpl LibraryP, const ObjectFile *Owner )
	: LibraryPimpl(LibraryP)		: LibraryPimpl(LibraryP)
	, OwningObject(Owner) {}		, OwningObject(Owner) {}
	inline bool LibraryRef::operator==(const LibraryRef &Other) const {		inline bool LibraryRef::operator==(const LibraryRef &Other) const {
	return LibraryPimpl == Other.LibraryPimpl;		return LibraryPimpl == Other.LibraryPimpl;
	}		}
	inline bool LibraryRef::operator<(const LibraryRef &Other) const {		inline bool LibraryRef::operator<(const LibraryRef &Other) const {
End of changes. 21 change blocks.
	38 lines changed or deleted		25 lines changed or added

	ObjectImage.h		ObjectImage.h
	skipping to change at line 27		skipping to change at line 27
	#include "llvm/ExecutionEngine/ObjectBuffer.h"		#include "llvm/ExecutionEngine/ObjectBuffer.h"
	#include "llvm/Object/ObjectFile.h"		#include "llvm/Object/ObjectFile.h"
	namespace llvm {		namespace llvm {
	/// ObjectImage - A container class that represents an ObjectFile that has been		/// ObjectImage - A container class that represents an ObjectFile that has been
	/// or is in the process of being loaded into memory for execution.		/// or is in the process of being loaded into memory for execution.
	class ObjectImage {		class ObjectImage {
	ObjectImage() LLVM_DELETED_FUNCTION;		ObjectImage() LLVM_DELETED_FUNCTION;
	ObjectImage(const ObjectImage &other) LLVM_DELETED_FUNCTION;		ObjectImage(const ObjectImage &other) LLVM_DELETED_FUNCTION;
			virtual void anchor();
	protected:		protected:
	OwningPtr<ObjectBuffer> Buffer;		OwningPtr<ObjectBuffer> Buffer;
	public:		public:
	ObjectImage(ObjectBuffer *Input) : Buffer(Input) {}		ObjectImage(ObjectBuffer *Input) : Buffer(Input) {}
	virtual ~ObjectImage() {}		virtual ~ObjectImage() {}
	virtual object::symbol_iterator begin_symbols() const = 0;		virtual object::symbol_iterator begin_symbols() const = 0;
	virtual object::symbol_iterator end_symbols() const = 0;		virtual object::symbol_iterator end_symbols() const = 0;
End of changes. 1 change blocks.
	0 lines changed or deleted		1 lines changed or added

	Operator.h		Operator.h
	skipping to change at line 437		skipping to change at line 437
	}		}
	return true;		return true;
	}		}
	/// \brief Accumulate the constant address offset of this GEP if possible .		/// \brief Accumulate the constant address offset of this GEP if possible .
	///		///
	/// This routine accepts an APInt into which it will accumulate the const ant		/// This routine accepts an APInt into which it will accumulate the const ant
	/// offset of this GEP if the GEP is in fact constant. If the GEP is not		/// offset of this GEP if the GEP is in fact constant. If the GEP is not
	/// all-constant, it returns false and the value of the offset APInt is		/// all-constant, it returns false and the value of the offset APInt is
	/// undefined (it is *not* preserved!). The APInt passed into this routin e		/// undefined (it is *not* preserved!). The APInt passed into this routin e
	/// must be at least as wide as the IntPtr type for the address space of		/// must be at exactly as wide as the IntPtr type for the address space o
	/// the base GEP pointer.		f the
			/// base GEP pointer.
	bool accumulateConstantOffset(const DataLayout &DL, APInt &Offset) const {		bool accumulateConstantOffset(const DataLayout &DL, APInt &Offset) const {
	assert(Offset.getBitWidth() ==		assert(Offset.getBitWidth() ==
	DL.getPointerSizeInBits(getPointerAddressSpace()) &&		DL.getPointerSizeInBits(getPointerAddressSpace()) &&
	"The offset must have exactly as many bits as our pointer.");		"The offset must have exactly as many bits as our pointer.");
	for (gep_type_iterator GTI = gep_type_begin(this), GTE = gep_type_end(t his);		for (gep_type_iterator GTI = gep_type_begin(this), GTE = gep_type_end(t his);
	GTI != GTE; ++GTI) {		GTI != GTE; ++GTI) {
	ConstantInt *OpC = dyn_cast<ConstantInt>(GTI.getOperand());		ConstantInt *OpC = dyn_cast<ConstantInt>(GTI.getOperand());
	if (!OpC)		if (!OpC)
	return false;		return false;
End of changes. 1 change blocks.
	2 lines changed or deleted		3 lines changed or added

	OptParser.td		OptParser.td
	skipping to change at line 17		skipping to change at line 17
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This file defines the common interfaces used by the option parsing Tabl eGen		// This file defines the common interfaces used by the option parsing Tabl eGen
	// backend.		// backend.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// Define the kinds of options.		// Define the kinds of options.
	class OptionKind<string name, int predecence = 0, bit sentinel = 0> {		class OptionKind<string name, int precedence = 0, bit sentinel = 0> {
	string Name = name;		string Name = name;
	// The kind precedence, kinds with lower precedence are matched first.		// The kind precedence, kinds with lower precedence are matched first.
	int Precedence = predecence;		int Precedence = precedence;
	// Indicate a sentinel option.		// Indicate a sentinel option.
	bit Sentinel = sentinel;		bit Sentinel = sentinel;
	}		}
	// An option group.		// An option group.
	def KIND_GROUP : OptionKind<"Group">;		def KIND_GROUP : OptionKind<"Group">;
	// The input option kind.		// The input option kind.
	def KIND_INPUT : OptionKind<"Input", 1, 1>;		def KIND_INPUT : OptionKind<"Input", 1, 1>;
	// The unknown option kind.		// The unknown option kind.
	def KIND_UNKNOWN : OptionKind<"Unknown", 2, 1>;		def KIND_UNKNOWN : OptionKind<"Unknown", 2, 1>;
	skipping to change at line 47		skipping to change at line 47
	// An option followed by its values, which are separated by commas.		// An option followed by its values, which are separated by commas.
	def KIND_COMMAJOINED : OptionKind<"CommaJoined">;		def KIND_COMMAJOINED : OptionKind<"CommaJoined">;
	// An option which is which takes multiple (separate) arguments.		// An option which is which takes multiple (separate) arguments.
	def KIND_MULTIARG : OptionKind<"MultiArg">;		def KIND_MULTIARG : OptionKind<"MultiArg">;
	// An option which is either joined to its (non-empty) value, or followed b y its		// An option which is either joined to its (non-empty) value, or followed b y its
	// value.		// value.
	def KIND_JOINED_OR_SEPARATE : OptionKind<"JoinedOrSeparate">;		def KIND_JOINED_OR_SEPARATE : OptionKind<"JoinedOrSeparate">;
	// An option which is both joined to its (first) value, and followed by its		// An option which is both joined to its (first) value, and followed by its
	// (second) value.		// (second) value.
	def KIND_JOINED_AND_SEPARATE : OptionKind<"JoinedAndSeparate">;		def KIND_JOINED_AND_SEPARATE : OptionKind<"JoinedAndSeparate">;
			// An option which consumes all remaining arguments if there are any.
			def KIND_REMAINING_ARGS : OptionKind<"RemainingArgs">;
	// Define the option flags.		// Define the option flags.
	class OptionFlag {}		class OptionFlag {}
	// HelpHidden - The option should not be displayed in --help, even if it ha s		// HelpHidden - The option should not be displayed in --help, even if it ha s
	// help text. Clients *can* use this in conjunction with the OptTable::Prin tHelp		// help text. Clients *can* use this in conjunction with the OptTable::Prin tHelp
	// arguments to implement hidden help groups.		// arguments to implement hidden help groups.
	def HelpHidden : OptionFlag;		def HelpHidden : OptionFlag;
	skipping to change at line 92		skipping to change at line 94
	list<string> Prefixes = prefixes;		list<string> Prefixes = prefixes;
	string Name = name;		string Name = name;
	OptionKind Kind = kind;		OptionKind Kind = kind;
	// Used by MultiArg option kind.		// Used by MultiArg option kind.
	int NumArgs = 0;		int NumArgs = 0;
	string HelpText = ?;		string HelpText = ?;
	string MetaVarName = ?;		string MetaVarName = ?;
	list<OptionFlag> Flags = [];		list<OptionFlag> Flags = [];
	OptionGroup Group = ?;		OptionGroup Group = ?;
	Option Alias = ?;		Option Alias = ?;
			list<string> AliasArgs = [];
	}		}
	// Helpers for defining options.		// Helpers for defining options.
	class Flag<list<string> prefixes, string name>		class Flag<list<string> prefixes, string name>
	: Option<prefixes, name, KIND_FLAG>;		: Option<prefixes, name, KIND_FLAG>;
	class Joined<list<string> prefixes, string name>		class Joined<list<string> prefixes, string name>
	: Option<prefixes, name, KIND_JOINED>;		: Option<prefixes, name, KIND_JOINED>;
	class Separate<list<string> prefixes, string name>		class Separate<list<string> prefixes, string name>
	: Option<prefixes, name, KIND_SEPARATE>;		: Option<prefixes, name, KIND_SEPARATE>;
	skipping to change at line 116		skipping to change at line 119
	int NumArgs = numargs;		int NumArgs = numargs;
	}		}
	class JoinedOrSeparate<list<string> prefixes, string name>		class JoinedOrSeparate<list<string> prefixes, string name>
	: Option<prefixes, name, KIND_JOINED_OR_SEPARATE>;		: Option<prefixes, name, KIND_JOINED_OR_SEPARATE>;
	class JoinedAndSeparate<list<string> prefixes, string name>		class JoinedAndSeparate<list<string> prefixes, string name>
	: Option<prefixes, name, KIND_JOINED_AND_SEPARATE>;		: Option<prefixes, name, KIND_JOINED_AND_SEPARATE>;
	// Mix-ins for adding optional attributes.		// Mix-ins for adding optional attributes.
	class Alias<Option alias> { Option Alias = alias; }		class Alias<Option alias> { Option Alias = alias; }
			class AliasArgs<list<string> aliasargs> { list<string> AliasArgs = aliasarg s; }
	class EnumName<string name> { string EnumName = name; }		class EnumName<string name> { string EnumName = name; }
	class Flags<list<OptionFlag> flags> { list<OptionFlag> Flags = flags; }		class Flags<list<OptionFlag> flags> { list<OptionFlag> Flags = flags; }
	class Group<OptionGroup group> { OptionGroup Group = group; }		class Group<OptionGroup group> { OptionGroup Group = group; }
	class HelpText<string text> { string HelpText = text; }		class HelpText<string text> { string HelpText = text; }
	class MetaVarName<string name> { string MetaVarName = name; }		class MetaVarName<string name> { string MetaVarName = name; }
	// Predefined options.		// Predefined options.
	// FIXME: Have generator validate that these appear in correct position (an d		// FIXME: Have generator validate that these appear in correct position (an d
	// aren't duplicated).		// aren't duplicated).
End of changes. 5 change blocks.
	2 lines changed or deleted		6 lines changed or added

	OptTable.h		OptTable.h
	skipping to change at line 47		skipping to change at line 47
	const char *const *Prefixes;		const char *const *Prefixes;
	const char *Name;		const char *Name;
	const char *HelpText;		const char *HelpText;
	const char *MetaVar;		const char *MetaVar;
	unsigned ID;		unsigned ID;
	unsigned char Kind;		unsigned char Kind;
	unsigned char Param;		unsigned char Param;
	unsigned short Flags;		unsigned short Flags;
	unsigned short GroupID;		unsigned short GroupID;
	unsigned short AliasID;		unsigned short AliasID;
			const char *AliasArgs;
	};		};
	private:		private:
	/// \brief The static option information table.		/// \brief The static option information table.
	const Info *OptionInfos;		const Info *OptionInfos;
	unsigned NumOptionInfos;		unsigned NumOptionInfos;
			bool IgnoreCase;
	unsigned TheInputOptionID;		unsigned TheInputOptionID;
	unsigned TheUnknownOptionID;		unsigned TheUnknownOptionID;
	/// The index of the first option which can be parsed (i.e., is not a		/// The index of the first option which can be parsed (i.e., is not a
	/// special option like 'input' or 'unknown', and is not an option group) .		/// special option like 'input' or 'unknown', and is not an option group) .
	unsigned FirstSearchableIndex;		unsigned FirstSearchableIndex;
	/// The union of all option prefixes. If an argument does not begin with		/// The union of all option prefixes. If an argument does not begin with
	/// one of these, it is an input.		/// one of these, it is an input.
	skipping to change at line 74		skipping to change at line 76
	std::string PrefixChars;		std::string PrefixChars;
	private:		private:
	const Info &getInfo(OptSpecifier Opt) const {		const Info &getInfo(OptSpecifier Opt) const {
	unsigned id = Opt.getID();		unsigned id = Opt.getID();
	assert(id > 0 && id - 1 < getNumOptions() && "Invalid Option ID.");		assert(id > 0 && id - 1 < getNumOptions() && "Invalid Option ID.");
	return OptionInfos[id - 1];		return OptionInfos[id - 1];
	}		}
	protected:		protected:
	OptTable(const Info *_OptionInfos, unsigned _NumOptionInfos);		OptTable(const Info *_OptionInfos, unsigned _NumOptionInfos,
			bool _IgnoreCase = false);
	public:		public:
	~OptTable();		~OptTable();
	/// \brief Return the total number of option classes.		/// \brief Return the total number of option classes.
	unsigned getNumOptions() const { return NumOptionInfos; }		unsigned getNumOptions() const { return NumOptionInfos; }
	/// \brief Get the given Opt's Option instance, lazily creating it		/// \brief Get the given Opt's Option instance, lazily creating it
	/// if necessary.		/// if necessary.
	///		///
	/// \return The option, or null for the INVALID option id.		/// \return The option, or null for the INVALID option id.
	skipping to change at line 102		skipping to change at line 105
	/// \brief Get the kind of the given option.		/// \brief Get the kind of the given option.
	unsigned getOptionKind(OptSpecifier id) const {		unsigned getOptionKind(OptSpecifier id) const {
	return getInfo(id).Kind;		return getInfo(id).Kind;
	}		}
	/// \brief Get the group id for the given option.		/// \brief Get the group id for the given option.
	unsigned getOptionGroupID(OptSpecifier id) const {		unsigned getOptionGroupID(OptSpecifier id) const {
	return getInfo(id).GroupID;		return getInfo(id).GroupID;
	}		}
	/// \brief Should the help for the given option be hidden by default.
	bool isOptionHelpHidden(OptSpecifier id) const;
	/// \brief Get the help text to use to describe this option.		/// \brief Get the help text to use to describe this option.
	const char *getOptionHelpText(OptSpecifier id) const {		const char *getOptionHelpText(OptSpecifier id) const {
	return getInfo(id).HelpText;		return getInfo(id).HelpText;
	}		}
	/// \brief Get the meta-variable name to use when describing		/// \brief Get the meta-variable name to use when describing
	/// this options values in the help text.		/// this options values in the help text.
	const char *getOptionMetaVar(OptSpecifier id) const {		const char *getOptionMetaVar(OptSpecifier id) const {
	return getInfo(id).MetaVar;		return getInfo(id).MetaVar;
	}		}
	/// \brief Parse a single argument; returning the new argument and		/// \brief Parse a single argument; returning the new argument and
	/// updating Index.		/// updating Index.
	///		///
	/// \param [in,out] Index - The current parsing position in the argument		/// \param [in,out] Index - The current parsing position in the argument
	/// string list; on return this will be the index of the next argument		/// string list; on return this will be the index of the next argument
	/// string to parse.		/// string to parse.
			/// \param [in] FlagsToInclude - Only parse options with any of these fla
			gs.
			/// Zero is the default which includes all flags.
			/// \param [in] FlagsToExclude - Don't parse options with this flag. Zer
			o
			/// is the default and means exclude nothing.
	///		///
	/// \return The parsed argument, or 0 if the argument is missing values		/// \return The parsed argument, or 0 if the argument is missing values
	/// (in which case Index still points at the conceptual next argument str ing		/// (in which case Index still points at the conceptual next argument str ing
	/// to parse).		/// to parse).
	Arg *ParseOneArg(const ArgList &Args, unsigned &Index) const;		Arg *ParseOneArg(const ArgList &Args, unsigned &Index,
			unsigned FlagsToInclude = 0,
			unsigned FlagsToExclude = 0) const;
	/// \brief Parse an list of arguments into an InputArgList.		/// \brief Parse an list of arguments into an InputArgList.
	///		///
	/// The resulting InputArgList will reference the strings in [\p ArgBegin ,		/// The resulting InputArgList will reference the strings in [\p ArgBegin ,
	/// \p ArgEnd), and their lifetime should extend past that of the returne d		/// \p ArgEnd), and their lifetime should extend past that of the returne d
	/// InputArgList.		/// InputArgList.
	///		///
	/// The only error that can occur in this routine is if an argument is		/// The only error that can occur in this routine is if an argument is
	/// missing values; in this case \p MissingArgCount will be non-zero.		/// missing values; in this case \p MissingArgCount will be non-zero.
	///		///
	/// \param ArgBegin - The beginning of the argument vector.		/// \param ArgBegin - The beginning of the argument vector.
	/// \param ArgEnd - The end of the argument vector.		/// \param ArgEnd - The end of the argument vector.
	/// \param MissingArgIndex - On error, the index of the option which coul d		/// \param MissingArgIndex - On error, the index of the option which coul d
	/// not be parsed.		/// not be parsed.
	/// \param MissingArgCount - On error, the number of missing options.		/// \param MissingArgCount - On error, the number of missing options.
			/// \param FlagsToInclude - Only parse options with any of these flags.
			/// Zero is the default which includes all flags.
			/// \param FlagsToExclude - Don't parse options with this flag. Zero
			/// is the default and means exclude nothing.
	/// \return An InputArgList; on error this will contain all the options		/// \return An InputArgList; on error this will contain all the options
	/// which could be parsed.		/// which could be parsed.
	InputArgList *ParseArgs(const char* const *ArgBegin,		InputArgList *ParseArgs(const char* const *ArgBegin,
	const char* const *ArgEnd,		const char* const *ArgEnd,
	unsigned &MissingArgIndex,		unsigned &MissingArgIndex,
	unsigned &MissingArgCount) const;		unsigned &MissingArgCount,
			unsigned FlagsToInclude = 0,
			unsigned FlagsToExclude = 0) const;
	/// \brief Render the help text for an option table.		/// \brief Render the help text for an option table.
	///		///
	/// \param OS - The stream to write the help text to.		/// \param OS - The stream to write the help text to.
	/// \param Name - The name to use in the usage line.		/// \param Name - The name to use in the usage line.
	/// \param Title - The title to use in the usage line.		/// \param Title - The title to use in the usage line.
	/// \param ShowHidden - Whether help-hidden arguments should be shown.		/// \param FlagsToInclude - If non-zero, only include options with any
			/// of these flags set.
			/// \param FlagsToExclude - Exclude options with any of these flags set.
			void PrintHelp(raw_ostream &OS, const char *Name,
			const char *Title, unsigned FlagsToInclude,
			unsigned FlagsToExclude) const;
	void PrintHelp(raw_ostream &OS, const char *Name,		void PrintHelp(raw_ostream &OS, const char *Name,
	const char *Title, bool ShowHidden = false) const;		const char *Title, bool ShowHidden = false) const;
	};		};
	} // end namespace opt		} // end namespace opt
	} // end namespace llvm		} // end namespace llvm
	#endif		#endif
End of changes. 9 change blocks.
	7 lines changed or deleted		27 lines changed or added

	Option.h		Option.h
	skipping to change at line 53		skipping to change at line 53
	/// particular Option instance.		/// particular Option instance.
	class Option {		class Option {
	public:		public:
	enum OptionClass {		enum OptionClass {
	GroupClass = 0,		GroupClass = 0,
	InputClass,		InputClass,
	UnknownClass,		UnknownClass,
	FlagClass,		FlagClass,
	JoinedClass,		JoinedClass,
	SeparateClass,		SeparateClass,
			RemainingArgsClass,
	CommaJoinedClass,		CommaJoinedClass,
	MultiArgClass,		MultiArgClass,
	JoinedOrSeparateClass,		JoinedOrSeparateClass,
	JoinedAndSeparateClass		JoinedAndSeparateClass
	};		};
	enum RenderStyleKind {		enum RenderStyleKind {
	RenderCommaJoinedStyle,		RenderCommaJoinedStyle,
	RenderJoinedStyle,		RenderJoinedStyle,
	RenderSeparateStyle,		RenderSeparateStyle,
	skipping to change at line 106		skipping to change at line 107
	assert(Owner && "Must have a valid owner!");		assert(Owner && "Must have a valid owner!");
	return Owner->getOption(Info->GroupID);		return Owner->getOption(Info->GroupID);
	}		}
	const Option getAlias() const {		const Option getAlias() const {
	assert(Info && "Must have a valid info!");		assert(Info && "Must have a valid info!");
	assert(Owner && "Must have a valid owner!");		assert(Owner && "Must have a valid owner!");
	return Owner->getOption(Info->AliasID);		return Owner->getOption(Info->AliasID);
	}		}
			/// \brief Get the alias arguments as a \0 separated list.
			/// E.g. ["foo", "bar"] would be returned as "foo\0bar\0".
			const char *getAliasArgs() const {
			assert(Info && "Must have a valid info!");
			assert((!Info->AliasArgs || Info->AliasArgs[0] != 0) &&
			"AliasArgs should be either 0 or non-empty.");
			return Info->AliasArgs;
			}
	/// \brief Get the default prefix for this option.		/// \brief Get the default prefix for this option.
	StringRef getPrefix() const {		StringRef getPrefix() const {
	const char *Prefix = *Info->Prefixes;		const char *Prefix = *Info->Prefixes;
	return Prefix ? Prefix : StringRef();		return Prefix ? Prefix : StringRef();
	}		}
	/// \brief Get the name of this option with the default prefix.		/// \brief Get the name of this option with the default prefix.
	std::string getPrefixedName() const {		std::string getPrefixedName() const {
	std::string Ret = getPrefix();		std::string Ret = getPrefix();
	Ret += getName();		Ret += getName();
	skipping to change at line 142		skipping to change at line 153
	return RenderValuesStyle;		return RenderValuesStyle;
	case JoinedClass:		case JoinedClass:
	case JoinedAndSeparateClass:		case JoinedAndSeparateClass:
	return RenderJoinedStyle;		return RenderJoinedStyle;
	case CommaJoinedClass:		case CommaJoinedClass:
	return RenderCommaJoinedStyle;		return RenderCommaJoinedStyle;
	case FlagClass:		case FlagClass:
	case SeparateClass:		case SeparateClass:
	case MultiArgClass:		case MultiArgClass:
	case JoinedOrSeparateClass:		case JoinedOrSeparateClass:
			case RemainingArgsClass:
	return RenderSeparateStyle;		return RenderSeparateStyle;
	}		}
	llvm_unreachable("Unexpected kind!");		llvm_unreachable("Unexpected kind!");
	}		}
	/// Test if this option has the flag \a Val.		/// Test if this option has the flag \a Val.
	bool hasFlag(unsigned Val) const {		bool hasFlag(unsigned Val) const {
	return Info->Flags & Val;		return Info->Flags & Val;
	}		}
	skipping to change at line 182		skipping to change at line 194
	bool matches(OptSpecifier ID) const;		bool matches(OptSpecifier ID) const;
	/// accept - Potentially accept the current argument, returning a		/// accept - Potentially accept the current argument, returning a
	/// new Arg instance, or 0 if the option does not accept this		/// new Arg instance, or 0 if the option does not accept this
	/// argument (or the argument is missing values).		/// argument (or the argument is missing values).
	///		///
	/// If the option accepts the current argument, accept() sets		/// If the option accepts the current argument, accept() sets
	/// Index to the position where argument parsing should resume		/// Index to the position where argument parsing should resume
	/// (even if the argument is missing values).		/// (even if the argument is missing values).
	///		///
	/// \parm ArgSize The number of bytes taken up by the matched Option pref		/// \param ArgSize The number of bytes taken up by the matched Option pre
	ix		fix
	/// and name. This is used to determine where joined values		/// and name. This is used to determine where joined value
	/// start.		s
			/// start.
	Arg *accept(const ArgList &Args, unsigned &Index, unsigned ArgSize) const ;		Arg *accept(const ArgList &Args, unsigned &Index, unsigned ArgSize) const ;
	void dump() const;		void dump() const;
	};		};
	} // end namespace opt		} // end namespace opt
	} // end namespace llvm		} // end namespace llvm
	#endif		#endif
End of changes. 4 change blocks.
	4 lines changed or deleted		17 lines changed or added

	OwningPtr.h		OwningPtr.h
	skipping to change at line 73		skipping to change at line 73
	return Tmp;		return Tmp;
	}		}
	T &operator*() const {		T &operator*() const {
	assert(Ptr && "Cannot dereference null pointer");		assert(Ptr && "Cannot dereference null pointer");
	return *Ptr;		return *Ptr;
	}		}
	T *operator->() const { return Ptr; }		T *operator->() const { return Ptr; }
	T *get() const { return Ptr; }		T *get() const { return Ptr; }
	operator bool() const { return Ptr != 0; }		LLVM_EXPLICIT operator bool() const { return Ptr != 0; }
	bool operator!() const { return Ptr == 0; }		bool operator!() const { return Ptr == 0; }
			bool isValid() const { return Ptr != 0; }
	void swap(OwningPtr &RHS) {		void swap(OwningPtr &RHS) {
	T *Tmp = RHS.Ptr;		T *Tmp = RHS.Ptr;
	RHS.Ptr = Ptr;		RHS.Ptr = Ptr;
	Ptr = Tmp;		Ptr = Tmp;
	}		}
	};		};
	template<class T>		template<class T>
	inline void swap(OwningPtr<T> &a, OwningPtr<T> &b) {		inline void swap(OwningPtr<T> &a, OwningPtr<T> &b) {
	skipping to change at line 135		skipping to change at line 136
	Ptr = 0;		Ptr = 0;
	return Tmp;		return Tmp;
	}		}
	T &operator[](std::ptrdiff_t i) const {		T &operator[](std::ptrdiff_t i) const {
	assert(Ptr && "Cannot dereference null pointer");		assert(Ptr && "Cannot dereference null pointer");
	return Ptr[i];		return Ptr[i];
	}		}
	T *get() const { return Ptr; }		T *get() const { return Ptr; }
	operator bool() const { return Ptr != 0; }		LLVM_EXPLICIT operator bool() const { return Ptr != 0; }
	bool operator!() const { return Ptr == 0; }		bool operator!() const { return Ptr == 0; }
	void swap(OwningArrayPtr &RHS) {		void swap(OwningArrayPtr &RHS) {
	T *Tmp = RHS.Ptr;		T *Tmp = RHS.Ptr;
	RHS.Ptr = Ptr;		RHS.Ptr = Ptr;
	Ptr = Tmp;		Ptr = Tmp;
	}		}
	};		};
	template<class T>		template<class T>
End of changes. 3 change blocks.
	2 lines changed or deleted		3 lines changed or added

	PassManager.h		PassManager.h
	//===- llvm/PassManager.h - Container for Passes ----------------*- C++ -*- ===//		//===- llvm/PassManager.h - Container for Passes ----------------*- C++ -*- ===//
	//		//
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This file defines the PassManager class. This class is used to hold,		// This is a legacy redirect header for the old PassManager. It is intended
	// maintain, and optimize execution of Passes. The PassManager class ensur		to
	es		// be used by clients that have not been converted to be aware of the new p
	// that analysis results are available before a pass runs, and that Pass's		ass
	are		// management infrastructure being built for LLVM, which is every client
	// destroyed when the PassManager is destroyed.		// initially. Eventually this header (and the legacy management layer) will
			go
			// away, but we want to minimize changes to out-of-tree users of LLVM in th
			e
			// interim.
			//
			// Note that this header *must not* be included into the same file as the n
			ew
			// pass management infrastructure is included. Things will break spectacula
			rly.
			// If you are starting that conversion, you should switch to explicitly
			// including LegacyPassManager.h and using the legacy namespace.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_PASSMANAGER_H		#ifndef LLVM_PASSMANAGER_H
	#define LLVM_PASSMANAGER_H		#define LLVM_PASSMANAGER_H
	#include "llvm/Pass.h"		#include "llvm/IR/LegacyPassManager.h"
	#include "llvm/Support/CBindingWrapping.h"
	namespace llvm {		namespace llvm {
	class Pass;		// Pull these into the llvm namespace so that existing code that expects it
	class Module;		// there can find it.
			using legacy::PassManagerBase;
	class PassManagerImpl;		using legacy::PassManager;
	class FunctionPassManagerImpl;		using legacy::FunctionPassManager;
	/// PassManagerBase - An abstract interface to allow code to add passes to
	/// a pass manager without having to hard-code what kind of pass manager
	/// it is.
	class PassManagerBase {
	public:
	virtual ~PassManagerBase();
	/// add - Add a pass to the queue of passes to run. This passes ownershi
	p of
	/// the Pass to the PassManager. When the PassManager is destroyed, the
	pass
	/// will be destroyed as well, so there is no need to delete the pass. T
	his
	/// implies that all passes MUST be allocated with 'new'.
	virtual void add(Pass *P) = 0;
	};
	/// PassManager manages ModulePassManagers
	class PassManager : public PassManagerBase {
	public:
	PassManager();
	~PassManager();
	/// add - Add a pass to the queue of passes to run. This passes ownershi
	p of
	/// the Pass to the PassManager. When the PassManager is destroyed, the
	pass
	/// will be destroyed as well, so there is no need to delete the pass. T
	his
	/// implies that all passes MUST be allocated with 'new'.
	void add(Pass *P);
	/// run - Execute all of the passes scheduled for execution. Keep track
	of
	/// whether any of the passes modifies the module, and if so, return true
	.
	bool run(Module &M);
	private:
	/// PassManagerImpl_New is the actual class. PassManager is just the
	/// wraper to publish simple pass manager interface
	PassManagerImpl *PM;
	};
	/// FunctionPassManager manages FunctionPasses and BasicBlockPassManagers.
	class FunctionPassManager : public PassManagerBase {
	public:
	/// FunctionPassManager ctor - This initializes the pass manager. It nee
	ds,
	/// but does not take ownership of, the specified Module.
	explicit FunctionPassManager(Module *M);
	~FunctionPassManager();
	/// add - Add a pass to the queue of passes to run. This passes
	/// ownership of the Pass to the PassManager. When the
	/// PassManager_X is destroyed, the pass will be destroyed as well, so
	/// there is no need to delete the pass.
	/// This implies that all passes MUST be allocated with 'new'.
	void add(Pass *P);
	/// run - Execute all of the passes scheduled for execution. Keep
	/// track of whether any of the passes modifies the function, and if
	/// so, return true.
	///
	bool run(Function &F);
	/// doInitialization - Run all of the initializers for the function passe
	s.
	///
	bool doInitialization();
	/// doFinalization - Run all of the finalizers for the function passes.
	///
	bool doFinalization();
	private:
	FunctionPassManagerImpl *FPM;
	Module *M;
	};
	// Create wrappers for C Binding types (see CBindingWrapping.h).
	DEFINE_STDCXX_CONVERSION_FUNCTIONS(PassManagerBase, LLVMPassManagerRef)
	} // End llvm namespace		}
	#endif		#endif
End of changes. 4 change blocks.
	98 lines changed or deleted		24 lines changed or added

	PassNameParser.h		PassNameParser.h
	//===- llvm/Support/PassNameParser.h ----------------------------*- C++ -*- ===//		//===- llvm/Support/PassNameParser.h ----------------------------*- C++ -*- ===//
	//		//
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This file the PassNameParser and FilteredPassNameParser<> classes, which		// This file contains the PassNameParser and FilteredPassNameParser<> class
	are		es,
	// used to add command line arguments to a utility for all of the passes th		// which are used to add command line arguments to a utility for all of the
	at		// passes that have been registered into the system.
	// have been registered into the system.
	//		//
	// The PassNameParser class adds ALL passes linked into the system (that ar e		// The PassNameParser class adds ALL passes linked into the system (that ar e
	// creatable) as command line arguments to the tool (when instantiated with the		// creatable) as command line arguments to the tool (when instantiated with the
	// appropriate command line option template). The FilteredPassNameParser<>		// appropriate command line option template). The FilteredPassNameParser<>
	// template is used for the same purposes as PassNameParser, except that it only		// template is used for the same purposes as PassNameParser, except that it only
	// includes passes that have a PassType that are compatible with the filter		// includes passes that have a PassType that are compatible with the filter
	// (which is the template argument).		// (which is the template argument).
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	skipping to change at line 89		skipping to change at line 89
	// printOptionInfo - Print out information about this option. Override t he		// printOptionInfo - Print out information about this option. Override t he
	// default implementation to sort the table before we print...		// default implementation to sort the table before we print...
	virtual void printOptionInfo(const cl::Option &O, size_t GlobalWidth) con st {		virtual void printOptionInfo(const cl::Option &O, size_t GlobalWidth) con st {
	PassNameParser *PNP = const_cast<PassNameParser*>(this);		PassNameParser *PNP = const_cast<PassNameParser*>(this);
	array_pod_sort(PNP->Values.begin(), PNP->Values.end(), ValLessThan);		array_pod_sort(PNP->Values.begin(), PNP->Values.end(), ValLessThan);
	cl::parser<const PassInfo*>::printOptionInfo(O, GlobalWidth);		cl::parser<const PassInfo*>::printOptionInfo(O, GlobalWidth);
	}		}
	private:		private:
	// ValLessThan - Provide a sorting comparator for Values elements...		// ValLessThan - Provide a sorting comparator for Values elements...
	static int ValLessThan(const void *VT1, const void *VT2) {		static int ValLessThan(const PassNameParser::OptionInfo *VT1,
	typedef PassNameParser::OptionInfo ValType;		const PassNameParser::OptionInfo *VT2) {
	return std::strcmp(static_cast<const ValType *>(VT1)->Name,		return std::strcmp(VT1->Name, VT2->Name);
	static_cast<const ValType *>(VT2)->Name);
	}		}
	};		};
	///===--------------------------------------------------------------------- -===//		///===--------------------------------------------------------------------- -===//
	/// FilteredPassNameParser class - Make use of the pass registration		/// FilteredPassNameParser class - Make use of the pass registration
	/// mechanism to automatically add a command line argument to opt for		/// mechanism to automatically add a command line argument to opt for
	/// each pass that satisfies a filter criteria. Filter should return		/// each pass that satisfies a filter criteria. Filter should return
	/// true for passes to be registered as command-line options.		/// true for passes to be registered as command-line options.
	///		///
	template<typename Filter>		template<typename Filter>
End of changes. 2 change blocks.
	9 lines changed or deleted		7 lines changed or added

	Passes.h		Passes.h
	skipping to change at line 24		skipping to change at line 24
	#ifndef LLVM_CODEGEN_PASSES_H		#ifndef LLVM_CODEGEN_PASSES_H
	#define LLVM_CODEGEN_PASSES_H		#define LLVM_CODEGEN_PASSES_H
	#include "llvm/Pass.h"		#include "llvm/Pass.h"
	#include "llvm/Target/TargetMachine.h"		#include "llvm/Target/TargetMachine.h"
	#include <string>		#include <string>
	namespace llvm {		namespace llvm {
	class FunctionPass;		class FunctionPass;
	class MachineFunctionPass;		class MachineFunctionPass;
	class PassInfo;
	class PassManagerBase;
	class TargetLoweringBase;
	class TargetLowering;
	class TargetRegisterClass;
	class raw_ostream;
	}
	namespace llvm {
	class PassConfigImpl;		class PassConfigImpl;
			class PassInfo;
			class ScheduleDAGInstrs;
			class TargetLowering;
			class TargetLoweringBase;
			class TargetRegisterClass;
			class raw_ostream;
			struct MachineSchedContext;
			// The old pass manager infrastructure is hidden in a legacy namespace now.
			namespace legacy {
			class PassManagerBase;
			}
			using legacy::PassManagerBase;
	/// Discriminated union of Pass ID types.		/// Discriminated union of Pass ID types.
	///		///
	/// The PassConfig API prefers dealing with IDs because they are safer and more		/// The PassConfig API prefers dealing with IDs because they are safer and more
	/// efficient. IDs decouple configuration from instantiation. This way, whe n a		/// efficient. IDs decouple configuration from instantiation. This way, whe n a
	/// pass is overriden, it isn't unnecessarily instantiated. It is also unsa fe to		/// pass is overriden, it isn't unnecessarily instantiated. It is also unsa fe to
	/// refer to a Pass pointer after adding it to a pass manager, which delete s		/// refer to a Pass pointer after adding it to a pass manager, which delete s
	/// redundant pass instances.		/// redundant pass instances.
	///		///
	/// However, it is convient to directly instantiate target passes with		/// However, it is convient to directly instantiate target passes with
	skipping to change at line 207		skipping to change at line 210
	/// addInstSelector - This method should install an instruction selector pass,		/// addInstSelector - This method should install an instruction selector pass,
	/// which converts from LLVM code to machine instructions.		/// which converts from LLVM code to machine instructions.
	virtual bool addInstSelector() {		virtual bool addInstSelector() {
	return true;		return true;
	}		}
	/// Add the complete, standard set of LLVM CodeGen passes.		/// Add the complete, standard set of LLVM CodeGen passes.
	/// Fully developed targets will not generally override this.		/// Fully developed targets will not generally override this.
	virtual void addMachinePasses();		virtual void addMachinePasses();
			/// createTargetScheduler - Create an instance of ScheduleDAGInstrs to be
			run
			/// within the standard MachineScheduler pass for this function and targe
			t at
			/// the current optimization level.
			///
			/// This can also be used to plug a new MachineSchedStrategy into an inst
			ance
			/// of the standard ScheduleDAGMI:
			/// return new ScheduleDAGMI(C, new MyStrategy(C))
			///
			/// Return NULL to select the default (generic) machine scheduler.
			virtual ScheduleDAGInstrs *
			createMachineScheduler(MachineSchedContext *C) const {
			return 0;
			}
	protected:		protected:
	// Helper to verify the analysis is really immutable.		// Helper to verify the analysis is really immutable.
	void setOpt(bool &Opt, bool Val);		void setOpt(bool &Opt, bool Val);
	/// Methods with trivial inline returns are convenient points in the comm on		/// Methods with trivial inline returns are convenient points in the comm on
	/// codegen pass pipeline where targets may insert passes. Methods with		/// codegen pass pipeline where targets may insert passes. Methods with
	/// out-of-line standard implementations are major CodeGen stages called by		/// out-of-line standard implementations are major CodeGen stages called by
	/// addMachinePasses. Some targets may override major stages when inserti ng		/// addMachinePasses. Some targets may override major stages when inserti ng
	/// passes is insufficient, but maintaining overriden stages is more work .		/// passes is insufficient, but maintaining overriden stages is more work .
	///		///
	skipping to change at line 311		skipping to change at line 328
	}		}
	/// Utilities for targets to add passes to the pass manager.		/// Utilities for targets to add passes to the pass manager.
	///		///
	/// Add a CodeGen pass at this point in the pipeline after checking overr ides.		/// Add a CodeGen pass at this point in the pipeline after checking overr ides.
	/// Return the pass that was added, or zero if no pass was added.		/// Return the pass that was added, or zero if no pass was added.
	AnalysisID addPass(AnalysisID PassID);		AnalysisID addPass(AnalysisID PassID);
	/// Add a pass to the PassManager if that pass is supposed to be run, as		/// Add a pass to the PassManager if that pass is supposed to be run, as
	/// determined by the StartAfter and StopAfter options.		/// determined by the StartAfter and StopAfter options. Takes ownership o
			f the
			/// pass.
	void addPass(Pass *P);		void addPass(Pass *P);
	/// addMachinePasses helper to create the target-selected or overriden		/// addMachinePasses helper to create the target-selected or overriden
	/// regalloc pass.		/// regalloc pass.
	FunctionPass *createRegAllocPass(bool Optimized);		FunctionPass *createRegAllocPass(bool Optimized);
	/// printAndVerify - Add a pass to dump then verify the machine function, if		/// printAndVerify - Add a pass to dump then verify the machine function, if
	/// those steps are enabled.		/// those steps are enabled.
	///		///
	void printAndVerify(const char *Banner);		void printAndVerify(const char *Banner);
	};		};
	} // namespace llvm		} // namespace llvm
	/// List of target independent CodeGen pass IDs.		/// List of target independent CodeGen pass IDs.
	namespace llvm {		namespace llvm {
	/// \brief Create a basic TargetTransformInfo analysis pass.		/// \brief Create a basic TargetTransformInfo analysis pass.
	///		///
	/// This pass implements the target transform info analysis using the tar get		/// This pass implements the target transform info analysis using the tar get
	/// independent information available to the LLVM code generator.		/// independent information available to the LLVM code generator.
	ImmutablePass *		ImmutablePass *
	createBasicTargetTransformInfoPass(const TargetLoweringBase *TLI);		createBasicTargetTransformInfoPass(const TargetMachine *TM);
	/// createUnreachableBlockEliminationPass - The LLVM code generator does not		/// createUnreachableBlockEliminationPass - The LLVM code generator does not
	/// work well with unreachable basic blocks (what live ranges make sense for a		/// work well with unreachable basic blocks (what live ranges make sense for a
	/// block that cannot be reached?). As such, a code generator should eit her		/// block that cannot be reached?). As such, a code generator should eit her
	/// not instruction select unreachable blocks, or run this pass as its		/// not instruction select unreachable blocks, or run this pass as its
	/// last LLVM modifying pass to clean up blocks that are not reachable fr om		/// last LLVM modifying pass to clean up blocks that are not reachable fr om
	/// the entry block.		/// the entry block.
	FunctionPass *createUnreachableBlockEliminationPass();		FunctionPass *createUnreachableBlockEliminationPass();
	/// MachineFunctionPrinter pass - This pass prints out the machine functi on to		/// MachineFunctionPrinter pass - This pass prints out the machine functi on to
	skipping to change at line 367		skipping to change at line 385
	/// LiveVariables pass - This pass computes the set of blocks in which ea ch		/// LiveVariables pass - This pass computes the set of blocks in which ea ch
	/// variable is life and sets machine operand kill flags.		/// variable is life and sets machine operand kill flags.
	extern char &LiveVariablesID;		extern char &LiveVariablesID;
	/// PHIElimination - This pass eliminates machine instruction PHI nodes		/// PHIElimination - This pass eliminates machine instruction PHI nodes
	/// by inserting copy instructions. This destroys SSA information, but i s the		/// by inserting copy instructions. This destroys SSA information, but i s the
	/// desired input for some register allocators. This pass is "required" by		/// desired input for some register allocators. This pass is "required" by
	/// these register allocator like this: AU.addRequiredID(PHIEliminationID );		/// these register allocator like this: AU.addRequiredID(PHIEliminationID );
	extern char &PHIEliminationID;		extern char &PHIEliminationID;
	/// StrongPHIElimination - This pass eliminates machine instruction PHI
	/// nodes by inserting copy instructions. This destroys SSA information,
	but
	/// is the desired input for some register allocators. This pass is
	/// "required" by these register allocator like this:
	/// AU.addRequiredID(PHIEliminationID);
	/// This pass is still in development
	extern char &StrongPHIEliminationID;
	/// LiveIntervals - This analysis keeps track of the live ranges of virtu al		/// LiveIntervals - This analysis keeps track of the live ranges of virtu al
	/// and physical registers.		/// and physical registers.
	extern char &LiveIntervalsID;		extern char &LiveIntervalsID;
	/// LiveStacks pass. An analysis keeping track of the liveness of stack s lots.		/// LiveStacks pass. An analysis keeping track of the liveness of stack s lots.
	extern char &LiveStacksID;		extern char &LiveStacksID;
	/// TwoAddressInstruction - This pass reduces two-address instructions to		/// TwoAddressInstruction - This pass reduces two-address instructions to
	/// use two operands. This destroys SSA information but it is desired by		/// use two operands. This destroys SSA information but it is desired by
	/// register allocators.		/// register allocators.
	skipping to change at line 521		skipping to change at line 531
	/// OptimizePHIs - This pass optimizes machine instruction PHIs		/// OptimizePHIs - This pass optimizes machine instruction PHIs
	/// to take advantage of opportunities created during DAG legalization.		/// to take advantage of opportunities created during DAG legalization.
	extern char &OptimizePHIsID;		extern char &OptimizePHIsID;
	/// StackSlotColoring - This pass performs stack slot coloring.		/// StackSlotColoring - This pass performs stack slot coloring.
	extern char &StackSlotColoringID;		extern char &StackSlotColoringID;
	/// createStackProtectorPass - This pass adds stack protectors to functio ns.		/// createStackProtectorPass - This pass adds stack protectors to functio ns.
	///		///
	FunctionPass *createStackProtectorPass(const TargetLoweringBase *tli);		FunctionPass *createStackProtectorPass(const TargetMachine *TM);
	/// createMachineVerifierPass - This pass verifies cenerated machine code		/// createMachineVerifierPass - This pass verifies cenerated machine code
	/// instructions for correctness.		/// instructions for correctness.
	///		///
	FunctionPass *createMachineVerifierPass(const char *Banner = 0);		FunctionPass *createMachineVerifierPass(const char *Banner = 0);
	/// createDwarfEHPass - This pass mulches exception handling code into a form		/// createDwarfEHPass - This pass mulches exception handling code into a form
	/// adapted to code generation. Required if using dwarf exception handli ng.		/// adapted to code generation. Required if using dwarf exception handli ng.
	FunctionPass *createDwarfEHPass(const TargetMachine *tm);		FunctionPass *createDwarfEHPass(const TargetMachine *TM);
	/// createSjLjEHPreparePass - This pass adapts exception handling code to use		/// createSjLjEHPreparePass - This pass adapts exception handling code to use
	/// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control fl ow.		/// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control fl ow.
	///		///
	FunctionPass *createSjLjEHPreparePass(const TargetLoweringBase *tli);		FunctionPass *createSjLjEHPreparePass(const TargetMachine *TM);
	/// LocalStackSlotAllocation - This pass assigns local frame indices to s tack		/// LocalStackSlotAllocation - This pass assigns local frame indices to s tack
	/// slots relative to one another and allocates base registers to access them		/// slots relative to one another and allocates base registers to access them
	/// when it is estimated by the target to be out of range of normal frame		/// when it is estimated by the target to be out of range of normal frame
	/// pointer or stack pointer index addressing.		/// pointer or stack pointer index addressing.
	extern char &LocalStackSlotAllocationID;		extern char &LocalStackSlotAllocationID;
	/// ExpandISelPseudos - This pass expands pseudo-instructions.		/// ExpandISelPseudos - This pass expands pseudo-instructions.
	extern char &ExpandISelPseudosID;		extern char &ExpandISelPseudosID;
End of changes. 9 change blocks.
	26 lines changed or deleted		39 lines changed or added

	Path.h		Path.h
	//===- llvm/Support/Path.h - Path Operating System Concept ------*- C++ -*- ===//		//===- llvm/Support/Path.h - Path Operating System Concept ------*- C++ -*- ===//
	//		//
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This file currently includes both PathV1 and PathV2 to facilitate moving		// This file declares the llvm::sys::path namespace. It is designed after
	// clients over to the new interface.		// TR2/boost filesystem (v3), but modified to remove exception handling and
			the
			// path class.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#include "llvm/Support/PathV1.h"		#ifndef LLVM_SUPPORT_PATH_H
	#include "llvm/Support/PathV2.h"		#define LLVM_SUPPORT_PATH_H
			#include "llvm/ADT/SmallString.h"
			#include "llvm/ADT/Twine.h"
			#include "llvm/Support/DataTypes.h"
			#include <iterator>
			namespace llvm {
			namespace sys {
			namespace path {
			/// @name Lexical Component Iterator
			/// @{
			/// @brief Path iterator.
			///
			/// This is a bidirectional iterator that iterates over the individual
			/// components in \a path. The forward traversal order is as follows:
			/// * The root-name element, if present.
			/// * The root-directory element, if present.
			/// * Each successive filename element, if present.
			/// * Dot, if one or more trailing non-root slash characters are present.
			/// The backwards traversal order is the reverse of forward traversal.
			///
			/// Iteration examples. Each component is separated by ',':
			/// @code
			/// / => /
			/// /foo => /,foo
			/// foo/ => foo,.
			/// /foo/bar => /,foo,bar
			/// ../ => ..,.
			/// C:\foo\bar => C:,/,foo,bar
			/// @endcode
			class const_iterator {
			StringRef Path; ///< The entire path.
			StringRef Component; ///< The current component. Not necessarily in Path.
			size_t Position; ///< The iterators current position within Path.
			// An end iterator has Position = Path.size() + 1.
			friend const_iterator begin(StringRef path);
			friend const_iterator end(StringRef path);
			public:
			typedef const StringRef value_type;
			typedef ptrdiff_t difference_type;
			typedef value_type &reference;
			typedef value_type *pointer;
			typedef std::bidirectional_iterator_tag iterator_category;
			reference operator*() const { return Component; }
			pointer operator->() const { return &Component; }
			const_iterator &operator++(); // preincrement
			const_iterator &operator++(int); // postincrement
			const_iterator &operator--(); // predecrement
			const_iterator &operator--(int); // postdecrement
			bool operator==(const const_iterator &RHS) const;
			bool operator!=(const const_iterator &RHS) const;
			/// @brief Difference in bytes between this and RHS.
			ptrdiff_t operator-(const const_iterator &RHS) const;
			};
			typedef std::reverse_iterator<const_iterator> reverse_iterator;
			/// @brief Get begin iterator over \a path.
			/// @param path Input path.
			/// @returns Iterator initialized with the first component of \a path.
			const_iterator begin(StringRef path);
			/// @brief Get end iterator over \a path.
			/// @param path Input path.
			/// @returns Iterator initialized to the end of \a path.
			const_iterator end(StringRef path);
			/// @brief Get reverse begin iterator over \a path.
			/// @param path Input path.
			/// @returns Iterator initialized with the first reverse component of \a pa
			th.
			inline reverse_iterator rbegin(StringRef path) {
			return reverse_iterator(end(path));
			}
			/// @brief Get reverse end iterator over \a path.
			/// @param path Input path.
			/// @returns Iterator initialized to the reverse end of \a path.
			inline reverse_iterator rend(StringRef path) {
			return reverse_iterator(begin(path));
			}
			/// @}
			/// @name Lexical Modifiers
			/// @{
			/// @brief Remove the last component from \a path unless it is the root dir
			.
			///
			/// @code
			/// directory/filename.cpp => directory/
			/// directory/ => directory
			/// filename.cpp => <empty>
			/// / => /
			/// @endcode
			///
			/// @param path A path that is modified to not have a file component.
			void remove_filename(SmallVectorImpl<char> &path);
			/// @brief Replace the file extension of \a path with \a extension.
			///
			/// @code
			/// ./filename.cpp => ./filename.extension
			/// ./filename => ./filename.extension
			/// ./ => ./.extension
			/// @endcode
			///
			/// @param path A path that has its extension replaced with \a extension.
			/// @param extension The extension to be added. It may be empty. It may als
			o
			/// optionally start with a '.', if it does not, one will
			be
			/// prepended.
			void replace_extension(SmallVectorImpl<char> &path, const Twine &extension)
			;
			/// @brief Append to path.
			///
			/// @code
			/// /foo + bar/f => /foo/bar/f
			/// /foo/ + bar/f => /foo/bar/f
			/// foo + bar/f => foo/bar/f
			/// @endcode
			///
			/// @param path Set to \a path + \a component.
			/// @param a The component to be appended to \a path.
			void append(SmallVectorImpl<char> &path, const Twine &a,
			const Twine &b = "",
			const Twine &c = "",
			const Twine &d = "");
			/// @brief Append to path.
			///
			/// @code
			/// /foo + [bar,f] => /foo/bar/f
			/// /foo/ + [bar,f] => /foo/bar/f
			/// foo + [bar,f] => foo/bar/f
			/// @endcode
			///
			/// @param path Set to \a path + [\a begin, \a end).
			/// @param begin Start of components to append.
			/// @param end One past the end of components to append.
			void append(SmallVectorImpl<char> &path,
			const_iterator begin, const_iterator end);
			/// @}
			/// @name Transforms (or some other better name)
			/// @{
			/// Convert path to the native form. This is used to give paths to users an
			d
			/// operating system calls in the platform's normal way. For example, on Wi
			ndows
			/// all '/' are converted to '\'.
			///
			/// @param path A path that is transformed to native format.
			/// @param result Holds the result of the transformation.
			void native(const Twine &path, SmallVectorImpl<char> &result);
			/// Convert path to the native form in place. This is used to give paths to
			/// users and operating system calls in the platform's normal way. For exam
			ple,
			/// on Windows all '/' are converted to '\'.
			///
			/// @param path A path that is transformed to native format.
			void native(SmallVectorImpl<char> &path);
			/// @}
			/// @name Lexical Observers
			/// @{
			/// @brief Get root name.
			///
			/// @code
			/// //net/hello => //net
			/// c:/hello => c: (on Windows, on other platforms nothing)
			/// /hello => <empty>
			/// @endcode
			///
			/// @param path Input path.
			/// @result The root name of \a path if it has one, otherwise "".
			const StringRef root_name(StringRef path);
			/// @brief Get root directory.
			///
			/// @code
			/// /goo/hello => /
			/// c:/hello => /
			/// d/file.txt => <empty>
			/// @endcode
			///
			/// @param path Input path.
			/// @result The root directory of \a path if it has one, otherwise
			/// "".
			const StringRef root_directory(StringRef path);
			/// @brief Get root path.
			///
			/// Equivalent to root_name + root_directory.
			///
			/// @param path Input path.
			/// @result The root path of \a path if it has one, otherwise "".
			const StringRef root_path(StringRef path);
			/// @brief Get relative path.
			///
			/// @code
			/// C:\hello\world => hello\world
			/// foo/bar => foo/bar
			/// /foo/bar => foo/bar
			/// @endcode
			///
			/// @param path Input path.
			/// @result The path starting after root_path if one exists, otherwise "".
			const StringRef relative_path(StringRef path);
			/// @brief Get parent path.
			///
			/// @code
			/// / => <empty>
			/// /foo => /
			/// foo/../bar => foo/..
			/// @endcode
			///
			/// @param path Input path.
			/// @result The parent path of \a path if one exists, otherwise "".
			const StringRef parent_path(StringRef path);
			/// @brief Get filename.
			///
			/// @code
			/// /foo.txt => foo.txt
			/// . => .
			/// .. => ..
			/// / => /
			/// @endcode
			///
			/// @param path Input path.
			/// @result The filename part of \a path. This is defined as the last compo
			nent
			/// of \a path.
			const StringRef filename(StringRef path);
			/// @brief Get stem.
			///
			/// If filename contains a dot but not solely one or two dots, result is th
			e
			/// substring of filename ending at (but not including) the last dot. Other
			wise
			/// it is filename.
			///
			/// @code
			/// /foo/bar.txt => bar
			/// /foo/bar => bar
			/// /foo/.txt => <empty>
			/// /foo/. => .
			/// /foo/.. => ..
			/// @endcode
			///
			/// @param path Input path.
			/// @result The stem of \a path.
			const StringRef stem(StringRef path);
			/// @brief Get extension.
			///
			/// If filename contains a dot but not solely one or two dots, result is th
			e
			/// substring of filename starting at (and including) the last dot, and end
			ing
			/// at the end of \a path. Otherwise "".
			///
			/// @code
			/// /foo/bar.txt => .txt
			/// /foo/bar => <empty>
			/// /foo/.txt => .txt
			/// @endcode
			///
			/// @param path Input path.
			/// @result The extension of \a path.
			const StringRef extension(StringRef path);
			/// @brief Check whether the given char is a path separator on the host OS.
			///
			/// @param value a character
			/// @result true if \a value is a path separator character on the host OS
			bool is_separator(char value);
			/// @brief Get the typical temporary directory for the system, e.g.,
			/// "/var/tmp" or "C:/TEMP"
			///
			/// @param erasedOnReboot Whether to favor a path that is erased on reboot
			/// rather than one that potentially persists longer. This parameter will b
			e
			/// ignored if the user or system has set the typical environment variable
			/// (e.g., TEMP on Windows, TMPDIR on *nix) to specify a temporary director
			y.
			///
			/// @param result Holds the resulting path name.
			void system_temp_directory(bool erasedOnReboot, SmallVectorImpl<char> &resu
			lt);
			/// @brief Has root name?
			///
			/// root_name != ""
			///
			/// @param path Input path.
			/// @result True if the path has a root name, false otherwise.
			bool has_root_name(const Twine &path);
			/// @brief Has root directory?
			///
			/// root_directory != ""
			///
			/// @param path Input path.
			/// @result True if the path has a root directory, false otherwise.
			bool has_root_directory(const Twine &path);
			/// @brief Has root path?
			///
			/// root_path != ""
			///
			/// @param path Input path.
			/// @result True if the path has a root path, false otherwise.
			bool has_root_path(const Twine &path);
			/// @brief Has relative path?
			///
			/// relative_path != ""
			///
			/// @param path Input path.
			/// @result True if the path has a relative path, false otherwise.
			bool has_relative_path(const Twine &path);
			/// @brief Has parent path?
			///
			/// parent_path != ""
			///
			/// @param path Input path.
			/// @result True if the path has a parent path, false otherwise.
			bool has_parent_path(const Twine &path);
			/// @brief Has filename?
			///
			/// filename != ""
			///
			/// @param path Input path.
			/// @result True if the path has a filename, false otherwise.
			bool has_filename(const Twine &path);
			/// @brief Has stem?
			///
			/// stem != ""
			///
			/// @param path Input path.
			/// @result True if the path has a stem, false otherwise.
			bool has_stem(const Twine &path);
			/// @brief Has extension?
			///
			/// extension != ""
			///
			/// @param path Input path.
			/// @result True if the path has a extension, false otherwise.
			bool has_extension(const Twine &path);
			/// @brief Is path absolute?
			///
			/// @param path Input path.
			/// @result True if the path is absolute, false if it is not.
			bool is_absolute(const Twine &path);
			/// @brief Is path relative?
			///
			/// @param path Input path.
			/// @result True if the path is relative, false if it is not.
			bool is_relative(const Twine &path);
			} // end namespace path
			} // end namespace sys
			} // end namespace llvm
			#endif
End of changes. 2 change blocks.
	2 lines changed or deleted		4 lines changed or added

	PatternMatch.h		PatternMatch.h
	skipping to change at line 694		skipping to change at line 694
	/// m_ZExt		/// m_ZExt
	template<typename OpTy>		template<typename OpTy>
	inline CastClass_match<OpTy, Instruction::ZExt>		inline CastClass_match<OpTy, Instruction::ZExt>
	m_ZExt(const OpTy &Op) {		m_ZExt(const OpTy &Op) {
	return CastClass_match<OpTy, Instruction::ZExt>(Op);		return CastClass_match<OpTy, Instruction::ZExt>(Op);
	}		}
	/// m_UIToFP		/// m_UIToFP
	template<typename OpTy>		template<typename OpTy>
	inline CastClass_match<OpTy, Instruction::UIToFP>		inline CastClass_match<OpTy, Instruction::UIToFP>
	m_UIToFp(const OpTy &Op) {		m_UIToFP(const OpTy &Op) {
	return CastClass_match<OpTy, Instruction::UIToFP>(Op);		return CastClass_match<OpTy, Instruction::UIToFP>(Op);
	}		}
			/// m_SIToFP
			template<typename OpTy>
			inline CastClass_match<OpTy, Instruction::SIToFP>
			m_SIToFP(const OpTy &Op) {
			return CastClass_match<OpTy, Instruction::SIToFP>(Op);
			}
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// Matchers for unary operators		// Matchers for unary operators
	//		//
	template<typename LHS_t>		template<typename LHS_t>
	struct not_match {		struct not_match {
	LHS_t L;		LHS_t L;
	not_match(const LHS_t &LHS) : L(LHS) {}		not_match(const LHS_t &LHS) : L(LHS) {}
	skipping to change at line 1028		skipping to change at line 1035
	/// Match an argument		/// Match an argument
	template<unsigned OpI, typename Opnd_t>		template<unsigned OpI, typename Opnd_t>
	inline Argument_match<Opnd_t> m_Argument(const Opnd_t &Op) {		inline Argument_match<Opnd_t> m_Argument(const Opnd_t &Op) {
	return Argument_match<Opnd_t>(OpI, Op);		return Argument_match<Opnd_t>(OpI, Op);
	}		}
	/// Intrinsic matchers.		/// Intrinsic matchers.
	struct IntrinsicID_match {		struct IntrinsicID_match {
	unsigned ID;		unsigned ID;
	IntrinsicID_match(unsigned IntrID) : ID(IntrID) { }		IntrinsicID_match(Intrinsic::ID IntrID) : ID(IntrID) { }
	template<typename OpTy>		template<typename OpTy>
	bool match(OpTy *V) {		bool match(OpTy *V) {
	IntrinsicInst *II = dyn_cast<IntrinsicInst>(V);		IntrinsicInst *II = dyn_cast<IntrinsicInst>(V);
	return II && II->getIntrinsicID() == ID;		return II && II->getIntrinsicID() == ID;
	}		}
	};		};
	/// Intrinsic matches are combinations of ID matchers, and argument		/// Intrinsic matches are combinations of ID matchers, and argument
	/// matchers. Higher arity matcher are defined recursively in terms of and- ing		/// matchers. Higher arity matcher are defined recursively in terms of and- ing
	skipping to change at line 1067		skipping to change at line 1074
	Argument_match<T2> > Ty;		Argument_match<T2> > Ty;
	};		};
	template <typename T0, typename T1, typename T2, typename T3>		template <typename T0, typename T1, typename T2, typename T3>
	struct m_Intrinsic_Ty<T0, T1, T2, T3> {		struct m_Intrinsic_Ty<T0, T1, T2, T3> {
	typedef match_combine_and<typename m_Intrinsic_Ty<T0, T1, T2>::Ty,		typedef match_combine_and<typename m_Intrinsic_Ty<T0, T1, T2>::Ty,
	Argument_match<T3> > Ty;		Argument_match<T3> > Ty;
	};		};
	/// Match intrinsic calls like this:		/// Match intrinsic calls like this:
	/// m_Intrinsic<Intrinsic::fabs>(m_Value(X))		/// m_Intrinsic<Intrinsic::fabs>(m_Value(X))
	template <unsigned IntrID>		template <Intrinsic::ID IntrID>
	inline IntrinsicID_match		inline IntrinsicID_match
	m_Intrinsic() { return IntrinsicID_match(IntrID); }		m_Intrinsic() { return IntrinsicID_match(IntrID); }
	template<unsigned IntrID, typename T0>		template<Intrinsic::ID IntrID, typename T0>
	inline typename m_Intrinsic_Ty<T0>::Ty		inline typename m_Intrinsic_Ty<T0>::Ty
	m_Intrinsic(const T0 &Op0) {		m_Intrinsic(const T0 &Op0) {
	return m_CombineAnd(m_Intrinsic<IntrID>(), m_Argument<0>(Op0));		return m_CombineAnd(m_Intrinsic<IntrID>(), m_Argument<0>(Op0));
	}		}
	template<unsigned IntrID, typename T0, typename T1>		template<Intrinsic::ID IntrID, typename T0, typename T1>
	inline typename m_Intrinsic_Ty<T0, T1>::Ty		inline typename m_Intrinsic_Ty<T0, T1>::Ty
	m_Intrinsic(const T0 &Op0, const T1 &Op1) {		m_Intrinsic(const T0 &Op0, const T1 &Op1) {
	return m_CombineAnd(m_Intrinsic<IntrID>(Op0), m_Argument<1>(Op1));		return m_CombineAnd(m_Intrinsic<IntrID>(Op0), m_Argument<1>(Op1));
	}		}
	template<unsigned IntrID, typename T0, typename T1, typename T2>		template<Intrinsic::ID IntrID, typename T0, typename T1, typename T2>
	inline typename m_Intrinsic_Ty<T0, T1, T2>::Ty		inline typename m_Intrinsic_Ty<T0, T1, T2>::Ty
	m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2) {		m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2) {
	return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1), m_Argument<2>(Op2));		return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1), m_Argument<2>(Op2));
	}		}
	template<unsigned IntrID, typename T0, typename T1, typename T2, typename T 3>		template<Intrinsic::ID IntrID, typename T0, typename T1, typename T2, typen ame T3>
	inline typename m_Intrinsic_Ty<T0, T1, T2, T3>::Ty		inline typename m_Intrinsic_Ty<T0, T1, T2, T3>::Ty
	m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) {		m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) {
	return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3 ));		return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3 ));
	}		}
	// Helper intrinsic matching specializations		// Helper intrinsic matching specializations
	template<typename Opnd0>		template<typename Opnd0>
	inline typename m_Intrinsic_Ty<Opnd0>::Ty		inline typename m_Intrinsic_Ty<Opnd0>::Ty
	m_BSwap(const Opnd0 &Op0) {		m_BSwap(const Opnd0 &Op0) {
	return m_Intrinsic<Intrinsic::bswap>(Op0);		return m_Intrinsic<Intrinsic::bswap>(Op0);
End of changes. 8 change blocks.
	7 lines changed or deleted		14 lines changed or added

	PointerIntPair.h		PointerIntPair.h
	skipping to change at line 17		skipping to change at line 17
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This file defines the PointerIntPair class.		// This file defines the PointerIntPair class.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_ADT_POINTERINTPAIR_H		#ifndef LLVM_ADT_POINTERINTPAIR_H
	#define LLVM_ADT_POINTERINTPAIR_H		#define LLVM_ADT_POINTERINTPAIR_H
			#include "llvm/Support/Compiler.h"
	#include "llvm/Support/PointerLikeTypeTraits.h"		#include "llvm/Support/PointerLikeTypeTraits.h"
	#include <cassert>		#include <cassert>
	namespace llvm {		namespace llvm {
	template<typename T>		template<typename T>
	struct DenseMapInfo;		struct DenseMapInfo;
	/// PointerIntPair - This class implements a pair of a pointer and small		/// PointerIntPair - This class implements a pair of a pointer and small
	/// integer. It is designed to represent this in the space required by one		/// integer. It is designed to represent this in the space required by one
	skipping to change at line 43		skipping to change at line 44
	/// possible. For example, PointerIntPair<void*, 1, bool> will put the bit for		/// possible. For example, PointerIntPair<void*, 1, bool> will put the bit for
	/// the bool into bit #2, not bit #0, which allows the low two bits to be u sed		/// the bool into bit #2, not bit #0, which allows the low two bits to be u sed
	/// for something else. For example, this allows:		/// for something else. For example, this allows:
	/// PointerIntPair<PointerIntPair<void*, 1, bool>, 1, bool>		/// PointerIntPair<PointerIntPair<void*, 1, bool>, 1, bool>
	/// ... and the two bools will land in different bits.		/// ... and the two bools will land in different bits.
	///		///
	template <typename PointerTy, unsigned IntBits, typename IntType=unsigned,		template <typename PointerTy, unsigned IntBits, typename IntType=unsigned,
	typename PtrTraits = PointerLikeTypeTraits<PointerTy> >		typename PtrTraits = PointerLikeTypeTraits<PointerTy> >
	class PointerIntPair {		class PointerIntPair {
	intptr_t Value;		intptr_t Value;
	enum {		enum LLVM_ENUM_INT_TYPE(uintptr_t) {
	/// PointerBitMask - The bits that come from the pointer.		/// PointerBitMask - The bits that come from the pointer.
	PointerBitMask =		PointerBitMask =
	~(uintptr_t)(((intptr_t)1 << PtrTraits::NumLowBitsAvailable)-1),		~(uintptr_t)(((intptr_t)1 << PtrTraits::NumLowBitsAvailable)-1),
	/// IntShift - The number of low bits that we reserve for other uses, a nd		/// IntShift - The number of low bits that we reserve for other uses, a nd
	/// keep zero.		/// keep zero.
	IntShift = (uintptr_t)PtrTraits::NumLowBitsAvailable-IntBits,		IntShift = (uintptr_t)PtrTraits::NumLowBitsAvailable-IntBits,
	/// IntMask - This is the unshifted mask for valid bits of the int type .		/// IntMask - This is the unshifted mask for valid bits of the int type .
	IntMask = (uintptr_t)(((intptr_t)1 << IntBits)-1),		IntMask = (uintptr_t)(((intptr_t)1 << IntBits)-1),
End of changes. 2 change blocks.
	1 lines changed or deleted		2 lines changed or added

	PointerUnion.h		PointerUnion.h
	skipping to change at line 18		skipping to change at line 18
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This file defines the PointerUnion class, which is a discriminated union of		// This file defines the PointerUnion class, which is a discriminated union of
	// pointer types.		// pointer types.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_ADT_POINTERUNION_H		#ifndef LLVM_ADT_POINTERUNION_H
	#define LLVM_ADT_POINTERUNION_H		#define LLVM_ADT_POINTERUNION_H
			#include "llvm/Support/Compiler.h"
	#include "llvm/ADT/PointerIntPair.h"		#include "llvm/ADT/PointerIntPair.h"
	namespace llvm {		namespace llvm {
	template <typename T>		template <typename T>
	struct PointerUnionTypeSelectorReturn {		struct PointerUnionTypeSelectorReturn {
	typedef T Return;		typedef T Return;
	};		};
	/// \brief Get a type based on whether two types are the same or not. For :		/// \brief Get a type based on whether two types are the same or not. For :
	skipping to change at line 74		skipping to change at line 75
	/// and keeps the discriminator bit-mangled into the low bits of the poin ter.		/// and keeps the discriminator bit-mangled into the low bits of the poin ter.
	/// This allows the implementation to be extremely efficient in space, bu t		/// This allows the implementation to be extremely efficient in space, bu t
	/// permits a very natural and type-safe API.		/// permits a very natural and type-safe API.
	///		///
	/// Common use patterns would be something like this:		/// Common use patterns would be something like this:
	/// PointerUnion<int*, float*> P;		/// PointerUnion<int*, float*> P;
	/// P = (int*)0;		/// P = (int*)0;
	/// printf("%d %d", P.is<int*>(), P.is<float*>()); // prints "1 0"		/// printf("%d %d", P.is<int*>(), P.is<float*>()); // prints "1 0"
	/// X = P.get<int*>(); // ok.		/// X = P.get<int*>(); // ok.
	/// Y = P.get<float*>(); // runtime assertion failure.		/// Y = P.get<float*>(); // runtime assertion failure.
	/// Z = P.get<double*>(); // runtime assertion failure (regardless of tag)		/// Z = P.get<double*>(); // compile time failure.
	/// P = (float*)0;		/// P = (float*)0;
	/// Y = P.get<float*>(); // ok.		/// Y = P.get<float*>(); // ok.
	/// X = P.get<int*>(); // runtime assertion failure.		/// X = P.get<int*>(); // runtime assertion failure.
	template <typename PT1, typename PT2>		template <typename PT1, typename PT2>
	class PointerUnion {		class PointerUnion {
	public:		public:
	typedef PointerIntPair<void*, 1, bool,		typedef PointerIntPair<void*, 1, bool,
	PointerUnionUIntTraits<PT1,PT2> > ValTy;		PointerUnionUIntTraits<PT1,PT2> > ValTy;
	private:		private:
	ValTy Val;		ValTy Val;
	skipping to change at line 112		skipping to change at line 113
	const_cast<void *>(PointerLikeTypeTraits<PT2>::getAsVoidPointer(V)), 1) {		const_cast<void *>(PointerLikeTypeTraits<PT2>::getAsVoidPointer(V)), 1) {
	}		}
	/// isNull - Return true if the pointer held in the union is null,		/// isNull - Return true if the pointer held in the union is null,
	/// regardless of which type it is.		/// regardless of which type it is.
	bool isNull() const {		bool isNull() const {
	// Convert from the void* to one of the pointer types, to make sure t hat		// Convert from the void* to one of the pointer types, to make sure t hat
	// we recursively strip off low bits if we have a nested PointerUnion .		// we recursively strip off low bits if we have a nested PointerUnion .
	return !PointerLikeTypeTraits<PT1>::getFromVoidPointer(Val.getPointer ());		return !PointerLikeTypeTraits<PT1>::getFromVoidPointer(Val.getPointer ());
	}		}
	operator bool() const { return !isNull(); }		LLVM_EXPLICIT operator bool() const { return !isNull(); }
	/// is<T>() return true if the Union currently holds the type matching T.		/// is<T>() return true if the Union currently holds the type matching T.
	template<typename T>		template<typename T>
	int is() const {		int is() const {
	typedef typename		typedef typename
	::llvm::PointerUnionTypeSelector<PT1, T, IsPT1,		::llvm::PointerUnionTypeSelector<PT1, T, IsPT1,
	::llvm::PointerUnionTypeSelector<PT2, T, IsPT2,		::llvm::PointerUnionTypeSelector<PT2, T, IsPT2,
	UNION_DOESNT_CONTAIN_TYPE<T> > >::Retur n Ty;		UNION_DOESNT_CONTAIN_TYPE<T> > >::Retur n Ty;
	int TyNo = Ty::Num;		int TyNo = Ty::Num;
	return static_cast<int>(Val.getInt()) == TyNo;		return static_cast<int>(Val.getInt()) == TyNo;
	skipping to change at line 178		skipping to change at line 179
	}		}
	void *getOpaqueValue() const { return Val.getOpaqueValue(); }		void *getOpaqueValue() const { return Val.getOpaqueValue(); }
	static inline PointerUnion getFromOpaqueValue(void *VP) {		static inline PointerUnion getFromOpaqueValue(void *VP) {
	PointerUnion V;		PointerUnion V;
	V.Val = ValTy::getFromOpaqueValue(VP);		V.Val = ValTy::getFromOpaqueValue(VP);
	return V;		return V;
	}		}
	};		};
			template<typename PT1, typename PT2>
			static bool operator==(PointerUnion<PT1, PT2> lhs,
			PointerUnion<PT1, PT2> rhs) {
			return lhs.getOpaqueValue() == rhs.getOpaqueValue();
			}
			template<typename PT1, typename PT2>
			static bool operator!=(PointerUnion<PT1, PT2> lhs,
			PointerUnion<PT1, PT2> rhs) {
			return lhs.getOpaqueValue() != rhs.getOpaqueValue();
			}
	// Teach SmallPtrSet that PointerUnion is "basically a pointer", that has		// Teach SmallPtrSet that PointerUnion is "basically a pointer", that has
	// # low bits available = min(PT1bits,PT2bits)-1.		// # low bits available = min(PT1bits,PT2bits)-1.
	template<typename PT1, typename PT2>		template<typename PT1, typename PT2>
	class PointerLikeTypeTraits<PointerUnion<PT1, PT2> > {		class PointerLikeTypeTraits<PointerUnion<PT1, PT2> > {
	public:		public:
	static inline void *		static inline void *
	getAsVoidPointer(const PointerUnion<PT1, PT2> &P) {		getAsVoidPointer(const PointerUnion<PT1, PT2> &P) {
	return P.getOpaqueValue();		return P.getOpaqueValue();
	}		}
	static inline PointerUnion<PT1, PT2>		static inline PointerUnion<PT1, PT2>
	skipping to change at line 253		skipping to change at line 266
	PointerUnion3(PT2 V) {		PointerUnion3(PT2 V) {
	Val = InnerUnion(V);		Val = InnerUnion(V);
	}		}
	PointerUnion3(PT3 V) {		PointerUnion3(PT3 V) {
	Val = V;		Val = V;
	}		}
	/// isNull - Return true if the pointer held in the union is null,		/// isNull - Return true if the pointer held in the union is null,
	/// regardless of which type it is.		/// regardless of which type it is.
	bool isNull() const { return Val.isNull(); }		bool isNull() const { return Val.isNull(); }
	operator bool() const { return !isNull(); }		LLVM_EXPLICIT operator bool() const { return !isNull(); }
	/// is<T>() return true if the Union currently holds the type matching T.		/// is<T>() return true if the Union currently holds the type matching T.
	template<typename T>		template<typename T>
	int is() const {		int is() const {
	// If T is PT1/PT2 choose IsInnerUnion otherwise choose IsPT3.		// If T is PT1/PT2 choose IsInnerUnion otherwise choose IsPT3.
	typedef typename		typedef typename
	::llvm::PointerUnionTypeSelector<PT1, T, IsInnerUnion,		::llvm::PointerUnionTypeSelector<PT1, T, IsInnerUnion,
	::llvm::PointerUnionTypeSelector<PT2, T, IsInnerUnion, IsPT3 >		::llvm::PointerUnionTypeSelector<PT2, T, IsInnerUnion, IsPT3 >
	>::Retur n Ty;		>::Retur n Ty;
	return Ty(Val).template is<T>();		return Ty(Val).template is<T>();
	skipping to change at line 361		skipping to change at line 374
	PointerUnion4(PT3 V) {		PointerUnion4(PT3 V) {
	Val = InnerUnion2(V);		Val = InnerUnion2(V);
	}		}
	PointerUnion4(PT4 V) {		PointerUnion4(PT4 V) {
	Val = InnerUnion2(V);		Val = InnerUnion2(V);
	}		}
	/// isNull - Return true if the pointer held in the union is null,		/// isNull - Return true if the pointer held in the union is null,
	/// regardless of which type it is.		/// regardless of which type it is.
	bool isNull() const { return Val.isNull(); }		bool isNull() const { return Val.isNull(); }
	operator bool() const { return !isNull(); }		LLVM_EXPLICIT operator bool() const { return !isNull(); }
	/// is<T>() return true if the Union currently holds the type matching T.		/// is<T>() return true if the Union currently holds the type matching T.
	template<typename T>		template<typename T>
	int is() const {		int is() const {
	// If T is PT1/PT2 choose InnerUnion1 otherwise choose InnerUnion2.		// If T is PT1/PT2 choose InnerUnion1 otherwise choose InnerUnion2.
	typedef typename		typedef typename
	::llvm::PointerUnionTypeSelector<PT1, T, InnerUnion1,		::llvm::PointerUnionTypeSelector<PT1, T, InnerUnion1,
	::llvm::PointerUnionTypeSelector<PT2, T, InnerUnion1, InnerUnion2 >		::llvm::PointerUnionTypeSelector<PT2, T, InnerUnion1, InnerUnion2 >
	>::Retur n Ty;		>::Retur n Ty;
	return Val.template is<Ty>() &&		return Val.template is<Ty>() &&
End of changes. 6 change blocks.
	4 lines changed or deleted		17 lines changed or added

	PostDominators.h		PostDominators.h
	skipping to change at line 77		skipping to change at line 77
	}		}
	inline bool properlyDominates(BasicBlock* A, BasicBlock* B) const {		inline bool properlyDominates(BasicBlock* A, BasicBlock* B) const {
	return DT->properlyDominates(A, B);		return DT->properlyDominates(A, B);
	}		}
	inline BasicBlock *findNearestCommonDominator(BasicBlock *A, BasicBlock * B) {		inline BasicBlock *findNearestCommonDominator(BasicBlock *A, BasicBlock * B) {
	return DT->findNearestCommonDominator(A, B);		return DT->findNearestCommonDominator(A, B);
	}		}
			inline const BasicBlock *findNearestCommonDominator(const BasicBlock *A,
			const BasicBlock *B)
			{
			return DT->findNearestCommonDominator(A, B);
			}
	virtual void releaseMemory() {		virtual void releaseMemory() {
	DT->releaseMemory();		DT->releaseMemory();
	}		}
	virtual void print(raw_ostream &OS, const Module*) const;		virtual void print(raw_ostream &OS, const Module*) const;
	};		};
	FunctionPass* createPostDomTree();		FunctionPass* createPostDomTree();
	template <> struct GraphTraits<PostDominatorTree*>		template <> struct GraphTraits<PostDominatorTree*>
End of changes. 1 change blocks.
	0 lines changed or deleted		6 lines changed or added

	PrettyStackTrace.h		PrettyStackTrace.h
	skipping to change at line 24		skipping to change at line 24
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_SUPPORT_PRETTYSTACKTRACE_H		#ifndef LLVM_SUPPORT_PRETTYSTACKTRACE_H
	#define LLVM_SUPPORT_PRETTYSTACKTRACE_H		#define LLVM_SUPPORT_PRETTYSTACKTRACE_H
	#include "llvm/Support/Compiler.h"		#include "llvm/Support/Compiler.h"
	namespace llvm {		namespace llvm {
	class raw_ostream;		class raw_ostream;
	/// DisablePrettyStackTrace - Set this to true to disable this module. Th		void EnablePrettyStackTrace();
	is
	/// might be necessary if the host application installs its own signal
	/// handlers which conflict with the ones installed by this module.
	/// Defaults to false.
	extern bool DisablePrettyStackTrace;
	/// PrettyStackTraceEntry - This class is used to represent a frame of th e		/// PrettyStackTraceEntry - This class is used to represent a frame of th e
	/// "pretty" stack trace that is dumped when a program crashes. You can d efine		/// "pretty" stack trace that is dumped when a program crashes. You can d efine
	/// subclasses of this and declare them on the program stack: when they a re		/// subclasses of this and declare them on the program stack: when they a re
	/// constructed and destructed, they will add their symbolic frames to a		/// constructed and destructed, they will add their symbolic frames to a
	/// virtual stack trace. This gets dumped out if the program crashes.		/// virtual stack trace. This gets dumped out if the program crashes.
	class PrettyStackTraceEntry {		class PrettyStackTraceEntry {
	const PrettyStackTraceEntry *NextEntry;		const PrettyStackTraceEntry *NextEntry;
	PrettyStackTraceEntry(const PrettyStackTraceEntry &) LLVM_DELETED_FUNCT ION;		PrettyStackTraceEntry(const PrettyStackTraceEntry &) LLVM_DELETED_FUNCT ION;
	void operator=(const PrettyStackTraceEntry&) LLVM_DELETED_FUNCTION;		void operator=(const PrettyStackTraceEntry&) LLVM_DELETED_FUNCTION;
	skipping to change at line 67		skipping to change at line 63
	virtual void print(raw_ostream &OS) const LLVM_OVERRIDE;		virtual void print(raw_ostream &OS) const LLVM_OVERRIDE;
	};		};
	/// PrettyStackTraceProgram - This object prints a specified program argu ments		/// PrettyStackTraceProgram - This object prints a specified program argu ments
	/// to the stream as the stack trace when a crash occurs.		/// to the stream as the stack trace when a crash occurs.
	class PrettyStackTraceProgram : public PrettyStackTraceEntry {		class PrettyStackTraceProgram : public PrettyStackTraceEntry {
	int ArgC;		int ArgC;
	const char *const *ArgV;		const char *const *ArgV;
	public:		public:
	PrettyStackTraceProgram(int argc, const char * const*argv)		PrettyStackTraceProgram(int argc, const char * const*argv)
	: ArgC(argc), ArgV(argv) {}		: ArgC(argc), ArgV(argv) {
			EnablePrettyStackTrace();
			}
	virtual void print(raw_ostream &OS) const LLVM_OVERRIDE;		virtual void print(raw_ostream &OS) const LLVM_OVERRIDE;
	};		};
	} // end namespace llvm		} // end namespace llvm
	#endif		#endif
End of changes. 2 change blocks.
	7 lines changed or deleted		4 lines changed or added

	Process.h		Process.h
	skipping to change at line 28		skipping to change at line 28
	/// This file declares the llvm::sys::Process class which contains a collec tion		/// This file declares the llvm::sys::Process class which contains a collec tion
	/// of legacy static interfaces for extracting various information about th e		/// of legacy static interfaces for extracting various information about th e
	/// current process. The goal is to migrate users of this API over to the n ew		/// current process. The goal is to migrate users of this API over to the n ew
	/// interfaces.		/// interfaces.
	///		///
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_SUPPORT_PROCESS_H		#ifndef LLVM_SUPPORT_PROCESS_H
	#define LLVM_SUPPORT_PROCESS_H		#define LLVM_SUPPORT_PROCESS_H
			#include "llvm/ADT/ArrayRef.h"
			#include "llvm/ADT/Optional.h"
	#include "llvm/Config/llvm-config.h"		#include "llvm/Config/llvm-config.h"
			#include "llvm/Support/Allocator.h"
			#include "llvm/Support/system_error.h"
	#include "llvm/Support/DataTypes.h"		#include "llvm/Support/DataTypes.h"
	#include "llvm/Support/TimeValue.h"		#include "llvm/Support/TimeValue.h"
	namespace llvm {		namespace llvm {
			class StringRef;
	namespace sys {		namespace sys {
	class self_process;		class self_process;
	/// \brief Generic base class which exposes information about an operating		/// \brief Generic base class which exposes information about an operating
	/// system process.		/// system process.
	///		///
	/// This base class is the core interface behind any OS process. It exposes		/// This base class is the core interface behind any OS process. It exposes
	/// methods to query for generic information about a particular process.		/// methods to query for generic information about a particular process.
	///		///
	/// Subclasses implement this interface based on the mechanisms available, and		/// Subclasses implement this interface based on the mechanisms available, and
	/// can optionally expose more interfaces unique to certain process kinds.		/// can optionally expose more interfaces unique to certain process kinds.
	class process {		class process {
	protected:		protected:
	/// \brief Only specific subclasses of process objects can be destroyed.		/// \brief Only specific subclasses of process objects can be destroyed.
	virtual ~process();		virtual ~process();
	public:		public:
	/// \brief Operating system specific type to identify a process.		/// \brief Operating system specific type to identify a process.
	///		///
	/// Note that the windows one is defined to 'void *' as this is the		/// Note that the windows one is defined to 'unsigned long' as this is th
	/// documented type for HANDLE on windows, and we don't want to pull in t		e
	he		/// documented type for DWORD on windows, and we don't want to pull in th
			e
	/// Windows headers here.		/// Windows headers here.
	#if defined(LLVM_ON_UNIX)		#if defined(LLVM_ON_UNIX)
	typedef pid_t id_type;		typedef pid_t id_type;
	#elif defined(LLVM_ON_WIN32)		#elif defined(LLVM_ON_WIN32)
	typedef void *id_type; // Must match the type of HANDLE.		typedef unsigned long id_type; // Must match the type of DWORD.
	#else		#else
	#error Unsupported operating system.		#error Unsupported operating system.
	#endif		#endif
	/// \brief Get the operating system specific identifier for this process.		/// \brief Get the operating system specific identifier for this process.
	virtual id_type get_id() = 0;		virtual id_type get_id() = 0;
	/// \brief Get the user time consumed by this process.		/// \brief Get the user time consumed by this process.
	///		///
	/// Note that this is often an approximation and may be zero on platforms		/// Note that this is often an approximation and may be zero on platforms
	skipping to change at line 157		skipping to change at line 163
	/// spent in user (non-kernel) mode and \p sys_time to the amount of CPU		/// spent in user (non-kernel) mode and \p sys_time to the amount of CPU
	/// time spent in system (kernel) mode. If the operating system does not		/// time spent in system (kernel) mode. If the operating system does not
	/// support collection of these metrics, a zero TimeValue will be for bot h		/// support collection of these metrics, a zero TimeValue will be for bot h
	/// values.		/// values.
	/// \param elapsed Returns the TimeValue::now() giving current time		/// \param elapsed Returns the TimeValue::now() giving current time
	/// \param user_time Returns the current amount of user time for the proc ess		/// \param user_time Returns the current amount of user time for the proc ess
	/// \param sys_time Returns the current amount of system time for the pro cess		/// \param sys_time Returns the current amount of system time for the pro cess
	static void GetTimeUsage(TimeValue &elapsed, TimeValue &user_time,		static void GetTimeUsage(TimeValue &elapsed, TimeValue &user_time,
	TimeValue &sys_time);		TimeValue &sys_time);
	/// This static function will return the process' current user id number.
	/// Not all operating systems support this feature. Where it is not
	/// supported, the function should return 65536 as the value.
	static int GetCurrentUserId();
	/// This static function will return the process' current group id number
	.
	/// Not all operating systems support this feature. Where it is not
	/// supported, the function should return 65536 as the value.
	static int GetCurrentGroupId();
	/// This function makes the necessary calls to the operating system to		/// This function makes the necessary calls to the operating system to
	/// prevent core files or any other kind of large memory dumps that can		/// prevent core files or any other kind of large memory dumps that can
	/// occur when a program fails.		/// occur when a program fails.
	/// @brief Prevent core file generation.		/// @brief Prevent core file generation.
	static void PreventCoreFiles();		static void PreventCoreFiles();
			// This function returns the environment variable \arg name's value as a
			UTF-8
			// string. \arg Name is assumed to be in UTF-8 encoding too.
			static Optional<std::string> GetEnv(StringRef name);
			/// This function returns a SmallVector containing the arguments passed f
			rom
			/// the operating system to the program. This function expects to be han
			ded
			/// the vector passed in from main.
			static error_code
			GetArgumentVector(SmallVectorImpl<const char *> &Args,
			ArrayRef<const char *> ArgsFromMain,
			SpecificBumpPtrAllocator<char> &ArgAllocator);
	/// This function determines if the standard input is connected directly		/// This function determines if the standard input is connected directly
	/// to a user's input (keyboard probably), rather than coming from a file		/// to a user's input (keyboard probably), rather than coming from a file
	/// or pipe.		/// or pipe.
	static bool StandardInIsUserInput();		static bool StandardInIsUserInput();
	/// This function determines if the standard output is connected to a		/// This function determines if the standard output is connected to a
	/// "tty" or "console" window. That is, the output would be displayed to		/// "tty" or "console" window. That is, the output would be displayed to
	/// the user rather than being put on a pipe or stored in a file.		/// the user rather than being put on a pipe or stored in a file.
	static bool StandardOutIsDisplayed();		static bool StandardOutIsDisplayed();
	skipping to change at line 221		skipping to change at line 229
	/// This function determines whether the terminal connected to standard		/// This function determines whether the terminal connected to standard
	/// output supports colors. If standard output is not connected to a		/// output supports colors. If standard output is not connected to a
	/// terminal, this function returns false.		/// terminal, this function returns false.
	static bool StandardOutHasColors();		static bool StandardOutHasColors();
	/// This function determines whether the terminal connected to standard		/// This function determines whether the terminal connected to standard
	/// error supports colors. If standard error is not connected to a		/// error supports colors. If standard error is not connected to a
	/// terminal, this function returns false.		/// terminal, this function returns false.
	static bool StandardErrHasColors();		static bool StandardErrHasColors();
			/// Enables or disables whether ANSI escape sequences are used to output
			/// colors. This only has an effect on Windows.
			/// Note: Setting this option is not thread-safe and should only be done
			/// during initialization.
			static void UseANSIEscapeCodes(bool enable);
	/// Whether changing colors requires the output to be flushed.		/// Whether changing colors requires the output to be flushed.
	/// This is needed on systems that don't support escape sequences for		/// This is needed on systems that don't support escape sequences for
	/// changing colors.		/// changing colors.
	static bool ColorNeedsFlush();		static bool ColorNeedsFlush();
	/// This function returns the colorcode escape sequences.		/// This function returns the colorcode escape sequences.
	/// If ColorNeedsFlush() is true then this function will change the color s		/// If ColorNeedsFlush() is true then this function will change the color s
	/// and return an empty escape sequence. In that case it is the		/// and return an empty escape sequence. In that case it is the
	/// responsibility of the client to flush the output stream prior to		/// responsibility of the client to flush the output stream prior to
	/// calling this function.		/// calling this function.
End of changes. 8 change blocks.
	15 lines changed or deleted		32 lines changed or added

	Program.h		Program.h
	skipping to change at line 19		skipping to change at line 19
	//		//
	// This file declares the llvm::sys::Program class.		// This file declares the llvm::sys::Program class.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_SUPPORT_PROGRAM_H		#ifndef LLVM_SUPPORT_PROGRAM_H
	#define LLVM_SUPPORT_PROGRAM_H		#define LLVM_SUPPORT_PROGRAM_H
	#include "llvm/ADT/ArrayRef.h"		#include "llvm/ADT/ArrayRef.h"
	#include "llvm/Support/Path.h"		#include "llvm/Support/Path.h"
			#include "llvm/Support/system_error.h"
	namespace llvm {		namespace llvm {
	class error_code;		class error_code;
	namespace sys {		namespace sys {
	// TODO: Add operations to communicate with the process, redirect its I/O		/// This is the OS-specific separator for PATH like environment variables
	,		:
	// etc.		// a colon on Unix or a semicolon on Windows.
			#if defined(LLVM_ON_UNIX)
			const char EnvPathSeparator = ':';
			#elif defined (LLVM_ON_WIN32)
			const char EnvPathSeparator = ';';
			#endif
			/// @brief This struct encapsulates information about a process.
			struct ProcessInfo {
			#if defined(LLVM_ON_UNIX)
			typedef pid_t ProcessId;
			#elif defined(LLVM_ON_WIN32)
			typedef unsigned long ProcessId; // Must match the type of DWORD on Windo
			ws.
			typedef void * HANDLE; // Must match the type of HANDLE on Windows.
			/// The handle to the process (available on Windows only).
			HANDLE ProcessHandle;
			#else
			#error "ProcessInfo is not defined for this platform!"
			#endif
			/// The process identifier.
			ProcessId Pid;
	/// This class provides an abstraction for programs that are executable b		/// The return code, set after execution.
	y the		int ReturnCode;
	/// operating system. It provides a platform generic way to find executab
	le		ProcessInfo();
	/// programs from the path and to execute them in various ways. The sys::		};
	Path
	/// class is used to specify the location of the Program.		/// This static constructor (factory) will attempt to locate a program in
	/// @since 1.4		/// the operating system's file system using some pre-determined set of
	/// @brief An abstraction for finding and executing programs.		/// locations to search (e.g. the PATH on Unix). Paths with slashes are
	class Program {		/// returned unmodified.
	/// Opaque handle for target specific data.		/// @returns A Path object initialized to the path of the program or a
	void *Data_;		/// Path object that is empty (invalid) if the program could not be found
			.
	// Noncopyable.		/// @brief Construct a Program by finding it by name.
	Program(const Program& other) LLVM_DELETED_FUNCTION;		std::string FindProgramByName(const std::string& name);
	Program& operator=(const Program& other) LLVM_DELETED_FUNCTION;
			// These functions change the specified standard stream (stdin, stdout, o
	/// @name Methods		r
	/// @{		// stderr) to binary mode. They return errc::success if the specified str
			eam
	Program();		// was changed. Otherwise a platform dependent error is returned.
	~Program();		error_code ChangeStdinToBinary();
			error_code ChangeStdoutToBinary();
	/// This function executes the program using the \p arguments provided.		error_code ChangeStderrToBinary();
	The
	/// invoked program will inherit the stdin, stdout, and stderr file		/// This function executes the program using the arguments provided. The
	/// descriptors, the environment and other configuration settings of th		/// invoked program will inherit the stdin, stdout, and stderr file
	e		/// descriptors, the environment and other configuration settings of the
	/// invoking program. If Path::executable() does not return true when t		/// invoking program.
	his		/// This function waits the program to finish.
	/// function is called then a std::string is thrown.		/// @returns an integer result code indicating the status of the program.
	/// @returns false in case of error, true otherwise.		/// A zero or positive value indicates the result code of the program.
	/// @see FindProgramByName		/// -1 indicates failure to execute
	/// @brief Executes the program with the given set of \p args.		/// -2 indicates a crash during execution or timeout
	bool Execute		int ExecuteAndWait(
	( const Path& path, ///< sys::Path object providing the path of the		StringRef Program, ///< Path of the program to be executed. It is
	///< program to be executed. It is presumed this is the result of		/// presumed this is the result of the FindProgramByName method.
	///< the FindProgramByName method.		const char **args, ///< A vector of strings that are passed to the
	const char** args, ///< A vector of strings that are passed to the
	///< program. The first element should be the name of the program.		///< program. The first element should be the name of the program.
	///< The list *must* be terminated by a null char* entry.		///< The list *must* be terminated by a null char* entry.
	const char ** env = 0, ///< An optional vector of strings to use for		const char **env = 0, ///< An optional vector of strings to use for
	///< the program's environment. If not provided, the current program' s		///< the program's environment. If not provided, the current program' s
	///< environment will be used.		///< environment will be used.
	const sys::Path** redirects = 0, ///< An optional array of pointers t		const StringRef **redirects = 0, ///< An optional array of pointers t
	o		o
	///< Paths. If the array is null, no redirection is done. The array		///< paths. If the array is null, no redirection is done. The array
	///< should have a size of at least three. If the pointer in the arra		///< should have a size of at least three. The inferior process's
	y		///< stdin(0), stdout(1), and stderr(2) will be redirected to the
	///< are not null, then the inferior process's stdin(0), stdout(1),		///< corresponding paths.
	///< and stderr(2) will be redirected to the corresponding Paths.		///< When an empty path is passed in, the corresponding file
	///< When an empty Path is passed in, the corresponding file
	///< descriptor will be disconnected (ie, /dev/null'd) in a portable		///< descriptor will be disconnected (ie, /dev/null'd) in a portable
	///< way.		///< way.
			unsigned secondsToWait = 0, ///< If non-zero, this specifies the amou
			nt
			///< of time to wait for the child process to exit. If the time
			///< expires, the child is killed and this call returns. If zero,
			///< this function will wait until the child finishes or forever if
			///< it doesn't.
	unsigned memoryLimit = 0, ///< If non-zero, this specifies max. amoun t		unsigned memoryLimit = 0, ///< If non-zero, this specifies max. amoun t
	///< of memory can be allocated by process. If memory usage will be		///< of memory can be allocated by process. If memory usage will be
	///< higher limit, the child is killed and this call returns. If zero		///< higher limit, the child is killed and this call returns. If zero
	///< - no memory limit.		///< - no memory limit.
	std::string* ErrMsg = 0 ///< If non-zero, provides a pointer to a str ing		std::string *ErrMsg = 0, ///< If non-zero, provides a pointer to a st ring
	///< instance in which error messages will be returned. If the string		///< instance in which error messages will be returned. If the string
	///< is non-empty upon return an error occurred while invoking the		///< is non-empty upon return an error occurred while invoking the
	///< program.		///< program.
	);		bool *ExecutionFailed = 0);
	/// This function waits for the program to exit. This function will blo
	ck
	/// the current program until the invoked program exits.
	/// @returns an integer result code indicating the status of the progra
	m.
	/// A zero or positive value indicates the result code of the program.
	/// -1 indicates failure to execute
	/// -2 indicates a crash during execution or timeout
	/// @see Execute
	/// @brief Waits for the program to exit.
	int Wait
	( const Path& path, ///< The path to the child process executable.
	unsigned secondsToWait, ///< If non-zero, this specifies the amount
	///< of time to wait for the child process to exit. If the time
	///< expires, the child is killed and this call returns. If zero,
	///< this function will wait until the child finishes or forever if
	///< it doesn't.
	std::string* ErrMsg ///< If non-zero, provides a pointer to a string
	///< instance in which error messages will be returned. If the string
	///< is non-empty upon return an error occurred while waiting.
	);
	public:
	/// This static constructor (factory) will attempt to locate a program
	in
	/// the operating system's file system using some pre-determined set of
	/// locations to search (e.g. the PATH on Unix). Paths with slashes are
	/// returned unmodified.
	/// @returns A Path object initialized to the path of the program or a
	/// Path object that is empty (invalid) if the program could not be fou
	nd.
	/// @brief Construct a Program by finding it by name.
	static Path FindProgramByName(const std::string& name);
	// These methods change the specified standard stream (stdin, stdout, o
	r
	// stderr) to binary mode. They return errc::success if the specified s
	tream
	// was changed. Otherwise a platform dependent error is returned.
	static error_code ChangeStdinToBinary();
	static error_code ChangeStdoutToBinary();
	static error_code ChangeStderrToBinary();
	/// A convenience function equivalent to Program prg; prg.Execute(..);
	/// prg.Wait(..);
	/// @see Execute, Wait
	static int ExecuteAndWait(const Path& path,
	const char** args,
	const char ** env = 0,
	const sys::Path** redirects = 0,
	unsigned secondsToWait = 0,
	unsigned memoryLimit = 0,
	std::string* ErrMsg = 0,
	bool *ExecutionFailed = 0);
	/// A convenience function equivalent to Program prg; prg.Execute(..);
	/// @see Execute
	static void ExecuteNoWait(const Path& path,
	const char** args,
	const char ** env = 0,
	const sys::Path** redirects = 0,
	unsigned memoryLimit = 0,
	std::string* ErrMsg = 0);
	/// @}
	};		/// Similar to ExecuteAndWait, but returns immediately.
			/// @returns The \see ProcessInfo of the newly launced process.
			/// \note On Microsoft Windows systems, users will need to either call \s
			ee
			/// Wait until the process finished execution or win32 CloseHandle() API
			on
			/// ProcessInfo.ProcessHandle to avoid memory leaks.
			ProcessInfo
			ExecuteNoWait(StringRef Program, const char **args, const char **env = 0,
			const StringRef **redirects = 0, unsigned memoryLimit = 0,
			std::string *ErrMsg = 0, bool *ExecutionFailed = 0);
	// Return true if the given arguments fit within system-specific		/// Return true if the given arguments fit within system-specific
	// argument length limits.		/// argument length limits.
	bool argumentsFitWithinSystemLimits(ArrayRef<const char*> Args);		bool argumentsFitWithinSystemLimits(ArrayRef<const char*> Args);
	}
			/// This function waits for the process specified by \p PI to finish.
			/// \returns A \see ProcessInfo struct with Pid set to:
			/// \li The process id of the child process if the child process has chan
			ged
			/// state.
			/// \li 0 if the child process has not changed state.
			/// \note Users of this function should always check the ReturnCode membe
			r of
			/// the \see ProcessInfo returned from this function.
			ProcessInfo Wait(
			const ProcessInfo &PI, ///< The child process that should be waited o
			n.
			unsigned SecondsToWait, ///< If non-zero, this specifies the amount o
			f
			///< time to wait for the child process to exit. If the time expires,
			the
			///< child is killed and this function returns. If zero, this functio
			n
			///< will perform a non-blocking wait on the child process.
			bool WaitUntilTerminates, ///< If true, ignores \p SecondsToWait and
			waits
			///< until child has terminated.
			std::string *ErrMsg = 0 ///< If non-zero, provides a pointer to a str
			ing
			///< instance in which error messages will be returned. If the string
			///< is non-empty upon return an error occurred while invoking the
			///< program.
			);
			}
	}		}
	#endif		#endif
End of changes. 11 change blocks.
	123 lines changed or deleted		123 lines changed or added

	PromoteMemToReg.h		PromoteMemToReg.h
	skipping to change at line 18		skipping to change at line 18
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This file exposes an interface to promote alloca instructions to SSA		// This file exposes an interface to promote alloca instructions to SSA
	// registers, by using the SSA construction algorithm.		// registers, by using the SSA construction algorithm.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_TRANSFORMS_UTILS_PROMOTEMEMTOREG_H		#ifndef LLVM_TRANSFORMS_UTILS_PROMOTEMEMTOREG_H
	#define LLVM_TRANSFORMS_UTILS_PROMOTEMEMTOREG_H		#define LLVM_TRANSFORMS_UTILS_PROMOTEMEMTOREG_H
	#include <vector>		#include "llvm/ADT/ArrayRef.h"
	namespace llvm {		namespace llvm {
	class AllocaInst;		class AllocaInst;
	class DominatorTree;		class DominatorTree;
	class AliasSetTracker;		class AliasSetTracker;
	/// isAllocaPromotable - Return true if this alloca is legal for promotion.		/// \brief Return true if this alloca is legal for promotion.
	/// This is true if there are only loads and stores to the alloca...
	///		///
			/// This is true if there are only loads, stores, and lifetime markers
			/// (transitively) using this alloca. This also enforces that there is only
			/// ever one layer of bitcasts or GEPs between the alloca and the lifetime
			/// markers.
	bool isAllocaPromotable(const AllocaInst *AI);		bool isAllocaPromotable(const AllocaInst *AI);
	/// PromoteMemToReg - Promote the specified list of alloca instructions int		/// \brief Promote the specified list of alloca instructions into scalar
	o		/// registers, inserting PHI nodes as appropriate.
	/// scalar registers, inserting PHI nodes as appropriate. This function ma		///
	kes		/// This function makes use of DominanceFrontier information. This functio
	/// use of DominanceFrontier information. This function does not modify th		n
	e CFG		/// does not modify the CFG of the function at all. All allocas must be fr
	/// of the function at all. All allocas must be from the same function.		om
			/// the same function.
	///		///
	/// If AST is specified, the specified tracker is updated to reflect change s		/// If AST is specified, the specified tracker is updated to reflect change s
	/// made to the IR.		/// made to the IR.
	///		void PromoteMemToReg(ArrayRef<AllocaInst *> Allocas, DominatorTree &DT,
	void PromoteMemToReg(const std::vector<AllocaInst*> &Allocas,		AliasSetTracker *AST = 0);
	DominatorTree &DT, AliasSetTracker *AST = 0);
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 5 change blocks.
	13 lines changed or deleted		16 lines changed or added

	PseudoSourceValue.h		PseudoSourceValue.h
	skipping to change at line 47		skipping to change at line 47
	/// isConstant - Test whether the memory pointed to by this		/// isConstant - Test whether the memory pointed to by this
	/// PseudoSourceValue has a constant value.		/// PseudoSourceValue has a constant value.
	///		///
	virtual bool isConstant(const MachineFrameInfo *) const;		virtual bool isConstant(const MachineFrameInfo *) const;
	/// isAliased - Test whether the memory pointed to by this		/// isAliased - Test whether the memory pointed to by this
	/// PseudoSourceValue may also be pointed to by an LLVM IR Value.		/// PseudoSourceValue may also be pointed to by an LLVM IR Value.
	virtual bool isAliased(const MachineFrameInfo *) const;		virtual bool isAliased(const MachineFrameInfo *) const;
	/// mayAlias - Return true if the memory pointed to by this		/// mayAlias - Return true if the memory pointed to by this
	/// PseudoSourceValue can ever alias a LLVM IR Value.		/// PseudoSourceValue can ever alias an LLVM IR Value.
	virtual bool mayAlias(const MachineFrameInfo *) const;		virtual bool mayAlias(const MachineFrameInfo *) const;
	/// classof - Methods for support type inquiry through isa, cast, and		/// classof - Methods for support type inquiry through isa, cast, and
	/// dyn_cast:		/// dyn_cast:
	///		///
	static inline bool classof(const Value *V) {		static inline bool classof(const Value *V) {
	return V->getValueID() == PseudoSourceValueVal ||		return V->getValueID() == PseudoSourceValueVal ||
	V->getValueID() == FixedStackPseudoSourceValueVal;		V->getValueID() == FixedStackPseudoSourceValueVal;
	}		}
End of changes. 1 change blocks.
	1 lines changed or deleted		1 lines changed or added

	Record.h		Record.h
	skipping to change at line 690		skipping to change at line 690
	virtual std::string getAsString() const;		virtual std::string getAsString() const;
	virtual Init *resolveReferences(Record &R, const RecordVal *RV) const;		virtual Init *resolveReferences(Record &R, const RecordVal *RV) const;
	virtual Init *getBit(unsigned Bit) const {		virtual Init *getBit(unsigned Bit) const {
	assert(Bit < Bits.size() && "Bit index out of range!");		assert(Bit < Bits.size() && "Bit index out of range!");
	return Bits[Bit];		return Bits[Bit];
	}		}
	};		};
	/// IntInit - 7 - Represent an initalization by a literal integer value.		/// IntInit - 7 - Represent an initialization by a literal integer value.
	///		///
	class IntInit : public TypedInit {		class IntInit : public TypedInit {
	int64_t Value;		int64_t Value;
	explicit IntInit(int64_t V)		explicit IntInit(int64_t V)
	: TypedInit(IK_IntInit, IntRecTy::get()), Value(V) {}		: TypedInit(IK_IntInit, IntRecTy::get()), Value(V) {}
	IntInit(const IntInit &Other) LLVM_DELETED_FUNCTION;		IntInit(const IntInit &Other) LLVM_DELETED_FUNCTION;
	IntInit &operator=(const IntInit &Other) LLVM_DELETED_FUNCTION;		IntInit &operator=(const IntInit &Other) LLVM_DELETED_FUNCTION;
	skipping to change at line 1719		skipping to change at line 1719
	/// LessRecordFieldName - Sorting predicate to sort record pointers by thei r		/// LessRecordFieldName - Sorting predicate to sort record pointers by thei r
	/// name field.		/// name field.
	///		///
	struct LessRecordFieldName {		struct LessRecordFieldName {
	bool operator()(const Record *Rec1, const Record *Rec2) const {		bool operator()(const Record *Rec1, const Record *Rec2) const {
	return Rec1->getValueAsString("Name") < Rec2->getValueAsString("Name");		return Rec1->getValueAsString("Name") < Rec2->getValueAsString("Name");
	}		}
	};		};
			struct LessRecordRegister {
			static size_t min(size_t a, size_t b) { return a < b ? a : b; }
			static bool ascii_isdigit(char x) { return x >= '0' && x <= '9'; }
			struct RecordParts {
			SmallVector<std::pair< bool, StringRef>, 4> Parts;
			RecordParts(StringRef Rec) {
			if (Rec.empty())
			return;
			size_t Len = 0;
			const char *Start = Rec.data();
			const char *Curr = Start;
			bool isDigitPart = ascii_isdigit(Curr[0]);
			for (size_t I = 0, E = Rec.size(); I != E; ++I, ++Len) {
			bool isDigit = ascii_isdigit(Curr[I]);
			if (isDigit != isDigitPart) {
			Parts.push_back(std::make_pair(isDigitPart, StringRef(Start, Len)
			));
			Len = 0;
			Start = &Curr[I];
			isDigitPart = ascii_isdigit(Curr[I]);
			}
			}
			// Push the last part.
			Parts.push_back(std::make_pair(isDigitPart, StringRef(Start, Len)));
			}
			size_t size() { return Parts.size(); }
			std::pair<bool, StringRef> getPart(size_t i) {
			assert (i < Parts.size() && "Invalid idx!");
			return Parts[i];
			}
			};
			bool operator()(const Record *Rec1, const Record *Rec2) const {
			RecordParts LHSParts(StringRef(Rec1->getName()));
			RecordParts RHSParts(StringRef(Rec2->getName()));
			size_t LHSNumParts = LHSParts.size();
			size_t RHSNumParts = RHSParts.size();
			assert (LHSNumParts && RHSNumParts && "Expected at least one part!");
			if (LHSNumParts != RHSNumParts)
			return LHSNumParts < RHSNumParts;
			// We expect the registers to be of the form [_a-zA-z]+([0-9]*[_a-zA-Z]
			*)*.
			for (size_t I = 0, E = LHSNumParts; I < E; I+=2) {
			std::pair<bool, StringRef> LHSPart = LHSParts.getPart(I);
			std::pair<bool, StringRef> RHSPart = RHSParts.getPart(I);
			// Expect even part to always be alpha.
			assert (LHSPart.first == false && RHSPart.first == false &&
			"Expected both parts to be alpha.");
			if (int Res = LHSPart.second.compare(RHSPart.second))
			return Res < 0;
			}
			for (size_t I = 1, E = LHSNumParts; I < E; I+=2) {
			std::pair<bool, StringRef> LHSPart = LHSParts.getPart(I);
			std::pair<bool, StringRef> RHSPart = RHSParts.getPart(I);
			// Expect odd part to always be numeric.
			assert (LHSPart.first == true && RHSPart.first == true &&
			"Expected both parts to be numeric.");
			if (LHSPart.second.size() != RHSPart.second.size())
			return LHSPart.second.size() < RHSPart.second.size();
			unsigned LHSVal, RHSVal;
			bool LHSFailed = LHSPart.second.getAsInteger(10, LHSVal); (void)LHSFa
			iled;
			assert(!LHSFailed && "Unable to convert LHS to integer.");
			bool RHSFailed = RHSPart.second.getAsInteger(10, RHSVal); (void)RHSFa
			iled;
			assert(!RHSFailed && "Unable to convert RHS to integer.");
			if (LHSVal != RHSVal)
			return LHSVal < RHSVal;
			}
			return LHSNumParts < RHSNumParts;
			}
			};
	raw_ostream &operator<<(raw_ostream &OS, const RecordKeeper &RK);		raw_ostream &operator<<(raw_ostream &OS, const RecordKeeper &RK);
	/// QualifyName - Return an Init with a qualifier prefix referring		/// QualifyName - Return an Init with a qualifier prefix referring
	/// to CurRec's name.		/// to CurRec's name.
	Init *QualifyName(Record &CurRec, MultiClass *CurMultiClass,		Init *QualifyName(Record &CurRec, MultiClass *CurMultiClass,
	Init *Name, const std::string &Scoper);		Init *Name, const std::string &Scoper);
	/// QualifyName - Return an Init with a qualifier prefix referring		/// QualifyName - Return an Init with a qualifier prefix referring
	/// to CurRec's name.		/// to CurRec's name.
	Init *QualifyName(Record &CurRec, MultiClass *CurMultiClass,		Init *QualifyName(Record &CurRec, MultiClass *CurMultiClass,
End of changes. 2 change blocks.
	1 lines changed or deleted		85 lines changed or added

	RecyclingAllocator.h		RecyclingAllocator.h
	skipping to change at line 54		skipping to change at line 54
	SubClass *Allocate() { return Base.template Allocate<SubClass>(Allocator) ; }		SubClass *Allocate() { return Base.template Allocate<SubClass>(Allocator) ; }
	T *Allocate() { return Base.Allocate(Allocator); }		T *Allocate() { return Base.Allocate(Allocator); }
	/// Deallocate - Release storage for the pointed-to object. The		/// Deallocate - Release storage for the pointed-to object. The
	/// storage will be kept track of and may be recycled.		/// storage will be kept track of and may be recycled.
	///		///
	template<class SubClass>		template<class SubClass>
	void Deallocate(SubClass* E) { return Base.Deallocate(Allocator, E); }		void Deallocate(SubClass* E) { return Base.Deallocate(Allocator, E); }
	void PrintStats() { Base.PrintStats(); }		void PrintStats() {
			Allocator.PrintStats();
			Base.PrintStats();
			}
	};		};
	}		}
	template<class AllocatorType, class T, size_t Size, size_t Align>		template<class AllocatorType, class T, size_t Size, size_t Align>
	inline void *operator new(size_t,		inline void *operator new(size_t size,
	llvm::RecyclingAllocator<AllocatorType,		llvm::RecyclingAllocator<AllocatorType,
	T, Size, Align> &Allocat or) {		T, Size, Align> &Allocat or) {
			assert(size <= Size && "allocation size exceeded");
	return Allocator.Allocate();		return Allocator.Allocate();
	}		}
	template<class AllocatorType, class T, size_t Size, size_t Align>		template<class AllocatorType, class T, size_t Size, size_t Align>
	inline void operator delete(void *E,		inline void operator delete(void *E,
	llvm::RecyclingAllocator<AllocatorType,		llvm::RecyclingAllocator<AllocatorType,
	T, Size, Align> &A) {		T, Size, Align> &A) {
	A.Deallocate(E);		A.Deallocate(E);
	}		}
End of changes. 3 change blocks.
	2 lines changed or deleted		6 lines changed or added

	RegAllocPBQP.h		RegAllocPBQP.h
	skipping to change at line 29		skipping to change at line 29
	#include "llvm/ADT/DenseMap.h"		#include "llvm/ADT/DenseMap.h"
	#include "llvm/CodeGen/MachineFunctionPass.h"		#include "llvm/CodeGen/MachineFunctionPass.h"
	#include "llvm/CodeGen/PBQP/Graph.h"		#include "llvm/CodeGen/PBQP/Graph.h"
	#include "llvm/CodeGen/PBQP/Solution.h"		#include "llvm/CodeGen/PBQP/Solution.h"
	#include <map>		#include <map>
	#include <set>		#include <set>
	namespace llvm {		namespace llvm {
	class LiveIntervals;		class LiveIntervals;
			class MachineBlockFrequencyInfo;
	class MachineFunction;		class MachineFunction;
	class MachineLoopInfo;
	class TargetRegisterInfo;		class TargetRegisterInfo;
	template<class T> class OwningPtr;		template<class T> class OwningPtr;
	/// This class wraps up a PBQP instance representing a register allocatio n		/// This class wraps up a PBQP instance representing a register allocatio n
	/// problem, plus the structures necessary to map back from the PBQP solu tion		/// problem, plus the structures necessary to map back from the PBQP solu tion
	/// to a register allocation solution. (i.e. The PBQP-node <--> vreg map,		/// to a register allocation solution. (i.e. The PBQP-node <--> vreg map,
	/// and the PBQP option <--> storage location map).		/// and the PBQP option <--> storage location map).
	class PBQPRAProblem {		class PBQPRAProblem {
	public:		public:
	skipping to change at line 55		skipping to change at line 55
	const PBQP::Graph& getGraph() const { return graph; }		const PBQP::Graph& getGraph() const { return graph; }
	/// Record the mapping between the given virtual register and PBQP node ,		/// Record the mapping between the given virtual register and PBQP node ,
	/// and the set of allowed pregs for the vreg.		/// and the set of allowed pregs for the vreg.
	///		///
	/// If you are extending		/// If you are extending
	/// PBQPBuilder you are unlikely to need this: Nodes and options for al l		/// PBQPBuilder you are unlikely to need this: Nodes and options for al l
	/// vregs will already have been set up for you by the base class.		/// vregs will already have been set up for you by the base class.
	template <typename AllowedRegsItr>		template <typename AllowedRegsItr>
	void recordVReg(unsigned vreg, PBQP::Graph::NodeItr node,		void recordVReg(unsigned vreg, PBQP::Graph::NodeId nodeId,
	AllowedRegsItr arBegin, AllowedRegsItr arEnd) {		AllowedRegsItr arBegin, AllowedRegsItr arEnd) {
	assert(node2VReg.find(node) == node2VReg.end() && "Re-mapping node.") ;		assert(node2VReg.find(nodeId) == node2VReg.end() && "Re-mapping node. ");
	assert(vreg2Node.find(vreg) == vreg2Node.end() && "Re-mapping vreg.") ;		assert(vreg2Node.find(vreg) == vreg2Node.end() && "Re-mapping vreg.") ;
	assert(allowedSets[vreg].empty() && "vreg already has pregs.");		assert(allowedSets[vreg].empty() && "vreg already has pregs.");
	node2VReg[node] = vreg;		node2VReg[nodeId] = vreg;
	vreg2Node[vreg] = node;		vreg2Node[vreg] = nodeId;
	std::copy(arBegin, arEnd, std::back_inserter(allowedSets[vreg]));		std::copy(arBegin, arEnd, std::back_inserter(allowedSets[vreg]));
	}		}
	/// Get the virtual register corresponding to the given PBQP node.		/// Get the virtual register corresponding to the given PBQP node.
	unsigned getVRegForNode(PBQP::Graph::ConstNodeItr node) const;		unsigned getVRegForNode(PBQP::Graph::NodeId nodeId) const;
	/// Get the PBQP node corresponding to the given virtual register.		/// Get the PBQP node corresponding to the given virtual register.
	PBQP::Graph::NodeItr getNodeForVReg(unsigned vreg) const;		PBQP::Graph::NodeId getNodeForVReg(unsigned vreg) const;
	/// Returns true if the given PBQP option represents a physical registe r,		/// Returns true if the given PBQP option represents a physical registe r,
	/// false otherwise.		/// false otherwise.
	bool isPRegOption(unsigned vreg, unsigned option) const {		bool isPRegOption(unsigned vreg, unsigned option) const {
	// At present we only have spills or pregs, so anything that's not a		// At present we only have spills or pregs, so anything that's not a
	// spill is a preg. (This might be extended one day to support remat) .		// spill is a preg. (This might be extended one day to support remat) .
	return !isSpillOption(vreg, option);		return !isSpillOption(vreg, option);
	}		}
	/// Returns true if the given PBQP option represents spilling, false		/// Returns true if the given PBQP option represents spilling, false
	skipping to change at line 95		skipping to change at line 95
	}		}
	/// Returns the allowed set for the given virtual register.		/// Returns the allowed set for the given virtual register.
	const AllowedSet& getAllowedSet(unsigned vreg) const;		const AllowedSet& getAllowedSet(unsigned vreg) const;
	/// Get PReg for option.		/// Get PReg for option.
	unsigned getPRegForOption(unsigned vreg, unsigned option) const;		unsigned getPRegForOption(unsigned vreg, unsigned option) const;
	private:		private:
	typedef std::map<PBQP::Graph::ConstNodeItr, unsigned,		typedef std::map<PBQP::Graph::NodeId, unsigned> Node2VReg;
	PBQP::NodeItrComparator> Node2VReg;		typedef DenseMap<unsigned, PBQP::Graph::NodeId> VReg2Node;
	typedef DenseMap<unsigned, PBQP::Graph::NodeItr> VReg2Node;
	typedef DenseMap<unsigned, AllowedSet> AllowedSetMap;		typedef DenseMap<unsigned, AllowedSet> AllowedSetMap;
	PBQP::Graph graph;		PBQP::Graph graph;
	Node2VReg node2VReg;		Node2VReg node2VReg;
	VReg2Node vreg2Node;		VReg2Node vreg2Node;
	AllowedSetMap allowedSets;		AllowedSetMap allowedSets;
	};		};
	skipping to change at line 128		skipping to change at line 127
	/// Default constructor.		/// Default constructor.
	PBQPBuilder() {}		PBQPBuilder() {}
	/// Clean up a PBQPBuilder.		/// Clean up a PBQPBuilder.
	virtual ~PBQPBuilder() {}		virtual ~PBQPBuilder() {}
	/// Build a PBQP instance to represent the register allocation problem for		/// Build a PBQP instance to represent the register allocation problem for
	/// the given MachineFunction.		/// the given MachineFunction.
	virtual PBQPRAProblem *build(MachineFunction *mf, const LiveIntervals * lis,		virtual PBQPRAProblem *build(MachineFunction *mf, const LiveIntervals * lis,
	const MachineLoopInfo *loopInfo,		const MachineBlockFrequencyInfo *mbfi,
	const RegSet &vregs);		const RegSet &vregs);
	private:		private:
	void addSpillCosts(PBQP::Vector &costVec, PBQP::PBQPNum spillCost);		void addSpillCosts(PBQP::Vector &costVec, PBQP::PBQPNum spillCost);
	void addInterferenceCosts(PBQP::Matrix &costMat,		void addInterferenceCosts(PBQP::Matrix &costMat,
	const PBQPRAProblem::AllowedSet &vr1Allowed,		const PBQPRAProblem::AllowedSet &vr1Allowed,
	const PBQPRAProblem::AllowedSet &vr2Allowed,		const PBQPRAProblem::AllowedSet &vr2Allowed,
	const TargetRegisterInfo *tri);		const TargetRegisterInfo *tri);
	};		};
	/// Extended builder which adds coalescing constraints to a problem.		/// Extended builder which adds coalescing constraints to a problem.
	class PBQPBuilderWithCoalescing : public PBQPBuilder {		class PBQPBuilderWithCoalescing : public PBQPBuilder {
	public:		public:
	/// Build a PBQP instance to represent the register allocation problem for		/// Build a PBQP instance to represent the register allocation problem for
	/// the given MachineFunction.		/// the given MachineFunction.
	virtual PBQPRAProblem *build(MachineFunction *mf, const LiveIntervals * lis,		virtual PBQPRAProblem *build(MachineFunction *mf, const LiveIntervals * lis,
	const MachineLoopInfo *loopInfo,		const MachineBlockFrequencyInfo *mbfi,
	const RegSet &vregs);		const RegSet &vregs);
	private:		private:
	void addPhysRegCoalesce(PBQP::Vector &costVec, unsigned pregOption,		void addPhysRegCoalesce(PBQP::Vector &costVec, unsigned pregOption,
	PBQP::PBQPNum benefit);		PBQP::PBQPNum benefit);
	void addVirtRegCoalesce(PBQP::Matrix &costMat,		void addVirtRegCoalesce(PBQP::Matrix &costMat,
	const PBQPRAProblem::AllowedSet &vr1Allowed,		const PBQPRAProblem::AllowedSet &vr1Allowed,
	const PBQPRAProblem::AllowedSet &vr2Allowed,		const PBQPRAProblem::AllowedSet &vr2Allowed,
End of changes. 10 change blocks.
	12 lines changed or deleted		11 lines changed or added

	Regex.h		Regex.h
	skipping to change at line 80		skipping to change at line 80
	/// replacement string are replaced with the appropriate match substrin g.		/// replacement string are replaced with the appropriate match substrin g.
	///		///
	/// Note that the replacement string has backslash escaping performed o n		/// Note that the replacement string has backslash escaping performed o n
	/// it. Invalid backreferences are ignored (replaced by empty strings).		/// it. Invalid backreferences are ignored (replaced by empty strings).
	///		///
	/// \param Error If non-null, any errors in the substitution (invalid		/// \param Error If non-null, any errors in the substitution (invalid
	/// backreferences, trailing backslashes) will be recorded as a non-emp ty		/// backreferences, trailing backslashes) will be recorded as a non-emp ty
	/// string.		/// string.
	std::string sub(StringRef Repl, StringRef String, std::string *Error = 0);		std::string sub(StringRef Repl, StringRef String, std::string *Error = 0);
			/// \brief If this function returns true, ^Str$ is an extended regular
			/// expression that matches Str and only Str.
			static bool isLiteralERE(StringRef Str);
	private:		private:
	struct llvm_regex *preg;		struct llvm_regex *preg;
	int error;		int error;
	};		};
	}		}
	#endif // LLVM_SUPPORT_REGEX_H		#endif // LLVM_SUPPORT_REGEX_H
End of changes. 1 change blocks.
	0 lines changed or deleted		4 lines changed or added

	RegionPass.h		RegionPass.h
	skipping to change at line 21		skipping to change at line 21
	// optimization and transformation passes are derived from RegionPass.		// optimization and transformation passes are derived from RegionPass.
	// This class is implemented following the some ideas of the LoopPass.h cla ss.		// This class is implemented following the some ideas of the LoopPass.h cla ss.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_ANALYSIS_REGIONPASS_H		#ifndef LLVM_ANALYSIS_REGIONPASS_H
	#define LLVM_ANALYSIS_REGIONPASS_H		#define LLVM_ANALYSIS_REGIONPASS_H
	#include "llvm/Analysis/RegionInfo.h"		#include "llvm/Analysis/RegionInfo.h"
	#include "llvm/IR/Function.h"		#include "llvm/IR/Function.h"
			#include "llvm/IR/LegacyPassManagers.h"
	#include "llvm/Pass.h"		#include "llvm/Pass.h"
	#include "llvm/PassManagers.h"
	#include <deque>		#include <deque>
	namespace llvm {		namespace llvm {
	class RGPassManager;		class RGPassManager;
	class Function;		class Function;
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	/// @brief A pass that runs on each Region in a function.		/// @brief A pass that runs on each Region in a function.
	///		///
	skipping to change at line 54		skipping to change at line 54
	/// Accessing regions not contained in the current region is not allowed.		/// Accessing regions not contained in the current region is not allowed.
	///		///
	/// @param R The region this pass is run on.		/// @param R The region this pass is run on.
	/// @param RGM The RegionPassManager that manages this Pass.		/// @param RGM The RegionPassManager that manages this Pass.
	///		///
	/// @return True if the pass modifies this Region.		/// @return True if the pass modifies this Region.
	virtual bool runOnRegion(Region *R, RGPassManager &RGM) = 0;		virtual bool runOnRegion(Region *R, RGPassManager &RGM) = 0;
	/// @brief Get a pass to print the LLVM IR in the region.		/// @brief Get a pass to print the LLVM IR in the region.
	///		///
	/// @param O The ouput stream to print the Region.		/// @param O The output stream to print the Region.
	/// @param Banner The banner to separate different printed passes.		/// @param Banner The banner to separate different printed passes.
	///		///
	/// @return The pass to print the LLVM IR in the region.		/// @return The pass to print the LLVM IR in the region.
	Pass *createPrinterPass(raw_ostream &O, const std::string &Banner) const;		Pass *createPrinterPass(raw_ostream &O, const std::string &Banner) const;
	using llvm::Pass::doInitialization;		using llvm::Pass::doInitialization;
	using llvm::Pass::doFinalization;		using llvm::Pass::doFinalization;
	virtual bool doInitialization(Region *R, RGPassManager &RGM) { return fal se; }		virtual bool doInitialization(Region *R, RGPassManager &RGM) { return fal se; }
	virtual bool doFinalization() { return false; }		virtual bool doFinalization() { return false; }
End of changes. 3 change blocks.
	2 lines changed or deleted		2 lines changed or added

	RegisterClassInfo.h		RegisterClassInfo.h
	skipping to change at line 65		skipping to change at line 65
	// Callee saved registers of last MF. Assumed to be valid until the next		// Callee saved registers of last MF. Assumed to be valid until the next
	// runOnFunction() call.		// runOnFunction() call.
	const uint16_t *CalleeSaved;		const uint16_t *CalleeSaved;
	// Map register number to CalleeSaved index + 1;		// Map register number to CalleeSaved index + 1;
	SmallVector<uint8_t, 4> CSRNum;		SmallVector<uint8_t, 4> CSRNum;
	// Reserved registers in the current MF.		// Reserved registers in the current MF.
	BitVector Reserved;		BitVector Reserved;
			OwningArrayPtr<unsigned> PSetLimits;
	// Compute all information about RC.		// Compute all information about RC.
	void compute(const TargetRegisterClass *RC) const;		void compute(const TargetRegisterClass *RC) const;
	// Return an up-to-date RCInfo for RC.		// Return an up-to-date RCInfo for RC.
	const RCInfo &get(const TargetRegisterClass *RC) const {		const RCInfo &get(const TargetRegisterClass *RC) const {
	const RCInfo &RCI = RegClass[RC->getID()];		const RCInfo &RCI = RegClass[RC->getID()];
	if (Tag != RCI.Tag)		if (Tag != RCI.Tag)
	compute(RC);		compute(RC);
	return RCI;		return RCI;
	}		}
	skipping to change at line 129		skipping to change at line 131
	return get(RC).MinCost;		return get(RC).MinCost;
	}		}
	/// Get the position of the last cost change in getOrder(RC).		/// Get the position of the last cost change in getOrder(RC).
	///		///
	/// All registers in getOrder(RC).slice(getLastCostChange(RC)) will have the		/// All registers in getOrder(RC).slice(getLastCostChange(RC)) will have the
	/// same cost according to TRI->getCostPerUse().		/// same cost according to TRI->getCostPerUse().
	unsigned getLastCostChange(const TargetRegisterClass *RC) {		unsigned getLastCostChange(const TargetRegisterClass *RC) {
	return get(RC).LastCostChange;		return get(RC).LastCostChange;
	}		}
			/// Get the register unit limit for the given pressure set index.
			///
			/// RegisterClassInfo adjusts this limit for reserved registers.
			unsigned getRegPressureSetLimit(unsigned Idx) const {
			if (!PSetLimits[Idx])
			PSetLimits[Idx] = computePSetLimit(Idx);
			return PSetLimits[Idx];
			}
			protected:
			unsigned computePSetLimit(unsigned Idx) const;
	};		};
	} // end namespace llvm		} // end namespace llvm
	#endif		#endif
End of changes. 2 change blocks.
	0 lines changed or deleted		14 lines changed or added

	RegisterPressure.h		RegisterPressure.h
	skipping to change at line 25		skipping to change at line 25
	#ifndef LLVM_CODEGEN_REGISTERPRESSURE_H		#ifndef LLVM_CODEGEN_REGISTERPRESSURE_H
	#define LLVM_CODEGEN_REGISTERPRESSURE_H		#define LLVM_CODEGEN_REGISTERPRESSURE_H
	#include "llvm/ADT/SparseSet.h"		#include "llvm/ADT/SparseSet.h"
	#include "llvm/CodeGen/SlotIndexes.h"		#include "llvm/CodeGen/SlotIndexes.h"
	#include "llvm/Target/TargetRegisterInfo.h"		#include "llvm/Target/TargetRegisterInfo.h"
	namespace llvm {		namespace llvm {
	class LiveIntervals;		class LiveIntervals;
	class LiveInterval;		class LiveRange;
	class RegisterClassInfo;		class RegisterClassInfo;
	class MachineInstr;		class MachineInstr;
	/// Base class for register pressure results.		/// Base class for register pressure results.
	struct RegisterPressure {		struct RegisterPressure {
	/// Map of max reg pressure indexed by pressure set ID, not class ID.		/// Map of max reg pressure indexed by pressure set ID, not class ID.
	std::vector<unsigned> MaxSetPressure;		std::vector<unsigned> MaxSetPressure;
	/// List of live in virtual registers or physical register units.		/// List of live in virtual registers or physical register units.
	SmallVector<unsigned,8> LiveInRegs;		SmallVector<unsigned,8> LiveInRegs;
	skipping to change at line 92		skipping to change at line 92
	MachineBasicBlock::const_iterator TopPos;		MachineBasicBlock::const_iterator TopPos;
	MachineBasicBlock::const_iterator BottomPos;		MachineBasicBlock::const_iterator BottomPos;
	void reset();		void reset();
	void openTop(MachineBasicBlock::const_iterator PrevTop);		void openTop(MachineBasicBlock::const_iterator PrevTop);
	void openBottom(MachineBasicBlock::const_iterator PrevBottom);		void openBottom(MachineBasicBlock::const_iterator PrevBottom);
	};		};
	/// An element of pressure difference that identifies the pressure set and		/// Capture a change in pressure for a single pressure set. UnitInc may be
	/// amount of increase or decrease in units of pressure.		/// expressed in terms of upward or downward pressure depending on the clie
	struct PressureElement {		nt
	unsigned PSetID;		/// and will be dynamically adjusted for current liveness.
	int UnitIncrease;		///
			/// Pressure increments are tiny, typically 1-2 units, and this is only for
			/// heuristics, so we don't check UnitInc overflow. Instead, we may have a
			/// higher level assert that pressure is consistent within a region. We als
			o
			/// effectively ignore dead defs which don't affect heuristics much.
			class PressureChange {
			uint16_t PSetID; // ID+1. 0=Invalid.
			int16_t UnitInc;
			public:
			PressureChange(): PSetID(0), UnitInc(0) {}
			PressureChange(unsigned id): PSetID(id+1), UnitInc(0) {
			assert(id < UINT16_MAX && "PSetID overflow.");
			}
			bool isValid() const { return PSetID > 0; }
			unsigned getPSet() const {
			assert(isValid() && "invalid PressureChange");
			return PSetID - 1;
			}
			// If PSetID is invalid, return UINT16_MAX to give it lowest priority.
			unsigned getPSetOrMax() const { return (PSetID - 1) & UINT16_MAX; }
			int getUnitInc() const { return UnitInc; }
			void setUnitInc(int Inc) { UnitInc = Inc; }
			bool operator==(const PressureChange &RHS) const {
			return PSetID == RHS.PSetID && UnitInc == RHS.UnitInc;
			}
			};
			template <> struct isPodLike<PressureChange> {
			static const bool value = true;
			};
			/// List of PressureChanges in order of increasing, unique PSetID.
			///
			/// Use a small fixed number, because we can fit more PressureChanges in an
			/// empty SmallVector than ever need to be tracked per register class. If m
			ore
			/// PSets are affected, then we only track the most constrained.
			class PressureDiff {
			// The initial design was for MaxPSets=4, but that requires PSet partitio
			ns,
			// which are not yet implemented. (PSet partitions are equivalent PSets g
			iven
			// the register classes actually in use within the scheduling region.)
			enum { MaxPSets = 16 };
	PressureElement(): PSetID(~0U), UnitIncrease(0) {}		PressureChange PressureChanges[MaxPSets];
	PressureElement(unsigned id, int inc): PSetID(id), UnitIncrease(inc) {}		public:
			typedef PressureChange* iterator;
			typedef const PressureChange* const_iterator;
			iterator begin() { return &PressureChanges[0]; }
			iterator end() { return &PressureChanges[MaxPSets]; }
			const_iterator begin() const { return &PressureChanges[0]; }
			const_iterator end() const { return &PressureChanges[MaxPSets]; }
	bool isValid() const { return PSetID != ~0U; }		void addPressureChange(unsigned RegUnit, bool IsDec,
			const MachineRegisterInfo *MRI);
			};
			/// Array of PressureDiffs.
			class PressureDiffs {
			PressureDiff *PDiffArray;
			unsigned Size;
			unsigned Max;
			public:
			PressureDiffs(): PDiffArray(0), Size(0), Max(0) {}
			~PressureDiffs() { free(PDiffArray); }
			void clear() { Size = 0; }
			void init(unsigned N);
			PressureDiff &operator[](unsigned Idx) {
			assert(Idx < Size && "PressureDiff index out of bounds");
			return PDiffArray[Idx];
			}
			const PressureDiff &operator[](unsigned Idx) const {
			return const_cast<PressureDiffs*>(this)->operator[](Idx);
			}
	};		};
	/// Store the effects of a change in pressure on things that MI scheduler c ares		/// Store the effects of a change in pressure on things that MI scheduler c ares
	/// about.		/// about.
	///		///
	/// Excess records the value of the largest difference in register units be yond		/// Excess records the value of the largest difference in register units be yond
	/// the target's pressure limits across the affected pressure sets, where		/// the target's pressure limits across the affected pressure sets, where
	/// largest is defined as the absolute value of the difference. Negative		/// largest is defined as the absolute value of the difference. Negative
	/// ExcessUnits indicates a reduction in pressure that had already exceeded the		/// ExcessUnits indicates a reduction in pressure that had already exceeded the
	/// target's limits.		/// target's limits.
	///		///
	/// CriticalMax records the largest increase in the tracker's max pressure that		/// CriticalMax records the largest increase in the tracker's max pressure that
	/// exceeds the critical limit for some pressure set determined by the clie nt.		/// exceeds the critical limit for some pressure set determined by the clie nt.
	///		///
	/// CurrentMax records the largest increase in the tracker's max pressure t hat		/// CurrentMax records the largest increase in the tracker's max pressure t hat
	/// exceeds the current limit for some pressure set determined by the clien t.		/// exceeds the current limit for some pressure set determined by the clien t.
	struct RegPressureDelta {		struct RegPressureDelta {
	PressureElement Excess;		PressureChange Excess;
	PressureElement CriticalMax;		PressureChange CriticalMax;
	PressureElement CurrentMax;		PressureChange CurrentMax;
	RegPressureDelta() {}		RegPressureDelta() {}
			bool operator==(const RegPressureDelta &RHS) const {
			return Excess == RHS.Excess && CriticalMax == RHS.CriticalMax
			&& CurrentMax == RHS.CurrentMax;
			}
			bool operator!=(const RegPressureDelta &RHS) const {
			return !operator==(RHS);
			}
	};		};
	/// \brief A set of live virtual registers and physical register units.		/// \brief A set of live virtual registers and physical register units.
	///		///
	/// Virtual and physical register numbers require separate sparse sets, but most		/// Virtual and physical register numbers require separate sparse sets, but most
	/// of the RegisterPressureTracker handles them uniformly.		/// of the RegisterPressureTracker handles them uniformly.
	struct LiveRegSet {		struct LiveRegSet {
	SparseSet<unsigned> PhysRegs;		SparseSet<unsigned> PhysRegs;
	SparseSet<unsigned, VirtReg2IndexFunctor> VirtRegs;		SparseSet<unsigned, VirtReg2IndexFunctor> VirtRegs;
	bool contains(unsigned Reg) {		bool contains(unsigned Reg) const {
	if (TargetRegisterInfo::isVirtualRegister(Reg))		if (TargetRegisterInfo::isVirtualRegister(Reg))
	return VirtRegs.count(Reg);		return VirtRegs.count(Reg);
	return PhysRegs.count(Reg);		return PhysRegs.count(Reg);
	}		}
	bool insert(unsigned Reg) {		bool insert(unsigned Reg) {
	if (TargetRegisterInfo::isVirtualRegister(Reg))		if (TargetRegisterInfo::isVirtualRegister(Reg))
	return VirtRegs.insert(Reg).second;		return VirtRegs.insert(Reg).second;
	return PhysRegs.insert(Reg).second;		return PhysRegs.insert(Reg).second;
	}		}
	skipping to change at line 186		skipping to change at line 267
	/// We currently only allow pressure tracking within a block.		/// We currently only allow pressure tracking within a block.
	const MachineBasicBlock *MBB;		const MachineBasicBlock *MBB;
	/// Track the max pressure within the region traversed so far.		/// Track the max pressure within the region traversed so far.
	RegisterPressure &P;		RegisterPressure &P;
	/// Run in two modes dependending on whether constructed with IntervalPre ssure		/// Run in two modes dependending on whether constructed with IntervalPre ssure
	/// or RegisterPressure. If requireIntervals is false, LIS are ignored.		/// or RegisterPressure. If requireIntervals is false, LIS are ignored.
	bool RequireIntervals;		bool RequireIntervals;
			/// True if UntiedDefs will be populated.
			bool TrackUntiedDefs;
	/// Register pressure corresponds to liveness before this instruction		/// Register pressure corresponds to liveness before this instruction
	/// iterator. It may point to the end of the block or a DebugValue rather than		/// iterator. It may point to the end of the block or a DebugValue rather than
	/// an instruction.		/// an instruction.
	MachineBasicBlock::const_iterator CurrPos;		MachineBasicBlock::const_iterator CurrPos;
	/// Pressure map indexed by pressure set ID, not class ID.		/// Pressure map indexed by pressure set ID, not class ID.
	std::vector<unsigned> CurrSetPressure;		std::vector<unsigned> CurrSetPressure;
	/// Set of live registers.		/// Set of live registers.
	LiveRegSet LiveRegs;		LiveRegSet LiveRegs;
			/// Set of vreg defs that start a live range.
			SparseSet<unsigned, VirtReg2IndexFunctor> UntiedDefs;
			/// Live-through pressure.
			std::vector<unsigned> LiveThruPressure;
	public:		public:
	RegPressureTracker(IntervalPressure &rp) :		RegPressureTracker(IntervalPressure &rp) :
	MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(true) {}		MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(true),
			TrackUntiedDefs(false) {}
	RegPressureTracker(RegionPressure &rp) :		RegPressureTracker(RegionPressure &rp) :
	MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(false) {		MF(0), TRI(0), RCI(0), LIS(0), MBB(0), P(rp), RequireIntervals(false),
	}		TrackUntiedDefs(false) {}
			void reset();
	void init(const MachineFunction *mf, const RegisterClassInfo *rci,		void init(const MachineFunction *mf, const RegisterClassInfo *rci,
	const LiveIntervals *lis, const MachineBasicBlock *mbb,		const LiveIntervals *lis, const MachineBasicBlock *mbb,
	MachineBasicBlock::const_iterator pos);		MachineBasicBlock::const_iterator pos,
			bool ShouldTrackUntiedDefs = false);
	/// Force liveness of virtual registers or physical register		/// Force liveness of virtual registers or physical register
	/// units. Particularly useful to initialize the livein/out state of the		/// units. Particularly useful to initialize the livein/out state of the
	/// tracker before the first call to advance/recede.		/// tracker before the first call to advance/recede.
	void addLiveRegs(ArrayRef<unsigned> Regs);		void addLiveRegs(ArrayRef<unsigned> Regs);
	/// Get the MI position corresponding to this register pressure.		/// Get the MI position corresponding to this register pressure.
	MachineBasicBlock::const_iterator getPos() const { return CurrPos; }		MachineBasicBlock::const_iterator getPos() const { return CurrPos; }
	// Reset the MI position corresponding to the register pressure. This all ows		// Reset the MI position corresponding to the register pressure. This all ows
	// schedulers to move instructions above the RegPressureTracker's		// schedulers to move instructions above the RegPressureTracker's
	// CurrPos. Since the pressure is computed before CurrPos, the iterator		// CurrPos. Since the pressure is computed before CurrPos, the iterator
	// position changes while pressure does not.		// position changes while pressure does not.
	void setPos(MachineBasicBlock::const_iterator Pos) { CurrPos = Pos; }		void setPos(MachineBasicBlock::const_iterator Pos) { CurrPos = Pos; }
	/// \brief Get the SlotIndex for the first nondebug instruction including or		/// \brief Get the SlotIndex for the first nondebug instruction including or
	/// after the current position.		/// after the current position.
	SlotIndex getCurrSlot() const;		SlotIndex getCurrSlot() const;
	/// Recede across the previous instruction.		/// Recede across the previous instruction.
	bool recede();		bool recede(SmallVectorImpl<unsigned> *LiveUses = 0, PressureDiff *PDiff = 0);
	/// Advance across the current instruction.		/// Advance across the current instruction.
	bool advance();		bool advance();
	/// Finalize the region boundaries and recored live ins and live outs.		/// Finalize the region boundaries and recored live ins and live outs.
	void closeRegion();		void closeRegion();
			/// Initialize the LiveThru pressure set based on the untied defs found i
			n
			/// RPTracker.
			void initLiveThru(const RegPressureTracker &RPTracker);
			/// Copy an existing live thru pressure result.
			void initLiveThru(ArrayRef<unsigned> PressureSet) {
			LiveThruPressure.assign(PressureSet.begin(), PressureSet.end());
			}
			ArrayRef<unsigned> getLiveThru() const { return LiveThruPressure; }
	/// Get the resulting register pressure over the traversed region.		/// Get the resulting register pressure over the traversed region.
	/// This result is complete if either advance() or recede() has returned true,		/// This result is complete if either advance() or recede() has returned true,
	/// or if closeRegion() was explicitly invoked.		/// or if closeRegion() was explicitly invoked.
	RegisterPressure &getPressure() { return P; }		RegisterPressure &getPressure() { return P; }
	const RegisterPressure &getPressure() const { return P; }		const RegisterPressure &getPressure() const { return P; }
	/// Get the register set pressure at the current position, which may be l ess		/// Get the register set pressure at the current position, which may be l ess
	/// than the pressure across the traversed region.		/// than the pressure across the traversed region.
	std::vector<unsigned> &getRegSetPressureAtPos() { return CurrSetPressure; }		std::vector<unsigned> &getRegSetPressureAtPos() { return CurrSetPressure; }
	skipping to change at line 259		skipping to change at line 364
	bool isBottomClosed() const;		bool isBottomClosed() const;
	void closeTop();		void closeTop();
	void closeBottom();		void closeBottom();
	/// Consider the pressure increase caused by traversing this instruction		/// Consider the pressure increase caused by traversing this instruction
	/// bottom-up. Find the pressure set with the most change beyond its pres sure		/// bottom-up. Find the pressure set with the most change beyond its pres sure
	/// limit based on the tracker's current pressure, and record the number of		/// limit based on the tracker's current pressure, and record the number of
	/// excess register units of that pressure set introduced by this instruc tion.		/// excess register units of that pressure set introduced by this instruc tion.
	void getMaxUpwardPressureDelta(const MachineInstr *MI,		void getMaxUpwardPressureDelta(const MachineInstr *MI,
			PressureDiff *PDiff,
	RegPressureDelta &Delta,		RegPressureDelta &Delta,
	ArrayRef<PressureElement> CriticalPSets,		ArrayRef<PressureChange> CriticalPSets,
	ArrayRef<unsigned> MaxPressureLimit);		ArrayRef<unsigned> MaxPressureLimit);
			void getUpwardPressureDelta(const MachineInstr *MI,
			/*const*/ PressureDiff &PDiff,
			RegPressureDelta &Delta,
			ArrayRef<PressureChange> CriticalPSets,
			ArrayRef<unsigned> MaxPressureLimit) const;
	/// Consider the pressure increase caused by traversing this instruction		/// Consider the pressure increase caused by traversing this instruction
	/// top-down. Find the pressure set with the most change beyond its press ure		/// top-down. Find the pressure set with the most change beyond its press ure
	/// limit based on the tracker's current pressure, and record the number of		/// limit based on the tracker's current pressure, and record the number of
	/// excess register units of that pressure set introduced by this instruc tion.		/// excess register units of that pressure set introduced by this instruc tion.
	void getMaxDownwardPressureDelta(const MachineInstr *MI,		void getMaxDownwardPressureDelta(const MachineInstr *MI,
	RegPressureDelta &Delta,		RegPressureDelta &Delta,
	ArrayRef<PressureElement> CriticalPSets,		ArrayRef<PressureChange> CriticalPSets,
	ArrayRef<unsigned> MaxPressureLimit);		ArrayRef<unsigned> MaxPressureLimit);
	/// Find the pressure set with the most change beyond its pressure limit after		/// Find the pressure set with the most change beyond its pressure limit after
	/// traversing this instruction either upward or downward depending on th e		/// traversing this instruction either upward or downward depending on th e
	/// closed end of the current region.		/// closed end of the current region.
	void getMaxPressureDelta(const MachineInstr *MI, RegPressureDelta &Delta,		void getMaxPressureDelta(const MachineInstr *MI,
	ArrayRef<PressureElement> CriticalPSets,		RegPressureDelta &Delta,
			ArrayRef<PressureChange> CriticalPSets,
	ArrayRef<unsigned> MaxPressureLimit) {		ArrayRef<unsigned> MaxPressureLimit) {
	if (isTopClosed())		if (isTopClosed())
	return getMaxDownwardPressureDelta(MI, Delta, CriticalPSets,		return getMaxDownwardPressureDelta(MI, Delta, CriticalPSets,
	MaxPressureLimit);		MaxPressureLimit);
	assert(isBottomClosed() && "Uninitialized pressure tracker");		assert(isBottomClosed() && "Uninitialized pressure tracker");
	return getMaxUpwardPressureDelta(MI, Delta, CriticalPSets,		return getMaxUpwardPressureDelta(MI, 0, Delta, CriticalPSets,
	MaxPressureLimit);		MaxPressureLimit);
	}		}
	/// Get the pressure of each PSet after traversing this instruction botto m-up.		/// Get the pressure of each PSet after traversing this instruction botto m-up.
	void getUpwardPressure(const MachineInstr *MI,		void getUpwardPressure(const MachineInstr *MI,
	std::vector<unsigned> &PressureResult,		std::vector<unsigned> &PressureResult,
	std::vector<unsigned> &MaxPressureResult);		std::vector<unsigned> &MaxPressureResult);
	/// Get the pressure of each PSet after traversing this instruction top-d own.		/// Get the pressure of each PSet after traversing this instruction top-d own.
	void getDownwardPressure(const MachineInstr *MI,		void getDownwardPressure(const MachineInstr *MI,
	skipping to change at line 307		skipping to change at line 420
	void getPressureAfterInst(const MachineInstr *MI,		void getPressureAfterInst(const MachineInstr *MI,
	std::vector<unsigned> &PressureResult,		std::vector<unsigned> &PressureResult,
	std::vector<unsigned> &MaxPressureResult) {		std::vector<unsigned> &MaxPressureResult) {
	if (isTopClosed())		if (isTopClosed())
	return getUpwardPressure(MI, PressureResult, MaxPressureResult);		return getUpwardPressure(MI, PressureResult, MaxPressureResult);
	assert(isBottomClosed() && "Uninitialized pressure tracker");		assert(isBottomClosed() && "Uninitialized pressure tracker");
	return getDownwardPressure(MI, PressureResult, MaxPressureResult);		return getDownwardPressure(MI, PressureResult, MaxPressureResult);
	}		}
			bool hasUntiedDef(unsigned VirtReg) const {
			return UntiedDefs.count(VirtReg);
			}
	void dump() const;		void dump() const;
	protected:		protected:
	const LiveInterval *getInterval(unsigned Reg) const;		const LiveRange *getLiveRange(unsigned Reg) const;
	void increaseRegPressure(ArrayRef<unsigned> Regs);		void increaseRegPressure(ArrayRef<unsigned> Regs);
	void decreaseRegPressure(ArrayRef<unsigned> Regs);		void decreaseRegPressure(ArrayRef<unsigned> Regs);
	void bumpUpwardPressure(const MachineInstr *MI);		void bumpUpwardPressure(const MachineInstr *MI);
	void bumpDownwardPressure(const MachineInstr *MI);		void bumpDownwardPressure(const MachineInstr *MI);
	};		};
			#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
			void dumpRegSetPressure(ArrayRef<unsigned> SetPressure,
			const TargetRegisterInfo *TRI);
			#endif
	} // end namespace llvm		} // end namespace llvm
	#endif		#endif
End of changes. 23 change blocks.
	24 lines changed or deleted		151 lines changed or added

	RegisterScavenging.h		RegisterScavenging.h
	skipping to change at line 134		skipping to change at line 134
	/// Return 0 if none is found.		/// Return 0 if none is found.
	unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;		unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
	/// Add a scavenging frame index.		/// Add a scavenging frame index.
	void addScavengingFrameIndex(int FI) {		void addScavengingFrameIndex(int FI) {
	Scavenged.push_back(ScavengedInfo(FI));		Scavenged.push_back(ScavengedInfo(FI));
	}		}
	/// Query whether a frame index is a scavenging frame index.		/// Query whether a frame index is a scavenging frame index.
	bool isScavengingFrameIndex(int FI) const {		bool isScavengingFrameIndex(int FI) const {
	for (SmallVector<ScavengedInfo, 2>::const_iterator I = Scavenged.begin( ),		for (SmallVectorImpl<ScavengedInfo>::const_iterator I = Scavenged.begin (),
	IE = Scavenged.end(); I != IE; ++I)		IE = Scavenged.end(); I != IE; ++I)
	if (I->FrameIndex == FI)		if (I->FrameIndex == FI)
	return true;		return true;
	return false;		return false;
	}		}
	/// Get an array of scavenging frame indices.		/// Get an array of scavenging frame indices.
	void getScavengingFrameIndices(SmallVectorImpl<int> &A) const {		void getScavengingFrameIndices(SmallVectorImpl<int> &A) const {
	for (SmallVector<ScavengedInfo, 2>::const_iterator I = Scavenged.begin( ),		for (SmallVectorImpl<ScavengedInfo>::const_iterator I = Scavenged.begin (),
	IE = Scavenged.end(); I != IE; ++I)		IE = Scavenged.end(); I != IE; ++I)
	if (I->FrameIndex >= 0)		if (I->FrameIndex >= 0)
	A.push_back(I->FrameIndex);		A.push_back(I->FrameIndex);
	}		}
	/// scavengeRegister - Make a register of the specific register class		/// scavengeRegister - Make a register of the specific register class
	/// available and do the appropriate bookkeeping. SPAdj is the stack		/// available and do the appropriate bookkeeping. SPAdj is the stack
	/// adjustment due to call frame, it's passed along to eliminateFrameInde x().		/// adjustment due to call frame, it's passed along to eliminateFrameInde x().
	/// Returns the scavenged register.		/// Returns the scavenged register.
	unsigned scavengeRegister(const TargetRegisterClass *RegClass,		unsigned scavengeRegister(const TargetRegisterClass *RegClass,
End of changes. 2 change blocks.
	2 lines changed or deleted		2 lines changed or added

	Registry.h		Registry.h
	skipping to change at line 17		skipping to change at line 17
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// Defines a registry template for discovering pluggable modules.		// Defines a registry template for discovering pluggable modules.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_SUPPORT_REGISTRY_H		#ifndef LLVM_SUPPORT_REGISTRY_H
	#define LLVM_SUPPORT_REGISTRY_H		#define LLVM_SUPPORT_REGISTRY_H
			#include "llvm/Support/Compiler.h"
	namespace llvm {		namespace llvm {
	/// A simple registry entry which provides only a name, description, and		/// A simple registry entry which provides only a name, description, and
	/// no-argument constructor.		/// no-argument constructor.
	template <typename T>		template <typename T>
	class SimpleRegistryEntry {		class SimpleRegistryEntry {
	const char *Name, *Desc;		const char *Name, *Desc;
	T *(*Ctor)();		T *(*Ctor)();
	public:		public:
	SimpleRegistryEntry(const char *N, const char *D, T *(*C)())		SimpleRegistryEntry(const char *N, const char *D, T *(*C)())
End of changes. 1 change blocks.
	0 lines changed or deleted		2 lines changed or added

	RelocVisitor.h		RelocVisitor.h
	skipping to change at line 21		skipping to change at line 21
	// in different file formats, such that a client can handle them in a unifi ed		// in different file formats, such that a client can handle them in a unifi ed
	// manner by only implementing a minimal number of functions.		// manner by only implementing a minimal number of functions.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_OBJECT_RELOCVISITOR_H		#ifndef LLVM_OBJECT_RELOCVISITOR_H
	#define LLVM_OBJECT_RELOCVISITOR_H		#define LLVM_OBJECT_RELOCVISITOR_H
	#include "llvm/ADT/StringRef.h"		#include "llvm/ADT/StringRef.h"
	#include "llvm/Object/ObjectFile.h"		#include "llvm/Object/ObjectFile.h"
			#include "llvm/Object/ELFObjectFile.h"
	#include "llvm/Support/Debug.h"		#include "llvm/Support/Debug.h"
	#include "llvm/Support/ELF.h"		#include "llvm/Support/ELF.h"
	#include "llvm/Support/raw_ostream.h"		#include "llvm/Support/raw_ostream.h"
	namespace llvm {		namespace llvm {
	namespace object {		namespace object {
	struct RelocToApply {		struct RelocToApply {
	// The computed value after applying the relevant relocations.		// The computed value after applying the relevant relocations.
	int64_t Value;		int64_t Value;
	skipping to change at line 83		skipping to change at line 84
	case llvm::ELF::R_386_PC32:		case llvm::ELF::R_386_PC32:
	return visitELF_386_PC32(R, Value, SecAddr);		return visitELF_386_PC32(R, Value, SecAddr);
	default:		default:
	HasError = true;		HasError = true;
	return RelocToApply();		return RelocToApply();
	}		}
	} else if (FileFormat == "ELF64-ppc64") {		} else if (FileFormat == "ELF64-ppc64") {
	switch (RelocType) {		switch (RelocType) {
	case llvm::ELF::R_PPC64_ADDR32:		case llvm::ELF::R_PPC64_ADDR32:
	return visitELF_PPC64_ADDR32(R, Value);		return visitELF_PPC64_ADDR32(R, Value);
			case llvm::ELF::R_PPC64_ADDR64:
			return visitELF_PPC64_ADDR64(R, Value);
			default:
			HasError = true;
			return RelocToApply();
			}
			} else if (FileFormat == "ELF32-ppc") {
			switch (RelocType) {
			case llvm::ELF::R_PPC_ADDR32:
			return visitELF_PPC_ADDR32(R, Value);
	default:		default:
	HasError = true;		HasError = true;
	return RelocToApply();		return RelocToApply();
	}		}
	} else if (FileFormat == "ELF32-mips") {		} else if (FileFormat == "ELF32-mips") {
	switch (RelocType) {		switch (RelocType) {
	case llvm::ELF::R_MIPS_32:		case llvm::ELF::R_MIPS_32:
	return visitELF_MIPS_32(R, Value);		return visitELF_MIPS_32(R, Value);
	default:		default:
	HasError = true;		HasError = true;
	skipping to change at line 126		skipping to change at line 137
	HasError = true;		HasError = true;
	return RelocToApply();		return RelocToApply();
	}		}
	bool error() { return HasError; }		bool error() { return HasError; }
	private:		private:
	StringRef FileFormat;		StringRef FileFormat;
	bool HasError;		bool HasError;
			int64_t getAddend32LE(RelocationRef R) {
			const ELF32LEObjectFile *Obj = cast<ELF32LEObjectFile>(R.getObjectFile(
			));
			DataRefImpl DRI = R.getRawDataRefImpl();
			int64_t Addend;
			Obj->getRelocationAddend(DRI, Addend);
			return Addend;
			}
			int64_t getAddend64LE(RelocationRef R) {
			const ELF64LEObjectFile *Obj = cast<ELF64LEObjectFile>(R.getObjectFile(
			));
			DataRefImpl DRI = R.getRawDataRefImpl();
			int64_t Addend;
			Obj->getRelocationAddend(DRI, Addend);
			return Addend;
			}
			int64_t getAddend32BE(RelocationRef R) {
			const ELF32BEObjectFile *Obj = cast<ELF32BEObjectFile>(R.getObjectFile(
			));
			DataRefImpl DRI = R.getRawDataRefImpl();
			int64_t Addend;
			Obj->getRelocationAddend(DRI, Addend);
			return Addend;
			}
			int64_t getAddend64BE(RelocationRef R) {
			const ELF64BEObjectFile *Obj = cast<ELF64BEObjectFile>(R.getObjectFile(
			));
			DataRefImpl DRI = R.getRawDataRefImpl();
			int64_t Addend;
			Obj->getRelocationAddend(DRI, Addend);
			return Addend;
			}
	/// Operations		/// Operations
	/// 386-ELF		/// 386-ELF
	RelocToApply visitELF_386_NONE(RelocationRef R) {		RelocToApply visitELF_386_NONE(RelocationRef R) {
	return RelocToApply(0, 0);		return RelocToApply(0, 0);
	}		}
	// Ideally the Addend here will be the addend in the data for		// Ideally the Addend here will be the addend in the data for
	// the relocation. It's not actually the case for Rel relocations.		// the relocation. It's not actually the case for Rel relocations.
	RelocToApply visitELF_386_32(RelocationRef R, uint64_t Value) {		RelocToApply visitELF_386_32(RelocationRef R, uint64_t Value) {
	int64_t Addend;		int64_t Addend = getAddend32LE(R);
	R.getAdditionalInfo(Addend);
	return RelocToApply(Value + Addend, 4);		return RelocToApply(Value + Addend, 4);
	}		}
	RelocToApply visitELF_386_PC32(RelocationRef R, uint64_t Value,		RelocToApply visitELF_386_PC32(RelocationRef R, uint64_t Value,
	uint64_t SecAddr) {		uint64_t SecAddr) {
	int64_t Addend;		int64_t Addend = getAddend32LE(R);
	R.getAdditionalInfo(Addend);
	uint64_t Address;		uint64_t Address;
	R.getOffset(Address);		R.getOffset(Address);
	return RelocToApply(Value + Addend - Address, 4);		return RelocToApply(Value + Addend - Address, 4);
	}		}
	/// X86-64 ELF		/// X86-64 ELF
	RelocToApply visitELF_X86_64_NONE(RelocationRef R) {		RelocToApply visitELF_X86_64_NONE(RelocationRef R) {
	return RelocToApply(0, 0);		return RelocToApply(0, 0);
	}		}
	RelocToApply visitELF_X86_64_64(RelocationRef R, uint64_t Value) {		RelocToApply visitELF_X86_64_64(RelocationRef R, uint64_t Value) {
	int64_t Addend;		int64_t Addend = getAddend64LE(R);
	R.getAdditionalInfo(Addend);
	return RelocToApply(Value + Addend, 8);		return RelocToApply(Value + Addend, 8);
	}		}
	RelocToApply visitELF_X86_64_PC32(RelocationRef R, uint64_t Value,		RelocToApply visitELF_X86_64_PC32(RelocationRef R, uint64_t Value,
	uint64_t SecAddr) {		uint64_t SecAddr) {
	int64_t Addend;		int64_t Addend = getAddend64LE(R);
	R.getAdditionalInfo(Addend);
	uint64_t Address;		uint64_t Address;
	R.getOffset(Address);		R.getOffset(Address);
	return RelocToApply(Value + Addend - Address, 4);		return RelocToApply(Value + Addend - Address, 4);
	}		}
	RelocToApply visitELF_X86_64_32(RelocationRef R, uint64_t Value) {		RelocToApply visitELF_X86_64_32(RelocationRef R, uint64_t Value) {
	int64_t Addend;		int64_t Addend = getAddend64LE(R);
	R.getAdditionalInfo(Addend);
	uint32_t Res = (Value + Addend) & 0xFFFFFFFF;		uint32_t Res = (Value + Addend) & 0xFFFFFFFF;
	return RelocToApply(Res, 4);		return RelocToApply(Res, 4);
	}		}
	RelocToApply visitELF_X86_64_32S(RelocationRef R, uint64_t Value) {		RelocToApply visitELF_X86_64_32S(RelocationRef R, uint64_t Value) {
	int64_t Addend;		int64_t Addend = getAddend64LE(R);
	R.getAdditionalInfo(Addend);
	int32_t Res = (Value + Addend) & 0xFFFFFFFF;		int32_t Res = (Value + Addend) & 0xFFFFFFFF;
	return RelocToApply(Res, 4);		return RelocToApply(Res, 4);
	}		}
	/// PPC64 ELF		/// PPC64 ELF
	RelocToApply visitELF_PPC64_ADDR32(RelocationRef R, uint64_t Value) {		RelocToApply visitELF_PPC64_ADDR32(RelocationRef R, uint64_t Value) {
	int64_t Addend;		int64_t Addend = getAddend64BE(R);
	R.getAdditionalInfo(Addend);		uint32_t Res = (Value + Addend) & 0xFFFFFFFF;
			return RelocToApply(Res, 4);
			}
			RelocToApply visitELF_PPC64_ADDR64(RelocationRef R, uint64_t Value) {
			int64_t Addend = getAddend64BE(R);
			return RelocToApply(Value + Addend, 8);
			}
			/// PPC32 ELF
			RelocToApply visitELF_PPC_ADDR32(RelocationRef R, uint64_t Value) {
			int64_t Addend = getAddend32BE(R);
	uint32_t Res = (Value + Addend) & 0xFFFFFFFF;		uint32_t Res = (Value + Addend) & 0xFFFFFFFF;
	return RelocToApply(Res, 4);		return RelocToApply(Res, 4);
	}		}
	/// MIPS ELF		/// MIPS ELF
	RelocToApply visitELF_MIPS_32(RelocationRef R, uint64_t Value) {		RelocToApply visitELF_MIPS_32(RelocationRef R, uint64_t Value) {
	int64_t Addend;		int64_t Addend;
	R.getAdditionalInfo(Addend);		getELFRelocationAddend(R, Addend);
	uint32_t Res = (Value + Addend) & 0xFFFFFFFF;		uint32_t Res = (Value + Addend) & 0xFFFFFFFF;
	return RelocToApply(Res, 4);		return RelocToApply(Res, 4);
	}		}
	// AArch64 ELF		// AArch64 ELF
	RelocToApply visitELF_AARCH64_ABS32(RelocationRef R, uint64_t Value) {		RelocToApply visitELF_AARCH64_ABS32(RelocationRef R, uint64_t Value) {
	int64_t Addend;		int64_t Addend = getAddend64LE(R);
	R.getAdditionalInfo(Addend);
	int64_t Res = Value + Addend;		int64_t Res = Value + Addend;
	// Overflow check allows for both signed and unsigned interpretation.		// Overflow check allows for both signed and unsigned interpretation.
	if (Res < INT32_MIN || Res > UINT32_MAX)		if (Res < INT32_MIN || Res > UINT32_MAX)
	HasError = true;		HasError = true;
	return RelocToApply(static_cast<uint32_t>(Res), 4);		return RelocToApply(static_cast<uint32_t>(Res), 4);
	}		}
	RelocToApply visitELF_AARCH64_ABS64(RelocationRef R, uint64_t Value) {		RelocToApply visitELF_AARCH64_ABS64(RelocationRef R, uint64_t Value) {
	int64_t Addend;		int64_t Addend = getAddend64LE(R);
	R.getAdditionalInfo(Addend);
	return RelocToApply(Value + Addend, 8);		return RelocToApply(Value + Addend, 8);
	}		}
	// SystemZ ELF		// SystemZ ELF
	RelocToApply visitELF_390_32(RelocationRef R, uint64_t Value) {		RelocToApply visitELF_390_32(RelocationRef R, uint64_t Value) {
	int64_t Addend;		int64_t Addend = getAddend64BE(R);
	R.getAdditionalInfo(Addend);
	int64_t Res = Value + Addend;		int64_t Res = Value + Addend;
	// Overflow check allows for both signed and unsigned interpretation.		// Overflow check allows for both signed and unsigned interpretation.
	if (Res < INT32_MIN || Res > UINT32_MAX)		if (Res < INT32_MIN || Res > UINT32_MAX)
	HasError = true;		HasError = true;
	return RelocToApply(static_cast<uint32_t>(Res), 4);		return RelocToApply(static_cast<uint32_t>(Res), 4);
	}		}
	RelocToApply visitELF_390_64(RelocationRef R, uint64_t Value) {		RelocToApply visitELF_390_64(RelocationRef R, uint64_t Value) {
	int64_t Addend;		int64_t Addend = getAddend64BE(R);
	R.getAdditionalInfo(Addend);
	return RelocToApply(Value + Addend, 8);		return RelocToApply(Value + Addend, 8);
	}		}
	};		};
	}		}
	}		}
	#endif		#endif
End of changes. 15 change blocks.
	23 lines changed or deleted		69 lines changed or added

	RuntimeDyld.h		RuntimeDyld.h
	skipping to change at line 19		skipping to change at line 19
	//		//
	// Interface for the runtime dynamic linker facilities of the MC-JIT.		// Interface for the runtime dynamic linker facilities of the MC-JIT.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_EXECUTIONENGINE_RUNTIMEDYLD_H		#ifndef LLVM_EXECUTIONENGINE_RUNTIMEDYLD_H
	#define LLVM_EXECUTIONENGINE_RUNTIMEDYLD_H		#define LLVM_EXECUTIONENGINE_RUNTIMEDYLD_H
	#include "llvm/ADT/StringRef.h"		#include "llvm/ADT/StringRef.h"
	#include "llvm/ExecutionEngine/ObjectBuffer.h"		#include "llvm/ExecutionEngine/ObjectBuffer.h"
			#include "llvm/ExecutionEngine/RTDyldMemoryManager.h"
	#include "llvm/Support/Memory.h"		#include "llvm/Support/Memory.h"
	namespace llvm {		namespace llvm {
	class RuntimeDyldImpl;		class RuntimeDyldImpl;
	class ObjectImage;		class ObjectImage;
	// RuntimeDyld clients often want to handle the memory management of
	// what gets placed where. For JIT clients, this is the subset of
	// JITMemoryManager required for dynamic loading of binaries.
	//
	// FIXME: As the RuntimeDyld fills out, additional routines will be needed
	// for the varying types of objects to be allocated.
	class RTDyldMemoryManager {
	RTDyldMemoryManager(const RTDyldMemoryManager&) LLVM_DELETED_FUNCTION;
	void operator=(const RTDyldMemoryManager&) LLVM_DELETED_FUNCTION;
	public:
	RTDyldMemoryManager() {}
	virtual ~RTDyldMemoryManager();
	/// Allocate a memory block of (at least) the given size suitable for
	/// executable code. The SectionID is a unique identifier assigned by the
	JIT
	/// engine, and optionally recorded by the memory manager to access a loa
	ded
	/// section.
	virtual uint8_t *allocateCodeSection(uintptr_t Size, unsigned Alignment,
	unsigned SectionID) = 0;
	/// Allocate a memory block of (at least) the given size suitable for dat
	a.
	/// The SectionID is a unique identifier assigned by the JIT engine, and
	/// optionally recorded by the memory manager to access a loaded section.
	virtual uint8_t *allocateDataSection(uintptr_t Size, unsigned Alignment,
	unsigned SectionID, bool IsReadOnly)
	= 0;
	/// This method returns the address of the specified function. As such it
	is
	/// only useful for resolving library symbols, not code generated symbols
	.
	///
	/// If AbortOnFailure is false and no function with the given name is
	/// found, this function returns a null pointer. Otherwise, it prints a
	/// message to stderr and aborts.
	virtual void *getPointerToNamedFunction(const std::string &Name,
	bool AbortOnFailure = true) = 0;
	/// This method is called when object loading is complete and section pag
	e
	/// permissions can be applied. It is up to the memory manager implement
	ation
	/// to decide whether or not to act on this method. The memory manager w
	ill
	/// typically allocate all sections as read-write and then apply specific
	/// permissions when this method is called.
	///
	/// Returns true if an error occurred, false otherwise.
	virtual bool applyPermissions(std::string *ErrMsg = 0) = 0;
	/// Register the EH frames with the runtime so that c++ exceptions work.
	The
	/// default implementation does nothing. Look at SectionMemoryManager for
	one
	/// that uses __register_frame.
	virtual void registerEHFrames(StringRef SectionData);
	};
	class RuntimeDyld {		class RuntimeDyld {
	RuntimeDyld(const RuntimeDyld &) LLVM_DELETED_FUNCTION;		RuntimeDyld(const RuntimeDyld &) LLVM_DELETED_FUNCTION;
	void operator=(const RuntimeDyld &) LLVM_DELETED_FUNCTION;		void operator=(const RuntimeDyld &) LLVM_DELETED_FUNCTION;
	// RuntimeDyldImpl is the actual class. RuntimeDyld is just the public		// RuntimeDyldImpl is the actual class. RuntimeDyld is just the public
	// interface.		// interface.
	RuntimeDyldImpl *Dyld;		RuntimeDyldImpl *Dyld;
	RTDyldMemoryManager *MM;		RTDyldMemoryManager *MM;
	protected:		protected:
	// Change the address associated with a section when resolving relocation s.		// Change the address associated with a section when resolving relocation s.
	skipping to change at line 116		skipping to change at line 67
	/// Resolve the relocations for all symbols we currently know about.		/// Resolve the relocations for all symbols we currently know about.
	void resolveRelocations();		void resolveRelocations();
	/// Map a section to its target address space value.		/// Map a section to its target address space value.
	/// Map the address of a JIT section as returned from the memory manager		/// Map the address of a JIT section as returned from the memory manager
	/// to the address in the target process as the running code will see it.		/// to the address in the target process as the running code will see it.
	/// This is the address which will be used for relocation resolution.		/// This is the address which will be used for relocation resolution.
	void mapSectionAddress(const void *LocalAddress, uint64_t TargetAddress);		void mapSectionAddress(const void *LocalAddress, uint64_t TargetAddress);
	StringRef getErrorString();		/// Register any EH frame sections that have been loaded but not previous
			ly
			/// registered with the memory manager. Note, RuntimeDyld is responsible
			/// for identifying the EH frame and calling the memory manager with the
			/// EH frame section data. However, the memory manager itself will handl
			e
			/// the actual target-specific EH frame registration.
			void registerEHFrames();
	StringRef getEHFrameSection();		void deregisterEHFrames();
			StringRef getErrorString();
	};		};
	} // end namespace llvm		} // end namespace llvm
	#endif		#endif
End of changes. 4 change blocks.
	63 lines changed or deleted		12 lines changed or added

	RuntimeLibcalls.h		RuntimeLibcalls.h
	//===-- CodeGen/RuntimeLibcall.h - Runtime Library Calls --------*- C++ -*- ===//		//===-- CodeGen/RuntimeLibcalls.h - Runtime Library Calls -------*- C++ -*- ===//
	//		//
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This file defines the enum representing the list of runtime library call s		// This file defines the enum representing the list of runtime library call s
	// the backend may emit during code generation, and also some helper functi ons.		// the backend may emit during code generation, and also some helper functi ons.
	skipping to change at line 191		skipping to change at line 191
	RINT_F32,		RINT_F32,
	RINT_F64,		RINT_F64,
	RINT_F80,		RINT_F80,
	RINT_F128,		RINT_F128,
	RINT_PPCF128,		RINT_PPCF128,
	NEARBYINT_F32,		NEARBYINT_F32,
	NEARBYINT_F64,		NEARBYINT_F64,
	NEARBYINT_F80,		NEARBYINT_F80,
	NEARBYINT_F128,		NEARBYINT_F128,
	NEARBYINT_PPCF128,		NEARBYINT_PPCF128,
			ROUND_F32,
			ROUND_F64,
			ROUND_F80,
			ROUND_F128,
			ROUND_PPCF128,
	FLOOR_F32,		FLOOR_F32,
	FLOOR_F64,		FLOOR_F64,
	FLOOR_F80,		FLOOR_F80,
	FLOOR_F128,		FLOOR_F128,
	FLOOR_PPCF128,		FLOOR_PPCF128,
	COPYSIGN_F32,		COPYSIGN_F32,
	COPYSIGN_F64,		COPYSIGN_F64,
	COPYSIGN_F80,		COPYSIGN_F80,
	COPYSIGN_F128,		COPYSIGN_F128,
	COPYSIGN_PPCF128,		COPYSIGN_PPCF128,
	skipping to change at line 323		skipping to change at line 328
	MEMMOVE,		MEMMOVE,
	// EXCEPTION HANDLING		// EXCEPTION HANDLING
	UNWIND_RESUME,		UNWIND_RESUME,
	// Family ATOMICs		// Family ATOMICs
	SYNC_VAL_COMPARE_AND_SWAP_1,		SYNC_VAL_COMPARE_AND_SWAP_1,
	SYNC_VAL_COMPARE_AND_SWAP_2,		SYNC_VAL_COMPARE_AND_SWAP_2,
	SYNC_VAL_COMPARE_AND_SWAP_4,		SYNC_VAL_COMPARE_AND_SWAP_4,
	SYNC_VAL_COMPARE_AND_SWAP_8,		SYNC_VAL_COMPARE_AND_SWAP_8,
			SYNC_VAL_COMPARE_AND_SWAP_16,
	SYNC_LOCK_TEST_AND_SET_1,		SYNC_LOCK_TEST_AND_SET_1,
	SYNC_LOCK_TEST_AND_SET_2,		SYNC_LOCK_TEST_AND_SET_2,
	SYNC_LOCK_TEST_AND_SET_4,		SYNC_LOCK_TEST_AND_SET_4,
	SYNC_LOCK_TEST_AND_SET_8,		SYNC_LOCK_TEST_AND_SET_8,
			SYNC_LOCK_TEST_AND_SET_16,
	SYNC_FETCH_AND_ADD_1,		SYNC_FETCH_AND_ADD_1,
	SYNC_FETCH_AND_ADD_2,		SYNC_FETCH_AND_ADD_2,
	SYNC_FETCH_AND_ADD_4,		SYNC_FETCH_AND_ADD_4,
	SYNC_FETCH_AND_ADD_8,		SYNC_FETCH_AND_ADD_8,
			SYNC_FETCH_AND_ADD_16,
	SYNC_FETCH_AND_SUB_1,		SYNC_FETCH_AND_SUB_1,
	SYNC_FETCH_AND_SUB_2,		SYNC_FETCH_AND_SUB_2,
	SYNC_FETCH_AND_SUB_4,		SYNC_FETCH_AND_SUB_4,
	SYNC_FETCH_AND_SUB_8,		SYNC_FETCH_AND_SUB_8,
			SYNC_FETCH_AND_SUB_16,
	SYNC_FETCH_AND_AND_1,		SYNC_FETCH_AND_AND_1,
	SYNC_FETCH_AND_AND_2,		SYNC_FETCH_AND_AND_2,
	SYNC_FETCH_AND_AND_4,		SYNC_FETCH_AND_AND_4,
	SYNC_FETCH_AND_AND_8,		SYNC_FETCH_AND_AND_8,
			SYNC_FETCH_AND_AND_16,
	SYNC_FETCH_AND_OR_1,		SYNC_FETCH_AND_OR_1,
	SYNC_FETCH_AND_OR_2,		SYNC_FETCH_AND_OR_2,
	SYNC_FETCH_AND_OR_4,		SYNC_FETCH_AND_OR_4,
	SYNC_FETCH_AND_OR_8,		SYNC_FETCH_AND_OR_8,
			SYNC_FETCH_AND_OR_16,
	SYNC_FETCH_AND_XOR_1,		SYNC_FETCH_AND_XOR_1,
	SYNC_FETCH_AND_XOR_2,		SYNC_FETCH_AND_XOR_2,
	SYNC_FETCH_AND_XOR_4,		SYNC_FETCH_AND_XOR_4,
	SYNC_FETCH_AND_XOR_8,		SYNC_FETCH_AND_XOR_8,
			SYNC_FETCH_AND_XOR_16,
	SYNC_FETCH_AND_NAND_1,		SYNC_FETCH_AND_NAND_1,
	SYNC_FETCH_AND_NAND_2,		SYNC_FETCH_AND_NAND_2,
	SYNC_FETCH_AND_NAND_4,		SYNC_FETCH_AND_NAND_4,
	SYNC_FETCH_AND_NAND_8,		SYNC_FETCH_AND_NAND_8,
			SYNC_FETCH_AND_NAND_16,
			SYNC_FETCH_AND_MAX_1,
			SYNC_FETCH_AND_MAX_2,
			SYNC_FETCH_AND_MAX_4,
			SYNC_FETCH_AND_MAX_8,
			SYNC_FETCH_AND_MAX_16,
			SYNC_FETCH_AND_UMAX_1,
			SYNC_FETCH_AND_UMAX_2,
			SYNC_FETCH_AND_UMAX_4,
			SYNC_FETCH_AND_UMAX_8,
			SYNC_FETCH_AND_UMAX_16,
			SYNC_FETCH_AND_MIN_1,
			SYNC_FETCH_AND_MIN_2,
			SYNC_FETCH_AND_MIN_4,
			SYNC_FETCH_AND_MIN_8,
			SYNC_FETCH_AND_MIN_16,
			SYNC_FETCH_AND_UMIN_1,
			SYNC_FETCH_AND_UMIN_2,
			SYNC_FETCH_AND_UMIN_4,
			SYNC_FETCH_AND_UMIN_8,
			SYNC_FETCH_AND_UMIN_16,
			// Stack Protector Fail.
			STACKPROTECTOR_CHECK_FAIL,
	UNKNOWN_LIBCALL		UNKNOWN_LIBCALL
	};		};
	/// getFPEXT - Return the FPEXT_*_* value for the given types, or		/// getFPEXT - Return the FPEXT_*_* value for the given types, or
	/// UNKNOWN_LIBCALL if there is none.		/// UNKNOWN_LIBCALL if there is none.
	Libcall getFPEXT(EVT OpVT, EVT RetVT);		Libcall getFPEXT(EVT OpVT, EVT RetVT);
	/// getFPROUND - Return the FPROUND_*_* value for the given types, or		/// getFPROUND - Return the FPROUND_*_* value for the given types, or
	/// UNKNOWN_LIBCALL if there is none.		/// UNKNOWN_LIBCALL if there is none.
End of changes. 10 change blocks.
	1 lines changed or deleted		37 lines changed or added

	SSAUpdater.h		SSAUpdater.h
	skipping to change at line 31		skipping to change at line 31
	class BasicBlock;		class BasicBlock;
	class Instruction;		class Instruction;
	class LoadInst;		class LoadInst;
	template<typename T> class SmallVectorImpl;		template<typename T> class SmallVectorImpl;
	template<typename T> class SSAUpdaterTraits;		template<typename T> class SSAUpdaterTraits;
	class PHINode;		class PHINode;
	class Type;		class Type;
	class Use;		class Use;
	class Value;		class Value;
	/// SSAUpdater - This class updates SSA form for a set of values defined in		/// \brief Helper class for SSA formation on a set of values defined in
	/// multiple blocks. This is used when code duplication or another unstruc		/// multiple blocks.
	tured		///
			/// This is used when code duplication or another unstructured
	/// transformation wants to rewrite a set of uses of one value with uses of a		/// transformation wants to rewrite a set of uses of one value with uses of a
	/// set of values.		/// set of values.
	class SSAUpdater {		class SSAUpdater {
	friend class SSAUpdaterTraits<SSAUpdater>;		friend class SSAUpdaterTraits<SSAUpdater>;
	private:		private:
	/// AvailableVals - This keeps track of which value to use on a per-block		/// This keeps track of which value to use on a per-block basis. When we
	/// basis. When we insert PHI nodes, we keep track of them here.		/// insert PHI nodes, we keep track of them here.
	//typedef DenseMap<BasicBlock*, Value*> AvailableValsTy;		//typedef DenseMap<BasicBlock*, Value*> AvailableValsTy;
	void *AV;		void *AV;
	/// ProtoType holds the type of the values being rewritten.		/// ProtoType holds the type of the values being rewritten.
	Type *ProtoType;		Type *ProtoType;
	// PHI nodes are given a name based on ProtoName.		/// PHI nodes are given a name based on ProtoName.
	std::string ProtoName;		std::string ProtoName;
	/// InsertedPHIs - If this is non-null, the SSAUpdater adds all PHI nodes		/// If this is non-null, the SSAUpdater adds all PHI nodes that it create
	that		s to
	/// it creates to the vector.		/// the vector.
	SmallVectorImpl<PHINode*> *InsertedPHIs;		SmallVectorImpl<PHINode*> *InsertedPHIs;
	public:		public:
	/// SSAUpdater constructor. If InsertedPHIs is specified, it will be fil led		/// If InsertedPHIs is specified, it will be filled
	/// in with all PHI Nodes created by rewriting.		/// in with all PHI Nodes created by rewriting.
	explicit SSAUpdater(SmallVectorImpl<PHINode*> *InsertedPHIs = 0);		explicit SSAUpdater(SmallVectorImpl<PHINode*> *InsertedPHIs = 0);
	~SSAUpdater();		~SSAUpdater();
	/// Initialize - Reset this object to get ready for a new set of SSA		/// \brief Reset this object to get ready for a new set of SSA updates wi
	/// updates with type 'Ty'. PHI nodes get a name based on 'Name'.		th
			/// type 'Ty'.
			///
			/// PHI nodes get a name based on 'Name'.
	void Initialize(Type *Ty, StringRef Name);		void Initialize(Type *Ty, StringRef Name);
	/// AddAvailableValue - Indicate that a rewritten value is available at t		/// \brief Indicate that a rewritten value is available in the specified
	he		block
	/// end of the specified block with the specified value.		/// with the specified value.
	void AddAvailableValue(BasicBlock *BB, Value *V);		void AddAvailableValue(BasicBlock *BB, Value *V);
	/// HasValueForBlock - Return true if the SSAUpdater already has a value		/// \brief Return true if the SSAUpdater already has a value for the spec
	for		ified
	/// the specified block.		/// block.
	bool HasValueForBlock(BasicBlock *BB) const;		bool HasValueForBlock(BasicBlock *BB) const;
	/// GetValueAtEndOfBlock - Construct SSA form, materializing a value that		/// \brief Construct SSA form, materializing a value that is live at the
	is		end
	/// live at the end of the specified block.		/// of the specified block.
	Value *GetValueAtEndOfBlock(BasicBlock *BB);		Value *GetValueAtEndOfBlock(BasicBlock *BB);
	/// GetValueInMiddleOfBlock - Construct SSA form, materializing a value t		/// \brief Construct SSA form, materializing a value that is live in the
	hat		/// middle of the specified block.
	/// is live in the middle of the specified block.
	///		///
	/// GetValueInMiddleOfBlock is the same as GetValueAtEndOfBlock except in		/// \c GetValueInMiddleOfBlock is the same as \c GetValueAtEndOfBlock exc
	one		ept
	/// important case: if there is a definition of the rewritten value after		/// in one important case: if there is a definition of the rewritten valu
	the		e
	/// 'use' in BB. Consider code like this:		/// after the 'use' in BB. Consider code like this:
	///		///
			/// \code
	/// X1 = ...		/// X1 = ...
	/// SomeBB:		/// SomeBB:
	/// use(X)		/// use(X)
	/// X2 = ...		/// X2 = ...
	/// br Cond, SomeBB, OutBB		/// br Cond, SomeBB, OutBB
			/// \endcode
	///		///
	/// In this case, there are two values (X1 and X2) added to the Available Vals		/// In this case, there are two values (X1 and X2) added to the Available Vals
	/// set by the client of the rewriter, and those values are both live out of		/// set by the client of the rewriter, and those values are both live out of
	/// their respective blocks. However, the use of X happens in the *middl e* of		/// their respective blocks. However, the use of X happens in the *middl e* of
	/// a block. Because of this, we need to insert a new PHI node in SomeBB to		/// a block. Because of this, we need to insert a new PHI node in SomeBB to
	/// merge the appropriate values, and this value isn't live out of the bl ock.		/// merge the appropriate values, and this value isn't live out of the bl ock.
	///
	Value *GetValueInMiddleOfBlock(BasicBlock *BB);		Value *GetValueInMiddleOfBlock(BasicBlock *BB);
	/// RewriteUse - Rewrite a use of the symbolic value. This handles PHI n		/// \brief Rewrite a use of the symbolic value.
	odes,		///
	/// which use their value in the corresponding predecessor. Note that th		/// This handles PHI nodes, which use their value in the corresponding
	is		/// predecessor. Note that this will not work if the use is supposed to b
	/// will not work if the use is supposed to be rewritten to a value defin		e
	ed in		/// rewritten to a value defined in the same block as the use, but above
	/// the same block as the use, but above it. Any 'AddAvailableValue's ad		it.
	ded		/// Any 'AddAvailableValue's added for the use's block will be considered
	/// for the use's block will be considered to be below it.		to
			/// be below it.
	void RewriteUse(Use &U);		void RewriteUse(Use &U);
	/// RewriteUseAfterInsertions - Rewrite a use, just like RewriteUse. How		/// \brief Rewrite a use like \c RewriteUse but handling in-block definit
	ever,		ions.
	/// this version of the method can rewrite uses in the same block as a		///
	/// definition, because it assumes that all uses of a value are below any		/// This version of the method can rewrite uses in the same block as
			/// a definition, because it assumes that all uses of a value are below a
			ny
	/// inserted values.		/// inserted values.
	void RewriteUseAfterInsertions(Use &U);		void RewriteUseAfterInsertions(Use &U);
	private:		private:
	Value *GetValueAtEndOfBlockInternal(BasicBlock *BB);		Value *GetValueAtEndOfBlockInternal(BasicBlock *BB);
	void operator=(const SSAUpdater&) LLVM_DELETED_FUNCTION;		void operator=(const SSAUpdater&) LLVM_DELETED_FUNCTION;
	SSAUpdater(const SSAUpdater&) LLVM_DELETED_FUNCTION;		SSAUpdater(const SSAUpdater&) LLVM_DELETED_FUNCTION;
	};		};
	/// LoadAndStorePromoter - This little helper class provides a convenient w		/// \brief Helper class for promoting a collection of loads and stores into
	ay to		SSA
	/// promote a collection of loads and stores into SSA Form using the SSAUpd		/// Form using the SSAUpdater.
	ater.		///
	/// This handles complexities that SSAUpdater doesn't, such as multiple loa ds		/// This handles complexities that SSAUpdater doesn't, such as multiple loa ds
	/// and stores in one block.		/// and stores in one block.
	///		///
	/// Clients of this class are expected to subclass this and implement the		/// Clients of this class are expected to subclass this and implement the
	/// virtual methods.		/// virtual methods.
	///
	class LoadAndStorePromoter {		class LoadAndStorePromoter {
	protected:		protected:
	SSAUpdater &SSA;		SSAUpdater &SSA;
	public:		public:
	LoadAndStorePromoter(const SmallVectorImpl<Instruction*> &Insts,		LoadAndStorePromoter(const SmallVectorImpl<Instruction*> &Insts,
	SSAUpdater &S, StringRef Name = StringRef());		SSAUpdater &S, StringRef Name = StringRef());
	virtual ~LoadAndStorePromoter() {}		virtual ~LoadAndStorePromoter() {}
	/// run - This does the promotion. Insts is a list of loads and stores t		/// \brief This does the promotion.
	o		///
	/// promote, and Name is the basename for the PHIs to insert. After this		/// Insts is a list of loads and stores to promote, and Name is the basen
	is		ame
	/// complete, the loads and stores are removed from the code.		/// for the PHIs to insert. After this is complete, the loads and stores
			are
			/// removed from the code.
	void run(const SmallVectorImpl<Instruction*> &Insts) const;		void run(const SmallVectorImpl<Instruction*> &Insts) const;
	/// Return true if the specified instruction is in the Inst list (which w		/// \brief Return true if the specified instruction is in the Inst list.
	as		///
	/// passed into the run method). Clients should implement this with a mo		/// The Insts list is the one passed into the constructor. Clients should
	re		/// implement this with a more efficient version if possible.
	/// efficient version if possible.
	virtual bool isInstInList(Instruction *I,		virtual bool isInstInList(Instruction *I,
	const SmallVectorImpl<Instruction*> &Insts) con st;		const SmallVectorImpl<Instruction*> &Insts) con st;
	/// doExtraRewritesBeforeFinalDeletion - This hook is invoked after all t		/// \brief This hook is invoked after all the stores are found and insert
	he		ed as
	/// stores are found and inserted as available values, but		/// available values.
	virtual void doExtraRewritesBeforeFinalDeletion() const {		virtual void doExtraRewritesBeforeFinalDeletion() const {
	}		}
	/// replaceLoadWithValue - Clients can choose to implement this to get		/// \brief Clients can choose to implement this to get notified right bef
	/// notified right before a load is RAUW'd another value.		ore
			/// a load is RAUW'd another value.
	virtual void replaceLoadWithValue(LoadInst *LI, Value *V) const {		virtual void replaceLoadWithValue(LoadInst *LI, Value *V) const {
	}		}
	/// This is called before each instruction is deleted.		/// \brief Called before each instruction is deleted.
	virtual void instructionDeleted(Instruction *I) const {		virtual void instructionDeleted(Instruction *I) const {
	}		}
	/// updateDebugInfo - This is called to update debug info associated with		/// \brief Called to update debug info associated with the instruction.
	the
	/// instruction.
	virtual void updateDebugInfo(Instruction *I) const {		virtual void updateDebugInfo(Instruction *I) const {
	}		}
	};		};
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 24 change blocks.
	67 lines changed or deleted		73 lines changed or added

	STLExtras.h		STLExtras.h
	skipping to change at line 216		skipping to change at line 216
	second = p.second;		second = p.second;
	return *this;		return *this;
	}		}
	};		};
	template <typename T1, typename T2>		template <typename T1, typename T2>
	inline tier<T1, T2> tie(T1& f, T2& s) {		inline tier<T1, T2> tie(T1& f, T2& s) {
	return tier<T1, T2>(f, s);		return tier<T1, T2>(f, s);
	}		}
			/// \brief Function object to check whether the first component of a std::p
			air
			/// compares less than the first component of another std::pair.
			struct less_first {
			template <typename T> bool operator()(const T &lhs, const T &rhs) const {
			return lhs.first < rhs.first;
			}
			};
			/// \brief Function object to check whether the second component of a std::
			pair
			/// compares less than the second component of another std::pair.
			struct less_second {
			template <typename T> bool operator()(const T &lhs, const T &rhs) const {
			return lhs.second < rhs.second;
			}
			};
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// Extra additions for arrays		// Extra additions for arrays
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	/// Find where an array ends (for ending iterators)		/// Find where an array ends (for ending iterators)
	/// This returns a pointer to the byte immediately		/// This returns a pointer to the byte immediately
	/// after the end of an array.		/// after the end of an array.
	template<class T, std::size_t N>		template<class T, std::size_t N>
	inline T *array_endof(T (&x)[N]) {		inline T *array_endof(T (&x)[N]) {
	return x+N;		return x+N;
	skipping to change at line 275		skipping to change at line 291
	/// NOTE: If qsort_r were portable, we could allow a custom comparator and		/// NOTE: If qsort_r were portable, we could allow a custom comparator and
	/// default to std::less.		/// default to std::less.
	template<class IteratorTy>		template<class IteratorTy>
	inline void array_pod_sort(IteratorTy Start, IteratorTy End) {		inline void array_pod_sort(IteratorTy Start, IteratorTy End) {
	// Don't dereference start iterator of empty sequence.		// Don't dereference start iterator of empty sequence.
	if (Start == End) return;		if (Start == End) return;
	qsort(&*Start, End-Start, sizeof(*Start),		qsort(&*Start, End-Start, sizeof(*Start),
	get_array_pod_sort_comparator(*Start));		get_array_pod_sort_comparator(*Start));
	}		}
	template<class IteratorTy>		template <class IteratorTy>
	inline void array_pod_sort(IteratorTy Start, IteratorTy End,		inline void array_pod_sort(
	int (*Compare)(const void*, const void*))		IteratorTy Start, IteratorTy End,
	{		int (*Compare)(
			const typename std::iterator_traits<IteratorTy>::value_type *,
			const typename std::iterator_traits<IteratorTy>::value_type *)) {
	// Don't dereference start iterator of empty sequence.		// Don't dereference start iterator of empty sequence.
	if (Start == End) return;		if (Start == End) return;
	qsort(&*Start, End-Start, sizeof(*Start), Compare);		qsort(&*Start, End - Start, sizeof(*Start),
			reinterpret_cast<int (*)(const void *, const void *)>(Compare));
	}		}
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// Extra additions to <algorithm>		// Extra additions to <algorithm>
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	/// For a container of pointers, deletes the pointers and then clears the		/// For a container of pointers, deletes the pointers and then clears the
	/// container.		/// container.
	template<typename Container>		template<typename Container>
	void DeleteContainerPointers(Container &C) {		void DeleteContainerPointers(Container &C) {
End of changes. 3 change blocks.
	5 lines changed or deleted		26 lines changed or added

	Scalar.h		Scalar.h
	skipping to change at line 18		skipping to change at line 18
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This header file defines prototypes for accessor functions that expose p asses		// This header file defines prototypes for accessor functions that expose p asses
	// in the Scalar transformations library.		// in the Scalar transformations library.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_TRANSFORMS_SCALAR_H		#ifndef LLVM_TRANSFORMS_SCALAR_H
	#define LLVM_TRANSFORMS_SCALAR_H		#define LLVM_TRANSFORMS_SCALAR_H
			#include "llvm/ADT/StringRef.h"
	namespace llvm {		namespace llvm {
	class FunctionPass;		class FunctionPass;
	class Pass;		class Pass;
	class GetElementPtrInst;		class GetElementPtrInst;
	class PassInfo;		class PassInfo;
	class TerminatorInst;		class TerminatorInst;
	class TargetLowering;		class TargetLowering;
			class TargetMachine;
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// ConstantPropagation - A worklist driven constant propagation pass		// ConstantPropagation - A worklist driven constant propagation pass
	//		//
	FunctionPass *createConstantPropagationPass();		FunctionPass *createConstantPropagationPass();
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// SCCP - Sparse conditional constant propagation.		// SCCP - Sparse conditional constant propagation.
	skipping to change at line 122		skipping to change at line 125
	//		//
	Pass *createLICMPass();		Pass *createLICMPass();
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// LoopStrengthReduce - This pass is strength reduces GEP instructions that use		// LoopStrengthReduce - This pass is strength reduces GEP instructions that use
	// a loop's canonical induction variable as one of their indices.		// a loop's canonical induction variable as one of their indices.
	//		//
	Pass *createLoopStrengthReducePass();		Pass *createLoopStrengthReducePass();
	Pass *createGlobalMergePass(const TargetLowering *TLI = 0);		Pass *createGlobalMergePass(const TargetMachine *TM = 0);
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// LoopUnswitch - This pass is a simple loop unswitching pass.		// LoopUnswitch - This pass is a simple loop unswitching pass.
	//		//
	Pass *createLoopUnswitchPass(bool OptimizeForSize = false);		Pass *createLoopUnswitchPass(bool OptimizeForSize = false);
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// LoopInstSimplify - This pass simplifies instructions in a loop's body.		// LoopInstSimplify - This pass simplifies instructions in a loop's body.
	//		//
	Pass *createLoopInstSimplifyPass();		Pass *createLoopInstSimplifyPass();
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// LoopUnroll - This pass is a simple loop unrolling pass.		// LoopUnroll - This pass is a simple loop unrolling pass.
	//		//
	Pass *createLoopUnrollPass(int Threshold = -1, int Count = -1, int AllowPar		Pass *createLoopUnrollPass(int Threshold = -1, int Count = -1,
	tial = -1);		int AllowPartial = -1, int Runtime = -1);
			//===----------------------------------------------------------------------
			===//
			//
			// LoopReroll - This pass is a simple loop rerolling pass.
			//
			Pass *createLoopRerollPass();
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// LoopRotate - This pass is a simple loop rotating pass.		// LoopRotate - This pass is a simple loop rotating pass.
	//		//
	Pass *createLoopRotatePass();		Pass *createLoopRotatePass();
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// LoopIdiom - This pass recognizes and replaces idioms in loops.		// LoopIdiom - This pass recognizes and replaces idioms in loops.
	skipping to change at line 202		skipping to change at line 212
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// CFGSimplification - Merge basic blocks, eliminate unreachable blocks,		// CFGSimplification - Merge basic blocks, eliminate unreachable blocks,
	// simplify terminator instructions, etc...		// simplify terminator instructions, etc...
	//		//
	FunctionPass *createCFGSimplificationPass();		FunctionPass *createCFGSimplificationPass();
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
			// FlattenCFG - flatten CFG, reduce number of conditional branches by using
			// parallel-and and parallel-or mode, etc...
			//
			FunctionPass *createFlattenCFGPass();
			//===----------------------------------------------------------------------
			===//
			//
			// CFG Structurization - Remove irreducible control flow
			//
			Pass *createStructurizeCFGPass();
			//===----------------------------------------------------------------------
			===//
			//
	// BreakCriticalEdges - Break all of the critical edges in the CFG by inser ting		// BreakCriticalEdges - Break all of the critical edges in the CFG by inser ting
	// a dummy basic block. This pass may be "required" by passes that cannot d eal		// a dummy basic block. This pass may be "required" by passes that cannot d eal
	// with critical edges. For this usage, a pass must call:		// with critical edges. For this usage, a pass must call:
	//		//
	// AU.addRequiredID(BreakCriticalEdgesID);		// AU.addRequiredID(BreakCriticalEdgesID);
	//		//
	// This pass obviously invalidates the CFG, but can update forward dominato r		// This pass obviously invalidates the CFG, but can update forward dominato r
	// (set, immediate dominators, tree, and frontier) information.		// (set, immediate dominators, tree, and frontier) information.
	//		//
	FunctionPass *createBreakCriticalEdgesPass();		FunctionPass *createBreakCriticalEdgesPass();
	skipping to change at line 250		skipping to change at line 273
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// LowerInvoke - This pass converts invoke and unwind instructions to use s jlj		// LowerInvoke - This pass converts invoke and unwind instructions to use s jlj
	// exception handling mechanisms. Note that after this pass runs the CFG i s not		// exception handling mechanisms. Note that after this pass runs the CFG i s not
	// entirely accurate (exceptional control flow edges are not correct anymor e) so		// entirely accurate (exceptional control flow edges are not correct anymor e) so
	// only very simple things should be done after the lowerinvoke pass has ru n		// only very simple things should be done after the lowerinvoke pass has ru n
	// (like generation of native code). This should *NOT* be used as a genera l		// (like generation of native code). This should *NOT* be used as a genera l
	// purpose "my LLVM-to-LLVM pass doesn't support the invoke instruction yet "		// purpose "my LLVM-to-LLVM pass doesn't support the invoke instruction yet "
	// lowering pass.		// lowering pass.
	//		//
	FunctionPass *createLowerInvokePass(const TargetLowering *TLI = 0);		FunctionPass *createLowerInvokePass(const TargetMachine *TM = 0,
	FunctionPass *createLowerInvokePass(const TargetLowering *TLI,		bool useExpensiveEHSupport = false);
	bool useExpensiveEHSupport);
	extern char &LowerInvokePassID;		extern char &LowerInvokePassID;
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// BlockPlacement - This pass reorders basic blocks in order to increase th
	e
	// number of fall-through conditional branches.
	//
	FunctionPass *createBlockPlacementPass();
	//===----------------------------------------------------------------------
	===//
	//
	// LCSSA - This pass inserts phi nodes at loop boundaries to simplify other loop		// LCSSA - This pass inserts phi nodes at loop boundaries to simplify other loop
	// optimizations.		// optimizations.
	//		//
	Pass *createLCSSAPass();		Pass *createLCSSAPass();
	extern char &LCSSAID;		extern char &LCSSAID;
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// EarlyCSE - This pass performs a simple and fast CSE pass over the domina tor		// EarlyCSE - This pass performs a simple and fast CSE pass over the domina tor
	// tree.		// tree.
	skipping to change at line 300		skipping to change at line 315
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// LoopDeletion - This pass performs DCE of non-infinite loops that it		// LoopDeletion - This pass performs DCE of non-infinite loops that it
	// can prove are dead.		// can prove are dead.
	//		//
	Pass *createLoopDeletionPass();		Pass *createLoopDeletionPass();
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	/// createSimplifyLibCallsPass - This pass optimizes specific calls to
	/// specific well-known (library) functions.
	FunctionPass *createSimplifyLibCallsPass();
	//===----------------------------------------------------------------------
	===//
	//
	// CodeGenPrepare - This pass prepares a function for instruction selection .		// CodeGenPrepare - This pass prepares a function for instruction selection .
	//		//
	FunctionPass *createCodeGenPreparePass(const TargetLowering *TLI = 0);		FunctionPass *createCodeGenPreparePass(const TargetMachine *TM = 0);
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// InstructionNamer - Give any unnamed non-void instructions "tmp" names.		// InstructionNamer - Give any unnamed non-void instructions "tmp" names.
	//		//
	FunctionPass *createInstructionNamerPass();		FunctionPass *createInstructionNamerPass();
	extern char &InstructionNamerID;		extern char &InstructionNamerID;
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	skipping to change at line 348		skipping to change at line 357
	//		//
	FunctionPass *createInstructionSimplifierPass();		FunctionPass *createInstructionSimplifierPass();
	extern char &InstructionSimplifierID;		extern char &InstructionSimplifierID;
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// LowerExpectIntrinsics - Removes llvm.expect intrinsics and creates		// LowerExpectIntrinsics - Removes llvm.expect intrinsics and creates
	// "block_weights" metadata.		// "block_weights" metadata.
	FunctionPass *createLowerExpectIntrinsicPass();		FunctionPass *createLowerExpectIntrinsicPass();
			//===----------------------------------------------------------------------
			===//
			//
			// PartiallyInlineLibCalls - Tries to inline the fast path of library
			// calls such as sqrt.
			//
			FunctionPass *createPartiallyInlineLibCallsPass();
			//===----------------------------------------------------------------------
			===//
			//
			// SampleProfilePass - Loads sample profile data from disk and generates
			// IR metadata to reflect the profile.
			FunctionPass *createSampleProfileLoaderPass();
			FunctionPass *createSampleProfileLoaderPass(StringRef Name);
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 10 change blocks.
	23 lines changed or deleted		47 lines changed or added

	ScalarEvolution.h		ScalarEvolution.h
	skipping to change at line 192		skipping to change at line 192
	/// BlockDisposition - An enum describing the relationship between a		/// BlockDisposition - An enum describing the relationship between a
	/// SCEV and a basic block.		/// SCEV and a basic block.
	enum BlockDisposition {		enum BlockDisposition {
	DoesNotDominateBlock, ///< The SCEV does not dominate the block.		DoesNotDominateBlock, ///< The SCEV does not dominate the block.
	DominatesBlock, ///< The SCEV dominates the block.		DominatesBlock, ///< The SCEV dominates the block.
	ProperlyDominatesBlock ///< The SCEV properly dominates the block.		ProperlyDominatesBlock ///< The SCEV properly dominates the block.
	};		};
	/// Convenient NoWrapFlags manipulation that hides enum casts and is		/// Convenient NoWrapFlags manipulation that hides enum casts and is
	/// visible in the ScalarEvolution name space.		/// visible in the ScalarEvolution name space.
	static SCEV::NoWrapFlags maskFlags(SCEV::NoWrapFlags Flags, int Mask) {		static SCEV::NoWrapFlags LLVM_ATTRIBUTE_UNUSED_RESULT
			maskFlags(SCEV::NoWrapFlags Flags, int Mask) {
	return (SCEV::NoWrapFlags)(Flags & Mask);		return (SCEV::NoWrapFlags)(Flags & Mask);
	}		}
	static SCEV::NoWrapFlags setFlags(SCEV::NoWrapFlags Flags,		static SCEV::NoWrapFlags LLVM_ATTRIBUTE_UNUSED_RESULT
	SCEV::NoWrapFlags OnFlags) {		setFlags(SCEV::NoWrapFlags Flags, SCEV::NoWrapFlags OnFlags) {
	return (SCEV::NoWrapFlags)(Flags | OnFlags);		return (SCEV::NoWrapFlags)(Flags | OnFlags);
	}		}
	static SCEV::NoWrapFlags clearFlags(SCEV::NoWrapFlags Flags,		static SCEV::NoWrapFlags LLVM_ATTRIBUTE_UNUSED_RESULT
	SCEV::NoWrapFlags OffFlags) {		clearFlags(SCEV::NoWrapFlags Flags, SCEV::NoWrapFlags OffFlags) {
	return (SCEV::NoWrapFlags)(Flags & ~OffFlags);		return (SCEV::NoWrapFlags)(Flags & ~OffFlags);
	}		}
	private:		private:
	/// SCEVCallbackVH - A CallbackVH to arrange for ScalarEvolution to be		/// SCEVCallbackVH - A CallbackVH to arrange for ScalarEvolution to be
	/// notified whenever a Value is deleted.		/// notified whenever a Value is deleted.
	class SCEVCallbackVH : public CallbackVH {		class SCEVCallbackVH : public CallbackVH {
	ScalarEvolution *SE;		ScalarEvolution *SE;
	virtual void deleted();		virtual void deleted();
	virtual void allUsesReplacedWith(Value *New);		virtual void allUsesReplacedWith(Value *New);
	skipping to change at line 364		skipping to change at line 365
	/// the PHI instructions that we attempt to compute constant evolutions for.		/// the PHI instructions that we attempt to compute constant evolutions for.
	/// This allows us to avoid potentially expensive recomputation of thes e		/// This allows us to avoid potentially expensive recomputation of thes e
	/// properties. An instruction maps to null if we are unable to comput e its		/// properties. An instruction maps to null if we are unable to comput e its
	/// exit value.		/// exit value.
	DenseMap<PHINode*, Constant*> ConstantEvolutionLoopExitValue;		DenseMap<PHINode*, Constant*> ConstantEvolutionLoopExitValue;
	/// ValuesAtScopes - This map contains entries for all the expressions		/// ValuesAtScopes - This map contains entries for all the expressions
	/// that we attempt to compute getSCEVAtScope information for, which ca n		/// that we attempt to compute getSCEVAtScope information for, which ca n
	/// be expensive in extreme cases.		/// be expensive in extreme cases.
	DenseMap<const SCEV *,		DenseMap<const SCEV *,
	std::map<const Loop *, const SCEV *> > ValuesAtScopes;		SmallVector<std::pair<const Loop *, const SCEV *>, 2> > Values AtScopes;
	/// LoopDispositions - Memoized computeLoopDisposition results.		/// LoopDispositions - Memoized computeLoopDisposition results.
	DenseMap<const SCEV *,		DenseMap<const SCEV *,
	std::map<const Loop *, LoopDisposition> > LoopDispositions;		SmallVector<std::pair<const Loop *, LoopDisposition>, 2> > Loo pDispositions;
	/// computeLoopDisposition - Compute a LoopDisposition value.		/// computeLoopDisposition - Compute a LoopDisposition value.
	LoopDisposition computeLoopDisposition(const SCEV *S, const Loop *L);		LoopDisposition computeLoopDisposition(const SCEV *S, const Loop *L);
	/// BlockDispositions - Memoized computeBlockDisposition results.		/// BlockDispositions - Memoized computeBlockDisposition results.
	DenseMap<const SCEV *,		DenseMap<const SCEV *,
	std::map<const BasicBlock *, BlockDisposition> > BlockDisposit ions;		SmallVector<std::pair<const BasicBlock *, BlockDisposition>, 2 > > BlockDispositions;
	/// computeBlockDisposition - Compute a BlockDisposition value.		/// computeBlockDisposition - Compute a BlockDisposition value.
	BlockDisposition computeBlockDisposition(const SCEV *S, const BasicBloc k *BB);		BlockDisposition computeBlockDisposition(const SCEV *S, const BasicBloc k *BB);
	/// UnsignedRanges - Memoized results from getUnsignedRange		/// UnsignedRanges - Memoized results from getUnsignedRange
	DenseMap<const SCEV *, ConstantRange> UnsignedRanges;		DenseMap<const SCEV *, ConstantRange> UnsignedRanges;
	/// SignedRanges - Memoized results from getSignedRange		/// SignedRanges - Memoized results from getSignedRange
	DenseMap<const SCEV *, ConstantRange> SignedRanges;		DenseMap<const SCEV *, ConstantRange> SignedRanges;
	skipping to change at line 429		skipping to change at line 430
	/// at most once for each SCEV+Loop pair.		/// at most once for each SCEV+Loop pair.
	///		///
	const SCEV *computeSCEVAtScope(const SCEV *S, const Loop *L);		const SCEV *computeSCEVAtScope(const SCEV *S, const Loop *L);
	/// ForgetSymbolicValue - This looks up computed SCEV values for all		/// ForgetSymbolicValue - This looks up computed SCEV values for all
	/// instructions that depend on the given instruction and removes them from		/// instructions that depend on the given instruction and removes them from
	/// the ValueExprMap map if they reference SymName. This is used during PHI		/// the ValueExprMap map if they reference SymName. This is used during PHI
	/// resolution.		/// resolution.
	void ForgetSymbolicName(Instruction *I, const SCEV *SymName);		void ForgetSymbolicName(Instruction *I, const SCEV *SymName);
	/// getBECount - Subtract the end and start values and divide by the st
	ep,
	/// rounding up, to get the number of times the backedge is executed. R
	eturn
	/// CouldNotCompute if an intermediate computation overflows.
	const SCEV *getBECount(const SCEV *Start,
	const SCEV *End,
	const SCEV *Step,
	bool NoWrap);
	/// getBackedgeTakenInfo - Return the BackedgeTakenInfo for the given		/// getBackedgeTakenInfo - Return the BackedgeTakenInfo for the given
	/// loop, lazily computing new values if the loop hasn't been analyzed		/// loop, lazily computing new values if the loop hasn't been analyzed
	/// yet.		/// yet.
	const BackedgeTakenInfo &getBackedgeTakenInfo(const Loop *L);		const BackedgeTakenInfo &getBackedgeTakenInfo(const Loop *L);
	/// ComputeBackedgeTakenCount - Compute the number of times the specifi ed		/// ComputeBackedgeTakenCount - Compute the number of times the specifi ed
	/// loop will iterate.		/// loop will iterate.
	BackedgeTakenInfo ComputeBackedgeTakenCount(const Loop *L);		BackedgeTakenInfo ComputeBackedgeTakenCount(const Loop *L);
	/// ComputeExitLimit - Compute the number of times the backedge of the		/// ComputeExitLimit - Compute the number of times the backedge of the
	skipping to change at line 501		skipping to change at line 494
	/// the specified value for nonzero will execute. If not computable, r eturn		/// the specified value for nonzero will execute. If not computable, r eturn
	/// CouldNotCompute.		/// CouldNotCompute.
	ExitLimit HowFarToNonZero(const SCEV *V, const Loop *L);		ExitLimit HowFarToNonZero(const SCEV *V, const Loop *L);
	/// HowManyLessThans - Return the number of times an exit condition		/// HowManyLessThans - Return the number of times an exit condition
	/// containing the specified less-than comparison will execute. If not		/// containing the specified less-than comparison will execute. If not
	/// computable, return CouldNotCompute. isSigned specifies whether the		/// computable, return CouldNotCompute. isSigned specifies whether the
	/// less-than is signed.		/// less-than is signed.
	ExitLimit HowManyLessThans(const SCEV *LHS, const SCEV *RHS,		ExitLimit HowManyLessThans(const SCEV *LHS, const SCEV *RHS,
	const Loop *L, bool isSigned, bool IsSubExpr );		const Loop *L, bool isSigned, bool IsSubExpr );
			ExitLimit HowManyGreaterThans(const SCEV *LHS, const SCEV *RHS,
			const Loop *L, bool isSigned, bool IsSubE
			xpr);
	/// getPredecessorWithUniqueSuccessorForBB - Return a predecessor of BB		/// getPredecessorWithUniqueSuccessorForBB - Return a predecessor of BB
	/// (which may not be an immediate predecessor) which has exactly one		/// (which may not be an immediate predecessor) which has exactly one
	/// successor from which BB is reachable, or null if no such block is		/// successor from which BB is reachable, or null if no such block is
	/// found.		/// found.
	std::pair<BasicBlock *, BasicBlock *>		std::pair<BasicBlock *, BasicBlock *>
	getPredecessorWithUniqueSuccessorForBB(BasicBlock *BB);		getPredecessorWithUniqueSuccessorForBB(BasicBlock *BB);
	/// isImpliedCond - Test whether the condition described by Pred, LHS, and		/// isImpliedCond - Test whether the condition described by Pred, LHS, and
	/// RHS is true whenever the given FoundCondValue value evaluates to tr ue.		/// RHS is true whenever the given FoundCondValue value evaluates to tr ue.
	skipping to change at line 548		skipping to change at line 543
	/// isKnownPredicateWithRanges - Test if the given expression is known to		/// isKnownPredicateWithRanges - Test if the given expression is known to
	/// satisfy the condition described by Pred and the known constant rang es		/// satisfy the condition described by Pred and the known constant rang es
	/// of LHS and RHS.		/// of LHS and RHS.
	///		///
	bool isKnownPredicateWithRanges(ICmpInst::Predicate Pred,		bool isKnownPredicateWithRanges(ICmpInst::Predicate Pred,
	const SCEV *LHS, const SCEV *RHS);		const SCEV *LHS, const SCEV *RHS);
	/// forgetMemoizedResults - Drop memoized information computed for S.		/// forgetMemoizedResults - Drop memoized information computed for S.
	void forgetMemoizedResults(const SCEV *S);		void forgetMemoizedResults(const SCEV *S);
			/// Return false iff given SCEV contains a SCEVUnknown with NULL value-
			/// pointer.
			bool checkValidity(const SCEV *S) const;
	public:		public:
	static char ID; // Pass identification, replacement for typeid		static char ID; // Pass identification, replacement for typeid
	ScalarEvolution();		ScalarEvolution();
	LLVMContext &getContext() const { return F->getContext(); }		LLVMContext &getContext() const { return F->getContext(); }
	/// isSCEVable - Test if values of the given type are analyzable within		/// isSCEVable - Test if values of the given type are analyzable within
	/// the SCEV framework. This primarily includes integer types, and it		/// the SCEV framework. This primarily includes integer types, and it
	/// can optionally include pointer types if the ScalarEvolution class		/// can optionally include pointer types if the ScalarEvolution class
	/// has access to target-specific information.		/// has access to target-specific information.
	skipping to change at line 635		skipping to change at line 634
	}		}
	const SCEV *getSMaxExpr(const SCEV *LHS, const SCEV *RHS);		const SCEV *getSMaxExpr(const SCEV *LHS, const SCEV *RHS);
	const SCEV *getSMaxExpr(SmallVectorImpl<const SCEV *> &Operands);		const SCEV *getSMaxExpr(SmallVectorImpl<const SCEV *> &Operands);
	const SCEV *getUMaxExpr(const SCEV *LHS, const SCEV *RHS);		const SCEV *getUMaxExpr(const SCEV *LHS, const SCEV *RHS);
	const SCEV *getUMaxExpr(SmallVectorImpl<const SCEV *> &Operands);		const SCEV *getUMaxExpr(SmallVectorImpl<const SCEV *> &Operands);
	const SCEV *getSMinExpr(const SCEV *LHS, const SCEV *RHS);		const SCEV *getSMinExpr(const SCEV *LHS, const SCEV *RHS);
	const SCEV *getUMinExpr(const SCEV *LHS, const SCEV *RHS);		const SCEV *getUMinExpr(const SCEV *LHS, const SCEV *RHS);
	const SCEV *getUnknown(Value *V);		const SCEV *getUnknown(Value *V);
	const SCEV *getCouldNotCompute();		const SCEV *getCouldNotCompute();
	/// getSizeOfExpr - Return an expression for sizeof on the given type.		/// getSizeOfExpr - Return an expression for sizeof AllocTy that is typ
	///		e
	const SCEV *getSizeOfExpr(Type *AllocTy);		/// IntTy
	/// getAlignOfExpr - Return an expression for alignof on the given type
	.
	///		///
	const SCEV *getAlignOfExpr(Type *AllocTy);		const SCEV *getSizeOfExpr(Type *IntTy, Type *AllocTy);
	/// getOffsetOfExpr - Return an expression for offsetof on the given fi		/// getOffsetOfExpr - Return an expression for offsetof on the given fi
	eld.		eld
			/// with type IntTy
	///		///
	const SCEV *getOffsetOfExpr(StructType *STy, unsigned FieldNo);		const SCEV *getOffsetOfExpr(Type *IntTy, StructType *STy, unsigned Fiel
			dNo);
	/// getOffsetOfExpr - Return an expression for offsetof on the given fi
	eld.
	///
	const SCEV *getOffsetOfExpr(Type *CTy, Constant *FieldNo);
	/// getNegativeSCEV - Return the SCEV object corresponding to -V.		/// getNegativeSCEV - Return the SCEV object corresponding to -V.
	///		///
	const SCEV *getNegativeSCEV(const SCEV *V);		const SCEV *getNegativeSCEV(const SCEV *V);
	/// getNotSCEV - Return the SCEV object corresponding to ~V.		/// getNotSCEV - Return the SCEV object corresponding to ~V.
	///		///
	const SCEV *getNotSCEV(const SCEV *V);		const SCEV *getNotSCEV(const SCEV *V);
	/// getMinusSCEV - Return LHS-RHS. Minus is represented in SCEV as A+B *-1.		/// getMinusSCEV - Return LHS-RHS. Minus is represented in SCEV as A+B *-1.
	skipping to change at line 885		skipping to change at line 878
	/// indirect operand.		/// indirect operand.
	bool hasOperand(const SCEV *S, const SCEV *Op) const;		bool hasOperand(const SCEV *S, const SCEV *Op) const;
	virtual bool runOnFunction(Function &F);		virtual bool runOnFunction(Function &F);
	virtual void releaseMemory();		virtual void releaseMemory();
	virtual void getAnalysisUsage(AnalysisUsage &AU) const;		virtual void getAnalysisUsage(AnalysisUsage &AU) const;
	virtual void print(raw_ostream &OS, const Module* = 0) const;		virtual void print(raw_ostream &OS, const Module* = 0) const;
	virtual void verifyAnalysis() const;		virtual void verifyAnalysis() const;
	private:		private:
			/// Compute the backedge taken count knowing the interval difference, t
			he
			/// stride and presence of the equality in the comparison.
			const SCEV *computeBECount(const SCEV *Delta, const SCEV *Stride,
			bool Equality);
			/// Verify if an linear IV with positive stride can overflow when in a
			/// less-than comparison, knowing the invariant term of the comparison,
			/// the stride and the knowledge of NSW/NUW flags on the recurrence.
			bool doesIVOverflowOnLT(const SCEV *RHS, const SCEV *Stride,
			bool IsSigned, bool NoWrap);
			/// Verify if an linear IV with negative stride can overflow when in a
			/// greater-than comparison, knowing the invariant term of the comparis
			on,
			/// the stride and the knowledge of NSW/NUW flags on the recurrence.
			bool doesIVOverflowOnGT(const SCEV *RHS, const SCEV *Stride,
			bool IsSigned, bool NoWrap);
			private:
	FoldingSet<SCEV> UniqueSCEVs;		FoldingSet<SCEV> UniqueSCEVs;
	BumpPtrAllocator SCEVAllocator;		BumpPtrAllocator SCEVAllocator;
	/// FirstUnknown - The head of a linked list of all SCEVUnknown		/// FirstUnknown - The head of a linked list of all SCEVUnknown
	/// values that have been allocated. This is used by releaseMemory		/// values that have been allocated. This is used by releaseMemory
	/// to locate them all and call their destructors.		/// to locate them all and call their destructors.
	SCEVUnknown *FirstUnknown;		SCEVUnknown *FirstUnknown;
	};		};
	}		}
End of changes. 14 change blocks.
	33 lines changed or deleted		45 lines changed or added

	ScalarEvolutionExpander.h		ScalarEvolutionExpander.h
	skipping to change at line 29		skipping to change at line 29
	#include "llvm/IR/IRBuilder.h"		#include "llvm/IR/IRBuilder.h"
	#include "llvm/Support/TargetFolder.h"		#include "llvm/Support/TargetFolder.h"
	#include "llvm/Support/ValueHandle.h"		#include "llvm/Support/ValueHandle.h"
	#include <set>		#include <set>
	namespace llvm {		namespace llvm {
	class TargetTransformInfo;		class TargetTransformInfo;
	/// Return true if the given expression is safe to expand in the sense th at		/// Return true if the given expression is safe to expand in the sense th at
	/// all materialized values are safe to speculate.		/// all materialized values are safe to speculate.
	bool isSafeToExpand(const SCEV *S);		bool isSafeToExpand(const SCEV *S, ScalarEvolution &SE);
	/// SCEVExpander - This class uses information about analyze scalars to		/// SCEVExpander - This class uses information about analyze scalars to
	/// rewrite expressions in canonical form.		/// rewrite expressions in canonical form.
	///		///
	/// Clients should create an instance of this class when rewriting is nee ded,		/// Clients should create an instance of this class when rewriting is nee ded,
	/// and destroy it when finished to allow the release of the associated		/// and destroy it when finished to allow the release of the associated
	/// memory.		/// memory.
	class SCEVExpander : public SCEVVisitor<SCEVExpander, Value*> {		class SCEVExpander : public SCEVVisitor<SCEVExpander, Value*> {
	ScalarEvolution &SE;		ScalarEvolution &SE;
	skipping to change at line 255		skipping to change at line 255
	Value *visitSMaxExpr(const SCEVSMaxExpr *S);		Value *visitSMaxExpr(const SCEVSMaxExpr *S);
	Value *visitUMaxExpr(const SCEVUMaxExpr *S);		Value *visitUMaxExpr(const SCEVUMaxExpr *S);
	Value *visitUnknown(const SCEVUnknown *S) {		Value *visitUnknown(const SCEVUnknown *S) {
	return S->getValue();		return S->getValue();
	}		}
	void rememberInstruction(Value *I);		void rememberInstruction(Value *I);
	void restoreInsertPoint(BasicBlock *BB, BasicBlock::iterator I);
	bool isNormalAddRecExprPHI(PHINode *PN, Instruction *IncV, const Loop * L);		bool isNormalAddRecExprPHI(PHINode *PN, Instruction *IncV, const Loop * L);
	bool isExpandedAddRecExprPHI(PHINode *PN, Instruction *IncV, const Loop *L);		bool isExpandedAddRecExprPHI(PHINode *PN, Instruction *IncV, const Loop *L);
	Value *expandAddRecExprLiterally(const SCEVAddRecExpr *);		Value *expandAddRecExprLiterally(const SCEVAddRecExpr *);
	PHINode *getAddRecExprPHILiterally(const SCEVAddRecExpr *Normalized,		PHINode *getAddRecExprPHILiterally(const SCEVAddRecExpr *Normalized,
	const Loop *L,		const Loop *L,
	Type *ExpandTy,		Type *ExpandTy,
	Type *IntTy);		Type *IntTy);
	Value *expandIVInc(PHINode *PN, Value *StepV, const Loop *L,		Value *expandIVInc(PHINode *PN, Value *StepV, const Loop *L,
End of changes. 2 change blocks.
	3 lines changed or deleted		1 lines changed or added

	ScalarEvolutionExpressions.h		ScalarEvolutionExpressions.h
	skipping to change at line 350		skipping to change at line 350
	/// getPostIncExpr - Return an expression representing the value of		/// getPostIncExpr - Return an expression representing the value of
	/// this expression one iteration of the loop ahead.		/// this expression one iteration of the loop ahead.
	const SCEVAddRecExpr *getPostIncExpr(ScalarEvolution &SE) const {		const SCEVAddRecExpr *getPostIncExpr(ScalarEvolution &SE) const {
	return cast<SCEVAddRecExpr>(SE.getAddExpr(this, getStepRecurrence(SE) ));		return cast<SCEVAddRecExpr>(SE.getAddExpr(this, getStepRecurrence(SE) ));
	}		}
	/// Methods for support type inquiry through isa, cast, and dyn_cast:		/// Methods for support type inquiry through isa, cast, and dyn_cast:
	static inline bool classof(const SCEV *S) {		static inline bool classof(const SCEV *S) {
	return S->getSCEVType() == scAddRecExpr;		return S->getSCEVType() == scAddRecExpr;
	}		}
			/// Splits the SCEV into two vectors of SCEVs representing the subscrip
			ts
			/// and sizes of an array access. Returns the remainder of the
			/// delinearization that is the offset start of the array.
			const SCEV *delinearize(ScalarEvolution &SE,
			SmallVectorImpl<const SCEV *> &Subscripts,
			SmallVectorImpl<const SCEV *> &Sizes) const;
	};		};
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	/// SCEVSMaxExpr - This class represents a signed maximum selection.		/// SCEVSMaxExpr - This class represents a signed maximum selection.
	///		///
	class SCEVSMaxExpr : public SCEVCommutativeExpr {		class SCEVSMaxExpr : public SCEVCommutativeExpr {
	friend class ScalarEvolution;		friend class ScalarEvolution;
	SCEVSMaxExpr(const FoldingSetNodeIDRef ID,		SCEVSMaxExpr(const FoldingSetNodeIDRef ID,
	const SCEV *const *O, size_t N)		const SCEV *const *O, size_t N)
	skipping to change at line 546		skipping to change at line 553
	}		}
	};		};
	/// Use SCEVTraversal to visit all nodes in the givien expression tree.		/// Use SCEVTraversal to visit all nodes in the givien expression tree.
	template<typename SV>		template<typename SV>
	void visitAll(const SCEV *Root, SV& Visitor) {		void visitAll(const SCEV *Root, SV& Visitor) {
	SCEVTraversal<SV> T(Visitor);		SCEVTraversal<SV> T(Visitor);
	T.visitAll(Root);		T.visitAll(Root);
	}		}
	/// The SCEVRewriter takes a scalar evolution expression and copies all i		typedef DenseMap<const Value*, Value*> ValueToValueMap;
	ts
	/// components. The result after a rewrite is an identical SCEV.		/// The SCEVParameterRewriter takes a scalar evolution expression and upd
	struct SCEVRewriter		ates
	: public SCEVVisitor<SCEVRewriter, const SCEV*> {		/// the SCEVUnknown components following the Map (Value -> Value).
			struct SCEVParameterRewriter
			: public SCEVVisitor<SCEVParameterRewriter, const SCEV*> {
	public:		public:
	SCEVRewriter(ScalarEvolution &S) : SE(S) {}		static const SCEV *rewrite(const SCEV *Scev, ScalarEvolution &SE,
			ValueToValueMap &Map) {
			SCEVParameterRewriter Rewriter(SE, Map);
			return Rewriter.visit(Scev);
			}
	virtual ~SCEVRewriter() {}		SCEVParameterRewriter(ScalarEvolution &S, ValueToValueMap &M)
			: SE(S), Map(M) {}
	virtual const SCEV *visitConstant(const SCEVConstant *Constant) {		const SCEV *visitConstant(const SCEVConstant *Constant) {
	return Constant;		return Constant;
	}		}
	virtual const SCEV *visitTruncateExpr(const SCEVTruncateExpr *Expr) {		const SCEV *visitTruncateExpr(const SCEVTruncateExpr *Expr) {
	const SCEV *Operand = visit(Expr->getOperand());		const SCEV *Operand = visit(Expr->getOperand());
	return SE.getTruncateExpr(Operand, Expr->getType());		return SE.getTruncateExpr(Operand, Expr->getType());
	}		}
	virtual const SCEV *visitZeroExtendExpr(const SCEVZeroExtendExpr *Expr) {		const SCEV *visitZeroExtendExpr(const SCEVZeroExtendExpr *Expr) {
	const SCEV *Operand = visit(Expr->getOperand());		const SCEV *Operand = visit(Expr->getOperand());
	return SE.getZeroExtendExpr(Operand, Expr->getType());		return SE.getZeroExtendExpr(Operand, Expr->getType());
	}		}
	virtual const SCEV *visitSignExtendExpr(const SCEVSignExtendExpr *Expr) {		const SCEV *visitSignExtendExpr(const SCEVSignExtendExpr *Expr) {
	const SCEV *Operand = visit(Expr->getOperand());		const SCEV *Operand = visit(Expr->getOperand());
	return SE.getSignExtendExpr(Operand, Expr->getType());		return SE.getSignExtendExpr(Operand, Expr->getType());
	}		}
	virtual const SCEV *visitAddExpr(const SCEVAddExpr *Expr) {		const SCEV *visitAddExpr(const SCEVAddExpr *Expr) {
	SmallVector<const SCEV *, 2> Operands;		SmallVector<const SCEV *, 2> Operands;
	for (int i = 0, e = Expr->getNumOperands(); i < e; ++i)		for (int i = 0, e = Expr->getNumOperands(); i < e; ++i)
	Operands.push_back(visit(Expr->getOperand(i)));		Operands.push_back(visit(Expr->getOperand(i)));
	return SE.getAddExpr(Operands);		return SE.getAddExpr(Operands);
	}		}
	virtual const SCEV *visitMulExpr(const SCEVMulExpr *Expr) {		const SCEV *visitMulExpr(const SCEVMulExpr *Expr) {
	SmallVector<const SCEV *, 2> Operands;		SmallVector<const SCEV *, 2> Operands;
	for (int i = 0, e = Expr->getNumOperands(); i < e; ++i)		for (int i = 0, e = Expr->getNumOperands(); i < e; ++i)
	Operands.push_back(visit(Expr->getOperand(i)));		Operands.push_back(visit(Expr->getOperand(i)));
	return SE.getMulExpr(Operands);		return SE.getMulExpr(Operands);
	}		}
	virtual const SCEV *visitUDivExpr(const SCEVUDivExpr *Expr) {		const SCEV *visitUDivExpr(const SCEVUDivExpr *Expr) {
	return SE.getUDivExpr(visit(Expr->getLHS()), visit(Expr->getRHS()));		return SE.getUDivExpr(visit(Expr->getLHS()), visit(Expr->getRHS()));
	}		}
	virtual const SCEV *visitAddRecExpr(const SCEVAddRecExpr *Expr) {		const SCEV *visitAddRecExpr(const SCEVAddRecExpr *Expr) {
	SmallVector<const SCEV *, 2> Operands;		SmallVector<const SCEV *, 2> Operands;
	for (int i = 0, e = Expr->getNumOperands(); i < e; ++i)		for (int i = 0, e = Expr->getNumOperands(); i < e; ++i)
	Operands.push_back(visit(Expr->getOperand(i)));		Operands.push_back(visit(Expr->getOperand(i)));
	return SE.getAddRecExpr(Operands, Expr->getLoop(),		return SE.getAddRecExpr(Operands, Expr->getLoop(),
	Expr->getNoWrapFlags());		Expr->getNoWrapFlags());
	}		}
	virtual const SCEV *visitSMaxExpr(const SCEVSMaxExpr *Expr) {		const SCEV *visitSMaxExpr(const SCEVSMaxExpr *Expr) {
	SmallVector<const SCEV *, 2> Operands;		SmallVector<const SCEV *, 2> Operands;
	for (int i = 0, e = Expr->getNumOperands(); i < e; ++i)		for (int i = 0, e = Expr->getNumOperands(); i < e; ++i)
	Operands.push_back(visit(Expr->getOperand(i)));		Operands.push_back(visit(Expr->getOperand(i)));
	return SE.getSMaxExpr(Operands);		return SE.getSMaxExpr(Operands);
	}		}
	virtual const SCEV *visitUMaxExpr(const SCEVUMaxExpr *Expr) {		const SCEV *visitUMaxExpr(const SCEVUMaxExpr *Expr) {
	SmallVector<const SCEV *, 2> Operands;		SmallVector<const SCEV *, 2> Operands;
	for (int i = 0, e = Expr->getNumOperands(); i < e; ++i)		for (int i = 0, e = Expr->getNumOperands(); i < e; ++i)
	Operands.push_back(visit(Expr->getOperand(i)));		Operands.push_back(visit(Expr->getOperand(i)));
	return SE.getUMaxExpr(Operands);		return SE.getUMaxExpr(Operands);
	}		}
	virtual const SCEV *visitUnknown(const SCEVUnknown *Expr) {		const SCEV *visitUnknown(const SCEVUnknown *Expr) {
	return Expr;
	}
	virtual const SCEV *visitCouldNotCompute(const SCEVCouldNotCompute *Exp
	r) {
	return Expr;
	}
	protected:
	ScalarEvolution &SE;
	};
	typedef DenseMap<const Value*, Value*> ValueToValueMap;
	/// The SCEVParameterRewriter takes a scalar evolution expression and upd
	ates
	/// the SCEVUnknown components following the Map (Value -> Value).
	struct SCEVParameterRewriter: public SCEVRewriter {
	public:
	static const SCEV *rewrite(const SCEV *Scev, ScalarEvolution &SE,
	ValueToValueMap &Map) {
	SCEVParameterRewriter Rewriter(SE, Map);
	return Rewriter.visit(Scev);
	}
	SCEVParameterRewriter(ScalarEvolution &S, ValueToValueMap &M)
	: SCEVRewriter(S), Map(M) {}
	virtual const SCEV *visitUnknown(const SCEVUnknown *Expr) {
	Value *V = Expr->getValue();		Value *V = Expr->getValue();
	if (Map.count(V))		if (Map.count(V))
	return SE.getUnknown(Map[V]);		return SE.getUnknown(Map[V]);
	return Expr;		return Expr;
	}		}
			const SCEV *visitCouldNotCompute(const SCEVCouldNotCompute *Expr) {
			return Expr;
			}
	private:		private:
			ScalarEvolution &SE;
	ValueToValueMap &Map;		ValueToValueMap &Map;
	};		};
	typedef DenseMap<const Loop*, const SCEV*> LoopToScevMapT;		typedef DenseMap<const Loop*, const SCEV*> LoopToScevMapT;
	/// The SCEVApplyRewriter takes a scalar evolution expression and applies		/// The SCEVApplyRewriter takes a scalar evolution expression and applies
	/// the Map (Loop -> SCEV) to all AddRecExprs.		/// the Map (Loop -> SCEV) to all AddRecExprs.
	struct SCEVApplyRewriter: public SCEVRewriter {		struct SCEVApplyRewriter
			: public SCEVVisitor<SCEVApplyRewriter, const SCEV*> {
	public:		public:
	static const SCEV *rewrite(const SCEV *Scev, LoopToScevMapT &Map,		static const SCEV *rewrite(const SCEV *Scev, LoopToScevMapT &Map,
	ScalarEvolution &SE) {		ScalarEvolution &SE) {
	SCEVApplyRewriter Rewriter(SE, Map);		SCEVApplyRewriter Rewriter(SE, Map);
	return Rewriter.visit(Scev);		return Rewriter.visit(Scev);
	}		}
	SCEVApplyRewriter(ScalarEvolution &S, LoopToScevMapT &M)		SCEVApplyRewriter(ScalarEvolution &S, LoopToScevMapT &M)
	: SCEVRewriter(S), Map(M) {}		: SE(S), Map(M) {}
			const SCEV *visitConstant(const SCEVConstant *Constant) {
			return Constant;
			}
			const SCEV *visitTruncateExpr(const SCEVTruncateExpr *Expr) {
			const SCEV *Operand = visit(Expr->getOperand());
			return SE.getTruncateExpr(Operand, Expr->getType());
			}
			const SCEV *visitZeroExtendExpr(const SCEVZeroExtendExpr *Expr) {
			const SCEV *Operand = visit(Expr->getOperand());
			return SE.getZeroExtendExpr(Operand, Expr->getType());
			}
			const SCEV *visitSignExtendExpr(const SCEVSignExtendExpr *Expr) {
			const SCEV *Operand = visit(Expr->getOperand());
			return SE.getSignExtendExpr(Operand, Expr->getType());
			}
			const SCEV *visitAddExpr(const SCEVAddExpr *Expr) {
			SmallVector<const SCEV *, 2> Operands;
			for (int i = 0, e = Expr->getNumOperands(); i < e; ++i)
			Operands.push_back(visit(Expr->getOperand(i)));
			return SE.getAddExpr(Operands);
			}
	virtual const SCEV *visitAddRecExpr(const SCEVAddRecExpr *Expr) {		const SCEV *visitMulExpr(const SCEVMulExpr *Expr) {
			SmallVector<const SCEV *, 2> Operands;
			for (int i = 0, e = Expr->getNumOperands(); i < e; ++i)
			Operands.push_back(visit(Expr->getOperand(i)));
			return SE.getMulExpr(Operands);
			}
			const SCEV *visitUDivExpr(const SCEVUDivExpr *Expr) {
			return SE.getUDivExpr(visit(Expr->getLHS()), visit(Expr->getRHS()));
			}
			const SCEV *visitAddRecExpr(const SCEVAddRecExpr *Expr) {
	SmallVector<const SCEV *, 2> Operands;		SmallVector<const SCEV *, 2> Operands;
	for (int i = 0, e = Expr->getNumOperands(); i < e; ++i)		for (int i = 0, e = Expr->getNumOperands(); i < e; ++i)
	Operands.push_back(visit(Expr->getOperand(i)));		Operands.push_back(visit(Expr->getOperand(i)));
	const Loop *L = Expr->getLoop();		const Loop *L = Expr->getLoop();
	const SCEV *Res = SE.getAddRecExpr(Operands, L, Expr->getNoWrapFlags( ));		const SCEV *Res = SE.getAddRecExpr(Operands, L, Expr->getNoWrapFlags( ));
	if (0 == Map.count(L))		if (0 == Map.count(L))
	return Res;		return Res;
	const SCEVAddRecExpr *Rec = (const SCEVAddRecExpr *) Res;		const SCEVAddRecExpr *Rec = (const SCEVAddRecExpr *) Res;
	return Rec->evaluateAtIteration(Map[L], SE);		return Rec->evaluateAtIteration(Map[L], SE);
	}		}
			const SCEV *visitSMaxExpr(const SCEVSMaxExpr *Expr) {
			SmallVector<const SCEV *, 2> Operands;
			for (int i = 0, e = Expr->getNumOperands(); i < e; ++i)
			Operands.push_back(visit(Expr->getOperand(i)));
			return SE.getSMaxExpr(Operands);
			}
			const SCEV *visitUMaxExpr(const SCEVUMaxExpr *Expr) {
			SmallVector<const SCEV *, 2> Operands;
			for (int i = 0, e = Expr->getNumOperands(); i < e; ++i)
			Operands.push_back(visit(Expr->getOperand(i)));
			return SE.getUMaxExpr(Operands);
			}
			const SCEV *visitUnknown(const SCEVUnknown *Expr) {
			return Expr;
			}
			const SCEV *visitCouldNotCompute(const SCEVCouldNotCompute *Expr) {
			return Expr;
			}
	private:		private:
			ScalarEvolution &SE;
	LoopToScevMapT &Map;		LoopToScevMapT &Map;
	};		};
	/// Applies the Map (Loop -> SCEV) to the given Scev.		/// Applies the Map (Loop -> SCEV) to the given Scev.
	static inline const SCEV *apply(const SCEV *Scev, LoopToScevMapT &Map,		static inline const SCEV *apply(const SCEV *Scev, LoopToScevMapT &Map,
	ScalarEvolution &SE) {		ScalarEvolution &SE) {
	return SCEVApplyRewriter::rewrite(Scev, Map, SE);		return SCEVApplyRewriter::rewrite(Scev, Map, SE);
	}		}
	}		}
End of changes. 23 change blocks.
	49 lines changed or deleted		103 lines changed or added

	ScheduleDAG.h		ScheduleDAG.h
	skipping to change at line 93		skipping to change at line 93
	unsigned Reg;		unsigned Reg;
	/// Order - Additional information about Order dependencies.		/// Order - Additional information about Order dependencies.
	unsigned OrdKind; // enum OrderKind		unsigned OrdKind; // enum OrderKind
	} Contents;		} Contents;
	/// Latency - The time associated with this edge. Often this is just		/// Latency - The time associated with this edge. Often this is just
	/// the value of the Latency field of the predecessor, however advanced		/// the value of the Latency field of the predecessor, however advanced
	/// models may provide additional information about specific edges.		/// models may provide additional information about specific edges.
	unsigned Latency;		unsigned Latency;
	/// Record MinLatency seperately from "expected" Latency.
	///
	/// FIXME: this field is not packed on LP64. Convert to 16-bit DAG edge
	/// latency after introducing saturating truncation.
	unsigned MinLatency;
	public:		public:
	/// SDep - Construct a null SDep. This is only for use by container		/// SDep - Construct a null SDep. This is only for use by container
	/// classes which require default constructors. SUnits may not		/// classes which require default constructors. SUnits may not
	/// have null SDep edges.		/// have null SDep edges.
	SDep() : Dep(0, Data) {}		SDep() : Dep(0, Data) {}
	/// SDep - Construct an SDep with the specified values.		/// SDep - Construct an SDep with the specified values.
	SDep(SUnit *S, Kind kind, unsigned Reg)		SDep(SUnit *S, Kind kind, unsigned Reg)
	: Dep(S, kind), Contents() {		: Dep(S, kind), Contents() {
	skipping to change at line 123		skipping to change at line 118
	assert(Reg != 0 &&		assert(Reg != 0 &&
	"SDep::Anti and SDep::Output must use a non-zero Reg!");		"SDep::Anti and SDep::Output must use a non-zero Reg!");
	Contents.Reg = Reg;		Contents.Reg = Reg;
	Latency = 0;		Latency = 0;
	break;		break;
	case Data:		case Data:
	Contents.Reg = Reg;		Contents.Reg = Reg;
	Latency = 1;		Latency = 1;
	break;		break;
	}		}
	MinLatency = Latency;
	}		}
	SDep(SUnit *S, OrderKind kind)		SDep(SUnit *S, OrderKind kind)
	: Dep(S, Order), Contents(), Latency(0), MinLatency(0) {		: Dep(S, Order), Contents(), Latency(0) {
	Contents.OrdKind = kind;		Contents.OrdKind = kind;
	}		}
	/// Return true if the specified SDep is equivalent except for latency.		/// Return true if the specified SDep is equivalent except for latency.
	bool overlaps(const SDep &Other) const {		bool overlaps(const SDep &Other) const {
	if (Dep != Other.Dep) return false;		if (Dep != Other.Dep) return false;
	switch (Dep.getInt()) {		switch (Dep.getInt()) {
	case Data:		case Data:
	case Anti:		case Anti:
	case Output:		case Output:
	return Contents.Reg == Other.Contents.Reg;		return Contents.Reg == Other.Contents.Reg;
	case Order:		case Order:
	return Contents.OrdKind == Other.Contents.OrdKind;		return Contents.OrdKind == Other.Contents.OrdKind;
	}		}
	llvm_unreachable("Invalid dependency kind!");		llvm_unreachable("Invalid dependency kind!");
	}		}
	bool operator==(const SDep &Other) const {		bool operator==(const SDep &Other) const {
	return overlaps(Other)		return overlaps(Other) && Latency == Other.Latency;
	&& Latency == Other.Latency && MinLatency == Other.MinLatency;
	}		}
	bool operator!=(const SDep &Other) const {		bool operator!=(const SDep &Other) const {
	return !operator==(Other);		return !operator==(Other);
	}		}
	/// getLatency - Return the latency value for this edge, which roughly		/// getLatency - Return the latency value for this edge, which roughly
	/// means the minimum number of cycles that must elapse between the		/// means the minimum number of cycles that must elapse between the
	/// predecessor and the successor, given that they have this edge		/// predecessor and the successor, given that they have this edge
	/// between them.		/// between them.
	unsigned getLatency() const {		unsigned getLatency() const {
	return Latency;		return Latency;
	}		}
	/// setLatency - Set the latency for this edge.		/// setLatency - Set the latency for this edge.
	void setLatency(unsigned Lat) {		void setLatency(unsigned Lat) {
	Latency = Lat;		Latency = Lat;
	}		}
	/// getMinLatency - Return the minimum latency for this edge. Minimum
	/// latency is used for scheduling groups, while normal (expected) late
	ncy
	/// is for instruction cost and critical path.
	unsigned getMinLatency() const {
	return MinLatency;
	}
	/// setMinLatency - Set the minimum latency for this edge.
	void setMinLatency(unsigned Lat) {
	MinLatency = Lat;
	}
	//// getSUnit - Return the SUnit to which this edge points.		//// getSUnit - Return the SUnit to which this edge points.
	SUnit *getSUnit() const {		SUnit *getSUnit() const {
	return Dep.getPointer();		return Dep.getPointer();
	}		}
	//// setSUnit - Assign the SUnit to which this edge points.		//// setSUnit - Assign the SUnit to which this edge points.
	void setSUnit(SUnit *SU) {		void setSUnit(SUnit *SU) {
	Dep.setPointer(SU);		Dep.setPointer(SU);
	}		}
	skipping to change at line 270		skipping to change at line 251
	Contents.Reg = Reg;		Contents.Reg = Reg;
	}		}
	};		};
	template <>		template <>
	struct isPodLike<SDep> { static const bool value = true; };		struct isPodLike<SDep> { static const bool value = true; };
	/// SUnit - Scheduling unit. This is a node in the scheduling DAG.		/// SUnit - Scheduling unit. This is a node in the scheduling DAG.
	class SUnit {		class SUnit {
	private:		private:
	enum { BoundaryID = ~0u };		enum LLVM_ENUM_INT_TYPE(unsigned) { BoundaryID = ~0u };
	SDNode *Node; // Representative node.		SDNode *Node; // Representative node.
	MachineInstr *Instr; // Alternatively, a MachineInstr.		MachineInstr *Instr; // Alternatively, a MachineInstr.
	public:		public:
	SUnit *OrigNode; // If not this, the node from which		SUnit *OrigNode; // If not this, the node from which
	// this node was cloned.		// this node was cloned.
	// (SD scheduling only)		// (SD scheduling only)
	const MCSchedClassDesc *SchedClass; // NULL or resolved SchedClass.		const MCSchedClassDesc *SchedClass; // NULL or resolved SchedClass.
	// Preds/Succs - The SUnits before/after us in the graph.		// Preds/Succs - The SUnits before/after us in the graph.
	SmallVector<SDep, 4> Preds; // All sunit predecessors.		SmallVector<SDep, 4> Preds; // All sunit predecessors.
	SmallVector<SDep, 4> Succs; // All sunit successors.		SmallVector<SDep, 4> Succs; // All sunit successors.
	typedef SmallVector<SDep, 4>::iterator pred_iterator;		typedef SmallVectorImpl<SDep>::iterator pred_iterator;
	typedef SmallVector<SDep, 4>::iterator succ_iterator;		typedef SmallVectorImpl<SDep>::iterator succ_iterator;
	typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator;		typedef SmallVectorImpl<SDep>::const_iterator const_pred_iterator;
	typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator;		typedef SmallVectorImpl<SDep>::const_iterator const_succ_iterator;
	unsigned NodeNum; // Entry # of node in the node vect or.		unsigned NodeNum; // Entry # of node in the node vect or.
	unsigned NodeQueueId; // Queue id of node.		unsigned NodeQueueId; // Queue id of node.
	unsigned NumPreds; // # of SDep::Data preds.		unsigned NumPreds; // # of SDep::Data preds.
	unsigned NumSuccs; // # of SDep::Data sucss.		unsigned NumSuccs; // # of SDep::Data sucss.
	unsigned NumPredsLeft; // # of preds not scheduled.		unsigned NumPredsLeft; // # of preds not scheduled.
	unsigned NumSuccsLeft; // # of succs not scheduled.		unsigned NumSuccsLeft; // # of succs not scheduled.
	unsigned WeakPredsLeft; // # of weak preds not scheduled.		unsigned WeakPredsLeft; // # of weak preds not scheduled.
	unsigned WeakSuccsLeft; // # of weak succs not scheduled.		unsigned WeakSuccsLeft; // # of weak succs not scheduled.
	unsigned short NumRegDefsLeft; // # of reg defs with no scheduled use.		unsigned short NumRegDefsLeft; // # of reg defs with no scheduled use.
End of changes. 7 change blocks.
	27 lines changed or deleted		7 lines changed or added

	ScheduleDAGInstrs.h		ScheduleDAGInstrs.h
	skipping to change at line 31		skipping to change at line 31
	#include "llvm/CodeGen/TargetSchedule.h"		#include "llvm/CodeGen/TargetSchedule.h"
	#include "llvm/Support/Compiler.h"		#include "llvm/Support/Compiler.h"
	#include "llvm/Target/TargetRegisterInfo.h"		#include "llvm/Target/TargetRegisterInfo.h"
	namespace llvm {		namespace llvm {
	class MachineFrameInfo;		class MachineFrameInfo;
	class MachineLoopInfo;		class MachineLoopInfo;
	class MachineDominatorTree;		class MachineDominatorTree;
	class LiveIntervals;		class LiveIntervals;
	class RegPressureTracker;		class RegPressureTracker;
			class PressureDiffs;
	/// An individual mapping from virtual register number to SUnit.		/// An individual mapping from virtual register number to SUnit.
	struct VReg2SUnit {		struct VReg2SUnit {
	unsigned VirtReg;		unsigned VirtReg;
	SUnit *SU;		SUnit *SU;
	VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}		VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
	unsigned getSparseSetIndex() const {		unsigned getSparseSetIndex() const {
	return TargetRegisterInfo::virtReg2Index(VirtReg);		return TargetRegisterInfo::virtReg2Index(VirtReg);
	skipping to change at line 59		skipping to change at line 60
	unsigned Reg;		unsigned Reg;
	PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}		PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
	unsigned getSparseSetIndex() const { return Reg; }		unsigned getSparseSetIndex() const { return Reg; }
	};		};
	/// Use a SparseMultiSet to track physical registers. Storage is only		/// Use a SparseMultiSet to track physical registers. Storage is only
	/// allocated once for the pass. It can be cleared in constant time and r eused		/// allocated once for the pass. It can be cleared in constant time and r eused
	/// without any frees.		/// without any frees.
	typedef SparseMultiSet<PhysRegSUOper, llvm::identity<unsigned>, uint16_t>		typedef SparseMultiSet<PhysRegSUOper, llvm::identity<unsigned>, uint16_t>
	Reg2SUnitsMap;		Reg2SUnitsMap;
	/// Use SparseSet as a SparseMap by relying on the fact that it never		/// Use SparseSet as a SparseMap by relying on the fact that it never
	/// compares ValueT's, only unsigned keys. This allows the set to be clea red		/// compares ValueT's, only unsigned keys. This allows the set to be clea red
	/// between scheduling regions in constant time as long as ValueT does no t		/// between scheduling regions in constant time as long as ValueT does no t
	/// require a destructor.		/// require a destructor.
	typedef SparseSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2SUnitMap;		typedef SparseSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2SUnitMap;
			/// Track local uses of virtual registers. These uses are gathered by the
			DAG
			/// builder and may be consulted by the scheduler to avoid iterating an e
			ntire
			/// vreg use list.
			typedef SparseMultiSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2UseMap;
	/// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of		/// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
	/// MachineInstrs.		/// MachineInstrs.
	class ScheduleDAGInstrs : public ScheduleDAG {		class ScheduleDAGInstrs : public ScheduleDAG {
	protected:		protected:
	const MachineLoopInfo &MLI;		const MachineLoopInfo &MLI;
	const MachineDominatorTree &MDT;		const MachineDominatorTree &MDT;
	const MachineFrameInfo *MFI;		const MachineFrameInfo *MFI;
	/// Live Intervals provides reaching defs in preRA scheduling.		/// Live Intervals provides reaching defs in preRA scheduling.
	LiveIntervals *LIS;		LiveIntervals *LIS;
	/// TargetSchedModel provides an interface to the machine model.		/// TargetSchedModel provides an interface to the machine model.
	TargetSchedModel SchedModel;		TargetSchedModel SchedModel;
	/// isPostRA flag indicates vregs cannot be present.		/// isPostRA flag indicates vregs cannot be present.
	bool IsPostRA;		bool IsPostRA;
	/// UnitLatencies (misnamed) flag avoids computing def-use latencies, u
	sing
	/// the def-side latency only.
	bool UnitLatencies;
	/// The standard DAG builder does not normally include terminators as D AG		/// The standard DAG builder does not normally include terminators as D AG
	/// nodes because it does not create the necessary dependencies to prev ent		/// nodes because it does not create the necessary dependencies to prev ent
	/// reordering. A specialized scheduler can overide		/// reordering. A specialized scheduler can overide
	/// TargetInstrInfo::isSchedulingBoundary then enable this flag to indi cate		/// TargetInstrInfo::isSchedulingBoundary then enable this flag to indi cate
	/// it has taken responsibility for scheduling the terminator correctly .		/// it has taken responsibility for scheduling the terminator correctly .
	bool CanHandleTerminators;		bool CanHandleTerminators;
	/// State specific to the current scheduling region.		/// State specific to the current scheduling region.
	/// ------------------------------------------------		/// ------------------------------------------------
	/// The block in which to insert instructions		/// The block in which to insert instructions
	MachineBasicBlock *BB;		MachineBasicBlock *BB;
	/// The beginning of the range to be scheduled.		/// The beginning of the range to be scheduled.
	MachineBasicBlock::iterator RegionBegin;		MachineBasicBlock::iterator RegionBegin;
	/// The end of the range to be scheduled.		/// The end of the range to be scheduled.
	MachineBasicBlock::iterator RegionEnd;		MachineBasicBlock::iterator RegionEnd;
	/// The index in BB of RegionEnd.		/// Instructions in this region (distance(RegionBegin, RegionEnd)).
	///		unsigned NumRegionInstrs;
	/// This is the instruction number from the top of the current block, n
	ot
	/// the SlotIndex. It is only used by the AntiDepBreaker and should be
	/// removed once that client is obsolete.
	unsigned EndIndex;
	/// After calling BuildSchedGraph, each machine instruction in the curr ent		/// After calling BuildSchedGraph, each machine instruction in the curr ent
	/// scheduling region is mapped to an SUnit.		/// scheduling region is mapped to an SUnit.
	DenseMap<MachineInstr*, SUnit*> MISUnitMap;		DenseMap<MachineInstr*, SUnit*> MISUnitMap;
			/// After calling BuildSchedGraph, each vreg used in the scheduling reg
			ion
			/// is mapped to a set of SUnits. These include all local vreg uses, no
			t
			/// just the uses for a singly defined vreg.
			VReg2UseMap VRegUses;
	/// State internal to DAG building.		/// State internal to DAG building.
	/// -------------------------------		/// -------------------------------
	/// Defs, Uses - Remember where defs and uses of each register are as w e		/// Defs, Uses - Remember where defs and uses of each register are as w e
	/// iterate upward through the instructions. This is allocated here ins tead		/// iterate upward through the instructions. This is allocated here ins tead
	/// of inside BuildSchedGraph to avoid the need for it to be initialize d and		/// of inside BuildSchedGraph to avoid the need for it to be initialize d and
	/// destructed for each block.		/// destructed for each block.
	Reg2SUnitsMap Defs;		Reg2SUnitsMap Defs;
	Reg2SUnitsMap Uses;		Reg2SUnitsMap Uses;
	/// Track the last instructon in this region defining each virtual regi ster.		/// Track the last instruction in this region defining each virtual reg ister.
	VReg2SUnitMap VRegDefs;		VReg2SUnitMap VRegDefs;
	/// PendingLoads - Remember where unknown loads are after the most rece nt		/// PendingLoads - Remember where unknown loads are after the most rece nt
	/// unknown store, as we iterate. As with Defs and Uses, this is here		/// unknown store, as we iterate. As with Defs and Uses, this is here
	/// to minimize construction/destruction.		/// to minimize construction/destruction.
	std::vector<SUnit *> PendingLoads;		std::vector<SUnit *> PendingLoads;
	/// DbgValues - Remember instruction that precedes DBG_VALUE.		/// DbgValues - Remember instruction that precedes DBG_VALUE.
	/// These are generated by buildSchedGraph but persist so they can be		/// These are generated by buildSchedGraph but persist so they can be
	/// referenced when emitting the final schedule.		/// referenced when emitting the final schedule.
	skipping to change at line 161		skipping to change at line 165
	virtual ~ScheduleDAGInstrs() {}		virtual ~ScheduleDAGInstrs() {}
	/// \brief Expose LiveIntervals for use in DAG mutators and such.		/// \brief Expose LiveIntervals for use in DAG mutators and such.
	LiveIntervals *getLIS() const { return LIS; }		LiveIntervals *getLIS() const { return LIS; }
	/// \brief Get the machine model for instruction scheduling.		/// \brief Get the machine model for instruction scheduling.
	const TargetSchedModel *getSchedModel() const { return &SchedModel; }		const TargetSchedModel *getSchedModel() const { return &SchedModel; }
	/// \brief Resolve and cache a resolved scheduling class for an SUnit.		/// \brief Resolve and cache a resolved scheduling class for an SUnit.
	const MCSchedClassDesc *getSchedClass(SUnit *SU) const {		const MCSchedClassDesc *getSchedClass(SUnit *SU) const {
	if (!SU->SchedClass)		if (!SU->SchedClass && SchedModel.hasInstrSchedModel())
	SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());		SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
	return SU->SchedClass;		return SU->SchedClass;
	}		}
	/// begin - Return an iterator to the top of the current scheduling reg ion.		/// begin - Return an iterator to the top of the current scheduling reg ion.
	MachineBasicBlock::iterator begin() const { return RegionBegin; }		MachineBasicBlock::iterator begin() const { return RegionBegin; }
	/// end - Return an iterator to the bottom of the current scheduling re gion.		/// end - Return an iterator to the bottom of the current scheduling re gion.
	MachineBasicBlock::iterator end() const { return RegionEnd; }		MachineBasicBlock::iterator end() const { return RegionEnd; }
	skipping to change at line 188		skipping to change at line 192
	/// startBlock - Prepare to perform scheduling in the given block.		/// startBlock - Prepare to perform scheduling in the given block.
	virtual void startBlock(MachineBasicBlock *BB);		virtual void startBlock(MachineBasicBlock *BB);
	/// finishBlock - Clean up after scheduling in the given block.		/// finishBlock - Clean up after scheduling in the given block.
	virtual void finishBlock();		virtual void finishBlock();
	/// Initialize the scheduler state for the next scheduling region.		/// Initialize the scheduler state for the next scheduling region.
	virtual void enterRegion(MachineBasicBlock *bb,		virtual void enterRegion(MachineBasicBlock *bb,
	MachineBasicBlock::iterator begin,		MachineBasicBlock::iterator begin,
	MachineBasicBlock::iterator end,		MachineBasicBlock::iterator end,
	unsigned endcount);		unsigned regioninstrs);
	/// Notify that the scheduler has finished scheduling the current regio n.		/// Notify that the scheduler has finished scheduling the current regio n.
	virtual void exitRegion();		virtual void exitRegion();
	/// buildSchedGraph - Build SUnits from the MachineBasicBlock that we a re		/// buildSchedGraph - Build SUnits from the MachineBasicBlock that we a re
	/// input.		/// input.
	void buildSchedGraph(AliasAnalysis *AA, RegPressureTracker *RPTracker =		void buildSchedGraph(AliasAnalysis *AA, RegPressureTracker *RPTracker =
	0);		0,
			PressureDiffs *PDiffs = 0);
	/// addSchedBarrierDeps - Add dependencies from instructions in the cur rent		/// addSchedBarrierDeps - Add dependencies from instructions in the cur rent
	/// list of instructions being scheduled to scheduling barrier. We want to		/// list of instructions being scheduled to scheduling barrier. We want to
	/// make sure instructions which define registers that are either used by		/// make sure instructions which define registers that are either used by
	/// the terminator or are live-out are properly scheduled. This is		/// the terminator or are live-out are properly scheduled. This is
	/// especially important when the definition latency of the return valu e(s)		/// especially important when the definition latency of the return valu e(s)
	/// are too high to be hidden by the branch or when the liveout registe rs		/// are too high to be hidden by the branch or when the liveout registe rs
	/// used by instructions in the fallthrough block.		/// used by instructions in the fallthrough block.
	void addSchedBarrierDeps();		void addSchedBarrierDeps();
End of changes. 10 change blocks.
	19 lines changed or deleted		25 lines changed or added

	SectionMemoryManager.h		SectionMemoryManager.h
	skipping to change at line 19		skipping to change at line 19
	//		//
	// This file contains the declaration of a section-based memory manager use d by		// This file contains the declaration of a section-based memory manager use d by
	// the MCJIT execution engine and RuntimeDyld.		// the MCJIT execution engine and RuntimeDyld.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_EXECUTIONENGINE_SECTIONMEMORYMANAGER_H		#ifndef LLVM_EXECUTIONENGINE_SECTIONMEMORYMANAGER_H
	#define LLVM_EXECUTIONENGINE_SECTIONMEMORYMANAGER_H		#define LLVM_EXECUTIONENGINE_SECTIONMEMORYMANAGER_H
	#include "llvm/ADT/SmallVector.h"		#include "llvm/ADT/SmallVector.h"
	#include "llvm/ExecutionEngine/JITMemoryManager.h"		#include "llvm/ExecutionEngine/RuntimeDyld.h"
	#include "llvm/Support/ErrorHandling.h"		#include "llvm/Support/ErrorHandling.h"
	#include "llvm/Support/Memory.h"		#include "llvm/Support/Memory.h"
	namespace llvm {		namespace llvm {
	/// This is a simple memory manager which implements the methods called by		/// This is a simple memory manager which implements the methods called by
	/// the RuntimeDyld class to allocate memory for section-based loading of		/// the RuntimeDyld class to allocate memory for section-based loading of
	/// objects, usually those generated by the MCJIT execution engine.		/// objects, usually those generated by the MCJIT execution engine.
	///		///
	/// This memory manager allocates all section memory as read-write. The		/// This memory manager allocates all section memory as read-write. The
	/// RuntimeDyld will copy JITed section memory into these allocated blocks		/// RuntimeDyld will copy JITed section memory into these allocated blocks
	/// and perform any necessary linking and relocations.		/// and perform any necessary linking and relocations.
	///		///
	/// Any client using this memory manager MUST ensure that section-specific		/// Any client using this memory manager MUST ensure that section-specific
	/// page permissions have been applied before attempting to execute functio ns		/// page permissions have been applied before attempting to execute functio ns
	/// in the JITed object. Permissions can be applied either by calling		/// in the JITed object. Permissions can be applied either by calling
	/// MCJIT::finalizeObject or by calling SectionMemoryManager::applyPermissi ons		/// MCJIT::finalizeObject or by calling SectionMemoryManager::finalizeMemor y
	/// directly. Clients of MCJIT should call MCJIT::finalizeObject.		/// directly. Clients of MCJIT should call MCJIT::finalizeObject.
	class SectionMemoryManager : public JITMemoryManager {		class SectionMemoryManager : public RTDyldMemoryManager {
	SectionMemoryManager(const SectionMemoryManager&) LLVM_DELETED_FUNCTION;		SectionMemoryManager(const SectionMemoryManager&) LLVM_DELETED_FUNCTION;
	void operator=(const SectionMemoryManager&) LLVM_DELETED_FUNCTION;		void operator=(const SectionMemoryManager&) LLVM_DELETED_FUNCTION;
	public:		public:
	SectionMemoryManager() { }		SectionMemoryManager() { }
	virtual ~SectionMemoryManager();		virtual ~SectionMemoryManager();
	/// \brief Allocates a memory block of (at least) the given size suitable for		/// \brief Allocates a memory block of (at least) the given size suitable for
	/// executable code.		/// executable code.
	///		///
	/// The value of \p Alignment must be a power of two. If \p Alignment is zero		/// The value of \p Alignment must be a power of two. If \p Alignment is zero
	/// a default alignment of 16 will be used.		/// a default alignment of 16 will be used.
	virtual uint8_t *allocateCodeSection(uintptr_t Size, unsigned Alignment,		virtual uint8_t *allocateCodeSection(uintptr_t Size, unsigned Alignment,
	unsigned SectionID);		unsigned SectionID,
			StringRef SectionName);
	/// \brief Allocates a memory block of (at least) the given size suitable for		/// \brief Allocates a memory block of (at least) the given size suitable for
	/// executable code.		/// executable code.
	///		///
	/// The value of \p Alignment must be a power of two. If \p Alignment is zero		/// The value of \p Alignment must be a power of two. If \p Alignment is zero
	/// a default alignment of 16 will be used.		/// a default alignment of 16 will be used.
	virtual uint8_t *allocateDataSection(uintptr_t Size, unsigned Alignment,		virtual uint8_t *allocateDataSection(uintptr_t Size, unsigned Alignment,
	unsigned SectionID,		unsigned SectionID,
			StringRef SectionName,
	bool isReadOnly);		bool isReadOnly);
	/// \brief Applies section-specific memory permissions.		/// \brief Update section-specific memory permissions and other attribute s.
	///		///
	/// This method is called when object loading is complete and section pag e		/// This method is called when object loading is complete and section pag e
	/// permissions can be applied. It is up to the memory manager implement ation		/// permissions can be applied. It is up to the memory manager implement ation
	/// to decide whether or not to act on this method. The memory manager w ill		/// to decide whether or not to act on this method. The memory manager w ill
	/// typically allocate all sections as read-write and then apply specific		/// typically allocate all sections as read-write and then apply specific
	/// permissions when this method is called. Code sections cannot be exec uted		/// permissions when this method is called. Code sections cannot be exec uted
	/// until this function has been called.		/// until this function has been called. In addition, any cache coherenc
			y
			/// operations needed to reliably use the memory are also performed.
	///		///
	/// \returns true if an error occurred, false otherwise.		/// \returns true if an error occurred, false otherwise.
	virtual bool applyPermissions(std::string *ErrMsg = 0);		virtual bool finalizeMemory(std::string *ErrMsg = 0);
	void registerEHFrames(StringRef SectionData);
	/// This method returns the address of the specified function. As such it
	is
	/// only useful for resolving library symbols, not code generated symbols
	.
	///
	/// If \p AbortOnFailure is false and no function with the given name is
	/// found, this function returns a null pointer. Otherwise, it prints a
	/// message to stderr and aborts.
	virtual void *getPointerToNamedFunction(const std::string &Name,
	bool AbortOnFailure = true);
	/// \brief Invalidate instruction cache for code sections.		/// \brief Invalidate instruction cache for code sections.
	///		///
	/// Some platforms with separate data cache and instruction cache require		/// Some platforms with separate data cache and instruction cache require
	/// explicit cache flush, otherwise JIT code manipulations (like resolved		/// explicit cache flush, otherwise JIT code manipulations (like resolved
	/// relocations) will get to the data cache but not to the instruction ca che.		/// relocations) will get to the data cache but not to the instruction ca che.
	///		///
	/// This method is called from applyPermissions.		/// This method is called from finalizeMemory.
	virtual void invalidateInstructionCache();		virtual void invalidateInstructionCache();
	private:		private:
	struct MemoryGroup {		struct MemoryGroup {
	SmallVector<sys::MemoryBlock, 16> AllocatedMem;		SmallVector<sys::MemoryBlock, 16> AllocatedMem;
	SmallVector<sys::MemoryBlock, 16> FreeMem;		SmallVector<sys::MemoryBlock, 16> FreeMem;
	sys::MemoryBlock Near;		sys::MemoryBlock Near;
	};		};
	uint8_t *allocateSection(MemoryGroup &MemGroup, uintptr_t Size,		uint8_t *allocateSection(MemoryGroup &MemGroup, uintptr_t Size,
	unsigned Alignment);		unsigned Alignment);
	error_code applyMemoryGroupPermissions(MemoryGroup &MemGroup,		error_code applyMemoryGroupPermissions(MemoryGroup &MemGroup,
	unsigned Permissions);		unsigned Permissions);
	MemoryGroup CodeMem;		MemoryGroup CodeMem;
	MemoryGroup RWDataMem;		MemoryGroup RWDataMem;
	MemoryGroup RODataMem;		MemoryGroup RODataMem;
	public:
	///
	/// Functions below are not used by MCJIT or RuntimeDyld, but must be
	/// implemented because they are declared as pure virtuals in the base cl
	ass.
	///
	virtual void setMemoryWritable() {
	llvm_unreachable("Unexpected call!");
	}
	virtual void setMemoryExecutable() {
	llvm_unreachable("Unexpected call!");
	}
	virtual void setPoisonMemory(bool poison) {
	llvm_unreachable("Unexpected call!");
	}
	virtual void AllocateGOT() {
	llvm_unreachable("Unexpected call!");
	}
	virtual uint8_t *getGOTBase() const {
	llvm_unreachable("Unexpected call!");
	return 0;
	}
	virtual uint8_t *startFunctionBody(const Function *F,
	uintptr_t &ActualSize){
	llvm_unreachable("Unexpected call!");
	return 0;
	}
	virtual uint8_t *allocateStub(const GlobalValue *F, unsigned StubSize,
	unsigned Alignment) {
	llvm_unreachable("Unexpected call!");
	return 0;
	}
	virtual void endFunctionBody(const Function *F, uint8_t *FunctionStart,
	uint8_t *FunctionEnd) {
	llvm_unreachable("Unexpected call!");
	}
	virtual uint8_t *allocateSpace(intptr_t Size, unsigned Alignment) {
	llvm_unreachable("Unexpected call!");
	return 0;
	}
	virtual uint8_t *allocateGlobal(uintptr_t Size, unsigned Alignment) {
	llvm_unreachable("Unexpected call!");
	return 0;
	}
	virtual void deallocateFunctionBody(void *Body) {
	llvm_unreachable("Unexpected call!");
	}
	virtual uint8_t *startExceptionTable(const Function *F,
	uintptr_t &ActualSize) {
	llvm_unreachable("Unexpected call!");
	return 0;
	}
	virtual void endExceptionTable(const Function *F, uint8_t *TableStart,
	uint8_t *TableEnd, uint8_t *FrameRegister)
	{
	llvm_unreachable("Unexpected call!");
	}
	virtual void deallocateExceptionTable(void *ET) {
	llvm_unreachable("Unexpected call!");
	}
	};		};
	}		}
	#endif // LLVM_EXECUTION_ENGINE_SECTION_MEMORY_MANAGER_H		#endif // LLVM_EXECUTION_ENGINE_SECTION_MEMORY_MANAGER_H
End of changes. 10 change blocks.
	83 lines changed or deleted		12 lines changed or added

	SelectionDAG.h		SelectionDAG.h
	skipping to change at line 36		skipping to change at line 36
	#include <map>		#include <map>
	#include <string>		#include <string>
	#include <vector>		#include <vector>
	namespace llvm {		namespace llvm {
	class AliasAnalysis;		class AliasAnalysis;
	class MachineConstantPoolValue;		class MachineConstantPoolValue;
	class MachineFunction;		class MachineFunction;
	class MDNode;		class MDNode;
	class SDNodeOrdering;
	class SDDbgValue;		class SDDbgValue;
	class TargetLowering;		class TargetLowering;
	class TargetSelectionDAGInfo;		class TargetSelectionDAGInfo;
	class TargetTransformInfo;		class TargetTransformInfo;
			class SDVTListNode : public FoldingSetNode {
			friend struct FoldingSetTrait<SDVTListNode>;
			/// FastID - A reference to an Interned FoldingSetNodeID for this node.
			/// The Allocator in SelectionDAG holds the data.
			/// SDVTList contains all types which are frequently accessed in Selectio
			nDAG.
			/// The size of this list is not expected big so it won't introduce memor
			y penalty.
			FoldingSetNodeIDRef FastID;
			const EVT *VTs;
			unsigned int NumVTs;
			/// The hash value for SDVTList is fixed so cache it to avoid hash calcul
			ation
			unsigned HashValue;
			public:
			SDVTListNode(const FoldingSetNodeIDRef ID, const EVT *VT, unsigned int Nu
			m) :
			FastID(ID), VTs(VT), NumVTs(Num) {
			HashValue = ID.ComputeHash();
			}
			SDVTList getSDVTList() {
			SDVTList result = {VTs, NumVTs};
			return result;
			}
			};
			// Specialize FoldingSetTrait for SDVTListNode
			// To avoid computing temp FoldingSetNodeID and hash value.
			template<> struct FoldingSetTrait<SDVTListNode> : DefaultFoldingSetTrait<SD
			VTListNode> {
			static void Profile(const SDVTListNode &X, FoldingSetNodeID& ID) {
			ID = X.FastID;
			}
			static bool Equals(const SDVTListNode &X, const FoldingSetNodeID &ID,
			unsigned IDHash, FoldingSetNodeID &TempID) {
			if (X.HashValue != IDHash)
			return false;
			return ID == X.FastID;
			}
			static unsigned ComputeHash(const SDVTListNode &X, FoldingSetNodeID &Temp
			ID) {
			return X.HashValue;
			}
			};
	template<> struct ilist_traits<SDNode> : public ilist_default_traits<SDNode > {		template<> struct ilist_traits<SDNode> : public ilist_default_traits<SDNode > {
	private:		private:
	mutable ilist_half_node<SDNode> Sentinel;		mutable ilist_half_node<SDNode> Sentinel;
	public:		public:
	SDNode *createSentinel() const {		SDNode *createSentinel() const {
	return static_cast<SDNode*>(&Sentinel);		return static_cast<SDNode*>(&Sentinel);
	}		}
	static void destroySentinel(SDNode *) {}		static void destroySentinel(SDNode *) {}
	SDNode *provideInitialHead() const { return createSentinel(); }		SDNode *provideInitialHead() const { return createSentinel(); }
	skipping to change at line 76		skipping to change at line 114
	/// DbgValMap.		/// DbgValMap.
	/// Byval parameters are handled separately because they don't use alloca's ,		/// Byval parameters are handled separately because they don't use alloca's ,
	/// which busts the normal mechanism. There is good reason for handling al l		/// which busts the normal mechanism. There is good reason for handling al l
	/// parameters separately: they may not have code generated for them, they		/// parameters separately: they may not have code generated for them, they
	/// should always go at the beginning of the function regardless of other c ode		/// should always go at the beginning of the function regardless of other c ode
	/// motion, and debug info for them is potentially useful even if the param eter		/// motion, and debug info for them is potentially useful even if the param eter
	/// is unused. Right now only byval parameters are handled separately.		/// is unused. Right now only byval parameters are handled separately.
	class SDDbgInfo {		class SDDbgInfo {
	SmallVector<SDDbgValue*, 32> DbgValues;		SmallVector<SDDbgValue*, 32> DbgValues;
	SmallVector<SDDbgValue*, 32> ByvalParmDbgValues;		SmallVector<SDDbgValue*, 32> ByvalParmDbgValues;
	DenseMap<const SDNode*, SmallVector<SDDbgValue*, 2> > DbgValMap;		typedef DenseMap<const SDNode*, SmallVector<SDDbgValue*, 2> > DbgValMapTy
			pe;
			DbgValMapType DbgValMap;
	void operator=(const SDDbgInfo&) LLVM_DELETED_FUNCTION;		void operator=(const SDDbgInfo&) LLVM_DELETED_FUNCTION;
	SDDbgInfo(const SDDbgInfo&) LLVM_DELETED_FUNCTION;		SDDbgInfo(const SDDbgInfo&) LLVM_DELETED_FUNCTION;
	public:		public:
	SDDbgInfo() {}		SDDbgInfo() {}
	void add(SDDbgValue *V, const SDNode *Node, bool isParameter) {		void add(SDDbgValue *V, const SDNode *Node, bool isParameter) {
	if (isParameter) {		if (isParameter) {
	ByvalParmDbgValues.push_back(V);		ByvalParmDbgValues.push_back(V);
	} else DbgValues.push_back(V);		} else DbgValues.push_back(V);
	skipping to change at line 102		skipping to change at line 141
	DbgValMap.clear();		DbgValMap.clear();
	DbgValues.clear();		DbgValues.clear();
	ByvalParmDbgValues.clear();		ByvalParmDbgValues.clear();
	}		}
	bool empty() const {		bool empty() const {
	return DbgValues.empty() && ByvalParmDbgValues.empty();		return DbgValues.empty() && ByvalParmDbgValues.empty();
	}		}
	ArrayRef<SDDbgValue*> getSDDbgValues(const SDNode *Node) {		ArrayRef<SDDbgValue*> getSDDbgValues(const SDNode *Node) {
	DenseMap<const SDNode*, SmallVector<SDDbgValue*, 2> >::iterator I =		DbgValMapType::iterator I = DbgValMap.find(Node);
	DbgValMap.find(Node);
	if (I != DbgValMap.end())		if (I != DbgValMap.end())
	return I->second;		return I->second;
	return ArrayRef<SDDbgValue*>();		return ArrayRef<SDDbgValue*>();
	}		}
	typedef SmallVector<SDDbgValue*,32>::iterator DbgIterator;		typedef SmallVectorImpl<SDDbgValue*>::iterator DbgIterator;
	DbgIterator DbgBegin() { return DbgValues.begin(); }		DbgIterator DbgBegin() { return DbgValues.begin(); }
	DbgIterator DbgEnd() { return DbgValues.end(); }		DbgIterator DbgEnd() { return DbgValues.end(); }
	DbgIterator ByvalParmDbgBegin() { return ByvalParmDbgValues.begin(); }		DbgIterator ByvalParmDbgBegin() { return ByvalParmDbgValues.begin(); }
	DbgIterator ByvalParmDbgEnd() { return ByvalParmDbgValues.end(); }		DbgIterator ByvalParmDbgEnd() { return ByvalParmDbgValues.end(); }
	};		};
	class SelectionDAG;		class SelectionDAG;
	void checkForCycles(const SDNode *N);		void checkForCycles(const SDNode *N);
	void checkForCycles(const SelectionDAG *DAG);		void checkForCycles(const SelectionDAG *DAG);
	skipping to change at line 133		skipping to change at line 171
	/// selection in order to allow implementation of machine specific optimiza tions		/// selection in order to allow implementation of machine specific optimiza tions
	/// and code simplifications.		/// and code simplifications.
	///		///
	/// The representation used by the SelectionDAG is a target-independent		/// The representation used by the SelectionDAG is a target-independent
	/// representation, which has some similarities to the GCC RTL representati on,		/// representation, which has some similarities to the GCC RTL representati on,
	/// but is significantly more simple, powerful, and is a graph form instead of a		/// but is significantly more simple, powerful, and is a graph form instead of a
	/// linear form.		/// linear form.
	///		///
	class SelectionDAG {		class SelectionDAG {
	const TargetMachine &TM;		const TargetMachine &TM;
	const TargetLowering &TLI;
	const TargetSelectionDAGInfo &TSI;		const TargetSelectionDAGInfo &TSI;
	const TargetTransformInfo *TTI;		const TargetTransformInfo *TTI;
			const TargetLowering *TLI;
	MachineFunction *MF;		MachineFunction *MF;
	LLVMContext *Context;		LLVMContext *Context;
	CodeGenOpt::Level OptLevel;		CodeGenOpt::Level OptLevel;
	/// EntryNode - The starting token.		/// EntryNode - The starting token.
	SDNode EntryNode;		SDNode EntryNode;
	/// Root - The root of the entire DAG.		/// Root - The root of the entire DAG.
	SDValue Root;		SDValue Root;
	skipping to change at line 169		skipping to change at line 207
	/// CSE with existing nodes when a duplicate is requested.		/// CSE with existing nodes when a duplicate is requested.
	FoldingSet<SDNode> CSEMap;		FoldingSet<SDNode> CSEMap;
	/// OperandAllocator - Pool allocation for machine-opcode SDNode operands .		/// OperandAllocator - Pool allocation for machine-opcode SDNode operands .
	BumpPtrAllocator OperandAllocator;		BumpPtrAllocator OperandAllocator;
	/// Allocator - Pool allocation for misc. objects that are created once p er		/// Allocator - Pool allocation for misc. objects that are created once p er
	/// SelectionDAG.		/// SelectionDAG.
	BumpPtrAllocator Allocator;		BumpPtrAllocator Allocator;
	/// SDNodeOrdering - The ordering of the SDNodes. It roughly corresponds
	to
	/// the ordering of the original LLVM instructions.
	SDNodeOrdering *Ordering;
	/// DbgInfo - Tracks dbg_value information through SDISel.		/// DbgInfo - Tracks dbg_value information through SDISel.
	SDDbgInfo *DbgInfo;		SDDbgInfo *DbgInfo;
	public:		public:
	/// DAGUpdateListener - Clients of various APIs that cause global effects on		/// DAGUpdateListener - Clients of various APIs that cause global effects on
	/// the DAG can optionally implement this interface. This allows the cli ents		/// the DAG can optionally implement this interface. This allows the cli ents
	/// to handle the various sorts of updates that happen.		/// to handle the various sorts of updates that happen.
	///		///
	/// A DAGUpdateListener automatically registers itself with DAG when it i s		/// A DAGUpdateListener automatically registers itself with DAG when it i s
	/// constructed, and removes itself when destroyed in RAII fashion.		/// constructed, and removes itself when destroyed in RAII fashion.
	skipping to change at line 206		skipping to change at line 240
	}		}
	/// NodeDeleted - The node N that was deleted and, if E is not null, an		/// NodeDeleted - The node N that was deleted and, if E is not null, an
	/// equivalent node E that replaced it.		/// equivalent node E that replaced it.
	virtual void NodeDeleted(SDNode *N, SDNode *E);		virtual void NodeDeleted(SDNode *N, SDNode *E);
	/// NodeUpdated - The node N that was updated.		/// NodeUpdated - The node N that was updated.
	virtual void NodeUpdated(SDNode *N);		virtual void NodeUpdated(SDNode *N);
	};		};
			/// NewNodesMustHaveLegalTypes - When true, additional steps are taken to
			/// ensure that getConstant() and similar functions return DAG nodes that
			/// have legal types. This is important after type legalization since
			/// any illegally typed nodes generated after this point will not experie
			nce
			/// type legalization.
			bool NewNodesMustHaveLegalTypes;
	private:		private:
	/// DAGUpdateListener is a friend so it can manipulate the listener stack .		/// DAGUpdateListener is a friend so it can manipulate the listener stack .
	friend struct DAGUpdateListener;		friend struct DAGUpdateListener;
	/// UpdateListeners - Linked list of registered DAGUpdateListener instanc es.		/// UpdateListeners - Linked list of registered DAGUpdateListener instanc es.
	/// This stack is maintained by DAGUpdateListener RAII.		/// This stack is maintained by DAGUpdateListener RAII.
	DAGUpdateListener *UpdateListeners;		DAGUpdateListener *UpdateListeners;
	/// setGraphColorHelper - Implementation of setSubgraphColor.		/// setGraphColorHelper - Implementation of setSubgraphColor.
	/// Return whether we had to truncate the search.		/// Return whether we had to truncate the search.
	skipping to change at line 231		skipping to change at line 272
	void operator=(const SelectionDAG&) LLVM_DELETED_FUNCTION;		void operator=(const SelectionDAG&) LLVM_DELETED_FUNCTION;
	SelectionDAG(const SelectionDAG&) LLVM_DELETED_FUNCTION;		SelectionDAG(const SelectionDAG&) LLVM_DELETED_FUNCTION;
	public:		public:
	explicit SelectionDAG(const TargetMachine &TM, llvm::CodeGenOpt::Level);		explicit SelectionDAG(const TargetMachine &TM, llvm::CodeGenOpt::Level);
	~SelectionDAG();		~SelectionDAG();
	/// init - Prepare this SelectionDAG to process code in the given		/// init - Prepare this SelectionDAG to process code in the given
	/// MachineFunction.		/// MachineFunction.
	///		///
	void init(MachineFunction &mf, const TargetTransformInfo *TTI);		void init(MachineFunction &mf, const TargetTransformInfo *TTI,
			const TargetLowering *TLI);
	/// clear - Clear state and free memory necessary to make this		/// clear - Clear state and free memory necessary to make this
	/// SelectionDAG ready to process a new block.		/// SelectionDAG ready to process a new block.
	///		///
	void clear();		void clear();
	MachineFunction &getMachineFunction() const { return *MF; }		MachineFunction &getMachineFunction() const { return *MF; }
	const TargetMachine &getTarget() const { return TM; }		const TargetMachine &getTarget() const { return TM; }
	const TargetLowering &getTargetLoweringInfo() const { return TLI; }		const TargetLowering &getTargetLoweringInfo() const { return *TLI; }
	const TargetSelectionDAGInfo &getSelectionDAGInfo() const { return TSI; }		const TargetSelectionDAGInfo &getSelectionDAGInfo() const { return TSI; }
	const TargetTransformInfo *getTargetTransformInfo() const { return TTI; }		const TargetTransformInfo *getTargetTransformInfo() const { return TTI; }
	LLVMContext *getContext() const {return Context; }		LLVMContext *getContext() const {return Context; }
	/// viewGraph - Pop up a GraphViz/gv window with the DAG rendered using ' dot'.		/// viewGraph - Pop up a GraphViz/gv window with the DAG rendered using ' dot'.
	///		///
	void viewGraph(const std::string &Title);		void viewGraph(const std::string &Title);
	void viewGraph();		void viewGraph();
	#ifndef NDEBUG		#ifndef NDEBUG
	skipping to change at line 389		skipping to change at line 431
	SDValue getConstantFP(const ConstantFP &CF, EVT VT, bool isTarget = false );		SDValue getConstantFP(const ConstantFP &CF, EVT VT, bool isTarget = false );
	SDValue getTargetConstantFP(double Val, EVT VT) {		SDValue getTargetConstantFP(double Val, EVT VT) {
	return getConstantFP(Val, VT, true);		return getConstantFP(Val, VT, true);
	}		}
	SDValue getTargetConstantFP(const APFloat& Val, EVT VT) {		SDValue getTargetConstantFP(const APFloat& Val, EVT VT) {
	return getConstantFP(Val, VT, true);		return getConstantFP(Val, VT, true);
	}		}
	SDValue getTargetConstantFP(const ConstantFP &Val, EVT VT) {		SDValue getTargetConstantFP(const ConstantFP &Val, EVT VT) {
	return getConstantFP(Val, VT, true);		return getConstantFP(Val, VT, true);
	}		}
	SDValue getGlobalAddress(const GlobalValue *GV, DebugLoc DL, EVT VT,		SDValue getGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT,
	int64_t offset = 0, bool isTargetGA = false,		int64_t offset = 0, bool isTargetGA = false,
	unsigned char TargetFlags = 0);		unsigned char TargetFlags = 0);
	SDValue getTargetGlobalAddress(const GlobalValue *GV, DebugLoc DL, EVT VT ,		SDValue getTargetGlobalAddress(const GlobalValue *GV, SDLoc DL, EVT VT,
	int64_t offset = 0,		int64_t offset = 0,
	unsigned char TargetFlags = 0) {		unsigned char TargetFlags = 0) {
	return getGlobalAddress(GV, DL, VT, offset, true, TargetFlags);		return getGlobalAddress(GV, DL, VT, offset, true, TargetFlags);
	}		}
	SDValue getFrameIndex(int FI, EVT VT, bool isTarget = false);		SDValue getFrameIndex(int FI, EVT VT, bool isTarget = false);
	SDValue getTargetFrameIndex(int FI, EVT VT) {		SDValue getTargetFrameIndex(int FI, EVT VT) {
	return getFrameIndex(FI, VT, true);		return getFrameIndex(FI, VT, true);
	}		}
	SDValue getJumpTable(int JTI, EVT VT, bool isTarget = false,		SDValue getJumpTable(int JTI, EVT VT, bool isTarget = false,
	unsigned char TargetFlags = 0);		unsigned char TargetFlags = 0);
	skipping to change at line 427		skipping to change at line 469
	SDValue getTargetConstantPool(MachineConstantPoolValue *C,		SDValue getTargetConstantPool(MachineConstantPoolValue *C,
	EVT VT, unsigned Align = 0,		EVT VT, unsigned Align = 0,
	int Offset = 0, unsigned char TargetFlags =0) {		int Offset = 0, unsigned char TargetFlags =0) {
	return getConstantPool(C, VT, Align, Offset, true, TargetFlags);		return getConstantPool(C, VT, Align, Offset, true, TargetFlags);
	}		}
	SDValue getTargetIndex(int Index, EVT VT, int64_t Offset = 0,		SDValue getTargetIndex(int Index, EVT VT, int64_t Offset = 0,
	unsigned char TargetFlags = 0);		unsigned char TargetFlags = 0);
	// When generating a branch to a BB, we don't in general know enough		// When generating a branch to a BB, we don't in general know enough
	// to provide debug info for the BB at that time, so keep this one around .		// to provide debug info for the BB at that time, so keep this one around .
	SDValue getBasicBlock(MachineBasicBlock *MBB);		SDValue getBasicBlock(MachineBasicBlock *MBB);
	SDValue getBasicBlock(MachineBasicBlock *MBB, DebugLoc dl);		SDValue getBasicBlock(MachineBasicBlock *MBB, SDLoc dl);
	SDValue getExternalSymbol(const char *Sym, EVT VT);		SDValue getExternalSymbol(const char *Sym, EVT VT);
	SDValue getExternalSymbol(const char *Sym, DebugLoc dl, EVT VT);		SDValue getExternalSymbol(const char *Sym, SDLoc dl, EVT VT);
	SDValue getTargetExternalSymbol(const char *Sym, EVT VT,		SDValue getTargetExternalSymbol(const char *Sym, EVT VT,
	unsigned char TargetFlags = 0);		unsigned char TargetFlags = 0);
	SDValue getValueType(EVT);		SDValue getValueType(EVT);
	SDValue getRegister(unsigned Reg, EVT VT);		SDValue getRegister(unsigned Reg, EVT VT);
	SDValue getRegisterMask(const uint32_t *RegMask);		SDValue getRegisterMask(const uint32_t *RegMask);
	SDValue getEHLabel(DebugLoc dl, SDValue Root, MCSymbol *Label);		SDValue getEHLabel(SDLoc dl, SDValue Root, MCSymbol *Label);
	SDValue getBlockAddress(const BlockAddress *BA, EVT VT,		SDValue getBlockAddress(const BlockAddress *BA, EVT VT,
	int64_t Offset = 0, bool isTarget = false,		int64_t Offset = 0, bool isTarget = false,
	unsigned char TargetFlags = 0);		unsigned char TargetFlags = 0);
	SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT,		SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT,
	int64_t Offset = 0,		int64_t Offset = 0,
	unsigned char TargetFlags = 0) {		unsigned char TargetFlags = 0) {
	return getBlockAddress(BA, VT, Offset, true, TargetFlags);		return getBlockAddress(BA, VT, Offset, true, TargetFlags);
	}		}
	SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N) {		SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N) {
	return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,		return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
	getRegister(Reg, N.getValueType()), N);		getRegister(Reg, N.getValueType()), N);
	}		}
	// This version of the getCopyToReg method takes an extra operand, which		// This version of the getCopyToReg method takes an extra operand, which
	// indicates that there is potentially an incoming glue value (if Glue is not		// indicates that there is potentially an incoming glue value (if Glue is not
	// null) and that there should be a glue result.		// null) and that there should be a glue result.
	SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N,		SDValue getCopyToReg(SDValue Chain, SDLoc dl, unsigned Reg, SDValue N,
	SDValue Glue) {		SDValue Glue) {
	SDVTList VTs = getVTList(MVT::Other, MVT::Glue);		SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
	SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Glue };		SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Glue };
	return getNode(ISD::CopyToReg, dl, VTs, Ops, Glue.getNode() ? 4 : 3);		return getNode(ISD::CopyToReg, dl, VTs, Ops, Glue.getNode() ? 4 : 3);
	}		}
	// Similar to last getCopyToReg() except parameter Reg is a SDValue		// Similar to last getCopyToReg() except parameter Reg is a SDValue
	SDValue getCopyToReg(SDValue Chain, DebugLoc dl, SDValue Reg, SDValue N,		SDValue getCopyToReg(SDValue Chain, SDLoc dl, SDValue Reg, SDValue N,
	SDValue Glue) {		SDValue Glue) {
	SDVTList VTs = getVTList(MVT::Other, MVT::Glue);		SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
	SDValue Ops[] = { Chain, Reg, N, Glue };		SDValue Ops[] = { Chain, Reg, N, Glue };
	return getNode(ISD::CopyToReg, dl, VTs, Ops, Glue.getNode() ? 4 : 3);		return getNode(ISD::CopyToReg, dl, VTs, Ops, Glue.getNode() ? 4 : 3);
	}		}
	SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, EVT VT) {		SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT) {
	SDVTList VTs = getVTList(VT, MVT::Other);		SDVTList VTs = getVTList(VT, MVT::Other);
	SDValue Ops[] = { Chain, getRegister(Reg, VT) };		SDValue Ops[] = { Chain, getRegister(Reg, VT) };
	return getNode(ISD::CopyFromReg, dl, VTs, Ops, 2);		return getNode(ISD::CopyFromReg, dl, VTs, Ops, 2);
	}		}
	// This version of the getCopyFromReg method takes an extra operand, whic h		// This version of the getCopyFromReg method takes an extra operand, whic h
	// indicates that there is potentially an incoming glue value (if Glue is not		// indicates that there is potentially an incoming glue value (if Glue is not
	// null) and that there should be a glue result.		// null) and that there should be a glue result.
	SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, EVT VT,		SDValue getCopyFromReg(SDValue Chain, SDLoc dl, unsigned Reg, EVT VT,
	SDValue Glue) {		SDValue Glue) {
	SDVTList VTs = getVTList(VT, MVT::Other, MVT::Glue);		SDVTList VTs = getVTList(VT, MVT::Other, MVT::Glue);
	SDValue Ops[] = { Chain, getRegister(Reg, VT), Glue };		SDValue Ops[] = { Chain, getRegister(Reg, VT), Glue };
	return getNode(ISD::CopyFromReg, dl, VTs, Ops, Glue.getNode() ? 3 : 2);		return getNode(ISD::CopyFromReg, dl, VTs, Ops, Glue.getNode() ? 3 : 2);
	}		}
	SDValue getCondCode(ISD::CondCode Cond);		SDValue getCondCode(ISD::CondCode Cond);
	/// Returns the ConvertRndSat Note: Avoid using this node because it may		/// Returns the ConvertRndSat Note: Avoid using this node because it may
	/// disappear in the future and most targets don't support it.		/// disappear in the future and most targets don't support it.
	SDValue getConvertRndSat(EVT VT, DebugLoc dl, SDValue Val, SDValue DTy,		SDValue getConvertRndSat(EVT VT, SDLoc dl, SDValue Val, SDValue DTy,
	SDValue STy,		SDValue STy,
	SDValue Rnd, SDValue Sat, ISD::CvtCode Code);		SDValue Rnd, SDValue Sat, ISD::CvtCode Code);
	/// getVectorShuffle - Return an ISD::VECTOR_SHUFFLE node. The number of		/// getVectorShuffle - Return an ISD::VECTOR_SHUFFLE node. The number of
	/// elements in VT, which must be a vector type, must match the number of		/// elements in VT, which must be a vector type, must match the number of
	/// mask elements NumElts. A integer mask element equal to -1 is treated as		/// mask elements NumElts. A integer mask element equal to -1 is treated as
	/// undefined.		/// undefined.
	SDValue getVectorShuffle(EVT VT, DebugLoc dl, SDValue N1, SDValue N2,		SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2,
	const int *MaskElts);		const int *MaskElts);
	/// getAnyExtOrTrunc - Convert Op, which must be of integer type, to the		/// getAnyExtOrTrunc - Convert Op, which must be of integer type, to the
	/// integer type VT, by either any-extending or truncating it.		/// integer type VT, by either any-extending or truncating it.
	SDValue getAnyExtOrTrunc(SDValue Op, DebugLoc DL, EVT VT);		SDValue getAnyExtOrTrunc(SDValue Op, SDLoc DL, EVT VT);
	/// getSExtOrTrunc - Convert Op, which must be of integer type, to the		/// getSExtOrTrunc - Convert Op, which must be of integer type, to the
	/// integer type VT, by either sign-extending or truncating it.		/// integer type VT, by either sign-extending or truncating it.
	SDValue getSExtOrTrunc(SDValue Op, DebugLoc DL, EVT VT);		SDValue getSExtOrTrunc(SDValue Op, SDLoc DL, EVT VT);
	/// getZExtOrTrunc - Convert Op, which must be of integer type, to the		/// getZExtOrTrunc - Convert Op, which must be of integer type, to the
	/// integer type VT, by either zero-extending or truncating it.		/// integer type VT, by either zero-extending or truncating it.
	SDValue getZExtOrTrunc(SDValue Op, DebugLoc DL, EVT VT);		SDValue getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT);
	/// getZeroExtendInReg - Return the expression required to zero extend th e Op		/// getZeroExtendInReg - Return the expression required to zero extend th e Op
	/// value assuming it was the smaller SrcTy value.		/// value assuming it was the smaller SrcTy value.
	SDValue getZeroExtendInReg(SDValue Op, DebugLoc DL, EVT SrcTy);		SDValue getZeroExtendInReg(SDValue Op, SDLoc DL, EVT SrcTy);
	/// getNOT - Create a bitwise NOT operation as (XOR Val, -1).		/// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
	SDValue getNOT(DebugLoc DL, SDValue Val, EVT VT);		SDValue getNOT(SDLoc DL, SDValue Val, EVT VT);
	/// getCALLSEQ_START - Return a new CALLSEQ_START node, which always must have		/// getCALLSEQ_START - Return a new CALLSEQ_START node, which always must have
	/// a glue result (to ensure it's not CSE'd). CALLSEQ_START does not hav e a		/// a glue result (to ensure it's not CSE'd). CALLSEQ_START does not hav e a
	/// useful DebugLoc.		/// useful SDLoc.
	SDValue getCALLSEQ_START(SDValue Chain, SDValue Op) {		SDValue getCALLSEQ_START(SDValue Chain, SDValue Op, SDLoc DL) {
	SDVTList VTs = getVTList(MVT::Other, MVT::Glue);		SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
	SDValue Ops[] = { Chain, Op };		SDValue Ops[] = { Chain, Op };
	return getNode(ISD::CALLSEQ_START, DebugLoc(), VTs, Ops, 2);		return getNode(ISD::CALLSEQ_START, DL, VTs, Ops, 2);
	}		}
	/// getCALLSEQ_END - Return a new CALLSEQ_END node, which always must hav e a		/// getCALLSEQ_END - Return a new CALLSEQ_END node, which always must hav e a
	/// glue result (to ensure it's not CSE'd). CALLSEQ_END does not have		/// glue result (to ensure it's not CSE'd). CALLSEQ_END does not have
	/// a useful DebugLoc.		/// a useful SDLoc.
	SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,		SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
	SDValue InGlue) {		SDValue InGlue, SDLoc DL) {
	SDVTList NodeTys = getVTList(MVT::Other, MVT::Glue);		SDVTList NodeTys = getVTList(MVT::Other, MVT::Glue);
	SmallVector<SDValue, 4> Ops;		SmallVector<SDValue, 4> Ops;
	Ops.push_back(Chain);		Ops.push_back(Chain);
	Ops.push_back(Op1);		Ops.push_back(Op1);
	Ops.push_back(Op2);		Ops.push_back(Op2);
	Ops.push_back(InGlue);		Ops.push_back(InGlue);
	return getNode(ISD::CALLSEQ_END, DebugLoc(), NodeTys, &Ops[0],		return getNode(ISD::CALLSEQ_END, DL, NodeTys, &Ops[0],
	(unsigned)Ops.size() - (InGlue.getNode() == 0 ? 1 : 0));		(unsigned)Ops.size() - (InGlue.getNode() == 0 ? 1 : 0));
	}		}
	/// getUNDEF - Return an UNDEF node. UNDEF does not have a useful DebugL oc.		/// getUNDEF - Return an UNDEF node. UNDEF does not have a useful SDLoc.
	SDValue getUNDEF(EVT VT) {		SDValue getUNDEF(EVT VT) {
	return getNode(ISD::UNDEF, DebugLoc(), VT);		return getNode(ISD::UNDEF, SDLoc(), VT);
	}		}
	/// getGLOBAL_OFFSET_TABLE - Return a GLOBAL_OFFSET_TABLE node. This doe s		/// getGLOBAL_OFFSET_TABLE - Return a GLOBAL_OFFSET_TABLE node. This doe s
	/// not have a useful DebugLoc.		/// not have a useful SDLoc.
	SDValue getGLOBAL_OFFSET_TABLE(EVT VT) {		SDValue getGLOBAL_OFFSET_TABLE(EVT VT) {
	return getNode(ISD::GLOBAL_OFFSET_TABLE, DebugLoc(), VT);		return getNode(ISD::GLOBAL_OFFSET_TABLE, SDLoc(), VT);
	}		}
	/// getNode - Gets or creates the specified node.		/// getNode - Gets or creates the specified node.
	///		///
	SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT);		SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT);
	SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT, SDValue N);		SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N);
	SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT, SDValue N1, SDValue		SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2
	N2);		);
	SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT,		SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT,
	SDValue N1, SDValue N2, SDValue N3);		SDValue N1, SDValue N2, SDValue N3);
	SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT,		SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT,
	SDValue N1, SDValue N2, SDValue N3, SDValue N4);		SDValue N1, SDValue N2, SDValue N3, SDValue N4);
	SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT,		SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT,
	SDValue N1, SDValue N2, SDValue N3, SDValue N4,		SDValue N1, SDValue N2, SDValue N3, SDValue N4,
	SDValue N5);		SDValue N5);
	SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT,		SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT,
	const SDUse *Ops, unsigned NumOps);		const SDUse *Ops, unsigned NumOps);
	SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT,		SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT,
	const SDValue *Ops, unsigned NumOps);		const SDValue *Ops, unsigned NumOps);
	SDValue getNode(unsigned Opcode, DebugLoc DL,		SDValue getNode(unsigned Opcode, SDLoc DL,
	ArrayRef<EVT> ResultTys,		ArrayRef<EVT> ResultTys,
	const SDValue *Ops, unsigned NumOps);		const SDValue *Ops, unsigned NumOps);
	SDValue getNode(unsigned Opcode, DebugLoc DL, const EVT *VTs, unsigned Nu mVTs,		SDValue getNode(unsigned Opcode, SDLoc DL, const EVT *VTs, unsigned NumVT s,
	const SDValue *Ops, unsigned NumOps);		const SDValue *Ops, unsigned NumOps);
	SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs,		SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs,
	const SDValue *Ops, unsigned NumOps);		const SDValue *Ops, unsigned NumOps);
	SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs);		SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs);
	SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, SDValue N);		SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs, SDValue N);
	SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs,		SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs,
	SDValue N1, SDValue N2);		SDValue N1, SDValue N2);
	SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs,		SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs,
	SDValue N1, SDValue N2, SDValue N3);		SDValue N1, SDValue N2, SDValue N3);
	SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs,		SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs,
	SDValue N1, SDValue N2, SDValue N3, SDValue N4);		SDValue N1, SDValue N2, SDValue N3, SDValue N4);
	SDValue getNode(unsigned Opcode, DebugLoc DL, SDVTList VTs,		SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs,
	SDValue N1, SDValue N2, SDValue N3, SDValue N4,		SDValue N1, SDValue N2, SDValue N3, SDValue N4,
	SDValue N5);		SDValue N5);
	/// getStackArgumentTokenFactor - Compute a TokenFactor to force all		/// getStackArgumentTokenFactor - Compute a TokenFactor to force all
	/// the incoming stack arguments to be loaded from the stack. This is		/// the incoming stack arguments to be loaded from the stack. This is
	/// used in tail call lowering to protect stack arguments from being		/// used in tail call lowering to protect stack arguments from being
	/// clobbered.		/// clobbered.
	SDValue getStackArgumentTokenFactor(SDValue Chain);		SDValue getStackArgumentTokenFactor(SDValue Chain);
	SDValue getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src,		SDValue getMemcpy(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src,
	SDValue Size, unsigned Align, bool isVol, bool AlwaysIn line,		SDValue Size, unsigned Align, bool isVol, bool AlwaysIn line,
	MachinePointerInfo DstPtrInfo,		MachinePointerInfo DstPtrInfo,
	MachinePointerInfo SrcPtrInfo);		MachinePointerInfo SrcPtrInfo);
	SDValue getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src,		SDValue getMemmove(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src,
	SDValue Size, unsigned Align, bool isVol,		SDValue Size, unsigned Align, bool isVol,
	MachinePointerInfo DstPtrInfo,		MachinePointerInfo DstPtrInfo,
	MachinePointerInfo SrcPtrInfo);		MachinePointerInfo SrcPtrInfo);
	SDValue getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, SDValue Src,		SDValue getMemset(SDValue Chain, SDLoc dl, SDValue Dst, SDValue Src,
	SDValue Size, unsigned Align, bool isVol,		SDValue Size, unsigned Align, bool isVol,
	MachinePointerInfo DstPtrInfo);		MachinePointerInfo DstPtrInfo);
	/// getSetCC - Helper function to make it easier to build SetCC's if you just		/// getSetCC - Helper function to make it easier to build SetCC's if you just
	/// have an ISD::CondCode instead of an SDValue.		/// have an ISD::CondCode instead of an SDValue.
	///		///
	SDValue getSetCC(DebugLoc DL, EVT VT, SDValue LHS, SDValue RHS,		SDValue getSetCC(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS,
	ISD::CondCode Cond) {		ISD::CondCode Cond) {
	assert(LHS.getValueType().isVector() == RHS.getValueType().isVector() & &		assert(LHS.getValueType().isVector() == RHS.getValueType().isVector() & &
	"Cannot compare scalars to vectors");		"Cannot compare scalars to vectors");
	assert(LHS.getValueType().isVector() == VT.isVector() &&		assert(LHS.getValueType().isVector() == VT.isVector() &&
	"Cannot compare scalars to vectors");		"Cannot compare scalars to vectors");
			assert(Cond != ISD::SETCC_INVALID &&
			"Cannot create a setCC of an invalid node.");
	return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));		return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
	}		}
			// getSelect - Helper function to make it easier to build Select's if you
			just
			// have operands and don't want to check for vector.
			SDValue getSelect(SDLoc DL, EVT VT, SDValue Cond,
			SDValue LHS, SDValue RHS) {
			assert(LHS.getValueType() == RHS.getValueType() &&
			"Cannot use select on differing types");
			assert(VT.isVector() == LHS.getValueType().isVector() &&
			"Cannot mix vectors and scalars");
			return getNode(Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SEL
			ECT, DL, VT,
			Cond, LHS, RHS);
			}
	/// getSelectCC - Helper function to make it easier to build SelectCC's i f you		/// getSelectCC - Helper function to make it easier to build SelectCC's i f you
	/// just have an ISD::CondCode instead of an SDValue.		/// just have an ISD::CondCode instead of an SDValue.
	///		///
	SDValue getSelectCC(DebugLoc DL, SDValue LHS, SDValue RHS,		SDValue getSelectCC(SDLoc DL, SDValue LHS, SDValue RHS,
	SDValue True, SDValue False, ISD::CondCode Cond) {		SDValue True, SDValue False, ISD::CondCode Cond) {
	return getNode(ISD::SELECT_CC, DL, True.getValueType(),		return getNode(ISD::SELECT_CC, DL, True.getValueType(),
	LHS, RHS, True, False, getCondCode(Cond));		LHS, RHS, True, False, getCondCode(Cond));
	}		}
	/// getVAArg - VAArg produces a result and token chain, and takes a point er		/// getVAArg - VAArg produces a result and token chain, and takes a point er
	/// and a source value as input.		/// and a source value as input.
	SDValue getVAArg(EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,		SDValue getVAArg(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr,
	SDValue SV, unsigned Align);		SDValue SV, unsigned Align);
	/// getAtomic - Gets a node for an atomic op, produces result and chain a nd		/// getAtomic - Gets a node for an atomic op, produces result and chain a nd
	/// takes 3 operands		/// takes 3 operands
	SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,		SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDValue Chain,
	SDValue Ptr, SDValue Cmp, SDValue Swp,		SDValue Ptr, SDValue Cmp, SDValue Swp,
	MachinePointerInfo PtrInfo, unsigned Alignment,		MachinePointerInfo PtrInfo, unsigned Alignment,
	AtomicOrdering Ordering,		AtomicOrdering Ordering,
	SynchronizationScope SynchScope);		SynchronizationScope SynchScope);
	SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,		SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDValue Chain,
	SDValue Ptr, SDValue Cmp, SDValue Swp,		SDValue Ptr, SDValue Cmp, SDValue Swp,
	MachineMemOperand *MMO,		MachineMemOperand *MMO,
	AtomicOrdering Ordering,		AtomicOrdering Ordering,
	SynchronizationScope SynchScope);		SynchronizationScope SynchScope);
	/// getAtomic - Gets a node for an atomic op, produces result (if relevan t)		/// getAtomic - Gets a node for an atomic op, produces result (if relevan t)
	/// and chain and takes 2 operands.		/// and chain and takes 2 operands.
	SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,		SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDValue Chain,
	SDValue Ptr, SDValue Val, const Value* PtrVal,		SDValue Ptr, SDValue Val, const Value* PtrVal,
	unsigned Alignment, AtomicOrdering Ordering,		unsigned Alignment, AtomicOrdering Ordering,
	SynchronizationScope SynchScope);		SynchronizationScope SynchScope);
	SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain,		SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDValue Chain,
	SDValue Ptr, SDValue Val, MachineMemOperand *MMO,		SDValue Ptr, SDValue Val, MachineMemOperand *MMO,
	AtomicOrdering Ordering,		AtomicOrdering Ordering,
	SynchronizationScope SynchScope);		SynchronizationScope SynchScope);
	/// getAtomic - Gets a node for an atomic op, produces result and chain a nd		/// getAtomic - Gets a node for an atomic op, produces result and chain a nd
	/// takes 1 operand.		/// takes 1 operand.
	SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, EVT VT,		SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, EVT VT,
	SDValue Chain, SDValue Ptr, const Value* PtrVal,		SDValue Chain, SDValue Ptr, const Value* PtrVal,
	unsigned Alignment,		unsigned Alignment,
	AtomicOrdering Ordering,		AtomicOrdering Ordering,
	SynchronizationScope SynchScope);		SynchronizationScope SynchScope);
	SDValue getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, EVT VT,		SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, EVT VT,
	SDValue Chain, SDValue Ptr, MachineMemOperand *MMO,		SDValue Chain, SDValue Ptr, MachineMemOperand *MMO,
	AtomicOrdering Ordering,		AtomicOrdering Ordering,
	SynchronizationScope SynchScope);		SynchronizationScope SynchScope);
			/// getAtomic - Gets a node for an atomic op, produces result and chain a
			nd
			/// takes N operands.
			SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDVTList VTList,
			SDValue* Ops, unsigned NumOps, MachineMemOperand *MMO,
			AtomicOrdering Ordering,
			SynchronizationScope SynchScope);
	/// getMemIntrinsicNode - Creates a MemIntrinsicNode that may produce a		/// getMemIntrinsicNode - Creates a MemIntrinsicNode that may produce a
	/// result and takes a list of operands. Opcode may be INTRINSIC_VOID,		/// result and takes a list of operands. Opcode may be INTRINSIC_VOID,
	/// INTRINSIC_W_CHAIN, or a target-specific opcode with a value not		/// INTRINSIC_W_CHAIN, or a target-specific opcode with a value not
	/// less than FIRST_TARGET_MEMORY_OPCODE.		/// less than FIRST_TARGET_MEMORY_OPCODE.
	SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,		SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl,
	const EVT *VTs, unsigned NumVTs,		const EVT *VTs, unsigned NumVTs,
	const SDValue *Ops, unsigned NumOps,		const SDValue *Ops, unsigned NumOps,
	EVT MemVT, MachinePointerInfo PtrInfo,		EVT MemVT, MachinePointerInfo PtrInfo,
	unsigned Align = 0, bool Vol = false,		unsigned Align = 0, bool Vol = false,
	bool ReadMem = true, bool WriteMem = true);		bool ReadMem = true, bool WriteMem = true);
	SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList ,		SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList,
	const SDValue *Ops, unsigned NumOps,		const SDValue *Ops, unsigned NumOps,
	EVT MemVT, MachinePointerInfo PtrInfo,		EVT MemVT, MachinePointerInfo PtrInfo,
	unsigned Align = 0, bool Vol = false,		unsigned Align = 0, bool Vol = false,
	bool ReadMem = true, bool WriteMem = true);		bool ReadMem = true, bool WriteMem = true);
	SDValue getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList ,		SDValue getMemIntrinsicNode(unsigned Opcode, SDLoc dl, SDVTList VTList,
	const SDValue *Ops, unsigned NumOps,		const SDValue *Ops, unsigned NumOps,
	EVT MemVT, MachineMemOperand *MMO);		EVT MemVT, MachineMemOperand *MMO);
	/// getMergeValues - Create a MERGE_VALUES node from the given operands.		/// getMergeValues - Create a MERGE_VALUES node from the given operands.
	SDValue getMergeValues(const SDValue *Ops, unsigned NumOps, DebugLoc dl);		SDValue getMergeValues(const SDValue *Ops, unsigned NumOps, SDLoc dl);
	/// getLoad - Loads are not normal binary operators: their result type is not		/// getLoad - Loads are not normal binary operators: their result type is not
	/// determined by their operands, and they produce a value AND a token ch ain.		/// determined by their operands, and they produce a value AND a token ch ain.
	///		///
	SDValue getLoad(EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr,		SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr,
	MachinePointerInfo PtrInfo, bool isVolatile,		MachinePointerInfo PtrInfo, bool isVolatile,
	bool isNonTemporal, bool isInvariant, unsigned Alignment,		bool isNonTemporal, bool isInvariant, unsigned Alignment,
	const MDNode *TBAAInfo = 0, const MDNode *Ranges = 0);		const MDNode *TBAAInfo = 0, const MDNode *Ranges = 0);
	SDValue getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT,		SDValue getLoad(EVT VT, SDLoc dl, SDValue Chain, SDValue Ptr,
			MachineMemOperand *MMO);
			SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT,
	SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo ,		SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo ,
	EVT MemVT, bool isVolatile,		EVT MemVT, bool isVolatile,
	bool isNonTemporal, unsigned Alignment,		bool isNonTemporal, unsigned Alignment,
	const MDNode *TBAAInfo = 0);		const MDNode *TBAAInfo = 0);
	SDValue getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base,		SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT,
			SDValue Chain, SDValue Ptr, EVT MemVT,
			MachineMemOperand *MMO);
			SDValue getIndexedLoad(SDValue OrigLoad, SDLoc dl, SDValue Base,
	SDValue Offset, ISD::MemIndexedMode AM);		SDValue Offset, ISD::MemIndexedMode AM);
	SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,		SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
	EVT VT, DebugLoc dl,		EVT VT, SDLoc dl,
	SDValue Chain, SDValue Ptr, SDValue Offset,		SDValue Chain, SDValue Ptr, SDValue Offset,
	MachinePointerInfo PtrInfo, EVT MemVT,		MachinePointerInfo PtrInfo, EVT MemVT,
	bool isVolatile, bool isNonTemporal, bool isInvariant,		bool isVolatile, bool isNonTemporal, bool isInvariant,
	unsigned Alignment, const MDNode *TBAAInfo = 0,		unsigned Alignment, const MDNode *TBAAInfo = 0,
	const MDNode *Ranges = 0);		const MDNode *Ranges = 0);
	SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,		SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
	EVT VT, DebugLoc dl,		EVT VT, SDLoc dl,
	SDValue Chain, SDValue Ptr, SDValue Offset,		SDValue Chain, SDValue Ptr, SDValue Offset,
	EVT MemVT, MachineMemOperand *MMO);		EVT MemVT, MachineMemOperand *MMO);
	/// getStore - Helper function to build ISD::STORE nodes.		/// getStore - Helper function to build ISD::STORE nodes.
	///		///
	SDValue getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,		SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr,
	MachinePointerInfo PtrInfo, bool isVolatile,		MachinePointerInfo PtrInfo, bool isVolatile,
	bool isNonTemporal, unsigned Alignment,		bool isNonTemporal, unsigned Alignment,
	const MDNode *TBAAInfo = 0);		const MDNode *TBAAInfo = 0);
	SDValue getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr,		SDValue getStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr,
	MachineMemOperand *MMO);		MachineMemOperand *MMO);
	SDValue getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Pt r,		SDValue getTruncStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr,
	MachinePointerInfo PtrInfo, EVT TVT,		MachinePointerInfo PtrInfo, EVT TVT,
	bool isNonTemporal, bool isVolatile,		bool isNonTemporal, bool isVolatile,
	unsigned Alignment,		unsigned Alignment,
	const MDNode *TBAAInfo = 0);		const MDNode *TBAAInfo = 0);
	SDValue getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Pt r,		SDValue getTruncStore(SDValue Chain, SDLoc dl, SDValue Val, SDValue Ptr,
	EVT TVT, MachineMemOperand *MMO);		EVT TVT, MachineMemOperand *MMO);
	SDValue getIndexedStore(SDValue OrigStoe, DebugLoc dl, SDValue Base,		SDValue getIndexedStore(SDValue OrigStoe, SDLoc dl, SDValue Base,
	SDValue Offset, ISD::MemIndexedMode AM);		SDValue Offset, ISD::MemIndexedMode AM);
	/// getSrcValue - Construct a node to track a Value* through the backend.		/// getSrcValue - Construct a node to track a Value* through the backend.
	SDValue getSrcValue(const Value *v);		SDValue getSrcValue(const Value *v);
	/// getMDNode - Return an MDNodeSDNode which holds an MDNode.		/// getMDNode - Return an MDNodeSDNode which holds an MDNode.
	SDValue getMDNode(const MDNode *MD);		SDValue getMDNode(const MDNode *MD);
			/// getAddrSpaceCast - Return an AddrSpaceCastSDNode.
			SDValue getAddrSpaceCast(SDLoc dl, EVT VT, SDValue Ptr,
			unsigned SrcAS, unsigned DestAS);
	/// getShiftAmountOperand - Return the specified value casted to		/// getShiftAmountOperand - Return the specified value casted to
	/// the target's desired shift amount type.		/// the target's desired shift amount type.
	SDValue getShiftAmountOperand(EVT LHSTy, SDValue Op);		SDValue getShiftAmountOperand(EVT LHSTy, SDValue Op);
	/// UpdateNodeOperands - *Mutate* the specified node in-place to have the		/// UpdateNodeOperands - *Mutate* the specified node in-place to have the
	/// specified operands. If the resultant node already exists in the DAG,		/// specified operands. If the resultant node already exists in the DAG,
	/// this does not modify the specified node, instead it returns the node that		/// this does not modify the specified node, instead it returns the node that
	/// already exists. If the resultant node does not exist in the DAG, the		/// already exists. If the resultant node does not exist in the DAG, the
	/// input node is returned. As a degenerate case, if you specify the sam e		/// input node is returned. As a degenerate case, if you specify the sam e
	/// input operands as the node already has, the input node is returned.		/// input operands as the node already has, the input node is returned.
	skipping to change at line 807		skipping to change at line 879
	/// return type, opcode, and operands.		/// return type, opcode, and operands.
	SDNode *MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs,		SDNode *MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs,
	const SDValue *Ops, unsigned NumOps);		const SDValue *Ops, unsigned NumOps);
	/// getMachineNode - These are used for target selectors to create a new node		/// getMachineNode - These are used for target selectors to create a new node
	/// with specified return type(s), MachineInstr opcode, and operands.		/// with specified return type(s), MachineInstr opcode, and operands.
	///		///
	/// Note that getMachineNode returns the resultant node. If there is alr eady		/// Note that getMachineNode returns the resultant node. If there is alr eady
	/// a node of the specified opcode and operands, it returns that node ins tead		/// a node of the specified opcode and operands, it returns that node ins tead
	/// of the current one.		/// of the current one.
	MachineSDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT);		MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT);
	MachineSDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT,		MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT,
	SDValue Op1);		SDValue Op1);
	MachineSDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT,		MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT,
	SDValue Op1, SDValue Op2);		SDValue Op1, SDValue Op2);
	MachineSDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT,		MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT,
	SDValue Op1, SDValue Op2, SDValue Op3);		SDValue Op1, SDValue Op2, SDValue Op3);
	MachineSDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT,		MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT,
	ArrayRef<SDValue> Ops);		ArrayRef<SDValue> Ops);
	MachineSDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT		MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2
	VT2);		);
	MachineSDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT		MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2
	VT2,		,
	SDValue Op1);		SDValue Op1);
	MachineSDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2,		MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2 ,
	SDValue Op1, SDValue Op2);		SDValue Op1, SDValue Op2);
	MachineSDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2,		MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2 ,
	SDValue Op1, SDValue Op2, SDValue Op3);		SDValue Op1, SDValue Op2, SDValue Op3);
	MachineSDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2,		MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2 ,
	ArrayRef<SDValue> Ops);		ArrayRef<SDValue> Ops);
	MachineSDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2,		MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2 ,
	EVT VT3, SDValue Op1, SDValue Op2);		EVT VT3, SDValue Op1, SDValue Op2);
	MachineSDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2,		MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2 ,
	EVT VT3, SDValue Op1, SDValue Op2,		EVT VT3, SDValue Op1, SDValue Op2,
	SDValue Op3);		SDValue Op3);
	MachineSDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2,		MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2 ,
	EVT VT3, ArrayRef<SDValue> Ops);		EVT VT3, ArrayRef<SDValue> Ops);
	MachineSDNode *getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2,		MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2 ,
	EVT VT3, EVT VT4, ArrayRef<SDValue> Ops);		EVT VT3, EVT VT4, ArrayRef<SDValue> Ops);
	MachineSDNode *getMachineNode(unsigned Opcode, DebugLoc dl,		MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl,
	ArrayRef<EVT> ResultTys,		ArrayRef<EVT> ResultTys,
	ArrayRef<SDValue> Ops);		ArrayRef<SDValue> Ops);
	MachineSDNode *getMachineNode(unsigned Opcode, DebugLoc dl, SDVTList VTs,		MachineSDNode *getMachineNode(unsigned Opcode, SDLoc dl, SDVTList VTs,
	ArrayRef<SDValue> Ops);		ArrayRef<SDValue> Ops);
	/// getTargetExtractSubreg - A convenience function for creating		/// getTargetExtractSubreg - A convenience function for creating
	/// TargetInstrInfo::EXTRACT_SUBREG nodes.		/// TargetInstrInfo::EXTRACT_SUBREG nodes.
	SDValue getTargetExtractSubreg(int SRIdx, DebugLoc DL, EVT VT,		SDValue getTargetExtractSubreg(int SRIdx, SDLoc DL, EVT VT,
	SDValue Operand);		SDValue Operand);
	/// getTargetInsertSubreg - A convenience function for creating		/// getTargetInsertSubreg - A convenience function for creating
	/// TargetInstrInfo::INSERT_SUBREG nodes.		/// TargetInstrInfo::INSERT_SUBREG nodes.
	SDValue getTargetInsertSubreg(int SRIdx, DebugLoc DL, EVT VT,		SDValue getTargetInsertSubreg(int SRIdx, SDLoc DL, EVT VT,
	SDValue Operand, SDValue Subreg);		SDValue Operand, SDValue Subreg);
	/// getNodeIfExists - Get the specified node if it's already available, o r		/// getNodeIfExists - Get the specified node if it's already available, o r
	/// else return NULL.		/// else return NULL.
	SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTs,		SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTs,
	const SDValue *Ops, unsigned NumOps);		const SDValue *Ops, unsigned NumOps);
	/// getDbgValue - Creates a SDDbgValue node.		/// getDbgValue - Creates a SDDbgValue node.
	///		///
	SDDbgValue *getDbgValue(MDNode *MDPtr, SDNode *N, unsigned R, uint64_t Of f,		SDDbgValue *getDbgValue(MDNode *MDPtr, SDNode *N, unsigned R, uint64_t Of f,
	skipping to change at line 953		skipping to change at line 1025
	default: llvm_unreachable("Unknown FP format");		default: llvm_unreachable("Unknown FP format");
	case MVT::f16: return APFloat::IEEEhalf;		case MVT::f16: return APFloat::IEEEhalf;
	case MVT::f32: return APFloat::IEEEsingle;		case MVT::f32: return APFloat::IEEEsingle;
	case MVT::f64: return APFloat::IEEEdouble;		case MVT::f64: return APFloat::IEEEdouble;
	case MVT::f80: return APFloat::x87DoubleExtended;		case MVT::f80: return APFloat::x87DoubleExtended;
	case MVT::f128: return APFloat::IEEEquad;		case MVT::f128: return APFloat::IEEEquad;
	case MVT::ppcf128: return APFloat::PPCDoubleDouble;		case MVT::ppcf128: return APFloat::PPCDoubleDouble;
	}		}
	}		}
	/// AssignOrdering - Assign an order to the SDNode.
	void AssignOrdering(const SDNode *SD, unsigned Order);
	/// GetOrdering - Get the order for the SDNode.
	unsigned GetOrdering(const SDNode *SD) const;
	/// AddDbgValue - Add a dbg_value SDNode. If SD is non-null that means th e		/// AddDbgValue - Add a dbg_value SDNode. If SD is non-null that means th e
	/// value is produced by SD.		/// value is produced by SD.
	void AddDbgValue(SDDbgValue *DB, SDNode *SD, bool isParameter);		void AddDbgValue(SDDbgValue *DB, SDNode *SD, bool isParameter);
	/// GetDbgValues - Get the debug values which reference the given SDNode.		/// GetDbgValues - Get the debug values which reference the given SDNode.
	ArrayRef<SDDbgValue*> GetDbgValues(const SDNode* SD) {		ArrayRef<SDDbgValue*> GetDbgValues(const SDNode* SD) {
	return DbgInfo->getSDDbgValues(SD);		return DbgInfo->getSDDbgValues(SD);
	}		}
	/// TransferDbgValues - Transfer SDDbgValues.		/// TransferDbgValues - Transfer SDDbgValues.
	skipping to change at line 1001		skipping to change at line 1067
	/// CreateStackTemporary - Create a stack temporary suitable for holding		/// CreateStackTemporary - Create a stack temporary suitable for holding
	/// either of the specified value types.		/// either of the specified value types.
	SDValue CreateStackTemporary(EVT VT1, EVT VT2);		SDValue CreateStackTemporary(EVT VT1, EVT VT2);
	/// FoldConstantArithmetic -		/// FoldConstantArithmetic -
	SDValue FoldConstantArithmetic(unsigned Opcode, EVT VT,		SDValue FoldConstantArithmetic(unsigned Opcode, EVT VT,
	SDNode *Cst1, SDNode *Cst2);		SDNode *Cst1, SDNode *Cst2);
	/// FoldSetCC - Constant fold a setcc to true or false.		/// FoldSetCC - Constant fold a setcc to true or false.
	SDValue FoldSetCC(EVT VT, SDValue N1,		SDValue FoldSetCC(EVT VT, SDValue N1,
	SDValue N2, ISD::CondCode Cond, DebugLoc dl);		SDValue N2, ISD::CondCode Cond, SDLoc dl);
	/// SignBitIsZero - Return true if the sign bit of Op is known to be zero . We		/// SignBitIsZero - Return true if the sign bit of Op is known to be zero . We
	/// use this predicate to simplify operations downstream.		/// use this predicate to simplify operations downstream.
	bool SignBitIsZero(SDValue Op, unsigned Depth = 0) const;		bool SignBitIsZero(SDValue Op, unsigned Depth = 0) const;
	/// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We		/// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We
	/// use this predicate to simplify operations downstream. Op and Mask ar e		/// use this predicate to simplify operations downstream. Op and Mask ar e
	/// known to be the same type.		/// known to be the same type.
	bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth = 0)		bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth = 0)
	const;		const;
	skipping to change at line 1067		skipping to change at line 1133
	/// isConsecutiveLoad - Return true if LD is loading 'Bytes' bytes from a		/// isConsecutiveLoad - Return true if LD is loading 'Bytes' bytes from a
	/// location that is 'Dist' units away from the location that the 'Base' load		/// location that is 'Dist' units away from the location that the 'Base' load
	/// is loading from.		/// is loading from.
	bool isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base,		bool isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base,
	unsigned Bytes, int Dist) const;		unsigned Bytes, int Dist) const;
	/// InferPtrAlignment - Infer alignment of a load / store address. Return 0 if		/// InferPtrAlignment - Infer alignment of a load / store address. Return 0 if
	/// it cannot be inferred.		/// it cannot be inferred.
	unsigned InferPtrAlignment(SDValue Ptr) const;		unsigned InferPtrAlignment(SDValue Ptr) const;
			/// GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a ty
			pe
			/// which is split (or expanded) into two not necessarily identical piece
			s.
			std::pair<EVT, EVT> GetSplitDestVTs(const EVT &VT) const;
			/// SplitVector - Split the vector with EXTRACT_SUBVECTOR using the provi
			des
			/// VTs and return the low/high part.
			std::pair<SDValue, SDValue> SplitVector(const SDValue &N, const SDLoc &DL
			,
			const EVT &LoVT, const EVT &HiVT)
			;
			/// SplitVector - Split the vector with EXTRACT_SUBVECTOR and return the
			/// low/high part.
			std::pair<SDValue, SDValue> SplitVector(const SDValue &N, const SDLoc &DL
			) {
			EVT LoVT, HiVT;
			llvm::tie(LoVT, HiVT) = GetSplitDestVTs(N.getValueType());
			return SplitVector(N, DL, LoVT, HiVT);
			}
			/// SplitVectorOperand - Split the node's operand with EXTRACT_SUBVECTOR
			and
			/// return the low/high part.
			std::pair<SDValue, SDValue> SplitVectorOperand(const SDNode *N, unsigned
			OpNo)
			{
			return SplitVector(N->getOperand(OpNo), SDLoc(N));
			}
	private:		private:
	bool RemoveNodeFromCSEMaps(SDNode *N);		bool RemoveNodeFromCSEMaps(SDNode *N);
	void AddModifiedNodeToCSEMaps(SDNode *N);		void AddModifiedNodeToCSEMaps(SDNode *N);
	SDNode *FindModifiedNodeSlot(SDNode *N, SDValue Op, void *&InsertPos);		SDNode *FindModifiedNodeSlot(SDNode *N, SDValue Op, void *&InsertPos);
	SDNode *FindModifiedNodeSlot(SDNode *N, SDValue Op1, SDValue Op2,		SDNode *FindModifiedNodeSlot(SDNode *N, SDValue Op1, SDValue Op2,
	void *&InsertPos);		void *&InsertPos);
	SDNode *FindModifiedNodeSlot(SDNode *N, const SDValue *Ops, unsigned NumO ps,		SDNode *FindModifiedNodeSlot(SDNode *N, const SDValue *Ops, unsigned NumO ps,
	void *&InsertPos);		void *&InsertPos);
	SDNode *UpdadeDebugLocOnMergedSDNode(SDNode *N, DebugLoc loc);		SDNode *UpdadeSDLocOnMergedSDNode(SDNode *N, SDLoc loc);
	void DeleteNodeNotInCSEMaps(SDNode *N);		void DeleteNodeNotInCSEMaps(SDNode *N);
	void DeallocateNode(SDNode *N);		void DeallocateNode(SDNode *N);
	unsigned getEVTAlignment(EVT MemoryVT) const;		unsigned getEVTAlignment(EVT MemoryVT) const;
	void allnodes_clear();		void allnodes_clear();
	/// VTList - List of non-single value types.		/// VTList - List of non-single value types.
	std::vector<SDVTList> VTList;		FoldingSet<SDVTListNode> VTListMap;
	/// CondCodeNodes - Maps to auto-CSE operations.		/// CondCodeNodes - Maps to auto-CSE operations.
	std::vector<CondCodeSDNode*> CondCodeNodes;		std::vector<CondCodeSDNode*> CondCodeNodes;
	std::vector<SDNode*> ValueTypeNodes;		std::vector<SDNode*> ValueTypeNodes;
	std::map<EVT, SDNode*, EVT::compareRawBits> ExtendedValueTypeNodes;		std::map<EVT, SDNode*, EVT::compareRawBits> ExtendedValueTypeNodes;
	StringMap<SDNode*> ExternalSymbols;		StringMap<SDNode*> ExternalSymbols;
	std::map<std::pair<std::string, unsigned char>,SDNode*> TargetExternalSym bols;		std::map<std::pair<std::string, unsigned char>,SDNode*> TargetExternalSym bols;
	};		};
End of changes. 100 change blocks.
	113 lines changed or deleted		221 lines changed or added

	SelectionDAGISel.h		SelectionDAGISel.h
	skipping to change at line 33		skipping to change at line 33
	namespace llvm {		namespace llvm {
	class FastISel;		class FastISel;
	class SelectionDAGBuilder;		class SelectionDAGBuilder;
	class SDValue;		class SDValue;
	class MachineRegisterInfo;		class MachineRegisterInfo;
	class MachineBasicBlock;		class MachineBasicBlock;
	class MachineFunction;		class MachineFunction;
	class MachineInstr;		class MachineInstr;
	class TargetLowering;		class TargetLowering;
	class TargetLibraryInfo;		class TargetLibraryInfo;
	class TargetInstrInfo;
	class TargetTransformInfo;		class TargetTransformInfo;
	class FunctionLoweringInfo;		class FunctionLoweringInfo;
	class ScheduleHazardRecognizer;		class ScheduleHazardRecognizer;
	class GCFunctionInfo;		class GCFunctionInfo;
	class ScheduleDAGSDNodes;		class ScheduleDAGSDNodes;
	class LoadInst;		class LoadInst;
	/// SelectionDAGISel - This is the common base class used for SelectionDAG- based		/// SelectionDAGISel - This is the common base class used for SelectionDAG- based
	/// pattern-matching instruction selectors.		/// pattern-matching instruction selectors.
	class SelectionDAGISel : public MachineFunctionPass {		class SelectionDAGISel : public MachineFunctionPass {
	public:		public:
	const TargetMachine &TM;		TargetMachine &TM;
	const TargetLowering &TLI;
	const TargetLibraryInfo *LibInfo;		const TargetLibraryInfo *LibInfo;
	const TargetTransformInfo *TTI;		const TargetTransformInfo *TTI;
	FunctionLoweringInfo *FuncInfo;		FunctionLoweringInfo *FuncInfo;
	MachineFunction *MF;		MachineFunction *MF;
	MachineRegisterInfo *RegInfo;		MachineRegisterInfo *RegInfo;
	SelectionDAG *CurDAG;		SelectionDAG *CurDAG;
	SelectionDAGBuilder *SDB;		SelectionDAGBuilder *SDB;
	AliasAnalysis *AA;		AliasAnalysis *AA;
	GCFunctionInfo *GFI;		GCFunctionInfo *GFI;
	CodeGenOpt::Level OptLevel;		CodeGenOpt::Level OptLevel;
	static char ID;		static char ID;
	explicit SelectionDAGISel(const TargetMachine &tm,		explicit SelectionDAGISel(TargetMachine &tm,
	CodeGenOpt::Level OL = CodeGenOpt::Default);		CodeGenOpt::Level OL = CodeGenOpt::Default);
	virtual ~SelectionDAGISel();		virtual ~SelectionDAGISel();
	const TargetLowering &getTargetLowering() { return TLI; }		const TargetLowering *getTargetLowering() const {
			return TM.getTargetLowering();
			}
	virtual void getAnalysisUsage(AnalysisUsage &AU) const;		virtual void getAnalysisUsage(AnalysisUsage &AU) const;
	virtual bool runOnMachineFunction(MachineFunction &MF);		virtual bool runOnMachineFunction(MachineFunction &MF);
	virtual void EmitFunctionEntryCode() {}		virtual void EmitFunctionEntryCode() {}
	/// PreprocessISelDAG - This hook allows targets to hack on the graph bef ore		/// PreprocessISelDAG - This hook allows targets to hack on the graph bef ore
	/// instruction selection starts.		/// instruction selection starts.
	virtual void PreprocessISelDAG() {}		virtual void PreprocessISelDAG() {}
	skipping to change at line 116		skipping to change at line 116
	enum BuiltinOpcodes {		enum BuiltinOpcodes {
	OPC_Scope,		OPC_Scope,
	OPC_RecordNode,		OPC_RecordNode,
	OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,		OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,
	OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,		OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,
	OPC_RecordMemRef,		OPC_RecordMemRef,
	OPC_CaptureGlueInput,		OPC_CaptureGlueInput,
	OPC_MoveChild,		OPC_MoveChild,
	OPC_MoveParent,		OPC_MoveParent,
	OPC_CheckSame,		OPC_CheckSame,
			OPC_CheckChild0Same, OPC_CheckChild1Same,
			OPC_CheckChild2Same, OPC_CheckChild3Same,
	OPC_CheckPatternPredicate,		OPC_CheckPatternPredicate,
	OPC_CheckPredicate,		OPC_CheckPredicate,
	OPC_CheckOpcode,		OPC_CheckOpcode,
	OPC_SwitchOpcode,		OPC_SwitchOpcode,
	OPC_CheckType,		OPC_CheckType,
	OPC_SwitchType,		OPC_SwitchType,
	OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,		OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,
	OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,		OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,
	OPC_CheckChild6Type, OPC_CheckChild7Type,		OPC_CheckChild6Type, OPC_CheckChild7Type,
	OPC_CheckInteger,		OPC_CheckInteger,
End of changes. 5 change blocks.
	5 lines changed or deleted		7 lines changed or added

	SelectionDAGNodes.h		SelectionDAGNodes.h
	skipping to change at line 344		skipping to change at line 344
	/// UseList - List of uses for this SDNode.		/// UseList - List of uses for this SDNode.
	SDUse *UseList;		SDUse *UseList;
	/// NumOperands/NumValues - The number of entries in the Operand/Value li st.		/// NumOperands/NumValues - The number of entries in the Operand/Value li st.
	unsigned short NumOperands, NumValues;		unsigned short NumOperands, NumValues;
	/// debugLoc - source line information.		/// debugLoc - source line information.
	DebugLoc debugLoc;		DebugLoc debugLoc;
			// The ordering of the SDNodes. It roughly corresponds to the ordering of
			the
			// original LLVM instructions.
			// This is used for turning off scheduling, because we'll forgo
			// the normal scheduling algorithms and output the instructions according
			to
			// this ordering.
			unsigned IROrder;
	/// getValueTypeList - Return a pointer to the specified value type.		/// getValueTypeList - Return a pointer to the specified value type.
	static const EVT *getValueTypeList(EVT VT);		static const EVT *getValueTypeList(EVT VT);
	friend class SelectionDAG;		friend class SelectionDAG;
	friend struct ilist_traits<SDNode>;		friend struct ilist_traits<SDNode>;
	public:		public:
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	// Accessors		// Accessors
	//		//
	skipping to change at line 412		skipping to change at line 419
	///		///
	size_t use_size() const { return std::distance(use_begin(), use_end()); }		size_t use_size() const { return std::distance(use_begin(), use_end()); }
	/// getNodeId - Return the unique node id.		/// getNodeId - Return the unique node id.
	///		///
	int getNodeId() const { return NodeId; }		int getNodeId() const { return NodeId; }
	/// setNodeId - Set unique node id.		/// setNodeId - Set unique node id.
	void setNodeId(int Id) { NodeId = Id; }		void setNodeId(int Id) { NodeId = Id; }
			/// getIROrder - Return the node ordering.
			///
			unsigned getIROrder() const { return IROrder; }
			/// setIROrder - Set the node ordering.
			///
			void setIROrder(unsigned Order) { IROrder = Order; }
	/// getDebugLoc - Return the source location info.		/// getDebugLoc - Return the source location info.
	const DebugLoc getDebugLoc() const { return debugLoc; }		const DebugLoc getDebugLoc() const { return debugLoc; }
	/// setDebugLoc - Set source location info. Try to avoid this, putting		/// setDebugLoc - Set source location info. Try to avoid this, putting
	/// it in the constructor is preferable.		/// it in the constructor is preferable.
	void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }		void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
	/// use_iterator - This class provides iterator support for SDUse		/// use_iterator - This class provides iterator support for SDUse
	/// operands that use a specific SDNode.		/// operands that use a specific SDNode.
	class use_iterator		class use_iterator
	skipping to change at line 504		skipping to change at line 519
	///		///
	bool isOnlyUserOf(SDNode *N) const;		bool isOnlyUserOf(SDNode *N) const;
	/// isOperandOf - Return true if this node is an operand of N.		/// isOperandOf - Return true if this node is an operand of N.
	///		///
	bool isOperandOf(SDNode *N) const;		bool isOperandOf(SDNode *N) const;
	/// isPredecessorOf - Return true if this node is a predecessor of N.		/// isPredecessorOf - Return true if this node is a predecessor of N.
	/// NOTE: Implemented on top of hasPredecessor and every bit as		/// NOTE: Implemented on top of hasPredecessor and every bit as
	/// expensive. Use carefully.		/// expensive. Use carefully.
	bool isPredecessorOf(const SDNode *N) const { return N->hasPredecessor(th		bool isPredecessorOf(const SDNode *N) const {
	is); }		return N->hasPredecessor(this);
			}
	/// hasPredecessor - Return true if N is a predecessor of this node.		/// hasPredecessor - Return true if N is a predecessor of this node.
	/// N is either an operand of this node, or can be reached by recursively		/// N is either an operand of this node, or can be reached by recursively
	/// traversing up the operands.		/// traversing up the operands.
	/// NOTE: This is an expensive method. Use it carefully.		/// NOTE: This is an expensive method. Use it carefully.
	bool hasPredecessor(const SDNode *N) const;		bool hasPredecessor(const SDNode *N) const;
	/// hasPredecesorHelper - Return true if N is a predecessor of this node.		/// hasPredecesorHelper - Return true if N is a predecessor of this node.
	/// N is either an operand of this node, or can be reached by recursively		/// N is either an operand of this node, or can be reached by recursively
	/// traversing up the operands.		/// traversing up the operands.
	/// In this helper the Visited and worklist sets are held externally to		/// In this helper the Visited and worklist sets are held externally to
	/// cache predecessors over multiple invocations. If you want to test for		/// cache predecessors over multiple invocations. If you want to test for
	/// multiple predecessors this method is preferable to multiple calls to		/// multiple predecessors this method is preferable to multiple calls to
	/// hasPredecessor. Be sure to clear Visited and Worklist if the DAG		/// hasPredecessor. Be sure to clear Visited and Worklist if the DAG
	/// changes.		/// changes.
	/// NOTE: This is still very expensive. Use carefully.		/// NOTE: This is still very expensive. Use carefully.
	bool hasPredecessorHelper(const SDNode *N,		bool hasPredecessorHelper(const SDNode *N,
	SmallPtrSet<const SDNode *, 32> &Visited,		SmallPtrSet<const SDNode *, 32> &Visited,
	SmallVector<const SDNode *, 16> &Worklist) cons t;		SmallVectorImpl<const SDNode *> &Worklist) cons t;
	/// getNumOperands - Return the number of values used by this operation.		/// getNumOperands - Return the number of values used by this operation.
	///		///
	unsigned getNumOperands() const { return NumOperands; }		unsigned getNumOperands() const { return NumOperands; }
	/// getConstantOperandVal - Helper method returns the integer value of a		/// getConstantOperandVal - Helper method returns the integer value of a
	/// ConstantSDNode operand.		/// ConstantSDNode operand.
	uint64_t getConstantOperandVal(unsigned Num) const;		uint64_t getConstantOperandVal(unsigned Num) const;
	const SDValue &getOperand(unsigned Num) const {		const SDValue &getOperand(unsigned Num) const {
	skipping to change at line 679		skipping to change at line 696
	/// addUse - This method should only be used by the SDUse class.		/// addUse - This method should only be used by the SDUse class.
	///		///
	void addUse(SDUse &U) { U.addToList(&UseList); }		void addUse(SDUse &U) { U.addToList(&UseList); }
	protected:		protected:
	static SDVTList getSDVTList(EVT VT) {		static SDVTList getSDVTList(EVT VT) {
	SDVTList Ret = { getValueTypeList(VT), 1 };		SDVTList Ret = { getValueTypeList(VT), 1 };
	return Ret;		return Ret;
	}		}
	SDNode(unsigned Opc, const DebugLoc dl, SDVTList VTs, const SDValue *Ops,		SDNode(unsigned Opc, unsigned Order, const DebugLoc dl, SDVTList VTs,
	unsigned NumOps)		const SDValue *Ops, unsigned NumOps)
	: NodeType(Opc), OperandsNeedDelete(true), HasDebugValue(false),		: NodeType(Opc), OperandsNeedDelete(true), HasDebugValue(false),
	SubclassData(0), NodeId(-1),		SubclassData(0), NodeId(-1),
	OperandList(NumOps ? new SDUse[NumOps] : 0),		OperandList(NumOps ? new SDUse[NumOps] : 0),
	ValueList(VTs.VTs), UseList(NULL),		ValueList(VTs.VTs), UseList(NULL),
	NumOperands(NumOps), NumValues(VTs.NumVTs),		NumOperands(NumOps), NumValues(VTs.NumVTs),
	debugLoc(dl) {		debugLoc(dl), IROrder(Order) {
	for (unsigned i = 0; i != NumOps; ++i) {		for (unsigned i = 0; i != NumOps; ++i) {
	OperandList[i].setUser(this);		OperandList[i].setUser(this);
	OperandList[i].setInitial(Ops[i]);		OperandList[i].setInitial(Ops[i]);
	}		}
	checkForCycles(this);		checkForCycles(this);
	}		}
	/// This constructor adds no operands itself; operands can be		/// This constructor adds no operands itself; operands can be
	/// set later with InitOperands.		/// set later with InitOperands.
	SDNode(unsigned Opc, const DebugLoc dl, SDVTList VTs)		SDNode(unsigned Opc, unsigned Order, const DebugLoc dl, SDVTList VTs)
	: NodeType(Opc), OperandsNeedDelete(false), HasDebugValue(false),		: NodeType(Opc), OperandsNeedDelete(false), HasDebugValue(false),
	SubclassData(0), NodeId(-1), OperandList(0), ValueList(VTs.VTs),		SubclassData(0), NodeId(-1), OperandList(0),
	UseList(NULL), NumOperands(0), NumValues(VTs.NumVTs),		ValueList(VTs.VTs), UseList(NULL), NumOperands(0), NumValues(VTs.NumV
	debugLoc(dl) {}		Ts),
			debugLoc(dl), IROrder(Order) {}
	/// InitOperands - Initialize the operands list of this with 1 operand.		/// InitOperands - Initialize the operands list of this with 1 operand.
	void InitOperands(SDUse *Ops, const SDValue &Op0) {		void InitOperands(SDUse *Ops, const SDValue &Op0) {
	Ops[0].setUser(this);		Ops[0].setUser(this);
	Ops[0].setInitial(Op0);		Ops[0].setInitial(Op0);
	NumOperands = 1;		NumOperands = 1;
	OperandList = Ops;		OperandList = Ops;
	checkForCycles(this);		checkForCycles(this);
	}		}
	skipping to change at line 768		skipping to change at line 785
	NumOperands = N;		NumOperands = N;
	OperandList = Ops;		OperandList = Ops;
	checkForCycles(this);		checkForCycles(this);
	}		}
	/// DropOperands - Release the operands and set this node to have		/// DropOperands - Release the operands and set this node to have
	/// zero operands.		/// zero operands.
	void DropOperands();		void DropOperands();
	};		};
			/// Wrapper class for IR location info (IR ordering and DebugLoc) to be pas
			sed
			/// into SDNode creation functions.
			/// When an SDNode is created from the DAGBuilder, the DebugLoc is extracte
			d
			/// from the original Instruction, and IROrder is the ordinal position of
			/// the instruction.
			/// When an SDNode is created after the DAG is being built, both DebugLoc a
			nd
			/// the IROrder are propagated from the original SDNode.
			/// So SDLoc class provides two constructors besides the default one, one t
			o
			/// be used by the DAGBuilder, the other to be used by others.
			class SDLoc {
			private:
			// Ptr could be used for either Instruction* or SDNode*. It is used for
			// Instruction* if IROrder is not -1.
			const void *Ptr;
			int IROrder;
			public:
			SDLoc() : Ptr(NULL), IROrder(0) {}
			SDLoc(const SDNode *N) : Ptr(N), IROrder(-1) {
			assert(N && "null SDNode");
			}
			SDLoc(const SDValue V) : Ptr(V.getNode()), IROrder(-1) {
			assert(Ptr && "null SDNode");
			}
			SDLoc(const Instruction *I, int Order) : Ptr(I), IROrder(Order) {
			assert(Order >= 0 && "bad IROrder");
			}
			unsigned getIROrder() {
			if (IROrder >= 0 || Ptr == NULL) {
			return (unsigned)IROrder;
			}
			const SDNode *N = (const SDNode*)(Ptr);
			return N->getIROrder();
			}
			DebugLoc getDebugLoc() {
			if (Ptr == NULL) {
			return DebugLoc();
			}
			if (IROrder >= 0) {
			const Instruction *I = (const Instruction*)(Ptr);
			return I->getDebugLoc();
			}
			const SDNode *N = (const SDNode*)(Ptr);
			return N->getDebugLoc();
			}
			};
	// Define inline functions from the SDValue class.		// Define inline functions from the SDValue class.
	inline unsigned SDValue::getOpcode() const {		inline unsigned SDValue::getOpcode() const {
	return Node->getOpcode();		return Node->getOpcode();
	}		}
	inline EVT SDValue::getValueType() const {		inline EVT SDValue::getValueType() const {
	return Node->getValueType(ResNo);		return Node->getValueType(ResNo);
	}		}
	inline unsigned SDValue::getNumOperands() const {		inline unsigned SDValue::getNumOperands() const {
	return Node->getNumOperands();		return Node->getNumOperands();
	skipping to change at line 836		skipping to change at line 900
	if (Val.getNode()) removeFromList();		if (Val.getNode()) removeFromList();
	Val.setNode(N);		Val.setNode(N);
	if (N) N->addUse(*this);		if (N) N->addUse(*this);
	}		}
	/// UnarySDNode - This class is used for single-operand SDNodes. This is s olely		/// UnarySDNode - This class is used for single-operand SDNodes. This is s olely
	/// to allow co-allocation of node operands with the node itself.		/// to allow co-allocation of node operands with the node itself.
	class UnarySDNode : public SDNode {		class UnarySDNode : public SDNode {
	SDUse Op;		SDUse Op;
	public:		public:
	UnarySDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, SDValue X)		UnarySDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs,
	: SDNode(Opc, dl, VTs) {		SDValue X)
			: SDNode(Opc, Order, dl, VTs) {
	InitOperands(&Op, X);		InitOperands(&Op, X);
	}		}
	};		};
	/// BinarySDNode - This class is used for two-operand SDNodes. This is sol ely		/// BinarySDNode - This class is used for two-operand SDNodes. This is sol ely
	/// to allow co-allocation of node operands with the node itself.		/// to allow co-allocation of node operands with the node itself.
	class BinarySDNode : public SDNode {		class BinarySDNode : public SDNode {
	SDUse Ops[2];		SDUse Ops[2];
	public:		public:
	BinarySDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, SDValue X, SDValue		BinarySDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs,
	Y)		SDValue X, SDValue Y)
	: SDNode(Opc, dl, VTs) {		: SDNode(Opc, Order, dl, VTs) {
	InitOperands(Ops, X, Y);		InitOperands(Ops, X, Y);
	}		}
	};		};
	/// TernarySDNode - This class is used for three-operand SDNodes. This is s olely		/// TernarySDNode - This class is used for three-operand SDNodes. This is s olely
	/// to allow co-allocation of node operands with the node itself.		/// to allow co-allocation of node operands with the node itself.
	class TernarySDNode : public SDNode {		class TernarySDNode : public SDNode {
	SDUse Ops[3];		SDUse Ops[3];
	public:		public:
	TernarySDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, SDValue X, SDValue		TernarySDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs,
	Y,		SDValue X, SDValue Y, SDValue Z)
	SDValue Z)		: SDNode(Opc, Order, dl, VTs) {
	: SDNode(Opc, dl, VTs) {
	InitOperands(Ops, X, Y, Z);		InitOperands(Ops, X, Y, Z);
	}		}
	};		};
	/// HandleSDNode - This class is used to form a handle around another node that		/// HandleSDNode - This class is used to form a handle around another node that
	/// is persistent and is updated across invocations of replaceAllUsesWith o n its		/// is persistent and is updated across invocations of replaceAllUsesWith o n its
	/// operand. This node should be directly created by end-users and not add ed to		/// operand. This node should be directly created by end-users and not add ed to
	/// the AllNodes list.		/// the AllNodes list.
	class HandleSDNode : public SDNode {		class HandleSDNode : public SDNode {
	SDUse Op;		SDUse Op;
	public:		public:
	// FIXME: Remove the "noinline" attribute once <rdar://problem/5852746> i
	s
	// fixed.
	#if __GNUC__==4 && __GNUC_MINOR__==2 && defined(__APPLE__) && !defined(__ll
	vm__)
	explicit __attribute__((__noinline__)) HandleSDNode(SDValue X)
	#else
	explicit HandleSDNode(SDValue X)		explicit HandleSDNode(SDValue X)
	#endif		: SDNode(ISD::HANDLENODE, 0, DebugLoc(), getSDVTList(MVT::Other)) {
	: SDNode(ISD::HANDLENODE, DebugLoc(), getSDVTList(MVT::Other)) {
	InitOperands(&Op, X);		InitOperands(&Op, X);
	}		}
	~HandleSDNode();		~HandleSDNode();
	const SDValue &getValue() const { return Op; }		const SDValue &getValue() const { return Op; }
	};		};
			class AddrSpaceCastSDNode : public UnarySDNode {
			private:
			unsigned SrcAddrSpace;
			unsigned DestAddrSpace;
			public:
			AddrSpaceCastSDNode(unsigned Order, DebugLoc dl, EVT VT, SDValue X,
			unsigned SrcAS, unsigned DestAS);
			unsigned getSrcAddressSpace() const { return SrcAddrSpace; }
			unsigned getDestAddressSpace() const { return DestAddrSpace; }
			static bool classof(const SDNode *N) {
			return N->getOpcode() == ISD::ADDRSPACECAST;
			}
			};
	/// Abstact virtual class for operations for memory operations		/// Abstact virtual class for operations for memory operations
	class MemSDNode : public SDNode {		class MemSDNode : public SDNode {
	private:		private:
	// MemoryVT - VT of in-memory value.		// MemoryVT - VT of in-memory value.
	EVT MemoryVT;		EVT MemoryVT;
	protected:		protected:
	/// MMO - Memory reference information.		/// MMO - Memory reference information.
	MachineMemOperand *MMO;		MachineMemOperand *MMO;
	public:		public:
	MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, EVT MemoryVT,		MemSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs,
	MachineMemOperand *MMO);		EVT MemoryVT, MachineMemOperand *MMO);
	MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, const SDValue *Ops,		MemSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs,
			const SDValue *Ops,
	unsigned NumOps, EVT MemoryVT, MachineMemOperand *MMO);		unsigned NumOps, EVT MemoryVT, MachineMemOperand *MMO);
	bool readMem() const { return MMO->isLoad(); }		bool readMem() const { return MMO->isLoad(); }
	bool writeMem() const { return MMO->isStore(); }		bool writeMem() const { return MMO->isStore(); }
	/// Returns alignment and volatility of the memory access		/// Returns alignment and volatility of the memory access
	unsigned getOriginalAlignment() const {		unsigned getOriginalAlignment() const {
	return MMO->getBaseAlignment();		return MMO->getBaseAlignment();
	}		}
	unsigned getAlignment() const {		unsigned getAlignment() const {
	skipping to change at line 1024		skipping to change at line 1102
	public:		public:
	// Opc: opcode for atomic		// Opc: opcode for atomic
	// VTL: value type list		// VTL: value type list
	// Chain: memory chain for operaand		// Chain: memory chain for operaand
	// Ptr: address to update as a SDValue		// Ptr: address to update as a SDValue
	// Cmp: compare value		// Cmp: compare value
	// Swp: swap value		// Swp: swap value
	// SrcVal: address to update as a Value (used for MemOperand)		// SrcVal: address to update as a Value (used for MemOperand)
	// Align: alignment of memory		// Align: alignment of memory
	AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, EVT MemVT,		AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL,
			EVT MemVT,
	SDValue Chain, SDValue Ptr,		SDValue Chain, SDValue Ptr,
	SDValue Cmp, SDValue Swp, MachineMemOperand *MMO,		SDValue Cmp, SDValue Swp, MachineMemOperand *MMO,
	AtomicOrdering Ordering, SynchronizationScope SynchScope)		AtomicOrdering Ordering, SynchronizationScope SynchScope)
	: MemSDNode(Opc, dl, VTL, MemVT, MMO) {		: MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {
	InitAtomic(Ordering, SynchScope);		InitAtomic(Ordering, SynchScope);
	InitOperands(Ops, Chain, Ptr, Cmp, Swp);		InitOperands(Ops, Chain, Ptr, Cmp, Swp);
	}		}
	AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, EVT MemVT,		AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL,
			EVT MemVT,
	SDValue Chain, SDValue Ptr,		SDValue Chain, SDValue Ptr,
	SDValue Val, MachineMemOperand *MMO,		SDValue Val, MachineMemOperand *MMO,
	AtomicOrdering Ordering, SynchronizationScope SynchScope)		AtomicOrdering Ordering, SynchronizationScope SynchScope)
	: MemSDNode(Opc, dl, VTL, MemVT, MMO) {		: MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {
	InitAtomic(Ordering, SynchScope);		InitAtomic(Ordering, SynchScope);
	InitOperands(Ops, Chain, Ptr, Val);		InitOperands(Ops, Chain, Ptr, Val);
	}		}
	AtomicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTL, EVT MemVT,		AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL,
			EVT MemVT,
	SDValue Chain, SDValue Ptr,		SDValue Chain, SDValue Ptr,
	MachineMemOperand *MMO,		MachineMemOperand *MMO,
	AtomicOrdering Ordering, SynchronizationScope SynchScope)		AtomicOrdering Ordering, SynchronizationScope SynchScope)
	: MemSDNode(Opc, dl, VTL, MemVT, MMO) {		: MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {
	InitAtomic(Ordering, SynchScope);		InitAtomic(Ordering, SynchScope);
	InitOperands(Ops, Chain, Ptr);		InitOperands(Ops, Chain, Ptr);
	}		}
			AtomicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTL, EVT
			MemVT,
			SDValue* AllOps, SDUse *DynOps, unsigned NumOps,
			MachineMemOperand *MMO,
			AtomicOrdering Ordering, SynchronizationScope SynchScope)
			: MemSDNode(Opc, Order, dl, VTL, MemVT, MMO) {
			InitAtomic(Ordering, SynchScope);
			assert((DynOps || NumOps <= array_lengthof(Ops)) &&
			"Too many ops for internal storage!");
			InitOperands(DynOps ? DynOps : Ops, AllOps, NumOps);
			}
	const SDValue &getBasePtr() const { return getOperand(1); }		const SDValue &getBasePtr() const { return getOperand(1); }
	const SDValue &getVal() const { return getOperand(2); }		const SDValue &getVal() const { return getOperand(2); }
	bool isCompareAndSwap() const {		bool isCompareAndSwap() const {
	unsigned Op = getOpcode();		unsigned Op = getOpcode();
	return Op == ISD::ATOMIC_CMP_SWAP;		return Op == ISD::ATOMIC_CMP_SWAP;
	}		}
	// Methods to support isa and dyn_cast		// Methods to support isa and dyn_cast
	skipping to change at line 1082		skipping to change at line 1173
	N->getOpcode() == ISD::ATOMIC_STORE;		N->getOpcode() == ISD::ATOMIC_STORE;
	}		}
	};		};
	/// MemIntrinsicSDNode - This SDNode is used for target intrinsics that tou ch		/// MemIntrinsicSDNode - This SDNode is used for target intrinsics that tou ch
	/// memory and need an associated MachineMemOperand. Its opcode may be		/// memory and need an associated MachineMemOperand. Its opcode may be
	/// INTRINSIC_VOID, INTRINSIC_W_CHAIN, PREFETCH, or a target-specific opcod e		/// INTRINSIC_VOID, INTRINSIC_W_CHAIN, PREFETCH, or a target-specific opcod e
	/// with a value not less than FIRST_TARGET_MEMORY_OPCODE.		/// with a value not less than FIRST_TARGET_MEMORY_OPCODE.
	class MemIntrinsicSDNode : public MemSDNode {		class MemIntrinsicSDNode : public MemSDNode {
	public:		public:
	MemIntrinsicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs,		MemIntrinsicSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VT s,
	const SDValue *Ops, unsigned NumOps,		const SDValue *Ops, unsigned NumOps,
	EVT MemoryVT, MachineMemOperand *MMO)		EVT MemoryVT, MachineMemOperand *MMO)
	: MemSDNode(Opc, dl, VTs, Ops, NumOps, MemoryVT, MMO) {		: MemSDNode(Opc, Order, dl, VTs, Ops, NumOps, MemoryVT, MMO) {
	}		}
	// Methods to support isa and dyn_cast		// Methods to support isa and dyn_cast
	static bool classof(const SDNode *N) {		static bool classof(const SDNode *N) {
	// We lower some target intrinsics to their target opcode		// We lower some target intrinsics to their target opcode
	// early a node with a target opcode can be of this class		// early a node with a target opcode can be of this class
	return N->getOpcode() == ISD::INTRINSIC_W_CHAIN ||		return N->getOpcode() == ISD::INTRINSIC_W_CHAIN ||
	N->getOpcode() == ISD::INTRINSIC_VOID ||		N->getOpcode() == ISD::INTRINSIC_VOID ||
	N->getOpcode() == ISD::PREFETCH ||		N->getOpcode() == ISD::PREFETCH ||
	N->isTargetMemoryOpcode();		N->isTargetMemoryOpcode();
	skipping to change at line 1115		skipping to change at line 1206
	/// An index of -1 is treated as undef, such that the code generator may pu t		/// An index of -1 is treated as undef, such that the code generator may pu t
	/// any value in the corresponding element of the result.		/// any value in the corresponding element of the result.
	class ShuffleVectorSDNode : public SDNode {		class ShuffleVectorSDNode : public SDNode {
	SDUse Ops[2];		SDUse Ops[2];
	// The memory for Mask is owned by the SelectionDAG's OperandAllocator, a nd		// The memory for Mask is owned by the SelectionDAG's OperandAllocator, a nd
	// is freed when the SelectionDAG object is destroyed.		// is freed when the SelectionDAG object is destroyed.
	const int *Mask;		const int *Mask;
	protected:		protected:
	friend class SelectionDAG;		friend class SelectionDAG;
	ShuffleVectorSDNode(EVT VT, DebugLoc dl, SDValue N1, SDValue N2,		ShuffleVectorSDNode(EVT VT, unsigned Order, DebugLoc dl, SDValue N1,
	const int *M)		SDValue N2, const int *M)
	: SDNode(ISD::VECTOR_SHUFFLE, dl, getSDVTList(VT)), Mask(M) {		: SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {
	InitOperands(Ops, N1, N2);		InitOperands(Ops, N1, N2);
	}		}
	public:		public:
	ArrayRef<int> getMask() const {		ArrayRef<int> getMask() const {
	EVT VT = getValueType(0);		EVT VT = getValueType(0);
	return makeArrayRef(Mask, VT.getVectorNumElements());		return makeArrayRef(Mask, VT.getVectorNumElements());
	}		}
	int getMaskElt(unsigned Idx) const {		int getMaskElt(unsigned Idx) const {
	assert(Idx < getValueType(0).getVectorNumElements() && "Idx out of rang e!");		assert(Idx < getValueType(0).getVectorNumElements() && "Idx out of rang e!");
	return Mask[Idx];		return Mask[Idx];
	}		}
	bool isSplat() const { return isSplatMask(Mask, getValueType(0)); }		bool isSplat() const { return isSplatMask(Mask, getValueType(0)); }
	int getSplatIndex() const {		int getSplatIndex() const {
	assert(isSplat() && "Cannot get splat index for non-splat!");		assert(isSplat() && "Cannot get splat index for non-splat!");
	EVT VT = getValueType(0);		EVT VT = getValueType(0);
	for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {		for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
	if (Mask[i] != -1)		if (Mask[i] >= 0)
	return Mask[i];		return Mask[i];
	}		}
	return -1;		llvm_unreachable("Splat with all undef indices?");
	}		}
	static bool isSplatMask(const int *Mask, EVT VT);		static bool isSplatMask(const int *Mask, EVT VT);
	static bool classof(const SDNode *N) {		static bool classof(const SDNode *N) {
	return N->getOpcode() == ISD::VECTOR_SHUFFLE;		return N->getOpcode() == ISD::VECTOR_SHUFFLE;
	}		}
	};		};
	class ConstantSDNode : public SDNode {		class ConstantSDNode : public SDNode {
	const ConstantInt *Value;		const ConstantInt *Value;
	friend class SelectionDAG;		friend class SelectionDAG;
	ConstantSDNode(bool isTarget, const ConstantInt *val, EVT VT)		ConstantSDNode(bool isTarget, const ConstantInt *val, EVT VT)
	: SDNode(isTarget ? ISD::TargetConstant : ISD::Constant,		: SDNode(isTarget ? ISD::TargetConstant : ISD::Constant,
	DebugLoc(), getSDVTList(VT)), Value(val) {		0, DebugLoc(), getSDVTList(VT)), Value(val) {
	}		}
	public:		public:
	const ConstantInt *getConstantIntValue() const { return Value; }		const ConstantInt *getConstantIntValue() const { return Value; }
	const APInt &getAPIntValue() const { return Value->getValue(); }		const APInt &getAPIntValue() const { return Value->getValue(); }
	uint64_t getZExtValue() const { return Value->getZExtValue(); }		uint64_t getZExtValue() const { return Value->getZExtValue(); }
	int64_t getSExtValue() const { return Value->getSExtValue(); }		int64_t getSExtValue() const { return Value->getSExtValue(); }
	bool isOne() const { return Value->isOne(); }		bool isOne() const { return Value->isOne(); }
	bool isNullValue() const { return Value->isNullValue(); }		bool isNullValue() const { return Value->isNullValue(); }
	skipping to change at line 1177		skipping to change at line 1268
	return N->getOpcode() == ISD::Constant ||		return N->getOpcode() == ISD::Constant ||
	N->getOpcode() == ISD::TargetConstant;		N->getOpcode() == ISD::TargetConstant;
	}		}
	};		};
	class ConstantFPSDNode : public SDNode {		class ConstantFPSDNode : public SDNode {
	const ConstantFP *Value;		const ConstantFP *Value;
	friend class SelectionDAG;		friend class SelectionDAG;
	ConstantFPSDNode(bool isTarget, const ConstantFP *val, EVT VT)		ConstantFPSDNode(bool isTarget, const ConstantFP *val, EVT VT)
	: SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP,		: SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP,
	DebugLoc(), getSDVTList(VT)), Value(val) {		0, DebugLoc(), getSDVTList(VT)), Value(val) {
	}		}
	public:		public:
	const APFloat& getValueAPF() const { return Value->getValueAPF(); }		const APFloat& getValueAPF() const { return Value->getValueAPF(); }
	const ConstantFP *getConstantFPValue() const { return Value; }		const ConstantFP *getConstantFPValue() const { return Value; }
	/// isZero - Return true if the value is positive or negative zero.		/// isZero - Return true if the value is positive or negative zero.
	bool isZero() const { return Value->isZero(); }		bool isZero() const { return Value->isZero(); }
	/// isNaN - Return true if the value is a NaN.		/// isNaN - Return true if the value is a NaN.
	skipping to change at line 1220		skipping to change at line 1311
	return N->getOpcode() == ISD::ConstantFP ||		return N->getOpcode() == ISD::ConstantFP ||
	N->getOpcode() == ISD::TargetConstantFP;		N->getOpcode() == ISD::TargetConstantFP;
	}		}
	};		};
	class GlobalAddressSDNode : public SDNode {		class GlobalAddressSDNode : public SDNode {
	const GlobalValue *TheGlobal;		const GlobalValue *TheGlobal;
	int64_t Offset;		int64_t Offset;
	unsigned char TargetFlags;		unsigned char TargetFlags;
	friend class SelectionDAG;		friend class SelectionDAG;
	GlobalAddressSDNode(unsigned Opc, DebugLoc DL, const GlobalValue *GA, EVT		GlobalAddressSDNode(unsigned Opc, unsigned Order, DebugLoc DL,
	VT,		const GlobalValue *GA, EVT VT, int64_t o,
	int64_t o, unsigned char TargetFlags);		unsigned char TargetFlags);
	public:		public:
	const GlobalValue *getGlobal() const { return TheGlobal; }		const GlobalValue *getGlobal() const { return TheGlobal; }
	int64_t getOffset() const { return Offset; }		int64_t getOffset() const { return Offset; }
	unsigned char getTargetFlags() const { return TargetFlags; }		unsigned char getTargetFlags() const { return TargetFlags; }
	// Return the address space this GlobalAddress belongs to.		// Return the address space this GlobalAddress belongs to.
	unsigned getAddressSpace() const;		unsigned getAddressSpace() const;
	static bool classof(const SDNode *N) {		static bool classof(const SDNode *N) {
	return N->getOpcode() == ISD::GlobalAddress ||		return N->getOpcode() == ISD::GlobalAddress ||
	skipping to change at line 1243		skipping to change at line 1335
	N->getOpcode() == ISD::GlobalTLSAddress ||		N->getOpcode() == ISD::GlobalTLSAddress ||
	N->getOpcode() == ISD::TargetGlobalTLSAddress;		N->getOpcode() == ISD::TargetGlobalTLSAddress;
	}		}
	};		};
	class FrameIndexSDNode : public SDNode {		class FrameIndexSDNode : public SDNode {
	int FI;		int FI;
	friend class SelectionDAG;		friend class SelectionDAG;
	FrameIndexSDNode(int fi, EVT VT, bool isTarg)		FrameIndexSDNode(int fi, EVT VT, bool isTarg)
	: SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,		: SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex,
	DebugLoc(), getSDVTList(VT)), FI(fi) {		0, DebugLoc(), getSDVTList(VT)), FI(fi) {
	}		}
	public:		public:
	int getIndex() const { return FI; }		int getIndex() const { return FI; }
	static bool classof(const SDNode *N) {		static bool classof(const SDNode *N) {
	return N->getOpcode() == ISD::FrameIndex ||		return N->getOpcode() == ISD::FrameIndex ||
	N->getOpcode() == ISD::TargetFrameIndex;		N->getOpcode() == ISD::TargetFrameIndex;
	}		}
	};		};
	class JumpTableSDNode : public SDNode {		class JumpTableSDNode : public SDNode {
	int JTI;		int JTI;
	unsigned char TargetFlags;		unsigned char TargetFlags;
	friend class SelectionDAG;		friend class SelectionDAG;
	JumpTableSDNode(int jti, EVT VT, bool isTarg, unsigned char TF)		JumpTableSDNode(int jti, EVT VT, bool isTarg, unsigned char TF)
	: SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable,		: SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable,
	DebugLoc(), getSDVTList(VT)), JTI(jti), TargetFlags(TF) {		0, DebugLoc(), getSDVTList(VT)), JTI(jti), TargetFlags(TF) {
	}		}
	public:		public:
	int getIndex() const { return JTI; }		int getIndex() const { return JTI; }
	unsigned char getTargetFlags() const { return TargetFlags; }		unsigned char getTargetFlags() const { return TargetFlags; }
	static bool classof(const SDNode *N) {		static bool classof(const SDNode *N) {
	return N->getOpcode() == ISD::JumpTable ||		return N->getOpcode() == ISD::JumpTable ||
	N->getOpcode() == ISD::TargetJumpTable;		N->getOpcode() == ISD::TargetJumpTable;
	}		}
	skipping to change at line 1285		skipping to change at line 1377
	union {		union {
	const Constant *ConstVal;		const Constant *ConstVal;
	MachineConstantPoolValue *MachineCPVal;		MachineConstantPoolValue *MachineCPVal;
	} Val;		} Val;
	int Offset; // It's a MachineConstantPoolValue if top bit is set.		int Offset; // It's a MachineConstantPoolValue if top bit is set.
	unsigned Alignment; // Minimum alignment requirement of CP (not log2 val ue).		unsigned Alignment; // Minimum alignment requirement of CP (not log2 val ue).
	unsigned char TargetFlags;		unsigned char TargetFlags;
	friend class SelectionDAG;		friend class SelectionDAG;
	ConstantPoolSDNode(bool isTarget, const Constant *c, EVT VT, int o,		ConstantPoolSDNode(bool isTarget, const Constant *c, EVT VT, int o,
	unsigned Align, unsigned char TF)		unsigned Align, unsigned char TF)
	: SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,		: SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
	DebugLoc(),		DebugLoc(), getSDVTList(VT)), Offset(o), Alignment(Align),
	getSDVTList(VT)), Offset(o), Alignment(Align), TargetFlags(TF)		TargetFlags(TF) {
	{
	assert(Offset >= 0 && "Offset is too large");		assert(Offset >= 0 && "Offset is too large");
	Val.ConstVal = c;		Val.ConstVal = c;
	}		}
	ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v,		ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v,
	EVT VT, int o, unsigned Align, unsigned char TF)		EVT VT, int o, unsigned Align, unsigned char TF)
	: SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,		: SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0,
	DebugLoc(),		DebugLoc(), getSDVTList(VT)), Offset(o), Alignment(Align),
	getSDVTList(VT)), Offset(o), Alignment(Align), TargetFlags(TF)		TargetFlags(TF) {
	{
	assert(Offset >= 0 && "Offset is too large");		assert(Offset >= 0 && "Offset is too large");
	Val.MachineCPVal = v;		Val.MachineCPVal = v;
	Offset |= 1 << (sizeof(unsigned)*CHAR_BIT-1);		Offset |= 1 << (sizeof(unsigned)*CHAR_BIT-1);
	}		}
	public:		public:
	bool isMachineConstantPoolEntry() const {		bool isMachineConstantPoolEntry() const {
	return Offset < 0;		return Offset < 0;
	}		}
	skipping to change at line 1342		skipping to change at line 1434
	/// Completely target-dependent object reference.		/// Completely target-dependent object reference.
	class TargetIndexSDNode : public SDNode {		class TargetIndexSDNode : public SDNode {
	unsigned char TargetFlags;		unsigned char TargetFlags;
	int Index;		int Index;
	int64_t Offset;		int64_t Offset;
	friend class SelectionDAG;		friend class SelectionDAG;
	public:		public:
	TargetIndexSDNode(int Idx, EVT VT, int64_t Ofs, unsigned char TF)		TargetIndexSDNode(int Idx, EVT VT, int64_t Ofs, unsigned char TF)
	: SDNode(ISD::TargetIndex, DebugLoc(), getSDVTList(VT)),		: SDNode(ISD::TargetIndex, 0, DebugLoc(), getSDVTList(VT)),
	TargetFlags(TF), Index(Idx), Offset(Ofs) {}		TargetFlags(TF), Index(Idx), Offset(Ofs) {}
	public:		public:
	unsigned char getTargetFlags() const { return TargetFlags; }		unsigned char getTargetFlags() const { return TargetFlags; }
	int getIndex() const { return Index; }		int getIndex() const { return Index; }
	int64_t getOffset() const { return Offset; }		int64_t getOffset() const { return Offset; }
	static bool classof(const SDNode *N) {		static bool classof(const SDNode *N) {
	return N->getOpcode() == ISD::TargetIndex;		return N->getOpcode() == ISD::TargetIndex;
	}		}
	};		};
	class BasicBlockSDNode : public SDNode {		class BasicBlockSDNode : public SDNode {
	MachineBasicBlock *MBB;		MachineBasicBlock *MBB;
	friend class SelectionDAG;		friend class SelectionDAG;
	/// Debug info is meaningful and potentially useful here, but we create		/// Debug info is meaningful and potentially useful here, but we create
	/// blocks out of order when they're jumped to, which makes it a bit		/// blocks out of order when they're jumped to, which makes it a bit
	/// harder. Let's see if we need it first.		/// harder. Let's see if we need it first.
	explicit BasicBlockSDNode(MachineBasicBlock *mbb)		explicit BasicBlockSDNode(MachineBasicBlock *mbb)
	: SDNode(ISD::BasicBlock, DebugLoc(), getSDVTList(MVT::Other)), MBB(mbb		: SDNode(ISD::BasicBlock, 0, DebugLoc(), getSDVTList(MVT::Other)), MBB(
	) {		mbb)
	}		{}
	public:		public:
	MachineBasicBlock *getBasicBlock() const { return MBB; }		MachineBasicBlock *getBasicBlock() const { return MBB; }
	static bool classof(const SDNode *N) {		static bool classof(const SDNode *N) {
	return N->getOpcode() == ISD::BasicBlock;		return N->getOpcode() == ISD::BasicBlock;
	}		}
	};		};
	/// BuildVectorSDNode - A "pseudo-class" with methods for operating on		/// BuildVectorSDNode - A "pseudo-class" with methods for operating on
	skipping to change at line 1406		skipping to change at line 1498
	/// SrcValueSDNode - An SDNode that holds an arbitrary LLVM IR Value. This is		/// SrcValueSDNode - An SDNode that holds an arbitrary LLVM IR Value. This is
	/// used when the SelectionDAG needs to make a simple reference to somethin g		/// used when the SelectionDAG needs to make a simple reference to somethin g
	/// in the LLVM IR representation.		/// in the LLVM IR representation.
	///		///
	class SrcValueSDNode : public SDNode {		class SrcValueSDNode : public SDNode {
	const Value *V;		const Value *V;
	friend class SelectionDAG;		friend class SelectionDAG;
	/// Create a SrcValue for a general value.		/// Create a SrcValue for a general value.
	explicit SrcValueSDNode(const Value *v)		explicit SrcValueSDNode(const Value *v)
	: SDNode(ISD::SRCVALUE, DebugLoc(), getSDVTList(MVT::Other)), V(v) {}		: SDNode(ISD::SRCVALUE, 0, DebugLoc(), getSDVTList(MVT::Other)), V(v) { }
	public:		public:
	/// getValue - return the contained Value.		/// getValue - return the contained Value.
	const Value *getValue() const { return V; }		const Value *getValue() const { return V; }
	static bool classof(const SDNode *N) {		static bool classof(const SDNode *N) {
	return N->getOpcode() == ISD::SRCVALUE;		return N->getOpcode() == ISD::SRCVALUE;
	}		}
	};		};
	class MDNodeSDNode : public SDNode {		class MDNodeSDNode : public SDNode {
	const MDNode *MD;		const MDNode *MD;
	friend class SelectionDAG;		friend class SelectionDAG;
	explicit MDNodeSDNode(const MDNode *md)		explicit MDNodeSDNode(const MDNode *md)
	: SDNode(ISD::MDNODE_SDNODE, DebugLoc(), getSDVTList(MVT::Other)), MD(md)		: SDNode(ISD::MDNODE_SDNODE, 0, DebugLoc(), getSDVTList(MVT::Other)), MD(
	{}		md)
			{}
	public:		public:
	const MDNode *getMD() const { return MD; }		const MDNode *getMD() const { return MD; }
	static bool classof(const SDNode *N) {		static bool classof(const SDNode *N) {
	return N->getOpcode() == ISD::MDNODE_SDNODE;		return N->getOpcode() == ISD::MDNODE_SDNODE;
	}		}
	};		};
	class RegisterSDNode : public SDNode {		class RegisterSDNode : public SDNode {
	unsigned Reg;		unsigned Reg;
	friend class SelectionDAG;		friend class SelectionDAG;
	RegisterSDNode(unsigned reg, EVT VT)		RegisterSDNode(unsigned reg, EVT VT)
	: SDNode(ISD::Register, DebugLoc(), getSDVTList(VT)), Reg(reg) {		: SDNode(ISD::Register, 0, DebugLoc(), getSDVTList(VT)), Reg(reg) {
	}		}
	public:		public:
	unsigned getReg() const { return Reg; }		unsigned getReg() const { return Reg; }
	static bool classof(const SDNode *N) {		static bool classof(const SDNode *N) {
	return N->getOpcode() == ISD::Register;		return N->getOpcode() == ISD::Register;
	}		}
	};		};
	class RegisterMaskSDNode : public SDNode {		class RegisterMaskSDNode : public SDNode {
	// The memory for RegMask is not owned by the node.		// The memory for RegMask is not owned by the node.
	const uint32_t *RegMask;		const uint32_t *RegMask;
	friend class SelectionDAG;		friend class SelectionDAG;
	RegisterMaskSDNode(const uint32_t *mask)		RegisterMaskSDNode(const uint32_t *mask)
	: SDNode(ISD::RegisterMask, DebugLoc(), getSDVTList(MVT::Untyped)),		: SDNode(ISD::RegisterMask, 0, DebugLoc(), getSDVTList(MVT::Untyped)),
	RegMask(mask) {}		RegMask(mask) {}
	public:		public:
	const uint32_t *getRegMask() const { return RegMask; }		const uint32_t *getRegMask() const { return RegMask; }
	static bool classof(const SDNode *N) {		static bool classof(const SDNode *N) {
	return N->getOpcode() == ISD::RegisterMask;		return N->getOpcode() == ISD::RegisterMask;
	}		}
	};		};
	class BlockAddressSDNode : public SDNode {		class BlockAddressSDNode : public SDNode {
	const BlockAddress *BA;		const BlockAddress *BA;
	int64_t Offset;		int64_t Offset;
	unsigned char TargetFlags;		unsigned char TargetFlags;
	friend class SelectionDAG;		friend class SelectionDAG;
	BlockAddressSDNode(unsigned NodeTy, EVT VT, const BlockAddress *ba,		BlockAddressSDNode(unsigned NodeTy, EVT VT, const BlockAddress *ba,
	int64_t o, unsigned char Flags)		int64_t o, unsigned char Flags)
	: SDNode(NodeTy, DebugLoc(), getSDVTList(VT)),		: SDNode(NodeTy, 0, DebugLoc(), getSDVTList(VT)),
	BA(ba), Offset(o), TargetFlags(Flags) {		BA(ba), Offset(o), TargetFlags(Flags) {
	}		}
	public:		public:
	const BlockAddress *getBlockAddress() const { return BA; }		const BlockAddress *getBlockAddress() const { return BA; }
	int64_t getOffset() const { return Offset; }		int64_t getOffset() const { return Offset; }
	unsigned char getTargetFlags() const { return TargetFlags; }		unsigned char getTargetFlags() const { return TargetFlags; }
	static bool classof(const SDNode *N) {		static bool classof(const SDNode *N) {
	return N->getOpcode() == ISD::BlockAddress ||		return N->getOpcode() == ISD::BlockAddress ||
	N->getOpcode() == ISD::TargetBlockAddress;		N->getOpcode() == ISD::TargetBlockAddress;
	}		}
	};		};
	class EHLabelSDNode : public SDNode {		class EHLabelSDNode : public SDNode {
	SDUse Chain;		SDUse Chain;
	MCSymbol *Label;		MCSymbol *Label;
	friend class SelectionDAG;		friend class SelectionDAG;
	EHLabelSDNode(DebugLoc dl, SDValue ch, MCSymbol *L)		EHLabelSDNode(unsigned Order, DebugLoc dl, SDValue ch, MCSymbol *L)
	: SDNode(ISD::EH_LABEL, dl, getSDVTList(MVT::Other)), Label(L) {		: SDNode(ISD::EH_LABEL, Order, dl, getSDVTList(MVT::Other)), Label(L) {
	InitOperands(&Chain, ch);		InitOperands(&Chain, ch);
	}		}
	public:		public:
	MCSymbol *getLabel() const { return Label; }		MCSymbol *getLabel() const { return Label; }
	static bool classof(const SDNode *N) {		static bool classof(const SDNode *N) {
	return N->getOpcode() == ISD::EH_LABEL;		return N->getOpcode() == ISD::EH_LABEL;
	}		}
	};		};
	class ExternalSymbolSDNode : public SDNode {		class ExternalSymbolSDNode : public SDNode {
	const char *Symbol;		const char *Symbol;
	unsigned char TargetFlags;		unsigned char TargetFlags;
	friend class SelectionDAG;		friend class SelectionDAG;
	ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned char TF, EV T VT)		ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned char TF, EV T VT)
	: SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol,		: SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol,
	DebugLoc(), getSDVTList(VT)), Symbol(Sym), TargetFlags(TF) {		0, DebugLoc(), getSDVTList(VT)), Symbol(Sym), TargetFlags(TF) {
	}		}
	public:		public:
	const char *getSymbol() const { return Symbol; }		const char *getSymbol() const { return Symbol; }
	unsigned char getTargetFlags() const { return TargetFlags; }		unsigned char getTargetFlags() const { return TargetFlags; }
	static bool classof(const SDNode *N) {		static bool classof(const SDNode *N) {
	return N->getOpcode() == ISD::ExternalSymbol ||		return N->getOpcode() == ISD::ExternalSymbol ||
	N->getOpcode() == ISD::TargetExternalSymbol;		N->getOpcode() == ISD::TargetExternalSymbol;
	}		}
	};		};
	class CondCodeSDNode : public SDNode {		class CondCodeSDNode : public SDNode {
	ISD::CondCode Condition;		ISD::CondCode Condition;
	friend class SelectionDAG;		friend class SelectionDAG;
	explicit CondCodeSDNode(ISD::CondCode Cond)		explicit CondCodeSDNode(ISD::CondCode Cond)
	: SDNode(ISD::CONDCODE, DebugLoc(), getSDVTList(MVT::Other)),		: SDNode(ISD::CONDCODE, 0, DebugLoc(), getSDVTList(MVT::Other)),
	Condition(Cond) {		Condition(Cond) {
	}		}
	public:		public:
	ISD::CondCode get() const { return Condition; }		ISD::CondCode get() const { return Condition; }
	static bool classof(const SDNode *N) {		static bool classof(const SDNode *N) {
	return N->getOpcode() == ISD::CONDCODE;		return N->getOpcode() == ISD::CONDCODE;
	}		}
	};		};
	/// CvtRndSatSDNode - NOTE: avoid using this node as this may disappear in the		/// CvtRndSatSDNode - NOTE: avoid using this node as this may disappear in the
	/// future and most targets don't support it.		/// future and most targets don't support it.
	class CvtRndSatSDNode : public SDNode {		class CvtRndSatSDNode : public SDNode {
	ISD::CvtCode CvtCode;		ISD::CvtCode CvtCode;
	friend class SelectionDAG;		friend class SelectionDAG;
	explicit CvtRndSatSDNode(EVT VT, DebugLoc dl, const SDValue *Ops,		explicit CvtRndSatSDNode(EVT VT, unsigned Order, DebugLoc dl,
	unsigned NumOps, ISD::CvtCode Code)		const SDValue *Ops, unsigned NumOps,
	: SDNode(ISD::CONVERT_RNDSAT, dl, getSDVTList(VT), Ops, NumOps),		ISD::CvtCode Code)
			: SDNode(ISD::CONVERT_RNDSAT, Order, dl, getSDVTList(VT), Ops, NumOps),
	CvtCode(Code) {		CvtCode(Code) {
	assert(NumOps == 5 && "wrong number of operations");		assert(NumOps == 5 && "wrong number of operations");
	}		}
	public:		public:
	ISD::CvtCode getCvtCode() const { return CvtCode; }		ISD::CvtCode getCvtCode() const { return CvtCode; }
	static bool classof(const SDNode *N) {		static bool classof(const SDNode *N) {
	return N->getOpcode() == ISD::CONVERT_RNDSAT;		return N->getOpcode() == ISD::CONVERT_RNDSAT;
	}		}
	};		};
	/// VTSDNode - This class is used to represent EVT's, which are used		/// VTSDNode - This class is used to represent EVT's, which are used
	/// to parameterize some operations.		/// to parameterize some operations.
	class VTSDNode : public SDNode {		class VTSDNode : public SDNode {
	EVT ValueType;		EVT ValueType;
	friend class SelectionDAG;		friend class SelectionDAG;
	explicit VTSDNode(EVT VT)		explicit VTSDNode(EVT VT)
	: SDNode(ISD::VALUETYPE, DebugLoc(), getSDVTList(MVT::Other)),		: SDNode(ISD::VALUETYPE, 0, DebugLoc(), getSDVTList(MVT::Other)),
	ValueType(VT) {		ValueType(VT) {
	}		}
	public:		public:
	EVT getVT() const { return ValueType; }		EVT getVT() const { return ValueType; }
	static bool classof(const SDNode *N) {		static bool classof(const SDNode *N) {
	return N->getOpcode() == ISD::VALUETYPE;		return N->getOpcode() == ISD::VALUETYPE;
	}		}
	};		};
	skipping to change at line 1583		skipping to change at line 1677
	///		///
	class LSBaseSDNode : public MemSDNode {		class LSBaseSDNode : public MemSDNode {
	//! Operand array for load and store		//! Operand array for load and store
	/*!		/*!
	\note Moving this array to the base class captures more		\note Moving this array to the base class captures more
	common functionality shared between LoadSDNode and		common functionality shared between LoadSDNode and
	StoreSDNode		StoreSDNode
	*/		*/
	SDUse Ops[4];		SDUse Ops[4];
	public:		public:
	LSBaseSDNode(ISD::NodeType NodeTy, DebugLoc dl, SDValue *Operands,		LSBaseSDNode(ISD::NodeType NodeTy, unsigned Order, DebugLoc dl,
	unsigned numOperands, SDVTList VTs, ISD::MemIndexedMode AM,		SDValue *Operands, unsigned numOperands,
	EVT MemVT, MachineMemOperand *MMO)		SDVTList VTs, ISD::MemIndexedMode AM, EVT MemVT,
	: MemSDNode(NodeTy, dl, VTs, MemVT, MMO) {		MachineMemOperand *MMO)
			: MemSDNode(NodeTy, Order, dl, VTs, MemVT, MMO) {
	SubclassData |= AM << 2;		SubclassData |= AM << 2;
	assert(getAddressingMode() == AM && "MemIndexedMode encoding error!");		assert(getAddressingMode() == AM && "MemIndexedMode encoding error!");
	InitOperands(Ops, Operands, numOperands);		InitOperands(Ops, Operands, numOperands);
	assert((getOffset().getOpcode() == ISD::UNDEF || isIndexed()) &&		assert((getOffset().getOpcode() == ISD::UNDEF || isIndexed()) &&
	"Only indexed loads and stores have a non-undef offset operand") ;		"Only indexed loads and stores have a non-undef offset operand") ;
	}		}
	const SDValue &getOffset() const {		const SDValue &getOffset() const {
	return getOperand(getOpcode() == ISD::LOAD ? 2 : 3);		return getOperand(getOpcode() == ISD::LOAD ? 2 : 3);
	}		}
	skipping to change at line 1620		skipping to change at line 1715
	static bool classof(const SDNode *N) {		static bool classof(const SDNode *N) {
	return N->getOpcode() == ISD::LOAD ||		return N->getOpcode() == ISD::LOAD ||
	N->getOpcode() == ISD::STORE;		N->getOpcode() == ISD::STORE;
	}		}
	};		};
	/// LoadSDNode - This class is used to represent ISD::LOAD nodes.		/// LoadSDNode - This class is used to represent ISD::LOAD nodes.
	///		///
	class LoadSDNode : public LSBaseSDNode {		class LoadSDNode : public LSBaseSDNode {
	friend class SelectionDAG;		friend class SelectionDAG;
	LoadSDNode(SDValue *ChainPtrOff, DebugLoc dl, SDVTList VTs,		LoadSDNode(SDValue *ChainPtrOff, unsigned Order, DebugLoc dl, SDVTList VT s,
	ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,		ISD::MemIndexedMode AM, ISD::LoadExtType ETy, EVT MemVT,
	MachineMemOperand *MMO)		MachineMemOperand *MMO)
	: LSBaseSDNode(ISD::LOAD, dl, ChainPtrOff, 3,		: LSBaseSDNode(ISD::LOAD, Order, dl, ChainPtrOff, 3, VTs, AM, MemVT, MM
	VTs, AM, MemVT, MMO) {		O) {
	SubclassData |= (unsigned short)ETy;		SubclassData |= (unsigned short)ETy;
	assert(getExtensionType() == ETy && "LoadExtType encoding error!");		assert(getExtensionType() == ETy && "LoadExtType encoding error!");
	assert(readMem() && "Load MachineMemOperand is not a load!");		assert(readMem() && "Load MachineMemOperand is not a load!");
	assert(!writeMem() && "Load MachineMemOperand is a store!");		assert(!writeMem() && "Load MachineMemOperand is a store!");
	}		}
	public:		public:
	/// getExtensionType - Return whether this is a plain node,		/// getExtensionType - Return whether this is a plain node,
	/// or one of the varieties of value-extending loads.		/// or one of the varieties of value-extending loads.
	ISD::LoadExtType getExtensionType() const {		ISD::LoadExtType getExtensionType() const {
	skipping to change at line 1650		skipping to change at line 1744
	static bool classof(const SDNode *N) {		static bool classof(const SDNode *N) {
	return N->getOpcode() == ISD::LOAD;		return N->getOpcode() == ISD::LOAD;
	}		}
	};		};
	/// StoreSDNode - This class is used to represent ISD::STORE nodes.		/// StoreSDNode - This class is used to represent ISD::STORE nodes.
	///		///
	class StoreSDNode : public LSBaseSDNode {		class StoreSDNode : public LSBaseSDNode {
	friend class SelectionDAG;		friend class SelectionDAG;
	StoreSDNode(SDValue *ChainValuePtrOff, DebugLoc dl, SDVTList VTs,		StoreSDNode(SDValue *ChainValuePtrOff, unsigned Order, DebugLoc dl,
	ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT,		SDVTList VTs, ISD::MemIndexedMode AM, bool isTrunc, EVT MemVT
			,
	MachineMemOperand *MMO)		MachineMemOperand *MMO)
	: LSBaseSDNode(ISD::STORE, dl, ChainValuePtrOff, 4,		: LSBaseSDNode(ISD::STORE, Order, dl, ChainValuePtrOff, 4,
	VTs, AM, MemVT, MMO) {		VTs, AM, MemVT, MMO) {
	SubclassData |= (unsigned short)isTrunc;		SubclassData |= (unsigned short)isTrunc;
	assert(isTruncatingStore() == isTrunc && "isTrunc encoding error!");		assert(isTruncatingStore() == isTrunc && "isTrunc encoding error!");
	assert(!readMem() && "Store MachineMemOperand is a load!");		assert(!readMem() && "Store MachineMemOperand is a load!");
	assert(writeMem() && "Store MachineMemOperand is not a store!");		assert(writeMem() && "Store MachineMemOperand is not a store!");
	}		}
	public:		public:
	/// isTruncatingStore - Return true if the op does a truncation before st ore.		/// isTruncatingStore - Return true if the op does a truncation before st ore.
	/// For integers this is the same as doing a TRUNCATE and storing the res ult.		/// For integers this is the same as doing a TRUNCATE and storing the res ult.
	skipping to change at line 1686		skipping to change at line 1780
	/// MachineSDNode - An SDNode that represents everything that will be neede d		/// MachineSDNode - An SDNode that represents everything that will be neede d
	/// to construct a MachineInstr. These nodes are created during the		/// to construct a MachineInstr. These nodes are created during the
	/// instruction selection proper phase.		/// instruction selection proper phase.
	///		///
	class MachineSDNode : public SDNode {		class MachineSDNode : public SDNode {
	public:		public:
	typedef MachineMemOperand **mmo_iterator;		typedef MachineMemOperand **mmo_iterator;
	private:		private:
	friend class SelectionDAG;		friend class SelectionDAG;
	MachineSDNode(unsigned Opc, const DebugLoc DL, SDVTList VTs)		MachineSDNode(unsigned Opc, unsigned Order, const DebugLoc DL, SDVTList V
	: SDNode(Opc, DL, VTs), MemRefs(0), MemRefsEnd(0) {}		Ts)
			: SDNode(Opc, Order, DL, VTs), MemRefs(0), MemRefsEnd(0) {}
	/// LocalOperands - Operands for this instruction, if they fit here. If		/// LocalOperands - Operands for this instruction, if they fit here. If
	/// they don't, this field is unused.		/// they don't, this field is unused.
	SDUse LocalOperands[4];		SDUse LocalOperands[4];
	/// MemRefs - Memory reference descriptions for this instruction.		/// MemRefs - Memory reference descriptions for this instruction.
	mmo_iterator MemRefs;		mmo_iterator MemRefs;
	mmo_iterator MemRefsEnd;		mmo_iterator MemRefsEnd;
	public:		public:
	skipping to change at line 1775		skipping to change at line 1869
	static inline ChildIteratorType child_begin(NodeType *N) {		static inline ChildIteratorType child_begin(NodeType *N) {
	return SDNodeIterator::begin(N);		return SDNodeIterator::begin(N);
	}		}
	static inline ChildIteratorType child_end(NodeType *N) {		static inline ChildIteratorType child_end(NodeType *N) {
	return SDNodeIterator::end(N);		return SDNodeIterator::end(N);
	}		}
	};		};
	/// LargestSDNode - The largest SDNode class.		/// LargestSDNode - The largest SDNode class.
	///		///
	typedef LoadSDNode LargestSDNode;		typedef AtomicSDNode LargestSDNode;
	/// MostAlignedSDNode - The SDNode class with the greatest alignment		/// MostAlignedSDNode - The SDNode class with the greatest alignment
	/// requirement.		/// requirement.
	///		///
	typedef GlobalAddressSDNode MostAlignedSDNode;		typedef GlobalAddressSDNode MostAlignedSDNode;
	namespace ISD {		namespace ISD {
	/// isNormalLoad - Returns true if the specified node is a non-extending		/// isNormalLoad - Returns true if the specified node is a non-extending
	/// and unindexed load.		/// and unindexed load.
	inline bool isNormalLoad(const SDNode *N) {		inline bool isNormalLoad(const SDNode *N) {
End of changes. 55 change blocks.
	90 lines changed or deleted		187 lines changed or added

	SetVector.h		SetVector.h
	skipping to change at line 172		skipping to change at line 172
	vector_.clear();		vector_.clear();
	}		}
	/// \brief Remove the last element of the SetVector.		/// \brief Remove the last element of the SetVector.
	void pop_back() {		void pop_back() {
	assert(!empty() && "Cannot remove an element from an empty SetVector!") ;		assert(!empty() && "Cannot remove an element from an empty SetVector!") ;
	set_.erase(back());		set_.erase(back());
	vector_.pop_back();		vector_.pop_back();
	}		}
	T pop_back_val() {		T LLVM_ATTRIBUTE_UNUSED_RESULT pop_back_val() {
	T Ret = back();		T Ret = back();
	pop_back();		pop_back();
	return Ret;		return Ret;
	}		}
	bool operator==(const SetVector &that) const {		bool operator==(const SetVector &that) const {
	return vector_ == that.vector_;		return vector_ == that.vector_;
	}		}
	bool operator!=(const SetVector &that) const {		bool operator!=(const SetVector &that) const {
End of changes. 1 change blocks.
	1 lines changed or deleted		1 lines changed or added

	Signals.h		Signals.h
	skipping to change at line 31		skipping to change at line 31
	namespace llvm {		namespace llvm {
	namespace sys {		namespace sys {
	/// This function runs all the registered interrupt handlers, including t he		/// This function runs all the registered interrupt handlers, including t he
	/// removal of files registered by RemoveFileOnSignal.		/// removal of files registered by RemoveFileOnSignal.
	void RunInterruptHandlers();		void RunInterruptHandlers();
	/// This function registers signal handlers to ensure that if a signal ge ts		/// This function registers signal handlers to ensure that if a signal ge ts
	/// delivered that the named file is removed.		/// delivered that the named file is removed.
	/// @brief Remove a file if a fatal signal occurs.		/// @brief Remove a file if a fatal signal occurs.
	bool RemoveFileOnSignal(const Path &Filename, std::string* ErrMsg = 0);		bool RemoveFileOnSignal(StringRef Filename, std::string* ErrMsg = 0);
	/// This function removes a file from the list of files to be removed on		/// This function removes a file from the list of files to be removed on
	/// signal delivery.		/// signal delivery.
	void DontRemoveFileOnSignal(const Path &Filename);		void DontRemoveFileOnSignal(StringRef Filename);
	/// When an error signal (such as SIBABRT or SIGSEGV) is delivered to the		/// When an error signal (such as SIBABRT or SIGSEGV) is delivered to the
	/// process, print a stack trace and then exit.		/// process, print a stack trace and then exit.
	/// @brief Print a stack trace if a fatal signal occurs.		/// @brief Print a stack trace if a fatal signal occurs.
	void PrintStackTraceOnErrorSignal();		void PrintStackTraceOnErrorSignal();
	/// \brief Print the stack trace using the given \c FILE object.		/// \brief Print the stack trace using the given \c FILE object.
	void PrintStackTrace(FILE *);		void PrintStackTrace(FILE *);
	/// AddSignalHandler - Add a function to be called when an abort/kill sig nal		/// AddSignalHandler - Add a function to be called when an abort/kill sig nal
End of changes. 2 change blocks.
	2 lines changed or deleted		2 lines changed or added

	SlotIndexes.h		SlotIndexes.h
	skipping to change at line 165		skipping to change at line 165
	"Attempt to construct index with 0 pointer.");		"Attempt to construct index with 0 pointer.");
	}		}
	/// Returns true if this is a valid index. Invalid indicies do		/// Returns true if this is a valid index. Invalid indicies do
	/// not point into an index table, and cannot be compared.		/// not point into an index table, and cannot be compared.
	bool isValid() const {		bool isValid() const {
	return lie.getPointer();		return lie.getPointer();
	}		}
	/// Return true for a valid index.		/// Return true for a valid index.
	operator bool() const { return isValid(); }		LLVM_EXPLICIT operator bool() const { return isValid(); }
	/// Print this index to the given raw_ostream.		/// Print this index to the given raw_ostream.
	void print(raw_ostream &os) const;		void print(raw_ostream &os) const;
	/// Dump this index to stderr.		/// Dump this index to stderr.
	void dump() const;		void dump() const;
	/// Compare two SlotIndex objects for equality.		/// Compare two SlotIndex objects for equality.
	bool operator==(SlotIndex other) const {		bool operator==(SlotIndex other) const {
	return lie == other.lie;		return lie == other.lie;
	skipping to change at line 221		skipping to change at line 221
	/// B. This is equivalent to A < B && !isSameInstr(A, B).		/// B. This is equivalent to A < B && !isSameInstr(A, B).
	static bool isEarlierInstr(SlotIndex A, SlotIndex B) {		static bool isEarlierInstr(SlotIndex A, SlotIndex B) {
	return A.listEntry()->getIndex() < B.listEntry()->getIndex();		return A.listEntry()->getIndex() < B.listEntry()->getIndex();
	}		}
	/// Return the distance from this index to the given one.		/// Return the distance from this index to the given one.
	int distance(SlotIndex other) const {		int distance(SlotIndex other) const {
	return other.getIndex() - getIndex();		return other.getIndex() - getIndex();
	}		}
			/// Return the scaled distance from this index to the given one, where
			all
			/// slots on the same instruction have zero distance.
			int getInstrDistance(SlotIndex other) const {
			return (other.listEntry()->getIndex() - listEntry()->getIndex())
			/ Slot_Count;
			}
	/// isBlock - Returns true if this is a block boundary slot.		/// isBlock - Returns true if this is a block boundary slot.
	bool isBlock() const { return getSlot() == Slot_Block; }		bool isBlock() const { return getSlot() == Slot_Block; }
	/// isEarlyClobber - Returns true if this is an early-clobber slot.		/// isEarlyClobber - Returns true if this is an early-clobber slot.
	bool isEarlyClobber() const { return getSlot() == Slot_EarlyClobber; }		bool isEarlyClobber() const { return getSlot() == Slot_EarlyClobber; }
	/// isRegister - Returns true if this is a normal register use/def slot .		/// isRegister - Returns true if this is a normal register use/def slot .
	/// Note that early-clobber slots may also be used for uses and defs.		/// Note that early-clobber slots may also be used for uses and defs.
	bool isRegister() const { return getSlot() == Slot_Register; }		bool isRegister() const { return getSlot() == Slot_Register; }
End of changes. 2 change blocks.
	1 lines changed or deleted		9 lines changed or added

	SmallBitVector.h		SmallBitVector.h
	skipping to change at line 219		skipping to change at line 219
	}		}
	/// find_first - Returns the index of the first set bit, -1 if none		/// find_first - Returns the index of the first set bit, -1 if none
	/// of the bits are set.		/// of the bits are set.
	int find_first() const {		int find_first() const {
	if (isSmall()) {		if (isSmall()) {
	uintptr_t Bits = getSmallBits();		uintptr_t Bits = getSmallBits();
	if (Bits == 0)		if (Bits == 0)
	return -1;		return -1;
	if (NumBaseBits == 32)		if (NumBaseBits == 32)
	return CountTrailingZeros_32(Bits);		return countTrailingZeros(Bits);
	if (NumBaseBits == 64)		if (NumBaseBits == 64)
	return CountTrailingZeros_64(Bits);		return countTrailingZeros(Bits);
	llvm_unreachable("Unsupported!");		llvm_unreachable("Unsupported!");
	}		}
	return getPointer()->find_first();		return getPointer()->find_first();
	}		}
	/// find_next - Returns the index of the next set bit following the		/// find_next - Returns the index of the next set bit following the
	/// "Prev" bit. Returns -1 if the next set bit is not found.		/// "Prev" bit. Returns -1 if the next set bit is not found.
	int find_next(unsigned Prev) const {		int find_next(unsigned Prev) const {
	if (isSmall()) {		if (isSmall()) {
	uintptr_t Bits = getSmallBits();		uintptr_t Bits = getSmallBits();
	// Mask off previous bits.		// Mask off previous bits.
	Bits &= ~uintptr_t(0) << (Prev + 1);		Bits &= ~uintptr_t(0) << (Prev + 1);
	if (Bits == 0 || Prev + 1 >= getSmallSize())		if (Bits == 0 || Prev + 1 >= getSmallSize())
	return -1;		return -1;
	if (NumBaseBits == 32)		if (NumBaseBits == 32)
	return CountTrailingZeros_32(Bits);		return countTrailingZeros(Bits);
	if (NumBaseBits == 64)		if (NumBaseBits == 64)
	return CountTrailingZeros_64(Bits);		return countTrailingZeros(Bits);
	llvm_unreachable("Unsupported!");		llvm_unreachable("Unsupported!");
	}		}
	return getPointer()->find_next(Prev);		return getPointer()->find_next(Prev);
	}		}
	/// clear - Clear all bits.		/// clear - Clear all bits.
	void clear() {		void clear() {
	if (!isSmall())		if (!isSmall())
	delete getPointer();		delete getPointer();
	switchToSmall(0, 0);		switchToSmall(0, 0);
	skipping to change at line 429		skipping to change at line 429
	else if (!RHS.isSmall())		else if (!RHS.isSmall())
	getPointer()->operator&=(*RHS.getPointer());		getPointer()->operator&=(*RHS.getPointer());
	else {		else {
	SmallBitVector Copy = RHS;		SmallBitVector Copy = RHS;
	Copy.resize(size());		Copy.resize(size());
	getPointer()->operator&=(*Copy.getPointer());		getPointer()->operator&=(*Copy.getPointer());
	}		}
	return *this;		return *this;
	}		}
			/// reset - Reset bits that are set in RHS. Same as *this &= ~RHS.
			SmallBitVector &reset(const SmallBitVector &RHS) {
			if (isSmall() && RHS.isSmall())
			setSmallBits(getSmallBits() & ~RHS.getSmallBits());
			else if (!isSmall() && !RHS.isSmall())
			getPointer()->reset(*RHS.getPointer());
			else
			for (unsigned i = 0, e = std::min(size(), RHS.size()); i != e; ++i)
			if (RHS.test(i))
			reset(i);
			return *this;
			}
			/// test - Check if (This - RHS) is zero.
			/// This is the same as reset(RHS) and any().
			bool test(const SmallBitVector &RHS) const {
			if (isSmall() && RHS.isSmall())
			return (getSmallBits() & ~RHS.getSmallBits()) != 0;
			if (!isSmall() && !RHS.isSmall())
			return getPointer()->test(*RHS.getPointer());
			unsigned i, e;
			for (i = 0, e = std::min(size(), RHS.size()); i != e; ++i)
			if (test(i) && !RHS.test(i))
			return true;
			for (e = size(); i != e; ++i)
			if (test(i))
			return true;
			return false;
			}
	SmallBitVector &operator|=(const SmallBitVector &RHS) {		SmallBitVector &operator|=(const SmallBitVector &RHS) {
	resize(std::max(size(), RHS.size()));		resize(std::max(size(), RHS.size()));
	if (isSmall())		if (isSmall())
	setSmallBits(getSmallBits() | RHS.getSmallBits());		setSmallBits(getSmallBits() | RHS.getSmallBits());
	else if (!RHS.isSmall())		else if (!RHS.isSmall())
	getPointer()->operator|=(*RHS.getPointer());		getPointer()->operator|=(*RHS.getPointer());
	else {		else {
	SmallBitVector Copy = RHS;		SmallBitVector Copy = RHS;
	Copy.resize(size());		Copy.resize(size());
	getPointer()->operator|=(*Copy.getPointer());		getPointer()->operator|=(*Copy.getPointer());
End of changes. 5 change blocks.
	4 lines changed or deleted		38 lines changed or added

	SmallPtrSet.h		SmallPtrSet.h
	skipping to change at line 74		skipping to change at line 74
	SmallPtrSetImpl(const void **SmallStorage, const SmallPtrSetImpl& that);		SmallPtrSetImpl(const void **SmallStorage, const SmallPtrSetImpl& that);
	explicit SmallPtrSetImpl(const void **SmallStorage, unsigned SmallSize) :		explicit SmallPtrSetImpl(const void **SmallStorage, unsigned SmallSize) :
	SmallArray(SmallStorage), CurArray(SmallStorage), CurArraySize(SmallSiz e) {		SmallArray(SmallStorage), CurArray(SmallStorage), CurArraySize(SmallSiz e) {
	assert(SmallSize && (SmallSize & (SmallSize-1)) == 0 &&		assert(SmallSize && (SmallSize & (SmallSize-1)) == 0 &&
	"Initial size must be a power of two!");		"Initial size must be a power of two!");
	clear();		clear();
	}		}
	~SmallPtrSetImpl();		~SmallPtrSetImpl();
	public:		public:
	bool empty() const { return size() == 0; }		bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const { return size() == 0; }
	unsigned size() const { return NumElements; }		unsigned size() const { return NumElements; }
	void clear() {		void clear() {
	// If the capacity of the array is huge, and the # elements used is sma ll,		// If the capacity of the array is huge, and the # elements used is sma ll,
	// shrink the array.		// shrink the array.
	if (!isSmall() && NumElements*4 < CurArraySize && CurArraySize > 32)		if (!isSmall() && NumElements*4 < CurArraySize && CurArraySize > 32)
	return shrink_and_clear();		return shrink_and_clear();
	// Fill the array with empty markers.		// Fill the array with empty markers.
	memset(CurArray, -1, CurArraySize*sizeof(void*));		memset(CurArray, -1, CurArraySize*sizeof(void*));
End of changes. 1 change blocks.
	1 lines changed or deleted		1 lines changed or added

	SmallVector.h		SmallVector.h
	skipping to change at line 56		skipping to change at line 56
	/// size_in_bytes - This returns size()*sizeof(T).		/// size_in_bytes - This returns size()*sizeof(T).
	size_t size_in_bytes() const {		size_t size_in_bytes() const {
	return size_t((char*)EndX - (char*)BeginX);		return size_t((char*)EndX - (char*)BeginX);
	}		}
	/// capacity_in_bytes - This returns capacity()*sizeof(T).		/// capacity_in_bytes - This returns capacity()*sizeof(T).
	size_t capacity_in_bytes() const {		size_t capacity_in_bytes() const {
	return size_t((char*)CapacityX - (char*)BeginX);		return size_t((char*)CapacityX - (char*)BeginX);
	}		}
	bool empty() const { return BeginX == EndX; }		bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const { return BeginX == EndX; }
	};		};
	template <typename T, unsigned N> struct SmallVectorStorage;		template <typename T, unsigned N> struct SmallVectorStorage;
	/// SmallVectorTemplateCommon - This is the part of SmallVectorTemplateBase		/// SmallVectorTemplateCommon - This is the part of SmallVectorTemplateBase
	/// which does not depend on whether the type T is a POD. The extra dummy		/// which does not depend on whether the type T is a POD. The extra dummy
	/// template argument is used by ArrayRef to avoid unnecessarily requiring T		/// template argument is used by ArrayRef to avoid unnecessarily requiring T
	/// to be complete.		/// to be complete.
	template <typename T, typename = void>		template <typename T, typename = void>
	class SmallVectorTemplateCommon : public SmallVectorBase {		class SmallVectorTemplateCommon : public SmallVectorBase {
	skipping to change at line 427		skipping to change at line 427
	std::uninitialized_fill(this->end(), this->begin()+N, NV);		std::uninitialized_fill(this->end(), this->begin()+N, NV);
	this->setEnd(this->begin()+N);		this->setEnd(this->begin()+N);
	}		}
	}		}
	void reserve(unsigned N) {		void reserve(unsigned N) {
	if (this->capacity() < N)		if (this->capacity() < N)
	this->grow(N);		this->grow(N);
	}		}
	T pop_back_val() {		T LLVM_ATTRIBUTE_UNUSED_RESULT pop_back_val() {
	#if LLVM_HAS_RVALUE_REFERENCES		#if LLVM_HAS_RVALUE_REFERENCES
	T Result = ::std::move(this->back());		T Result = ::std::move(this->back());
	#else		#else
	T Result = this->back();		T Result = this->back();
	#endif		#endif
	this->pop_back();		this->pop_back();
	return Result;		return Result;
	}		}
	void swap(SmallVectorImpl &RHS);		void swap(SmallVectorImpl &RHS);
End of changes. 2 change blocks.
	2 lines changed or deleted		2 lines changed or added

	Solaris.h		Solaris.h
	skipping to change at line 20		skipping to change at line 20
	* This file contains portability fixes for Solaris hosts.		* This file contains portability fixes for Solaris hosts.
	*		*
	*===---------------------------------------------------------------------- ===*/		*===---------------------------------------------------------------------- ===*/
	#ifndef LLVM_SUPPORT_SOLARIS_H		#ifndef LLVM_SUPPORT_SOLARIS_H
	#define LLVM_SUPPORT_SOLARIS_H		#define LLVM_SUPPORT_SOLARIS_H
	#include <sys/types.h>		#include <sys/types.h>
	#include <sys/regset.h>		#include <sys/regset.h>
			/* Solaris doesn't have endian.h. SPARC is the only supported big-endian IS
			A. */
			#define BIG_ENDIAN 4321
			#define LITTLE_ENDIAN 1234
			#if defined(__sparc) || defined(__sparc__)
			#define BYTE_ORDER BIG_ENDIAN
			#else
			#define BYTE_ORDER LITTLE_ENDIAN
			#endif
	#undef CS		#undef CS
	#undef DS		#undef DS
	#undef ES		#undef ES
	#undef FS		#undef FS
	#undef GS		#undef GS
	#undef SS		#undef SS
	#undef EAX		#undef EAX
	#undef ECX		#undef ECX
	#undef EDX		#undef EDX
	#undef EBX		#undef EBX
End of changes. 1 change blocks.
	0 lines changed or deleted		10 lines changed or added

	Solution.h		Solution.h
	skipping to change at line 29		skipping to change at line 29
	#include <map>		#include <map>
	namespace PBQP {		namespace PBQP {
	/// \brief Represents a solution to a PBQP problem.		/// \brief Represents a solution to a PBQP problem.
	///		///
	/// To get the selection for each node in the problem use the getSelectio n method.		/// To get the selection for each node in the problem use the getSelectio n method.
	class Solution {		class Solution {
	private:		private:
	typedef std::map<Graph::ConstNodeItr, unsigned,		typedef std::map<Graph::NodeId, unsigned> SelectionsMap;
	NodeItrComparator> SelectionsMap;
	SelectionsMap selections;		SelectionsMap selections;
	unsigned r0Reductions, r1Reductions, r2Reductions, rNReductions;		unsigned r0Reductions, r1Reductions, r2Reductions, rNReductions;
	public:		public:
	/// \brief Initialise an empty solution.		/// \brief Initialise an empty solution.
	Solution()		Solution()
	: r0Reductions(0), r1Reductions(0), r2Reductions(0), rNReductions(0) {}		: r0Reductions(0), r1Reductions(0), r2Reductions(0), rNReductions(0) {}
	skipping to change at line 74		skipping to change at line 73
	unsigned numR2Reductions() const { return r2Reductions; }		unsigned numR2Reductions() const { return r2Reductions; }
	/// \brief Records a reduction via the RN rule. Should be called from t he		/// \brief Records a reduction via the RN rule. Should be called from t he
	/// solver only.		/// solver only.
	void recordRN() { ++ rNReductions; }		void recordRN() { ++ rNReductions; }
	/// \brief Returns the number of RN reductions applied to solve the pro blem.		/// \brief Returns the number of RN reductions applied to solve the pro blem.
	unsigned numRNReductions() const { return rNReductions; }		unsigned numRNReductions() const { return rNReductions; }
	/// \brief Set the selection for a given node.		/// \brief Set the selection for a given node.
	/// @param nItr Node iterator.		/// @param nodeId Node id.
	/// @param selection Selection for nItr.		/// @param selection Selection for nodeId.
	void setSelection(Graph::NodeItr nItr, unsigned selection) {		void setSelection(Graph::NodeId nodeId, unsigned selection) {
	selections[nItr] = selection;		selections[nodeId] = selection;
	}		}
	/// \brief Get a node's selection.		/// \brief Get a node's selection.
	/// @param nItr Node iterator.		/// @param nodeId Node id.
	/// @return The selection for nItr;		/// @return The selection for nodeId;
	unsigned getSelection(Graph::ConstNodeItr nItr) const {		unsigned getSelection(Graph::NodeId nodeId) const {
	SelectionsMap::const_iterator sItr = selections.find(nItr);		SelectionsMap::const_iterator sItr = selections.find(nodeId);
	assert(sItr != selections.end() && "No selection for node.");		assert(sItr != selections.end() && "No selection for node.");
	return sItr->second;		return sItr->second;
	}		}
	};		};
	}		}
	#endif // LLVM_CODEGEN_PBQP_SOLUTION_H		#endif // LLVM_CODEGEN_PBQP_SOLUTION_H
End of changes. 3 change blocks.
	10 lines changed or deleted		9 lines changed or added

	SourceMgr.h		SourceMgr.h
	skipping to change at line 101		skipping to change at line 101
	const SrcBuffer &getBufferInfo(unsigned i) const {		const SrcBuffer &getBufferInfo(unsigned i) const {
	assert(i < Buffers.size() && "Invalid Buffer ID!");		assert(i < Buffers.size() && "Invalid Buffer ID!");
	return Buffers[i];		return Buffers[i];
	}		}
	const MemoryBuffer *getMemoryBuffer(unsigned i) const {		const MemoryBuffer *getMemoryBuffer(unsigned i) const {
	assert(i < Buffers.size() && "Invalid Buffer ID!");		assert(i < Buffers.size() && "Invalid Buffer ID!");
	return Buffers[i].Buffer;		return Buffers[i].Buffer;
	}		}
	unsigned getNumBuffers() const {		size_t getNumBuffers() const {
	return Buffers.size();		return Buffers.size();
	}		}
	SMLoc getParentIncludeLoc(unsigned i) const {		SMLoc getParentIncludeLoc(unsigned i) const {
	assert(i < Buffers.size() && "Invalid Buffer ID!");		assert(i < Buffers.size() && "Invalid Buffer ID!");
	return Buffers[i].IncludeLoc;		return Buffers[i].IncludeLoc;
	}		}
	/// AddNewSourceBuffer - Add a new source buffer to this source manager. This		/// AddNewSourceBuffer - Add a new source buffer to this source manager. This
	/// takes ownership of the memory buffer.		/// takes ownership of the memory buffer.
	unsigned AddNewSourceBuffer(MemoryBuffer *F, SMLoc IncludeLoc) {		size_t AddNewSourceBuffer(MemoryBuffer *F, SMLoc IncludeLoc) {
	SrcBuffer NB;		SrcBuffer NB;
	NB.Buffer = F;		NB.Buffer = F;
	NB.IncludeLoc = IncludeLoc;		NB.IncludeLoc = IncludeLoc;
	Buffers.push_back(NB);		Buffers.push_back(NB);
	return Buffers.size()-1;		return Buffers.size() - 1;
	}		}
	/// AddIncludeFile - Search for a file with the specified name in the cur rent		/// AddIncludeFile - Search for a file with the specified name in the cur rent
	/// directory or in one of the IncludeDirs. If no file is found, this re turns		/// directory or in one of the IncludeDirs. If no file is found, this re turns
	/// ~0, otherwise it returns the buffer ID of the stacked file.		/// ~0, otherwise it returns the buffer ID of the stacked file.
	/// The full path to the included file can be found in IncludedFile.		/// The full path to the included file can be found in IncludedFile.
	unsigned AddIncludeFile(const std::string &Filename, SMLoc IncludeLoc,		size_t AddIncludeFile(const std::string &Filename, SMLoc IncludeLoc,
	std::string &IncludedFile);		std::string &IncludedFile);
	/// FindBufferContainingLoc - Return the ID of the buffer containing the		/// FindBufferContainingLoc - Return the ID of the buffer containing the
	/// specified location, returning -1 if not found.		/// specified location, returning -1 if not found.
	int FindBufferContainingLoc(SMLoc Loc) const;		int FindBufferContainingLoc(SMLoc Loc) const;
	/// FindLineNumber - Find the line number for the specified location in t he		/// FindLineNumber - Find the line number for the specified location in t he
	/// specified file. This is not a fast method.		/// specified file. This is not a fast method.
	unsigned FindLineNumber(SMLoc Loc, int BufferID = -1) const {		unsigned FindLineNumber(SMLoc Loc, int BufferID = -1) const {
	return getLineAndColumn(Loc, BufferID).first;		return getLineAndColumn(Loc, BufferID).first;
	}		}
	skipping to change at line 147		skipping to change at line 147
	/// getLineAndColumn - Find the line and column number for the specified		/// getLineAndColumn - Find the line and column number for the specified
	/// location in the specified file. This is not a fast method.		/// location in the specified file. This is not a fast method.
	std::pair<unsigned, unsigned>		std::pair<unsigned, unsigned>
	getLineAndColumn(SMLoc Loc, int BufferID = -1) const;		getLineAndColumn(SMLoc Loc, int BufferID = -1) const;
	/// PrintMessage - Emit a message about the specified location with the		/// PrintMessage - Emit a message about the specified location with the
	/// specified string.		/// specified string.
	///		///
	/// @param ShowColors - Display colored messages if output is a terminal and		/// @param ShowColors - Display colored messages if output is a terminal and
	/// the default error handler is used.		/// the default error handler is used.
			void PrintMessage(raw_ostream &OS, SMLoc Loc, DiagKind Kind,
			const Twine &Msg,
			ArrayRef<SMRange> Ranges = None,
			ArrayRef<SMFixIt> FixIts = None,
			bool ShowColors = true) const;
			/// Emits a diagnostic to llvm::errs().
	void PrintMessage(SMLoc Loc, DiagKind Kind, const Twine &Msg,		void PrintMessage(SMLoc Loc, DiagKind Kind, const Twine &Msg,
	ArrayRef<SMRange> Ranges = None,		ArrayRef<SMRange> Ranges = None,
	ArrayRef<SMFixIt> FixIts = None,		ArrayRef<SMFixIt> FixIts = None,
	bool ShowColors = true) const;		bool ShowColors = true) const;
	/// GetMessage - Return an SMDiagnostic at the specified location with th e		/// GetMessage - Return an SMDiagnostic at the specified location with th e
	/// specified string.		/// specified string.
	///		///
	/// @param Msg If non-null, the kind of message (e.g., "error") which is		/// @param Msg If non-null, the kind of message (e.g., "error") which is
	/// prefixed to the message.		/// prefixed to the message.
End of changes. 5 change blocks.
	5 lines changed or deleted		12 lines changed or added

	SparseBitVector.h		SparseBitVector.h
	skipping to change at line 139		skipping to change at line 139
	else		else
	llvm_unreachable("Unsupported!");		llvm_unreachable("Unsupported!");
	return NumBits;		return NumBits;
	}		}
	/// find_first - Returns the index of the first set bit.		/// find_first - Returns the index of the first set bit.
	int find_first() const {		int find_first() const {
	for (unsigned i = 0; i < BITWORDS_PER_ELEMENT; ++i)		for (unsigned i = 0; i < BITWORDS_PER_ELEMENT; ++i)
	if (Bits[i] != 0) {		if (Bits[i] != 0) {
	if (sizeof(BitWord) == 4)		if (sizeof(BitWord) == 4)
	return i * BITWORD_SIZE + CountTrailingZeros_32(Bits[i]);		return i * BITWORD_SIZE + countTrailingZeros(Bits[i]);
	if (sizeof(BitWord) == 8)		if (sizeof(BitWord) == 8)
	return i * BITWORD_SIZE + CountTrailingZeros_64(Bits[i]);		return i * BITWORD_SIZE + countTrailingZeros(Bits[i]);
	llvm_unreachable("Unsupported!");		llvm_unreachable("Unsupported!");
	}		}
	llvm_unreachable("Illegal empty element");		llvm_unreachable("Illegal empty element");
	}		}
	/// find_next - Returns the index of the next set bit starting from the		/// find_next - Returns the index of the next set bit starting from the
	/// "Curr" bit. Returns -1 if the next set bit is not found.		/// "Curr" bit. Returns -1 if the next set bit is not found.
	int find_next(unsigned Curr) const {		int find_next(unsigned Curr) const {
	if (Curr >= BITS_PER_ELEMENT)		if (Curr >= BITS_PER_ELEMENT)
	return -1;		return -1;
	skipping to change at line 164		skipping to change at line 164
	unsigned BitPos = Curr % BITWORD_SIZE;		unsigned BitPos = Curr % BITWORD_SIZE;
	BitWord Copy = Bits[WordPos];		BitWord Copy = Bits[WordPos];
	assert (WordPos <= BITWORDS_PER_ELEMENT		assert (WordPos <= BITWORDS_PER_ELEMENT
	&& "Word Position outside of element");		&& "Word Position outside of element");
	// Mask off previous bits.		// Mask off previous bits.
	Copy &= ~0UL << BitPos;		Copy &= ~0UL << BitPos;
	if (Copy != 0) {		if (Copy != 0) {
	if (sizeof(BitWord) == 4)		if (sizeof(BitWord) == 4)
	return WordPos * BITWORD_SIZE + CountTrailingZeros_32(Copy);		return WordPos * BITWORD_SIZE + countTrailingZeros(Copy);
	if (sizeof(BitWord) == 8)		if (sizeof(BitWord) == 8)
	return WordPos * BITWORD_SIZE + CountTrailingZeros_64(Copy);		return WordPos * BITWORD_SIZE + countTrailingZeros(Copy);
	llvm_unreachable("Unsupported!");		llvm_unreachable("Unsupported!");
	}		}
	// Check subsequent words.		// Check subsequent words.
	for (unsigned i = WordPos+1; i < BITWORDS_PER_ELEMENT; ++i)		for (unsigned i = WordPos+1; i < BITWORDS_PER_ELEMENT; ++i)
	if (Bits[i] != 0) {		if (Bits[i] != 0) {
	if (sizeof(BitWord) == 4)		if (sizeof(BitWord) == 4)
	return i * BITWORD_SIZE + CountTrailingZeros_32(Bits[i]);		return i * BITWORD_SIZE + countTrailingZeros(Bits[i]);
	if (sizeof(BitWord) == 8)		if (sizeof(BitWord) == 8)
	return i * BITWORD_SIZE + CountTrailingZeros_64(Bits[i]);		return i * BITWORD_SIZE + countTrailingZeros(Bits[i]);
	llvm_unreachable("Unsupported!");		llvm_unreachable("Unsupported!");
	}		}
	return -1;		return -1;
	}		}
	// Union this element with RHS and return true if this one changed.		// Union this element with RHS and return true if this one changed.
	bool unionWith(const SparseBitVectorElement &RHS) {		bool unionWith(const SparseBitVectorElement &RHS) {
	bool changed = false;		bool changed = false;
	for (unsigned i = 0; i < BITWORDS_PER_ELEMENT; ++i) {		for (unsigned i = 0; i < BITWORDS_PER_ELEMENT; ++i) {
	BitWord old = changed ? 0 : Bits[i];		BitWord old = changed ? 0 : Bits[i];
End of changes. 6 change blocks.
	6 lines changed or deleted		6 lines changed or added

	StreamableMemoryObject.h		StreamableMemoryObject.h
	skipping to change at line 40		skipping to change at line 40
	/// used to test addresses without knowing the exact size of the stream.		/// used to test addresses without knowing the exact size of the stream.
	/// Finally, getPointer can be used instead of readBytes to avoid extra cop ying.		/// Finally, getPointer can be used instead of readBytes to avoid extra cop ying.
	class StreamableMemoryObject : public MemoryObject {		class StreamableMemoryObject : public MemoryObject {
	public:		public:
	/// Destructor - Override as necessary.		/// Destructor - Override as necessary.
	virtual ~StreamableMemoryObject();		virtual ~StreamableMemoryObject();
	/// getBase - Returns the lowest valid address in the region.		/// getBase - Returns the lowest valid address in the region.
	///		///
	/// @result - The lowest valid address.		/// @result - The lowest valid address.
	virtual uint64_t getBase() const = 0;		virtual uint64_t getBase() const LLVM_OVERRIDE = 0;
	/// getExtent - Returns the size of the region in bytes. (The regi on is		/// getExtent - Returns the size of the region in bytes. (The regi on is
	/// contiguous, so the highest valid address of the reg ion		/// contiguous, so the highest valid address of the reg ion
	/// is getBase() + getExtent() - 1).		/// is getBase() + getExtent() - 1).
	/// May block until all bytes in the stream have been r ead		/// May block until all bytes in the stream have been r ead
	///		///
	/// @result - The size of the region.		/// @result - The size of the region.
	virtual uint64_t getExtent() const = 0;		virtual uint64_t getExtent() const LLVM_OVERRIDE = 0;
	/// readByte - Tries to read a single byte from the region.		/// readByte - Tries to read a single byte from the region.
	/// May block until (address - base) bytes have been re ad		/// May block until (address - base) bytes have been re ad
	/// @param address - The address of the byte, in the same space as getBa se().		/// @param address - The address of the byte, in the same space as getBa se().
	/// @param ptr - A pointer to a byte to be filled in. Must be non-N ULL.		/// @param ptr - A pointer to a byte to be filled in. Must be non-N ULL.
	/// @result - 0 if successful; -1 if not. Failure may be due to a		/// @result - 0 if successful; -1 if not. Failure may be due to a
	/// bounds violation or an implementation-specific erro r.		/// bounds violation or an implementation-specific erro r.
	virtual int readByte(uint64_t address, uint8_t* ptr) const = 0;		virtual int readByte(uint64_t address, uint8_t *ptr) const LLVM_OVERRIDE = 0;
	/// readBytes - Tries to read a contiguous range of bytes from the		/// readBytes - Tries to read a contiguous range of bytes from the
	/// region, up to the end of the region.		/// region, up to the end of the region.
	/// May block until (address - base + size) bytes have		/// May block until (address - base + size) bytes have
	/// been read. Additionally, StreamableMemoryObjects wi ll		/// been read. Additionally, StreamableMemoryObjects wi ll
	/// not do partial reads - if size bytes cannot be read ,		/// not do partial reads - if size bytes cannot be read ,
	/// readBytes will fail.		/// readBytes will fail.
	///		///
	/// @param address - The address of the first byte, in the same space as		/// @param address - The address of the first byte, in the same space as
	/// getBase().		/// getBase().
	/// @param size - The maximum number of bytes to copy.		/// @param size - The number of bytes to copy.
	/// @param buf - A pointer to a buffer to be filled in. Must be non -NULL		/// @param buf - A pointer to a buffer to be filled in. Must be non -NULL
	/// and large enough to hold size bytes.		/// and large enough to hold size bytes.
	/// @param copied - A pointer to a nunber that is filled in with the nu
	mber
	/// of bytes actually read. May be NULL.
	/// @result - 0 if successful; -1 if not. Failure may be due to a		/// @result - 0 if successful; -1 if not. Failure may be due to a
	/// bounds violation or an implementation-specific erro r.		/// bounds violation or an implementation-specific erro r.
	virtual int readBytes(uint64_t address,		virtual int readBytes(uint64_t address,
	uint64_t size,		uint64_t size,
	uint8_t* buf,		uint8_t *buf) const LLVM_OVERRIDE = 0;
	uint64_t* copied) const = 0;
	/// getPointer - Ensures that the requested data is in memory, and retur ns		/// getPointer - Ensures that the requested data is in memory, and retur ns
	/// A pointer to it. More efficient than using readBytes if the		/// A pointer to it. More efficient than using readBytes if the
	/// data is already in memory.		/// data is already in memory.
	/// May block until (address - base + size) bytes have been read		/// May block until (address - base + size) bytes have been read
	/// @param address - address of the byte, in the same space as getBase()		/// @param address - address of the byte, in the same space as getBase()
	/// @param size - amount of data that must be available on return		/// @param size - amount of data that must be available on return
	/// @result - valid pointer to the requested data		/// @result - valid pointer to the requested data
	virtual const uint8_t *getPointer(uint64_t address, uint64_t size) const = 0;		virtual const uint8_t *getPointer(uint64_t address, uint64_t size) const = 0;
	skipping to change at line 112		skipping to change at line 109
	/// StreamingMemoryObject - interface to data which is actually streamed fr om		/// StreamingMemoryObject - interface to data which is actually streamed fr om
	/// a DataStreamer. In addition to inherited members, it has the		/// a DataStreamer. In addition to inherited members, it has the
	/// dropLeadingBytes and setKnownObjectSize methods which are not applicabl e		/// dropLeadingBytes and setKnownObjectSize methods which are not applicabl e
	/// to non-streamed objects.		/// to non-streamed objects.
	class StreamingMemoryObject : public StreamableMemoryObject {		class StreamingMemoryObject : public StreamableMemoryObject {
	public:		public:
	StreamingMemoryObject(DataStreamer *streamer);		StreamingMemoryObject(DataStreamer *streamer);
	virtual uint64_t getBase() const LLVM_OVERRIDE { return 0; }		virtual uint64_t getBase() const LLVM_OVERRIDE { return 0; }
	virtual uint64_t getExtent() const LLVM_OVERRIDE;		virtual uint64_t getExtent() const LLVM_OVERRIDE;
	virtual int readByte(uint64_t address, uint8_t* ptr) const LLVM_OVERRIDE;		virtual int readByte(uint64_t address, uint8_t *ptr) const LLVM_OVERRIDE;
	virtual int readBytes(uint64_t address,		virtual int readBytes(uint64_t address,
	uint64_t size,		uint64_t size,
	uint8_t* buf,		uint8_t *buf) const LLVM_OVERRIDE;
	uint64_t* copied) const LLVM_OVERRIDE;
	virtual const uint8_t *getPointer(uint64_t address,		virtual const uint8_t *getPointer(uint64_t address,
	uint64_t size) const LLVM_OVERRIDE {		uint64_t size) const LLVM_OVERRIDE {
	// This could be fixed by ensuring the bytes are fetched and making a c opy,		// This could be fixed by ensuring the bytes are fetched and making a c opy,
	// requiring that the bitcode size be known, or otherwise ensuring that		// requiring that the bitcode size be known, or otherwise ensuring that
	// the memory doesn't go away/get reallocated, but it's		// the memory doesn't go away/get reallocated, but it's
	// not currently necessary. Users that need the pointer don't stream.		// not currently necessary. Users that need the pointer don't stream.
	assert(0 && "getPointer in streaming memory objects not allowed");		assert(0 && "getPointer in streaming memory objects not allowed");
	return NULL;		return NULL;
	}		}
	virtual bool isValidAddress(uint64_t address) const LLVM_OVERRIDE;		virtual bool isValidAddress(uint64_t address) const LLVM_OVERRIDE;
End of changes. 8 change blocks.
	12 lines changed or deleted		7 lines changed or added

	StringExtras.h		StringExtras.h
	skipping to change at line 17		skipping to change at line 17
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// This file contains some functions that are useful when dealing with stri ngs.		// This file contains some functions that are useful when dealing with stri ngs.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_ADT_STRINGEXTRAS_H		#ifndef LLVM_ADT_STRINGEXTRAS_H
	#define LLVM_ADT_STRINGEXTRAS_H		#define LLVM_ADT_STRINGEXTRAS_H
			#include <iterator>
	#include "llvm/ADT/StringRef.h"		#include "llvm/ADT/StringRef.h"
	#include "llvm/Support/DataTypes.h"		#include "llvm/Support/DataTypes.h"
	namespace llvm {		namespace llvm {
	template<typename T> class SmallVectorImpl;		template<typename T> class SmallVectorImpl;
	/// hexdigit - Return the hexadecimal character for the		/// hexdigit - Return the hexadecimal character for the
	/// given number \p X (which should be less than 16).		/// given number \p X (which should be less than 16).
	static inline char hexdigit(unsigned X, bool LowerCase = false) {		static inline char hexdigit(unsigned X, bool LowerCase = false) {
	const char HexChar = LowerCase ? 'a' : 'A';		const char HexChar = LowerCase ? 'a' : 'A';
	skipping to change at line 161		skipping to change at line 162
	default:		default:
	switch (Val % 10) {		switch (Val % 10) {
	case 1: return "st";		case 1: return "st";
	case 2: return "nd";		case 2: return "nd";
	case 3: return "rd";		case 3: return "rd";
	default: return "th";		default: return "th";
	}		}
	}		}
	}		}
			template <typename IteratorT>
			inline std::string join_impl(IteratorT Begin, IteratorT End,
			StringRef Separator, std::input_iterator_tag)
			{
			std::string S;
			if (Begin == End)
			return S;
			S += (*Begin);
			while (++Begin != End) {
			S += Separator;
			S += (*Begin);
			}
			return S;
			}
			template <typename IteratorT>
			inline std::string join_impl(IteratorT Begin, IteratorT End,
			StringRef Separator, std::forward_iterator_tag
			) {
			std::string S;
			if (Begin == End)
			return S;
			size_t Len = (std::distance(Begin, End) - 1) * Separator.size();
			for (IteratorT I = Begin; I != End; ++I)
			Len += (*Begin).size();
			S.reserve(Len);
			S += (*Begin);
			while (++Begin != End) {
			S += Separator;
			S += (*Begin);
			}
			return S;
			}
			/// Joins the strings in the range [Begin, End), adding Separator between
			/// the elements.
			template <typename IteratorT>
			inline std::string join(IteratorT Begin, IteratorT End, StringRef Separator
			) {
			typedef typename std::iterator_traits<IteratorT>::iterator_category tag;
			return join_impl(Begin, End, Separator, tag());
			}
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 2 change blocks.
	0 lines changed or deleted		46 lines changed or added

	StringMap.h		StringMap.h
	skipping to change at line 104		skipping to change at line 104
	public:		public:
	static StringMapEntryBase *getTombstoneVal() {		static StringMapEntryBase *getTombstoneVal() {
	return (StringMapEntryBase*)-1;		return (StringMapEntryBase*)-1;
	}		}
	unsigned getNumBuckets() const { return NumBuckets; }		unsigned getNumBuckets() const { return NumBuckets; }
	unsigned getNumItems() const { return NumItems; }		unsigned getNumItems() const { return NumItems; }
	bool empty() const { return NumItems == 0; }		bool empty() const { return NumItems == 0; }
	unsigned size() const { return NumItems; }		unsigned size() const { return NumItems; }
			void swap(StringMapImpl &Other) {
			std::swap(TheTable, Other.TheTable);
			std::swap(NumBuckets, Other.NumBuckets);
			std::swap(NumItems, Other.NumItems);
			std::swap(NumTombstones, Other.NumTombstones);
			}
	};		};
	/// StringMapEntry - This is used to represent one value that is inserted i nto		/// StringMapEntry - This is used to represent one value that is inserted i nto
	/// a StringMap. It contains the Value itself and the key: the string leng th		/// a StringMap. It contains the Value itself and the key: the string leng th
	/// and data.		/// and data.
	template<typename ValueTy>		template<typename ValueTy>
	class StringMapEntry : public StringMapEntryBase {		class StringMapEntry : public StringMapEntryBase {
			StringMapEntry(StringMapEntry &E) LLVM_DELETED_FUNCTION;
	public:		public:
	ValueTy second;		ValueTy second;
	explicit StringMapEntry(unsigned strLen)		explicit StringMapEntry(unsigned strLen)
	: StringMapEntryBase(strLen), second() {}		: StringMapEntryBase(strLen), second() {}
	StringMapEntry(unsigned strLen, const ValueTy &V)		StringMapEntry(unsigned strLen, const ValueTy &V)
	: StringMapEntryBase(strLen), second(V) {}		: StringMapEntryBase(strLen), second(V) {}
	StringRef getKey() const {		StringRef getKey() const {
	return StringRef(getKeyData(), getKeyLength());		return StringRef(getKeyData(), getKeyLength());
	skipping to change at line 409		skipping to change at line 417
	}		}
	};		};
	template<typename ValueTy>		template<typename ValueTy>
	class StringMapConstIterator {		class StringMapConstIterator {
	protected:		protected:
	StringMapEntryBase **Ptr;		StringMapEntryBase **Ptr;
	public:		public:
	typedef StringMapEntry<ValueTy> value_type;		typedef StringMapEntry<ValueTy> value_type;
			StringMapConstIterator() : Ptr(0) { }
	explicit StringMapConstIterator(StringMapEntryBase **Bucket,		explicit StringMapConstIterator(StringMapEntryBase **Bucket,
	bool NoAdvance = false)		bool NoAdvance = false)
	: Ptr(Bucket) {		: Ptr(Bucket) {
	if (!NoAdvance) AdvancePastEmptyBuckets();		if (!NoAdvance) AdvancePastEmptyBuckets();
	}		}
	const value_type &operator*() const {		const value_type &operator*() const {
	return *static_cast<StringMapEntry<ValueTy>*>(*Ptr);		return *static_cast<StringMapEntry<ValueTy>*>(*Ptr);
	}		}
	const value_type *operator->() const {		const value_type *operator->() const {
	skipping to change at line 448		skipping to change at line 458
	private:		private:
	void AdvancePastEmptyBuckets() {		void AdvancePastEmptyBuckets() {
	while (*Ptr == 0 || *Ptr == StringMapImpl::getTombstoneVal())		while (*Ptr == 0 || *Ptr == StringMapImpl::getTombstoneVal())
	++Ptr;		++Ptr;
	}		}
	};		};
	template<typename ValueTy>		template<typename ValueTy>
	class StringMapIterator : public StringMapConstIterator<ValueTy> {		class StringMapIterator : public StringMapConstIterator<ValueTy> {
	public:		public:
			StringMapIterator() {}
	explicit StringMapIterator(StringMapEntryBase **Bucket,		explicit StringMapIterator(StringMapEntryBase **Bucket,
	bool NoAdvance = false)		bool NoAdvance = false)
	: StringMapConstIterator<ValueTy>(Bucket, NoAdvance) {		: StringMapConstIterator<ValueTy>(Bucket, NoAdvance) {
	}		}
	StringMapEntry<ValueTy> &operator*() const {		StringMapEntry<ValueTy> &operator*() const {
	return *static_cast<StringMapEntry<ValueTy>*>(*this->Ptr);		return *static_cast<StringMapEntry<ValueTy>*>(*this->Ptr);
	}		}
	StringMapEntry<ValueTy> *operator->() const {		StringMapEntry<ValueTy> *operator->() const {
	return static_cast<StringMapEntry<ValueTy>*>(*this->Ptr);		return static_cast<StringMapEntry<ValueTy>*>(*this->Ptr);
	}		}
End of changes. 4 change blocks.
	0 lines changed or deleted		11 lines changed or added

	StringRef.h		StringRef.h
	skipping to change at line 22		skipping to change at line 22
	#include "llvm/Support/type_traits.h"		#include "llvm/Support/type_traits.h"
	#include <algorithm>		#include <algorithm>
	#include <cassert>		#include <cassert>
	#include <cstring>		#include <cstring>
	#include <limits>		#include <limits>
	#include <string>		#include <string>
	#include <utility>		#include <utility>
	namespace llvm {		namespace llvm {
	template<typename T>		template <typename T>
	class SmallVectorImpl;		class SmallVectorImpl;
	class APInt;		class APInt;
	class hash_code;		class hash_code;
	class StringRef;		class StringRef;
	/// Helper functions for StringRef::getAsInteger.		/// Helper functions for StringRef::getAsInteger.
	bool getAsUnsignedInteger(StringRef Str, unsigned Radix,		bool getAsUnsignedInteger(StringRef Str, unsigned Radix,
	unsigned long long &Result);		unsigned long long &Result);
	bool getAsSignedInteger(StringRef Str, unsigned Radix, long long &Result) ;		bool getAsSignedInteger(StringRef Str, unsigned Radix, long long &Result) ;
	skipping to change at line 178		skipping to change at line 178
	///		///
	/// \param MaxEditDistance If non-zero, the maximum edit distance that		/// \param MaxEditDistance If non-zero, the maximum edit distance that
	/// this routine is allowed to compute. If the edit distance will excee d		/// this routine is allowed to compute. If the edit distance will excee d
	/// that maximum, returns \c MaxEditDistance+1.		/// that maximum, returns \c MaxEditDistance+1.
	///		///
	/// \returns the minimum number of character insertions, removals,		/// \returns the minimum number of character insertions, removals,
	/// or (if \p AllowReplacements is \c true) replacements needed to		/// or (if \p AllowReplacements is \c true) replacements needed to
	/// transform one of the given strings into the other. If zero,		/// transform one of the given strings into the other. If zero,
	/// the strings are identical.		/// the strings are identical.
	unsigned edit_distance(StringRef Other, bool AllowReplacements = true,		unsigned edit_distance(StringRef Other, bool AllowReplacements = true,
	unsigned MaxEditDistance = 0);		unsigned MaxEditDistance = 0) const;
	/// str - Get the contents as an std::string.		/// str - Get the contents as an std::string.
	std::string str() const {		std::string str() const {
	if (Data == 0) return std::string();		if (Data == 0) return std::string();
	return std::string(Data, Length);		return std::string(Data, Length);
	}		}
	/// @}		/// @}
	/// @name Operator Overloads		/// @name Operator Overloads
	/// @{		/// @{
	skipping to change at line 213		skipping to change at line 213
	/// @}		/// @}
	/// @name String Predicates		/// @name String Predicates
	/// @{		/// @{
	/// Check if this string starts with the given \p Prefix.		/// Check if this string starts with the given \p Prefix.
	bool startswith(StringRef Prefix) const {		bool startswith(StringRef Prefix) const {
	return Length >= Prefix.Length &&		return Length >= Prefix.Length &&
	compareMemory(Data, Prefix.Data, Prefix.Length) == 0;		compareMemory(Data, Prefix.Data, Prefix.Length) == 0;
	}		}
			/// Check if this string starts with the given \p Prefix, ignoring case
			.
			bool startswith_lower(StringRef Prefix) const;
	/// Check if this string ends with the given \p Suffix.		/// Check if this string ends with the given \p Suffix.
	bool endswith(StringRef Suffix) const {		bool endswith(StringRef Suffix) const {
	return Length >= Suffix.Length &&		return Length >= Suffix.Length &&
	compareMemory(end() - Suffix.Length, Suffix.Data, Suffix.Length) == 0;		compareMemory(end() - Suffix.Length, Suffix.Data, Suffix.Length) == 0;
	}		}
			/// Check if this string ends with the given \p Suffix, ignoring case.
			bool endswith_lower(StringRef Suffix) const;
	/// @}		/// @}
	/// @name String Searching		/// @name String Searching
	/// @{		/// @{
	/// Search for the first character \p C in the string.		/// Search for the first character \p C in the string.
	///		///
	/// \returns The index of the first occurrence of \p C, or npos if not		/// \returns The index of the first occurrence of \p C, or npos if not
	/// found.		/// found.
	size_t find(char C, size_t From = 0) const {		size_t find(char C, size_t From = 0) const {
	for (size_t i = min(From, Length), e = Length; i != e; ++i)		for (size_t i = min(From, Length), e = Length; i != e; ++i)
	skipping to change at line 551		skipping to change at line 557
	/// @}		/// @}
	/// \brief Compute a hash_code for a StringRef.		/// \brief Compute a hash_code for a StringRef.
	hash_code hash_value(StringRef S);		hash_code hash_value(StringRef S);
	// StringRefs can be treated like a POD type.		// StringRefs can be treated like a POD type.
	template <typename T> struct isPodLike;		template <typename T> struct isPodLike;
	template <> struct isPodLike<StringRef> { static const bool value = true; };		template <> struct isPodLike<StringRef> { static const bool value = true; };
			/// Construct a string ref from a boolean.
			inline StringRef toStringRef(bool B) {
			return StringRef(B ? "true" : "false");
			}
	}		}
	#endif		#endif
End of changes. 5 change blocks.
	2 lines changed or deleted		13 lines changed or added

	SubtargetFeature.h		SubtargetFeature.h
	skipping to change at line 40		skipping to change at line 40
	///		///
	/// SubtargetFeatureKV - Used to provide key value pairs for feature and		/// SubtargetFeatureKV - Used to provide key value pairs for feature and
	/// CPU bit flags.		/// CPU bit flags.
	//		//
	struct SubtargetFeatureKV {		struct SubtargetFeatureKV {
	const char *Key; // K-V key string		const char *Key; // K-V key string
	const char *Desc; // Help descriptor		const char *Desc; // Help descriptor
	uint64_t Value; // K-V integer value		uint64_t Value; // K-V integer value
	uint64_t Implies; // K-V bit mask		uint64_t Implies; // K-V bit mask
	// Compare routine for std binary search		// Compare routine for std::lower_bound
	bool operator<(const SubtargetFeatureKV &S) const {		bool operator<(StringRef S) const {
	return strcmp(Key, S.Key) < 0;		return StringRef(Key) < S;
	}		}
	};		};
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	///		///
	/// SubtargetInfoKV - Used to provide key value pairs for CPU and arbitrary		/// SubtargetInfoKV - Used to provide key value pairs for CPU and arbitrary
	/// pointers.		/// pointers.
	//		//
	struct SubtargetInfoKV {		struct SubtargetInfoKV {
	const char *Key; // K-V key string		const char *Key; // K-V key string
	const void *Value; // K-V pointer value		const void *Value; // K-V pointer value
	// Compare routine for std binary search		// Compare routine for std::lower_bound
	bool operator<(const SubtargetInfoKV &S) const {		bool operator<(StringRef S) const {
	return strcmp(Key, S.Key) < 0;		return StringRef(Key) < S;
	}		}
	};		};
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	///		///
	/// SubtargetFeatures - Manages the enabling and disabling of subtarget		/// SubtargetFeatures - Manages the enabling and disabling of subtarget
	/// specific features. Features are encoded as a string of the form		/// specific features. Features are encoded as a string of the form
	/// "+attr1,+attr2,-attr3,...,+attrN"		/// "+attr1,+attr2,-attr3,...,+attrN"
	/// A comma separates each feature from the next (all lowercase.)		/// A comma separates each feature from the next (all lowercase.)
	/// Each of the remaining features is prefixed with + or - indicating wheth er		/// Each of the remaining features is prefixed with + or - indicating wheth er
	skipping to change at line 102		skipping to change at line 102
	size_t CPUTableSize,		size_t CPUTableSize,
	const SubtargetFeatureKV *FeatureTable,		const SubtargetFeatureKV *FeatureTable,
	size_t FeatureTableSize);		size_t FeatureTableSize);
	/// Print feature string.		/// Print feature string.
	void print(raw_ostream &OS) const;		void print(raw_ostream &OS) const;
	// Dump feature info.		// Dump feature info.
	void dump() const;		void dump() const;
	/// Retrieve a formatted string of the default features for the specified		/// Adds the default features for the specified target triple.
	/// target triple.
	void getDefaultSubtargetFeatures(const Triple& Triple);		void getDefaultSubtargetFeatures(const Triple& Triple);
	};		};
	} // End namespace llvm		} // End namespace llvm
	#endif		#endif
End of changes. 3 change blocks.
	8 lines changed or deleted		7 lines changed or added

	SystemUtils.h		SystemUtils.h
	skipping to change at line 22		skipping to change at line 22
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_SUPPORT_SYSTEMUTILS_H		#ifndef LLVM_SUPPORT_SYSTEMUTILS_H
	#define LLVM_SUPPORT_SYSTEMUTILS_H		#define LLVM_SUPPORT_SYSTEMUTILS_H
	#include <string>		#include <string>
	namespace llvm {		namespace llvm {
	class raw_ostream;		class raw_ostream;
	namespace sys { class Path; }
	/// Determine if the raw_ostream provided is connected to a terminal. If so ,		/// Determine if the raw_ostream provided is connected to a terminal. If so ,
	/// generate a warning message to errs() advising against display of bitcod e		/// generate a warning message to errs() advising against display of bitcod e
	/// and return true. Otherwise just return false.		/// and return true. Otherwise just return false.
	/// @brief Check for output written to a console		/// @brief Check for output written to a console
	bool CheckBitcodeOutputToConsole(		bool CheckBitcodeOutputToConsole(
	raw_ostream &stream_to_check, ///< The stream to be checked		raw_ostream &stream_to_check, ///< The stream to be checked
	bool print_warning = true ///< Control whether warnings are printed		bool print_warning = true ///< Control whether warnings are printed
	);		);
	/// PrependMainExecutablePath - Prepend the path to the program being execu
	ted
	/// to \p ExeName, given the value of argv[0] and the address of main()
	/// itself. This allows us to find another LLVM tool if it is built in the
	same
	/// directory. An empty string is returned on error; note that this functio
	n
	/// just mainpulates the path and doesn't check for executability.
	/// @brief Find a named executable.
	sys::Path PrependMainExecutablePath(const std::string &ExeName,
	const char *Argv0, void *MainAddr);
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 2 change blocks.
	13 lines changed or deleted		0 lines changed or added

	TableGenBackend.h		TableGenBackend.h
	skipping to change at line 23		skipping to change at line 23
	#ifndef LLVM_TABLEGEN_TABLEGENBACKEND_H		#ifndef LLVM_TABLEGEN_TABLEGENBACKEND_H
	#define LLVM_TABLEGEN_TABLEGENBACKEND_H		#define LLVM_TABLEGEN_TABLEGENBACKEND_H
	#include "llvm/ADT/StringRef.h"		#include "llvm/ADT/StringRef.h"
	namespace llvm {		namespace llvm {
	class raw_ostream;		class raw_ostream;
	/// emitSourceFileHeader - Output a LLVM style file header to the specified		/// emitSourceFileHeader - Output an LLVM style file header to the specifie d
	/// raw_ostream.		/// raw_ostream.
	void emitSourceFileHeader(StringRef Desc, raw_ostream &OS);		void emitSourceFileHeader(StringRef Desc, raw_ostream &OS);
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 1 change blocks.
	1 lines changed or deleted		1 lines changed or added

	Target.h		Target.h
	skipping to change at line 25		skipping to change at line 25
	/* tools written in such languages. */		/* tools written in such languages. */
	/* */		/* */
	/*===---------------------------------------------------------------------- ===*/		/*===---------------------------------------------------------------------- ===*/
	#ifndef LLVM_C_TARGET_H		#ifndef LLVM_C_TARGET_H
	#define LLVM_C_TARGET_H		#define LLVM_C_TARGET_H
	#include "llvm-c/Core.h"		#include "llvm-c/Core.h"
	#include "llvm/Config/llvm-config.h"		#include "llvm/Config/llvm-config.h"
			#if defined(_MSC_VER) && !defined(inline)
			#define inline __inline
			#endif
	#ifdef __cplusplus		#ifdef __cplusplus
	extern "C" {		extern "C" {
	#endif		#endif
	/**		/**
	* @defgroup LLVMCTarget Target information		* @defgroup LLVMCTarget Target information
	* @ingroup LLVMC		* @ingroup LLVMC
	*		*
	* @{		* @{
	*/		*/
	enum LLVMByteOrdering { LLVMBigEndian, LLVMLittleEndian };		enum LLVMByteOrdering { LLVMBigEndian, LLVMLittleEndian };
	typedef struct LLVMOpaqueTargetData *LLVMTargetDataRef;		typedef struct LLVMOpaqueTargetData *LLVMTargetDataRef;
	typedef struct LLVMOpaqueTargetLibraryInfotData *LLVMTargetLibraryInfoRef;		typedef struct LLVMOpaqueTargetLibraryInfotData *LLVMTargetLibraryInfoRef;
	typedef struct LLVMStructLayout *LLVMStructLayoutRef;
	/* Declare all of the target-initialization functions that are available. * /		/* Declare all of the target-initialization functions that are available. * /
	#define LLVM_TARGET(TargetName) \		#define LLVM_TARGET(TargetName) \
	void LLVMInitialize##TargetName##TargetInfo(void);		void LLVMInitialize##TargetName##TargetInfo(void);
	#include "llvm/Config/Targets.def"		#include "llvm/Config/Targets.def"
	#undef LLVM_TARGET /* Explicit undef to make SWIG happier */		#undef LLVM_TARGET /* Explicit undef to make SWIG happier */
	#define LLVM_TARGET(TargetName) void LLVMInitialize##TargetName##Target(voi d);		#define LLVM_TARGET(TargetName) void LLVMInitialize##TargetName##Target(voi d);
	#include "llvm/Config/Targets.def"		#include "llvm/Config/Targets.def"
	#undef LLVM_TARGET /* Explicit undef to make SWIG happier */		#undef LLVM_TARGET /* Explicit undef to make SWIG happier */
	skipping to change at line 145		skipping to change at line 148
	#ifdef LLVM_NATIVE_TARGET		#ifdef LLVM_NATIVE_TARGET
	LLVM_NATIVE_TARGETINFO();		LLVM_NATIVE_TARGETINFO();
	LLVM_NATIVE_TARGET();		LLVM_NATIVE_TARGET();
	LLVM_NATIVE_TARGETMC();		LLVM_NATIVE_TARGETMC();
	return 0;		return 0;
	#else		#else
	return 1;		return 1;
	#endif		#endif
	}		}
			/** LLVMInitializeNativeTargetAsmParser - The main program should call this
			function to initialize the parser for the native target corresponding t
			o the
			host. */
			static inline LLVMBool LLVMInitializeNativeAsmParser(void) {
			#ifdef LLVM_NATIVE_ASMPARSER
			LLVM_NATIVE_ASMPARSER();
			return 0;
			#else
			return 1;
			#endif
			}
			/** LLVMInitializeNativeTargetAsmPrinter - The main program should call thi
			s
			function to initialize the printer for the native target corresponding
			to
			the host. */
			static inline LLVMBool LLVMInitializeNativeAsmPrinter(void) {
			#ifdef LLVM_NATIVE_ASMPRINTER
			LLVM_NATIVE_ASMPRINTER();
			return 0;
			#else
			return 1;
			#endif
			}
			/** LLVMInitializeNativeTargetDisassembler - The main program should call t
			his
			function to initialize the disassembler for the native target correspon
			ding
			to the host. */
			static inline LLVMBool LLVMInitializeNativeDisassembler(void) {
			#ifdef LLVM_NATIVE_DISASSEMBLER
			LLVM_NATIVE_DISASSEMBLER();
			return 0;
			#else
			return 1;
			#endif
			}
	/*===-- Target Data ------------------------------------------------------- ===*/		/*===-- Target Data ------------------------------------------------------- ===*/
	/** Creates target data from a target layout string.		/** Creates target data from a target layout string.
	See the constructor llvm::DataLayout::DataLayout. */		See the constructor llvm::DataLayout::DataLayout. */
	LLVMTargetDataRef LLVMCreateTargetData(const char *StringRep);		LLVMTargetDataRef LLVMCreateTargetData(const char *StringRep);
	/** Adds target data information to a pass manager. This does not take owne rship		/** Adds target data information to a pass manager. This does not take owne rship
	of the target data.		of the target data.
	See the method llvm::PassManagerBase::add. */		See the method llvm::PassManagerBase::add. */
	void LLVMAddTargetData(LLVMTargetDataRef, LLVMPassManagerRef);		void LLVMAddTargetData(LLVMTargetDataRef TD, LLVMPassManagerRef PM);
	/** Adds target library information to a pass manager. This does not take		/** Adds target library information to a pass manager. This does not take
	ownership of the target library info.		ownership of the target library info.
	See the method llvm::PassManagerBase::add. */		See the method llvm::PassManagerBase::add. */
	void LLVMAddTargetLibraryInfo(LLVMTargetLibraryInfoRef, LLVMPassManagerRef)		void LLVMAddTargetLibraryInfo(LLVMTargetLibraryInfoRef TLI,
	;		LLVMPassManagerRef PM);
	/** Converts target data to a target layout string. The string must be disp osed		/** Converts target data to a target layout string. The string must be disp osed
	with LLVMDisposeMessage.		with LLVMDisposeMessage.
	See the constructor llvm::DataLayout::DataLayout. */		See the constructor llvm::DataLayout::DataLayout. */
	char *LLVMCopyStringRepOfTargetData(LLVMTargetDataRef);		char *LLVMCopyStringRepOfTargetData(LLVMTargetDataRef TD);
	/** Returns the byte order of a target, either LLVMBigEndian or		/** Returns the byte order of a target, either LLVMBigEndian or
	LLVMLittleEndian.		LLVMLittleEndian.
	See the method llvm::DataLayout::isLittleEndian. */		See the method llvm::DataLayout::isLittleEndian. */
	enum LLVMByteOrdering LLVMByteOrder(LLVMTargetDataRef);		enum LLVMByteOrdering LLVMByteOrder(LLVMTargetDataRef TD);
	/** Returns the pointer size in bytes for a target.		/** Returns the pointer size in bytes for a target.
	See the method llvm::DataLayout::getPointerSize. */		See the method llvm::DataLayout::getPointerSize. */
	unsigned LLVMPointerSize(LLVMTargetDataRef);		unsigned LLVMPointerSize(LLVMTargetDataRef TD);
	/** Returns the pointer size in bytes for a target for a specified		/** Returns the pointer size in bytes for a target for a specified
	address space.		address space.
	See the method llvm::DataLayout::getPointerSize. */		See the method llvm::DataLayout::getPointerSize. */
	unsigned LLVMPointerSizeForAS(LLVMTargetDataRef, unsigned AS);		unsigned LLVMPointerSizeForAS(LLVMTargetDataRef TD, unsigned AS);
			/** Returns the integer type that is the same size as a pointer on a target
			.
			See the method llvm::DataLayout::getIntPtrType. */
			LLVMTypeRef LLVMIntPtrType(LLVMTargetDataRef TD);
			/** Returns the integer type that is the same size as a pointer on a target
			.
			This version allows the address space to be specified.
			See the method llvm::DataLayout::getIntPtrType. */
			LLVMTypeRef LLVMIntPtrTypeForAS(LLVMTargetDataRef TD, unsigned AS);
	/** Returns the integer type that is the same size as a pointer on a target .		/** Returns the integer type that is the same size as a pointer on a target .
	See the method llvm::DataLayout::getIntPtrType. */		See the method llvm::DataLayout::getIntPtrType. */
	LLVMTypeRef LLVMIntPtrType(LLVMTargetDataRef);		LLVMTypeRef LLVMIntPtrTypeInContext(LLVMContextRef C, LLVMTargetDataRef TD) ;
	/** Returns the integer type that is the same size as a pointer on a target .		/** Returns the integer type that is the same size as a pointer on a target .
	This version allows the address space to be specified.		This version allows the address space to be specified.
	See the method llvm::DataLayout::getIntPtrType. */		See the method llvm::DataLayout::getIntPtrType. */
	LLVMTypeRef LLVMIntPtrTypeForAS(LLVMTargetDataRef, unsigned AS);		LLVMTypeRef LLVMIntPtrTypeForASInContext(LLVMContextRef C, LLVMTargetDataRe
			f TD,
			unsigned AS);
	/** Computes the size of a type in bytes for a target.		/** Computes the size of a type in bytes for a target.
	See the method llvm::DataLayout::getTypeSizeInBits. */		See the method llvm::DataLayout::getTypeSizeInBits. */
	unsigned long long LLVMSizeOfTypeInBits(LLVMTargetDataRef, LLVMTypeRef);		unsigned long long LLVMSizeOfTypeInBits(LLVMTargetDataRef TD, LLVMTypeRef T y);
	/** Computes the storage size of a type in bytes for a target.		/** Computes the storage size of a type in bytes for a target.
	See the method llvm::DataLayout::getTypeStoreSize. */		See the method llvm::DataLayout::getTypeStoreSize. */
	unsigned long long LLVMStoreSizeOfType(LLVMTargetDataRef, LLVMTypeRef);		unsigned long long LLVMStoreSizeOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty );
	/** Computes the ABI size of a type in bytes for a target.		/** Computes the ABI size of a type in bytes for a target.
	See the method llvm::DataLayout::getTypeAllocSize. */		See the method llvm::DataLayout::getTypeAllocSize. */
	unsigned long long LLVMABISizeOfType(LLVMTargetDataRef, LLVMTypeRef);		unsigned long long LLVMABISizeOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty);
	/** Computes the ABI alignment of a type in bytes for a target.		/** Computes the ABI alignment of a type in bytes for a target.
	See the method llvm::DataLayout::getTypeABISize. */		See the method llvm::DataLayout::getTypeABISize. */
	unsigned LLVMABIAlignmentOfType(LLVMTargetDataRef, LLVMTypeRef);		unsigned LLVMABIAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty);
	/** Computes the call frame alignment of a type in bytes for a target.		/** Computes the call frame alignment of a type in bytes for a target.
	See the method llvm::DataLayout::getTypeABISize. */		See the method llvm::DataLayout::getTypeABISize. */
	unsigned LLVMCallFrameAlignmentOfType(LLVMTargetDataRef, LLVMTypeRef);		unsigned LLVMCallFrameAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) ;
	/** Computes the preferred alignment of a type in bytes for a target.		/** Computes the preferred alignment of a type in bytes for a target.
	See the method llvm::DataLayout::getTypeABISize. */		See the method llvm::DataLayout::getTypeABISize. */
	unsigned LLVMPreferredAlignmentOfType(LLVMTargetDataRef, LLVMTypeRef);		unsigned LLVMPreferredAlignmentOfType(LLVMTargetDataRef TD, LLVMTypeRef Ty) ;
	/** Computes the preferred alignment of a global variable in bytes for a ta rget.		/** Computes the preferred alignment of a global variable in bytes for a ta rget.
	See the method llvm::DataLayout::getPreferredAlignment. */		See the method llvm::DataLayout::getPreferredAlignment. */
	unsigned LLVMPreferredAlignmentOfGlobal(LLVMTargetDataRef,		unsigned LLVMPreferredAlignmentOfGlobal(LLVMTargetDataRef TD,
	LLVMValueRef GlobalVar);		LLVMValueRef GlobalVar);
	/** Computes the structure element that contains the byte offset for a targ et.		/** Computes the structure element that contains the byte offset for a targ et.
	See the method llvm::StructLayout::getElementContainingOffset. */		See the method llvm::StructLayout::getElementContainingOffset. */
	unsigned LLVMElementAtOffset(LLVMTargetDataRef, LLVMTypeRef StructTy,		unsigned LLVMElementAtOffset(LLVMTargetDataRef TD, LLVMTypeRef StructTy,
	unsigned long long Offset);		unsigned long long Offset);
	/** Computes the byte offset of the indexed struct element for a target.		/** Computes the byte offset of the indexed struct element for a target.
	See the method llvm::StructLayout::getElementContainingOffset. */		See the method llvm::StructLayout::getElementContainingOffset. */
	unsigned long long LLVMOffsetOfElement(LLVMTargetDataRef, LLVMTypeRef Struc		unsigned long long LLVMOffsetOfElement(LLVMTargetDataRef TD,
	tTy,		LLVMTypeRef StructTy, unsigned Eleme
	unsigned Element);		nt);
	/** Deallocates a TargetData.		/** Deallocates a TargetData.
	See the destructor llvm::DataLayout::~DataLayout. */		See the destructor llvm::DataLayout::~DataLayout. */
	void LLVMDisposeTargetData(LLVMTargetDataRef);		void LLVMDisposeTargetData(LLVMTargetDataRef TD);
	/**		/**
	* @}		* @}
	*/		*/
	#ifdef __cplusplus		#ifdef __cplusplus
	}		}
	#endif /* defined(__cplusplus) */		#endif /* defined(__cplusplus) */
	#endif		#endif
End of changes. 21 change blocks.
	22 lines changed or deleted		79 lines changed or added

	Target.td		Target.td
	skipping to change at line 25		skipping to change at line 25
	// Include all information about LLVM intrinsics.		// Include all information about LLVM intrinsics.
	include "llvm/IR/Intrinsics.td"		include "llvm/IR/Intrinsics.td"
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// Register file description - These classes are used to fill in the target		// Register file description - These classes are used to fill in the target
	// description classes.		// description classes.
	class RegisterClass; // Forward def		class RegisterClass; // Forward def
	// SubRegIndex - Use instances of SubRegIndex to identify subregisters.		// SubRegIndex - Use instances of SubRegIndex to identify subregisters.
	class SubRegIndex<list<SubRegIndex> comps = []> {		class SubRegIndex<int size, int offset = 0> {
	string Namespace = "";		string Namespace = "";
			// Size - Size (in bits) of the sub-registers represented by this index.
			int Size = size;
			// Offset - Offset of the first bit that is part of this sub-register ind
			ex.
			// Set it to -1 if the same index is used to represent sub-registers that
			can
			// be at different offsets (for example when using an index to access an
			// element in a register tuple).
			int Offset = offset;
	// ComposedOf - A list of two SubRegIndex instances, [A, B].		// ComposedOf - A list of two SubRegIndex instances, [A, B].
	// This indicates that this SubRegIndex is the result of composing A and B.		// This indicates that this SubRegIndex is the result of composing A and B.
	list<SubRegIndex> ComposedOf = comps;		// See ComposedSubRegIndex.
			list<SubRegIndex> ComposedOf = [];
	// CoveringSubRegIndices - A list of two or more sub-register indexes tha t		// CoveringSubRegIndices - A list of two or more sub-register indexes tha t
	// cover this sub-register.		// cover this sub-register.
	//		//
	// This field should normally be left blank as TableGen can infer it.		// This field should normally be left blank as TableGen can infer it.
	//		//
	// TableGen automatically detects sub-registers that straddle the registe rs		// TableGen automatically detects sub-registers that straddle the registe rs
	// in the SubRegs field of a Register definition. For example:		// in the SubRegs field of a Register definition. For example:
	//		//
	// Q0 = dsub_0 -> D0, dsub_1 -> D1		// Q0 = dsub_0 -> D0, dsub_1 -> D1
	// Q1 = dsub_0 -> D2, dsub_1 -> D3		// Q1 = dsub_0 -> D2, dsub_1 -> D3
	// D1_D2 = dsub_0 -> D1, dsub_1 -> D2		// D1_D2 = dsub_0 -> D1, dsub_1 -> D2
	// QQ0 = qsub_0 -> Q0, qsub_1 -> Q1		// QQ0 = qsub_0 -> Q0, qsub_1 -> Q1
	//		//
	// TableGen will infer that D1_D2 is a sub-register of QQ0. It will be gi ven		// TableGen will infer that D1_D2 is a sub-register of QQ0. It will be gi ven
	// the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined w ith		// the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined w ith
	// CoveringSubRegIndices = [dsub_1, dsub_2].		// CoveringSubRegIndices = [dsub_1, dsub_2].
	list<SubRegIndex> CoveringSubRegIndices = [];		list<SubRegIndex> CoveringSubRegIndices = [];
	}		}
			// ComposedSubRegIndex - A sub-register that is the result of composing A a
			nd B.
			// Offset is set to the sum of A and B's Offsets. Size is set to B's Size.
			class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B>
			: SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1,
			!if(!eq(B.Offset, -1), -1,
			!add(A.Offset, B.Offset)))> {
			// See SubRegIndex.
			let ComposedOf = [A, B];
			}
	// RegAltNameIndex - The alternate name set to use for register operands of		// RegAltNameIndex - The alternate name set to use for register operands of
	// this register class when printing.		// this register class when printing.
	class RegAltNameIndex {		class RegAltNameIndex {
	string Namespace = "";		string Namespace = "";
	}		}
	def NoRegAltName : RegAltNameIndex;		def NoRegAltName : RegAltNameIndex;
	// Register - You should define one instance of this class for each registe r		// Register - You should define one instance of this class for each registe r
	// in the target machine. String n will become the "name" of the register.		// in the target machine. String n will become the "name" of the register.
	class Register<string n, list<string> altNames = []> {		class Register<string n, list<string> altNames = []> {
	skipping to change at line 427		skipping to change at line 447
	string AsmMatchConverter = "";		string AsmMatchConverter = "";
	/// TwoOperandAliasConstraint - Enable TableGen to auto-generate a		/// TwoOperandAliasConstraint - Enable TableGen to auto-generate a
	/// two-operand matcher inst-alias for a three operand instruction.		/// two-operand matcher inst-alias for a three operand instruction.
	/// For example, the arm instruction "add r3, r3, r5" can be written		/// For example, the arm instruction "add r3, r3, r5" can be written
	/// as "add r3, r5". The constraint is of the same form as a tied-operand		/// as "add r3, r5". The constraint is of the same form as a tied-operand
	/// constraint. For example, "$Rn = $Rd".		/// constraint. For example, "$Rn = $Rd".
	string TwoOperandAliasConstraint = "";		string TwoOperandAliasConstraint = "";
	///@}		///@}
			/// UseNamedOperandTable - If set, the operand indices of this instructio
			n
			/// can be queried via the getNamedOperandIdx() function which is generat
			ed
			/// by TableGen.
			bit UseNamedOperandTable = 0;
	}		}
	/// PseudoInstExpansion - Expansion information for a pseudo-instruction.		/// PseudoInstExpansion - Expansion information for a pseudo-instruction.
	/// Which instruction it expands to and how the operands map from the		/// Which instruction it expands to and how the operands map from the
	/// pseudo.		/// pseudo.
	class PseudoInstExpansion<dag Result> {		class PseudoInstExpansion<dag Result> {
	dag ResultInst = Result; // The instruction to generate.		dag ResultInst = Result; // The instruction to generate.
	bit isPseudo = 1;		bit isPseudo = 1;
	}		}
	skipping to change at line 607		skipping to change at line 632
	def i64imm : Operand<i64>;		def i64imm : Operand<i64>;
	def f32imm : Operand<f32>;		def f32imm : Operand<f32>;
	def f64imm : Operand<f64>;		def f64imm : Operand<f64>;
	}		}
	/// zero_reg definition - Special node to stand for the zero register.		/// zero_reg definition - Special node to stand for the zero register.
	///		///
	def zero_reg;		def zero_reg;
			/// All operands which the MC layer classifies as predicates should inherit
			from
			/// this class in some manner. This is already handled for the most commonl
			y
			/// used PredicateOperand, but may be useful in other circumstances.
			class PredicateOp;
	/// OperandWithDefaultOps - This Operand class can be used as the parent cl ass		/// OperandWithDefaultOps - This Operand class can be used as the parent cl ass
	/// for an Operand that needs to be initialized with a default value if		/// for an Operand that needs to be initialized with a default value if
	/// no value is supplied in a pattern. This class can be used to simplify the		/// no value is supplied in a pattern. This class can be used to simplify the
	/// pattern definitions for instructions that have target specific flags		/// pattern definitions for instructions that have target specific flags
	/// encoded as immediate operands.		/// encoded as immediate operands.
	class OperandWithDefaultOps<ValueType ty, dag defaultops>		class OperandWithDefaultOps<ValueType ty, dag defaultops>
	: Operand<ty> {		: Operand<ty> {
	dag DefaultOps = defaultops;		dag DefaultOps = defaultops;
	}		}
	/// PredicateOperand - This can be used to define a predicate operand for a n		/// PredicateOperand - This can be used to define a predicate operand for a n
	/// instruction. OpTypes specifies the MIOperandInfo for the operand, and		/// instruction. OpTypes specifies the MIOperandInfo for the operand, and
	/// AlwaysVal specifies the value of this predicate when set to "always		/// AlwaysVal specifies the value of this predicate when set to "always
	/// execute".		/// execute".
	class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>		class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
	: OperandWithDefaultOps<ty, AlwaysVal> {		: OperandWithDefaultOps<ty, AlwaysVal>, PredicateOp {
	let MIOperandInfo = OpTypes;		let MIOperandInfo = OpTypes;
	}		}
	/// OptionalDefOperand - This is used to define a optional definition opera nd		/// OptionalDefOperand - This is used to define a optional definition opera nd
	/// for an instruction. DefaultOps is the register the operand represents i f		/// for an instruction. DefaultOps is the register the operand represents i f
	/// none is supplied, e.g. zero_reg.		/// none is supplied, e.g. zero_reg.
	class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>		class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
	: OperandWithDefaultOps<ty, defaultops> {		: OperandWithDefaultOps<ty, defaultops> {
	let MIOperandInfo = OpTypes;		let MIOperandInfo = OpTypes;
	}		}
	skipping to change at line 769		skipping to change at line 799
	let InOperandList = (ins i32imm:$id);		let InOperandList = (ins i32imm:$id);
	let AsmString = "LIFETIME_START";		let AsmString = "LIFETIME_START";
	let neverHasSideEffects = 1;		let neverHasSideEffects = 1;
	}		}
	def LIFETIME_END : Instruction {		def LIFETIME_END : Instruction {
	let OutOperandList = (outs);		let OutOperandList = (outs);
	let InOperandList = (ins i32imm:$id);		let InOperandList = (ins i32imm:$id);
	let AsmString = "LIFETIME_END";		let AsmString = "LIFETIME_END";
	let neverHasSideEffects = 1;		let neverHasSideEffects = 1;
	}		}
			def STACKMAP : Instruction {
			let OutOperandList = (outs);
			let InOperandList = (ins i32imm:$id, i32imm:$nbytes, variable_ops);
			let isCall = 1;
			let mayLoad = 1;
			}
			def PATCHPOINT : Instruction {
			let OutOperandList = (outs unknown:$dst);
			let InOperandList = (ins i32imm:$id, i32imm:$nbytes, unknown:$callee,
			i32imm:$nargs, i32imm:$cc, variable_ops);
			let isCall = 1;
			let mayLoad = 1;
			}
	}		}
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// AsmParser - This class can be implemented by targets that wish to implem ent		// AsmParser - This class can be implemented by targets that wish to implem ent
	// .s file parsing.		// .s file parsing.
	//		//
	// Subtargets can have multiple different assembly parsers (e.g. AT&T vs In tel		// Subtargets can have multiple different assembly parsers (e.g. AT&T vs In tel
	// syntax on X86 for example).		// syntax on X86 for example).
	//		//
	class AsmParser {		class AsmParser {
	skipping to change at line 792		skipping to change at line 835
	string AsmParserClassName = "AsmParser";		string AsmParserClassName = "AsmParser";
	// AsmParserInstCleanup - If non-empty, this is the name of a custom memb er		// AsmParserInstCleanup - If non-empty, this is the name of a custom memb er
	// function of the AsmParser class to call on every matched instruction.		// function of the AsmParser class to call on every matched instruction.
	// This can be used to perform target specific instruction post-processin g.		// This can be used to perform target specific instruction post-processin g.
	string AsmParserInstCleanup = "";		string AsmParserInstCleanup = "";
	// ShouldEmitMatchRegisterName - Set to false if the target needs a hand		// ShouldEmitMatchRegisterName - Set to false if the target needs a hand
	// written register name matcher		// written register name matcher
	bit ShouldEmitMatchRegisterName = 1;		bit ShouldEmitMatchRegisterName = 1;
			/// Does the instruction mnemonic allow '.'
			bit MnemonicContainsDot = 0;
	}		}
	def DefaultAsmParser : AsmParser;		def DefaultAsmParser : AsmParser;
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// AsmParserVariant - Subtargets can have multiple different assembly parse rs		// AsmParserVariant - Subtargets can have multiple different assembly parse rs
	// (e.g. AT&T vs Intel syntax on X86 for example). This class can be		// (e.g. AT&T vs Intel syntax on X86 for example). This class can be
	// implemented by targets to describe such variants.		// implemented by targets to describe such variants.
	//		//
	class AsmParserVariant {		class AsmParserVariant {
	// Variant - AsmParsers can be of multiple different variants. Variants are		// Variant - AsmParsers can be of multiple different variants. Variants are
	skipping to change at line 974		skipping to change at line 1020
	// information.		// information.
	//		//
	string Desc = d;		string Desc = d;
	// Implies - Features that this feature implies are present. If one of th ose		// Implies - Features that this feature implies are present. If one of th ose
	// features isn't set, then this one shouldn't be set either.		// features isn't set, then this one shouldn't be set either.
	//		//
	list<SubtargetFeature> Implies = i;		list<SubtargetFeature> Implies = i;
	}		}
			/// Specifies a Subtarget feature that this instruction is deprecated on.
			class Deprecated<SubtargetFeature dep> {
			SubtargetFeature DeprecatedFeatureMask = dep;
			}
			/// A custom predicate used to determine if an instruction is
			/// deprecated or not.
			class ComplexDeprecationPredicate<string dep> {
			string ComplexDeprecationPredicate = dep;
			}
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// Processor chip sets - These values represent each of the chip sets suppo rted		// Processor chip sets - These values represent each of the chip sets suppo rted
	// by the scheduler. Each Processor definition requires corresponding		// by the scheduler. Each Processor definition requires corresponding
	// instruction itineraries.		// instruction itineraries.
	//		//
	class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f > {		class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f > {
	// Name - Chip set name. Used by command line (-mcpu=) to determine the		// Name - Chip set name. Used by command line (-mcpu=) to determine the
	// appropriate target chip.		// appropriate target chip.
	//		//
	string Name = n;		string Name = n;
End of changes. 10 change blocks.
	3 lines changed or deleted		67 lines changed or added

	TargetCallingConv.h		TargetCallingConv.h
	skipping to change at line 116		skipping to change at line 116
	uint64_t getRawBits() const { return Flags; }		uint64_t getRawBits() const { return Flags; }
	};		};
	/// InputArg - This struct carries flags and type information about a		/// InputArg - This struct carries flags and type information about a
	/// single incoming (formal) argument or incoming (from the perspective		/// single incoming (formal) argument or incoming (from the perspective
	/// of the caller) return value virtual register.		/// of the caller) return value virtual register.
	///		///
	struct InputArg {		struct InputArg {
	ArgFlagsTy Flags;		ArgFlagsTy Flags;
	MVT VT;		MVT VT;
			EVT ArgVT;
	bool Used;		bool Used;
	/// Index original Function's argument.		/// Index original Function's argument.
	unsigned OrigArgIndex;		unsigned OrigArgIndex;
	/// Offset in bytes of current input value relative to the beginning of		/// Offset in bytes of current input value relative to the beginning of
	/// original argument. E.g. if argument was splitted into four 32 bit		/// original argument. E.g. if argument was splitted into four 32 bit
	/// registers, we got 4 InputArgs with PartOffsets 0, 4, 8 and 12.		/// registers, we got 4 InputArgs with PartOffsets 0, 4, 8 and 12.
	unsigned PartOffset;		unsigned PartOffset;
	InputArg() : VT(MVT::Other), Used(false) {}		InputArg() : VT(MVT::Other), Used(false) {}
	InputArg(ArgFlagsTy flags, EVT vt, bool used,		InputArg(ArgFlagsTy flags, EVT vt, EVT argvt, bool used,
	unsigned origIdx, unsigned partOffs)		unsigned origIdx, unsigned partOffs)
	: Flags(flags), Used(used), OrigArgIndex(origIdx), PartOffset(partOff s) {		: Flags(flags), Used(used), OrigArgIndex(origIdx), PartOffset(partOff s) {
	VT = vt.getSimpleVT();		VT = vt.getSimpleVT();
			ArgVT = argvt;
	}		}
	};		};
	/// OutputArg - This struct carries flags and a value for a		/// OutputArg - This struct carries flags and a value for a
	/// single outgoing (actual) argument or outgoing (from the perspective		/// single outgoing (actual) argument or outgoing (from the perspective
	/// of the caller) return value virtual register.		/// of the caller) return value virtual register.
	///		///
	struct OutputArg {		struct OutputArg {
	ArgFlagsTy Flags;		ArgFlagsTy Flags;
	MVT VT;		MVT VT;
			EVT ArgVT;
	/// IsFixed - Is this a "fixed" value, ie not passed through a vararg " ...".		/// IsFixed - Is this a "fixed" value, ie not passed through a vararg " ...".
	bool IsFixed;		bool IsFixed;
	/// Index original Function's argument.		/// Index original Function's argument.
	unsigned OrigArgIndex;		unsigned OrigArgIndex;
	/// Offset in bytes of current output value relative to the beginning o f		/// Offset in bytes of current output value relative to the beginning o f
	/// original argument. E.g. if argument was splitted into four 32 bit		/// original argument. E.g. if argument was splitted into four 32 bit
	/// registers, we got 4 OutputArgs with PartOffsets 0, 4, 8 and 12.		/// registers, we got 4 OutputArgs with PartOffsets 0, 4, 8 and 12.
	unsigned PartOffset;		unsigned PartOffset;
	OutputArg() : IsFixed(false) {}		OutputArg() : IsFixed(false) {}
	OutputArg(ArgFlagsTy flags, EVT vt, bool isfixed,		OutputArg(ArgFlagsTy flags, EVT vt, EVT argvt, bool isfixed,
	unsigned origIdx, unsigned partOffs)		unsigned origIdx, unsigned partOffs)
	: Flags(flags), IsFixed(isfixed), OrigArgIndex(origIdx),		: Flags(flags), IsFixed(isfixed), OrigArgIndex(origIdx),
	PartOffset(partOffs) {		PartOffset(partOffs) {
	VT = vt.getSimpleVT();		VT = vt.getSimpleVT();
			ArgVT = argvt;
	}		}
	};		};
	}		}
	} // end llvm namespace		} // end llvm namespace
	#endif		#endif
End of changes. 6 change blocks.
	2 lines changed or deleted		6 lines changed or added

	TargetCallingConv.td		TargetCallingConv.td
	skipping to change at line 146		skipping to change at line 146
	/// CalleeSavedRegs - A list of callee saved registers for a given calling		/// CalleeSavedRegs - A list of callee saved registers for a given calling
	/// convention. The order of registers is used by PrologEpilogInsertion wh en		/// convention. The order of registers is used by PrologEpilogInsertion wh en
	/// allocation stack slots for saved registers.		/// allocation stack slots for saved registers.
	///		///
	/// For each CalleeSavedRegs def, TableGen will emit a FOO_SaveList array f or		/// For each CalleeSavedRegs def, TableGen will emit a FOO_SaveList array f or
	/// returning from getCalleeSavedRegs(), and a FOO_RegMask bit mask suitabl e for		/// returning from getCalleeSavedRegs(), and a FOO_RegMask bit mask suitabl e for
	/// returning from getCallPreservedMask().		/// returning from getCallPreservedMask().
	class CalleeSavedRegs<dag saves> {		class CalleeSavedRegs<dag saves> {
	dag SaveList = saves;		dag SaveList = saves;
			// Registers that are also preserved across function calls, but should no
			t be
			// included in the generated FOO_SaveList array. These registers will be
			// included in the FOO_RegMask bit mask. This can be used for registers t
			hat
			// are saved automatically, like the SPARC register windows.
			dag OtherPreserved;
	}		}
End of changes. 1 change blocks.
	0 lines changed or deleted		8 lines changed or added

	TargetFrameLowering.h		TargetFrameLowering.h
	skipping to change at line 91		skipping to change at line 91
	/// realigned.		/// realigned.
	bool isStackRealignable() const {		bool isStackRealignable() const {
	return StackRealignable;		return StackRealignable;
	}		}
	/// getOffsetOfLocalArea - This method returns the offset of the local ar ea		/// getOffsetOfLocalArea - This method returns the offset of the local ar ea
	/// from the stack pointer on entrance to a function.		/// from the stack pointer on entrance to a function.
	///		///
	int getOffsetOfLocalArea() const { return LocalAreaOffset; }		int getOffsetOfLocalArea() const { return LocalAreaOffset; }
			/// isFPCloseToIncomingSP - Return true if the frame pointer is close to
			/// the incoming stack pointer, false if it is close to the post-prologue
			/// stack pointer.
			virtual bool isFPCloseToIncomingSP() const { return true; }
	/// getCalleeSavedSpillSlots - This method returns a pointer to an array of		/// getCalleeSavedSpillSlots - This method returns a pointer to an array of
	/// pairs, that contains an entry for each callee saved register that mus t be		/// pairs, that contains an entry for each callee saved register that mus t be
	/// spilled to a particular stack location if it is spilled.		/// spilled to a particular stack location if it is spilled.
	///		///
	/// Each entry in this array contains a <register,offset> pair, indicatin g the		/// Each entry in this array contains a <register,offset> pair, indicatin g the
	/// fixed offset from the incoming stack pointer that each register shoul d be		/// fixed offset from the incoming stack pointer that each register shoul d be
	/// spilled at. If a register is not listed here, the code generator is		/// spilled at. If a register is not listed here, the code generator is
	/// allowed to spill it anywhere it chooses.		/// allowed to spill it anywhere it chooses.
	///		///
	virtual const SpillSlot *		virtual const SpillSlot *
End of changes. 1 change blocks.
	0 lines changed or deleted		5 lines changed or added

	TargetInstrInfo.h		TargetInstrInfo.h
	skipping to change at line 175		skipping to change at line 175
	/// hasStoreToStackSlot - If the specified machine instruction has a		/// hasStoreToStackSlot - If the specified machine instruction has a
	/// store to a stack slot, return true along with the FrameIndex of		/// store to a stack slot, return true along with the FrameIndex of
	/// the loaded stack slot and the machine mem operand containing the		/// the loaded stack slot and the machine mem operand containing the
	/// reference. If not, return false. Unlike isStoreToStackSlot,		/// reference. If not, return false. Unlike isStoreToStackSlot,
	/// this returns true for any instructions that stores to the		/// this returns true for any instructions that stores to the
	/// stack. This is just a hint, as some cases may be missed.		/// stack. This is just a hint, as some cases may be missed.
	virtual bool hasStoreToStackSlot(const MachineInstr *MI,		virtual bool hasStoreToStackSlot(const MachineInstr *MI,
	const MachineMemOperand *&MMO,		const MachineMemOperand *&MMO,
	int &FrameIndex) const;		int &FrameIndex) const;
			/// isStackSlotCopy - Return true if the specified machine instruction
			/// is a copy of one stack slot to another and has no other effect.
			/// Provide the identity of the two frame indices.
			virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
			int &SrcFrameIndex) const {
			return false;
			}
			/// Compute the size in bytes and offset within a stack slot of a spilled
			/// register or subregister.
			///
			/// \param [out] Size in bytes of the spilled value.
			/// \param [out] Offset in bytes within the stack slot.
			/// \returns true if both Size and Offset are successfully computed.
			///
			/// Not all subregisters have computable spill slots. For example,
			/// subregisters registers may not be byte-sized, and a pair of discontig
			uous
			/// subregisters has no single offset.
			///
			/// Targets with nontrivial bigendian implementations may need to overrid
			e
			/// this, particularly to support spilled vector registers.
			virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned Su
			bIdx,
			unsigned &Size, unsigned &Offset,
			const TargetMachine *TM) const;
	/// reMaterialize - Re-issue the specified 'original' instruction at the		/// reMaterialize - Re-issue the specified 'original' instruction at the
	/// specific location targeting a new destination register.		/// specific location targeting a new destination register.
	/// The register in Orig->getOperand(0).getReg() will be substituted by		/// The register in Orig->getOperand(0).getReg() will be substituted by
	/// DestReg:SubIdx. Any existing subreg index is preserved or composed wi th		/// DestReg:SubIdx. Any existing subreg index is preserved or composed wi th
	/// SubIdx.		/// SubIdx.
	virtual void reMaterialize(MachineBasicBlock &MBB,		virtual void reMaterialize(MachineBasicBlock &MBB,
	MachineBasicBlock::iterator MI,		MachineBasicBlock::iterator MI,
	unsigned DestReg, unsigned SubIdx,		unsigned DestReg, unsigned SubIdx,
	const MachineInstr *Orig,		const MachineInstr *Orig,
	const TargetRegisterInfo &TRI) const;		const TargetRegisterInfo &TRI) const;
	skipping to change at line 507		skipping to change at line 532
	/// expandPostRAPseudo - This function is called for all pseudo instructi ons		/// expandPostRAPseudo - This function is called for all pseudo instructi ons
	/// that remain after register allocation. Many pseudo instructions are		/// that remain after register allocation. Many pseudo instructions are
	/// created to help register allocation. This is the place to convert the m		/// created to help register allocation. This is the place to convert the m
	/// into real instructions. The target can edit MI in place, or it can in sert		/// into real instructions. The target can edit MI in place, or it can in sert
	/// new instructions and erase MI. The function should return true if		/// new instructions and erase MI. The function should return true if
	/// anything was changed.		/// anything was changed.
	virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const {		virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
	return false;		return false;
	}		}
	/// emitFrameIndexDebugValue - Emit a target-dependent form of
	/// DBG_VALUE encoding the address of a frame index. Addresses would
	/// normally be lowered the same way as other addresses on the target,
	/// e.g. in load instructions. For targets that do not support this
	/// the debug info is simply lost.
	/// If you add this for a target you should handle this DBG_VALUE in the
	/// target-specific AsmPrinter code as well; you will probably get invali
	d
	/// assembly output if you don't.
	virtual MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
	int FrameIx,
	uint64_t Offset,
	const MDNode *MDPtr,
	DebugLoc dl) const {
	return 0;
	}
	/// foldMemoryOperand - Attempt to fold a load or store of the specified stack		/// foldMemoryOperand - Attempt to fold a load or store of the specified stack
	/// slot into the specified machine instruction for the specified operand (s).		/// slot into the specified machine instruction for the specified operand (s).
	/// If this is possible, a new instruction is returned with the specified		/// If this is possible, a new instruction is returned with the specified
	/// operand folded, otherwise NULL is returned.		/// operand folded, otherwise NULL is returned.
	/// The new instruction is inserted before MI, and the client is responsi ble		/// The new instruction is inserted before MI, and the client is responsi ble
	/// for removing the old instruction.		/// for removing the old instruction.
	MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,		MachineInstr* foldMemoryOperand(MachineBasicBlock::iterator MI,
	const SmallVectorImpl<unsigned> &Ops,		const SmallVectorImpl<unsigned> &Ops,
	int FrameIndex) const;		int FrameIndex) const;
	skipping to change at line 625		skipping to change at line 634
	return false;		return false;
	}		}
	/// \brief Get the base register and byte offset of a load/store instr.		/// \brief Get the base register and byte offset of a load/store instr.
	virtual bool getLdStBaseRegImmOfs(MachineInstr *LdSt,		virtual bool getLdStBaseRegImmOfs(MachineInstr *LdSt,
	unsigned &BaseReg, unsigned &Offset,		unsigned &BaseReg, unsigned &Offset,
	const TargetRegisterInfo *TRI) const {		const TargetRegisterInfo *TRI) const {
	return false;		return false;
	}		}
			virtual bool enableClusterLoads() const { return false; }
	virtual bool shouldClusterLoads(MachineInstr *FirstLdSt,		virtual bool shouldClusterLoads(MachineInstr *FirstLdSt,
	MachineInstr *SecondLdSt,		MachineInstr *SecondLdSt,
	unsigned NumLoads) const {		unsigned NumLoads) const {
	return false;		return false;
	}		}
	/// \brief Can this target fuse the given instructions if they are schedu led		/// \brief Can this target fuse the given instructions if they are schedu led
	/// adjacent.		/// adjacent.
	virtual bool shouldScheduleAdjacent(MachineInstr* First,		virtual bool shouldScheduleAdjacent(MachineInstr* First,
	MachineInstr *Second) const {		MachineInstr *Second) const {
	skipping to change at line 817		skipping to change at line 828
	///		///
	/// This is a raw interface to the itinerary that may be directly overrid en by		/// This is a raw interface to the itinerary that may be directly overrid en by
	/// a target. Use computeOperandLatency to get the best estimate of laten cy.		/// a target. Use computeOperandLatency to get the best estimate of laten cy.
	virtual int getOperandLatency(const InstrItineraryData *ItinData,		virtual int getOperandLatency(const InstrItineraryData *ItinData,
	const MachineInstr *DefMI, unsigned DefIdx,		const MachineInstr *DefMI, unsigned DefIdx,
	const MachineInstr *UseMI,		const MachineInstr *UseMI,
	unsigned UseIdx) const;		unsigned UseIdx) const;
	/// computeOperandLatency - Compute and return the latency of the given d ata		/// computeOperandLatency - Compute and return the latency of the given d ata
	/// dependent def and use when the operand indices are already known.		/// dependent def and use when the operand indices are already known.
	///
	/// FindMin may be set to get the minimum vs. expected latency.
	unsigned computeOperandLatency(const InstrItineraryData *ItinData,		unsigned computeOperandLatency(const InstrItineraryData *ItinData,
	const MachineInstr *DefMI, unsigned DefIdx ,		const MachineInstr *DefMI, unsigned DefIdx ,
	const MachineInstr *UseMI, unsigned UseIdx		const MachineInstr *UseMI, unsigned UseIdx
	,		)
	bool FindMin = false) const;		const;
	/// getInstrLatency - Compute the instruction latency of a given instruct ion.		/// getInstrLatency - Compute the instruction latency of a given instruct ion.
	/// If the instruction has higher cost when predicated, it's returned via		/// If the instruction has higher cost when predicated, it's returned via
	/// PredCost.		/// PredCost.
	virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,		virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
	const MachineInstr *MI,		const MachineInstr *MI,
	unsigned *PredCost = 0) const;		unsigned *PredCost = 0) const;
			virtual unsigned getPredicationCost(const MachineInstr *MI) const;
	virtual int getInstrLatency(const InstrItineraryData *ItinData,		virtual int getInstrLatency(const InstrItineraryData *ItinData,
	SDNode *Node) const;		SDNode *Node) const;
	/// Return the default expected latency for a def based on it's opcode.		/// Return the default expected latency for a def based on it's opcode.
	unsigned defaultDefLatency(const MCSchedModel *SchedModel,		unsigned defaultDefLatency(const MCSchedModel *SchedModel,
	const MachineInstr *DefMI) const;		const MachineInstr *DefMI) const;
	int computeDefOperandLatency(const InstrItineraryData *ItinData,		int computeDefOperandLatency(const InstrItineraryData *ItinData,
	const MachineInstr *DefMI, bool FindMin) con st;		const MachineInstr *DefMI) const;
	/// isHighLatencyDef - Return true if this opcode has high latency to its		/// isHighLatencyDef - Return true if this opcode has high latency to its
	/// result.		/// result.
	virtual bool isHighLatencyDef(int opc) const { return false; }		virtual bool isHighLatencyDef(int opc) const { return false; }
	/// hasHighOperandLatency - Compute operand latency between a def of 'Reg '		/// hasHighOperandLatency - Compute operand latency between a def of 'Reg '
	/// and an use in the current loop, return true if the target considered		/// and an use in the current loop, return true if the target considered
	/// it 'high'. This is used by optimization passes such as machine LICM t o		/// it 'high'. This is used by optimization passes such as machine LICM t o
	/// determine whether it makes sense to hoist an instruction out even in		/// determine whether it makes sense to hoist an instruction out even in
	/// high register pressure situation.		/// high register pressure situation.
	skipping to change at line 947		skipping to change at line 958
	/// 3. Calling breakPartialRegDependency() with the same arguments. This		/// 3. Calling breakPartialRegDependency() with the same arguments. This
	/// allows the target to insert a dependency breaking instruction.		/// allows the target to insert a dependency breaking instruction.
	///		///
	virtual unsigned		virtual unsigned
	getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,		getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
	const TargetRegisterInfo *TRI) const {		const TargetRegisterInfo *TRI) const {
	// The default implementation returns 0 for no partial register depende ncy.		// The default implementation returns 0 for no partial register depende ncy.
	return 0;		return 0;
	}		}
			/// \brief Return the minimum clearance before an instruction that reads
			an
			/// unused register.
			///
			/// For example, AVX instructions may copy part of an register operand in
			to
			/// the unused high bits of the destination register.
			///
			/// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
			///
			/// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creati
			ng a
			/// false dependence on any previous write to %xmm0.
			///
			/// This hook works similarly to getPartialRegUpdateClearance, except tha
			t it
			/// does not take an operand index. Instead sets \p OpNum to the index of
			the
			/// unused register.
			virtual unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &O
			pNum,
			const TargetRegisterInfo *TRI) cons
			t {
			// The default implementation returns 0 for no undef register dependenc
			y.
			return 0;
			}
	/// breakPartialRegDependency - Insert a dependency-breaking instruction		/// breakPartialRegDependency - Insert a dependency-breaking instruction
	/// before MI to eliminate an unwanted dependency on OpNum.		/// before MI to eliminate an unwanted dependency on OpNum.
	///		///
	/// If it wasn't possible to avoid a def in the last N instructions befor e MI		/// If it wasn't possible to avoid a def in the last N instructions befor e MI
	/// (see getPartialRegUpdateClearance), this hook will be called to break the		/// (see getPartialRegUpdateClearance), this hook will be called to break the
	/// unwanted dependency.		/// unwanted dependency.
	///		///
	/// On x86, an xorps instruction can be used as a dependency breaker:		/// On x86, an xorps instruction can be used as a dependency breaker:
	///		///
	/// addps %xmm1, %xmm0		/// addps %xmm1, %xmm0
End of changes. 8 change blocks.
	23 lines changed or deleted		64 lines changed or added

	TargetLibraryInfo.h		TargetLibraryInfo.h
	skipping to change at line 27		skipping to change at line 27
	class Triple;		class Triple;
	namespace LibFunc {		namespace LibFunc {
	enum Func {		enum Func {
	/// int _IO_getc(_IO_FILE * __fp);		/// int _IO_getc(_IO_FILE * __fp);
	under_IO_getc,		under_IO_getc,
	/// int _IO_putc(int __c, _IO_FILE * __fp);		/// int _IO_putc(int __c, _IO_FILE * __fp);
	under_IO_putc,		under_IO_putc,
	/// void operator delete[](void*);		/// void operator delete[](void*);
	ZdaPv,		ZdaPv,
			/// void operator delete[](void*, nothrow);
			ZdaPvRKSt9nothrow_t,
	/// void operator delete(void*);		/// void operator delete(void*);
	ZdlPv,		ZdlPv,
			/// void operator delete(void*, nothrow);
			ZdlPvRKSt9nothrow_t,
	/// void *new[](unsigned int);		/// void *new[](unsigned int);
	Znaj,		Znaj,
	/// void *new[](unsigned int, nothrow);		/// void *new[](unsigned int, nothrow);
	ZnajRKSt9nothrow_t,		ZnajRKSt9nothrow_t,
	/// void *new[](unsigned long);		/// void *new[](unsigned long);
	Znam,		Znam,
	/// void *new[](unsigned long, nothrow);		/// void *new[](unsigned long, nothrow);
	ZnamRKSt9nothrow_t,		ZnamRKSt9nothrow_t,
	/// void *new(unsigned int);		/// void *new(unsigned int);
	Znwj,		Znwj,
	/// void *new(unsigned int, nothrow);		/// void *new(unsigned int, nothrow);
	ZnwjRKSt9nothrow_t,		ZnwjRKSt9nothrow_t,
	/// void *new(unsigned long);		/// void *new(unsigned long);
	Znwm,		Znwm,
	/// void *new(unsigned long, nothrow);		/// void *new(unsigned long, nothrow);
	ZnwmRKSt9nothrow_t,		ZnwmRKSt9nothrow_t,
			/// double __cospi(double x);
			cospi,
			/// float __cospif(float x);
			cospif,
	/// int __cxa_atexit(void (*f)(void *), void *p, void *d);		/// int __cxa_atexit(void (*f)(void *), void *p, void *d);
	cxa_atexit,		cxa_atexit,
	/// void __cxa_guard_abort(guard_t *guard);		/// void __cxa_guard_abort(guard_t *guard);
	/// guard_t is int64_t in Itanium ABI or int32_t on ARM eabi.		/// guard_t is int64_t in Itanium ABI or int32_t on ARM eabi.
	cxa_guard_abort,		cxa_guard_abort,
	/// int __cxa_guard_acquire(guard_t *guard);		/// int __cxa_guard_acquire(guard_t *guard);
	cxa_guard_acquire,		cxa_guard_acquire,
	/// void __cxa_guard_release(guard_t *guard);		/// void __cxa_guard_release(guard_t *guard);
	cxa_guard_release,		cxa_guard_release,
	/// int __isoc99_scanf (const char *format, ...)		/// int __isoc99_scanf (const char *format, ...)
	dunder_isoc99_scanf,		dunder_isoc99_scanf,
	/// int __isoc99_sscanf(const char *s, const char *format, ...)		/// int __isoc99_sscanf(const char *s, const char *format, ...)
	dunder_isoc99_sscanf,		dunder_isoc99_sscanf,
	/// void *__memcpy_chk(void *s1, const void *s2, size_t n, size_t s1s ize);		/// void *__memcpy_chk(void *s1, const void *s2, size_t n, size_t s1s ize);
	memcpy_chk,		memcpy_chk,
			/// double __sincospi_stret(double x);
			sincospi_stret,
			/// float __sincospi_stretf(float x);
			sincospi_stretf,
			/// double __sinpi(double x);
			sinpi,
			/// float __sinpif(float x);
			sinpif,
			/// double __sqrt_finite(double x);
			sqrt_finite,
			/// float __sqrt_finite(float x);
			sqrtf_finite,
			/// long double __sqrt_finite(long double x);
			sqrtl_finite,
	/// char * __strdup(const char *s);		/// char * __strdup(const char *s);
	dunder_strdup,		dunder_strdup,
	/// char *__strndup(const char *s, size_t n);		/// char *__strndup(const char *s, size_t n);
	dunder_strndup,		dunder_strndup,
	/// char * __strtok_r(char *s, const char *delim, char **save_ptr);		/// char * __strtok_r(char *s, const char *delim, char **save_ptr);
	dunder_strtok_r,		dunder_strtok_r,
	/// int abs(int j);		/// int abs(int j);
	abs,		abs,
	/// int access(const char *path, int amode);		/// int access(const char *path, int amode);
	access,		access,
	skipping to change at line 305		skipping to change at line 327
	/// char *getenv(const char *name);		/// char *getenv(const char *name);
	getenv,		getenv,
	/// int getitimer(int which, struct itimerval *value);		/// int getitimer(int which, struct itimerval *value);
	getitimer,		getitimer,
	/// int getlogin_r(char *name, size_t namesize);		/// int getlogin_r(char *name, size_t namesize);
	getlogin_r,		getlogin_r,
	/// struct passwd *getpwnam(const char *name);		/// struct passwd *getpwnam(const char *name);
	getpwnam,		getpwnam,
	/// char *gets(char *s);		/// char *gets(char *s);
	gets,		gets,
			/// int gettimeofday(struct timeval *tp, void *tzp);
			gettimeofday,
	/// uint32_t htonl(uint32_t hostlong);		/// uint32_t htonl(uint32_t hostlong);
	htonl,		htonl,
	/// uint16_t htons(uint16_t hostshort);		/// uint16_t htons(uint16_t hostshort);
	htons,		htons,
	/// int iprintf(const char *format, ...);		/// int iprintf(const char *format, ...);
	iprintf,		iprintf,
	/// int isascii(int c);		/// int isascii(int c);
	isascii,		isascii,
	/// int isdigit(int c);		/// int isdigit(int c);
	isdigit,		isdigit,
	skipping to change at line 680		skipping to change at line 704
	bool hasOptimizedCodeGen(LibFunc::Func F) const {		bool hasOptimizedCodeGen(LibFunc::Func F) const {
	if (getState(F) == Unavailable)		if (getState(F) == Unavailable)
	return false;		return false;
	switch (F) {		switch (F) {
	default: break;		default: break;
	case LibFunc::copysign: case LibFunc::copysignf: case LibFunc::copysi gnl:		case LibFunc::copysign: case LibFunc::copysignf: case LibFunc::copysi gnl:
	case LibFunc::fabs: case LibFunc::fabsf: case LibFunc::fabsl:		case LibFunc::fabs: case LibFunc::fabsf: case LibFunc::fabsl:
	case LibFunc::sin: case LibFunc::sinf: case LibFunc::sinl:		case LibFunc::sin: case LibFunc::sinf: case LibFunc::sinl:
	case LibFunc::cos: case LibFunc::cosf: case LibFunc::cosl:		case LibFunc::cos: case LibFunc::cosf: case LibFunc::cosl:
	case LibFunc::sqrt: case LibFunc::sqrtf: case LibFunc::sqrtl:		case LibFunc::sqrt: case LibFunc::sqrtf: case LibFunc::sqrtl:
			case LibFunc::sqrt_finite: case LibFunc::sqrtf_finite:
			case LibFunc::sqrtl_finit
			e:
	case LibFunc::floor: case LibFunc::floorf: case LibFunc::floorl :		case LibFunc::floor: case LibFunc::floorf: case LibFunc::floorl :
	case LibFunc::nearbyint: case LibFunc::nearbyintf: case LibFunc::nearby intl:		case LibFunc::nearbyint: case LibFunc::nearbyintf: case LibFunc::nearby intl:
	case LibFunc::ceil: case LibFunc::ceilf: case LibFunc::ceill:		case LibFunc::ceil: case LibFunc::ceilf: case LibFunc::ceill:
	case LibFunc::rint: case LibFunc::rintf: case LibFunc::rintl:		case LibFunc::rint: case LibFunc::rintf: case LibFunc::rintl:
			case LibFunc::round: case LibFunc::roundf: case LibFunc::roundl :
	case LibFunc::trunc: case LibFunc::truncf: case LibFunc::truncl :		case LibFunc::trunc: case LibFunc::truncf: case LibFunc::truncl :
	case LibFunc::log2: case LibFunc::log2f: case LibFunc::log2l:		case LibFunc::log2: case LibFunc::log2f: case LibFunc::log2l:
	case LibFunc::exp2: case LibFunc::exp2f: case LibFunc::exp2l:		case LibFunc::exp2: case LibFunc::exp2f: case LibFunc::exp2l:
	case LibFunc::memcmp:		case LibFunc::memcmp: case LibFunc::strcmp: case LibFunc::strcpy
			:
			case LibFunc::stpcpy: case LibFunc::strlen: case LibFunc::strnle
			n:
			case LibFunc::memchr:
	return true;		return true;
	}		}
	return false;		return false;
	}		}
	StringRef getName(LibFunc::Func F) const {		StringRef getName(LibFunc::Func F) const {
	AvailabilityState State = getState(F);		AvailabilityState State = getState(F);
	if (State == Unavailable)		if (State == Unavailable)
	return StringRef();		return StringRef();
	if (State == StandardName)		if (State == StandardName)
End of changes. 8 change blocks.
	1 lines changed or deleted		33 lines changed or added

	TargetLowering.h		TargetLowering.h
	//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*- ===//		//===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*- ===//
	//		//
	// The LLVM Compiler Infrastructure		// The LLVM Compiler Infrastructure
	//		//
	// This file is distributed under the University of Illinois Open Source		// This file is distributed under the University of Illinois Open Source
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		///
	// This file describes how to lower LLVM code to machine code. This has tw		/// \file
	o		/// This file describes how to lower LLVM code to machine code. This has t
	// main components:		wo
	//		/// main components:
	// 1. Which ValueTypes are natively supported by the target.		///
	// 2. Which operations are supported for supported ValueTypes.		/// 1. Which ValueTypes are natively supported by the target.
	// 3. Cost thresholds for alternative implementations of certain operation		/// 2. Which operations are supported for supported ValueTypes.
	s.		/// 3. Cost thresholds for alternative implementations of certain operatio
	//		ns.
	// In addition it has a few other components, like information about FP		///
	// immediates.		/// In addition it has a few other components, like information about FP
	//		/// immediates.
			///
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_TARGET_TARGETLOWERING_H		#ifndef LLVM_TARGET_TARGETLOWERING_H
	#define LLVM_TARGET_TARGETLOWERING_H		#define LLVM_TARGET_TARGETLOWERING_H
	#include "llvm/ADT/DenseMap.h"		#include "llvm/ADT/DenseMap.h"
	#include "llvm/CodeGen/DAGCombine.h"		#include "llvm/CodeGen/DAGCombine.h"
	#include "llvm/CodeGen/RuntimeLibcalls.h"		#include "llvm/CodeGen/RuntimeLibcalls.h"
	#include "llvm/CodeGen/SelectionDAGNodes.h"		#include "llvm/CodeGen/SelectionDAGNodes.h"
	#include "llvm/IR/Attributes.h"		#include "llvm/IR/Attributes.h"
	#include "llvm/IR/CallingConv.h"		#include "llvm/IR/CallingConv.h"
	#include "llvm/IR/InlineAsm.h"		#include "llvm/IR/InlineAsm.h"
	#include "llvm/Support/CallSite.h"		#include "llvm/Support/CallSite.h"
	#include "llvm/Support/DebugLoc.h"
	#include "llvm/Target/TargetCallingConv.h"		#include "llvm/Target/TargetCallingConv.h"
	#include "llvm/Target/TargetMachine.h"		#include "llvm/Target/TargetMachine.h"
	#include <climits>		#include <climits>
	#include <map>		#include <map>
	#include <vector>		#include <vector>
	namespace llvm {		namespace llvm {
	class CallInst;		class CallInst;
	class CCState;		class CCState;
	class FastISel;		class FastISel;
	skipping to change at line 71		skipping to change at line 71
	enum Preference {		enum Preference {
	None, // No preference		None, // No preference
	Source, // Follow source order.		Source, // Follow source order.
	RegPressure, // Scheduling for lowest register pressure.		RegPressure, // Scheduling for lowest register pressure.
	Hybrid, // Scheduling for both latency and register pressur e.		Hybrid, // Scheduling for both latency and register pressur e.
	ILP, // Scheduling for ILP in low register pressure mode .		ILP, // Scheduling for ILP in low register pressure mode .
	VLIW // Scheduling for VLIW targets.		VLIW // Scheduling for VLIW targets.
	};		};
	}		}
	/// TargetLoweringBase - This base class for TargetLowering contains the		/// This base class for TargetLowering contains the SelectionDAG-independen
	/// SelectionDAG-independent parts that can be used from the rest of CodeGe		t
	n.		/// parts that can be used from the rest of CodeGen.
	class TargetLoweringBase {		class TargetLoweringBase {
	TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;		TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
	void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;		void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
	public:		public:
	/// LegalizeAction - This enum indicates whether operations are valid for		/// This enum indicates whether operations are valid for a target, and if
	a		not,
	/// target, and if not, what action should be used to make them valid.		/// what action should be used to make them valid.
	enum LegalizeAction {		enum LegalizeAction {
	Legal, // The target natively supports this operation.		Legal, // The target natively supports this operation.
	Promote, // This operation should be executed in a larger type.		Promote, // This operation should be executed in a larger type.
	Expand, // Try to expand this to other ops, otherwise use a libcall .		Expand, // Try to expand this to other ops, otherwise use a libcall .
	Custom // Use the LowerOperation hook to implement custom lowering .		Custom // Use the LowerOperation hook to implement custom lowering .
	};		};
	/// LegalizeTypeAction - This enum indicates whether a types are legal fo		/// This enum indicates whether a types are legal for a target, and if no
	r a		t,
	/// target, and if not, what action should be used to make them valid.		/// what action should be used to make them valid.
	enum LegalizeTypeAction {		enum LegalizeTypeAction {
	TypeLegal, // The target natively supports this type.		TypeLegal, // The target natively supports this type.
	TypePromoteInteger, // Replace this integer with a larger one.		TypePromoteInteger, // Replace this integer with a larger one.
	TypeExpandInteger, // Split this integer into two of half the size.		TypeExpandInteger, // Split this integer into two of half the size.
	TypeSoftenFloat, // Convert this float to a same size integer type.		TypeSoftenFloat, // Convert this float to a same size integer type.
	TypeExpandFloat, // Split this float into two of half the size.		TypeExpandFloat, // Split this float into two of half the size.
	TypeScalarizeVector, // Replace this one-element vector with its elemen t.		TypeScalarizeVector, // Replace this one-element vector with its elemen t.
	TypeSplitVector, // Split this vector into two of half the size.		TypeSplitVector, // Split this vector into two of half the size.
	TypeWidenVector // This vector should be widened into a larger vec tor.		TypeWidenVector // This vector should be widened into a larger vec tor.
	};		};
	/// LegalizeKind holds the legalization kind that needs to happen to EVT		/// LegalizeKind holds the legalization kind that needs to happen to EVT
	/// in order to type-legalize it.		/// in order to type-legalize it.
	typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;		typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
	enum BooleanContent { // How the target represents true/false values.		/// Enum that describes how the target represents true/false values.
			enum BooleanContent {
	UndefinedBooleanContent, // Only bit 0 counts, the rest can hold gar bage.		UndefinedBooleanContent, // Only bit 0 counts, the rest can hold gar bage.
	ZeroOrOneBooleanContent, // All bits zero except for bit 0.		ZeroOrOneBooleanContent, // All bits zero except for bit 0.
	ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.		ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
	};		};
			/// Enum that describes what type of support for selects the target has.
	enum SelectSupportKind {		enum SelectSupportKind {
	ScalarValSelect, // The target supports scalar selects (ex: cmov).		ScalarValSelect, // The target supports scalar selects (ex: cmov).
	ScalarCondVectorVal, // The target supports selects with a scalar cond ition		ScalarCondVectorVal, // The target supports selects with a scalar cond ition
	// and vector values (ex: cmov).		// and vector values (ex: cmov).
	VectorMaskSelect // The target supports vector selects with a vect or		VectorMaskSelect // The target supports vector selects with a vect or
	// mask (ex: x86 blends).		// mask (ex: x86 blends).
	};		};
	static ISD::NodeType getExtendForContent(BooleanContent Content) {		static ISD::NodeType getExtendForContent(BooleanContent Content) {
	switch (Content) {		switch (Content) {
	skipping to change at line 149		skipping to change at line 151
	/// \brief Initialize all of the actions to default values.		/// \brief Initialize all of the actions to default values.
	void initActions();		void initActions();
	public:		public:
	const TargetMachine &getTargetMachine() const { return TM; }		const TargetMachine &getTargetMachine() const { return TM; }
	const DataLayout *getDataLayout() const { return TD; }		const DataLayout *getDataLayout() const { return TD; }
	const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }		const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
	bool isBigEndian() const { return !IsLittleEndian; }		bool isBigEndian() const { return !IsLittleEndian; }
	bool isLittleEndian() const { return IsLittleEndian; }		bool isLittleEndian() const { return IsLittleEndian; }
	// Return the pointer type for the given address space, defaults to
	// the pointer type from the data layout.		/// Return the pointer type for the given address space, defaults to
	// FIXME: The default needs to be removed once all the code is updated.		/// the pointer type from the data layout.
	virtual MVT getPointerTy(uint32_t AS = 0) const { return PointerTy; }		/// FIXME: The default needs to be removed once all the code is updated.
			virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const;
			unsigned getPointerSizeInBits(uint32_t AS = 0) const;
			unsigned getPointerTypeSizeInBits(Type *Ty) const;
	virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;		virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
	EVT getShiftAmountTy(EVT LHSTy) const;		EVT getShiftAmountTy(EVT LHSTy) const;
	/// isSelectExpensive - Return true if the select operation is expensive		/// Returns the type to be used for the index operand of:
	for		/// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
	/// this target.		/// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
			virtual MVT getVectorIdxTy() const {
			return getPointerTy();
			}
			/// Return true if the select operation is expensive for this target.
	bool isSelectExpensive() const { return SelectIsExpensive; }		bool isSelectExpensive() const { return SelectIsExpensive; }
	virtual bool isSelectSupported(SelectSupportKind kind) const { return tru		virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
	e; }		return true;
			}
	/// shouldSplitVectorElementType - Return true if a vector of the given t		/// Return true if a vector of the given type should be split
	ype		/// (TypeSplitVector) instead of promoted (TypePromoteInteger) during typ
	/// should be split (TypeSplitVector) instead of promoted		e
	/// (TypePromoteInteger) during type legalization.		/// legalization.
	virtual bool shouldSplitVectorElementType(EVT VT) const { return false; }		virtual bool shouldSplitVectorElementType(EVT /*VT*/) const { return fals
			e; }
	/// isIntDivCheap() - Return true if integer divide is usually cheaper th		/// Return true if integer divide is usually cheaper than a sequence of
	an		/// several shifts, adds, and multiplies for this target.
	/// a sequence of several shifts, adds, and multiplies for this target.
	bool isIntDivCheap() const { return IntDivIsCheap; }		bool isIntDivCheap() const { return IntDivIsCheap; }
	/// isSlowDivBypassed - Returns true if target has indicated at least one		/// Returns true if target has indicated at least one type should be bypa
	/// type should be bypassed.		ssed.
	bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }		bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
	/// getBypassSlowDivTypes - Returns map of slow types for division or		/// Returns map of slow types for division or remainder with correspondin
	/// remainder with corresponding fast types		g
			/// fast types
	const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() cons t {		const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() cons t {
	return BypassSlowDivWidths;		return BypassSlowDivWidths;
	}		}
	/// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of		/// Return true if pow2 div is cheaper than a chain of srl/add/sra.
	/// srl/add/sra.
	bool isPow2DivCheap() const { return Pow2DivIsCheap; }		bool isPow2DivCheap() const { return Pow2DivIsCheap; }
	/// isJumpExpensive() - Return true if Flow Control is an expensive opera		/// Return true if Flow Control is an expensive operation that should be
	tion		/// avoided.
	/// that should be avoided.
	bool isJumpExpensive() const { return JumpIsExpensive; }		bool isJumpExpensive() const { return JumpIsExpensive; }
	/// isPredictableSelectExpensive - Return true if selects are only cheape		/// Return true if selects are only cheaper than branches if the branch i
	r		s
	/// than branches if the branch is unlikely to be predicted right.		/// unlikely to be predicted right.
	bool isPredictableSelectExpensive() const {		bool isPredictableSelectExpensive() const {
	return PredictableSelectIsExpensive;		return PredictableSelectIsExpensive;
	}		}
	/// getSetCCResultType - Return the ValueType of the result of SETCC		/// isLoadBitCastBeneficial() - Return true if the following transform
	/// operations. Also used to obtain the target's preferred type for		/// is beneficial.
	/// the condition operand of SELECT and BRCOND nodes. In the case of		/// fold (conv (load x)) -> (load (conv*)x)
	/// BRCOND the argument passed is MVT::Other since there are no other		/// On architectures that don't natively support some vector loads effici
	/// operands to get a type hint from.		ently,
	virtual EVT getSetCCResultType(EVT VT) const;		/// casting the load to a smaller vector of larger types and loading
			/// is more efficient, however, this can be undone by optimizations in
	/// getCmpLibcallReturnType - Return the ValueType for comparison		/// dag combiner.
	/// libcalls. Comparions libcalls include floating point comparion calls,		virtual bool isLoadBitCastBeneficial(EVT /* Load */, EVT /* Bitcast */) c
	/// and Ordered/Unordered check calls on floating point numbers.		onst {
			return true;
			}
			/// Return the ValueType of the result of SETCC operations. Also used to
			/// obtain the target's preferred type for the condition operand of SELEC
			T and
			/// BRCOND nodes. In the case of BRCOND the argument passed is MVT::Othe
			r
			/// since there are no other operands to get a type hint from.
			virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
			/// Return the ValueType for comparison libcalls. Comparions libcalls inc
			lude
			/// floating point comparion calls, and Ordered/Unordered check calls on
			/// floating point numbers.
	virtual		virtual
	MVT::SimpleValueType getCmpLibcallReturnType() const;		MVT::SimpleValueType getCmpLibcallReturnType() const;
	/// getBooleanContents - For targets without i1 registers, this gives the		/// For targets without i1 registers, this gives the nature of the high-b
	/// nature of the high-bits of boolean values held in types wider than i1		its
	.		/// of boolean values held in types wider than i1.
			///
	/// "Boolean values" are special true/false values produced by nodes like		/// "Boolean values" are special true/false values produced by nodes like
	/// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND .		/// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND .
	/// Not to be confused with general values promoted from i1.		/// Not to be confused with general values promoted from i1. Some cpus
	/// Some cpus distinguish between vectors of boolean and scalars; the isV		/// distinguish between vectors of boolean and scalars; the isVec paramet
	ec		er
	/// parameter selects between the two kinds. For example on X86 a scalar		/// selects between the two kinds. For example on X86 a scalar boolean s
	/// boolean should be zero extended from i1, while the elements of a vect		hould
	or		/// be zero extended from i1, while the elements of a vector of booleans
	/// of booleans should be sign extended from i1.		/// should be sign extended from i1.
	BooleanContent getBooleanContents(bool isVec) const {		BooleanContent getBooleanContents(bool isVec) const {
	return isVec ? BooleanVectorContents : BooleanContents;		return isVec ? BooleanVectorContents : BooleanContents;
	}		}
	/// getSchedulingPreference - Return target scheduling preference.		/// Return target scheduling preference.
	Sched::Preference getSchedulingPreference() const {		Sched::Preference getSchedulingPreference() const {
	return SchedPreferenceInfo;		return SchedPreferenceInfo;
	}		}
	/// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to		/// Some scheduler, e.g. hybrid, can switch to different scheduling heuri
	/// different scheduling heuristics for different nodes. This function re		stics
	turns		/// for different nodes. This function returns the preference (or none) f
	/// the preference (or none) for the given node.		or
			/// the given node.
	virtual Sched::Preference getSchedulingPreference(SDNode *) const {		virtual Sched::Preference getSchedulingPreference(SDNode *) const {
	return Sched::None;		return Sched::None;
	}		}
	/// getRegClassFor - Return the register class that should be used for th		/// Return the register class that should be used for the specified value
	e		/// type.
	/// specified value type.
	virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {		virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
	const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];		const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
	assert(RC && "This value type is not natively supported!");		assert(RC && "This value type is not natively supported!");
	return RC;		return RC;
	}		}
	/// getRepRegClassFor - Return the 'representative' register class for th		/// Return the 'representative' register class for the specified value
	e		/// type.
	/// specified value type. The 'representative' register class is the larg		///
	est		/// The 'representative' register class is the largest legal super-reg
	/// legal super-reg register class for the register class of the value ty		/// register class for the register class of the value type. For example
	pe.		, on
	/// For example, on i386 the rep register class for i8, i16, and i32 are		/// i386 the rep register class for i8, i16, and i32 are GR32; while the
	GR32;		rep
	/// while the rep register class is GR64 on x86_64.		/// register class is GR64 on x86_64.
	virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {		virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
	const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];		const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
	return RC;		return RC;
	}		}
	/// getRepRegClassCostFor - Return the cost of the 'representative' regis		/// Return the cost of the 'representative' register class for the specif
	ter		ied
	/// class for the specified value type.		/// value type.
	virtual uint8_t getRepRegClassCostFor(MVT VT) const {		virtual uint8_t getRepRegClassCostFor(MVT VT) const {
	return RepRegClassCostForVT[VT.SimpleTy];		return RepRegClassCostForVT[VT.SimpleTy];
	}		}
	/// isTypeLegal - Return true if the target has native support for the		/// Return true if the target has native support for the specified value
	/// specified value type. This means that it has a register that directl		type.
	y		/// This means that it has a register that directly holds it without
	/// holds it without promotions or expansions.		/// promotions or expansions.
	bool isTypeLegal(EVT VT) const {		bool isTypeLegal(EVT VT) const {
	assert(!VT.isSimple() ||		assert(!VT.isSimple() ||
	(unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassFor VT));		(unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassFor VT));
	return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;		return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
	}		}
	class ValueTypeActionImpl {		class ValueTypeActionImpl {
	/// ValueTypeActions - For each value type, keep a LegalizeTypeAction e num		/// ValueTypeActions - For each value type, keep a LegalizeTypeAction e num
	/// that indicates how instruction selection should deal with the type.		/// that indicates how instruction selection should deal with the type.
	uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];		uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
	skipping to change at line 291		skipping to change at line 315
	void setTypeAction(MVT VT, LegalizeTypeAction Action) {		void setTypeAction(MVT VT, LegalizeTypeAction Action) {
	unsigned I = VT.SimpleTy;		unsigned I = VT.SimpleTy;
	ValueTypeActions[I] = Action;		ValueTypeActions[I] = Action;
	}		}
	};		};
	const ValueTypeActionImpl &getValueTypeActions() const {		const ValueTypeActionImpl &getValueTypeActions() const {
	return ValueTypeActions;		return ValueTypeActions;
	}		}
	/// getTypeAction - Return how we should legalize values of this type, ei		/// Return how we should legalize values of this type, either it is alrea
	ther		dy
	/// it is already legal (return 'Legal') or we need to promote it to a la		/// legal (return 'Legal') or we need to promote it to a larger type (ret
	rger		urn
	/// type (return 'Promote'), or we need to expand it into multiple regist		/// 'Promote'), or we need to expand it into multiple registers of smalle
	ers		r
	/// of smaller integer type (return 'Expand'). 'Custom' is not an option		/// integer type (return 'Expand'). 'Custom' is not an option.
	.
	LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {		LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
	return getTypeConversion(Context, VT).first;		return getTypeConversion(Context, VT).first;
	}		}
	LegalizeTypeAction getTypeAction(MVT VT) const {		LegalizeTypeAction getTypeAction(MVT VT) const {
	return ValueTypeActions.getTypeAction(VT);		return ValueTypeActions.getTypeAction(VT);
	}		}
	/// getTypeToTransformTo - For types supported by the target, this is an		/// For types supported by the target, this is an identity function. For
	/// identity function. For types that must be promoted to larger types,		/// types that must be promoted to larger types, this returns the larger
	this		type
	/// returns the larger type to promote to. For integer types that are la		/// to promote to. For integer types that are larger than the largest in
	rger		teger
	/// than the largest integer register, this contains one step in the expa		/// register, this contains one step in the expansion to get to the small
	nsion		er
	/// to get to the smaller register. For illegal floating point types, thi		/// register. For illegal floating point types, this returns the integer
	s		type
	/// returns the integer type to transform to.		/// to transform to.
	EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {		EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
	return getTypeConversion(Context, VT).second;		return getTypeConversion(Context, VT).second;
	}		}
	/// getTypeToExpandTo - For types supported by the target, this is an		/// For types supported by the target, this is an identity function. For
	/// identity function. For types that must be expanded (i.e. integer typ		/// types that must be expanded (i.e. integer types that are larger than
	es		the
	/// that are larger than the largest integer register or illegal floating		/// largest integer register or illegal floating point types), this retur
	/// point types), this returns the largest legal type it will be expanded		ns
	to.		/// the largest legal type it will be expanded to.
	EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {		EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
	assert(!VT.isVector());		assert(!VT.isVector());
	while (true) {		while (true) {
	switch (getTypeAction(Context, VT)) {		switch (getTypeAction(Context, VT)) {
	case TypeLegal:		case TypeLegal:
	return VT;		return VT;
	case TypeExpandInteger:		case TypeExpandInteger:
	VT = getTypeToTransformTo(Context, VT);		VT = getTypeToTransformTo(Context, VT);
	break;		break;
	default:		default:
	llvm_unreachable("Type is not legal nor is it to be expanded!");		llvm_unreachable("Type is not legal nor is it to be expanded!");
	}		}
	}		}
	}		}
	/// getVectorTypeBreakdown - Vector types are broken down into some numbe		/// Vector types are broken down into some number of legal first class ty
	r of		pes.
	/// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f3		/// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or
	2		8
	/// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP s		/// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i6
	tack.		4
	/// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and		/// turns into 4 EVT::i32 values with both PPC and X86.
	X86.
	///		///
	/// This method returns the number of registers needed, and the VT for ea ch		/// This method returns the number of registers needed, and the VT for ea ch
	/// register. It also returns the VT and quantity of the intermediate va lues		/// register. It also returns the VT and quantity of the intermediate va lues
	/// before they are promoted/expanded.		/// before they are promoted/expanded.
	///
	unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,		unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
	EVT &IntermediateVT,		EVT &IntermediateVT,
	unsigned &NumIntermediates,		unsigned &NumIntermediates,
	MVT &RegisterVT) const;		MVT &RegisterVT) const;
	/// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
	/// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
	/// this is the case, it returns true and store the intrinsic
	/// information into the IntrinsicInfo that was passed to the function.
	struct IntrinsicInfo {		struct IntrinsicInfo {
	unsigned opc; // target opcode		unsigned opc; // target opcode
	EVT memVT; // memory VT		EVT memVT; // memory VT
	const Value* ptrVal; // value representing memory location		const Value* ptrVal; // value representing memory location
	int offset; // offset off of ptrVal		int offset; // offset off of ptrVal
	unsigned align; // alignment		unsigned align; // alignment
	bool vol; // is volatile?		bool vol; // is volatile?
	bool readMem; // reads memory?		bool readMem; // reads memory?
	bool writeMem; // writes memory?		bool writeMem; // writes memory?
	};		};
			/// Given an intrinsic, checks if on the target the intrinsic will need t
			o map
			/// to a MemIntrinsicNode (touches memory). If this is the case, it retur
			ns
			/// true and store the intrinsic information into the IntrinsicInfo that
			was
			/// passed to the function.
	virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,		virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
	unsigned /*Intrinsic*/) const {		unsigned /*Intrinsic*/) const {
	return false;		return false;
	}		}
	/// isFPImmLegal - Returns true if the target can instruction select the		/// Returns true if the target can instruction select the specified FP
	/// specified FP immediate natively. If false, the legalizer will materia		/// immediate natively. If false, the legalizer will materialize the FP
	lize		/// immediate as a load from a constant pool.
	/// the FP immediate as a load from a constant pool.
	virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {		virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
	return false;		return false;
	}		}
	/// isShuffleMaskLegal - Targets can use this to indicate that they only		/// Targets can use this to indicate that they only support *some*
	/// support *some* VECTOR_SHUFFLE operations, those with specific masks.		/// VECTOR_SHUFFLE operations, those with specific masks. By default, if
	/// By default, if a target supports the VECTOR_SHUFFLE node, all mask va		a
	lues		/// target supports the VECTOR_SHUFFLE node, all mask values are assumed
	/// are assumed to be legal.		to be
			/// legal.
	virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,		virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
	EVT /*VT*/) const {		EVT /*VT*/) const {
	return true;		return true;
	}		}
	/// canOpTrap - Returns true if the operation can trap for the value type		/// Returns true if the operation can trap for the value type.
	.		///
	/// VT must be a legal type. By default, we optimistically assume most		/// VT must be a legal type. By default, we optimistically assume most
	/// operations don't trap except for divide and remainder.		/// operations don't trap except for divide and remainder.
	virtual bool canOpTrap(unsigned Op, EVT VT) const;		virtual bool canOpTrap(unsigned Op, EVT VT) const;
	/// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is		/// Similar to isShuffleMaskLegal. This is used by Targets can use this t
	/// used by Targets can use this to indicate if there is a suitable		o
	/// VECTOR_SHUFFLE that can be used to replace a VAND with a constant		/// indicate if there is a suitable VECTOR_SHUFFLE that can be used to re
	/// pool entry.		place
			/// a VAND with a constant pool entry.
	virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,		virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
	EVT /*VT*/) const {		EVT /*VT*/) const {
	return false;		return false;
	}		}
	/// getOperationAction - Return how this operation should be treated: eit		/// Return how this operation should be treated: either it is legal, need
	her		s to
	/// it is legal, needs to be promoted to a larger size, needs to be		/// be promoted to a larger size, needs to be expanded to some other code
	/// expanded to some other code sequence, or the target has a custom expa		/// sequence, or the target has a custom expander for it.
	nder
	/// for it.
	LegalizeAction getOperationAction(unsigned Op, EVT VT) const {		LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
	if (VT.isExtended()) return Expand;		if (VT.isExtended()) return Expand;
	// If a target-specific SDNode requires legalization, require the targe t		// If a target-specific SDNode requires legalization, require the targe t
	// to provide custom legalization for it.		// to provide custom legalization for it.
	if (Op > array_lengthof(OpActions[0])) return Custom;		if (Op > array_lengthof(OpActions[0])) return Custom;
	unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;		unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
	return (LegalizeAction)OpActions[I][Op];		return (LegalizeAction)OpActions[I][Op];
	}		}
	/// isOperationLegalOrCustom - Return true if the specified operation is		/// Return true if the specified operation is legal on this target or can
	/// legal on this target or can be made legal with custom lowering. This		be
	/// is used to help guide high-level lowering decisions.		/// made legal with custom lowering. This is used to help guide high-leve
			l
			/// lowering decisions.
	bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {		bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
	return (VT == MVT::Other || isTypeLegal(VT)) &&		return (VT == MVT::Other || isTypeLegal(VT)) &&
	(getOperationAction(Op, VT) == Legal ||		(getOperationAction(Op, VT) == Legal ||
	getOperationAction(Op, VT) == Custom);		getOperationAction(Op, VT) == Custom);
	}		}
	/// isOperationLegalOrPromote - Return true if the specified operation is		/// Return true if the specified operation is legal on this target or can
	/// legal on this target or can be made legal using promotion. This		be
	/// is used to help guide high-level lowering decisions.		/// made legal using promotion. This is used to help guide high-level low
			ering
			/// decisions.
	bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {		bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
	return (VT == MVT::Other || isTypeLegal(VT)) &&		return (VT == MVT::Other || isTypeLegal(VT)) &&
	(getOperationAction(Op, VT) == Legal ||		(getOperationAction(Op, VT) == Legal ||
	getOperationAction(Op, VT) == Promote);		getOperationAction(Op, VT) == Promote);
	}		}
	/// isOperationExpand - Return true if the specified operation is illegal		/// Return true if the specified operation is illegal on this target or
	on		/// unlikely to be made legal with custom lowering. This is used to help
	/// this target or unlikely to be made legal with custom lowering. This i		guide
	s		/// high-level lowering decisions.
	/// used to help guide high-level lowering decisions.
	bool isOperationExpand(unsigned Op, EVT VT) const {		bool isOperationExpand(unsigned Op, EVT VT) const {
	return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);		return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
	}		}
	/// isOperationLegal - Return true if the specified operation is legal on		/// Return true if the specified operation is legal on this target.
	this
	/// target.
	bool isOperationLegal(unsigned Op, EVT VT) const {		bool isOperationLegal(unsigned Op, EVT VT) const {
	return (VT == MVT::Other || isTypeLegal(VT)) &&		return (VT == MVT::Other || isTypeLegal(VT)) &&
	getOperationAction(Op, VT) == Legal;		getOperationAction(Op, VT) == Legal;
	}		}
	/// getLoadExtAction - Return how this load with extension should be trea		/// Return how this load with extension should be treated: either it is l
	ted:		egal,
	/// either it is legal, needs to be promoted to a larger size, needs to b		/// needs to be promoted to a larger size, needs to be expanded to some o
	e		ther
	/// expanded to some other code sequence, or the target has a custom expa		/// code sequence, or the target has a custom expander for it.
	nder
	/// for it.
	LegalizeAction getLoadExtAction(unsigned ExtType, MVT VT) const {		LegalizeAction getLoadExtAction(unsigned ExtType, MVT VT) const {
	assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&		assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
	"Table isn't big enough!");		"Table isn't big enough!");
	return (LegalizeAction)LoadExtActions[VT.SimpleTy][ExtType];		return (LegalizeAction)LoadExtActions[VT.SimpleTy][ExtType];
	}		}
	/// isLoadExtLegal - Return true if the specified load with extension is		/// Return true if the specified load with extension is legal on this tar
	legal		get.
	/// on this target.
	bool isLoadExtLegal(unsigned ExtType, EVT VT) const {		bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
	return VT.isSimple() &&		return VT.isSimple() &&
	getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal;		getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal;
	}		}
	/// getTruncStoreAction - Return how this store with truncation should be		/// Return how this store with truncation should be treated: either it is
	/// treated: either it is legal, needs to be promoted to a larger size, n		/// legal, needs to be promoted to a larger size, needs to be expanded to
	eeds		some
	/// to be expanded to some other code sequence, or the target has a custo		/// other code sequence, or the target has a custom expander for it.
	m
	/// expander for it.
	LegalizeAction getTruncStoreAction(MVT ValVT, MVT MemVT) const {		LegalizeAction getTruncStoreAction(MVT ValVT, MVT MemVT) const {
	assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&		assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
	"Table isn't big enough!");		"Table isn't big enough!");
	return (LegalizeAction)TruncStoreActions[ValVT.SimpleTy]		return (LegalizeAction)TruncStoreActions[ValVT.SimpleTy]
	[MemVT.SimpleTy];		[MemVT.SimpleTy];
	}		}
	/// isTruncStoreLegal - Return true if the specified store with truncatio		/// Return true if the specified store with truncation is legal on this
	n is		/// target.
	/// legal on this target.
	bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {		bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
	return isTypeLegal(ValVT) && MemVT.isSimple() &&		return isTypeLegal(ValVT) && MemVT.isSimple() &&
	getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Lega l;		getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Lega l;
	}		}
	/// getIndexedLoadAction - Return how the indexed load should be treated:		/// Return how the indexed load should be treated: either it is legal, ne
	/// either it is legal, needs to be promoted to a larger size, needs to b		eds
	e		/// to be promoted to a larger size, needs to be expanded to some other c
	/// expanded to some other code sequence, or the target has a custom expa		ode
	nder		/// sequence, or the target has a custom expander for it.
	/// for it.
	LegalizeAction		LegalizeAction
	getIndexedLoadAction(unsigned IdxMode, MVT VT) const {		getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
	assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&		assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
	"Table isn't big enough!");		"Table isn't big enough!");
	unsigned Ty = (unsigned)VT.SimpleTy;		unsigned Ty = (unsigned)VT.SimpleTy;
	return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);		return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
	}		}
	/// isIndexedLoadLegal - Return true if the specified indexed load is leg		/// Return true if the specified indexed load is legal on this target.
	al
	/// on this target.
	bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {		bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
	return VT.isSimple() &&		return VT.isSimple() &&
	(getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||		(getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
	getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);		getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
	}		}
	/// getIndexedStoreAction - Return how the indexed store should be treate		/// Return how the indexed store should be treated: either it is legal, n
	d:		eeds
	/// either it is legal, needs to be promoted to a larger size, needs to b		/// to be promoted to a larger size, needs to be expanded to some other c
	e		ode
	/// expanded to some other code sequence, or the target has a custom expa		/// sequence, or the target has a custom expander for it.
	nder
	/// for it.
	LegalizeAction		LegalizeAction
	getIndexedStoreAction(unsigned IdxMode, MVT VT) const {		getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
	assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&		assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
	"Table isn't big enough!");		"Table isn't big enough!");
	unsigned Ty = (unsigned)VT.SimpleTy;		unsigned Ty = (unsigned)VT.SimpleTy;
	return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);		return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
	}		}
	/// isIndexedStoreLegal - Return true if the specified indexed load is le		/// Return true if the specified indexed load is legal on this target.
	gal
	/// on this target.
	bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {		bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
	return VT.isSimple() &&		return VT.isSimple() &&
	(getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||		(getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
	getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);		getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
	}		}
	/// getCondCodeAction - Return how the condition code should be treated:		/// Return how the condition code should be treated: either it is legal,
	/// either it is legal, needs to be expanded to some other code sequence,		needs
	/// or the target has a custom expander for it.		/// to be expanded to some other code sequence, or the target has a custo
			m
			/// expander for it.
	LegalizeAction		LegalizeAction
	getCondCodeAction(ISD::CondCode CC, MVT VT) const {		getCondCodeAction(ISD::CondCode CC, MVT VT) const {
	assert((unsigned)CC < array_lengthof(CondCodeActions) &&		assert((unsigned)CC < array_lengthof(CondCodeActions) &&
	(unsigned)VT.SimpleTy < sizeof(CondCodeActions[0])*4 &&		((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0] ) &&
	"Table isn't big enough!");		"Table isn't big enough!");
	/// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 6		// See setCondCodeAction for how this is encoded.
	4bit		uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
	/// value and the upper 27 bits index into the second dimension of the		uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
	/// array to select what 64bit value to use.		LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
	LegalizeAction Action = (LegalizeAction)
	((CondCodeActions[CC][VT.SimpleTy >> 5] >> (2*(VT.SimpleTy & 0x1F)))
	& 3);
	assert(Action != Promote && "Can't promote condition code!");		assert(Action != Promote && "Can't promote condition code!");
	return Action;		return Action;
	}		}
	/// isCondCodeLegal - Return true if the specified condition code is lega		/// Return true if the specified condition code is legal on this target.
	l
	/// on this target.
	bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {		bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
	return		return
	getCondCodeAction(CC, VT) == Legal ||		getCondCodeAction(CC, VT) == Legal ||
	getCondCodeAction(CC, VT) == Custom;		getCondCodeAction(CC, VT) == Custom;
	}		}
	/// getTypeToPromoteTo - If the action for this operation is to promote,		/// If the action for this operation is to promote, this method returns t
	this		he
	/// method returns the ValueType to promote to.		/// ValueType to promote to.
	MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {		MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
	assert(getOperationAction(Op, VT) == Promote &&		assert(getOperationAction(Op, VT) == Promote &&
	"This operation isn't promoted!");		"This operation isn't promoted!");
	// See if this has an explicit type specified.		// See if this has an explicit type specified.
	std::map<std::pair<unsigned, MVT::SimpleValueType>,		std::map<std::pair<unsigned, MVT::SimpleValueType>,
	MVT::SimpleValueType>::const_iterator PTTI =		MVT::SimpleValueType>::const_iterator PTTI =
	PromoteToType.find(std::make_pair(Op, VT.SimpleTy));		PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
	if (PTTI != PromoteToType.end()) return PTTI->second;		if (PTTI != PromoteToType.end()) return PTTI->second;
	skipping to change at line 565		skipping to change at line 577
	MVT NVT = VT;		MVT NVT = VT;
	do {		do {
	NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);		NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
	assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&		assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
	"Didn't find type to promote to!");		"Didn't find type to promote to!");
	} while (!isTypeLegal(NVT) ||		} while (!isTypeLegal(NVT) ||
	getOperationAction(Op, NVT) == Promote);		getOperationAction(Op, NVT) == Promote);
	return NVT;		return NVT;
	}		}
	/// getValueType - Return the EVT corresponding to this LLVM type.		/// Return the EVT corresponding to this LLVM type. This is fixed by the
	/// This is fixed by the LLVM operations except for the pointer size. If		LLVM
	/// AllowUnknown is true, this will return MVT::Other for types with no E		/// operations except for the pointer size. If AllowUnknown is true, thi
	VT		s
	/// counterpart (e.g. structs), otherwise it will assert.		/// will return MVT::Other for types with no EVT counterpart (e.g. struct
			s),
			/// otherwise it will assert.
	EVT getValueType(Type *Ty, bool AllowUnknown = false) const {		EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
	// Lower scalar pointers to native pointer types.		// Lower scalar pointers to native pointer types.
	if (Ty->isPointerTy()) return PointerTy;		if (PointerType *PTy = dyn_cast<PointerType>(Ty))
			return getPointerTy(PTy->getAddressSpace());
	if (Ty->isVectorTy()) {		if (Ty->isVectorTy()) {
	VectorType *VTy = cast<VectorType>(Ty);		VectorType *VTy = cast<VectorType>(Ty);
	Type *Elm = VTy->getElementType();		Type *Elm = VTy->getElementType();
	// Lower vectors of pointers to native pointer types.		// Lower vectors of pointers to native pointer types.
	if (Elm->isPointerTy())		if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
	Elm = EVT(PointerTy).getTypeForEVT(Ty->getContext());		EVT PointerTy(getPointerTy(PT->getAddressSpace()));
			Elm = PointerTy.getTypeForEVT(Ty->getContext());
			}
	return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),		return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
	VTy->getNumElements());		VTy->getNumElements());
	}		}
	return EVT::getEVT(Ty, AllowUnknown);		return EVT::getEVT(Ty, AllowUnknown);
	}		}
	/// Return the MVT corresponding to this LLVM type. See getValueType.		/// Return the MVT corresponding to this LLVM type. See getValueType.
	MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const {		MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const {
	return getValueType(Ty, AllowUnknown).getSimpleVT();		return getValueType(Ty, AllowUnknown).getSimpleVT();
	}		}
	/// getByValTypeAlignment - Return the desired alignment for ByVal aggreg		/// Return the desired alignment for ByVal aggregate function arguments i
	ate		n the
	/// function arguments in the caller parameter area. This is the actual		/// caller parameter area. This is the actual alignment, not its logarit
	/// alignment, not its logarithm.		hm.
	virtual unsigned getByValTypeAlignment(Type *Ty) const;		virtual unsigned getByValTypeAlignment(Type *Ty) const;
	/// getRegisterType - Return the type of registers that this ValueType wi		/// Return the type of registers that this ValueType will eventually requ
	ll		ire.
	/// eventually require.
	MVT getRegisterType(MVT VT) const {		MVT getRegisterType(MVT VT) const {
	assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));		assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
	return RegisterTypeForVT[VT.SimpleTy];		return RegisterTypeForVT[VT.SimpleTy];
	}		}
	/// getRegisterType - Return the type of registers that this ValueType wi		/// Return the type of registers that this ValueType will eventually requ
	ll		ire.
	/// eventually require.
	MVT getRegisterType(LLVMContext &Context, EVT VT) const {		MVT getRegisterType(LLVMContext &Context, EVT VT) const {
	if (VT.isSimple()) {		if (VT.isSimple()) {
	assert((unsigned)VT.getSimpleVT().SimpleTy <		assert((unsigned)VT.getSimpleVT().SimpleTy <
	array_lengthof(RegisterTypeForVT));		array_lengthof(RegisterTypeForVT));
	return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];		return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
	}		}
	if (VT.isVector()) {		if (VT.isVector()) {
	EVT VT1;		EVT VT1;
	MVT RegisterVT;		MVT RegisterVT;
	unsigned NumIntermediates;		unsigned NumIntermediates;
	(void)getVectorTypeBreakdown(Context, VT, VT1,		(void)getVectorTypeBreakdown(Context, VT, VT1,
	NumIntermediates, RegisterVT);		NumIntermediates, RegisterVT);
	return RegisterVT;		return RegisterVT;
	}		}
	if (VT.isInteger()) {		if (VT.isInteger()) {
	return getRegisterType(Context, getTypeToTransformTo(Context, VT));		return getRegisterType(Context, getTypeToTransformTo(Context, VT));
	}		}
	llvm_unreachable("Unsupported extended type!");		llvm_unreachable("Unsupported extended type!");
	}		}
	/// getNumRegisters - Return the number of registers that this ValueType		/// Return the number of registers that this ValueType will eventually
	will		/// require.
	/// eventually require. This is one for any types promoted to live in la		///
	rger		/// This is one for any types promoted to live in larger registers, but m
	/// registers, but may be more than one for types (like i64) that are spl		ay be
	it		/// more than one for types (like i64) that are split into pieces. For t
	/// into pieces. For types like i140, which are first promoted then expa		ypes
	nded,		/// like i140, which are first promoted then expanded, it is the number o
	/// it is the number of registers needed to hold all the bits of the orig		f
	inal		/// registers needed to hold all the bits of the original type. For an i
	/// type. For an i140 on a 32 bit machine this means 5 registers.		140
			/// on a 32 bit machine this means 5 registers.
	unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {		unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
	if (VT.isSimple()) {		if (VT.isSimple()) {
	assert((unsigned)VT.getSimpleVT().SimpleTy <		assert((unsigned)VT.getSimpleVT().SimpleTy <
	array_lengthof(NumRegistersForVT));		array_lengthof(NumRegistersForVT));
	return NumRegistersForVT[VT.getSimpleVT().SimpleTy];		return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
	}		}
	if (VT.isVector()) {		if (VT.isVector()) {
	EVT VT1;		EVT VT1;
	MVT VT2;		MVT VT2;
	unsigned NumIntermediates;		unsigned NumIntermediates;
	return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2 );		return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2 );
	}		}
	if (VT.isInteger()) {		if (VT.isInteger()) {
	unsigned BitWidth = VT.getSizeInBits();		unsigned BitWidth = VT.getSizeInBits();
	unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();		unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
	return (BitWidth + RegWidth - 1) / RegWidth;		return (BitWidth + RegWidth - 1) / RegWidth;
	}		}
	llvm_unreachable("Unsupported extended type!");		llvm_unreachable("Unsupported extended type!");
	}		}
	/// ShouldShrinkFPConstant - If true, then instruction selection should		/// If true, then instruction selection should seek to shrink the FP cons
	/// seek to shrink the FP constant of the specified type to a smaller typ		tant
	e		/// of the specified type to a smaller type in order to save space and /
	/// in order to save space and / or reduce runtime.		or
			/// reduce runtime.
	virtual bool ShouldShrinkFPConstant(EVT) const { return true; }		virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
	/// hasTargetDAGCombine - If true, the target has custom DAG combine		/// If true, the target has custom DAG combine transformations that it ca
	/// transformations that it can perform for the specified node.		n
			/// perform for the specified node.
	bool hasTargetDAGCombine(ISD::NodeType NT) const {		bool hasTargetDAGCombine(ISD::NodeType NT) const {
	assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));		assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
	return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));		return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
	}		}
			/// \brief Get maximum # of store operations permitted for llvm.memset
			///
	/// This function returns the maximum number of store operations permitte d		/// This function returns the maximum number of store operations permitte d
	/// to replace a call to llvm.memset. The value is set by the target at t he		/// to replace a call to llvm.memset. The value is set by the target at t he
	/// performance threshold for such a replacement. If OptSize is true,		/// performance threshold for such a replacement. If OptSize is true,
	/// return the limit for functions that have OptSize attribute.		/// return the limit for functions that have OptSize attribute.
	/// @brief Get maximum # of store operations permitted for llvm.memset
	unsigned getMaxStoresPerMemset(bool OptSize) const {		unsigned getMaxStoresPerMemset(bool OptSize) const {
	return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;		return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
	}		}
			/// \brief Get maximum # of store operations permitted for llvm.memcpy
			///
	/// This function returns the maximum number of store operations permitte d		/// This function returns the maximum number of store operations permitte d
	/// to replace a call to llvm.memcpy. The value is set by the target at t he		/// to replace a call to llvm.memcpy. The value is set by the target at t he
	/// performance threshold for such a replacement. If OptSize is true,		/// performance threshold for such a replacement. If OptSize is true,
	/// return the limit for functions that have OptSize attribute.		/// return the limit for functions that have OptSize attribute.
	/// @brief Get maximum # of store operations permitted for llvm.memcpy
	unsigned getMaxStoresPerMemcpy(bool OptSize) const {		unsigned getMaxStoresPerMemcpy(bool OptSize) const {
	return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;		return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
	}		}
			/// \brief Get maximum # of store operations permitted for llvm.memmove
			///
	/// This function returns the maximum number of store operations permitte d		/// This function returns the maximum number of store operations permitte d
	/// to replace a call to llvm.memmove. The value is set by the target at the		/// to replace a call to llvm.memmove. The value is set by the target at the
	/// performance threshold for such a replacement. If OptSize is true,		/// performance threshold for such a replacement. If OptSize is true,
	/// return the limit for functions that have OptSize attribute.		/// return the limit for functions that have OptSize attribute.
	/// @brief Get maximum # of store operations permitted for llvm.memmove
	unsigned getMaxStoresPerMemmove(bool OptSize) const {		unsigned getMaxStoresPerMemmove(bool OptSize) const {
	return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;		return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
	}		}
			/// \brief Determine if the target supports unaligned memory accesses.
			///
	/// This function returns true if the target allows unaligned memory acce sses.		/// This function returns true if the target allows unaligned memory acce sses.
	/// of the specified type. If true, it also returns whether the unaligned		/// of the specified type. If true, it also returns whether the unaligned
	/// memory access is "fast" in the second argument by reference. This is used,		/// memory access is "fast" in the second argument by reference. This is used,
	/// for example, in situations where an array copy/move/set is converted to a		/// for example, in situations where an array copy/move/set is converted to a
	/// sequence of store operations. It's use helps to ensure that such		/// sequence of store operations. It's use helps to ensure that such
	/// replacements don't generate code that causes an alignment error (tra p) on		/// replacements don't generate code that causes an alignment error (trap ) on
	/// the target machine.		/// the target machine.
	/// @brief Determine if the target supports unaligned memory accesses.		virtual bool allowsUnalignedMemoryAccesses(EVT, bool * /*Fast*/ = 0) cons
	virtual bool allowsUnalignedMemoryAccesses(EVT, bool *Fast = 0) const {		t {
	return false;		return false;
	}		}
	/// getOptimalMemOpType - Returns the target specific optimal type for lo		/// Returns the target specific optimal type for load and store operation
	ad		s as
	/// and store operations as a result of memset, memcpy, and memmove		/// a result of memset, memcpy, and memmove lowering.
	/// lowering. If DstAlign is zero that means it's safe to destination		///
	/// alignment can satisfy any constraint. Similarly if SrcAlign is zero i		/// If DstAlign is zero that means it's safe to destination alignment can
	t		/// satisfy any constraint. Similarly if SrcAlign is zero it means there
	/// means there isn't a need to check it against alignment requirement,		isn't
	/// probably because the source does not need to be loaded. If 'IsMemset'		/// a need to check it against alignment requirement, probably because th
	is		e
	/// true, that means it's expanding a memset. If 'ZeroMemset' is true, th		/// source does not need to be loaded. If 'IsMemset' is true, that means
	at		it's
	/// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the mem		/// expanding a memset. If 'ZeroMemset' is true, that means it's a memset
	cpy		of
	/// source is constant so it does not need to be loaded.		/// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant
	/// It returns EVT::Other if the type should be determined using generic		so it
	/// target-independent logic.		/// does not need to be loaded. It returns EVT::Other if the type should
			be
			/// determined using generic target-independent logic.
	virtual EVT getOptimalMemOpType(uint64_t /*Size*/,		virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
	unsigned /*DstAlign*/, unsigned /*SrcAlig n*/,		unsigned /*DstAlign*/, unsigned /*SrcAlig n*/,
	bool /*IsMemset*/,		bool /*IsMemset*/,
	bool /*ZeroMemset*/,		bool /*ZeroMemset*/,
	bool /*MemcpyStrSrc*/,		bool /*MemcpyStrSrc*/,
	MachineFunction &/*MF*/) const {		MachineFunction &/*MF*/) const {
	return MVT::Other;		return MVT::Other;
	}		}
	/// isSafeMemOpType - Returns true if it's safe to use load / store of th		/// Returns true if it's safe to use load / store of the specified type t
	e		o
	/// specified type to expand memcpy / memset inline. This is mostly true		/// expand memcpy / memset inline.
	/// for all types except for some special cases. For example, on X86		///
	/// targets without SSE2 f64 load / store are done with fldl / fstpl whic		/// This is mostly true for all types except for some special cases. For
	h		/// example, on X86 targets without SSE2 f64 load / store are done with f
	/// also does type conversion. Note the specified type doesn't have to be		ldl /
	/// legal as the hook is used before type legalization.		/// fstpl which also does type conversion. Note the specified type doesn'
	virtual bool isSafeMemOpType(MVT VT) const {		t
	return true;		/// have to be legal as the hook is used before type legalization.
	}		virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
	/// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp		/// Determine if we should use _setjmp or setjmp to implement llvm.setjmp
	/// to implement llvm.setjmp.		.
	bool usesUnderscoreSetJmp() const {		bool usesUnderscoreSetJmp() const {
	return UseUnderscoreSetJmp;		return UseUnderscoreSetJmp;
	}		}
	/// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjm		/// Determine if we should use _longjmp or longjmp to implement llvm.long
	p		jmp.
	/// to implement llvm.longjmp.
	bool usesUnderscoreLongJmp() const {		bool usesUnderscoreLongJmp() const {
	return UseUnderscoreLongJmp;		return UseUnderscoreLongJmp;
	}		}
	/// supportJumpTables - return whether the target can generate code for		/// Return whether the target can generate code for jump tables.
	/// jump tables.
	bool supportJumpTables() const {		bool supportJumpTables() const {
	return SupportJumpTables;		return SupportJumpTables;
	}		}
	/// getMinimumJumpTableEntries - return integer threshold on number of		/// Return integer threshold on number of blocks to use jump tables rathe
	/// blocks to use jump tables rather than if sequence.		r
			/// than if sequence.
	int getMinimumJumpTableEntries() const {		int getMinimumJumpTableEntries() const {
	return MinimumJumpTableEntries;		return MinimumJumpTableEntries;
	}		}
	/// getStackPointerRegisterToSaveRestore - If a physical register, this		/// If a physical register, this specifies the register that
	/// specifies the register that llvm.savestack/llvm.restorestack should s		/// llvm.savestack/llvm.restorestack should save and restore.
	ave
	/// and restore.
	unsigned getStackPointerRegisterToSaveRestore() const {		unsigned getStackPointerRegisterToSaveRestore() const {
	return StackPointerRegisterToSaveRestore;		return StackPointerRegisterToSaveRestore;
	}		}
	/// getExceptionPointerRegister - If a physical register, this returns		/// If a physical register, this returns the register that receives the
	/// the register that receives the exception address on entry to a landin		/// exception address on entry to a landing pad.
	g
	/// pad.
	unsigned getExceptionPointerRegister() const {		unsigned getExceptionPointerRegister() const {
	return ExceptionPointerRegister;		return ExceptionPointerRegister;
	}		}
	/// getExceptionSelectorRegister - If a physical register, this returns		/// If a physical register, this returns the register that receives the
	/// the register that receives the exception typeid on entry to a landing		/// exception typeid on entry to a landing pad.
	/// pad.
	unsigned getExceptionSelectorRegister() const {		unsigned getExceptionSelectorRegister() const {
	return ExceptionSelectorRegister;		return ExceptionSelectorRegister;
	}		}
	/// getJumpBufSize - returns the target's jmp_buf size in bytes (if never		/// Returns the target's jmp_buf size in bytes (if never set, the default
	/// set, the default is 200)		is
			/// 200)
	unsigned getJumpBufSize() const {		unsigned getJumpBufSize() const {
	return JumpBufSize;		return JumpBufSize;
	}		}
	/// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes		/// Returns the target's jmp_buf alignment in bytes (if never set, the de
	/// (if never set, the default is 0)		fault
			/// is 0)
	unsigned getJumpBufAlignment() const {		unsigned getJumpBufAlignment() const {
	return JumpBufAlignment;		return JumpBufAlignment;
	}		}
	/// getMinStackArgumentAlignment - return the minimum stack alignment of		/// Return the minimum stack alignment of an argument.
	an
	/// argument.
	unsigned getMinStackArgumentAlignment() const {		unsigned getMinStackArgumentAlignment() const {
	return MinStackArgumentAlignment;		return MinStackArgumentAlignment;
	}		}
	/// getMinFunctionAlignment - return the minimum function alignment.		/// Return the minimum function alignment.
	///
	unsigned getMinFunctionAlignment() const {		unsigned getMinFunctionAlignment() const {
	return MinFunctionAlignment;		return MinFunctionAlignment;
	}		}
	/// getPrefFunctionAlignment - return the preferred function alignment.		/// Return the preferred function alignment.
	///
	unsigned getPrefFunctionAlignment() const {		unsigned getPrefFunctionAlignment() const {
	return PrefFunctionAlignment;		return PrefFunctionAlignment;
	}		}
	/// getPrefLoopAlignment - return the preferred loop alignment.		/// Return the preferred loop alignment.
	///
	unsigned getPrefLoopAlignment() const {		unsigned getPrefLoopAlignment() const {
	return PrefLoopAlignment;		return PrefLoopAlignment;
	}		}
	/// getInsertFencesFor - return whether the DAG builder should automatica		/// Return whether the DAG builder should automatically insert fences and
	lly		/// reduce ordering for atomics.
	/// insert fences and reduce ordering for atomics.
	///
	bool getInsertFencesForAtomic() const {		bool getInsertFencesForAtomic() const {
	return InsertFencesForAtomic;		return InsertFencesForAtomic;
	}		}
	/// getStackCookieLocation - Return true if the target stores stack		/// Return true if the target stores stack protector cookies at a fixed o
	/// protector cookies at a fixed offset in some non-standard address		ffset
	/// space, and populates the address space and offset as		/// in some non-standard address space, and populates the address space a
	/// appropriate.		nd
			/// offset as appropriate.
	virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,		virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
	unsigned &/*Offset*/) const {		unsigned &/*Offset*/) const {
	return false;		return false;
	}		}
	/// getMaximalGlobalOffset - Returns the maximal possible offset which ca		/// Returns the maximal possible offset which can be used for loads / sto
	n be		res
	/// used for loads / stores from the global.		/// from the global.
	virtual unsigned getMaximalGlobalOffset() const {		virtual unsigned getMaximalGlobalOffset() const {
	return 0;		return 0;
	}		}
			/// Returns true if a cast between SrcAS and DestAS is a noop.
			virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
			return false;
			}
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	/// \name Helpers for TargetTransformInfo implementations		/// \name Helpers for TargetTransformInfo implementations
	/// @{		/// @{
	/// Get the ISD node that corresponds to the Instruction class opcode.		/// Get the ISD node that corresponds to the Instruction class opcode.
	int InstructionOpcodeToISD(unsigned Opcode) const;		int InstructionOpcodeToISD(unsigned Opcode) const;
	/// Estimate the cost of type-legalization and the legalized type.		/// Estimate the cost of type-legalization and the legalized type.
	std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const;		std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const;
	skipping to change at line 855		skipping to change at line 866
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	// TargetLowering Configuration Methods - These methods should be invoked by		// TargetLowering Configuration Methods - These methods should be invoked by
	// the derived class constructor to configure this object for the target.		// the derived class constructor to configure this object for the target.
	//		//
	/// \brief Reset the operation actions based on target options.		/// \brief Reset the operation actions based on target options.
	virtual void resetOperationActions() {}		virtual void resetOperationActions() {}
	protected:		protected:
	/// setBooleanContents - Specify how the target extends the result of a		/// Specify how the target extends the result of a boolean value from i1
	/// boolean value from i1 to a wider type. See getBooleanContents.		to a
			/// wider type. See getBooleanContents.
	void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }		void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
	/// setBooleanVectorContents - Specify how the target extends the result
	/// of a vector boolean value from a vector of i1 to a wider type. See		/// Specify how the target extends the result of a vector boolean value f
	/// getBooleanContents.		rom a
			/// vector of i1 to a wider type. See getBooleanContents.
	void setBooleanVectorContents(BooleanContent Ty) {		void setBooleanVectorContents(BooleanContent Ty) {
	BooleanVectorContents = Ty;		BooleanVectorContents = Ty;
	}		}
	/// setSchedulingPreference - Specify the target scheduling preference.		/// Specify the target scheduling preference.
	void setSchedulingPreference(Sched::Preference Pref) {		void setSchedulingPreference(Sched::Preference Pref) {
	SchedPreferenceInfo = Pref;		SchedPreferenceInfo = Pref;
	}		}
	/// setUseUnderscoreSetJmp - Indicate whether this target prefers to		/// Indicate whether this target prefers to use _setjmp to implement
	/// use _setjmp to implement llvm.setjmp or the non _ version.		/// llvm.setjmp or the non _ version. Defaults to false.
	/// Defaults to false.
	void setUseUnderscoreSetJmp(bool Val) {		void setUseUnderscoreSetJmp(bool Val) {
	UseUnderscoreSetJmp = Val;		UseUnderscoreSetJmp = Val;
	}		}
	/// setUseUnderscoreLongJmp - Indicate whether this target prefers to		/// Indicate whether this target prefers to use _longjmp to implement
	/// use _longjmp to implement llvm.longjmp or the non _ version.		/// llvm.longjmp or the non _ version. Defaults to false.
	/// Defaults to false.
	void setUseUnderscoreLongJmp(bool Val) {		void setUseUnderscoreLongJmp(bool Val) {
	UseUnderscoreLongJmp = Val;		UseUnderscoreLongJmp = Val;
	}		}
	/// setSupportJumpTables - Indicate whether the target can generate code		/// Indicate whether the target can generate code for jump tables.
	for
	/// jump tables.
	void setSupportJumpTables(bool Val) {		void setSupportJumpTables(bool Val) {
	SupportJumpTables = Val;		SupportJumpTables = Val;
	}		}
	/// setMinimumJumpTableEntries - Indicate the number of blocks to generat		/// Indicate the number of blocks to generate jump tables rather than if
	e		/// sequence.
	/// jump tables rather than if sequence.
	void setMinimumJumpTableEntries(int Val) {		void setMinimumJumpTableEntries(int Val) {
	MinimumJumpTableEntries = Val;		MinimumJumpTableEntries = Val;
	}		}
	/// setStackPointerRegisterToSaveRestore - If set to a physical register,		/// If set to a physical register, this specifies the register that
	this		/// llvm.savestack/llvm.restorestack should save and restore.
	/// specifies the register that llvm.savestack/llvm.restorestack should s
	ave
	/// and restore.
	void setStackPointerRegisterToSaveRestore(unsigned R) {		void setStackPointerRegisterToSaveRestore(unsigned R) {
	StackPointerRegisterToSaveRestore = R;		StackPointerRegisterToSaveRestore = R;
	}		}
	/// setExceptionPointerRegister - If set to a physical register, this set		/// If set to a physical register, this sets the register that receives t
	s		he
	/// the register that receives the exception address on entry to a landin		/// exception address on entry to a landing pad.
	g
	/// pad.
	void setExceptionPointerRegister(unsigned R) {		void setExceptionPointerRegister(unsigned R) {
	ExceptionPointerRegister = R;		ExceptionPointerRegister = R;
	}		}
	/// setExceptionSelectorRegister - If set to a physical register, this se		/// If set to a physical register, this sets the register that receives t
	ts		he
	/// the register that receives the exception typeid on entry to a landing		/// exception typeid on entry to a landing pad.
	/// pad.
	void setExceptionSelectorRegister(unsigned R) {		void setExceptionSelectorRegister(unsigned R) {
	ExceptionSelectorRegister = R;		ExceptionSelectorRegister = R;
	}		}
	/// SelectIsExpensive - Tells the code generator not to expand operations		/// Tells the code generator not to expand operations into sequences that
	/// into sequences that use the select operations if possible.		use
			/// the select operations if possible.
	void setSelectIsExpensive(bool isExpensive = true) {		void setSelectIsExpensive(bool isExpensive = true) {
	SelectIsExpensive = isExpensive;		SelectIsExpensive = isExpensive;
	}		}
	/// JumpIsExpensive - Tells the code generator not to expand sequence of		/// Tells the code generator not to expand sequence of operations into a
	/// operations into a separate sequences that increases the amount of		/// separate sequences that increases the amount of flow control.
	/// flow control.
	void setJumpIsExpensive(bool isExpensive = true) {		void setJumpIsExpensive(bool isExpensive = true) {
	JumpIsExpensive = isExpensive;		JumpIsExpensive = isExpensive;
	}		}
	/// setIntDivIsCheap - Tells the code generator that integer divide is		/// Tells the code generator that integer divide is expensive, and if
	/// expensive, and if possible, should be replaced by an alternate sequen		/// possible, should be replaced by an alternate sequence of instructions
	ce		not
	/// of instructions not containing an integer divide.		/// containing an integer divide.
	void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }		void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
	/// addBypassSlowDiv - Tells the code generator which bitwidths to bypass .		/// Tells the code generator which bitwidths to bypass.
	void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidt h) {		void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidt h) {
	BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;		BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
	}		}
	/// setPow2DivIsCheap - Tells the code generator that it shouldn't genera		/// Tells the code generator that it shouldn't generate srl/add/sra for a
	te		/// signed divide by power of two, and let the target handle it.
	/// srl/add/sra for a signed divide by power of two, and let the target h
	andle
	/// it.
	void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }		void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
	/// addRegisterClass - Add the specified register class as an available		/// Add the specified register class as an available regclass for the
	/// regclass for the specified value type. This indicates the selector c		/// specified value type. This indicates the selector can handle values o
	an		f
	/// handle values of that class natively.		/// that class natively.
	void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {		void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
	assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));		assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
	AvailableRegClasses.push_back(std::make_pair(VT, RC));		AvailableRegClasses.push_back(std::make_pair(VT, RC));
	RegClassForVT[VT.SimpleTy] = RC;		RegClassForVT[VT.SimpleTy] = RC;
	}		}
	/// clearRegisterClasses - Remove all register classes.		/// Remove all register classes.
	void clearRegisterClasses() {		void clearRegisterClasses() {
	memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClas s*));		memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClas s*));
	AvailableRegClasses.clear();		AvailableRegClasses.clear();
	}		}
	/// \brief Remove all operation actions.		/// \brief Remove all operation actions.
	void clearOperationActions() {		void clearOperationActions() {
	}		}
	/// findRepresentativeClass - Return the largest legal super-reg register		/// Return the largest legal super-reg register class of the register cla
	class		ss
	/// of the register class for the specified type and its associated "cost		/// for the specified type and its associated "cost".
	".
	virtual std::pair<const TargetRegisterClass*, uint8_t>		virtual std::pair<const TargetRegisterClass*, uint8_t>
	findRepresentativeClass(MVT VT) const;		findRepresentativeClass(MVT VT) const;
	/// computeRegisterProperties - Once all of the register classes are adde		/// Once all of the register classes are added, this allows us to compute
	d,		/// derived properties we expose.
	/// this allows us to compute derived properties we expose.
	void computeRegisterProperties();		void computeRegisterProperties();
	/// setOperationAction - Indicate that the specified operation does not w		/// Indicate that the specified operation does not work with the specifie
	ork		d
	/// with the specified type and indicate what to do about it.		/// type and indicate what to do about it.
	void setOperationAction(unsigned Op, MVT VT,		void setOperationAction(unsigned Op, MVT VT,
	LegalizeAction Action) {		LegalizeAction Action) {
	assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");		assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
	OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;		OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
	}		}
	/// setLoadExtAction - Indicate that the specified load with extension do		/// Indicate that the specified load with extension does not work with th
	es		e
	/// not work with the specified type and indicate what to do about it.		/// specified type and indicate what to do about it.
	void setLoadExtAction(unsigned ExtType, MVT VT,		void setLoadExtAction(unsigned ExtType, MVT VT,
	LegalizeAction Action) {		LegalizeAction Action) {
	assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&		assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
	"Table isn't big enough!");		"Table isn't big enough!");
	LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;		LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
	}		}
	/// setTruncStoreAction - Indicate that the specified truncating store do		/// Indicate that the specified truncating store does not work with the
	es		/// specified type and indicate what to do about it.
	/// not work with the specified type and indicate what to do about it.
	void setTruncStoreAction(MVT ValVT, MVT MemVT,		void setTruncStoreAction(MVT ValVT, MVT MemVT,
	LegalizeAction Action) {		LegalizeAction Action) {
	assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&		assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
	"Table isn't big enough!");		"Table isn't big enough!");
	TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;		TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
	}		}
	/// setIndexedLoadAction - Indicate that the specified indexed load does		/// Indicate that the specified indexed load does or does not work with t
	or		he
	/// does not work with the specified type and indicate what to do abort		/// specified type and indicate what to do abort it.
	/// it. NOTE: All indexed mode loads are initialized to Expand in		///
			/// NOTE: All indexed mode loads are initialized to Expand in
	/// TargetLowering.cpp		/// TargetLowering.cpp
	void setIndexedLoadAction(unsigned IdxMode, MVT VT,		void setIndexedLoadAction(unsigned IdxMode, MVT VT,
	LegalizeAction Action) {		LegalizeAction Action) {
	assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&		assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
	(unsigned)Action < 0xf && "Table isn't big enough!");		(unsigned)Action < 0xf && "Table isn't big enough!");
	// Load action are kept in the upper half.		// Load action are kept in the upper half.
	IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;		IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
	IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;		IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
	}		}
	/// setIndexedStoreAction - Indicate that the specified indexed store doe		/// Indicate that the specified indexed store does or does not work with
	s or		the
	/// does not work with the specified type and indicate what to do about		/// specified type and indicate what to do about it.
	/// it. NOTE: All indexed mode stores are initialized to Expand in		///
			/// NOTE: All indexed mode stores are initialized to Expand in
	/// TargetLowering.cpp		/// TargetLowering.cpp
	void setIndexedStoreAction(unsigned IdxMode, MVT VT,		void setIndexedStoreAction(unsigned IdxMode, MVT VT,
	LegalizeAction Action) {		LegalizeAction Action) {
	assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&		assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
	(unsigned)Action < 0xf && "Table isn't big enough!");		(unsigned)Action < 0xf && "Table isn't big enough!");
	// Store action are kept in the lower half.		// Store action are kept in the lower half.
	IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;		IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
	IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) ;		IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) ;
	}		}
	/// setCondCodeAction - Indicate that the specified condition code is or		/// Indicate that the specified condition code is or isn't supported on t
	isn't		he
	/// supported on the target and indicate what to do about it.		/// target and indicate what to do about it.
	void setCondCodeAction(ISD::CondCode CC, MVT VT,		void setCondCodeAction(ISD::CondCode CC, MVT VT,
	LegalizeAction Action) {		LegalizeAction Action) {
	assert(VT < MVT::LAST_VALUETYPE &&		assert(VT < MVT::LAST_VALUETYPE &&
	(unsigned)CC < array_lengthof(CondCodeActions) &&		(unsigned)CC < array_lengthof(CondCodeActions) &&
	"Table isn't big enough!");		"Table isn't big enough!");
	/// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 6		/// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 3
	4bit		2-bit
	/// value and the upper 27 bits index into the second dimension of the		/// value and the upper 27 bits index into the second dimension of the
	/// array to select what 64bit value to use.		array
	CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5]		/// to select what 32-bit value to use.
	&= ~(uint64_t(3UL) << (VT.SimpleTy & 0x1F)*2);		uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
	CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5]		CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
	|= (uint64_t)Action << (VT.SimpleTy & 0x1F)*2;		CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
	}		}
	/// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the		/// If Opc/OrigVT is specified as being promoted, the promotion code defa
	/// promotion code defaults to trying a larger integer/fp until it can fi		ults
	nd		/// to trying a larger integer/fp until it can find one that works. If th
	/// one that works. If that default is insufficient, this method can be		at
	used		/// default is insufficient, this method can be used by the target to ove
	/// by the target to override the default.		rride
			/// the default.
	void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {		void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
	PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;		PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
	}		}
	/// setTargetDAGCombine - Targets should invoke this method for each targ		/// Targets should invoke this method for each target independent node th
	et		at
	/// independent node that they want to provide a custom DAG combiner for		/// they want to provide a custom DAG combiner for by implementing the
	by		/// PerformDAGCombine virtual method.
	/// implementing the PerformDAGCombine virtual method.
	void setTargetDAGCombine(ISD::NodeType NT) {		void setTargetDAGCombine(ISD::NodeType NT) {
	assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));		assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
	TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);		TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
	}		}
	/// setJumpBufSize - Set the target's required jmp_buf buffer size (in		/// Set the target's required jmp_buf buffer size (in bytes); default is
	/// bytes); default is 200		200
	void setJumpBufSize(unsigned Size) {		void setJumpBufSize(unsigned Size) {
	JumpBufSize = Size;		JumpBufSize = Size;
	}		}
	/// setJumpBufAlignment - Set the target's required jmp_buf buffer		/// Set the target's required jmp_buf buffer alignment (in bytes); defaul
	/// alignment (in bytes); default is 0		t is
			/// 0
	void setJumpBufAlignment(unsigned Align) {		void setJumpBufAlignment(unsigned Align) {
	JumpBufAlignment = Align;		JumpBufAlignment = Align;
	}		}
	/// setMinFunctionAlignment - Set the target's minimum function alignment		/// Set the target's minimum function alignment (in log2(bytes))
	(in
	/// log2(bytes))
	void setMinFunctionAlignment(unsigned Align) {		void setMinFunctionAlignment(unsigned Align) {
	MinFunctionAlignment = Align;		MinFunctionAlignment = Align;
	}		}
	/// setPrefFunctionAlignment - Set the target's preferred function alignm		/// Set the target's preferred function alignment. This should be set if
	ent.		/// there is a performance benefit to higher-than-minimum alignment (in
	/// This should be set if there is a performance benefit to		/// log2(bytes))
	/// higher-than-minimum alignment (in log2(bytes))
	void setPrefFunctionAlignment(unsigned Align) {		void setPrefFunctionAlignment(unsigned Align) {
	PrefFunctionAlignment = Align;		PrefFunctionAlignment = Align;
	}		}
	/// setPrefLoopAlignment - Set the target's preferred loop alignment. Def		/// Set the target's preferred loop alignment. Default alignment is zero,
	ault		it
	/// alignment is zero, it means the target does not care about loop align		/// means the target does not care about loop alignment. The alignment i
	ment.		s
	/// The alignment is specified in log2(bytes).		/// specified in log2(bytes).
	void setPrefLoopAlignment(unsigned Align) {		void setPrefLoopAlignment(unsigned Align) {
	PrefLoopAlignment = Align;		PrefLoopAlignment = Align;
	}		}
	/// setMinStackArgumentAlignment - Set the minimum stack alignment of an		/// Set the minimum stack alignment of an argument (in log2(bytes)).
	/// argument (in log2(bytes)).
	void setMinStackArgumentAlignment(unsigned Align) {		void setMinStackArgumentAlignment(unsigned Align) {
	MinStackArgumentAlignment = Align;		MinStackArgumentAlignment = Align;
	}		}
	/// setInsertFencesForAtomic - Set if the DAG builder should		/// Set if the DAG builder should automatically insert fences and reduce
	/// automatically insert fences and reduce the order of atomic memory		the
	/// operations to Monotonic.		/// order of atomic memory operations to Monotonic.
	void setInsertFencesForAtomic(bool fence) {		void setInsertFencesForAtomic(bool fence) {
	InsertFencesForAtomic = fence;		InsertFencesForAtomic = fence;
	}		}
	public:		public:
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	// Addressing mode description hooks (used by LSR etc).		// Addressing mode description hooks (used by LSR etc).
	//		//
	/// GetAddrModeArguments - CodeGenPrepare sinks address calculations into		/// CodeGenPrepare sinks address calculations into the same BB as Load/St
	the		ore
	/// same BB as Load/Store instructions reading the address. This allows		/// instructions reading the address. This allows as much computation as
	as		/// possible to be done in the address mode for that operand. This hook l
	/// much computation as possible to be done in the address mode for that		ets
	/// operand. This hook lets targets also pass back when this should be d		/// targets also pass back when this should be done on intrinsics which
	one		/// load/store.
	/// on intrinsics which load/store.		virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
	virtual bool GetAddrModeArguments(IntrinsicInst *I,		SmallVectorImpl<Value*> &/*Ops*/,
	SmallVectorImpl<Value*> &Ops,		Type *&/*AccessTy*/) const {
	Type *&AccessTy) const {
	return false;		return false;
	}		}
	/// AddrMode - This represents an addressing mode of:		/// This represents an addressing mode of:
	/// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg		/// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
	/// If BaseGV is null, there is no BaseGV.		/// If BaseGV is null, there is no BaseGV.
	/// If BaseOffs is zero, there is no base offset.		/// If BaseOffs is zero, there is no base offset.
	/// If HasBaseReg is false, there is no base register.		/// If HasBaseReg is false, there is no base register.
	/// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg w ith		/// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg w ith
	/// no scale.		/// no scale.
	///
	struct AddrMode {		struct AddrMode {
	GlobalValue *BaseGV;		GlobalValue *BaseGV;
	int64_t BaseOffs;		int64_t BaseOffs;
	bool HasBaseReg;		bool HasBaseReg;
	int64_t Scale;		int64_t Scale;
	AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}		AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
	};		};
	/// isLegalAddressingMode - Return true if the addressing mode represente		/// Return true if the addressing mode represented by AM is legal for thi
	d by		s
	/// AM is legal for this target, for a load/store of the specified type.		/// target, for a load/store of the specified type.
			///
	/// The type may be VoidTy, in which case only return true if the address ing		/// The type may be VoidTy, in which case only return true if the address ing
	/// mode is legal for a load/store of any legal type.		/// mode is legal for a load/store of any legal type. TODO: Handle
	/// TODO: Handle pre/postinc as well.		/// pre/postinc as well.
	virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;		virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
	/// isLegalICmpImmediate - Return true if the specified immediate is lega		/// \brief Return the cost of the scaling factor used in the addressing m
	l		ode
	/// icmp immediate, that is the target has icmp instructions which can co		/// represented by AM for this target, for a load/store of the specified
	mpare		type.
	/// a register against the immediate without having to materialize the		///
	/// immediate into a register.		/// If the AM is supported, the return value must be >= 0.
			/// If the AM is not supported, it returns a negative value.
			/// TODO: Handle pre/postinc as well.
			virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty) const {
			// Default: assume that any scaling factor used in a legal AM is free.
			if (isLegalAddressingMode(AM, Ty)) return 0;
			return -1;
			}
			/// Return true if the specified immediate is legal icmp immediate, that
			is
			/// the target has icmp instructions which can compare a register against
			the
			/// immediate without having to materialize the immediate into a register
			.
	virtual bool isLegalICmpImmediate(int64_t) const {		virtual bool isLegalICmpImmediate(int64_t) const {
	return true;		return true;
	}		}
	/// isLegalAddImmediate - Return true if the specified immediate is legal		/// Return true if the specified immediate is legal add immediate, that i
	/// add immediate, that is the target has add instructions which can add		s the
	/// a register with the immediate without having to materialize the		/// target has add instructions which can add a register with the immedia
	/// immediate into a register.		te
			/// without having to materialize the immediate into a register.
	virtual bool isLegalAddImmediate(int64_t) const {		virtual bool isLegalAddImmediate(int64_t) const {
	return true;		return true;
	}		}
	/// isTruncateFree - Return true if it's free to truncate a value of		/// Return true if it's free to truncate a value of type Ty1 to type
	/// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value i		/// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to
	n		i16
	/// register EAX to i16 by referencing its sub-register AX.		/// by referencing its sub-register AX.
	virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {		virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
	return false;		return false;
	}		}
			/// Return true if a truncation from Ty1 to Ty2 is permitted when decidin
			g
			/// whether a call is in tail position. Typically this means that both re
			sults
			/// would be assigned to the same register or stack slot, but it could me
			an
			/// the target performs adequate checks of its own before proceeding with
			the
			/// tail call.
			virtual bool allowTruncateForTailCall(Type * /*Ty1*/, Type * /*Ty2*/) con
			st {
			return false;
			}
	virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {		virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
	return false;		return false;
	}		}
	/// isZExtFree - Return true if any actual instruction that defines a		/// Return true if any actual instruction that defines a value of type Ty
	/// value of type Ty1 implicitly zero-extends the value to Ty2 in the res		1
	ult		/// implicitly zero-extends the value to Ty2 in the result register.
	/// register. This does not necessarily include registers defined in		///
	/// unknown ways, such as incoming arguments, or copies from unknown		/// This does not necessarily include registers defined in unknown ways,
	/// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this		such
	/// does not necessarily apply to truncate instructions. e.g. on x86-64,		/// as incoming arguments, or copies from unknown virtual registers. Also
	/// all instructions that define 32-bit values implicit zero-extend the		, if
	/// result out to 64 bits.		/// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to
			/// truncate instructions. e.g. on x86-64, all instructions that define 3
			2-bit
			/// values implicit zero-extend the result out to 64 bits.
	virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {		virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
	return false;		return false;
	}		}
	virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {		virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
	return false;		return false;
	}		}
	/// isZExtFree - Return true if zero-extending the specific node Val to t		/// Return true if the target supplies and combines to a paired load
	ype		/// two loaded values of type LoadedType next to each other in memory.
	/// VT2 is free (either because it's implicitly zero-extended such as ARM		/// RequiredAlignment gives the minimal alignment constraints that must b
	/// ldrb / ldrh or because it's folded such as X86 zero-extending loads).		e met
			/// to be able to select this paired load.
			///
			/// This information is *not* used to generate actual paired loads, but i
			t is
			/// used to generate a sequence of loads that is easier to combine into a
			/// paired load.
			/// For instance, something like this:
			/// a = load i64* addr
			/// b = trunc i64 a to i32
			/// c = lshr i64 a, 32
			/// d = trunc i64 c to i32
			/// will be optimized into:
			/// b = load i32* addr1
			/// d = load i32* addr2
			/// Where addr1 = addr2 +/- sizeof(i32).
			///
			/// In other words, unless the target performs a post-isel load combining
			,
			/// this information should not be provided because it will generate more
			/// loads.
			virtual bool hasPairedLoad(Type * /*LoadedType*/,
			unsigned & /*RequiredAligment*/) const {
			return false;
			}
			virtual bool hasPairedLoad(EVT /*LoadedType*/,
			unsigned & /*RequiredAligment*/) const {
			return false;
			}
			/// Return true if zero-extending the specific node Val to type VT2 is fr
			ee
			/// (either because it's implicitly zero-extended such as ARM ldrb / ldrh
			or
			/// because it's folded such as X86 zero-extending loads).
	virtual bool isZExtFree(SDValue Val, EVT VT2) const {		virtual bool isZExtFree(SDValue Val, EVT VT2) const {
	return isZExtFree(Val.getValueType(), VT2);		return isZExtFree(Val.getValueType(), VT2);
	}		}
	/// isFNegFree - Return true if an fneg operation is free to the point wh		/// Return true if an fneg operation is free to the point where it is nev
	ere		er
	/// it is never worthwhile to replace it with a bitwise operation.		/// worthwhile to replace it with a bitwise operation.
	virtual bool isFNegFree(EVT) const {		virtual bool isFNegFree(EVT VT) const {
			assert(VT.isFloatingPoint());
	return false;		return false;
	}		}
	/// isFAbsFree - Return true if an fneg operation is free to the point wh		/// Return true if an fabs operation is free to the point where it is nev
	ere		er
	/// it is never worthwhile to replace it with a bitwise operation.		/// worthwhile to replace it with a bitwise operation.
	virtual bool isFAbsFree(EVT) const {		virtual bool isFAbsFree(EVT VT) const {
			assert(VT.isFloatingPoint());
	return false;		return false;
	}		}
	/// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster		/// Return true if an FMA operation is faster than a pair of fmul and fad
	than		d
	/// a pair of mul and add instructions. fmuladd intrinsics will be expand		/// instructions. fmuladd intrinsics will be expanded to FMAs when this m
	ed to		ethod
	/// FMAs when this method returns true (and FMAs are legal), otherwise fm		/// returns true, otherwise fmuladd is expanded to fmul + fadd.
	uladd		///
	/// is expanded to mul + add.		/// NOTE: This may be called before legalization on types for which FMAs
	virtual bool isFMAFasterThanMulAndAdd(EVT) const {		are
			/// not legal, but should return true if those types will eventually lega
			lize
			/// to types that support FMAs. After legalization, it will only be calle
			d on
			/// types that support FMAs (via Legal or Custom actions)
			virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
	return false;		return false;
	}		}
	/// isNarrowingProfitable - Return true if it's profitable to narrow		/// Return true if it's profitable to narrow operations of type VT1 to
	/// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow		/// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not fr
	/// from i32 to i8 but not from i32 to i16.		om
			/// i32 to i16.
	virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {		virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
	return false;		return false;
	}		}
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	// Runtime Library hooks		// Runtime Library hooks
	//		//
	/// setLibcallName - Rename the default libcall routine name for the spec		/// Rename the default libcall routine name for the specified libcall.
	ified
	/// libcall.
	void setLibcallName(RTLIB::Libcall Call, const char *Name) {		void setLibcallName(RTLIB::Libcall Call, const char *Name) {
	LibcallRoutineNames[Call] = Name;		LibcallRoutineNames[Call] = Name;
	}		}
	/// getLibcallName - Get the libcall routine name for the specified libca		/// Get the libcall routine name for the specified libcall.
	ll.
	///
	const char *getLibcallName(RTLIB::Libcall Call) const {		const char *getLibcallName(RTLIB::Libcall Call) const {
	return LibcallRoutineNames[Call];		return LibcallRoutineNames[Call];
	}		}
	/// setCmpLibcallCC - Override the default CondCode to be used to test th		/// Override the default CondCode to be used to test the result of the
	e		/// comparison libcall against zero.
	/// result of the comparison libcall against zero.
	void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {		void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
	CmpLibcallCCs[Call] = CC;		CmpLibcallCCs[Call] = CC;
	}		}
	/// getCmpLibcallCC - Get the CondCode that's to be used to test the resu		/// Get the CondCode that's to be used to test the result of the comparis
	lt of		on
	/// the comparison libcall against zero.		/// libcall against zero.
	ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {		ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
	return CmpLibcallCCs[Call];		return CmpLibcallCCs[Call];
	}		}
	/// setLibcallCallingConv - Set the CallingConv that should be used for t		/// Set the CallingConv that should be used for the specified libcall.
	he
	/// specified libcall.
	void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {		void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
	LibcallCallingConvs[Call] = CC;		LibcallCallingConvs[Call] = CC;
	}		}
	/// getLibcallCallingConv - Get the CallingConv that should be used for t		/// Get the CallingConv that should be used for the specified libcall.
	he
	/// specified libcall.
	CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {		CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
	return LibcallCallingConvs[Call];		return LibcallCallingConvs[Call];
	}		}
	private:		private:
	const TargetMachine &TM;		const TargetMachine &TM;
	const DataLayout *TD;		const DataLayout *TD;
	const TargetLoweringObjectFile &TLOF;		const TargetLoweringObjectFile &TLOF;
	/// PointerTy - The type to use for pointers for the default address spac		/// True if this is a little endian target.
	e,
	/// usually i32 or i64.
	///
	MVT PointerTy;
	/// IsLittleEndian - True if this is a little endian target.
	///
	bool IsLittleEndian;		bool IsLittleEndian;
	/// SelectIsExpensive - Tells the code generator not to expand operations		/// Tells the code generator not to expand operations into sequences that
	/// into sequences that use the select operations if possible.		use
			/// the select operations if possible.
	bool SelectIsExpensive;		bool SelectIsExpensive;
	/// IntDivIsCheap - Tells the code generator not to expand integer divide		/// Tells the code generator not to expand integer divides by constants i
	s by		nto a
	/// constants into a sequence of muls, adds, and shifts. This is a hack		/// sequence of muls, adds, and shifts. This is a hack until a real cost
	until		/// model is in place. If we ever optimize for size, this will be set to
	/// a real cost model is in place. If we ever optimize for size, this wi		true
	ll be		/// unconditionally.
	/// set to true unconditionally.
	bool IntDivIsCheap;		bool IntDivIsCheap;
	/// BypassSlowDivMap - Tells the code generator to bypass slow divide or		/// Tells the code generator to bypass slow divide or remainder
	/// remainder instructions. For example, BypassSlowDivWidths[32,8] tells		/// instructions. For example, BypassSlowDivWidths[32,8] tells the code
	the		/// generator to bypass 32-bit integer div/rem with an 8-bit unsigned int
	/// code generator to bypass 32-bit integer div/rem with an 8-bit unsigne		eger
	d		/// div/rem when the operands are positive and less than 256.
	/// integer div/rem when the operands are positive and less than 256.
	DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;		DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
	/// Pow2DivIsCheap - Tells the code generator that it shouldn't generate		/// Tells the code generator that it shouldn't generate srl/add/sra for a
	/// srl/add/sra for a signed divide by power of two, and let the target h		/// signed divide by power of two, and let the target handle it.
	andle
	/// it.
	bool Pow2DivIsCheap;		bool Pow2DivIsCheap;
	/// JumpIsExpensive - Tells the code generator that it shouldn't generate		/// Tells the code generator that it shouldn't generate extra flow contro
	/// extra flow control instructions and should attempt to combine flow		l
	/// control instructions via predication.		/// instructions and should attempt to combine flow control instructions
			via
			/// predication.
	bool JumpIsExpensive;		bool JumpIsExpensive;
	/// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement		/// This target prefers to use _setjmp to implement llvm.setjmp.
	/// llvm.setjmp. Defaults to false.		///
			/// Defaults to false.
	bool UseUnderscoreSetJmp;		bool UseUnderscoreSetJmp;
	/// UseUnderscoreLongJmp - This target prefers to use _longjmp to impleme		/// This target prefers to use _longjmp to implement llvm.longjmp.
	nt		///
	/// llvm.longjmp. Defaults to false.		/// Defaults to false.
	bool UseUnderscoreLongJmp;		bool UseUnderscoreLongJmp;
	/// SupportJumpTables - Whether the target can generate code for jumptabl		/// Whether the target can generate code for jumptables. If it's not tru
	es.		e,
	/// If it's not true, then each jumptable must be lowered into if-then-el		/// then each jumptable must be lowered into if-then-else's.
	se's.
	bool SupportJumpTables;		bool SupportJumpTables;
	/// MinimumJumpTableEntries - Number of blocks threshold to use jump tabl es.		/// Number of blocks threshold to use jump tables.
	int MinimumJumpTableEntries;		int MinimumJumpTableEntries;
	/// BooleanContents - Information about the contents of the high-bits in		/// Information about the contents of the high-bits in boolean values hel
	/// boolean values held in a type wider than i1. See getBooleanContents.		d in
			/// a type wider than i1. See getBooleanContents.
	BooleanContent BooleanContents;		BooleanContent BooleanContents;
	/// BooleanVectorContents - Information about the contents of the high-bi
	ts		/// Information about the contents of the high-bits in boolean vector val
	/// in boolean vector values when the element type is wider than i1. See		ues
	/// getBooleanContents.		/// when the element type is wider than i1. See getBooleanContents.
	BooleanContent BooleanVectorContents;		BooleanContent BooleanVectorContents;
	/// SchedPreferenceInfo - The target scheduling preference: shortest poss		/// The target scheduling preference: shortest possible total cycles or l
	ible		owest
	/// total cycles or lowest register usage.		/// register usage.
	Sched::Preference SchedPreferenceInfo;		Sched::Preference SchedPreferenceInfo;
	/// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers		/// The size, in bytes, of the target's jmp_buf buffers
	unsigned JumpBufSize;		unsigned JumpBufSize;
	/// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf		/// The alignment, in bytes, of the target's jmp_buf buffers
	/// buffers
	unsigned JumpBufAlignment;		unsigned JumpBufAlignment;
	/// MinStackArgumentAlignment - The minimum alignment that any argument		/// The minimum alignment that any argument on the stack needs to have.
	/// on the stack needs to have.
	///
	unsigned MinStackArgumentAlignment;		unsigned MinStackArgumentAlignment;
	/// MinFunctionAlignment - The minimum function alignment (used when		/// The minimum function alignment (used when optimizing for size, and to
	/// optimizing for size, and to prevent explicitly provided alignment		/// prevent explicitly provided alignment from leading to incorrect code)
	/// from leading to incorrect code).		.
	///
	unsigned MinFunctionAlignment;		unsigned MinFunctionAlignment;
	/// PrefFunctionAlignment - The preferred function alignment (used when		/// The preferred function alignment (used when alignment unspecified and
	/// alignment unspecified and optimizing for speed).		/// optimizing for speed).
	///
	unsigned PrefFunctionAlignment;		unsigned PrefFunctionAlignment;
	/// PrefLoopAlignment - The preferred loop alignment.		/// The preferred loop alignment.
	///
	unsigned PrefLoopAlignment;		unsigned PrefLoopAlignment;
	/// InsertFencesForAtomic - Whether the DAG builder should automatically		/// Whether the DAG builder should automatically insert fences and reduce
	/// insert fences and reduce ordering for atomics. (This will be set for		/// ordering for atomics. (This will be set for for most architectures w
	/// for most architectures with weak memory ordering.)		ith
			/// weak memory ordering.)
	bool InsertFencesForAtomic;		bool InsertFencesForAtomic;
	/// StackPointerRegisterToSaveRestore - If set to a physical register, th		/// If set to a physical register, this specifies the register that
	is		/// llvm.savestack/llvm.restorestack should save and restore.
	/// specifies the register that llvm.savestack/llvm.restorestack should s
	ave
	/// and restore.
	unsigned StackPointerRegisterToSaveRestore;		unsigned StackPointerRegisterToSaveRestore;
	/// ExceptionPointerRegister - If set to a physical register, this specif		/// If set to a physical register, this specifies the register that recei
	ies		ves
	/// the register that receives the exception address on entry to a landin		/// the exception address on entry to a landing pad.
	g
	/// pad.
	unsigned ExceptionPointerRegister;		unsigned ExceptionPointerRegister;
	/// ExceptionSelectorRegister - If set to a physical register, this speci		/// If set to a physical register, this specifies the register that recei
	fies		ves
	/// the register that receives the exception typeid on entry to a landing		/// the exception typeid on entry to a landing pad.
	/// pad.
	unsigned ExceptionSelectorRegister;		unsigned ExceptionSelectorRegister;
	/// RegClassForVT - This indicates the default register class to use for		/// This indicates the default register class to use for each ValueType t
	/// each ValueType the target supports natively.		he
			/// target supports natively.
	const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];		const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
	unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];		unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
	MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];		MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
	/// RepRegClassForVT - This indicates the "representative" register class		/// This indicates the "representative" register class to use for each
	to		/// ValueType the target supports natively. This information is used by t
	/// use for each ValueType the target supports natively. This information		he
	is		/// scheduler to track register pressure. By default, the representative
	/// used by the scheduler to track register pressure. By default, the		/// register class is the largest legal super-reg register class of the
	/// representative register class is the largest legal super-reg register		/// register class of the specified type. e.g. On x86, i8, i16, and i32's
	/// class of the register class of the specified type. e.g. On x86, i8, i		/// representative class would be GR32.
	16,
	/// and i32's representative class would be GR32.
	const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];		const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
	/// RepRegClassCostForVT - This indicates the "cost" of the "representati		/// This indicates the "cost" of the "representative" register class for
	ve"		each
	/// register class for each ValueType. The cost is used by the scheduler		/// ValueType. The cost is used by the scheduler to approximate register
	to		/// pressure.
	/// approximate register pressure.
	uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];		uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
	/// TransformToType - For any value types we are promoting or expanding,		/// For any value types we are promoting or expanding, this contains the
	this		value
	/// contains the value type that we are changing to. For Expanded types,		/// type that we are changing to. For Expanded types, this contains one
	this		step
	/// contains one step of the expand (e.g. i64 -> i32), even if there are		/// of the expand (e.g. i64 -> i32), even if there are multiple steps req
	/// multiple steps required (e.g. i64 -> i16). For types natively suppor		uired
	ted		/// (e.g. i64 -> i16). For types natively supported by the system, this
	/// by the system, this holds the same type (e.g. i32 -> i32).		holds
			/// the same type (e.g. i32 -> i32).
	MVT TransformToType[MVT::LAST_VALUETYPE];		MVT TransformToType[MVT::LAST_VALUETYPE];
	/// OpActions - For each operation and each value type, keep a LegalizeAc		/// For each operation and each value type, keep a LegalizeAction that
	tion		/// indicates how instruction selection should deal with the operation.
	/// that indicates how instruction selection should deal with the operati		Most
	on.		/// operations are Legal (aka, supported natively by the target), but
	/// Most operations are Legal (aka, supported natively by the target), bu
	t
	/// operations that are not should be described. Note that operations on		/// operations that are not should be described. Note that operations on
	/// non-legal value types are not described here.		/// non-legal value types are not described here.
	uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];		uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
	/// LoadExtActions - For each load extension type and each value type,		/// For each load extension type and each value type, keep a LegalizeActi
	/// keep a LegalizeAction that indicates how instruction selection should		on
	deal		/// that indicates how instruction selection should deal with a load of a
	/// with a load of a specific value type and extension type.		/// specific value type and extension type.
	uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];		uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
	/// TruncStoreActions - For each value type pair keep a LegalizeAction th		/// For each value type pair keep a LegalizeAction that indicates whether
	at		a
	/// indicates whether a truncating store of a specific value type and		/// truncating store of a specific value type and truncating type is lega
	/// truncating type is legal.		l.
	uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];		uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
	/// IndexedModeActions - For each indexed mode and each value type,		/// For each indexed mode and each value type, keep a pair of LegalizeAct
	/// keep a pair of LegalizeAction that indicates how instruction		ion
	/// selection should deal with the load / store. The first dimension is		/// that indicates how instruction selection should deal with the load /
	the		/// store.
	/// value_type for the reference. The second dimension represents the var		///
	ious		/// The first dimension is the value_type for the reference. The second
	/// modes for load store.		/// dimension represents the various modes for load store.
	uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];		uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
	/// CondCodeActions - For each condition code (ISD::CondCode) keep a		/// For each condition code (ISD::CondCode) keep a LegalizeAction that
	/// LegalizeAction that indicates how instruction selection should		/// indicates how instruction selection should deal with the condition co
	/// deal with the condition code.		de.
	/// Because each CC action takes up 2 bits, we need to have the array siz		///
	e		/// Because each CC action takes up 2 bits, we need to have the array siz
	/// be large enough to fit all of the value types. This can be done by		e be
	/// dividing the MVT::LAST_VALUETYPE by 32 and adding one.		/// large enough to fit all of the value types. This can be done by round
	uint64_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE / 32) +		ing
	1];		/// up the MVT::LAST_VALUETYPE value to the next multiple of 16.
			uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) /
			16];
	ValueTypeActionImpl ValueTypeActions;		ValueTypeActionImpl ValueTypeActions;
	public:		public:
	LegalizeKind		LegalizeKind
	getTypeConversion(LLVMContext &Context, EVT VT) const {		getTypeConversion(LLVMContext &Context, EVT VT) const {
	// If this is a simple type, use the ComputeRegisterProp mechanism.		// If this is a simple type, use the ComputeRegisterProp mechanism.
	if (VT.isSimple()) {		if (VT.isSimple()) {
	MVT SVT = VT.getSimpleVT();		MVT SVT = VT.getSimpleVT();
	assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));		assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
	skipping to change at line 1484		skipping to change at line 1521
	}		}
	// Handle vector types.		// Handle vector types.
	unsigned NumElts = VT.getVectorNumElements();		unsigned NumElts = VT.getVectorNumElements();
	EVT EltVT = VT.getVectorElementType();		EVT EltVT = VT.getVectorElementType();
	// Vectors with only one element are always scalarized.		// Vectors with only one element are always scalarized.
	if (NumElts == 1)		if (NumElts == 1)
	return LegalizeKind(TypeScalarizeVector, EltVT);		return LegalizeKind(TypeScalarizeVector, EltVT);
	// Try to widen vector elements until a legal type is found.		// Try to widen vector elements until the element type is a power of tw
			o and
			// promote it to a legal type later on, for example:
			// <3 x i8> -> <4 x i8> -> <4 x i32>
	if (EltVT.isInteger()) {		if (EltVT.isInteger()) {
	// Vectors with a number of elements that is not a power of two are a lways		// Vectors with a number of elements that is not a power of two are a lways
	// widened, for example <3 x float> -> <4 x float>.		// widened, for example <3 x i8> -> <4 x i8>.
	if (!VT.isPow2VectorType()) {		if (!VT.isPow2VectorType()) {
	NumElts = (unsigned)NextPowerOf2(NumElts);		NumElts = (unsigned)NextPowerOf2(NumElts);
	EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);		EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
	return LegalizeKind(TypeWidenVector, NVT);		return LegalizeKind(TypeWidenVector, NVT);
	}		}
	// Examine the element type.		// Examine the element type.
	LegalizeKind LK = getTypeConversion(Context, EltVT);		LegalizeKind LK = getTypeConversion(Context, EltVT);
	// If type is to be expanded, split the vector.		// If type is to be expanded, split the vector.
	skipping to change at line 1516		skipping to change at line 1555
	// vector.		// vector.
	EVT OldEltVT = EltVT;		EVT OldEltVT = EltVT;
	while (1) {		while (1) {
	// Increase the bitwidth of the element to the next pow-of-two		// Increase the bitwidth of the element to the next pow-of-two
	// (which is greater than 8 bits).		// (which is greater than 8 bits).
	EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()		EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
	).getRoundIntegerType(Context);		).getRoundIntegerType(Context);
	// Stop trying when getting a non-simple element type.		// Stop trying when getting a non-simple element type.
	// Note that vector elements may be greater than legal vector eleme nt		// Note that vector elements may be greater than legal vector eleme nt
	// types. Example: X86 XMM registers hold 64bit element on 32bit sy		// types. Example: X86 XMM registers hold 64bit element on 32bit
	stems.		// systems.
	if (!EltVT.isSimple()) break;		if (!EltVT.isSimple()) break;
	// Build a new vector type and check if it is legal.		// Build a new vector type and check if it is legal.
	MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);		MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
	// Found a legal promoted vector type.		// Found a legal promoted vector type.
	if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLega l)		if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLega l)
	return LegalizeKind(TypePromoteInteger,		return LegalizeKind(TypePromoteInteger,
	EVT::getVectorVT(Context, EltVT, NumElts));		EVT::getVectorVT(Context, EltVT, NumElts));
	}		}
	skipping to change at line 1564		skipping to change at line 1604
	}		}
	// Vectors with illegal element types are expanded.		// Vectors with illegal element types are expanded.
	EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);		EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
	return LegalizeKind(TypeSplitVector, NVT);		return LegalizeKind(TypeSplitVector, NVT);
	}		}
	private:		private:
	std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClas ses;		std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClas ses;
	/// TargetDAGCombineArray - Targets can specify ISD nodes that they would		/// Targets can specify ISD nodes that they would like PerformDAGCombine
	/// like PerformDAGCombine callbacks for by calling setTargetDAGCombine()		/// callbacks for by calling setTargetDAGCombine(), which sets a bit in t
	,		his
	/// which sets a bit in this array.		/// array.
	unsigned char		unsigned char
	TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];		TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
	/// PromoteToType - For operations that must be promoted to a specific ty		/// For operations that must be promoted to a specific type, this holds t
	pe,		he
	/// this holds the destination type. This map should be sparse, so don't		/// destination type. This map should be sparse, so don't hold it as an
	hold		/// array.
	/// it as an array.
	///		///
	/// Targets add entries to this map with AddPromotedToType(..), clients a ccess		/// Targets add entries to this map with AddPromotedToType(..), clients a ccess
	/// this with getTypeToPromoteTo(..).		/// this with getTypeToPromoteTo(..).
	std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>		std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
	PromoteToType;		PromoteToType;
	/// LibcallRoutineNames - Stores the name each libcall.		/// Stores the name each libcall.
	///
	const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];		const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
	/// CmpLibcallCCs - The ISD::CondCode that should be used to test the res		/// The ISD::CondCode that should be used to test the result of each of t
	ult		he
	/// of each of the comparison libcall against zero.		/// comparison libcall against zero.
	ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];		ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
	/// LibcallCallingConvs - Stores the CallingConv that should be used for		/// Stores the CallingConv that should be used for each libcall.
	each
	/// libcall.
	CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];		CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
	protected:		protected:
			/// \brief Specify maximum number of store instructions per memset call.
			///
	/// When lowering \@llvm.memset this field specifies the maximum number o f		/// When lowering \@llvm.memset this field specifies the maximum number o f
	/// store operations that may be substituted for the call to memset. Targ ets		/// store operations that may be substituted for the call to memset. Targ ets
	/// must set this value based on the cost threshold for that target. Targ ets		/// must set this value based on the cost threshold for that target. Targ ets
	/// should assume that the memset will be done using as many of the large st		/// should assume that the memset will be done using as many of the large st
	/// store operations first, followed by smaller ones, if necessary, per		/// store operations first, followed by smaller ones, if necessary, per
	/// alignment restrictions. For example, storing 9 bytes on a 32-bit mach ine		/// alignment restrictions. For example, storing 9 bytes on a 32-bit mach ine
	/// with 16-bit alignment would result in four 2-byte stores and one 1-by te		/// with 16-bit alignment would result in four 2-byte stores and one 1-by te
	/// store. This only applies to setting a constant array of a constant s ize.		/// store. This only applies to setting a constant array of a constant s ize.
	/// @brief Specify maximum number of store instructions per memset call.
	unsigned MaxStoresPerMemset;		unsigned MaxStoresPerMemset;
	/// Maximum number of stores operations that may be substituted for the c all		/// Maximum number of stores operations that may be substituted for the c all
	/// to memset, used for functions with OptSize attribute.		/// to memset, used for functions with OptSize attribute.
	unsigned MaxStoresPerMemsetOptSize;		unsigned MaxStoresPerMemsetOptSize;
			/// \brief Specify maximum bytes of store instructions per memcpy call.
			///
	/// When lowering \@llvm.memcpy this field specifies the maximum number o f		/// When lowering \@llvm.memcpy this field specifies the maximum number o f
	/// store operations that may be substituted for a call to memcpy. Target s		/// store operations that may be substituted for a call to memcpy. Target s
	/// must set this value based on the cost threshold for that target. Targ ets		/// must set this value based on the cost threshold for that target. Targ ets
	/// should assume that the memcpy will be done using as many of the large st		/// should assume that the memcpy will be done using as many of the large st
	/// store operations first, followed by smaller ones, if necessary, per		/// store operations first, followed by smaller ones, if necessary, per
	/// alignment restrictions. For example, storing 7 bytes on a 32-bit mach ine		/// alignment restrictions. For example, storing 7 bytes on a 32-bit mach ine
	/// with 32-bit alignment would result in one 4-byte store, a one 2-byte store		/// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
	/// and one 1-byte store. This only applies to copying a constant array o f		/// and one 1-byte store. This only applies to copying a constant array o f
	/// constant size.		/// constant size.
	/// @brief Specify maximum bytes of store instructions per memcpy call.
	unsigned MaxStoresPerMemcpy;		unsigned MaxStoresPerMemcpy;
	/// Maximum number of store operations that may be substituted for a call		/// Maximum number of store operations that may be substituted for a call
	/// to memcpy, used for functions with OptSize attribute.		to
			/// memcpy, used for functions with OptSize attribute.
	unsigned MaxStoresPerMemcpyOptSize;		unsigned MaxStoresPerMemcpyOptSize;
			/// \brief Specify maximum bytes of store instructions per memmove call.
			///
	/// When lowering \@llvm.memmove this field specifies the maximum number of		/// When lowering \@llvm.memmove this field specifies the maximum number of
	/// store instructions that may be substituted for a call to memmove. Tar gets		/// store instructions that may be substituted for a call to memmove. Tar gets
	/// must set this value based on the cost threshold for that target. Targ ets		/// must set this value based on the cost threshold for that target. Targ ets
	/// should assume that the memmove will be done using as many of the larg est		/// should assume that the memmove will be done using as many of the larg est
	/// store operations first, followed by smaller ones, if necessary, per		/// store operations first, followed by smaller ones, if necessary, per
	/// alignment restrictions. For example, moving 9 bytes on a 32-bit machi ne		/// alignment restrictions. For example, moving 9 bytes on a 32-bit machi ne
	/// with 8-bit alignment would result in nine 1-byte stores. This only		/// with 8-bit alignment would result in nine 1-byte stores. This only
	/// applies to copying a constant array of constant size.		/// applies to copying a constant array of constant size.
	/// @brief Specify maximum bytes of store instructions per memmove call.
	unsigned MaxStoresPerMemmove;		unsigned MaxStoresPerMemmove;
	/// Maximum number of store instructions that may be substituted for a ca		/// Maximum number of store instructions that may be substituted for a ca
	ll		ll to
	/// to memmove, used for functions with OpSize attribute.		/// memmove, used for functions with OpSize attribute.
	unsigned MaxStoresPerMemmoveOptSize;		unsigned MaxStoresPerMemmoveOptSize;
	/// PredictableSelectIsExpensive - Tells the code generator that select i		/// Tells the code generator that select is more expensive than a branch
	s		if
	/// more expensive than a branch if the branch is usually predicted right		/// the branch is usually predicted right.
	.
	bool PredictableSelectIsExpensive;		bool PredictableSelectIsExpensive;
	protected:		protected:
	/// isLegalRC - Return true if the value types that can be represented by		/// Return true if the value types that can be represented by the specifi
	the		ed
	/// specified register class are all legal.		/// register class are all legal.
	bool isLegalRC(const TargetRegisterClass *RC) const;		bool isLegalRC(const TargetRegisterClass *RC) const;
	};		};
	//===----------------------------------------------------------------------		/// This class defines information used to lower LLVM code to legal Selecti
	===//		onDAG
	/// TargetLowering - This class defines information used to lower LLVM code		/// operators that the target instruction selector can accept natively.
	to
	/// legal SelectionDAG operators that the target instruction selector can a
	ccept
	/// natively.
	///		///
	/// This class also defines callbacks that targets must implement to lower		/// This class also defines callbacks that targets must implement to lower
	/// target-specific constructs to SelectionDAG operators.		/// target-specific constructs to SelectionDAG operators.
	///
	class TargetLowering : public TargetLoweringBase {		class TargetLowering : public TargetLoweringBase {
	TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION;		TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION;
	void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION;		void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION;
	public:		public:
	/// NOTE: The constructor takes ownership of TLOF.		/// NOTE: The constructor takes ownership of TLOF.
	explicit TargetLowering(const TargetMachine &TM,		explicit TargetLowering(const TargetMachine &TM,
	const TargetLoweringObjectFile *TLOF);		const TargetLoweringObjectFile *TLOF);
	/// getPreIndexedAddressParts - returns true by value, base pointer and		/// Returns true by value, base pointer and offset pointer and addressing
	/// offset pointer and addressing mode by reference if the node's address		mode
	/// can be legally represented as pre-indexed load / store address.		/// by reference if the node's address can be legally represented as
			/// pre-indexed load / store address.
	virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,		virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
	SDValue &/*Offset*/,		SDValue &/*Offset*/,
	ISD::MemIndexedMode &/*AM*/,		ISD::MemIndexedMode &/*AM*/,
	SelectionDAG &/*DAG*/) const {		SelectionDAG &/*DAG*/) const {
	return false;		return false;
	}		}
	/// getPostIndexedAddressParts - returns true by value, base pointer and		/// Returns true by value, base pointer and offset pointer and addressing
	/// offset pointer and addressing mode by reference if this node can be		mode
	/// combined with a load / store to form a post-indexed load / store.		/// by reference if this node can be combined with a load / store to form
			a
			/// post-indexed load / store.
	virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,		virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
	SDValue &/*Base*/, SDValue &/*Off		SDValue &/*Base*/,
	set*/,		SDValue &/*Offset*/,
	ISD::MemIndexedMode &/*AM*/,		ISD::MemIndexedMode &/*AM*/,
	SelectionDAG &/*DAG*/) const {		SelectionDAG &/*DAG*/) const {
	return false;		return false;
	}		}
	/// getJumpTableEncoding - Return the entry encoding for a jump table in		/// Return the entry encoding for a jump table in the current function.
	the		The
	/// current function. The returned value is a member of the		/// returned value is a member of the MachineJumpTableInfo::JTEntryKind e
	/// MachineJumpTableInfo::JTEntryKind enum.		num.
	virtual unsigned getJumpTableEncoding() const;		virtual unsigned getJumpTableEncoding() const;
	virtual const MCExpr *		virtual const MCExpr *
	LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,		LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
	const MachineBasicBlock * /*MBB*/, unsigned /*u id*/,		const MachineBasicBlock * /*MBB*/, unsigned /*u id*/,
	MCContext &/*Ctx*/) const {		MCContext &/*Ctx*/) const {
	llvm_unreachable("Need to implement this hook if target has custom JTIs ");		llvm_unreachable("Need to implement this hook if target has custom JTIs ");
	}		}
	/// getPICJumpTableRelocaBase - Returns relocation base for the given PIC		/// Returns relocation base for the given PIC jumptable.
	/// jumptable.
	virtual SDValue getPICJumpTableRelocBase(SDValue Table,		virtual SDValue getPICJumpTableRelocBase(SDValue Table,
	SelectionDAG &DAG) const;		SelectionDAG &DAG) const;
	/// getPICJumpTableRelocBaseExpr - This returns the relocation base for t		/// This returns the relocation base for the given PIC jumptable, the sam
	he		e as
	/// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an		/// getPICJumpTableRelocBase, but as an MCExpr.
	/// MCExpr.
	virtual const MCExpr *		virtual const MCExpr *
	getPICJumpTableRelocBaseExpr(const MachineFunction *MF,		getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
	unsigned JTI, MCContext &Ctx) const;		unsigned JTI, MCContext &Ctx) const;
	/// isOffsetFoldingLegal - Return true if folding a constant offset		/// Return true if folding a constant offset with the given GlobalAddress
	/// with the given GlobalAddress is legal. It is frequently not legal in		is
	/// PIC relocation models.		/// legal. It is frequently not legal in PIC relocation models.
	virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;		virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
	bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,		bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
	SDValue &Chain) const;		SDValue &Chain) const;
	void softenSetCCOperands(SelectionDAG &DAG, EVT VT,		void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
	SDValue &NewLHS, SDValue &NewRHS,		SDValue &NewLHS, SDValue &NewRHS,
	ISD::CondCode &CCCode, DebugLoc DL) const;		ISD::CondCode &CCCode, SDLoc DL) const;
	SDValue makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT,		/// Returns a pair of (return value, chain).
	const SDValue *Ops, unsigned NumOps,		std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall
	bool isSigned, DebugLoc dl) const;		LC,
			EVT RetVT, const SDValue *Ops,
			unsigned NumOps, bool isSigned,
			SDLoc dl, bool doesNotReturn = fa
			lse,
			bool isReturnValueUsed = true) co
			nst;
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	// TargetLowering Optimization Methods		// TargetLowering Optimization Methods
	//		//
	/// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and		/// A convenience struct that encapsulates a DAG, and two SDValues for
	two		/// returning information from TargetLowering to its clients that want to
	/// SDValues for returning information from TargetLowering to its clients		/// combine.
	/// that want to combine
	struct TargetLoweringOpt {		struct TargetLoweringOpt {
	SelectionDAG &DAG;		SelectionDAG &DAG;
	bool LegalTys;		bool LegalTys;
	bool LegalOps;		bool LegalOps;
	SDValue Old;		SDValue Old;
	SDValue New;		SDValue New;
	explicit TargetLoweringOpt(SelectionDAG &InDAG,		explicit TargetLoweringOpt(SelectionDAG &InDAG,
	bool LT, bool LO) :		bool LT, bool LO) :
	DAG(InDAG), LegalTys(LT), LegalOps(LO) {}		DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
	bool LegalTypes() const { return LegalTys; }		bool LegalTypes() const { return LegalTys; }
	bool LegalOperations() const { return LegalOps; }		bool LegalOperations() const { return LegalOps; }
	bool CombineTo(SDValue O, SDValue N) {		bool CombineTo(SDValue O, SDValue N) {
	Old = O;		Old = O;
	New = N;		New = N;
	return true;		return true;
	}		}
	/// ShrinkDemandedConstant - Check to see if the specified operand of t		/// Check to see if the specified operand of the specified instruction
	he		is a
	/// specified instruction is a constant integer. If so, check to see i		/// constant integer. If so, check to see if there are any bits set in
	f		the
	/// there are any bits set in the constant that are not demanded. If s		/// constant that are not demanded. If so, shrink the constant and ret
	o,		urn
	/// shrink the constant and return true.		/// true.
	bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);		bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
	/// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if th		/// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free.
	e		This
	/// casts are free. This uses isZExtFree and ZERO_EXTEND for the widen		/// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could
	ing		be
	/// cast, but it could be generalized for targets with other types of		/// generalized for targets with other types of implicit widening casts
	/// implicit widening casts.		.
	bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Deman ded,		bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Deman ded,
	DebugLoc dl);		SDLoc dl);
	};		};
	/// SimplifyDemandedBits - Look at Op. At this point, we know that only		/// Look at Op. At this point, we know that only the DemandedMask bits o
	the		f the
	/// DemandedMask bits of the result of Op are ever used downstream. If w		/// result of Op are ever used downstream. If we can use this informatio
	e can		n to
	/// use this information to simplify Op, create a new simplified DAG node		/// simplify Op, create a new simplified DAG node and return true, return
	and		ing
	/// return true, returning the original and new nodes in Old and New.		/// the original and new nodes in Old and New. Otherwise, analyze the
	/// Otherwise, analyze the expression and return a mask of KnownOne and		/// expression and return a mask of KnownOne and KnownZero bits for the
	/// KnownZero bits for the expression (used to simplify the caller).		/// expression (used to simplify the caller). The KnownZero/One bits may
	/// The KnownZero/One bits may only be accurate for those bits in the		only
	/// DemandedMask.		/// be accurate for those bits in the DemandedMask.
	bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,		bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
	APInt &KnownZero, APInt &KnownOne,		APInt &KnownZero, APInt &KnownOne,
	TargetLoweringOpt &TLO, unsigned Depth = 0) con st;		TargetLoweringOpt &TLO, unsigned Depth = 0) con st;
	/// computeMaskedBitsForTargetNode - Determine which of the bits specifie		/// Determine which of the bits specified in Mask are known to be either
	d in		zero
	/// Mask are known to be either zero or one and return them in the		/// or one and return them in the KnownZero/KnownOne bitsets.
	/// KnownZero/KnownOne bitsets.
	virtual void computeMaskedBitsForTargetNode(const SDValue Op,		virtual void computeMaskedBitsForTargetNode(const SDValue Op,
	APInt &KnownZero,		APInt &KnownZero,
	APInt &KnownOne,		APInt &KnownOne,
	const SelectionDAG &DAG,		const SelectionDAG &DAG,
	unsigned Depth = 0) const;		unsigned Depth = 0) const;
	/// ComputeNumSignBitsForTargetNode - This method can be implemented by		/// This method can be implemented by targets that want to expose additio
	/// targets that want to expose additional information about sign bits to		nal
	the		/// information about sign bits to the DAG Combiner.
	/// DAG Combiner.
	virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,		virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
	unsigned Depth = 0) cons t;		unsigned Depth = 0) cons t;
	struct DAGCombinerInfo {		struct DAGCombinerInfo {
	void *DC; // The DAG Combiner object.		void *DC; // The DAG Combiner object.
	CombineLevel Level;		CombineLevel Level;
	bool CalledByLegalizer;		bool CalledByLegalizer;
	public:		public:
	SelectionDAG &DAG;		SelectionDAG &DAG;
	skipping to change at line 1821		skipping to change at line 1855
	void AddToWorklist(SDNode *N);		void AddToWorklist(SDNode *N);
	void RemoveFromWorklist(SDNode *N);		void RemoveFromWorklist(SDNode *N);
	SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,		SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
	bool AddTo = true);		bool AddTo = true);
	SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);		SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
	SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = t rue);		SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = t rue);
	void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);		void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
	};		};
	/// SimplifySetCC - Try to simplify a setcc built with the specified oper		/// Try to simplify a setcc built with the specified operands and cc. If
	ands		it is
	/// and cc. If it is unable to simplify it, return a null SDValue.		/// unable to simplify it, return a null SDValue.
	SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,		SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
	ISD::CondCode Cond, bool foldBooleans,		ISD::CondCode Cond, bool foldBooleans,
	DAGCombinerInfo &DCI, DebugLoc dl) const;		DAGCombinerInfo &DCI, SDLoc dl) const;
	/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if		/// Returns true (and the GlobalValue and the offset) if the node is a
	the		/// GlobalAddress + offset.
	/// node is a GlobalAddress + offset.
	virtual bool		virtual bool
	isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;		isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
	/// PerformDAGCombine - This method will be invoked for all target nodes		/// This method will be invoked for all target nodes and for any
	and		/// target-independent nodes that the target has registered with invoke i
	/// for any target-independent nodes that the target has registered with		t
	/// invoke it for.		/// for.
	///		///
	/// The semantics are as follows:		/// The semantics are as follows:
	/// Return Value:		/// Return Value:
	/// SDValue.Val == 0 - No change was made		/// SDValue.Val == 0 - No change was made
	/// SDValue.Val == N - N was replaced, is dead, and is already handle d.		/// SDValue.Val == N - N was replaced, is dead, and is already handle d.
	/// otherwise - N should be replaced by the returned Operand.		/// otherwise - N should be replaced by the returned Operand.
	///		///
	/// In addition, methods provided by DAGCombinerInfo may be used to perfo rm		/// In addition, methods provided by DAGCombinerInfo may be used to perfo rm
	/// more complex transformations.		/// more complex transformations.
	///		///
	virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;		virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
	/// isTypeDesirableForOp - Return true if the target has native support f		/// Return true if the target has native support for the specified value
	or		type
	/// the specified value type and it is 'desirable' to use the type for th		/// and it is 'desirable' to use the type for the given node type. e.g. O
	e		n x86
	/// given node type. e.g. On x86 i16 is legal, but undesirable since i16		/// i16 is legal, but undesirable since i16 instruction encodings are lon
	/// instruction encodings are longer and some i16 instructions are slow.		ger
			/// and some i16 instructions are slow.
	virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {		virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
	// By default, assume all legal types are desirable.		// By default, assume all legal types are desirable.
	return isTypeLegal(VT);		return isTypeLegal(VT);
	}		}
	/// isDesirableToPromoteOp - Return true if it is profitable for dag comb		/// Return true if it is profitable for dag combiner to transform a float
	iner		ing
	/// to transform a floating point op of specified opcode to a equivalent		/// point op of specified opcode to a equivalent op of an integer
	op of		/// type. e.g. f32 load -> i32 load can be profitable on ARM.
	/// an integer type. e.g. f32 load -> i32 load can be profitable on ARM.
	virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,		virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
	EVT /*VT*/) const {		EVT /*VT*/) const {
	return false;		return false;
	}		}
	/// IsDesirableToPromoteOp - This method query the target whether it is		/// This method query the target whether it is beneficial for dag combine
	/// beneficial for dag combiner to promote the specified node. If true, i		r to
	t		/// promote the specified node. If true, it should return the desired
	/// should return the desired promotion type by reference.		/// promotion type by reference.
	virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {		virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
	return false;		return false;
	}		}
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	// Lowering methods - These methods must be implemented by targets so tha t		// Lowering methods - These methods must be implemented by targets so tha t
	// the SelectionDAGBuilder code knows how to lower these.		// the SelectionDAGBuilder code knows how to lower these.
	//		//
	/// LowerFormalArguments - This hook must be implemented to lower the		/// This hook must be implemented to lower the incoming (formal) argument
	/// incoming (formal) arguments, described by the Ins array, into the		s,
	/// specified DAG. The implementation should fill in the InVals array		/// described by the Ins array, into the specified DAG. The implementatio
	/// with legal-type argument values, and return the resulting token		n
	/// chain value.		/// should fill in the InVals array with legal-type argument values, and
			/// return the resulting token chain value.
	///		///
	virtual SDValue		virtual SDValue
	LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,		LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
	bool /*isVarArg*/,		bool /*isVarArg*/,
	const SmallVectorImpl<ISD::InputArg> &/*Ins*/,		const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
	DebugLoc /*dl*/, SelectionDAG &/*DAG*/,		SDLoc /*dl*/, SelectionDAG &/*DAG*/,
	SmallVectorImpl<SDValue> &/*InVals*/) const {		SmallVectorImpl<SDValue> &/*InVals*/) const {
	llvm_unreachable("Not Implemented");		llvm_unreachable("Not Implemented");
	}		}
	struct ArgListEntry {		struct ArgListEntry {
	SDValue Node;		SDValue Node;
	Type* Ty;		Type* Ty;
	bool isSExt : 1;		bool isSExt : 1;
	bool isZExt : 1;		bool isZExt : 1;
	bool isInReg : 1;		bool isInReg : 1;
	bool isSRet : 1;		bool isSRet : 1;
	bool isNest : 1;		bool isNest : 1;
	bool isByVal : 1;		bool isByVal : 1;
	bool isReturned : 1;		bool isReturned : 1;
	uint16_t Alignment;		uint16_t Alignment;
	ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),		ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
	isSRet(false), isNest(false), isByVal(false), isReturned(false),		isSRet(false), isNest(false), isByVal(false), isReturned(false),
	Alignment(0) { }		Alignment(0) { }
			void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
	};		};
	typedef std::vector<ArgListEntry> ArgListTy;		typedef std::vector<ArgListEntry> ArgListTy;
	/// CallLoweringInfo - This structure contains all information that is		/// This structure contains all information that is necessary for lowerin
	/// necessary for lowering calls. It is passed to TLI::LowerCallTo when t		g
	he		/// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
	/// SelectionDAG builder needs to lower a call, and targets will see this		/// needs to lower a call, and targets will see this struct in their Lowe
	/// struct in their LowerCall implementation.		rCall
			/// implementation.
	struct CallLoweringInfo {		struct CallLoweringInfo {
	SDValue Chain;		SDValue Chain;
	Type *RetTy;		Type *RetTy;
	bool RetSExt : 1;		bool RetSExt : 1;
	bool RetZExt : 1;		bool RetZExt : 1;
	bool IsVarArg : 1;		bool IsVarArg : 1;
	bool IsInReg : 1;		bool IsInReg : 1;
	bool DoesNotReturn : 1;		bool DoesNotReturn : 1;
	bool IsReturnValueUsed : 1;		bool IsReturnValueUsed : 1;
	// IsTailCall should be modified by implementations of		// IsTailCall should be modified by implementations of
	// TargetLowering::LowerCall that perform tail call conversions.		// TargetLowering::LowerCall that perform tail call conversions.
	bool IsTailCall;		bool IsTailCall;
	unsigned NumFixedArgs;		unsigned NumFixedArgs;
	CallingConv::ID CallConv;		CallingConv::ID CallConv;
	SDValue Callee;		SDValue Callee;
	ArgListTy &Args;		ArgListTy &Args;
	SelectionDAG &DAG;		SelectionDAG &DAG;
	DebugLoc DL;		SDLoc DL;
	ImmutableCallSite *CS;		ImmutableCallSite *CS;
	SmallVector<ISD::OutputArg, 32> Outs;		SmallVector<ISD::OutputArg, 32> Outs;
	SmallVector<SDValue, 32> OutVals;		SmallVector<SDValue, 32> OutVals;
	SmallVector<ISD::InputArg, 32> Ins;		SmallVector<ISD::InputArg, 32> Ins;
	/// CallLoweringInfo - Constructs a call lowering context based on the		/// Constructs a call lowering context based on the ImmutableCallSite \
	/// ImmutableCallSite \p cs.		p cs.
	CallLoweringInfo(SDValue chain, Type *retTy,		CallLoweringInfo(SDValue chain, Type *retTy,
	FunctionType *FTy, bool isTailCall, SDValue callee,		FunctionType *FTy, bool isTailCall, SDValue callee,
	ArgListTy &args, SelectionDAG &dag, DebugLoc dl,		ArgListTy &args, SelectionDAG &dag, SDLoc dl,
	ImmutableCallSite &cs)		ImmutableCallSite &cs)
	: Chain(chain), RetTy(retTy), RetSExt(cs.paramHasAttr(0, Attribute::SEx t)),		: Chain(chain), RetTy(retTy), RetSExt(cs.paramHasAttr(0, Attribute::SEx t)),
	RetZExt(cs.paramHasAttr(0, Attribute::ZExt)), IsVarArg(FTy->isVarArg( )),		RetZExt(cs.paramHasAttr(0, Attribute::ZExt)), IsVarArg(FTy->isVarArg( )),
	IsInReg(cs.paramHasAttr(0, Attribute::InReg)),		IsInReg(cs.paramHasAttr(0, Attribute::InReg)),
	DoesNotReturn(cs.doesNotReturn()),		DoesNotReturn(cs.doesNotReturn()),
	IsReturnValueUsed(!cs.getInstruction()->use_empty()),		IsReturnValueUsed(!cs.getInstruction()->use_empty()),
	IsTailCall(isTailCall), NumFixedArgs(FTy->getNumParams()),		IsTailCall(isTailCall), NumFixedArgs(FTy->getNumParams()),
	CallConv(cs.getCallingConv()), Callee(callee), Args(args), DAG(dag),		CallConv(cs.getCallingConv()), Callee(callee), Args(args), DAG(dag),
	DL(dl), CS(&cs) {}		DL(dl), CS(&cs) {}
	/// CallLoweringInfo - Constructs a call lowering context based on the		/// Constructs a call lowering context based on the provided call
	/// provided call information.		/// information.
	CallLoweringInfo(SDValue chain, Type *retTy, bool retSExt, bool retZExt ,		CallLoweringInfo(SDValue chain, Type *retTy, bool retSExt, bool retZExt ,
	bool isVarArg, bool isInReg, unsigned numFixedArgs,		bool isVarArg, bool isInReg, unsigned numFixedArgs,
	CallingConv::ID callConv, bool isTailCall,		CallingConv::ID callConv, bool isTailCall,
	bool doesNotReturn, bool isReturnValueUsed, SDValue ca llee,		bool doesNotReturn, bool isReturnValueUsed, SDValue ca llee,
	ArgListTy &args, SelectionDAG &dag, DebugLoc dl)		ArgListTy &args, SelectionDAG &dag, SDLoc dl)
	: Chain(chain), RetTy(retTy), RetSExt(retSExt), RetZExt(retZExt),		: Chain(chain), RetTy(retTy), RetSExt(retSExt), RetZExt(retZExt),
	IsVarArg(isVarArg), IsInReg(isInReg), DoesNotReturn(doesNotReturn),		IsVarArg(isVarArg), IsInReg(isInReg), DoesNotReturn(doesNotReturn),
	IsReturnValueUsed(isReturnValueUsed), IsTailCall(isTailCall),		IsReturnValueUsed(isReturnValueUsed), IsTailCall(isTailCall),
	NumFixedArgs(numFixedArgs), CallConv(callConv), Callee(callee),		NumFixedArgs(numFixedArgs), CallConv(callConv), Callee(callee),
	Args(args), DAG(dag), DL(dl), CS(NULL) {}		Args(args), DAG(dag), DL(dl), CS(NULL) {}
	};		};
	/// LowerCallTo - This function lowers an abstract call to a function int		/// This function lowers an abstract call to a function into an actual ca
	o an		ll.
	/// actual call. This returns a pair of operands. The first element is		/// This returns a pair of operands. The first element is the return val
	the		ue
	/// return value for the function (if RetTy is not VoidTy). The second		/// for the function (if RetTy is not VoidTy). The second element is the
	/// element is the outgoing token chain. It calls LowerCall to do the act		/// outgoing token chain. It calls LowerCall to do the actual lowering.
	ual
	/// lowering.
	std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;		std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
	/// LowerCall - This hook must be implemented to lower calls into the		/// This hook must be implemented to lower calls into the the specified
	/// the specified DAG. The outgoing arguments to the call are described		/// DAG. The outgoing arguments to the call are described by the Outs arr
	/// by the Outs array, and the values to be returned by the call are		ay,
	/// described by the Ins array. The implementation should fill in the		/// and the values to be returned by the call are described by the Ins
	/// InVals array with legal-type return values from the call, and return		/// array. The implementation should fill in the InVals array with legal-
	/// the resulting token chain value.		type
			/// return values from the call, and return the resulting token chain val
			ue.
	virtual SDValue		virtual SDValue
	LowerCall(CallLoweringInfo &/*CLI*/,		LowerCall(CallLoweringInfo &/*CLI*/,
	SmallVectorImpl<SDValue> &/*InVals*/) const {		SmallVectorImpl<SDValue> &/*InVals*/) const {
	llvm_unreachable("Not Implemented");		llvm_unreachable("Not Implemented");
	}		}
	/// HandleByVal - Target-specific cleanup for formal ByVal parameters.		/// Target-specific cleanup for formal ByVal parameters.
	virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}		virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
	/// CanLowerReturn - This hook should be implemented to check whether the		/// This hook should be implemented to check whether the return values
	/// return values described by the Outs array can fit into the return		/// described by the Outs array can fit into the return registers. If fa
	/// registers. If false is returned, an sret-demotion is performed.		lse
	///		/// is returned, an sret-demotion is performed.
	virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,		virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
	MachineFunction &/*MF*/, bool /*isVarArg*/,		MachineFunction &/*MF*/, bool /*isVarArg*/,
	const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,		const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
	LLVMContext &/*Context*/) const		LLVMContext &/*Context*/) const
	{		{
	// Return true by default to get preexisting behavior.		// Return true by default to get preexisting behavior.
	return true;		return true;
	}		}
	/// LowerReturn - This hook must be implemented to lower outgoing		/// This hook must be implemented to lower outgoing return values, descri
	/// return values, described by the Outs array, into the specified		bed
	/// DAG. The implementation should return the resulting token chain		/// by the Outs array, into the specified DAG. The implementation should
	/// value.		/// return the resulting token chain value.
	///
	virtual SDValue		virtual SDValue
	LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,		LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
	bool /*isVarArg*/,		bool /*isVarArg*/,
	const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,		const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
	const SmallVectorImpl<SDValue> &/*OutVals*/,		const SmallVectorImpl<SDValue> &/*OutVals*/,
	DebugLoc /*dl*/, SelectionDAG &/*DAG*/) const {		SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
	llvm_unreachable("Not Implemented");		llvm_unreachable("Not Implemented");
	}		}
	/// isUsedByReturnOnly - Return true if result of the specified node is u		/// Return true if result of the specified node is used by a return node
	sed		/// only. It also compute and return the input chain for the tail call.
	/// by a return node only. It also compute and return the input chain for		///
	the		/// This is used to determine whether it is possible to codegen a libcall
	/// tail call.		as
	/// This is used to determine whether it is possible		/// tail call at legalization time.
	/// to codegen a libcall as tail call at legalization time.		virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
	virtual bool isUsedByReturnOnly(SDNode *, SDValue &Chain) const {
	return false;		return false;
	}		}
	/// mayBeEmittedAsTailCall - Return true if the target may be able emit t		/// Return true if the target may be able emit the call instruction as a
	he		tail
	/// call instruction as a tail call. This is used by optimization passes		/// call. This is used by optimization passes to determine if it's profit
	to		able
	/// determine if it's profitable to duplicate return instructions to enab		/// to duplicate return instructions to enable tailcall optimization.
	le
	/// tailcall optimization.
	virtual bool mayBeEmittedAsTailCall(CallInst *) const {		virtual bool mayBeEmittedAsTailCall(CallInst *) const {
	return false;		return false;
	}		}
	/// getTypeForExtArgOrReturn - Return the type that should be used to zer		/// Return the type that should be used to zero or sign extend a
	o or		/// zeroext/signext integer argument or return value. FIXME: Most C call
	/// sign extend a zeroext/signext integer argument or return value.		ing
	/// FIXME: Most C calling convention requires the return type to be promo		/// convention requires the return type to be promoted, but this is not t
	ted,		rue
	/// but this is not true all the time, e.g. i1 on x86-64. It is also not		/// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
	/// necessary for non-C calling conventions. The frontend should handle t		/// calling conventions. The frontend should handle this and include all
	his		of
	/// and include all of the necessary information.		/// the necessary information.
	virtual MVT getTypeForExtArgOrReturn(MVT VT,		virtual MVT getTypeForExtArgOrReturn(MVT VT,
	ISD::NodeType /*ExtendKind*/) const {		ISD::NodeType /*ExtendKind*/) const {
	MVT MinVT = getRegisterType(MVT::i32);		MVT MinVT = getRegisterType(MVT::i32);
	return VT.bitsLT(MinVT) ? MinVT : VT;		return VT.bitsLT(MinVT) ? MinVT : VT;
	}		}
	/// LowerOperationWrapper - This callback is invoked by the type legalize		/// Returns a 0 terminated array of registers that can be safely used as
	r		/// scratch registers.
	/// to legalize nodes with an illegal operand type but legal result types		virtual const uint16_t *getScratchRegisters(CallingConv::ID CC) const {
	.		return NULL;
	/// It replaces the LowerOperation callback in the type Legalizer.		}
	/// The reason we can not do away with LowerOperation entirely is that
	/// LegalizeDAG isn't yet ready to use this callback.
	/// TODO: Consider merging with ReplaceNodeResults.
			/// This callback is invoked by the type legalizer to legalize nodes with
			an
			/// illegal operand type but legal result types. It replaces the
			/// LowerOperation callback in the type Legalizer. The reason we can not
			do
			/// away with LowerOperation entirely is that LegalizeDAG isn't yet ready
			to
			/// use this callback.
			///
			/// TODO: Consider merging with ReplaceNodeResults.
			///
	/// The target places new result values for the node in Results (their nu mber		/// The target places new result values for the node in Results (their nu mber
	/// and types must exactly match those of the original return values of		/// and types must exactly match those of the original return values of
	/// the node), or leaves Results empty, which indicates that the node is not		/// the node), or leaves Results empty, which indicates that the node is not
	/// to be custom lowered after all.		/// to be custom lowered after all.
	/// The default implementation calls LowerOperation.		/// The default implementation calls LowerOperation.
	virtual void LowerOperationWrapper(SDNode *N,		virtual void LowerOperationWrapper(SDNode *N,
	SmallVectorImpl<SDValue> &Results,		SmallVectorImpl<SDValue> &Results,
	SelectionDAG &DAG) const;		SelectionDAG &DAG) const;
	/// LowerOperation - This callback is invoked for operations that are		/// This callback is invoked for operations that are unsupported by the
	/// unsupported by the target, which are registered to use 'custom' lower		/// target, which are registered to use 'custom' lowering, and whose defi
	ing,		ned
	/// and whose defined values are all legal.		/// values are all legal. If the target has no operations that require c
	/// If the target has no operations that require custom lowering, it need		ustom
	not		/// lowering, it need not implement this. The default implementation of
	/// implement this. The default implementation of this aborts.		this
			/// aborts.
	virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;		virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
	/// ReplaceNodeResults - This callback is invoked when a node result type		/// This callback is invoked when a node result type is illegal for the
	is		/// target, and the operation was registered to use 'custom' lowering for
	/// illegal for the target, and the operation was registered to use 'cust		that
	om'		/// result type. The target places new result values for the node in Res
	/// lowering for that result type. The target places new result values f		ults
	or		/// (their number and types must exactly match those of the original retu
	/// the node in Results (their number and types must exactly match those		rn
	of		/// values of the node), or leaves Results empty, which indicates that th
	/// the original return values of the node), or leaves Results empty, whi		e
	ch		/// node is not to be custom lowered after all.
	/// indicates that the node is not to be custom lowered after all.
	///		///
	/// If the target has no operations that require custom lowering, it need not		/// If the target has no operations that require custom lowering, it need not
	/// implement this. The default implementation aborts.		/// implement this. The default implementation aborts.
	virtual void ReplaceNodeResults(SDNode * /*N*/,		virtual void ReplaceNodeResults(SDNode * /*N*/,
	SmallVectorImpl<SDValue> &/*Results*/,		SmallVectorImpl<SDValue> &/*Results*/,
	SelectionDAG &/*DAG*/) const {		SelectionDAG &/*DAG*/) const {
	llvm_unreachable("ReplaceNodeResults not implemented for this target!") ;		llvm_unreachable("ReplaceNodeResults not implemented for this target!") ;
	}		}
	/// getTargetNodeName() - This method returns the name of a target specif		/// This method returns the name of a target specific DAG node.
	ic
	/// DAG node.
	virtual const char *getTargetNodeName(unsigned Opcode) const;		virtual const char *getTargetNodeName(unsigned Opcode) const;
	/// createFastISel - This method returns a target specific FastISel objec		/// This method returns a target specific FastISel object, or null if the
	t,		/// target does not support "fast" ISel.
	/// or null if the target does not support "fast" ISel.
	virtual FastISel *createFastISel(FunctionLoweringInfo &,		virtual FastISel *createFastISel(FunctionLoweringInfo &,
	const TargetLibraryInfo *) const {		const TargetLibraryInfo *) const {
	return 0;		return 0;
	}		}
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	// Inline Asm Support hooks		// Inline Asm Support hooks
	//		//
	/// ExpandInlineAsm - This hook allows the target to expand an inline asm		/// This hook allows the target to expand an inline asm call to be explic
	/// call to be explicit llvm code if it wants to. This is useful for		it
	/// turning simple inline asms into LLVM intrinsics, which gives the		/// llvm code if it wants to. This is useful for turning simple inline a
	/// compiler more information about the behavior of the code.		sms
			/// into LLVM intrinsics, which gives the compiler more information about
			the
			/// behavior of the code.
	virtual bool ExpandInlineAsm(CallInst *) const {		virtual bool ExpandInlineAsm(CallInst *) const {
	return false;		return false;
	}		}
	enum ConstraintType {		enum ConstraintType {
	C_Register, // Constraint represents specific register(s).		C_Register, // Constraint represents specific register(s).
	C_RegisterClass, // Constraint represents any of register(s) in c lass.		C_RegisterClass, // Constraint represents any of register(s) in c lass.
	C_Memory, // Memory constraint.		C_Memory, // Memory constraint.
	C_Other, // Something else.		C_Other, // Something else.
	C_Unknown // Unsupported constraint.		C_Unknown // Unsupported constraint.
	skipping to change at line 2130		skipping to change at line 2164
	CW_Best = 3, // Best weight.		CW_Best = 3, // Best weight.
	// Well-known weights.		// Well-known weights.
	CW_SpecificReg = CW_Okay, // Specific register operands.		CW_SpecificReg = CW_Okay, // Specific register operands.
	CW_Register = CW_Good, // Register operands.		CW_Register = CW_Good, // Register operands.
	CW_Memory = CW_Better, // Memory operands.		CW_Memory = CW_Better, // Memory operands.
	CW_Constant = CW_Best, // Constant operand.		CW_Constant = CW_Best, // Constant operand.
	CW_Default = CW_Okay // Default or don't know type.		CW_Default = CW_Okay // Default or don't know type.
	};		};
	/// AsmOperandInfo - This contains information for each constraint that w		/// This contains information for each constraint that we are lowering.
	e are
	/// lowering.
	struct AsmOperandInfo : public InlineAsm::ConstraintInfo {		struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
	/// ConstraintCode - This contains the actual string for the code, like		/// This contains the actual string for the code, like "m". TargetLowe
	"m".		ring
	/// TargetLowering picks the 'best' code from ConstraintInfo::Codes tha		/// picks the 'best' code from ConstraintInfo::Codes that most closely
	t		/// matches the operand.
	/// most closely matches the operand.
	std::string ConstraintCode;		std::string ConstraintCode;
	/// ConstraintType - Information about the constraint code, e.g. Regist		/// Information about the constraint code, e.g. Register, RegisterClass
	er,		,
	/// RegisterClass, Memory, Other, Unknown.		/// Memory, Other, Unknown.
	TargetLowering::ConstraintType ConstraintType;		TargetLowering::ConstraintType ConstraintType;
	/// CallOperandval - If this is the result output operand or a		/// If this is the result output operand or a clobber, this is null,
	/// clobber, this is null, otherwise it is the incoming operand to the		/// otherwise it is the incoming operand to the CallInst. This gets
	/// CallInst. This gets modified as the asm is processed.		/// modified as the asm is processed.
	Value *CallOperandVal;		Value *CallOperandVal;
	/// ConstraintVT - The ValueType for the operand value.		/// The ValueType for the operand value.
	MVT ConstraintVT;		MVT ConstraintVT;
	/// isMatchingInputConstraint - Return true of this is an input operand		/// Return true of this is an input operand that is a matching constrai
	that		nt
	/// is a matching constraint like "4".		/// like "4".
	bool isMatchingInputConstraint() const;		bool isMatchingInputConstraint() const;
	/// getMatchedOperand - If this is an input matching constraint, this m		/// If this is an input matching constraint, this method returns the ou
	ethod		tput
	/// returns the output operand it matches.		/// operand it matches.
	unsigned getMatchedOperand() const;		unsigned getMatchedOperand() const;
	/// Copy constructor for copying from an AsmOperandInfo.		/// Copy constructor for copying from an AsmOperandInfo.
	AsmOperandInfo(const AsmOperandInfo &info)		AsmOperandInfo(const AsmOperandInfo &info)
	: InlineAsm::ConstraintInfo(info),		: InlineAsm::ConstraintInfo(info),
	ConstraintCode(info.ConstraintCode),		ConstraintCode(info.ConstraintCode),
	ConstraintType(info.ConstraintType),		ConstraintType(info.ConstraintType),
	CallOperandVal(info.CallOperandVal),		CallOperandVal(info.CallOperandVal),
	ConstraintVT(info.ConstraintVT) {		ConstraintVT(info.ConstraintVT) {
	}		}
	skipping to change at line 2177		skipping to change at line 2210
	/// Copy constructor for copying from a ConstraintInfo.		/// Copy constructor for copying from a ConstraintInfo.
	AsmOperandInfo(const InlineAsm::ConstraintInfo &info)		AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
	: InlineAsm::ConstraintInfo(info),		: InlineAsm::ConstraintInfo(info),
	ConstraintType(TargetLowering::C_Unknown),		ConstraintType(TargetLowering::C_Unknown),
	CallOperandVal(0), ConstraintVT(MVT::Other) {		CallOperandVal(0), ConstraintVT(MVT::Other) {
	}		}
	};		};
	typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;		typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
	/// ParseConstraints - Split up the constraint string from the inline		/// Split up the constraint string from the inline assembly value into th
	/// assembly value into the specific constraints and their prefixes,		e
	/// and also tie in the associated operand values.		/// specific constraints and their prefixes, and also tie in the associat
	/// If this returns an empty vector, and if the constraint string itself		ed
	/// isn't empty, there was an error parsing.		/// operand values. If this returns an empty vector, and if the constrai
			nt
			/// string itself isn't empty, there was an error parsing.
	virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const ;		virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const ;
	/// Examine constraint type and operand type and determine a weight value .		/// Examine constraint type and operand type and determine a weight value .
	/// The operand object must already have been set up with the operand typ e.		/// The operand object must already have been set up with the operand typ e.
	virtual ConstraintWeight getMultipleConstraintMatchWeight(		virtual ConstraintWeight getMultipleConstraintMatchWeight(
	AsmOperandInfo &info, int maIndex) const;		AsmOperandInfo &info, int maIndex) const;
	/// Examine constraint string and operand type and determine a weight val ue.		/// Examine constraint string and operand type and determine a weight val ue.
	/// The operand object must already have been set up with the operand typ e.		/// The operand object must already have been set up with the operand typ e.
	virtual ConstraintWeight getSingleConstraintMatchWeight(		virtual ConstraintWeight getSingleConstraintMatchWeight(
	AsmOperandInfo &info, const char *constraint) const;		AsmOperandInfo &info, const char *constraint) const;
	/// ComputeConstraintToUse - Determines the constraint code and constrain		/// Determines the constraint code and constraint type to use for the spe
	t		cific
	/// type to use for the specific AsmOperandInfo, setting		/// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintTy
	/// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual opera		pe.
	nd		/// If the actual operand being passed in is available, it can be passed
	/// being passed in is available, it can be passed in as Op, otherwise an		in as
	/// empty SDValue can be passed.		/// Op, otherwise an empty SDValue can be passed.
	virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,		virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
	SDValue Op,		SDValue Op,
	SelectionDAG *DAG = 0) const;		SelectionDAG *DAG = 0) const;
	/// getConstraintType - Given a constraint, return the type of constraint		/// Given a constraint, return the type of constraint it is for this targ
	it		et.
	/// is for this target.
	virtual ConstraintType getConstraintType(const std::string &Constraint) c onst;		virtual ConstraintType getConstraintType(const std::string &Constraint) c onst;
	/// getRegForInlineAsmConstraint - Given a physical register constraint (		/// Given a physical register constraint (e.g. {edx}), return the regist
	e.g.		er
	/// {edx}), return the register number and the register class for the		/// number and the register class for the register.
	/// register.
	///		///
	/// Given a register class constraint, like 'r', if this corresponds dire ctly		/// Given a register class constraint, like 'r', if this corresponds dire ctly
	/// to an LLVM register class, return a register of 0 and the register cl ass		/// to an LLVM register class, return a register of 0 and the register cl ass
	/// pointer.		/// pointer.
	///		///
	/// This should only be used for C_Register constraints. On error,		/// This should only be used for C_Register constraints. On error, this
	/// this returns a register number of 0 and a null register class pointer		/// returns a register number of 0 and a null register class pointer..
	..
	virtual std::pair<unsigned, const TargetRegisterClass*>		virtual std::pair<unsigned, const TargetRegisterClass*>
	getRegForInlineAsmConstraint(const std::string &Constraint,		getRegForInlineAsmConstraint(const std::string &Constraint,
	EVT VT) const;		MVT VT) const;
	/// LowerXConstraint - try to replace an X constraint, which matches anyt		/// Try to replace an X constraint, which matches anything, with another
	hing,		that
	/// with another that has more specific requirements based on the type of		/// has more specific requirements based on the type of the corresponding
	the		/// operand. This returns null if there is no replacement to make.
	/// corresponding operand. This returns null if there is no replacement
	to
	/// make.
	virtual const char *LowerXConstraint(EVT ConstraintVT) const;		virtual const char *LowerXConstraint(EVT ConstraintVT) const;
	/// LowerAsmOperandForConstraint - Lower the specified operand into the O		/// Lower the specified operand into the Ops vector. If it is invalid, d
	ps		on't
	/// vector. If it is invalid, don't add anything to Ops.		/// add anything to Ops.
	virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constr aint,		virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constr aint,
	std::vector<SDValue> &Ops,		std::vector<SDValue> &Ops,
	SelectionDAG &DAG) const;		SelectionDAG &DAG) const;
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	// Div utility functions		// Div utility functions
	//		//
	SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,		SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
	SelectionDAG &DAG) const;		SelectionDAG &DAG) const;
	SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,		SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
	std::vector<SDNode*> *Created) const;		std::vector<SDNode*> *Created) const;
	SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,		SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
	std::vector<SDNode*> *Created) const;		std::vector<SDNode*> *Created) const;
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	// Instruction Emitting Hooks		// Instruction Emitting Hooks
	//		//
	// EmitInstrWithCustomInserter - This method should be implemented by tar		/// This method should be implemented by targets that mark instructions w
	gets		ith
	// that mark instructions with the 'usesCustomInserter' flag. These		/// the 'usesCustomInserter' flag. These instructions are special in var
	// instructions are special in various ways, which require special suppor		ious
	t to		/// ways, which require special support to insert. The specified Machine
	// insert. The specified MachineInstr is created but not inserted into a		Instr
	ny		/// is created but not inserted into any basic blocks, and this method is
	// basic blocks, and this method is called to expand it into a sequence o		/// called to expand it into a sequence of instructions, potentially also
	f		/// creating new basic blocks and control flow.
	// instructions, potentially also creating new basic blocks and control f
	low.
	virtual MachineBasicBlock *		virtual MachineBasicBlock *
	EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) c onst;		EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) c onst;
	/// AdjustInstrPostInstrSelection - This method should be implemented by		/// This method should be implemented by targets that mark instructions w
	/// targets that mark instructions with the 'hasPostISelHook' flag. These		ith
	/// instructions must be adjusted after instruction selection by target h		/// the 'hasPostISelHook' flag. These instructions must be adjusted after
	ooks.		/// instruction selection by target hooks. e.g. To fill in optional defs
	/// e.g. To fill in optional defs for ARM 's' setting instructions.		for
			/// ARM 's' setting instructions.
	virtual void		virtual void
	AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;		AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
	};		};
	/// GetReturnInfo - Given an LLVM IR type and return type attributes,		/// Given an LLVM IR type and return type attributes, compute the return va
	/// compute the return value EVTs and flags, and optionally also		lue
	/// the offsets, if the return value is being lowered to memory.		/// EVTs and flags, and optionally also the offsets, if the return value is
			/// being lowered to memory.
	void GetReturnInfo(Type* ReturnType, AttributeSet attr,		void GetReturnInfo(Type* ReturnType, AttributeSet attr,
	SmallVectorImpl<ISD::OutputArg> &Outs,		SmallVectorImpl<ISD::OutputArg> &Outs,
	const TargetLowering &TLI);		const TargetLowering &TLI);
	} // end llvm namespace		} // end llvm namespace
	#endif		#endif
End of changes. 268 change blocks.
	982 lines changed or deleted		1033 lines changed or added

	TargetLoweringObjectFile.h		TargetLoweringObjectFile.h
	skipping to change at line 120		skipping to change at line 120
	}		}
	/// getTTypeGlobalReference - Return an MCExpr to use for a reference		/// getTTypeGlobalReference - Return an MCExpr to use for a reference
	/// to the specified global variable from exception handling information.		/// to the specified global variable from exception handling information.
	///		///
	virtual const MCExpr *		virtual const MCExpr *
	getTTypeGlobalReference(const GlobalValue *GV, Mangler *Mang,		getTTypeGlobalReference(const GlobalValue *GV, Mangler *Mang,
	MachineModuleInfo *MMI, unsigned Encoding,		MachineModuleInfo *MMI, unsigned Encoding,
	MCStreamer &Streamer) const;		MCStreamer &Streamer) const;
			/// Return the MCSymbol for the specified global value. This symbol is t
			he
			/// main label that is the address of the global
			MCSymbol *getSymbol(Mangler &M, const GlobalValue *GV) const;
	// getCFIPersonalitySymbol - The symbol that gets passed to .cfi_personal ity.		// getCFIPersonalitySymbol - The symbol that gets passed to .cfi_personal ity.
	virtual MCSymbol *		virtual MCSymbol *
	getCFIPersonalitySymbol(const GlobalValue *GV, Mangler *Mang,		getCFIPersonalitySymbol(const GlobalValue *GV, Mangler *Mang,
	MachineModuleInfo *MMI) const;		MachineModuleInfo *MMI) const;
	///		///
	const MCExpr *		const MCExpr *
	getTTypeReference(const MCSymbolRefExpr *Sym, unsigned Encoding,		getTTypeReference(const MCSymbolRefExpr *Sym, unsigned Encoding,
	MCStreamer &Streamer) const;		MCStreamer &Streamer) const;
	skipping to change at line 141		skipping to change at line 145
	getStaticCtorSection(unsigned Priority = 65535) const {		getStaticCtorSection(unsigned Priority = 65535) const {
	(void)Priority;		(void)Priority;
	return StaticCtorSection;		return StaticCtorSection;
	}		}
	virtual const MCSection *		virtual const MCSection *
	getStaticDtorSection(unsigned Priority = 65535) const {		getStaticDtorSection(unsigned Priority = 65535) const {
	(void)Priority;		(void)Priority;
	return StaticDtorSection;		return StaticDtorSection;
	}		}
			/// \brief Create a symbol reference to describe the given TLS variable w
			hen
			/// emitting the address in debug info.
			virtual const MCExpr *getDebugThreadLocalSymbol(const MCSymbol *Sym) cons
			t;
	protected:		protected:
	virtual const MCSection *		virtual const MCSection *
	SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind,		SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind,
	Mangler *Mang, const TargetMachine &TM) const;		Mangler *Mang, const TargetMachine &TM) const;
	};		};
	} // end namespace llvm		} // end namespace llvm
	#endif		#endif
End of changes. 2 change blocks.
	0 lines changed or deleted		11 lines changed or added

	TargetMachine.h		TargetMachine.h
	skipping to change at line 60		skipping to change at line 60
	LLVMCodeModelMedium,		LLVMCodeModelMedium,
	LLVMCodeModelLarge		LLVMCodeModelLarge
	} LLVMCodeModel;		} LLVMCodeModel;
	typedef enum {		typedef enum {
	LLVMAssemblyFile,		LLVMAssemblyFile,
	LLVMObjectFile		LLVMObjectFile
	} LLVMCodeGenFileType;		} LLVMCodeGenFileType;
	/** Returns the first llvm::Target in the registered targets list. */		/** Returns the first llvm::Target in the registered targets list. */
	LLVMTargetRef LLVMGetFirstTarget();		LLVMTargetRef LLVMGetFirstTarget(void);
	/** Returns the next llvm::Target given a previous one (or null if there's none) */		/** Returns the next llvm::Target given a previous one (or null if there's none) */
	LLVMTargetRef LLVMGetNextTarget(LLVMTargetRef T);		LLVMTargetRef LLVMGetNextTarget(LLVMTargetRef T);
	/*===-- Target ------------------------------------------------------------ ===*/		/*===-- Target ------------------------------------------------------------ ===*/
			/** Finds the target corresponding to the given name and stores it in \p T.
			Returns 0 on success. */
			LLVMTargetRef LLVMGetTargetFromName(const char *Name);
			/** Finds the target corresponding to the given triple and stores it in \p
			T.
			Returns 0 on success. Optionally returns any error in ErrorMessage.
			Use LLVMDisposeMessage to dispose the message. */
			LLVMBool LLVMGetTargetFromTriple(const char* Triple, LLVMTargetRef *T,
			char **ErrorMessage);
	/** Returns the name of a target. See llvm::Target::getName */		/** Returns the name of a target. See llvm::Target::getName */
	const char *LLVMGetTargetName(LLVMTargetRef T);		const char *LLVMGetTargetName(LLVMTargetRef T);
	/** Returns the description of a target. See llvm::Target::getDescription */		/** Returns the description of a target. See llvm::Target::getDescription */
	const char *LLVMGetTargetDescription(LLVMTargetRef T);		const char *LLVMGetTargetDescription(LLVMTargetRef T);
	/** Returns if the target has a JIT */		/** Returns if the target has a JIT */
	LLVMBool LLVMTargetHasJIT(LLVMTargetRef T);		LLVMBool LLVMTargetHasJIT(LLVMTargetRef T);
	/** Returns if the target has a TargetMachine associated */		/** Returns if the target has a TargetMachine associated */
	LLVMBool LLVMTargetHasTargetMachine(LLVMTargetRef T);		LLVMBool LLVMTargetHasTargetMachine(LLVMTargetRef T);
	/** Returns if the target as an ASM backend (required for emitting output) */		/** Returns if the target as an ASM backend (required for emitting output) */
	LLVMBool LLVMTargetHasAsmBackend(LLVMTargetRef T);		LLVMBool LLVMTargetHasAsmBackend(LLVMTargetRef T);
	/*===-- Target Machine ---------------------------------------------------- ===*/		/*===-- Target Machine ---------------------------------------------------- ===*/
	/** Creates a new llvm::TargetMachine. See llvm::Target::createTargetMachin e */		/** Creates a new llvm::TargetMachine. See llvm::Target::createTargetMachin e */
	LLVMTargetMachineRef LLVMCreateTargetMachine(LLVMTargetRef T, char *Triple,		LLVMTargetMachineRef LLVMCreateTargetMachine(LLVMTargetRef T,
	char *CPU, char *Features, LLVMCodeGenOptLevel Level, LLVMRelocMode Reloc		const char *Triple, const char *CPU, const char *Features,
	,		LLVMCodeGenOptLevel Level, LLVMRelocMode Reloc, LLVMCodeModel CodeModel);
	LLVMCodeModel CodeModel);
	/** Dispose the LLVMTargetMachineRef instance generated by		/** Dispose the LLVMTargetMachineRef instance generated by
	LLVMCreateTargetMachine. */		LLVMCreateTargetMachine. */
	void LLVMDisposeTargetMachine(LLVMTargetMachineRef T);		void LLVMDisposeTargetMachine(LLVMTargetMachineRef T);
	/** Returns the Target used in a TargetMachine */		/** Returns the Target used in a TargetMachine */
	LLVMTargetRef LLVMGetTargetMachineTarget(LLVMTargetMachineRef T);		LLVMTargetRef LLVMGetTargetMachineTarget(LLVMTargetMachineRef T);
	/** Returns the triple used creating this target machine. See		/** Returns the triple used creating this target machine. See
	llvm::TargetMachine::getTriple. The result needs to be disposed with		llvm::TargetMachine::getTriple. The result needs to be disposed with
	skipping to change at line 111		skipping to change at line 121
	char *LLVMGetTargetMachineCPU(LLVMTargetMachineRef T);		char *LLVMGetTargetMachineCPU(LLVMTargetMachineRef T);
	/** Returns the feature string used creating this target machine. See		/** Returns the feature string used creating this target machine. See
	llvm::TargetMachine::getFeatureString. The result needs to be disposed wi th		llvm::TargetMachine::getFeatureString. The result needs to be disposed wi th
	LLVMDisposeMessage. */		LLVMDisposeMessage. */
	char *LLVMGetTargetMachineFeatureString(LLVMTargetMachineRef T);		char *LLVMGetTargetMachineFeatureString(LLVMTargetMachineRef T);
	/** Returns the llvm::DataLayout used for this llvm:TargetMachine. */		/** Returns the llvm::DataLayout used for this llvm:TargetMachine. */
	LLVMTargetDataRef LLVMGetTargetMachineData(LLVMTargetMachineRef T);		LLVMTargetDataRef LLVMGetTargetMachineData(LLVMTargetMachineRef T);
			/** Set the target machine's ASM verbosity. */
			void LLVMSetTargetMachineAsmVerbosity(LLVMTargetMachineRef T,
			LLVMBool VerboseAsm);
	/** Emits an asm or object file for the given module to the filename. This		/** Emits an asm or object file for the given module to the filename. This
	wraps several c++ only classes (among them a file stream). Returns any		wraps several c++ only classes (among them a file stream). Returns any
	error in ErrorMessage. Use LLVMDisposeMessage to dispose the message. */		error in ErrorMessage. Use LLVMDisposeMessage to dispose the message. */
	LLVMBool LLVMTargetMachineEmitToFile(LLVMTargetMachineRef T, LLVMModuleRef M,		LLVMBool LLVMTargetMachineEmitToFile(LLVMTargetMachineRef T, LLVMModuleRef M,
	char *Filename, LLVMCodeGenFileType codegen, char **ErrorMessage);		char *Filename, LLVMCodeGenFileType codegen, char **ErrorMessage);
	/** Compile the LLVM IR stored in \p M and store the result in \p OutMemBuf . */		/** Compile the LLVM IR stored in \p M and store the result in \p OutMemBuf . */
	LLVMBool LLVMTargetMachineEmitToMemoryBuffer(LLVMTargetMachineRef T, LLVMMo duleRef M,		LLVMBool LLVMTargetMachineEmitToMemoryBuffer(LLVMTargetMachineRef T, LLVMMo duleRef M,
	LLVMCodeGenFileType codegen, char** ErrorMessage, LLVMMemoryBufferRef *Ou tMemBuf);		LLVMCodeGenFileType codegen, char** ErrorMessage, LLVMMemoryBufferRef *Ou tMemBuf);
			/*===-- Triple ------------------------------------------------------------
			===*/
			/** Get a triple for the host machine as a string. The result needs to be
			disposed with LLVMDisposeMessage. */
			char* LLVMGetDefaultTargetTriple(void);
	#ifdef __cplusplus		#ifdef __cplusplus
	}		}
	#endif		#endif
	#endif		#endif
End of changes. 5 change blocks.
	5 lines changed or deleted		26 lines changed or added

	TargetOpcodes.h		TargetOpcodes.h
	skipping to change at line 72		skipping to change at line 72
	/// used between instruction selection and MachineInstr creation, befor e		/// used between instruction selection and MachineInstr creation, befor e
	/// virtual registers have been created for all the instructions, and i t's		/// virtual registers have been created for all the instructions, and i t's
	/// only needed in cases where the register classes implied by the		/// only needed in cases where the register classes implied by the
	/// instructions are insufficient. It is emitted as a COPY MachineInstr .		/// instructions are insufficient. It is emitted as a COPY MachineInstr .
	COPY_TO_REGCLASS = 10,		COPY_TO_REGCLASS = 10,
	/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic		/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
	DBG_VALUE = 11,		DBG_VALUE = 11,
	/// REG_SEQUENCE - This variadic instruction is used to form a register that		/// REG_SEQUENCE - This variadic instruction is used to form a register that
	/// represent a consecutive sequence of sub-registers. It's used as reg		/// represents a consecutive sequence of sub-registers. It's used as a
	ister		/// register coalescing / allocation aid and must be eliminated before
	/// coalescing / allocation aid and must be eliminated before code emis		code
	sion.		/// emission.
	// In SDNode form, the first operand encodes the register class created by		// In SDNode form, the first operand encodes the register class created by
	// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg i ndex		// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg i ndex
	// pair. Once it has been lowered to a MachineInstr, the regclass oper and		// pair. Once it has been lowered to a MachineInstr, the regclass oper and
	// is no longer present.		// is no longer present.
	/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5		/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
	/// After register coalescing references of v1024 should be replace wit h		/// After register coalescing references of v1024 should be replace wit h
	/// v1027:3, v1025 with v1027:4, etc.		/// v1027:3, v1025 with v1027:4, etc.
	REG_SEQUENCE = 12,		REG_SEQUENCE = 12,
	/// COPY - Target-independent register copy. This instruction can also be		/// COPY - Target-independent register copy. This instruction can also be
	/// used to copy between subregisters of virtual registers.		/// used to copy between subregisters of virtual registers.
	COPY = 13,		COPY = 13,
	/// BUNDLE - This instruction represents an instruction bundle. Instruc tions		/// BUNDLE - This instruction represents an instruction bundle. Instruc tions
	/// which immediately follow a BUNDLE instruction which are marked with		/// which immediately follow a BUNDLE instruction which are marked with
	/// 'InsideBundle' flag are inside the bundle.		/// 'InsideBundle' flag are inside the bundle.
	BUNDLE = 14,		BUNDLE = 14,
	/// Lifetime markers.		/// Lifetime markers.
	LIFETIME_START = 15,		LIFETIME_START = 15,
	LIFETIME_END = 16		LIFETIME_END = 16,
			/// A Stackmap instruction captures the location of live variables at i
			ts
			/// position in the instruction stream. It is followed by a shadow of b
			ytes
			/// that must lie within the function and not contain another stackmap.
			STACKMAP = 17,
			/// Patchable call instruction - this instruction represents a call to
			a
			/// constant address, followed by a series of NOPs. It is intended to
			/// support optimizations for dynamic languages (such as javascript) th
			at
			/// rewrite calls to runtimes with more efficient code sequences.
			/// This also implies a stack map.
			PATCHPOINT = 18
	};		};
	} // end namespace TargetOpcode		} // end namespace TargetOpcode
	} // end namespace llvm		} // end namespace llvm
	#endif		#endif
End of changes. 2 change blocks.
	5 lines changed or deleted		21 lines changed or added

	TargetOptions.h		TargetOptions.h
	skipping to change at line 45		skipping to change at line 45
	Fast, // Enable fusion of FP ops wherever it's profitable.		Fast, // Enable fusion of FP ops wherever it's profitable.
	Standard, // Only allow fusion of 'blessed' ops (currently just fmula dd).		Standard, // Only allow fusion of 'blessed' ops (currently just fmula dd).
	Strict // Never fuse FP-ops.		Strict // Never fuse FP-ops.
	};		};
	}		}
	class TargetOptions {		class TargetOptions {
	public:		public:
	TargetOptions()		TargetOptions()
	: PrintMachineCode(false), NoFramePointerElim(false),		: PrintMachineCode(false), NoFramePointerElim(false),
	NoFramePointerElimNonLeaf(false), LessPreciseFPMADOption(false),		LessPreciseFPMADOption(false),
	UnsafeFPMath(false), NoInfsFPMath(false),		UnsafeFPMath(false), NoInfsFPMath(false),
	NoNaNsFPMath(false), HonorSignDependentRoundingFPMathOption(false ),		NoNaNsFPMath(false), HonorSignDependentRoundingFPMathOption(false ),
	UseSoftFloat(false), NoZerosInBSS(false), JITExceptionHandling(fa lse),		UseSoftFloat(false), NoZerosInBSS(false),
	JITEmitDebugInfo(false), JITEmitDebugInfoToDisk(false),		JITEmitDebugInfo(false), JITEmitDebugInfoToDisk(false),
	GuaranteedTailCallOpt(false), DisableTailCalls(false),		GuaranteedTailCallOpt(false), DisableTailCalls(false),
	StackAlignmentOverride(0), RealignStack(true), SSPBufferSize(0),		StackAlignmentOverride(0),
	EnableFastISel(false), PositionIndependentExecutable(false),		EnableFastISel(false), PositionIndependentExecutable(false),
	EnableSegmentedStacks(false), UseInitArray(false), TrapFuncName(" "),		EnableSegmentedStacks(false), UseInitArray(false), TrapFuncName(" "),
	FloatABIType(FloatABI::Default), AllowFPOpFusion(FPOpFusion::Stan dard)		FloatABIType(FloatABI::Default), AllowFPOpFusion(FPOpFusion::Stan dard)
	{}		{}
	/// PrintMachineCode - This flag is enabled when the -print-machineinst rs		/// PrintMachineCode - This flag is enabled when the -print-machineinst rs
	/// option is specified on the command line, and should enable debuggin g		/// option is specified on the command line, and should enable debuggin g
	/// output from the code generator.		/// output from the code generator.
	unsigned PrintMachineCode : 1;		unsigned PrintMachineCode : 1;
	/// NoFramePointerElim - This flag is enabled when the -disable-fp-elim is		/// NoFramePointerElim - This flag is enabled when the -disable-fp-elim is
	/// specified on the command line. If the target supports the frame po inter		/// specified on the command line. If the target supports the frame po inter
	/// elimination optimization, this option should disable it.		/// elimination optimization, this option should disable it.
	unsigned NoFramePointerElim : 1;		unsigned NoFramePointerElim : 1;
	/// NoFramePointerElimNonLeaf - This flag is enabled when the
	/// -disable-non-leaf-fp-elim is specified on the command line. If the
	/// target supports the frame pointer elimination optimization, this op
	tion
	/// should disable it for non-leaf functions.
	unsigned NoFramePointerElimNonLeaf : 1;
	/// DisableFramePointerElim - This returns true if frame pointer elimin ation		/// DisableFramePointerElim - This returns true if frame pointer elimin ation
	/// optimization should be disabled for the given machine function.		/// optimization should be disabled for the given machine function.
	bool DisableFramePointerElim(const MachineFunction &MF) const;		bool DisableFramePointerElim(const MachineFunction &MF) const;
	/// LessPreciseFPMAD - This flag is enabled when the		/// LessPreciseFPMAD - This flag is enabled when the
	/// -enable-fp-mad is specified on the command line. When this flag is off		/// -enable-fp-mad is specified on the command line. When this flag is off
	/// (the default), the code generator is not allowed to generate mad		/// (the default), the code generator is not allowed to generate mad
	/// (multiply add) if the result is "less precise" than doing those		/// (multiply add) if the result is "less precise" than doing those
	/// operations individually.		/// operations individually.
	unsigned LessPreciseFPMADOption : 1;		unsigned LessPreciseFPMADOption : 1;
	skipping to change at line 126		skipping to change at line 120
	/// specified on the command line. When this flag is on, the code gene rator		/// specified on the command line. When this flag is on, the code gene rator
	/// will generate libcalls to the software floating point library inste ad of		/// will generate libcalls to the software floating point library inste ad of
	/// target FP instructions.		/// target FP instructions.
	unsigned UseSoftFloat : 1;		unsigned UseSoftFloat : 1;
	/// NoZerosInBSS - By default some codegens place zero-initialized data to		/// NoZerosInBSS - By default some codegens place zero-initialized data to
	/// .bss section. This flag disables such behaviour (necessary, e.g. fo r		/// .bss section. This flag disables such behaviour (necessary, e.g. fo r
	/// crt*.o compiling).		/// crt*.o compiling).
	unsigned NoZerosInBSS : 1;		unsigned NoZerosInBSS : 1;
	/// JITExceptionHandling - This flag indicates that the JIT should emit
	/// exception handling information.
	unsigned JITExceptionHandling : 1;
	/// JITEmitDebugInfo - This flag indicates that the JIT should try to e mit		/// JITEmitDebugInfo - This flag indicates that the JIT should try to e mit
	/// debug information and notify a debugger about it.		/// debug information and notify a debugger about it.
	unsigned JITEmitDebugInfo : 1;		unsigned JITEmitDebugInfo : 1;
	/// JITEmitDebugInfoToDisk - This flag indicates that the JIT should wr ite		/// JITEmitDebugInfoToDisk - This flag indicates that the JIT should wr ite
	/// the object files generated by the JITEmitDebugInfo flag to disk. T his		/// the object files generated by the JITEmitDebugInfo flag to disk. T his
	/// flag is hidden and is only for debugging the debug info.		/// flag is hidden and is only for debugging the debug info.
	unsigned JITEmitDebugInfoToDisk : 1;		unsigned JITEmitDebugInfoToDisk : 1;
	/// GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is		/// GuaranteedTailCallOpt - This flag is enabled when -tailcallopt is
	skipping to change at line 154		skipping to change at line 144
	/// as their parent function, etc.), using an alternate ABI if necessar y.		/// as their parent function, etc.), using an alternate ABI if necessar y.
	unsigned GuaranteedTailCallOpt : 1;		unsigned GuaranteedTailCallOpt : 1;
	/// DisableTailCalls - This flag controls whether we will use tail call s.		/// DisableTailCalls - This flag controls whether we will use tail call s.
	/// Disabling them may be useful to maintain a correct call stack.		/// Disabling them may be useful to maintain a correct call stack.
	unsigned DisableTailCalls : 1;		unsigned DisableTailCalls : 1;
	/// StackAlignmentOverride - Override default stack alignment for targe t.		/// StackAlignmentOverride - Override default stack alignment for targe t.
	unsigned StackAlignmentOverride;		unsigned StackAlignmentOverride;
	/// RealignStack - This flag indicates whether the stack should be
	/// automatically realigned, if needed.
	unsigned RealignStack : 1;
	/// SSPBufferSize - The minimum size of buffers that will receive stack
	/// smashing protection when -fstack-protection is used.
	unsigned SSPBufferSize;
	/// EnableFastISel - This flag enables fast-path instruction selection		/// EnableFastISel - This flag enables fast-path instruction selection
	/// which trades away generated code quality in favor of reducing		/// which trades away generated code quality in favor of reducing
	/// compile time.		/// compile time.
	unsigned EnableFastISel : 1;		unsigned EnableFastISel : 1;
	/// PositionIndependentExecutable - This flag indicates whether the cod e		/// PositionIndependentExecutable - This flag indicates whether the cod e
	/// will eventually be linked into a single executable, despite the PIC		/// will eventually be linked into a single executable, despite the PIC
	/// relocation model being in use. It's value is undefined (and irrelev ant)		/// relocation model being in use. It's value is undefined (and irrelev ant)
	/// if the relocation model is anything other than PIC.		/// if the relocation model is anything other than PIC.
	unsigned PositionIndependentExecutable : 1;		unsigned PositionIndependentExecutable : 1;
	skipping to change at line 210		skipping to change at line 192
	/// only blessed op is the fmuladd intrinsic. In the future more blesse d ops		/// only blessed op is the fmuladd intrinsic. In the future more blesse d ops
	/// may be added.		/// may be added.
	/// Strict mode - allow fusion only if/when it can be proven that the e xcess		/// Strict mode - allow fusion only if/when it can be proven that the e xcess
	/// precision won't effect the result.		/// precision won't effect the result.
	///		///
	/// Note: This option only controls formation of fused ops by the		/// Note: This option only controls formation of fused ops by the
	/// optimizers. Fused operations that are explicitly specified (e.g. F MA		/// optimizers. Fused operations that are explicitly specified (e.g. F MA
	/// via the llvm.fma.* intrinsic) will always be honored, regardless of		/// via the llvm.fma.* intrinsic) will always be honored, regardless of
	/// the value of this option.		/// the value of this option.
	FPOpFusion::FPOpFusionMode AllowFPOpFusion;		FPOpFusion::FPOpFusionMode AllowFPOpFusion;
	bool operator==(const TargetOptions &);
	};		};
			// Comparison operators:
			inline bool operator==(const TargetOptions &LHS,
			const TargetOptions &RHS) {
			#define ARE_EQUAL(X) LHS.X == RHS.X
			return
			ARE_EQUAL(UnsafeFPMath) &&
			ARE_EQUAL(NoInfsFPMath) &&
			ARE_EQUAL(NoNaNsFPMath) &&
			ARE_EQUAL(HonorSignDependentRoundingFPMathOption) &&
			ARE_EQUAL(UseSoftFloat) &&
			ARE_EQUAL(NoZerosInBSS) &&
			ARE_EQUAL(JITEmitDebugInfo) &&
			ARE_EQUAL(JITEmitDebugInfoToDisk) &&
			ARE_EQUAL(GuaranteedTailCallOpt) &&
			ARE_EQUAL(DisableTailCalls) &&
			ARE_EQUAL(StackAlignmentOverride) &&
			ARE_EQUAL(EnableFastISel) &&
			ARE_EQUAL(PositionIndependentExecutable) &&
			ARE_EQUAL(EnableSegmentedStacks) &&
			ARE_EQUAL(UseInitArray) &&
			ARE_EQUAL(TrapFuncName) &&
			ARE_EQUAL(FloatABIType) &&
			ARE_EQUAL(AllowFPOpFusion);
			#undef ARE_EQUAL
			}
			inline bool operator!=(const TargetOptions &LHS,
			const TargetOptions &RHS) {
			return !(LHS == RHS);
			}
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 8 change blocks.
	24 lines changed or deleted		36 lines changed or added

	TargetRegisterInfo.h		TargetRegisterInfo.h
	skipping to change at line 229		skipping to change at line 229
	class TargetRegisterInfo : public MCRegisterInfo {		class TargetRegisterInfo : public MCRegisterInfo {
	public:		public:
	typedef const TargetRegisterClass * const * regclass_iterator;		typedef const TargetRegisterClass * const * regclass_iterator;
	private:		private:
	const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codeg en		const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codeg en
	const char *const *SubRegIndexNames; // Names of subreg indexes.		const char *const *SubRegIndexNames; // Names of subreg indexes.
	// Pointer to array of lane masks, one per sub-reg index.		// Pointer to array of lane masks, one per sub-reg index.
	const unsigned *SubRegIndexLaneMasks;		const unsigned *SubRegIndexLaneMasks;
	regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses		regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
			unsigned CoveringLanes;
	protected:		protected:
	TargetRegisterInfo(const TargetRegisterInfoDesc *ID,		TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
	regclass_iterator RegClassBegin,		regclass_iterator RegClassBegin,
	regclass_iterator RegClassEnd,		regclass_iterator RegClassEnd,
	const char *const *SRINames,		const char *const *SRINames,
	const unsigned *SRILaneMasks);		const unsigned *SRILaneMasks,
			unsigned CoveringLanes);
	virtual ~TargetRegisterInfo();		virtual ~TargetRegisterInfo();
	public:		public:
	// Register numbers can represent physical registers, virtual registers, and		// Register numbers can represent physical registers, virtual registers, and
	// sometimes stack slots. The unsigned values are divided into these rang es:		// sometimes stack slots. The unsigned values are divided into these rang es:
	//		//
	// 0 Not a register, can be used as a sentinel.		// 0 Not a register, can be used as a sentinel.
	// [1;2^30) Physical registers assigned by TableGen.		// [1;2^30) Physical registers assigned by TableGen.
	// [2^30;2^31) Stack slots. (Rarely used.)		// [2^30;2^31) Stack slots. (Rarely used.)
	// [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.		// [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
	skipping to change at line 365		skipping to change at line 367
	///		///
	/// The converse is not necessarily true. If two lane masks have a common		/// The converse is not necessarily true. If two lane masks have a common
	/// bit, the corresponding sub-registers may not overlap, but it can be		/// bit, the corresponding sub-registers may not overlap, but it can be
	/// assumed that they usually will.		/// assumed that they usually will.
	unsigned getSubRegIndexLaneMask(unsigned SubIdx) const {		unsigned getSubRegIndexLaneMask(unsigned SubIdx) const {
	// SubIdx == 0 is allowed, it has the lane mask ~0u.		// SubIdx == 0 is allowed, it has the lane mask ~0u.
	assert(SubIdx < getNumSubRegIndices() && "This is not a subregister ind ex");		assert(SubIdx < getNumSubRegIndices() && "This is not a subregister ind ex");
	return SubRegIndexLaneMasks[SubIdx];		return SubRegIndexLaneMasks[SubIdx];
	}		}
			/// The lane masks returned by getSubRegIndexLaneMask() above can only be
			/// used to determine if sub-registers overlap - they can't be used to
			/// determine if a set of sub-registers completely cover another
			/// sub-register.
			///
			/// The X86 general purpose registers have two lanes corresponding to the
			/// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit
			have
			/// lane masks '3', but the sub_16bit sub-register doesn't fully cover th
			e
			/// sub_32bit sub-register.
			///
			/// On the other hand, the ARM NEON lanes fully cover their registers: Th
			e
			/// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 la
			nes.
			/// This is related to the CoveredBySubRegs property on register definiti
			ons.
			///
			/// This function returns a bit mask of lanes that completely cover their
			/// sub-registers. More precisely, given:
			///
			/// Covering = getCoveringLanes();
			/// MaskA = getSubRegIndexLaneMask(SubA);
			/// MaskB = getSubRegIndexLaneMask(SubB);
			///
			/// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covere
			d by
			/// SubB.
			unsigned getCoveringLanes() const { return CoveringLanes; }
	/// regsOverlap - Returns true if the two registers are equal or alias ea ch		/// regsOverlap - Returns true if the two registers are equal or alias ea ch
	/// other. The registers may be virtual register.		/// other. The registers may be virtual register.
	bool regsOverlap(unsigned regA, unsigned regB) const {		bool regsOverlap(unsigned regA, unsigned regB) const {
	if (regA == regB) return true;		if (regA == regB) return true;
	if (isVirtualRegister(regA) || isVirtualRegister(regB))		if (isVirtualRegister(regA) || isVirtualRegister(regB))
	return false;		return false;
	// Regunits are numerically ordered. Find a common unit.		// Regunits are numerically ordered. Find a common unit.
	MCRegUnitIterator RUA(regA, this);		MCRegUnitIterator RUA(regA, this);
	MCRegUnitIterator RUB(regB, this);		MCRegUnitIterator RUB(regB, this);
	skipping to change at line 875		skipping to change at line 902
	/// PrintRegUnit - Helper class for printing register units on a raw_ostrea m.		/// PrintRegUnit - Helper class for printing register units on a raw_ostrea m.
	///		///
	/// Register units are named after their root registers:		/// Register units are named after their root registers:
	///		///
	/// AL - Single root.		/// AL - Single root.
	/// FP0~ST7 - Dual roots.		/// FP0~ST7 - Dual roots.
	///		///
	/// Usage: OS << PrintRegUnit(Unit, TRI) << '\n';		/// Usage: OS << PrintRegUnit(Unit, TRI) << '\n';
	///		///
	class PrintRegUnit {		class PrintRegUnit {
			protected:
	const TargetRegisterInfo *TRI;		const TargetRegisterInfo *TRI;
	unsigned Unit;		unsigned Unit;
	public:		public:
	PrintRegUnit(unsigned unit, const TargetRegisterInfo *tri)		PrintRegUnit(unsigned unit, const TargetRegisterInfo *tri)
	: TRI(tri), Unit(unit) {}		: TRI(tri), Unit(unit) {}
	void print(raw_ostream&) const;		void print(raw_ostream&) const;
	};		};
	static inline raw_ostream &operator<<(raw_ostream &OS, const PrintRegUnit & PR) {		static inline raw_ostream &operator<<(raw_ostream &OS, const PrintRegUnit & PR) {
	PR.print(OS);		PR.print(OS);
	return OS;		return OS;
	}		}
			/// PrintVRegOrUnit - It is often convenient to track virtual registers and
			/// physical register units in the same list.
			class PrintVRegOrUnit : protected PrintRegUnit {
			public:
			PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *tri)
			: PrintRegUnit(VRegOrUnit, tri) {}
			void print(raw_ostream&) const;
			};
			static inline raw_ostream &operator<<(raw_ostream &OS,
			const PrintVRegOrUnit &PR) {
			PR.print(OS);
			return OS;
			}
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 5 change blocks.
	1 lines changed or deleted		50 lines changed or added

	TargetRegistry.h		TargetRegistry.h
	skipping to change at line 24		skipping to change at line 24
	// Target specific class implementations should register themselves using t he		// Target specific class implementations should register themselves using t he
	// appropriate TargetRegistry interfaces.		// appropriate TargetRegistry interfaces.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_SUPPORT_TARGETREGISTRY_H		#ifndef LLVM_SUPPORT_TARGETREGISTRY_H
	#define LLVM_SUPPORT_TARGETREGISTRY_H		#define LLVM_SUPPORT_TARGETREGISTRY_H
	#include "llvm/ADT/Triple.h"		#include "llvm/ADT/Triple.h"
	#include "llvm/Support/CodeGen.h"		#include "llvm/Support/CodeGen.h"
			#include "llvm-c/Disassembler.h"
	#include <cassert>		#include <cassert>
	#include <string>		#include <string>
	namespace llvm {		namespace llvm {
	class AsmPrinter;		class AsmPrinter;
	class Module;		class Module;
	class MCAssembler;		class MCAssembler;
	class MCAsmBackend;		class MCAsmBackend;
	class MCAsmInfo;		class MCAsmInfo;
	class MCAsmParser;		class MCAsmParser;
	class MCCodeEmitter;		class MCCodeEmitter;
	class MCCodeGenInfo;		class MCCodeGenInfo;
	class MCContext;		class MCContext;
	class MCDisassembler;		class MCDisassembler;
	class MCInstrAnalysis;		class MCInstrAnalysis;
	class MCInstPrinter;		class MCInstPrinter;
	class MCInstrInfo;		class MCInstrInfo;
	class MCRegisterInfo;		class MCRegisterInfo;
	class MCStreamer;		class MCStreamer;
	class MCSubtargetInfo;		class MCSubtargetInfo;
			class MCSymbolizer;
			class MCRelocationInfo;
	class MCTargetAsmParser;		class MCTargetAsmParser;
	class TargetMachine;		class TargetMachine;
			class MCTargetStreamer;
	class TargetOptions;		class TargetOptions;
	class raw_ostream;		class raw_ostream;
	class formatted_raw_ostream;		class formatted_raw_ostream;
	MCStreamer *createAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,		MCStreamer *createAsmStreamer(MCContext &Ctx,
	bool isVerboseAsm,		MCTargetStreamer *TargetStreamer,
			formatted_raw_ostream &OS, bool isVerboseAs
			m,
	bool useLoc, bool useCFI,		bool useLoc, bool useCFI,
	bool useDwarfDirectory,		bool useDwarfDirectory,
	MCInstPrinter *InstPrint,		MCInstPrinter *InstPrint, MCCodeEmitter *CE
	MCCodeEmitter *CE,		,
	MCAsmBackend *TAB,		MCAsmBackend *TAB, bool ShowInst);
	bool ShowInst);
			MCRelocationInfo *createMCRelocationInfo(StringRef TT, MCContext &Ctx);
			MCSymbolizer *createMCSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpIn
			fo,
			LLVMSymbolLookupCallback SymbolLookUp,
			void *DisInfo,
			MCContext *Ctx,
			MCRelocationInfo *RelInfo);
	/// Target - Wrapper for Target specific information.		/// Target - Wrapper for Target specific information.
	///		///
	/// For registration purposes, this is a POD type so that targets can be		/// For registration purposes, this is a POD type so that targets can be
	/// registered without the use of static constructors.		/// registered without the use of static constructors.
	///		///
	/// Targets should implement a single global instance of this class (whic h		/// Targets should implement a single global instance of this class (whic h
	/// will be zero initialized), and pass that instance to the TargetRegist ry as		/// will be zero initialized), and pass that instance to the TargetRegist ry as
	/// part of their initialization.		/// part of their initialization.
	class Target {		class Target {
	public:		public:
	friend struct TargetRegistry;		friend struct TargetRegistry;
	typedef unsigned (*TripleMatchQualityFnTy)(const std::string &TT);		typedef unsigned (*TripleMatchQualityFnTy)(const std::string &TT);
	typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const Target &T,		typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const MCRegisterInfo &MRI,
	StringRef TT);		StringRef TT);
	typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT,		typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(StringRef TT,
	Reloc::Model RM,		Reloc::Model RM,
	CodeModel::Model CM,		CodeModel::Model CM,
	CodeGenOpt::Level OL);		CodeGenOpt::Level OL);
	typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);		typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
	typedef MCInstrAnalysis *(*MCInstrAnalysisCtorFnTy)(const MCInstrInfo*I nfo);		typedef MCInstrAnalysis *(*MCInstrAnalysisCtorFnTy)(const MCInstrInfo*I nfo);
	typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT);		typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(StringRef TT);
	typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT,		typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT,
	StringRef CPU,		StringRef CPU,
	skipping to change at line 96		skipping to change at line 107
	StringRef TT,		StringRef TT,
	StringRef CPU,		StringRef CPU,
	StringRef Features,		StringRef Features,
	const TargetOptions &Opti ons,		const TargetOptions &Opti ons,
	Reloc::Model RM,		Reloc::Model RM,
	CodeModel::Model CM,		CodeModel::Model CM,
	CodeGenOpt::Level OL);		CodeGenOpt::Level OL);
	typedef AsmPrinter *(*AsmPrinterCtorTy)(TargetMachine &TM,		typedef AsmPrinter *(*AsmPrinterCtorTy)(TargetMachine &TM,
	MCStreamer &Streamer);		MCStreamer &Streamer);
	typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T,		typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T,
			const MCRegisterInfo &MRI,
	StringRef TT,		StringRef TT,
	StringRef CPU);		StringRef CPU);
	typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(MCSubtargetInfo &STI,		typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(MCSubtargetInfo &STI,
	MCAsmParser &P);		MCAsmParser &P,
			const MCInstrInfo &MII)
			;
	typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T,		typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T,
	const MCSubtargetInfo & STI);		const MCSubtargetInfo & STI);
	typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T,		typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T,
	unsigned SyntaxVariant,		unsigned SyntaxVariant,
	const MCAsmInfo &MAI,		const MCAsmInfo &MAI,
	const MCInstrInfo &MII,		const MCInstrInfo &MII,
	const MCRegisterInfo &MRI ,		const MCRegisterInfo &MRI ,
	const MCSubtargetInfo &ST I);		const MCSubtargetInfo &ST I);
	typedef MCCodeEmitter *(*MCCodeEmitterCtorTy)(const MCInstrInfo &II,		typedef MCCodeEmitter *(*MCCodeEmitterCtorTy)(const MCInstrInfo &II,
	const MCRegisterInfo &MRI ,		const MCRegisterInfo &MRI ,
	skipping to change at line 130		skipping to change at line 143
	typedef MCStreamer *(*AsmStreamerCtorTy)(MCContext &Ctx,		typedef MCStreamer *(*AsmStreamerCtorTy)(MCContext &Ctx,
	formatted_raw_ostream &OS,		formatted_raw_ostream &OS,
	bool isVerboseAsm,		bool isVerboseAsm,
	bool useLoc,		bool useLoc,
	bool useCFI,		bool useCFI,
	bool useDwarfDirectory,		bool useDwarfDirectory,
	MCInstPrinter *InstPrint,		MCInstPrinter *InstPrint,
	MCCodeEmitter *CE,		MCCodeEmitter *CE,
	MCAsmBackend *TAB,		MCAsmBackend *TAB,
	bool ShowInst);		bool ShowInst);
			typedef MCRelocationInfo *(*MCRelocationInfoCtorTy)(StringRef TT,
			MCContext &Ctx);
			typedef MCSymbolizer *(*MCSymbolizerCtorTy)(StringRef TT,
			LLVMOpInfoCallback GetOpInfo,
			LLVMSymbolLookupCallback SymbolLookUp,
			void *DisInfo,
			MCContext *Ctx,
			MCRelocationInfo *RelInfo);
	private:		private:
	/// Next - The next registered target in the linked list, maintained by the		/// Next - The next registered target in the linked list, maintained by the
	/// TargetRegistry.		/// TargetRegistry.
	Target *Next;		Target *Next;
	/// TripleMatchQualityFn - The target function for rating the match qua lity		/// TripleMatchQualityFn - The target function for rating the match qua lity
	/// of a triple.		/// of a triple.
	TripleMatchQualityFnTy TripleMatchQualityFn;		TripleMatchQualityFnTy TripleMatchQualityFn;
	skipping to change at line 209		skipping to change at line 230
	MCCodeEmitterCtorTy MCCodeEmitterCtorFn;		MCCodeEmitterCtorTy MCCodeEmitterCtorFn;
	/// MCObjectStreamerCtorFn - Construction function for this target's		/// MCObjectStreamerCtorFn - Construction function for this target's
	/// MCObjectStreamer, if registered.		/// MCObjectStreamer, if registered.
	MCObjectStreamerCtorTy MCObjectStreamerCtorFn;		MCObjectStreamerCtorTy MCObjectStreamerCtorFn;
	/// AsmStreamerCtorFn - Construction function for this target's		/// AsmStreamerCtorFn - Construction function for this target's
	/// AsmStreamer, if registered (default = llvm::createAsmStreamer).		/// AsmStreamer, if registered (default = llvm::createAsmStreamer).
	AsmStreamerCtorTy AsmStreamerCtorFn;		AsmStreamerCtorTy AsmStreamerCtorFn;
			/// MCRelocationInfoCtorFn - Construction function for this target's
			/// MCRelocationInfo, if registered (default = llvm::createMCRelocation
			Info)
			MCRelocationInfoCtorTy MCRelocationInfoCtorFn;
			/// MCSymbolizerCtorFn - Construction function for this target's
			/// MCSymbolizer, if registered (default = llvm::createMCSymbolizer)
			MCSymbolizerCtorTy MCSymbolizerCtorFn;
	public:		public:
	Target() : AsmStreamerCtorFn(llvm::createAsmStreamer) {}		Target()
			: AsmStreamerCtorFn(0), MCRelocationInfoCtorFn(0),
			MCSymbolizerCtorFn(0) {}
	/// @name Target Information		/// @name Target Information
	/// @{		/// @{
	// getNext - Return the next registered target.		// getNext - Return the next registered target.
	const Target *getNext() const { return Next; }		const Target *getNext() const { return Next; }
	/// getName - Get the target name.		/// getName - Get the target name.
	const char *getName() const { return Name; }		const char *getName() const { return Name; }
	skipping to change at line 237		skipping to change at line 268
	/// hasJIT - Check if this targets supports the just-in-time compilatio n.		/// hasJIT - Check if this targets supports the just-in-time compilatio n.
	bool hasJIT() const { return HasJIT; }		bool hasJIT() const { return HasJIT; }
	/// hasTargetMachine - Check if this target supports code generation.		/// hasTargetMachine - Check if this target supports code generation.
	bool hasTargetMachine() const { return TargetMachineCtorFn != 0; }		bool hasTargetMachine() const { return TargetMachineCtorFn != 0; }
	/// hasMCAsmBackend - Check if this target supports .o generation.		/// hasMCAsmBackend - Check if this target supports .o generation.
	bool hasMCAsmBackend() const { return MCAsmBackendCtorFn != 0; }		bool hasMCAsmBackend() const { return MCAsmBackendCtorFn != 0; }
	/// hasAsmParser - Check if this target supports .s parsing.
	bool hasMCAsmParser() const { return MCAsmParserCtorFn != 0; }
	/// hasAsmPrinter - Check if this target supports .s printing.
	bool hasAsmPrinter() const { return AsmPrinterCtorFn != 0; }
	/// hasMCDisassembler - Check if this target has a disassembler.
	bool hasMCDisassembler() const { return MCDisassemblerCtorFn != 0; }
	/// hasMCInstPrinter - Check if this target has an instruction printer.
	bool hasMCInstPrinter() const { return MCInstPrinterCtorFn != 0; }
	/// hasMCCodeEmitter - Check if this target supports instruction encodi
	ng.
	bool hasMCCodeEmitter() const { return MCCodeEmitterCtorFn != 0; }
	/// hasMCObjectStreamer - Check if this target supports streaming to fi
	les.
	bool hasMCObjectStreamer() const { return MCObjectStreamerCtorFn != 0;
	}
	/// hasAsmStreamer - Check if this target supports streaming to files.
	bool hasAsmStreamer() const { return AsmStreamerCtorFn != 0; }
	/// @}		/// @}
	/// @name Feature Constructors		/// @name Feature Constructors
	/// @{		/// @{
	/// createMCAsmInfo - Create a MCAsmInfo implementation for the specifi ed		/// createMCAsmInfo - Create a MCAsmInfo implementation for the specifi ed
	/// target triple.		/// target triple.
	///		///
	/// \param Triple This argument is used to determine the target machine		/// \param Triple This argument is used to determine the target machine
	/// feature set; it should always be provided. Generally this should be		/// feature set; it should always be provided. Generally this should be
	/// either the target triple from the module, or the target triple of t he		/// either the target triple from the module, or the target triple of t he
	/// host if that does not exist.		/// host if that does not exist.
	MCAsmInfo *createMCAsmInfo(StringRef Triple) const {		MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI,
			StringRef Triple) const {
	if (!MCAsmInfoCtorFn)		if (!MCAsmInfoCtorFn)
	return 0;		return 0;
	return MCAsmInfoCtorFn(*this, Triple);		return MCAsmInfoCtorFn(MRI, Triple);
	}		}
	/// createMCCodeGenInfo - Create a MCCodeGenInfo implementation.		/// createMCCodeGenInfo - Create a MCCodeGenInfo implementation.
	///		///
	MCCodeGenInfo *createMCCodeGenInfo(StringRef Triple, Reloc::Model RM,		MCCodeGenInfo *createMCCodeGenInfo(StringRef Triple, Reloc::Model RM,
	CodeModel::Model CM,		CodeModel::Model CM,
	CodeGenOpt::Level OL) const {		CodeGenOpt::Level OL) const {
	if (!MCCodeGenInfoCtorFn)		if (!MCCodeGenInfoCtorFn)
	return 0;		return 0;
	return MCCodeGenInfoCtorFn(Triple, RM, CM, OL);		return MCCodeGenInfoCtorFn(Triple, RM, CM, OL);
	skipping to change at line 346		skipping to change at line 357
	CodeGenOpt::Level OL = CodeGenOpt::Default) co nst {		CodeGenOpt::Level OL = CodeGenOpt::Default) co nst {
	if (!TargetMachineCtorFn)		if (!TargetMachineCtorFn)
	return 0;		return 0;
	return TargetMachineCtorFn(*this, Triple, CPU, Features, Options,		return TargetMachineCtorFn(*this, Triple, CPU, Features, Options,
	RM, CM, OL);		RM, CM, OL);
	}		}
	/// createMCAsmBackend - Create a target specific assembly parser.		/// createMCAsmBackend - Create a target specific assembly parser.
	///		///
	/// \param Triple The target triple string.		/// \param Triple The target triple string.
	MCAsmBackend *createMCAsmBackend(StringRef Triple, StringRef CPU) const		MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI,
	{		StringRef Triple, StringRef CPU) const
			{
	if (!MCAsmBackendCtorFn)		if (!MCAsmBackendCtorFn)
	return 0;		return 0;
	return MCAsmBackendCtorFn(*this, Triple, CPU);		return MCAsmBackendCtorFn(*this, MRI, Triple, CPU);
	}		}
	/// createMCAsmParser - Create a target specific assembly parser.		/// createMCAsmParser - Create a target specific assembly parser.
	///		///
	/// \param Parser The target independent parser implementation to use f or		/// \param Parser The target independent parser implementation to use f or
	/// parsing and lexing.		/// parsing and lexing.
	MCTargetAsmParser *createMCAsmParser(MCSubtargetInfo &STI,		MCTargetAsmParser *createMCAsmParser(MCSubtargetInfo &STI,
	MCAsmParser &Parser) const {		MCAsmParser &Parser,
			const MCInstrInfo &MII) const {
	if (!MCAsmParserCtorFn)		if (!MCAsmParserCtorFn)
	return 0;		return 0;
	return MCAsmParserCtorFn(STI, Parser);		return MCAsmParserCtorFn(STI, Parser, MII);
	}		}
	/// createAsmPrinter - Create a target specific assembly printer pass. This		/// createAsmPrinter - Create a target specific assembly printer pass. This
	/// takes ownership of the MCStreamer object.		/// takes ownership of the MCStreamer object.
	AsmPrinter *createAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) c onst{		AsmPrinter *createAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) c onst{
	if (!AsmPrinterCtorFn)		if (!AsmPrinterCtorFn)
	return 0;		return 0;
	return AsmPrinterCtorFn(TM, Streamer);		return AsmPrinterCtorFn(TM, Streamer);
	}		}
	skipping to change at line 429		skipping to change at line 442
	MCStreamer *createAsmStreamer(MCContext &Ctx,		MCStreamer *createAsmStreamer(MCContext &Ctx,
	formatted_raw_ostream &OS,		formatted_raw_ostream &OS,
	bool isVerboseAsm,		bool isVerboseAsm,
	bool useLoc,		bool useLoc,
	bool useCFI,		bool useCFI,
	bool useDwarfDirectory,		bool useDwarfDirectory,
	MCInstPrinter *InstPrint,		MCInstPrinter *InstPrint,
	MCCodeEmitter *CE,		MCCodeEmitter *CE,
	MCAsmBackend *TAB,		MCAsmBackend *TAB,
	bool ShowInst) const {		bool ShowInst) const {
	// AsmStreamerCtorFn is default to llvm::createAsmStreamer		if (AsmStreamerCtorFn)
	return AsmStreamerCtorFn(Ctx, OS, isVerboseAsm, useLoc, useCFI,		return AsmStreamerCtorFn(Ctx, OS, isVerboseAsm, useLoc, useCFI,
	useDwarfDirectory, InstPrint, CE, TAB, ShowI		useDwarfDirectory, InstPrint, CE, TAB,
	nst);		ShowInst);
			return llvm::createAsmStreamer(Ctx, 0, OS, isVerboseAsm, useLoc, useC
			FI,
			useDwarfDirectory, InstPrint, CE, TAB,
			ShowInst);
			}
			/// createMCRelocationInfo - Create a target specific MCRelocationInfo.
			///
			/// \param TT The target triple.
			/// \param Ctx The target context.
			MCRelocationInfo *
			createMCRelocationInfo(StringRef TT, MCContext &Ctx) const {
			MCRelocationInfoCtorTy Fn = MCRelocationInfoCtorFn
			? MCRelocationInfoCtorFn
			: llvm::createMCRelocationInfo;
			return Fn(TT, Ctx);
			}
			/// createMCSymbolizer - Create a target specific MCSymbolizer.
			///
			/// \param TT The target triple.
			/// \param GetOpInfo The function to get the symbolic information for o
			perands.
			/// \param SymbolLookUp The function to lookup a symbol name.
			/// \param DisInfo The pointer to the block of symbolic information for
			above call
			/// back.
			/// \param Ctx The target context.
			/// \param RelInfo The relocation information for this target. Takes ow
			nership.
			MCSymbolizer *
			createMCSymbolizer(StringRef TT, LLVMOpInfoCallback GetOpInfo,
			LLVMSymbolLookupCallback SymbolLookUp,
			void *DisInfo,
			MCContext *Ctx, MCRelocationInfo *RelInfo) const {
			MCSymbolizerCtorTy Fn =
			MCSymbolizerCtorFn ? MCSymbolizerCtorFn : llvm::createMCSymbolize
			r;
			return Fn(TT, GetOpInfo, SymbolLookUp, DisInfo, Ctx, RelInfo);
	}		}
	/// @}		/// @}
	};		};
	/// TargetRegistry - Generic interface to target specific features.		/// TargetRegistry - Generic interface to target specific features.
	struct TargetRegistry {		struct TargetRegistry {
	class iterator {		class iterator {
	const Target *Current;		const Target *Current;
	explicit iterator(Target *T) : Current(T) {}		explicit iterator(Target *T) : Current(T) {}
	skipping to change at line 552		skipping to change at line 600
	/// RegisterMCAsmInfo - Register a MCAsmInfo implementation for the		/// RegisterMCAsmInfo - Register a MCAsmInfo implementation for the
	/// given target.		/// given target.
	///		///
	/// Clients are responsible for ensuring that registration doesn't occu r		/// Clients are responsible for ensuring that registration doesn't occu r
	/// while another thread is attempting to access the registry. Typicall y		/// while another thread is attempting to access the registry. Typicall y
	/// this is done by initializing all targets at program startup.		/// this is done by initializing all targets at program startup.
	///		///
	/// @param T - The target being registered.		/// @param T - The target being registered.
	/// @param Fn - A function to construct a MCAsmInfo for the target.		/// @param Fn - A function to construct a MCAsmInfo for the target.
	static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn) {		static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn) {
	// Ignore duplicate registration.		T.MCAsmInfoCtorFn = Fn;
	if (!T.MCAsmInfoCtorFn)
	T.MCAsmInfoCtorFn = Fn;
	}		}
	/// RegisterMCCodeGenInfo - Register a MCCodeGenInfo implementation for the		/// RegisterMCCodeGenInfo - Register a MCCodeGenInfo implementation for the
	/// given target.		/// given target.
	///		///
	/// Clients are responsible for ensuring that registration doesn't occu r		/// Clients are responsible for ensuring that registration doesn't occu r
	/// while another thread is attempting to access the registry. Typicall y		/// while another thread is attempting to access the registry. Typicall y
	/// this is done by initializing all targets at program startup.		/// this is done by initializing all targets at program startup.
	///		///
	/// @param T - The target being registered.		/// @param T - The target being registered.
	/// @param Fn - A function to construct a MCCodeGenInfo for the target.		/// @param Fn - A function to construct a MCCodeGenInfo for the target.
	static void RegisterMCCodeGenInfo(Target &T,		static void RegisterMCCodeGenInfo(Target &T,
	Target::MCCodeGenInfoCtorFnTy Fn) {		Target::MCCodeGenInfoCtorFnTy Fn) {
	// Ignore duplicate registration.		T.MCCodeGenInfoCtorFn = Fn;
	if (!T.MCCodeGenInfoCtorFn)
	T.MCCodeGenInfoCtorFn = Fn;
	}		}
	/// RegisterMCInstrInfo - Register a MCInstrInfo implementation for the		/// RegisterMCInstrInfo - Register a MCInstrInfo implementation for the
	/// given target.		/// given target.
	///		///
	/// Clients are responsible for ensuring that registration doesn't occu r		/// Clients are responsible for ensuring that registration doesn't occu r
	/// while another thread is attempting to access the registry. Typicall y		/// while another thread is attempting to access the registry. Typicall y
	/// this is done by initializing all targets at program startup.		/// this is done by initializing all targets at program startup.
	///		///
	/// @param T - The target being registered.		/// @param T - The target being registered.
	/// @param Fn - A function to construct a MCInstrInfo for the target.		/// @param Fn - A function to construct a MCInstrInfo for the target.
	static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn) {		static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn) {
	// Ignore duplicate registration.		T.MCInstrInfoCtorFn = Fn;
	if (!T.MCInstrInfoCtorFn)
	T.MCInstrInfoCtorFn = Fn;
	}		}
	/// RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for		/// RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for
	/// the given target.		/// the given target.
	static void RegisterMCInstrAnalysis(Target &T,		static void RegisterMCInstrAnalysis(Target &T,
	Target::MCInstrAnalysisCtorFnTy Fn) {		Target::MCInstrAnalysisCtorFnTy Fn) {
	// Ignore duplicate registration.		T.MCInstrAnalysisCtorFn = Fn;
	if (!T.MCInstrAnalysisCtorFn)
	T.MCInstrAnalysisCtorFn = Fn;
	}		}
	/// RegisterMCRegInfo - Register a MCRegisterInfo implementation for th e		/// RegisterMCRegInfo - Register a MCRegisterInfo implementation for th e
	/// given target.		/// given target.
	///		///
	/// Clients are responsible for ensuring that registration doesn't occu r		/// Clients are responsible for ensuring that registration doesn't occu r
	/// while another thread is attempting to access the registry. Typicall y		/// while another thread is attempting to access the registry. Typicall y
	/// this is done by initializing all targets at program startup.		/// this is done by initializing all targets at program startup.
	///		///
	/// @param T - The target being registered.		/// @param T - The target being registered.
	/// @param Fn - A function to construct a MCRegisterInfo for the target .		/// @param Fn - A function to construct a MCRegisterInfo for the target .
	static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn) {		static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn) {
	// Ignore duplicate registration.		T.MCRegInfoCtorFn = Fn;
	if (!T.MCRegInfoCtorFn)
	T.MCRegInfoCtorFn = Fn;
	}		}
	/// RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for		/// RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for
	/// the given target.		/// the given target.
	///		///
	/// Clients are responsible for ensuring that registration doesn't occu r		/// Clients are responsible for ensuring that registration doesn't occu r
	/// while another thread is attempting to access the registry. Typicall y		/// while another thread is attempting to access the registry. Typicall y
	/// this is done by initializing all targets at program startup.		/// this is done by initializing all targets at program startup.
	///		///
	/// @param T - The target being registered.		/// @param T - The target being registered.
	/// @param Fn - A function to construct a MCSubtargetInfo for the targe t.		/// @param Fn - A function to construct a MCSubtargetInfo for the targe t.
	static void RegisterMCSubtargetInfo(Target &T,		static void RegisterMCSubtargetInfo(Target &T,
	Target::MCSubtargetInfoCtorFnTy Fn) {		Target::MCSubtargetInfoCtorFnTy Fn) {
	// Ignore duplicate registration.		T.MCSubtargetInfoCtorFn = Fn;
	if (!T.MCSubtargetInfoCtorFn)
	T.MCSubtargetInfoCtorFn = Fn;
	}		}
	/// RegisterTargetMachine - Register a TargetMachine implementation for the		/// RegisterTargetMachine - Register a TargetMachine implementation for the
	/// given target.		/// given target.
	///		///
	/// Clients are responsible for ensuring that registration doesn't occu r		/// Clients are responsible for ensuring that registration doesn't occu r
	/// while another thread is attempting to access the registry. Typicall y		/// while another thread is attempting to access the registry. Typicall y
	/// this is done by initializing all targets at program startup.		/// this is done by initializing all targets at program startup.
	///		///
	/// @param T - The target being registered.		/// @param T - The target being registered.
	/// @param Fn - A function to construct a TargetMachine for the target.		/// @param Fn - A function to construct a TargetMachine for the target.
	static void RegisterTargetMachine(Target &T,		static void RegisterTargetMachine(Target &T,
	Target::TargetMachineCtorTy Fn) {		Target::TargetMachineCtorTy Fn) {
	// Ignore duplicate registration.		T.TargetMachineCtorFn = Fn;
	if (!T.TargetMachineCtorFn)
	T.TargetMachineCtorFn = Fn;
	}		}
	/// RegisterMCAsmBackend - Register a MCAsmBackend implementation for t he		/// RegisterMCAsmBackend - Register a MCAsmBackend implementation for t he
	/// given target.		/// given target.
	///		///
	/// Clients are responsible for ensuring that registration doesn't occu r		/// Clients are responsible for ensuring that registration doesn't occu r
	/// while another thread is attempting to access the registry. Typicall y		/// while another thread is attempting to access the registry. Typicall y
	/// this is done by initializing all targets at program startup.		/// this is done by initializing all targets at program startup.
	///		///
	/// @param T - The target being registered.		/// @param T - The target being registered.
	/// @param Fn - A function to construct an AsmBackend for the target.		/// @param Fn - A function to construct an AsmBackend for the target.
	static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn) {		static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn) {
	if (!T.MCAsmBackendCtorFn)		T.MCAsmBackendCtorFn = Fn;
	T.MCAsmBackendCtorFn = Fn;
	}		}
	/// RegisterMCAsmParser - Register a MCTargetAsmParser implementation f or		/// RegisterMCAsmParser - Register a MCTargetAsmParser implementation f or
	/// the given target.		/// the given target.
	///		///
	/// Clients are responsible for ensuring that registration doesn't occu r		/// Clients are responsible for ensuring that registration doesn't occu r
	/// while another thread is attempting to access the registry. Typicall y		/// while another thread is attempting to access the registry. Typicall y
	/// this is done by initializing all targets at program startup.		/// this is done by initializing all targets at program startup.
	///		///
	/// @param T - The target being registered.		/// @param T - The target being registered.
	/// @param Fn - A function to construct an MCTargetAsmParser for the ta rget.		/// @param Fn - A function to construct an MCTargetAsmParser for the ta rget.
	static void RegisterMCAsmParser(Target &T, Target::MCAsmParserCtorTy Fn ) {		static void RegisterMCAsmParser(Target &T, Target::MCAsmParserCtorTy Fn ) {
	if (!T.MCAsmParserCtorFn)		T.MCAsmParserCtorFn = Fn;
	T.MCAsmParserCtorFn = Fn;
	}		}
	/// RegisterAsmPrinter - Register an AsmPrinter implementation for the given		/// RegisterAsmPrinter - Register an AsmPrinter implementation for the given
	/// target.		/// target.
	///		///
	/// Clients are responsible for ensuring that registration doesn't occu r		/// Clients are responsible for ensuring that registration doesn't occu r
	/// while another thread is attempting to access the registry. Typicall y		/// while another thread is attempting to access the registry. Typicall y
	/// this is done by initializing all targets at program startup.		/// this is done by initializing all targets at program startup.
	///		///
	/// @param T - The target being registered.		/// @param T - The target being registered.
	/// @param Fn - A function to construct an AsmPrinter for the target.		/// @param Fn - A function to construct an AsmPrinter for the target.
	static void RegisterAsmPrinter(Target &T, Target::AsmPrinterCtorTy Fn) {		static void RegisterAsmPrinter(Target &T, Target::AsmPrinterCtorTy Fn) {
	// Ignore duplicate registration.		T.AsmPrinterCtorFn = Fn;
	if (!T.AsmPrinterCtorFn)
	T.AsmPrinterCtorFn = Fn;
	}		}
	/// RegisterMCDisassembler - Register a MCDisassembler implementation f or		/// RegisterMCDisassembler - Register a MCDisassembler implementation f or
	/// the given target.		/// the given target.
	///		///
	/// Clients are responsible for ensuring that registration doesn't occu r		/// Clients are responsible for ensuring that registration doesn't occu r
	/// while another thread is attempting to access the registry. Typicall y		/// while another thread is attempting to access the registry. Typicall y
	/// this is done by initializing all targets at program startup.		/// this is done by initializing all targets at program startup.
	///		///
	/// @param T - The target being registered.		/// @param T - The target being registered.
	/// @param Fn - A function to construct an MCDisassembler for the targe t.		/// @param Fn - A function to construct an MCDisassembler for the targe t.
	static void RegisterMCDisassembler(Target &T,		static void RegisterMCDisassembler(Target &T,
	Target::MCDisassemblerCtorTy Fn) {		Target::MCDisassemblerCtorTy Fn) {
	if (!T.MCDisassemblerCtorFn)		T.MCDisassemblerCtorFn = Fn;
	T.MCDisassemblerCtorFn = Fn;
	}		}
	/// RegisterMCInstPrinter - Register a MCInstPrinter implementation for the		/// RegisterMCInstPrinter - Register a MCInstPrinter implementation for the
	/// given target.		/// given target.
	///		///
	/// Clients are responsible for ensuring that registration doesn't occu r		/// Clients are responsible for ensuring that registration doesn't occu r
	/// while another thread is attempting to access the registry. Typicall y		/// while another thread is attempting to access the registry. Typicall y
	/// this is done by initializing all targets at program startup.		/// this is done by initializing all targets at program startup.
	///		///
	/// @param T - The target being registered.		/// @param T - The target being registered.
	/// @param Fn - A function to construct an MCInstPrinter for the target .		/// @param Fn - A function to construct an MCInstPrinter for the target .
	static void RegisterMCInstPrinter(Target &T,		static void RegisterMCInstPrinter(Target &T,
	Target::MCInstPrinterCtorTy Fn) {		Target::MCInstPrinterCtorTy Fn) {
	if (!T.MCInstPrinterCtorFn)		T.MCInstPrinterCtorFn = Fn;
	T.MCInstPrinterCtorFn = Fn;
	}		}
	/// RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the		/// RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the
	/// given target.		/// given target.
	///		///
	/// Clients are responsible for ensuring that registration doesn't occu r		/// Clients are responsible for ensuring that registration doesn't occu r
	/// while another thread is attempting to access the registry. Typicall y		/// while another thread is attempting to access the registry. Typicall y
	/// this is done by initializing all targets at program startup.		/// this is done by initializing all targets at program startup.
	///		///
	/// @param T - The target being registered.		/// @param T - The target being registered.
	/// @param Fn - A function to construct an MCCodeEmitter for the target .		/// @param Fn - A function to construct an MCCodeEmitter for the target .
	static void RegisterMCCodeEmitter(Target &T,		static void RegisterMCCodeEmitter(Target &T,
	Target::MCCodeEmitterCtorTy Fn) {		Target::MCCodeEmitterCtorTy Fn) {
	if (!T.MCCodeEmitterCtorFn)		T.MCCodeEmitterCtorFn = Fn;
	T.MCCodeEmitterCtorFn = Fn;
	}		}
	/// RegisterMCObjectStreamer - Register a object code MCStreamer		/// RegisterMCObjectStreamer - Register a object code MCStreamer
	/// implementation for the given target.		/// implementation for the given target.
	///		///
	/// Clients are responsible for ensuring that registration doesn't occu r		/// Clients are responsible for ensuring that registration doesn't occu r
	/// while another thread is attempting to access the registry. Typicall y		/// while another thread is attempting to access the registry. Typicall y
	/// this is done by initializing all targets at program startup.		/// this is done by initializing all targets at program startup.
	///		///
	/// @param T - The target being registered.		/// @param T - The target being registered.
	/// @param Fn - A function to construct an MCStreamer for the target.		/// @param Fn - A function to construct an MCStreamer for the target.
	static void RegisterMCObjectStreamer(Target &T,		static void RegisterMCObjectStreamer(Target &T,
	Target::MCObjectStreamerCtorTy Fn) {		Target::MCObjectStreamerCtorTy Fn) {
	if (!T.MCObjectStreamerCtorFn)		T.MCObjectStreamerCtorFn = Fn;
	T.MCObjectStreamerCtorFn = Fn;
	}		}
	/// RegisterAsmStreamer - Register an assembly MCStreamer implementatio n		/// RegisterAsmStreamer - Register an assembly MCStreamer implementatio n
	/// for the given target.		/// for the given target.
	///		///
	/// Clients are responsible for ensuring that registration doesn't occu r		/// Clients are responsible for ensuring that registration doesn't occu r
	/// while another thread is attempting to access the registry. Typicall y		/// while another thread is attempting to access the registry. Typicall y
	/// this is done by initializing all targets at program startup.		/// this is done by initializing all targets at program startup.
	///		///
	/// @param T - The target being registered.		/// @param T - The target being registered.
	/// @param Fn - A function to construct an MCStreamer for the target.		/// @param Fn - A function to construct an MCStreamer for the target.
	static void RegisterAsmStreamer(Target &T, Target::AsmStreamerCtorTy Fn ) {		static void RegisterAsmStreamer(Target &T, Target::AsmStreamerCtorTy Fn ) {
	if (T.AsmStreamerCtorFn == createAsmStreamer)		T.AsmStreamerCtorFn = Fn;
	T.AsmStreamerCtorFn = Fn;		}
			/// RegisterMCRelocationInfo - Register an MCRelocationInfo
			/// implementation for the given target.
			///
			/// Clients are responsible for ensuring that registration doesn't occu
			r
			/// while another thread is attempting to access the registry. Typicall
			y
			/// this is done by initializing all targets at program startup.
			///
			/// @param T - The target being registered.
			/// @param Fn - A function to construct an MCRelocationInfo for the tar
			get.
			static void RegisterMCRelocationInfo(Target &T,
			Target::MCRelocationInfoCtorTy Fn)
			{
			T.MCRelocationInfoCtorFn = Fn;
			}
			/// RegisterMCSymbolizer - Register an MCSymbolizer
			/// implementation for the given target.
			///
			/// Clients are responsible for ensuring that registration doesn't occu
			r
			/// while another thread is attempting to access the registry. Typicall
			y
			/// this is done by initializing all targets at program startup.
			///
			/// @param T - The target being registered.
			/// @param Fn - A function to construct an MCSymbolizer for the target.
			static void RegisterMCSymbolizer(Target &T,
			Target::MCSymbolizerCtorTy Fn) {
			T.MCSymbolizerCtorFn = Fn;
	}		}
	/// @}		/// @}
	};		};
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	/// RegisterTarget - Helper template for registering a target, for use in the		/// RegisterTarget - Helper template for registering a target, for use in the
	/// target's initialization function. Usage:		/// target's initialization function. Usage:
	///		///
	skipping to change at line 805		skipping to change at line 858
	/// extern "C" void LLVMInitializeFooTarget() {		/// extern "C" void LLVMInitializeFooTarget() {
	/// extern Target TheFooTarget;		/// extern Target TheFooTarget;
	/// RegisterMCAsmInfo<FooMCAsmInfo> X(TheFooTarget);		/// RegisterMCAsmInfo<FooMCAsmInfo> X(TheFooTarget);
	/// }		/// }
	template<class MCAsmInfoImpl>		template<class MCAsmInfoImpl>
	struct RegisterMCAsmInfo {		struct RegisterMCAsmInfo {
	RegisterMCAsmInfo(Target &T) {		RegisterMCAsmInfo(Target &T) {
	TargetRegistry::RegisterMCAsmInfo(T, &Allocator);		TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
	}		}
	private:		private:
	static MCAsmInfo *Allocator(const Target &T, StringRef TT) {		static MCAsmInfo *Allocator(const MCRegisterInfo &/*MRI*/, StringRef TT
	return new MCAsmInfoImpl(T, TT);		) {
			return new MCAsmInfoImpl(TT);
	}		}
	};		};
	/// RegisterMCAsmInfoFn - Helper template for registering a target assemb ly info		/// RegisterMCAsmInfoFn - Helper template for registering a target assemb ly info
	/// implementation. This invokes the specified function to do the		/// implementation. This invokes the specified function to do the
	/// construction. Usage:		/// construction. Usage:
	///		///
	/// extern "C" void LLVMInitializeFooTarget() {		/// extern "C" void LLVMInitializeFooTarget() {
	/// extern Target TheFooTarget;		/// extern Target TheFooTarget;
	skipping to change at line 839		skipping to change at line 892
	/// extern "C" void LLVMInitializeFooTarget() {		/// extern "C" void LLVMInitializeFooTarget() {
	/// extern Target TheFooTarget;		/// extern Target TheFooTarget;
	/// RegisterMCCodeGenInfo<FooMCCodeGenInfo> X(TheFooTarget);		/// RegisterMCCodeGenInfo<FooMCCodeGenInfo> X(TheFooTarget);
	/// }		/// }
	template<class MCCodeGenInfoImpl>		template<class MCCodeGenInfoImpl>
	struct RegisterMCCodeGenInfo {		struct RegisterMCCodeGenInfo {
	RegisterMCCodeGenInfo(Target &T) {		RegisterMCCodeGenInfo(Target &T) {
	TargetRegistry::RegisterMCCodeGenInfo(T, &Allocator);		TargetRegistry::RegisterMCCodeGenInfo(T, &Allocator);
	}		}
	private:		private:
	static MCCodeGenInfo *Allocator(StringRef TT, Reloc::Model RM,		static MCCodeGenInfo *Allocator(StringRef /*TT*/, Reloc::Model /*RM*/,
	CodeModel::Model CM, CodeGenOpt::Level		CodeModel::Model /*CM*/,
	OL) {		CodeGenOpt::Level /*OL*/) {
	return new MCCodeGenInfoImpl();		return new MCCodeGenInfoImpl();
	}		}
	};		};
	/// RegisterMCCodeGenInfoFn - Helper template for registering a target co degen		/// RegisterMCCodeGenInfoFn - Helper template for registering a target co degen
	/// info implementation. This invokes the specified function to do the		/// info implementation. This invokes the specified function to do the
	/// construction. Usage:		/// construction. Usage:
	///		///
	/// extern "C" void LLVMInitializeFooTarget() {		/// extern "C" void LLVMInitializeFooTarget() {
	/// extern Target TheFooTarget;		/// extern Target TheFooTarget;
	skipping to change at line 939		skipping to change at line 993
	/// extern "C" void LLVMInitializeFooTarget() {		/// extern "C" void LLVMInitializeFooTarget() {
	/// extern Target TheFooTarget;		/// extern Target TheFooTarget;
	/// RegisterMCRegInfo<FooMCRegInfo> X(TheFooTarget);		/// RegisterMCRegInfo<FooMCRegInfo> X(TheFooTarget);
	/// }		/// }
	template<class MCRegisterInfoImpl>		template<class MCRegisterInfoImpl>
	struct RegisterMCRegInfo {		struct RegisterMCRegInfo {
	RegisterMCRegInfo(Target &T) {		RegisterMCRegInfo(Target &T) {
	TargetRegistry::RegisterMCRegInfo(T, &Allocator);		TargetRegistry::RegisterMCRegInfo(T, &Allocator);
	}		}
	private:		private:
	static MCRegisterInfo *Allocator(StringRef TT) {		static MCRegisterInfo *Allocator(StringRef /*TT*/) {
	return new MCRegisterInfoImpl();		return new MCRegisterInfoImpl();
	}		}
	};		};
	/// RegisterMCRegInfoFn - Helper template for registering a target regist er		/// RegisterMCRegInfoFn - Helper template for registering a target regist er
	/// info implementation. This invokes the specified function to do the		/// info implementation. This invokes the specified function to do the
	/// construction. Usage:		/// construction. Usage:
	///		///
	/// extern "C" void LLVMInitializeFooTarget() {		/// extern "C" void LLVMInitializeFooTarget() {
	/// extern Target TheFooTarget;		/// extern Target TheFooTarget;
	skipping to change at line 972		skipping to change at line 1026
	/// extern "C" void LLVMInitializeFooTarget() {		/// extern "C" void LLVMInitializeFooTarget() {
	/// extern Target TheFooTarget;		/// extern Target TheFooTarget;
	/// RegisterMCSubtargetInfo<FooMCSubtargetInfo> X(TheFooTarget);		/// RegisterMCSubtargetInfo<FooMCSubtargetInfo> X(TheFooTarget);
	/// }		/// }
	template<class MCSubtargetInfoImpl>		template<class MCSubtargetInfoImpl>
	struct RegisterMCSubtargetInfo {		struct RegisterMCSubtargetInfo {
	RegisterMCSubtargetInfo(Target &T) {		RegisterMCSubtargetInfo(Target &T) {
	TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator);		TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator);
	}		}
	private:		private:
	static MCSubtargetInfo *Allocator(StringRef TT, StringRef CPU,		static MCSubtargetInfo *Allocator(StringRef /*TT*/, StringRef /*CPU*/,
	StringRef FS) {		StringRef /*FS*/) {
	return new MCSubtargetInfoImpl();		return new MCSubtargetInfoImpl();
	}		}
	};		};
	/// RegisterMCSubtargetInfoFn - Helper template for registering a target		/// RegisterMCSubtargetInfoFn - Helper template for registering a target
	/// subtarget info implementation. This invokes the specified function t o		/// subtarget info implementation. This invokes the specified function t o
	/// do the construction. Usage:		/// do the construction. Usage:
	///		///
	/// extern "C" void LLVMInitializeFooTarget() {		/// extern "C" void LLVMInitializeFooTarget() {
	/// extern Target TheFooTarget;		/// extern Target TheFooTarget;
	skipping to change at line 1031		skipping to change at line 1085
	/// extern Target TheFooTarget;		/// extern Target TheFooTarget;
	/// RegisterMCAsmBackend<FooAsmLexer> X(TheFooTarget);		/// RegisterMCAsmBackend<FooAsmLexer> X(TheFooTarget);
	/// }		/// }
	template<class MCAsmBackendImpl>		template<class MCAsmBackendImpl>
	struct RegisterMCAsmBackend {		struct RegisterMCAsmBackend {
	RegisterMCAsmBackend(Target &T) {		RegisterMCAsmBackend(Target &T) {
	TargetRegistry::RegisterMCAsmBackend(T, &Allocator);		TargetRegistry::RegisterMCAsmBackend(T, &Allocator);
	}		}
	private:		private:
	static MCAsmBackend *Allocator(const Target &T, StringRef Triple,		static MCAsmBackend *Allocator(const Target &T,
	StringRef CPU) {		const MCRegisterInfo &MRI,
	return new MCAsmBackendImpl(T, Triple, CPU);		StringRef Triple, StringRef CPU) {
			return new MCAsmBackendImpl(T, MRI, Triple, CPU);
	}		}
	};		};
	/// RegisterMCAsmParser - Helper template for registering a target specif ic		/// RegisterMCAsmParser - Helper template for registering a target specif ic
	/// assembly parser, for use in the target machine initialization		/// assembly parser, for use in the target machine initialization
	/// function. Usage:		/// function. Usage:
	///		///
	/// extern "C" void LLVMInitializeFooMCAsmParser() {		/// extern "C" void LLVMInitializeFooMCAsmParser() {
	/// extern Target TheFooTarget;		/// extern Target TheFooTarget;
	/// RegisterMCAsmParser<FooAsmParser> X(TheFooTarget);		/// RegisterMCAsmParser<FooAsmParser> X(TheFooTarget);
	/// }		/// }
	template<class MCAsmParserImpl>		template<class MCAsmParserImpl>
	struct RegisterMCAsmParser {		struct RegisterMCAsmParser {
	RegisterMCAsmParser(Target &T) {		RegisterMCAsmParser(Target &T) {
	TargetRegistry::RegisterMCAsmParser(T, &Allocator);		TargetRegistry::RegisterMCAsmParser(T, &Allocator);
	}		}
	private:		private:
	static MCTargetAsmParser *Allocator(MCSubtargetInfo &STI, MCAsmParser &		static MCTargetAsmParser *Allocator(MCSubtargetInfo &STI, MCAsmParser &
	P) {		P,
	return new MCAsmParserImpl(STI, P);		const MCInstrInfo &MII) {
			return new MCAsmParserImpl(STI, P, MII);
	}		}
	};		};
	/// RegisterAsmPrinter - Helper template for registering a target specifi c		/// RegisterAsmPrinter - Helper template for registering a target specifi c
	/// assembly printer, for use in the target machine initialization		/// assembly printer, for use in the target machine initialization
	/// function. Usage:		/// function. Usage:
	///		///
	/// extern "C" void LLVMInitializeFooAsmPrinter() {		/// extern "C" void LLVMInitializeFooAsmPrinter() {
	/// extern Target TheFooTarget;		/// extern Target TheFooTarget;
	/// RegisterAsmPrinter<FooAsmPrinter> X(TheFooTarget);		/// RegisterAsmPrinter<FooAsmPrinter> X(TheFooTarget);
	skipping to change at line 1092		skipping to change at line 1148
	/// extern Target TheFooTarget;		/// extern Target TheFooTarget;
	/// RegisterMCCodeEmitter<FooCodeEmitter> X(TheFooTarget);		/// RegisterMCCodeEmitter<FooCodeEmitter> X(TheFooTarget);
	/// }		/// }
	template<class MCCodeEmitterImpl>		template<class MCCodeEmitterImpl>
	struct RegisterMCCodeEmitter {		struct RegisterMCCodeEmitter {
	RegisterMCCodeEmitter(Target &T) {		RegisterMCCodeEmitter(Target &T) {
	TargetRegistry::RegisterMCCodeEmitter(T, &Allocator);		TargetRegistry::RegisterMCCodeEmitter(T, &Allocator);
	}		}
	private:		private:
	static MCCodeEmitter *Allocator(const MCInstrInfo &II,		static MCCodeEmitter *Allocator(const MCInstrInfo &/*II*/,
	const MCRegisterInfo &MRI,		const MCRegisterInfo &/*MRI*/,
	const MCSubtargetInfo &STI,		const MCSubtargetInfo &/*STI*/,
	MCContext &Ctx) {		MCContext &/*Ctx*/) {
	return new MCCodeEmitterImpl();		return new MCCodeEmitterImpl();
	}		}
	};		};
	}		}
	#endif		#endif
End of changes. 41 change blocks.
	100 lines changed or deleted		168 lines changed or added

	TargetSchedule.h		TargetSchedule.h
	skipping to change at line 87		skipping to change at line 87
	return &InstrItins;		return &InstrItins;
	return 0;		return 0;
	}		}
	/// \brief Identify the processor corresponding to the current subtarget.		/// \brief Identify the processor corresponding to the current subtarget.
	unsigned getProcessorID() const { return SchedModel.getProcessorID(); }		unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
	/// \brief Maximum number of micro-ops that may be scheduled per cycle.		/// \brief Maximum number of micro-ops that may be scheduled per cycle.
	unsigned getIssueWidth() const { return SchedModel.IssueWidth; }		unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
	/// \brief Number of cycles the OOO processor is expected to hide.
	unsigned getILPWindow() const { return SchedModel.ILPWindow; }
	/// \brief Return the number of issue slots required for this MI.		/// \brief Return the number of issue slots required for this MI.
	unsigned getNumMicroOps(const MachineInstr *MI,		unsigned getNumMicroOps(const MachineInstr *MI,
	const MCSchedClassDesc *SC = 0) const;		const MCSchedClassDesc *SC = 0) const;
	/// \brief Get the number of kinds of resources for this target.		/// \brief Get the number of kinds of resources for this target.
	unsigned getNumProcResourceKinds() const {		unsigned getNumProcResourceKinds() const {
	return SchedModel.getNumProcResourceKinds();		return SchedModel.getNumProcResourceKinds();
	}		}
	/// \brief Get a processor resource by ID for convenience.		/// \brief Get a processor resource by ID for convenience.
	skipping to change at line 134		skipping to change at line 131
	unsigned getMicroOpFactor() const {		unsigned getMicroOpFactor() const {
	return MicroOpFactor;		return MicroOpFactor;
	}		}
	/// \brief Multiply cycle count by this factor to normalize it relative t o		/// \brief Multiply cycle count by this factor to normalize it relative t o
	/// other resources. This is the number of resource units per cycle.		/// other resources. This is the number of resource units per cycle.
	unsigned getLatencyFactor() const {		unsigned getLatencyFactor() const {
	return ResourceLCM;		return ResourceLCM;
	}		}
			/// \brief Number of micro-ops that may be buffered for OOO execution.
			unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSi
			ze; }
			/// \brief Number of resource units that may be buffered for OOO executio
			n.
			/// \return The buffer size in resource units or -1 for unlimited.
			int getResourceBufferSize(unsigned PIdx) const {
			return SchedModel.getProcResource(PIdx)->BufferSize;
			}
	/// \brief Compute operand latency based on the available machine model.		/// \brief Compute operand latency based on the available machine model.
	///		///
	/// Computes and return the latency of the given data dependent def and u se		/// Compute and return the latency of the given data dependent def and us e
	/// when the operand indices are already known. UseMI may be NULL for an		/// when the operand indices are already known. UseMI may be NULL for an
	/// unknown user.		/// unknown user.
	///
	/// FindMin may be set to get the minimum vs. expected latency. Minimum
	/// latency is used for scheduling groups, while expected latency is for
	/// instruction cost and critical path.
	unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOpe rIdx,		unsigned computeOperandLatency(const MachineInstr *DefMI, unsigned DefOpe rIdx,
	const MachineInstr *UseMI, unsigned UseOpe		const MachineInstr *UseMI, unsigned UseOpe
	rIdx,		rIdx)
	bool FindMin) const;		const;
	/// \brief Compute the instruction latency based on the available machine		/// \brief Compute the instruction latency based on the available machine
	/// model.		/// model.
	///		///
	/// Compute and return the expected latency of this instruction independe nt of		/// Compute and return the expected latency of this instruction independe nt of
	/// a particular use. computeOperandLatency is the prefered API, but this is		/// a particular use. computeOperandLatency is the prefered API, but this is
	/// occasionally useful to help estimate instruction cost.		/// occasionally useful to help estimate instruction cost.
	unsigned computeInstrLatency(const MachineInstr *MI) const;		///
			/// If UseDefaultDefLatency is false and no new machine sched model is
			/// present this method falls back to TII->getInstrLatency with an empty
			/// instruction itinerary (this is so we preserve the previous behavior o
			f the
			/// if converter after moving it to TargetSchedModel).
			unsigned computeInstrLatency(const MachineInstr *MI,
			bool UseDefaultDefLatency = true) const;
	/// \brief Output dependency latency of a pair of defs of the same regist er.		/// \brief Output dependency latency of a pair of defs of the same regist er.
	///		///
	/// This is typically one cycle.		/// This is typically one cycle.
	unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,		unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
	const MachineInstr *DepMI) const;		const MachineInstr *DepMI) const;
	private:
	/// getDefLatency is a helper for computeOperandLatency. Return the
	/// instruction's latency if operand lookup is not required.
	/// Otherwise return -1.
	int getDefLatency(const MachineInstr *DefMI, bool FindMin) const;
	};		};
	} // namespace llvm		} // namespace llvm
	#endif		#endif
End of changes. 7 change blocks.
	18 lines changed or deleted		23 lines changed or added

	TargetSchedule.td		TargetSchedule.td
	skipping to change at line 75		skipping to change at line 75
	def instregex;		def instregex;
	// Define the SchedMachineModel and provide basic properties for		// Define the SchedMachineModel and provide basic properties for
	// coarse grained instruction cost model. Default values for the		// coarse grained instruction cost model. Default values for the
	// properties are defined in MCSchedModel. A value of "-1" in the		// properties are defined in MCSchedModel. A value of "-1" in the
	// target description's SchedMachineModel indicates that the property		// target description's SchedMachineModel indicates that the property
	// is not overriden by the target.		// is not overriden by the target.
	//		//
	// Target hooks allow subtargets to associate LoadLatency and		// Target hooks allow subtargets to associate LoadLatency and
	// HighLatency with groups of opcodes.		// HighLatency with groups of opcodes.
			//
			// See MCSchedule.h for detailed comments.
	class SchedMachineModel {		class SchedMachineModel {
	int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle.		int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle.
	int MinLatency = -1; // Determines which instrucions are allowed in a gro up.		int MinLatency = -1; // Determines which instructions are allowed in a gr oup.
	// (-1) inorder (0) ooo, (1): inorder +var latencies .		// (-1) inorder (0) ooo, (1): inorder +var latencies .
	int ILPWindow = -1; // Cycles of latency likely hidden by hardware buffe rs.		int MicroOpBufferSize = -1; // Max micro-ops that can be buffered.
	int LoadLatency = -1; // Cycles for loads to access the cache.		int LoadLatency = -1; // Cycles for loads to access the cache.
	int HighLatency = -1; // Approximation of cycles for "high latency" ops.		int HighLatency = -1; // Approximation of cycles for "high latency" ops.
	int MispredictPenalty = -1; // Extra cycles for a mispredicted branch.		int MispredictPenalty = -1; // Extra cycles for a mispredicted branch.
	// Per-cycle resources tables.		// Per-cycle resources tables.
	ProcessorItineraries Itineraries = NoItineraries;		ProcessorItineraries Itineraries = NoItineraries;
			// Subtargets that define a model for only a subset of instructions
			// that have a scheduling class (itinerary class or SchedRW list)
			// and may actually be generated for that subtarget must clear this
			// bit. Otherwise, the scheduler considers an unmodelled opcode to
			// be an error. This should only be set during initial bringup,
			// or there will be no way to catch simple errors in the model
			// resulting from changes to the instruction definitions.
			bit CompleteModel = 1;
	bit NoModel = 0; // Special tag to indicate missing machine model.		bit NoModel = 0; // Special tag to indicate missing machine model.
	}		}
	def NoSchedModel : SchedMachineModel {		def NoSchedModel : SchedMachineModel {
	let NoModel = 1;		let NoModel = 1;
	}		}
	// Define a kind of processor resource that may be common across		// Define a kind of processor resource that may be common across
	// similar subtargets.		// similar subtargets.
	class ProcResourceKind;		class ProcResourceKind;
	skipping to change at line 109		skipping to change at line 120
	// determines the throughput of instructions that require the resource.		// determines the throughput of instructions that require the resource.
	//		//
	// An optional Super resource may be given to model these resources as		// An optional Super resource may be given to model these resources as
	// a subset of the more general super resources. Using one of these		// a subset of the more general super resources. Using one of these
	// resources implies using one of the super resoruces.		// resources implies using one of the super resoruces.
	//		//
	// ProcResourceUnits normally model a few buffered resources within an		// ProcResourceUnits normally model a few buffered resources within an
	// out-of-order engine that the compiler attempts to conserve.		// out-of-order engine that the compiler attempts to conserve.
	// Buffered resources may be held for multiple clock cycles, but the		// Buffered resources may be held for multiple clock cycles, but the
	// scheduler does not pin them to a particular clock cycle relative to		// scheduler does not pin them to a particular clock cycle relative to
	// instruction dispatch. Setting Buffered=0 changes this to an		// instruction dispatch. Setting BufferSize=0 changes this to an
	// in-order resource. In this case, the scheduler counts down from the		// in-order resource. In this case, the scheduler counts down from the
	// cycle that the instruction issues in-order, forcing an interlock		// cycle that the instruction issues in-order, forcing an interlock
	// with subsequent instructions that require the same resource until		// with subsequent instructions that require the same resource until
	// the number of ResourceCyles specified in WriteRes expire.		// the number of ResourceCyles specified in WriteRes expire.
	//		//
	// SchedModel ties these units to a processor for any stand-alone defs		// SchedModel ties these units to a processor for any stand-alone defs
	// of this class. Instances of subclass ProcResource will be automatically		// of this class. Instances of subclass ProcResource will be automatically
	// attached to a processor, so SchedModel is not needed.		// attached to a processor, so SchedModel is not needed.
	class ProcResourceUnits<ProcResourceKind kind, int num> {		class ProcResourceUnits<ProcResourceKind kind, int num> {
	ProcResourceKind Kind = kind;		ProcResourceKind Kind = kind;
	int NumUnits = num;		int NumUnits = num;
	ProcResourceKind Super = ?;		ProcResourceKind Super = ?;
	bit Buffered = 1;		int BufferSize = -1;
	SchedMachineModel SchedModel = ?;		SchedMachineModel SchedModel = ?;
	}		}
	// EponymousProcResourceKind helps implement ProcResourceUnits by		// EponymousProcResourceKind helps implement ProcResourceUnits by
	// allowing a ProcResourceUnits definition to reference itself. It		// allowing a ProcResourceUnits definition to reference itself. It
	// should not be referenced anywhere else.		// should not be referenced anywhere else.
	def EponymousProcResourceKind : ProcResourceKind;		def EponymousProcResourceKind : ProcResourceKind;
	// Subtargets typically define processor resource kind and number of		// Subtargets typically define processor resource kind and number of
	// units in one place.		// units in one place.
	class ProcResource<int num> : ProcResourceKind,		class ProcResource<int num> : ProcResourceKind,
	ProcResourceUnits<EponymousProcResourceKind, num>;		ProcResourceUnits<EponymousProcResourceKind, num>;
	class ProcResGroup<list<ProcResource> resources> : ProcResourceKind {		class ProcResGroup<list<ProcResource> resources> : ProcResourceKind {
	list<ProcResource> Resources = resources;		list<ProcResource> Resources = resources;
	SchedMachineModel SchedModel = ?;		SchedMachineModel SchedModel = ?;
			int BufferSize = -1;
	}		}
	// A target architecture may define SchedReadWrite types and associate		// A target architecture may define SchedReadWrite types and associate
	// them with instruction operands.		// them with instruction operands.
	class SchedReadWrite;		class SchedReadWrite;
	// List the per-operand types that map to the machine model of an		// List the per-operand types that map to the machine model of an
	// instruction. One SchedWrite type must be listed for each explicit		// instruction. One SchedWrite type must be listed for each explicit
	// def operand in order. Additional SchedWrite types may optionally be		// def operand in order. Additional SchedWrite types may optionally be
	// listed for implicit def operands. SchedRead types may optionally		// listed for implicit def operands. SchedRead types may optionally
End of changes. 7 change blocks.
	4 lines changed or deleted		16 lines changed or added

	TargetSelectionDAG.td		TargetSelectionDAG.td
	skipping to change at line 378		skipping to change at line 378
	def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;		def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
	def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;		def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
	def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>;		def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>;
	def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;		def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
	def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;		def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
	def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;		def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
	def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;		def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
	def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;		def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
	def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;		def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
	def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;		def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
			def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>;
	def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>;		def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>;
	def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;		def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
	def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;		def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
	def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;		def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
	def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;		def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
	def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;		def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
			def frnd : SDNode<"ISD::FROUND" , SDTFPUnaryOp>;
	def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;		def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
	def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;		def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
	def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;		def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
	def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;		def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
	def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;		def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
	def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;		def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
	def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;		def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
	def f16_to_f32 : SDNode<"ISD::FP16_TO_FP32", SDTIntToFPOp>;		def f16_to_f32 : SDNode<"ISD::FP16_TO_FP32", SDTIntToFPOp>;
	skipping to change at line 465		skipping to change at line 467
	[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;		[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
	def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;		def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
	def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, [] >;		def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, [] >;
	def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,		def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
	[]>;		[]>;
	def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",		def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
	SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;		SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
	def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",		def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
	SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;		SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
			def concat_vectors : SDNode<"ISD::CONCAT_VECTORS",
			SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<1, 2>]>,[
			]>;
	// This operator does not do subvector type checking. The ARM		// This operator does not do subvector type checking. The ARM
	// backend, at least, needs it.		// backend, at least, needs it.
	def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",		def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
	SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>,		SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>,
	[]>;		[]>;
	// This operator does subvector type checking.		// This operator does subvector type checking.
	def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;		def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
	def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []> ;		def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []> ;
End of changes. 3 change blocks.
	0 lines changed or deleted		5 lines changed or added

	TargetSelectionDAGInfo.h		TargetSelectionDAGInfo.h
	skipping to change at line 57		skipping to change at line 57
	/// SDValue if the target declines to use custom code and a different		/// SDValue if the target declines to use custom code and a different
	/// lowering strategy should be used.		/// lowering strategy should be used.
	///		///
	/// If AlwaysInline is true, the size is constant and the target should n ot		/// If AlwaysInline is true, the size is constant and the target should n ot
	/// emit any calls and is strongly encouraged to attempt to emit inline c ode		/// emit any calls and is strongly encouraged to attempt to emit inline c ode
	/// even if it is beyond the usual threshold because this intrinsic is be ing		/// even if it is beyond the usual threshold because this intrinsic is be ing
	/// expanded in a place where calls are not feasible (e.g. within the pro logue		/// expanded in a place where calls are not feasible (e.g. within the pro logue
	/// for another call). If the target chooses to decline an AlwaysInline		/// for another call). If the target chooses to decline an AlwaysInline
	/// request here, legalize will resort to using simple loads and stores.		/// request here, legalize will resort to using simple loads and stores.
	virtual SDValue		virtual SDValue
	EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,		EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
	SDValue Chain,		SDValue Chain,
	SDValue Op1, SDValue Op2,		SDValue Op1, SDValue Op2,
	SDValue Op3, unsigned Align, bool isVolatile,		SDValue Op3, unsigned Align, bool isVolatile,
	bool AlwaysInline,		bool AlwaysInline,
	MachinePointerInfo DstPtrInfo,		MachinePointerInfo DstPtrInfo,
	MachinePointerInfo SrcPtrInfo) const {		MachinePointerInfo SrcPtrInfo) const {
	return SDValue();		return SDValue();
	}		}
	/// EmitTargetCodeForMemmove - Emit target-specific code that performs a		/// EmitTargetCodeForMemmove - Emit target-specific code that performs a
	/// memmove. This can be used by targets to provide code sequences for ca ses		/// memmove. This can be used by targets to provide code sequences for ca ses
	/// that don't fit the target's parameters for simple loads/stores and ca n be		/// that don't fit the target's parameters for simple loads/stores and ca n be
	/// more efficient than using a library call. This function can return a null		/// more efficient than using a library call. This function can return a null
	/// SDValue if the target declines to use custom code and a different		/// SDValue if the target declines to use custom code and a different
	/// lowering strategy should be used.		/// lowering strategy should be used.
	virtual SDValue		virtual SDValue
	EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl,		EmitTargetCodeForMemmove(SelectionDAG &DAG, SDLoc dl,
	SDValue Chain,		SDValue Chain,
	SDValue Op1, SDValue Op2,		SDValue Op1, SDValue Op2,
	SDValue Op3, unsigned Align, bool isVolatile,		SDValue Op3, unsigned Align, bool isVolatile,
	MachinePointerInfo DstPtrInfo,		MachinePointerInfo DstPtrInfo,
	MachinePointerInfo SrcPtrInfo) const {		MachinePointerInfo SrcPtrInfo) const {
	return SDValue();		return SDValue();
	}		}
	/// EmitTargetCodeForMemset - Emit target-specific code that performs a		/// EmitTargetCodeForMemset - Emit target-specific code that performs a
	/// memset. This can be used by targets to provide code sequences for cas es		/// memset. This can be used by targets to provide code sequences for cas es
	/// that don't fit the target's parameters for simple stores and can be m ore		/// that don't fit the target's parameters for simple stores and can be m ore
	/// efficient than using a library call. This function can return a null		/// efficient than using a library call. This function can return a null
	/// SDValue if the target declines to use custom code and a different		/// SDValue if the target declines to use custom code and a different
	/// lowering strategy should be used.		/// lowering strategy should be used.
	virtual SDValue		virtual SDValue
	EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,		EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl,
	SDValue Chain,		SDValue Chain,
	SDValue Op1, SDValue Op2,		SDValue Op1, SDValue Op2,
	SDValue Op3, unsigned Align, bool isVolatile,		SDValue Op3, unsigned Align, bool isVolatile,
	MachinePointerInfo DstPtrInfo) const {		MachinePointerInfo DstPtrInfo) const {
	return SDValue();		return SDValue();
	}		}
			/// EmitTargetCodeForMemcmp - Emit target-specific code that performs a
			/// memcmp, in cases where that is faster than a libcall. The first
			/// returned SDValue is the result of the memcmp and the second is
			/// the chain. Both SDValues can be null if a normal libcall should
			/// be used.
			virtual std::pair<SDValue, SDValue>
			EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc dl,
			SDValue Chain,
			SDValue Op1, SDValue Op2,
			SDValue Op3, MachinePointerInfo Op1PtrInfo,
			MachinePointerInfo Op2PtrInfo) const {
			return std::make_pair(SDValue(), SDValue());
			}
			/// EmitTargetCodeForMemchr - Emit target-specific code that performs a
			/// memchr, in cases where that is faster than a libcall. The first
			/// returned SDValue is the result of the memchr and the second is
			/// the chain. Both SDValues can be null if a normal libcall should
			/// be used.
			virtual std::pair<SDValue, SDValue>
			EmitTargetCodeForMemchr(SelectionDAG &DAG, SDLoc dl, SDValue Chain,
			SDValue Src, SDValue Char, SDValue Length,
			MachinePointerInfo SrcPtrInfo) const {
			return std::make_pair(SDValue(), SDValue());
			}
			/// EmitTargetCodeForStrcpy - Emit target-specific code that performs a
			/// strcpy or stpcpy, in cases where that is faster than a libcall.
			/// The first returned SDValue is the result of the copy (the start
			/// of the destination string for strcpy, a pointer to the null terminato
			r
			/// for stpcpy) and the second is the chain. Both SDValues can be null
			/// if a normal libcall should be used.
			virtual std::pair<SDValue, SDValue>
			EmitTargetCodeForStrcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
			SDValue Dest, SDValue Src,
			MachinePointerInfo DestPtrInfo,
			MachinePointerInfo SrcPtrInfo,
			bool isStpcpy) const {
			return std::make_pair(SDValue(), SDValue());
			}
			/// EmitTargetCodeForStrcmp - Emit target-specific code that performs a
			/// strcmp, in cases where that is faster than a libcall. The first
			/// returned SDValue is the result of the strcmp and the second is
			/// the chain. Both SDValues can be null if a normal libcall should
			/// be used.
			virtual std::pair<SDValue, SDValue>
			EmitTargetCodeForStrcmp(SelectionDAG &DAG, SDLoc dl,
			SDValue Chain,
			SDValue Op1, SDValue Op2,
			MachinePointerInfo Op1PtrInfo,
			MachinePointerInfo Op2PtrInfo) const {
			return std::make_pair(SDValue(), SDValue());
			}
			virtual std::pair<SDValue, SDValue>
			EmitTargetCodeForStrlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
			SDValue Src, MachinePointerInfo SrcPtrInfo) const
			{
			return std::make_pair(SDValue(), SDValue());
			}
			virtual std::pair<SDValue, SDValue>
			EmitTargetCodeForStrnlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
			SDValue Src, SDValue MaxLength,
			MachinePointerInfo SrcPtrInfo) const {
			return std::make_pair(SDValue(), SDValue());
			}
	};		};
	} // end llvm namespace		} // end llvm namespace
	#endif		#endif
End of changes. 4 change blocks.
	3 lines changed or deleted		73 lines changed or added

	TargetSubtargetInfo.h		TargetSubtargetInfo.h
	skipping to change at line 28		skipping to change at line 28
	#include "llvm/Support/CodeGen.h"		#include "llvm/Support/CodeGen.h"
	namespace llvm {		namespace llvm {
	class MachineFunction;		class MachineFunction;
	class MachineInstr;		class MachineInstr;
	class SDep;		class SDep;
	class SUnit;		class SUnit;
	class TargetRegisterClass;		class TargetRegisterClass;
	class TargetSchedModel;		class TargetSchedModel;
			struct MachineSchedPolicy;
	template <typename T> class SmallVectorImpl;		template <typename T> class SmallVectorImpl;
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	///		///
	/// TargetSubtargetInfo - Generic base class for all target subtargets. Al l		/// TargetSubtargetInfo - Generic base class for all target subtargets. Al l
	/// Target-specific options that control code generation and printing shoul d		/// Target-specific options that control code generation and printing shoul d
	/// be exposed through a TargetSubtargetInfo-derived class.		/// be exposed through a TargetSubtargetInfo-derived class.
	///		///
	class TargetSubtargetInfo : public MCSubtargetInfo {		class TargetSubtargetInfo : public MCSubtargetInfo {
	TargetSubtargetInfo(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION;		TargetSubtargetInfo(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION;
	skipping to change at line 58		skipping to change at line 59
	/// Resolve a SchedClass at runtime, where SchedClass identifies an		/// Resolve a SchedClass at runtime, where SchedClass identifies an
	/// MCSchedClassDesc with the isVariant property. This may return the ID of		/// MCSchedClassDesc with the isVariant property. This may return the ID of
	/// another variant SchedClass, but repeated invocation must quickly term inate		/// another variant SchedClass, but repeated invocation must quickly term inate
	/// in a nonvariant SchedClass.		/// in a nonvariant SchedClass.
	virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInst r *MI,		virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInst r *MI,
	const TargetSchedModel* SchedModel) co nst {		const TargetSchedModel* SchedModel) co nst {
	return 0;		return 0;
	}		}
			/// \brief Temporary API to test migration to MI scheduler.
			bool useMachineScheduler() const;
	/// \brief True if the subtarget should run MachineScheduler after aggres sive		/// \brief True if the subtarget should run MachineScheduler after aggres sive
	/// coalescing.		/// coalescing.
	///		///
	/// This currently replaces the SelectionDAG scheduler with the "source" order		/// This currently replaces the SelectionDAG scheduler with the "source" order
	/// scheduler. It does not yet disable the postRA scheduler.		/// scheduler. It does not yet disable the postRA scheduler.
	virtual bool enableMachineScheduler() const;		virtual bool enableMachineScheduler() const;
			/// \brief Override generic scheduling policy within a region.
			///
			/// This is a convenient way for targets that don't provide any custom
			/// scheduling heuristics (no custom MachineSchedStrategy) to make
			/// changes to the generic scheduling policy.
			virtual void overrideSchedPolicy(MachineSchedPolicy &Policy,
			MachineInstr *begin,
			MachineInstr *end,
			unsigned NumRegionInstrs) const {}
	// enablePostRAScheduler - If the target can benefit from post-regalloc		// enablePostRAScheduler - If the target can benefit from post-regalloc
	// scheduling and the specified optimization level meets the requirement		// scheduling and the specified optimization level meets the requirement
	// return true to enable post-register-allocation scheduling. In		// return true to enable post-register-allocation scheduling. In
	// CriticalPathRCs return any register classes that should only be broken		// CriticalPathRCs return any register classes that should only be broken
	// if on the critical path.		// if on the critical path.
	virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,		virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
	AntiDepBreakMode& Mode,		AntiDepBreakMode& Mode,
	RegClassVector& CriticalPathRCs) const ;		RegClassVector& CriticalPathRCs) const ;
	// adjustSchedDependency - Perform target specific adjustments to		// adjustSchedDependency - Perform target specific adjustments to
	// the latency of a schedule dependency.		// the latency of a schedule dependency.
	virtual void adjustSchedDependency(SUnit *def, SUnit *use,		virtual void adjustSchedDependency(SUnit *def, SUnit *use,
	SDep& dep) const { }		SDep& dep) const { }
			/// \brief Enable use of alias analysis during code generation (during MI
			/// scheduling, DAGCombine, etc.).
			virtual bool useAA() const;
	/// \brief Reset the features for the subtarget.		/// \brief Reset the features for the subtarget.
	virtual void resetSubtargetFeatures(const MachineFunction *MF) { }		virtual void resetSubtargetFeatures(const MachineFunction *MF) { }
	};		};
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 4 change blocks.
	0 lines changed or deleted		18 lines changed or added

	TargetTransformInfo.h		TargetTransformInfo.h
	skipping to change at line 32		skipping to change at line 32
	#ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFO_H		#ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFO_H
	#define LLVM_ANALYSIS_TARGETTRANSFORMINFO_H		#define LLVM_ANALYSIS_TARGETTRANSFORMINFO_H
	#include "llvm/IR/Intrinsics.h"		#include "llvm/IR/Intrinsics.h"
	#include "llvm/Pass.h"		#include "llvm/Pass.h"
	#include "llvm/Support/DataTypes.h"		#include "llvm/Support/DataTypes.h"
	namespace llvm {		namespace llvm {
	class GlobalValue;		class GlobalValue;
			class Loop;
	class Type;		class Type;
	class User;		class User;
	class Value;		class Value;
	/// TargetTransformInfo - This pass provides access to the codegen		/// TargetTransformInfo - This pass provides access to the codegen
	/// interfaces that are needed for IR-level transformations.		/// interfaces that are needed for IR-level transformations.
	class TargetTransformInfo {		class TargetTransformInfo {
	protected:		protected:
	/// \brief The TTI instance one level down the stack.		/// \brief The TTI instance one level down the stack.
	///		///
	skipping to change at line 174		skipping to change at line 175
	/// The advantages are that it can inspect the SSA use graph to reason mo re		/// The advantages are that it can inspect the SSA use graph to reason mo re
	/// accurately about the cost. For example, all-constant-GEPs can often b e		/// accurately about the cost. For example, all-constant-GEPs can often b e
	/// folded into a load or other instruction, but if they are used in some		/// folded into a load or other instruction, but if they are used in some
	/// other context they may not be folded. This routine can distinguish su ch		/// other context they may not be folded. This routine can distinguish su ch
	/// cases.		/// cases.
	///		///
	/// The returned cost is defined in terms of \c TargetCostConstants, see its		/// The returned cost is defined in terms of \c TargetCostConstants, see its
	/// comments for a detailed explanation of the cost values.		/// comments for a detailed explanation of the cost values.
	virtual unsigned getUserCost(const User *U) const;		virtual unsigned getUserCost(const User *U) const;
			/// \brief hasBranchDivergence - Return true if branch divergence exists.
			/// Branch divergence has a significantly negative impact on GPU performa
			nce
			/// when threads in the same wavefront take different paths due to condit
			ional
			/// branches.
			virtual bool hasBranchDivergence() const;
	/// \brief Test whether calls to a function lower to actual program funct ion		/// \brief Test whether calls to a function lower to actual program funct ion
	/// calls.		/// calls.
	///		///
	/// The idea is to test whether the program is likely to require a 'call'		/// The idea is to test whether the program is likely to require a 'call'
	/// instruction or equivalent in order to call the given function.		/// instruction or equivalent in order to call the given function.
	///		///
	/// FIXME: It's not clear that this is a good or useful query API. Client 's		/// FIXME: It's not clear that this is a good or useful query API. Client 's
	/// should probably move to simpler cost metrics using the above.		/// should probably move to simpler cost metrics using the above.
	/// Alternatively, we could split the cost interface into distinct code-s ize		/// Alternatively, we could split the cost interface into distinct code-s ize
	/// and execution-speed costs. This would allow modelling the core of thi s		/// and execution-speed costs. This would allow modelling the core of thi s
	/// query more accurately as the a call is a single small instruction, bu t		/// query more accurately as the a call is a single small instruction, bu t
	/// incurs significant execution cost.		/// incurs significant execution cost.
	virtual bool isLoweredToCall(const Function *F) const;		virtual bool isLoweredToCall(const Function *F) const;
			/// Parameters that control the generic loop unrolling transformation.
			struct UnrollingPreferences {
			/// The cost threshold for the unrolled loop, compared to
			/// CodeMetrics.NumInsts aggregated over all basic blocks in the loop b
			ody.
			/// The unrolling factor is set such that the unrolled loop body does n
			ot
			/// exceed this cost. Set this to UINT_MAX to disable the loop body cos
			t
			/// restriction.
			unsigned Threshold;
			/// The cost threshold for the unrolled loop when optimizing for size (
			set
			/// to UINT_MAX to disable).
			unsigned OptSizeThreshold;
			/// A forced unrolling factor (the number of concatenated bodies of the
			/// original loop in the unrolled loop body). When set to 0, the unroll
			ing
			/// transformation will select an unrolling factor based on the current
			cost
			/// threshold and other factors.
			unsigned Count;
			/// Allow partial unrolling (unrolling of loops to expand the size of t
			he
			/// loop body, not only to eliminate small constant-trip-count loops).
			bool Partial;
			/// Allow runtime unrolling (unrolling of loops to expand the size of t
			he
			/// loop body even when the number of loop iterations is not known at c
			ompile
			/// time).
			bool Runtime;
			};
			/// \brief Get target-customized preferences for the generic loop unrolli
			ng
			/// transformation. The caller will initialize UP with the current
			/// target-independent defaults.
			virtual void getUnrollingPreferences(Loop *L, UnrollingPreferences &UP) c
			onst;
	/// @}		/// @}
	/// \name Scalar Target Information		/// \name Scalar Target Information
	/// @{		/// @{
	/// \brief Flags indicating the kind of support for population count.		/// \brief Flags indicating the kind of support for population count.
	///		///
	/// Compared to the SW implementation, HW support is supposed to		/// Compared to the SW implementation, HW support is supposed to
	/// significantly boost the performance when the population is dense, and it		/// significantly boost the performance when the population is dense, and it
	/// may or may not degrade performance if the population is sparse. A HW		/// may or may not degrade performance if the population is sparse. A HW
	skipping to change at line 228		skipping to change at line 265
	/// isLegalAddressingMode - Return true if the addressing mode represente d by		/// isLegalAddressingMode - Return true if the addressing mode represente d by
	/// AM is legal for this target, for a load/store of the specified type.		/// AM is legal for this target, for a load/store of the specified type.
	/// The type may be VoidTy, in which case only return true if the address ing		/// The type may be VoidTy, in which case only return true if the address ing
	/// mode is legal for a load/store of any legal type.		/// mode is legal for a load/store of any legal type.
	/// TODO: Handle pre/postinc as well.		/// TODO: Handle pre/postinc as well.
	virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,		virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
	int64_t BaseOffset, bool HasBaseReg,		int64_t BaseOffset, bool HasBaseReg,
	int64_t Scale) const;		int64_t Scale) const;
			/// \brief Return the cost of the scaling factor used in the addressing
			/// mode represented by AM for this target, for a load/store
			/// of the specified type.
			/// If the AM is supported, the return value must be >= 0.
			/// If the AM is not supported, it returns a negative value.
			/// TODO: Handle pre/postinc as well.
			virtual int getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
			int64_t BaseOffset, bool HasBaseReg,
			int64_t Scale) const;
	/// isTruncateFree - Return true if it's free to truncate a value of		/// isTruncateFree - Return true if it's free to truncate a value of
	/// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value i n		/// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value i n
	/// register EAX to i16 by referencing its sub-register AX.		/// register EAX to i16 by referencing its sub-register AX.
	virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;		virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
	/// Is this type legal.		/// Is this type legal.
	virtual bool isTypeLegal(Type *Ty) const;		virtual bool isTypeLegal(Type *Ty) const;
	/// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes		/// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
	virtual unsigned getJumpBufAlignment() const;		virtual unsigned getJumpBufAlignment() const;
	skipping to change at line 249		skipping to change at line 296
	/// getJumpBufSize - returns the target's jmp_buf size in bytes.		/// getJumpBufSize - returns the target's jmp_buf size in bytes.
	virtual unsigned getJumpBufSize() const;		virtual unsigned getJumpBufSize() const;
	/// shouldBuildLookupTables - Return true if switches should be turned in to		/// shouldBuildLookupTables - Return true if switches should be turned in to
	/// lookup tables for the target.		/// lookup tables for the target.
	virtual bool shouldBuildLookupTables() const;		virtual bool shouldBuildLookupTables() const;
	/// getPopcntSupport - Return hardware support for population count.		/// getPopcntSupport - Return hardware support for population count.
	virtual PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) cons t;		virtual PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) cons t;
			/// haveFastSqrt -- Return true if the hardware has a fast square-root
			/// instruction.
			virtual bool haveFastSqrt(Type *Ty) const;
	/// getIntImmCost - Return the expected cost of materializing the given		/// getIntImmCost - Return the expected cost of materializing the given
	/// integer immediate of the specified type.		/// integer immediate of the specified type.
	virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const;		virtual unsigned getIntImmCost(const APInt &Imm, Type *Ty) const;
	/// @}		/// @}
	/// \name Vector Target Information		/// \name Vector Target Information
	/// @{		/// @{
	/// \brief The various kinds of shuffle patterns for vector queries.		/// \brief The various kinds of shuffle patterns for vector queries.
	enum ShuffleKind {		enum ShuffleKind {
	SK_Broadcast, ///< Broadcast element 0 to all other elements.		SK_Broadcast, ///< Broadcast element 0 to all other elements.
	SK_Reverse, ///< Reverse the order of the vector.		SK_Reverse, ///< Reverse the order of the vector.
	SK_InsertSubvector, ///< InsertSubvector. Index indicates start offset.		SK_InsertSubvector, ///< InsertSubvector. Index indicates start offset.
	SK_ExtractSubvector ///< ExtractSubvector Index indicates start offset.		SK_ExtractSubvector ///< ExtractSubvector Index indicates start offset.
	};		};
	/// \brief Additonal information about an operand's possible values.		/// \brief Additional information about an operand's possible values.
	enum OperandValueKind {		enum OperandValueKind {
	OK_AnyValue, // Operand can have any value.		OK_AnyValue, // Operand can have any value.
	OK_UniformValue, // Operand is uniform (splat of a value).		OK_UniformValue, // Operand is uniform (splat of a value).
	OK_UniformConstantValue // Operand is uniform constant.		OK_UniformConstantValue // Operand is uniform constant.
	};		};
	/// \return The number of scalar or vector registers that the target has.		/// \return The number of scalar or vector registers that the target has.
	/// If 'Vectors' is true, it returns the number of vector registers. If i t is		/// If 'Vectors' is true, it returns the number of vector registers. If i t is
	/// set to false, it returns the number of scalar registers.		/// set to false, it returns the number of scalar registers.
	virtual unsigned getNumberOfRegisters(bool Vector) const;		virtual unsigned getNumberOfRegisters(bool Vector) const;
	skipping to change at line 320		skipping to change at line 371
	/// \return The expected cost of vector Insert and Extract.		/// \return The expected cost of vector Insert and Extract.
	/// Use -1 to indicate that there is no information on the index value.		/// Use -1 to indicate that there is no information on the index value.
	virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,		virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
	unsigned Index = -1) const;		unsigned Index = -1) const;
	/// \return The cost of Load and Store instructions.		/// \return The cost of Load and Store instructions.
	virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,		virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
	unsigned Alignment,		unsigned Alignment,
	unsigned AddressSpace) const;		unsigned AddressSpace) const;
			/// \brief Calculate the cost of performing a vector reduction.
			///
			/// This is the cost of reducing the vector value of type \p Ty to a scal
			ar
			/// value using the operation denoted by \p Opcode. The form of the reduc
			tion
			/// can either be a pairwise reduction or a reduction that splits the vec
			tor
			/// at every reduction level.
			///
			/// Pairwise:
			/// (v0, v1, v2, v3)
			/// ((v0+v1), (v2, v3), undef, undef)
			/// Split:
			/// (v0, v1, v2, v3)
			/// ((v0+v2), (v1+v3), undef, undef)
			virtual unsigned getReductionCost(unsigned Opcode, Type *Ty,
			bool IsPairwiseForm) const;
	/// \returns The cost of Intrinsic instructions.		/// \returns The cost of Intrinsic instructions.
	virtual unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,		virtual unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
	ArrayRef<Type *> Tys) const;		ArrayRef<Type *> Tys) const;
	/// \returns The number of pieces into which the provided type must be		/// \returns The number of pieces into which the provided type must be
	/// split during legalization. Zero is returned when the answer is unknow n.		/// split during legalization. Zero is returned when the answer is unknow n.
	virtual unsigned getNumberOfParts(Type *Tp) const;		virtual unsigned getNumberOfParts(Type *Tp) const;
	/// \returns The cost of the address computation. For most targets this c an be		/// \returns The cost of the address computation. For most targets this c an be
	/// merged into the instruction indexing mode. Some targets might want to		/// merged into the instruction indexing mode. Some targets might want to
	/// distinguish between address computation for memory operations on vect or		/// distinguish between address computation for memory operations on vect or
	/// types and scalar types. Such targets should override this function.		/// types and scalar types. Such targets should override this function.
	virtual unsigned getAddressComputationCost(Type *Ty) const;		/// The 'IsComplex' parameter is a hint that the address computation is l
			ikely
			/// to involve multiple instructions and as such unlikely to be merged in
			to
			/// the address indexing mode.
			virtual unsigned getAddressComputationCost(Type *Ty,
			bool IsComplex = false) const;
	/// @}		/// @}
	/// Analysis group identification.		/// Analysis group identification.
	static char ID;		static char ID;
	};		};
	/// \brief Create the base case instance of a pass in the TTI analysis grou p.		/// \brief Create the base case instance of a pass in the TTI analysis grou p.
	///		///
	/// This class provides the base case for the stack of TTI analyzes. It doe sn't		/// This class provides the base case for the stack of TTI analyzes. It doe sn't
End of changes. 8 change blocks.
	2 lines changed or deleted		91 lines changed or added

	Targets.def		Targets.def
	skipping to change at line 26		skipping to change at line 26
	|* The set of targets supported by LLVM is generated at configuration *|		|* The set of targets supported by LLVM is generated at configuration *|
	|* time, at which point this header is generated. Do not modify this *|		|* time, at which point this header is generated. Do not modify this *|
	|* header directly. *|		|* header directly. *|
	|* *|		|* *|
	\*===---------------------------------------------------------------------- ===*/		\*===---------------------------------------------------------------------- ===*/
	#ifndef LLVM_TARGET		#ifndef LLVM_TARGET
	# error Please define the macro LLVM_TARGET(TargetName)		# error Please define the macro LLVM_TARGET(TargetName)
	#endif		#endif
	LLVM_TARGET(SystemZ) LLVM_TARGET(Hexagon) LLVM_TARGET(NVPTX) LLVM_TARGET(MB laze) LLVM_TARGET(CppBackend) LLVM_TARGET(MSP430) LLVM_TARGET(XCore) LLVM_T ARGET(Mips) LLVM_TARGET(ARM) LLVM_TARGET(AArch64) LLVM_TARGET(PowerPC) LLVM _TARGET(Sparc) LLVM_TARGET(X86)		LLVM_TARGET(R600) LLVM_TARGET(SystemZ) LLVM_TARGET(Hexagon) LLVM_TARGET(NVP TX) LLVM_TARGET(CppBackend) LLVM_TARGET(MSP430) LLVM_TARGET(XCore) LLVM_TAR GET(Mips) LLVM_TARGET(ARM) LLVM_TARGET(AArch64) LLVM_TARGET(PowerPC) LLVM_T ARGET(Sparc) LLVM_TARGET(X86)
	#undef LLVM_TARGET		#undef LLVM_TARGET
End of changes. 1 change blocks.
	1 lines changed or deleted		1 lines changed or added

	TimeValue.h		TimeValue.h
	skipping to change at line 256		skipping to change at line 256
	}		}
	/// Converts the TimeValue into the corresponding number of seconds		/// Converts the TimeValue into the corresponding number of seconds
	/// since the epoch (00:00:00 Jan 1,1970).		/// since the epoch (00:00:00 Jan 1,1970).
	uint64_t toEpochTime() const {		uint64_t toEpochTime() const {
	return seconds_ - PosixZeroTimeSeconds;		return seconds_ - PosixZeroTimeSeconds;
	}		}
	/// Converts the TimeValue into the corresponding number of "ticks" for		/// Converts the TimeValue into the corresponding number of "ticks" for
	/// Win32 platforms, correcting for the difference in Win32 zero time.		/// Win32 platforms, correcting for the difference in Win32 zero time.
	/// @brief Convert to windows time (seconds since 12:00:00a Jan 1, 1601		/// @brief Convert to Win32's FILETIME
	)		/// (100ns intervals since 00:00:00 Jan 1, 1601 UTC)
	uint64_t toWin32Time() const {		uint64_t toWin32Time() const {
	uint64_t result = seconds_ - Win32ZeroTimeSeconds;		uint64_t result = (uint64_t)10000000 * (seconds_ - Win32ZeroTimeSecon ds);
	result += nanos_ / NANOSECONDS_PER_WIN32_TICK;		result += nanos_ / NANOSECONDS_PER_WIN32_TICK;
	return result;		return result;
	}		}
	/// Provides the seconds and nanoseconds as results in its arguments af ter		/// Provides the seconds and nanoseconds as results in its arguments af ter
	/// correction for the Posix zero time.		/// correction for the Posix zero time.
	/// @brief Convert to timespec time (ala POSIX.1b)		/// @brief Convert to timespec time (ala POSIX.1b)
	void getTimespecTime( uint64_t& seconds, uint32_t& nanos ) const {		void getTimespecTime( uint64_t& seconds, uint32_t& nanos ) const {
	seconds = seconds_ - PosixZeroTimeSeconds;		seconds = seconds_ - PosixZeroTimeSeconds;
	nanos = nanos_;		nanos = nanos_;
End of changes. 2 change blocks.
	3 lines changed or deleted		3 lines changed or added

	ToolOutputFile.h		ToolOutputFile.h
	skipping to change at line 50		skipping to change at line 50
	} Installer;		} Installer;
	/// OS - The contained stream. This is intentionally declared after		/// OS - The contained stream. This is intentionally declared after
	/// Installer.		/// Installer.
	raw_fd_ostream OS;		raw_fd_ostream OS;
	public:		public:
	/// tool_output_file - This constructor's arguments are passed to		/// tool_output_file - This constructor's arguments are passed to
	/// to raw_fd_ostream's constructor.		/// to raw_fd_ostream's constructor.
	tool_output_file(const char *filename, std::string &ErrorInfo,		tool_output_file(const char *filename, std::string &ErrorInfo,
	unsigned Flags = 0);		sys::fs::OpenFlags Flags = sys::fs::F_None);
			tool_output_file(const char *Filename, int FD);
	/// os - Return the contained raw_fd_ostream.		/// os - Return the contained raw_fd_ostream.
	raw_fd_ostream &os() { return OS; }		raw_fd_ostream &os() { return OS; }
	/// keep - Indicate that the tool's job wrt this output file has been		/// keep - Indicate that the tool's job wrt this output file has been
	/// successful and the file should not be deleted.		/// successful and the file should not be deleted.
	void keep() { Installer.Keep = true; }		void keep() { Installer.Keep = true; }
	};		};
	} // end llvm namespace		} // end llvm namespace
End of changes. 1 change blocks.
	1 lines changed or deleted		3 lines changed or added

	Triple.h		Triple.h
	skipping to change at line 17		skipping to change at line 17
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_ADT_TRIPLE_H		#ifndef LLVM_ADT_TRIPLE_H
	#define LLVM_ADT_TRIPLE_H		#define LLVM_ADT_TRIPLE_H
	#include "llvm/ADT/Twine.h"		#include "llvm/ADT/Twine.h"
	// Some system headers or GCC predefined macros conflict with identifiers i n		// Some system headers or GCC predefined macros conflict with identifiers i n
	// this file. Undefine them here.		// this file. Undefine them here.
			#undef NetBSD
	#undef mips		#undef mips
	#undef sparc		#undef sparc
	namespace llvm {		namespace llvm {
	/// Triple - Helper class for working with target triples.		/// Triple - Helper class for working with autoconf configuration names. Fo
			r
			/// historical reasons, we also call these 'triples' (they used to contain
			/// exactly three fields).
	///		///
	/// Target triples are strings in the canonical form:		/// Configuration names are strings in the canonical form:
	/// ARCHITECTURE-VENDOR-OPERATING_SYSTEM		/// ARCHITECTURE-VENDOR-OPERATING_SYSTEM
	/// or		/// or
	/// ARCHITECTURE-VENDOR-OPERATING_SYSTEM-ENVIRONMENT		/// ARCHITECTURE-VENDOR-OPERATING_SYSTEM-ENVIRONMENT
	///		///
	/// This class is used for clients which want to support arbitrary		/// This class is used for clients which want to support arbitrary
	/// target triples, but also want to implement certain special		/// configuration names, but also want to implement certain special
	/// behavior for particular targets. This class isolates the mapping		/// behavior for particular configurations. This class isolates the mapping
	/// from the components of the target triple to well known IDs.		/// from the components of the configuration name to well known IDs.
	///		///
	/// At its core the Triple class is designed to be a wrapper for a triple		/// At its core the Triple class is designed to be a wrapper for a triple
	/// string; the constructor does not change or normalize the triple string.		/// string; the constructor does not change or normalize the triple string.
	/// Clients that need to handle the non-canonical triples that users often		/// Clients that need to handle the non-canonical triples that users often
	/// specify should use the normalize method.		/// specify should use the normalize method.
	///		///
	/// See autoconf/config.guess for a glimpse into what triples look like in		/// See autoconf/config.guess for a glimpse into what configuration names
	/// practice.		/// look like in practice.
	class Triple {		class Triple {
	public:		public:
	enum ArchType {		enum ArchType {
	UnknownArch,		UnknownArch,
	arm, // ARM: arm, armv.*, xscale		arm, // ARM: arm, armv.*, xscale
	aarch64, // AArch64: aarch64		aarch64, // AArch64: aarch64
	hexagon, // Hexagon: hexagon		hexagon, // Hexagon: hexagon
	mips, // MIPS: mips, mipsallegrex		mips, // MIPS: mips, mipsallegrex
	mipsel, // MIPSEL: mipsel, mipsallegrexel		mipsel, // MIPSEL: mipsel, mipsallegrexel
	mips64, // MIPS64: mips64		mips64, // MIPS64: mips64
	mips64el,// MIPS64EL: mips64el		mips64el,// MIPS64EL: mips64el
	msp430, // MSP430: msp430		msp430, // MSP430: msp430
	ppc, // PPC: powerpc		ppc, // PPC: powerpc
	ppc64, // PPC64: powerpc64, ppu		ppc64, // PPC64: powerpc64, ppu
			ppc64le, // PPC64LE: powerpc64le
	r600, // R600: AMD GPUs HD2XXX - HD6XXX		r600, // R600: AMD GPUs HD2XXX - HD6XXX
	sparc, // Sparc: sparc		sparc, // Sparc: sparc
	sparcv9, // Sparcv9: Sparcv9		sparcv9, // Sparcv9: Sparcv9
	systemz, // SystemZ: s390x		systemz, // SystemZ: s390x
	tce, // TCE (http://tce.cs.tut.fi/): tce		tce, // TCE (http://tce.cs.tut.fi/): tce
	thumb, // Thumb: thumb, thumbv.*		thumb, // Thumb: thumb, thumbv.*
	x86, // X86: i[3-9]86		x86, // X86: i[3-9]86
	x86_64, // X86-64: amd64, x86_64		x86_64, // X86-64: amd64, x86_64
	xcore, // XCore: xcore		xcore, // XCore: xcore
	mblaze, // MBlaze: mblaze
	nvptx, // NVPTX: 32-bit		nvptx, // NVPTX: 32-bit
	nvptx64, // NVPTX: 64-bit		nvptx64, // NVPTX: 64-bit
	le32, // le32: generic little-endian 32-bit CPU (PNaCl / Emscripten)		le32, // le32: generic little-endian 32-bit CPU (PNaCl / Emscripten)
	amdil, // amdil: amd IL		amdil, // amdil: amd IL
	spir, // SPIR: standard portable IR for OpenCL 32-bit version		spir, // SPIR: standard portable IR for OpenCL 32-bit version
	spir64 // SPIR: standard portable IR for OpenCL 64-bit version		spir64 // SPIR: standard portable IR for OpenCL 64-bit version
	};		};
	enum VendorType {		enum VendorType {
	UnknownVendor,		UnknownVendor,
	Apple,		Apple,
	PC,		PC,
	SCEI,		SCEI,
	BGP,		BGP,
	BGQ,		BGQ,
	Freescale,		Freescale,
	IBM		IBM,
			NVIDIA
	};		};
	enum OSType {		enum OSType {
	UnknownOS,		UnknownOS,
	AuroraUX,		AuroraUX,
	Cygwin,		Cygwin,
	Darwin,		Darwin,
	DragonFly,		DragonFly,
	FreeBSD,		FreeBSD,
	IOS,		IOS,
	skipping to change at line 108		skipping to change at line 112
	NetBSD,		NetBSD,
	OpenBSD,		OpenBSD,
	Solaris,		Solaris,
	Win32,		Win32,
	Haiku,		Haiku,
	Minix,		Minix,
	RTEMS,		RTEMS,
	NaCl, // Native Client		NaCl, // Native Client
	CNK, // BG/P Compute-Node Kernel		CNK, // BG/P Compute-Node Kernel
	Bitrig,		Bitrig,
	AIX		AIX,
			CUDA, // NVIDIA CUDA
			NVCL // NVIDIA OpenCL
	};		};
	enum EnvironmentType {		enum EnvironmentType {
	UnknownEnvironment,		UnknownEnvironment,
	GNU,		GNU,
	GNUEABI,		GNUEABI,
	GNUEABIHF,		GNUEABIHF,
	GNUX32,		GNUX32,
	EABI,		EABI,
	MachO,		MachO,
	skipping to change at line 316		skipping to change at line 322
	/// isOSDarwin - Is this a "Darwin" OS (OS X or iOS).		/// isOSDarwin - Is this a "Darwin" OS (OS X or iOS).
	bool isOSDarwin() const {		bool isOSDarwin() const {
	return isMacOSX() || isiOS();		return isMacOSX() || isiOS();
	}		}
	/// \brief Tests for either Cygwin or MinGW OS		/// \brief Tests for either Cygwin or MinGW OS
	bool isOSCygMing() const {		bool isOSCygMing() const {
	return getOS() == Triple::Cygwin || getOS() == Triple::MinGW32;		return getOS() == Triple::Cygwin || getOS() == Triple::MinGW32;
	}		}
	/// isOSWindows - Is this a "Windows" OS.		/// \brief Is this a "Windows" OS targeting a "MSVCRT.dll" environment.
			bool isOSMSVCRT() const {
			return getOS() == Triple::Win32 || getOS() == Triple::MinGW32;
			}
			/// \brief Tests whether the OS is Windows.
	bool isOSWindows() const {		bool isOSWindows() const {
	return getOS() == Triple::Win32 || isOSCygMing();		return getOS() == Triple::Win32 || isOSCygMing();
	}		}
	/// \brief Tests whether the OS is NaCl (Native Client)		/// \brief Tests whether the OS is NaCl (Native Client)
	bool isOSNaCl() const {		bool isOSNaCl() const {
	return getOS() == Triple::NaCl;		return getOS() == Triple::NaCl;
	}		}
			/// \brief Tests whether the OS is Linux.
			bool isOSLinux() const {
			return getOS() == Triple::Linux;
			}
	/// \brief Tests whether the OS uses the ELF binary format.		/// \brief Tests whether the OS uses the ELF binary format.
	bool isOSBinFormatELF() const {		bool isOSBinFormatELF() const {
	return !isOSDarwin() && !isOSWindows();		return !isOSDarwin() && !isOSWindows();
	}		}
	/// \brief Tests whether the OS uses the COFF binary format.		/// \brief Tests whether the OS uses the COFF binary format.
	bool isOSBinFormatCOFF() const {		bool isOSBinFormatCOFF() const {
	return isOSWindows();		return isOSWindows();
	}		}
End of changes. 11 change blocks.
	11 lines changed or deleted		28 lines changed or added

	Type.h		Type.h
	skipping to change at line 327		skipping to change at line 327
	const Type *getScalarType() const;		const Type *getScalarType() const;
	Type *getScalarType();		Type *getScalarType();
	//===-------------------------------------------------------------------- ===//		//===-------------------------------------------------------------------- ===//
	// Type Iteration support.		// Type Iteration support.
	//		//
	typedef Type * const *subtype_iterator;		typedef Type * const *subtype_iterator;
	subtype_iterator subtype_begin() const { return ContainedTys; }		subtype_iterator subtype_begin() const { return ContainedTys; }
	subtype_iterator subtype_end() const { return &ContainedTys[NumContainedT ys];}		subtype_iterator subtype_end() const { return &ContainedTys[NumContainedT ys];}
			typedef std::reverse_iterator<subtype_iterator> subtype_reverse_iterator;
			subtype_reverse_iterator subtype_rbegin() const {
			return subtype_reverse_iterator(subtype_end());
			}
			subtype_reverse_iterator subtype_rend() const {
			return subtype_reverse_iterator(subtype_begin());
			}
	/// getContainedType - This method is used to implement the type iterator		/// getContainedType - This method is used to implement the type iterator
	/// (defined a the end of the file). For derived types, this returns the		/// (defined a the end of the file). For derived types, this returns the
	/// types 'contained' in the derived type.		/// types 'contained' in the derived type.
	///		///
	Type *getContainedType(unsigned i) const {		Type *getContainedType(unsigned i) const {
	assert(i < NumContainedTys && "Index out of range!");		assert(i < NumContainedTys && "Index out of range!");
	return ContainedTys[i];		return ContainedTys[i];
	}		}
	/// getNumContainedTypes - Return the number of types in the derived type .		/// getNumContainedTypes - Return the number of types in the derived type .
End of changes. 1 change blocks.
	0 lines changed or deleted		8 lines changed or added

	TypeBuilder.h		TypeBuilder.h
	skipping to change at line 20		skipping to change at line 20
	// This file defines the TypeBuilder class, which is used as a convenient w ay to		// This file defines the TypeBuilder class, which is used as a convenient w ay to
	// create LLVM types with a consistent and simplified interface.		// create LLVM types with a consistent and simplified interface.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_IR_TYPEBUILDER_H		#ifndef LLVM_IR_TYPEBUILDER_H
	#define LLVM_IR_TYPEBUILDER_H		#define LLVM_IR_TYPEBUILDER_H
	#include "llvm/IR/DerivedTypes.h"		#include "llvm/IR/DerivedTypes.h"
	#include "llvm/IR/LLVMContext.h"		#include "llvm/IR/LLVMContext.h"
	#include <limits.h>		#include <climits>
	namespace llvm {		namespace llvm {
	/// TypeBuilder - This provides a uniform API for looking up types		/// TypeBuilder - This provides a uniform API for looking up types
	/// known at compile time. To support cross-compilation, we define a		/// known at compile time. To support cross-compilation, we define a
	/// series of tag types in the llvm::types namespace, like i<N>,		/// series of tag types in the llvm::types namespace, like i<N>,
	/// ieee_float, ppc_fp128, etc. TypeBuilder<T, false> allows T to be		/// ieee_float, ppc_fp128, etc. TypeBuilder<T, false> allows T to be
	/// any of these, a native C type (whose size may depend on the host		/// any of these, a native C type (whose size may depend on the host
	/// compiler), or a pointer, function, or struct type built out of		/// compiler), or a pointer, function, or struct type built out of
	/// these. TypeBuilder<T, true> removes native C types from this set		/// these. TypeBuilder<T, true> removes native C types from this set
End of changes. 1 change blocks.
	1 lines changed or deleted		1 lines changed or added

	UnifyFunctionExitNodes.h		UnifyFunctionExitNodes.h
	skipping to change at line 37		skipping to change at line 37
	public:		public:
	static char ID; // Pass identification, replacement for typeid		static char ID; // Pass identification, replacement for typeid
	UnifyFunctionExitNodes() : FunctionPass(ID),		UnifyFunctionExitNodes() : FunctionPass(ID),
	ReturnBlock(0), UnwindBlock(0) {		ReturnBlock(0), UnwindBlock(0) {
	initializeUnifyFunctionExitNodesPass(*PassRegistry::getPassRegistry());		initializeUnifyFunctionExitNodesPass(*PassRegistry::getPassRegistry());
	}		}
	// We can preserve non-critical-edgeness when we unify function exit node s		// We can preserve non-critical-edgeness when we unify function exit node s
	virtual void getAnalysisUsage(AnalysisUsage &AU) const;		virtual void getAnalysisUsage(AnalysisUsage &AU) const;
	// getReturn|Unwind|UnreachableBlock - Return the new single (or nonexist ant)		// getReturn|Unwind|UnreachableBlock - Return the new single (or nonexist ent)
	// return, unwind, or unreachable basic blocks in the CFG.		// return, unwind, or unreachable basic blocks in the CFG.
	//		//
	BasicBlock *getReturnBlock() const { return ReturnBlock; }		BasicBlock *getReturnBlock() const { return ReturnBlock; }
	BasicBlock *getUnwindBlock() const { return UnwindBlock; }		BasicBlock *getUnwindBlock() const { return UnwindBlock; }
	BasicBlock *getUnreachableBlock() const { return UnreachableBlock; }		BasicBlock *getUnreachableBlock() const { return UnreachableBlock; }
	virtual bool runOnFunction(Function &F);		virtual bool runOnFunction(Function &F);
	};		};
	Pass *createUnifyFunctionExitNodesPass();		Pass *createUnifyFunctionExitNodesPass();
End of changes. 1 change blocks.
	1 lines changed or deleted		1 lines changed or added

	Use.h		Use.h
	skipping to change at line 177		skipping to change at line 177
	typedef std::iterator<std::forward_iterator_tag, UserTy*, ptrdiff_t> supe r;		typedef std::iterator<std::forward_iterator_tag, UserTy*, ptrdiff_t> supe r;
	typedef value_use_iterator<UserTy> _Self;		typedef value_use_iterator<UserTy> _Self;
	Use *U;		Use *U;
	explicit value_use_iterator(Use *u) : U(u) {}		explicit value_use_iterator(Use *u) : U(u) {}
	friend class Value;		friend class Value;
	public:		public:
	typedef typename super::reference reference;		typedef typename super::reference reference;
	typedef typename super::pointer pointer;		typedef typename super::pointer pointer;
	value_use_iterator(const _Self &I) : U(I.U) {}
	value_use_iterator() {}		value_use_iterator() {}
	bool operator==(const _Self &x) const {		bool operator==(const _Self &x) const {
	return U == x.U;		return U == x.U;
	}		}
	bool operator!=(const _Self &x) const {		bool operator!=(const _Self &x) const {
	return !operator==(x);		return !operator==(x);
	}		}
	/// atEnd - return true if this iterator is equal to use_end() on the val ue.		/// atEnd - return true if this iterator is equal to use_end() on the val ue.
End of changes. 1 change blocks.
	1 lines changed or deleted		0 lines changed or added

	Valgrind.h		Valgrind.h
	skipping to change at line 16		skipping to change at line 16
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// Methods for communicating with a valgrind instance this program is runni ng		// Methods for communicating with a valgrind instance this program is runni ng
	// under. These are all no-ops unless LLVM was configured on a system with the		// under. These are all no-ops unless LLVM was configured on a system with the
	// valgrind headers installed and valgrind is controlling this process.		// valgrind headers installed and valgrind is controlling this process.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_SYSTEM_VALGRIND_H		#ifndef LLVM_SUPPORT_VALGRIND_H
	#define LLVM_SYSTEM_VALGRIND_H		#define LLVM_SUPPORT_VALGRIND_H
	#include "llvm/Config/llvm-config.h"		#include "llvm/Config/llvm-config.h"
	#include "llvm/Support/Compiler.h"		#include "llvm/Support/Compiler.h"
	#include <stddef.h>		#include <stddef.h>
	#if LLVM_ENABLE_THREADS != 0 && !defined(NDEBUG)		#if LLVM_ENABLE_THREADS != 0 && !defined(NDEBUG)
	// tsan (Thread Sanitizer) is a valgrind-based tool that detects these exac t		// tsan (Thread Sanitizer) is a valgrind-based tool that detects these exac t
	// functions by name.		// functions by name.
	extern "C" {		extern "C" {
	LLVM_ATTRIBUTE_WEAK void AnnotateHappensAfter(const char *file, int line,		LLVM_ATTRIBUTE_WEAK void AnnotateHappensAfter(const char *file, int line,
End of changes. 1 change blocks.
	2 lines changed or deleted		2 lines changed or added

	Value.h		Value.h
	skipping to change at line 25		skipping to change at line 25
	#define LLVM_IR_VALUE_H		#define LLVM_IR_VALUE_H
	#include "llvm/IR/Use.h"		#include "llvm/IR/Use.h"
	#include "llvm/Support/Casting.h"		#include "llvm/Support/Casting.h"
	#include "llvm/Support/CBindingWrapping.h"		#include "llvm/Support/CBindingWrapping.h"
	#include "llvm/Support/Compiler.h"		#include "llvm/Support/Compiler.h"
	#include "llvm-c/Core.h"		#include "llvm-c/Core.h"
	namespace llvm {		namespace llvm {
	class Constant;		class APInt;
	class Argument;		class Argument;
	class Instruction;		class AssemblyAnnotationWriter;
	class BasicBlock;		class BasicBlock;
	class GlobalValue;		class Constant;
			class DataLayout;
	class Function;		class Function;
	class GlobalVariable;
	class GlobalAlias;		class GlobalAlias;
			class GlobalValue;
			class GlobalVariable;
	class InlineAsm;		class InlineAsm;
	class ValueSymbolTable;		class Instruction;
	template<typename ValueTy> class StringMapEntry;
	typedef StringMapEntry<Value*> ValueName;
	class raw_ostream;
	class AssemblyAnnotationWriter;
	class ValueHandleBase;
	class LLVMContext;		class LLVMContext;
	class Twine;
	class MDNode;		class MDNode;
	class Type;
	class StringRef;		class StringRef;
			class Twine;
			class Type;
			class ValueHandleBase;
			class ValueSymbolTable;
			class raw_ostream;
			template<typename ValueTy> class StringMapEntry;
			typedef StringMapEntry<Value*> ValueName;
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	// Value Class		// Value Class
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	/// This is a very important LLVM class. It is the base class of all values		/// This is a very important LLVM class. It is the base class of all values
	/// computed by a program that may be used as operands to other values. Val ue is		/// computed by a program that may be used as operands to other values. Val ue is
	/// the super class of other important classes such as Instruction and Func tion.		/// the super class of other important classes such as Instruction and Func tion.
	/// All Values have a Type. Type is not a subclass of Value. Some values ca n		/// All Values have a Type. Type is not a subclass of Value. Some values ca n
	/// have a name and they belong to some Module. Setting the name on the Va lue		/// have a name and they belong to some Module. Setting the name on the Va lue
	skipping to change at line 262		skipping to change at line 265
	/// intersectOptionalDataWith - Clear any optional flags in this value		/// intersectOptionalDataWith - Clear any optional flags in this value
	/// that are not also set in the given value.		/// that are not also set in the given value.
	void intersectOptionalDataWith(const Value *V) {		void intersectOptionalDataWith(const Value *V) {
	SubclassOptionalData &= V->SubclassOptionalData;		SubclassOptionalData &= V->SubclassOptionalData;
	}		}
	/// hasValueHandle - Return true if there is a value handle associated wi th		/// hasValueHandle - Return true if there is a value handle associated wi th
	/// this value.		/// this value.
	bool hasValueHandle() const { return HasValueHandle; }		bool hasValueHandle() const { return HasValueHandle; }
	/// \brief This method strips off any unneeded pointer casts,		/// \brief Strips off any unneeded pointer casts, all-zero GEPs and alias
	/// all-zero GEPs and aliases from the specified value, returning the ori		es
	ginal		/// from the specified value, returning the original uncasted value.
	/// uncasted value. If this is called on a non-pointer value, it returns		///
	/// 'this'.		/// If this is called on a non-pointer value, it returns 'this'.
	Value *stripPointerCasts();		Value *stripPointerCasts();
	const Value *stripPointerCasts() const {		const Value *stripPointerCasts() const {
	return const_cast<Value*>(this)->stripPointerCasts();		return const_cast<Value*>(this)->stripPointerCasts();
	}		}
	/// \brief This method strips off any unneeded pointer casts and		/// \brief Strips off any unneeded pointer casts and all-zero GEPs from t
	/// all-zero GEPs from the specified value, returning the original		he
	/// uncasted value. If this is called on a non-pointer value, it returns		/// specified value, returning the original uncasted value.
	/// 'this'.		///
			/// If this is called on a non-pointer value, it returns 'this'.
	Value *stripPointerCastsNoFollowAliases();		Value *stripPointerCastsNoFollowAliases();
	const Value *stripPointerCastsNoFollowAliases() const {		const Value *stripPointerCastsNoFollowAliases() const {
	return const_cast<Value*>(this)->stripPointerCastsNoFollowAliases();		return const_cast<Value*>(this)->stripPointerCastsNoFollowAliases();
	}		}
	/// stripInBoundsConstantOffsets - This method strips off unneeded pointe		/// \brief Strips off unneeded pointer casts and all-constant GEPs from t
	r casts and		he
	/// all-constant GEPs from the specified value, returning the original		/// specified value, returning the original pointer value.
	/// pointer value. If this is called on a non-pointer value, it returns		///
	/// 'this'.		/// If this is called on a non-pointer value, it returns 'this'.
	Value *stripInBoundsConstantOffsets();		Value *stripInBoundsConstantOffsets();
	const Value *stripInBoundsConstantOffsets() const {		const Value *stripInBoundsConstantOffsets() const {
	return const_cast<Value*>(this)->stripInBoundsConstantOffsets();		return const_cast<Value*>(this)->stripInBoundsConstantOffsets();
	}		}
	/// stripInBoundsOffsets - This method strips off unneeded pointer casts		/// \brief Strips like \c stripInBoundsConstantOffsets but also accumulat
	and		es
	/// any in-bounds Offsets from the specified value, returning the origina		/// the constant offset stripped.
	l		///
	/// pointer value. If this is called on a non-pointer value, it returns		/// Stores the resulting constant offset stripped into the APInt provided
	/// 'this'.		.
			/// The provided APInt will be extended or truncated as needed to be the
			/// correct bitwidth for an offset of this pointer type.
			///
			/// If this is called on a non-pointer value, it returns 'this'.
			Value *stripAndAccumulateInBoundsConstantOffsets(const DataLayout &DL,
			APInt &Offset);
			const Value *stripAndAccumulateInBoundsConstantOffsets(const DataLayout &
			DL,
			APInt &Offset) con
			st {
			return const_cast<Value *>(this)
			->stripAndAccumulateInBoundsConstantOffsets(DL, Offset);
			}
			/// \brief Strips off unneeded pointer casts and any in-bounds offsets fr
			om
			/// the specified value, returning the original pointer value.
			///
			/// If this is called on a non-pointer value, it returns 'this'.
	Value *stripInBoundsOffsets();		Value *stripInBoundsOffsets();
	const Value *stripInBoundsOffsets() const {		const Value *stripInBoundsOffsets() const {
	return const_cast<Value*>(this)->stripInBoundsOffsets();		return const_cast<Value*>(this)->stripInBoundsOffsets();
	}		}
	/// isDereferenceablePointer - Test if this value is always a pointer to		/// isDereferenceablePointer - Test if this value is always a pointer to
	/// allocated and suitably aligned memory for a simple load or store.		/// allocated and suitably aligned memory for a simple load or store.
	bool isDereferenceablePointer() const;		bool isDereferenceablePointer() const;
	/// DoPHITranslation - If this value is a PHI node with CurBB as its pare nt,		/// DoPHITranslation - If this value is a PHI node with CurBB as its pare nt,
End of changes. 13 change blocks.
	32 lines changed or deleted		55 lines changed or added

	ValueHandle.h		ValueHandle.h
	skipping to change at line 341		skipping to change at line 341
	ValueTy &operator*() const { return *getValPtr(); }		ValueTy &operator*() const { return *getValPtr(); }
	};		};
	/// CallbackVH - This is a value handle that allows subclasses to define		/// CallbackVH - This is a value handle that allows subclasses to define
	/// callbacks that run when the underlying Value has RAUW called on it or i s		/// callbacks that run when the underlying Value has RAUW called on it or i s
	/// destroyed. This class can be used as the key of a map, as long as the user		/// destroyed. This class can be used as the key of a map, as long as the user
	/// takes it out of the map before calling setValPtr() (since the map has t o		/// takes it out of the map before calling setValPtr() (since the map has t o
	/// rearrange itself when the pointer changes). Unlike ValueHandleBase, th is		/// rearrange itself when the pointer changes). Unlike ValueHandleBase, th is
	/// class has a vtable and a virtual destructor.		/// class has a vtable and a virtual destructor.
	class CallbackVH : public ValueHandleBase {		class CallbackVH : public ValueHandleBase {
			virtual void anchor();
	protected:		protected:
	CallbackVH(const CallbackVH &RHS)		CallbackVH(const CallbackVH &RHS)
	: ValueHandleBase(Callback, RHS) {}		: ValueHandleBase(Callback, RHS) {}
	virtual ~CallbackVH() {}		virtual ~CallbackVH() {}
	void setValPtr(Value *P) {		void setValPtr(Value *P) {
	ValueHandleBase::operator=(P);		ValueHandleBase::operator=(P);
	}		}
	skipping to change at line 367		skipping to change at line 368
	}		}
	/// Called when this->getValPtr() is destroyed, inside ~Value(), so you m ay		/// Called when this->getValPtr() is destroyed, inside ~Value(), so you m ay
	/// call any non-virtual Value method on getValPtr(), but no subclass met hods.		/// call any non-virtual Value method on getValPtr(), but no subclass met hods.
	/// If WeakVH were implemented as a CallbackVH, it would use this method to		/// If WeakVH were implemented as a CallbackVH, it would use this method to
	/// call setValPtr(NULL). AssertingVH would use this method to cause an		/// call setValPtr(NULL). AssertingVH would use this method to cause an
	/// assertion failure.		/// assertion failure.
	///		///
	/// All implementations must remove the reference from this object to the		/// All implementations must remove the reference from this object to the
	/// Value that's being destroyed.		/// Value that's being destroyed.
	virtual void deleted();		virtual void deleted() { setValPtr(NULL); }
	/// Called when this->getValPtr()->replaceAllUsesWith(new_value) is calle d,		/// Called when this->getValPtr()->replaceAllUsesWith(new_value) is calle d,
	/// _before_ any of the uses have actually been replaced. If WeakVH were		/// _before_ any of the uses have actually been replaced. If WeakVH were
	/// implemented as a CallbackVH, it would use this method to call		/// implemented as a CallbackVH, it would use this method to call
	/// setValPtr(new_value). AssertingVH would do nothing in this method.		/// setValPtr(new_value). AssertingVH would do nothing in this method.
	virtual void allUsesReplacedWith(Value *);		virtual void allUsesReplacedWith(Value *) {}
	};		};
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 3 change blocks.
	2 lines changed or deleted		3 lines changed or added

	ValueMapper.h		ValueMapper.h
	skipping to change at line 37		skipping to change at line 37
	class ValueMapTypeRemapper {		class ValueMapTypeRemapper {
	virtual void anchor(); // Out of line method.		virtual void anchor(); // Out of line method.
	public:		public:
	virtual ~ValueMapTypeRemapper() {}		virtual ~ValueMapTypeRemapper() {}
	/// remapType - The client should implement this method if they want to		/// remapType - The client should implement this method if they want to
	/// remap types while mapping values.		/// remap types while mapping values.
	virtual Type *remapType(Type *SrcTy) = 0;		virtual Type *remapType(Type *SrcTy) = 0;
	};		};
			/// ValueMaterializer - This is a class that can be implemented by client
			s
			/// to materialize Values on demand.
			class ValueMaterializer {
			virtual void anchor(); // Out of line method.
			public:
			virtual ~ValueMaterializer() {}
			/// materializeValueFor - The client should implement this method if th
			ey
			/// want to generate a mapped Value on demand. For example, if linking
			/// lazily.
			virtual Value *materializeValueFor(Value *V) = 0;
			};
	/// RemapFlags - These are flags that the value mapping APIs allow.		/// RemapFlags - These are flags that the value mapping APIs allow.
	enum RemapFlags {		enum RemapFlags {
	RF_None = 0,		RF_None = 0,
	/// RF_NoModuleLevelChanges - If this flag is set, the remapper knows t hat		/// RF_NoModuleLevelChanges - If this flag is set, the remapper knows t hat
	/// only local values within a function (such as an instruction or argu ment)		/// only local values within a function (such as an instruction or argu ment)
	/// are mapped, not global values like functions and global metadata.		/// are mapped, not global values like functions and global metadata.
	RF_NoModuleLevelChanges = 1,		RF_NoModuleLevelChanges = 1,
	/// RF_IgnoreMissingEntries - If this flag is set, the remapper ignores		/// RF_IgnoreMissingEntries - If this flag is set, the remapper ignores
	skipping to change at line 58		skipping to change at line 71
	/// operand is asked to be remapped which doesn't exist in the mapping.		/// operand is asked to be remapped which doesn't exist in the mapping.
	RF_IgnoreMissingEntries = 2		RF_IgnoreMissingEntries = 2
	};		};
	static inline RemapFlags operator|(RemapFlags LHS, RemapFlags RHS) {		static inline RemapFlags operator|(RemapFlags LHS, RemapFlags RHS) {
	return RemapFlags(unsigned(LHS)|unsigned(RHS));		return RemapFlags(unsigned(LHS)|unsigned(RHS));
	}		}
	Value *MapValue(const Value *V, ValueToValueMapTy &VM,		Value *MapValue(const Value *V, ValueToValueMapTy &VM,
	RemapFlags Flags = RF_None,		RemapFlags Flags = RF_None,
	ValueMapTypeRemapper *TypeMapper = 0);		ValueMapTypeRemapper *TypeMapper = 0,
			ValueMaterializer *Materializer = 0);
	void RemapInstruction(Instruction *I, ValueToValueMapTy &VM,		void RemapInstruction(Instruction *I, ValueToValueMapTy &VM,
	RemapFlags Flags = RF_None,		RemapFlags Flags = RF_None,
	ValueMapTypeRemapper *TypeMapper = 0);		ValueMapTypeRemapper *TypeMapper = 0,
			ValueMaterializer *Materializer = 0);
	/// MapValue - provide versions that preserve type safety for MDNode and		/// MapValue - provide versions that preserve type safety for MDNode and
	/// Constants.		/// Constants.
	inline MDNode *MapValue(const MDNode *V, ValueToValueMapTy &VM,		inline MDNode *MapValue(const MDNode *V, ValueToValueMapTy &VM,
	RemapFlags Flags = RF_None,		RemapFlags Flags = RF_None,
	ValueMapTypeRemapper *TypeMapper = 0) {		ValueMapTypeRemapper *TypeMapper = 0,
	return cast<MDNode>(MapValue((const Value*)V, VM, Flags, TypeMapper));		ValueMaterializer *Materializer = 0) {
			return cast<MDNode>(MapValue((const Value*)V, VM, Flags, TypeMapper,
			Materializer));
	}		}
	inline Constant *MapValue(const Constant *V, ValueToValueMapTy &VM,		inline Constant *MapValue(const Constant *V, ValueToValueMapTy &VM,
	RemapFlags Flags = RF_None,		RemapFlags Flags = RF_None,
	ValueMapTypeRemapper *TypeMapper = 0) {		ValueMapTypeRemapper *TypeMapper = 0,
	return cast<Constant>(MapValue((const Value*)V, VM, Flags, TypeMapper))		ValueMaterializer *Materializer = 0) {
	;		return cast<Constant>(MapValue((const Value*)V, VM, Flags, TypeMapper,
			Materializer));
	}		}
	} // End llvm namespace		} // End llvm namespace
	#endif		#endif
End of changes. 5 change blocks.
	7 lines changed or deleted		27 lines changed or added

	ValueTracking.h		ValueTracking.h
	skipping to change at line 28		skipping to change at line 28
	#include "llvm/ADT/ArrayRef.h"		#include "llvm/ADT/ArrayRef.h"
	#include "llvm/Support/DataTypes.h"		#include "llvm/Support/DataTypes.h"
	namespace llvm {		namespace llvm {
	class Value;		class Value;
	class Instruction;		class Instruction;
	class APInt;		class APInt;
	class DataLayout;		class DataLayout;
	class StringRef;		class StringRef;
	class MDNode;		class MDNode;
			class TargetLibraryInfo;
	/// ComputeMaskedBits - Determine which of the bits specified in Mask are		/// ComputeMaskedBits - Determine which of the bits specified in Mask are
	/// known to be either zero or one and return them in the KnownZero/Known One		/// known to be either zero or one and return them in the KnownZero/Known One
	/// bit sets. This code only analyzes bits in Mask, in order to short-ci rcuit		/// bit sets. This code only analyzes bits in Mask, in order to short-ci rcuit
	/// processing.		/// processing.
	///		///
	/// This function is defined on values with integer type, values with poi nter		/// This function is defined on values with integer type, values with poi nter
	/// type (but only if TD is non-null), and vectors of integers. In the c ase		/// type (but only if TD is non-null), and vectors of integers. In the c ase
	/// where V is a vector, the mask, known zero, and known one values are t he		/// where V is a vector, the mask, known zero, and known one values are t he
	/// same width as the vector element, and the bit is set only if it is tr ue		/// same width as the vector element, and the bit is set only if it is tr ue
	skipping to change at line 188		skipping to change at line 189
	/// this method returns true, it is safe to move the instruction as long as		/// this method returns true, it is safe to move the instruction as long as
	/// the correct dominance relationships for the operands and users hold.		/// the correct dominance relationships for the operands and users hold.
	/// However, this method can return true for instructions that read memor y;		/// However, this method can return true for instructions that read memor y;
	/// for such instructions, moving them may change the resulting value.		/// for such instructions, moving them may change the resulting value.
	bool isSafeToSpeculativelyExecute(const Value *V,		bool isSafeToSpeculativelyExecute(const Value *V,
	const DataLayout *TD = 0);		const DataLayout *TD = 0);
	/// isKnownNonNull - Return true if this pointer couldn't possibly be nul l by		/// isKnownNonNull - Return true if this pointer couldn't possibly be nul l by
	/// its definition. This returns true for allocas, non-extern-weak globa ls		/// its definition. This returns true for allocas, non-extern-weak globa ls
	/// and byval arguments.		/// and byval arguments.
	bool isKnownNonNull(const Value *V);		bool isKnownNonNull(const Value *V, const TargetLibraryInfo *TLI = 0);
	} // end namespace llvm		} // end namespace llvm
	#endif		#endif
End of changes. 2 change blocks.
	1 lines changed or deleted		2 lines changed or added

	ValueTypes.h		ValueTypes.h
	skipping to change at line 30		skipping to change at line 30
	#include "llvm/Support/ErrorHandling.h"		#include "llvm/Support/ErrorHandling.h"
	#include "llvm/Support/MathExtras.h"		#include "llvm/Support/MathExtras.h"
	#include <cassert>		#include <cassert>
	#include <string>		#include <string>
	namespace llvm {		namespace llvm {
	class Type;		class Type;
	class LLVMContext;		class LLVMContext;
	struct EVT;		struct EVT;
	/// MVT - Machine Value Type. Every type that is supported natively by s		/// MVT - Machine Value Type. Every type that is supported natively by so
	ome		me
	/// processor targeted by LLVM occurs here. This means that any legal va		/// processor targeted by LLVM occurs here. This means that any legal val
	lue		ue
	/// type can be represented by a MVT.		/// type can be represented by an MVT.
	class MVT {		class MVT {
	public:		public:
	enum SimpleValueType {		enum SimpleValueType {
	// INVALID_SIMPLE_VALUE_TYPE - Simple value types less than zero are		// INVALID_SIMPLE_VALUE_TYPE - Simple value types less than zero are
	// considered extended value types.		// considered extended value types.
	INVALID_SIMPLE_VALUE_TYPE = -1,		INVALID_SIMPLE_VALUE_TYPE = -1,
	// If you change this numbering, you must change the values in		// If you change this numbering, you must change the values in
	// ValueTypes.td as well!		// ValueTypes.td as well!
	Other = 0, // This is a non-standard value		Other = 0, // This is a non-standard value
	skipping to change at line 70		skipping to change at line 70
	FIRST_FP_VALUETYPE = f16,		FIRST_FP_VALUETYPE = f16,
	LAST_FP_VALUETYPE = ppcf128,		LAST_FP_VALUETYPE = ppcf128,
	v2i1 = 13, // 2 x i1		v2i1 = 13, // 2 x i1
	v4i1 = 14, // 4 x i1		v4i1 = 14, // 4 x i1
	v8i1 = 15, // 8 x i1		v8i1 = 15, // 8 x i1
	v16i1 = 16, // 16 x i1		v16i1 = 16, // 16 x i1
	v32i1 = 17, // 32 x i1		v32i1 = 17, // 32 x i1
	v64i1 = 18, // 64 x i1		v64i1 = 18, // 64 x i1
	v2i8 = 19, // 2 x i8		v1i8 = 19, // 1 x i8
	v4i8 = 20, // 4 x i8		v2i8 = 20, // 2 x i8
	v8i8 = 21, // 8 x i8		v4i8 = 21, // 4 x i8
	v16i8 = 22, // 16 x i8		v8i8 = 22, // 8 x i8
	v32i8 = 23, // 32 x i8		v16i8 = 23, // 16 x i8
	v64i8 = 24, // 64 x i8		v32i8 = 24, // 32 x i8
	v1i16 = 25, // 1 x i16		v64i8 = 25, // 64 x i8
	v2i16 = 26, // 2 x i16		v1i16 = 26, // 1 x i16
	v4i16 = 27, // 4 x i16		v2i16 = 27, // 2 x i16
	v8i16 = 28, // 8 x i16		v4i16 = 28, // 4 x i16
	v16i16 = 29, // 16 x i16		v8i16 = 29, // 8 x i16
	v32i16 = 30, // 32 x i16		v16i16 = 30, // 16 x i16
	v1i32 = 31, // 1 x i32		v32i16 = 31, // 32 x i16
	v2i32 = 32, // 2 x i32		v1i32 = 32, // 1 x i32
	v4i32 = 33, // 4 x i32		v2i32 = 33, // 2 x i32
	v8i32 = 34, // 8 x i32		v4i32 = 34, // 4 x i32
	v16i32 = 35, // 16 x i32		v8i32 = 35, // 8 x i32
	v1i64 = 36, // 1 x i64		v16i32 = 36, // 16 x i32
	v2i64 = 37, // 2 x i64		v1i64 = 37, // 1 x i64
	v4i64 = 38, // 4 x i64		v2i64 = 38, // 2 x i64
	v8i64 = 39, // 8 x i64		v4i64 = 39, // 4 x i64
	v16i64 = 40, // 16 x i64		v8i64 = 40, // 8 x i64
			v16i64 = 41, // 16 x i64
	FIRST_INTEGER_VECTOR_VALUETYPE = v2i1,		FIRST_INTEGER_VECTOR_VALUETYPE = v2i1,
	LAST_INTEGER_VECTOR_VALUETYPE = v16i64,		LAST_INTEGER_VECTOR_VALUETYPE = v16i64,
	v2f16 = 41, // 2 x f16		v2f16 = 42, // 2 x f16
	v2f32 = 42, // 2 x f32		v4f16 = 43, // 4 x f16
	v4f32 = 43, // 4 x f32		v8f16 = 44, // 8 x f16
	v8f32 = 44, // 8 x f32		v1f32 = 45, // 1 x f32
	v16f32 = 45, // 16 x f32		v2f32 = 46, // 2 x f32
	v2f64 = 46, // 2 x f64		v4f32 = 47, // 4 x f32
	v4f64 = 47, // 4 x f64		v8f32 = 48, // 8 x f32
	v8f64 = 48, // 8 x f64		v16f32 = 49, // 16 x f32
			v1f64 = 50, // 1 x f64
			v2f64 = 51, // 2 x f64
			v4f64 = 52, // 4 x f64
			v8f64 = 53, // 8 x f64
	FIRST_FP_VECTOR_VALUETYPE = v2f16,		FIRST_FP_VECTOR_VALUETYPE = v2f16,
	LAST_FP_VECTOR_VALUETYPE = v8f64,		LAST_FP_VECTOR_VALUETYPE = v8f64,
	FIRST_VECTOR_VALUETYPE = v2i1,		FIRST_VECTOR_VALUETYPE = v2i1,
	LAST_VECTOR_VALUETYPE = v8f64,		LAST_VECTOR_VALUETYPE = v8f64,
	x86mmx = 49, // This is an X86 MMX value		x86mmx = 54, // This is an X86 MMX value
	Glue = 50, // This glues nodes together during pre-RA sc hed		Glue = 55, // This glues nodes together during pre-RA sc hed
	isVoid = 51, // This has no value		isVoid = 56, // This has no value
	Untyped = 52, // This value takes a register, but has		Untyped = 57, // This value takes a register, but has
	// unspecified type. The register class		// unspecified type. The register class
	// will be determined by the opcode.		// will be determined by the opcode.
	LAST_VALUETYPE = 53, // This always remains at the end of the list .		LAST_VALUETYPE = 58, // This always remains at the end of the list .
	// This is the current maximum for LAST_VALUETYPE.		// This is the current maximum for LAST_VALUETYPE.
	// MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vec tors		// MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vec tors
	// This value must be a multiple of 32.		// This value must be a multiple of 32.
	MAX_ALLOWED_VALUETYPE = 64,		MAX_ALLOWED_VALUETYPE = 64,
	// Metadata - This is MDNode or MDString.		// Metadata - This is MDNode or MDString.
	Metadata = 250,		Metadata = 250,
	// iPTRAny - An int value the size of the pointer of the current		// iPTRAny - An int value the size of the pointer of the current
	skipping to change at line 206		skipping to change at line 211
	/// is32BitVector - Return true if this is a 32-bit vector type.		/// is32BitVector - Return true if this is a 32-bit vector type.
	bool is32BitVector() const {		bool is32BitVector() const {
	return (SimpleTy == MVT::v4i8 || SimpleTy == MVT::v2i16 ||		return (SimpleTy == MVT::v4i8 || SimpleTy == MVT::v2i16 ||
	SimpleTy == MVT::v1i32);		SimpleTy == MVT::v1i32);
	}		}
	/// is64BitVector - Return true if this is a 64-bit vector type.		/// is64BitVector - Return true if this is a 64-bit vector type.
	bool is64BitVector() const {		bool is64BitVector() const {
	return (SimpleTy == MVT::v8i8 || SimpleTy == MVT::v4i16 ||		return (SimpleTy == MVT::v8i8 || SimpleTy == MVT::v4i16 ||
	SimpleTy == MVT::v2i32 || SimpleTy == MVT::v1i64 ||		SimpleTy == MVT::v2i32 || SimpleTy == MVT::v1i64 ||
	SimpleTy == MVT::v2f32);		SimpleTy == MVT::v1f64 || SimpleTy == MVT::v2f32);
	}		}
	/// is128BitVector - Return true if this is a 128-bit vector type.		/// is128BitVector - Return true if this is a 128-bit vector type.
	bool is128BitVector() const {		bool is128BitVector() const {
	return (SimpleTy == MVT::v16i8 || SimpleTy == MVT::v8i16 ||		return (SimpleTy == MVT::v16i8 || SimpleTy == MVT::v8i16 ||
	SimpleTy == MVT::v4i32 || SimpleTy == MVT::v2i64 ||		SimpleTy == MVT::v4i32 || SimpleTy == MVT::v2i64 ||
	SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64);		SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64);
	}		}
	/// is256BitVector - Return true if this is a 256-bit vector type.		/// is256BitVector - Return true if this is a 256-bit vector type.
	skipping to change at line 268		skipping to change at line 273
	MVT getVectorElementType() const {		MVT getVectorElementType() const {
	switch (SimpleTy) {		switch (SimpleTy) {
	default:		default:
	llvm_unreachable("Not a vector MVT!");		llvm_unreachable("Not a vector MVT!");
	case v2i1 :		case v2i1 :
	case v4i1 :		case v4i1 :
	case v8i1 :		case v8i1 :
	case v16i1 :		case v16i1 :
	case v32i1 :		case v32i1 :
	case v64i1: return i1;		case v64i1: return i1;
			case v1i8 :
	case v2i8 :		case v2i8 :
	case v4i8 :		case v4i8 :
	case v8i8 :		case v8i8 :
	case v16i8:		case v16i8:
	case v32i8:		case v32i8:
	case v64i8: return i8;		case v64i8: return i8;
	case v1i16:		case v1i16:
	case v2i16:		case v2i16:
	case v4i16:		case v4i16:
	case v8i16:		case v8i16:
	skipping to change at line 290		skipping to change at line 296
	case v1i32:		case v1i32:
	case v2i32:		case v2i32:
	case v4i32:		case v4i32:
	case v8i32:		case v8i32:
	case v16i32: return i32;		case v16i32: return i32;
	case v1i64:		case v1i64:
	case v2i64:		case v2i64:
	case v4i64:		case v4i64:
	case v8i64:		case v8i64:
	case v16i64: return i64;		case v16i64: return i64;
	case v2f16: return f16;		case v2f16:
			case v4f16:
			case v8f16: return f16;
			case v1f32:
	case v2f32:		case v2f32:
	case v4f32:		case v4f32:
	case v8f32:		case v8f32:
	case v16f32: return f32;		case v16f32: return f32;
			case v1f64:
	case v2f64:		case v2f64:
	case v4f64:		case v4f64:
	case v8f64: return f64;		case v8f64: return f64;
	}		}
	}		}
	unsigned getVectorNumElements() const {		unsigned getVectorNumElements() const {
	switch (SimpleTy) {		switch (SimpleTy) {
	default:		default:
	llvm_unreachable("Not a vector MVT!");		llvm_unreachable("Not a vector MVT!");
	skipping to change at line 321		skipping to change at line 331
	case v16i8:		case v16i8:
	case v16i16:		case v16i16:
	case v16i32:		case v16i32:
	case v16i64:		case v16i64:
	case v16f32: return 16;		case v16f32: return 16;
	case v8i1 :		case v8i1 :
	case v8i8 :		case v8i8 :
	case v8i16:		case v8i16:
	case v8i32:		case v8i32:
	case v8i64:		case v8i64:
			case v8f16:
	case v8f32:		case v8f32:
	case v8f64: return 8;		case v8f64: return 8;
	case v4i1:		case v4i1:
	case v4i8:		case v4i8:
	case v4i16:		case v4i16:
	case v4i32:		case v4i32:
	case v4i64:		case v4i64:
			case v4f16:
	case v4f32:		case v4f32:
	case v4f64: return 4;		case v4f64: return 4;
	case v2i1:		case v2i1:
	case v2i8:		case v2i8:
	case v2i16:		case v2i16:
	case v2i32:		case v2i32:
	case v2i64:		case v2i64:
	case v2f16:		case v2f16:
	case v2f32:		case v2f32:
	case v2f64: return 2;		case v2f64: return 2;
			case v1i8:
	case v1i16:		case v1i16:
	case v1i32:		case v1i32:
	case v1i64: return 1;		case v1i64:
			case v1f32:
			case v1f64: return 1;
	}		}
	}		}
	unsigned getSizeInBits() const {		unsigned getSizeInBits() const {
	switch (SimpleTy) {		switch (SimpleTy) {
			default:
			llvm_unreachable("getSizeInBits called on extended MVT.");
			case Other:
			llvm_unreachable("Value type is non-standard value, Other.");
	case iPTR:		case iPTR:
	llvm_unreachable("Value type size is target-dependent. Ask TLI.");		llvm_unreachable("Value type size is target-dependent. Ask TLI.");
	case iPTRAny:		case iPTRAny:
	case iAny:		case iAny:
	case fAny:		case fAny:
	case vAny:		case vAny:
	llvm_unreachable("Value type is overloaded.");		llvm_unreachable("Value type is overloaded.");
	case Metadata:		case Metadata:
	llvm_unreachable("Value type is metadata.");		llvm_unreachable("Value type is metadata.");
	default:
	llvm_unreachable("getSizeInBits called on extended MVT.");
	case i1 : return 1;		case i1 : return 1;
	case v2i1: return 2;		case v2i1: return 2;
	case v4i1: return 4;		case v4i1: return 4;
	case i8 :		case i8 :
			case v1i8:
	case v8i1: return 8;		case v8i1: return 8;
	case i16 :		case i16 :
	case f16:		case f16:
	case v16i1:		case v16i1:
	case v2i8:		case v2i8:
	case v1i16: return 16;		case v1i16: return 16;
	case f32 :		case f32 :
	case i32 :		case i32 :
	case v32i1:		case v32i1:
	case v4i8:		case v4i8:
	case v2i16:		case v2i16:
	case v2f16:		case v2f16:
			case v1f32:
	case v1i32: return 32;		case v1i32: return 32;
	case x86mmx:		case x86mmx:
	case f64 :		case f64 :
	case i64 :		case i64 :
	case v64i1:		case v64i1:
	case v8i8:		case v8i8:
	case v4i16:		case v4i16:
	case v2i32:		case v2i32:
	case v1i64:		case v1i64:
	case v2f32: return 64;		case v4f16:
			case v2f32:
			case v1f64: return 64;
	case f80 : return 80;		case f80 : return 80;
	case f128:		case f128:
	case ppcf128:		case ppcf128:
	case i128:		case i128:
	case v16i8:		case v16i8:
	case v8i16:		case v8i16:
	case v4i32:		case v4i32:
	case v2i64:		case v2i64:
			case v8f16:
	case v4f32:		case v4f32:
	case v2f64: return 128;		case v2f64: return 128;
	case v32i8:		case v32i8:
	case v16i16:		case v16i16:
	case v8i32:		case v8i32:
	case v4i64:		case v4i64:
	case v8f32:		case v8f32:
	case v4f64: return 256;		case v4f64: return 256;
	case v64i8:		case v64i8:
	case v32i16:		case v32i16:
	skipping to change at line 490		skipping to change at line 512
	break;		break;
	case MVT::i1:		case MVT::i1:
	if (NumElements == 2) return MVT::v2i1;		if (NumElements == 2) return MVT::v2i1;
	if (NumElements == 4) return MVT::v4i1;		if (NumElements == 4) return MVT::v4i1;
	if (NumElements == 8) return MVT::v8i1;		if (NumElements == 8) return MVT::v8i1;
	if (NumElements == 16) return MVT::v16i1;		if (NumElements == 16) return MVT::v16i1;
	if (NumElements == 32) return MVT::v32i1;		if (NumElements == 32) return MVT::v32i1;
	if (NumElements == 64) return MVT::v64i1;		if (NumElements == 64) return MVT::v64i1;
	break;		break;
	case MVT::i8:		case MVT::i8:
			if (NumElements == 1) return MVT::v1i8;
	if (NumElements == 2) return MVT::v2i8;		if (NumElements == 2) return MVT::v2i8;
	if (NumElements == 4) return MVT::v4i8;		if (NumElements == 4) return MVT::v4i8;
	if (NumElements == 8) return MVT::v8i8;		if (NumElements == 8) return MVT::v8i8;
	if (NumElements == 16) return MVT::v16i8;		if (NumElements == 16) return MVT::v16i8;
	if (NumElements == 32) return MVT::v32i8;		if (NumElements == 32) return MVT::v32i8;
	if (NumElements == 64) return MVT::v64i8;		if (NumElements == 64) return MVT::v64i8;
	break;		break;
	case MVT::i16:		case MVT::i16:
	if (NumElements == 1) return MVT::v1i16;		if (NumElements == 1) return MVT::v1i16;
	if (NumElements == 2) return MVT::v2i16;		if (NumElements == 2) return MVT::v2i16;
	skipping to change at line 521		skipping to change at line 544
	break;		break;
	case MVT::i64:		case MVT::i64:
	if (NumElements == 1) return MVT::v1i64;		if (NumElements == 1) return MVT::v1i64;
	if (NumElements == 2) return MVT::v2i64;		if (NumElements == 2) return MVT::v2i64;
	if (NumElements == 4) return MVT::v4i64;		if (NumElements == 4) return MVT::v4i64;
	if (NumElements == 8) return MVT::v8i64;		if (NumElements == 8) return MVT::v8i64;
	if (NumElements == 16) return MVT::v16i64;		if (NumElements == 16) return MVT::v16i64;
	break;		break;
	case MVT::f16:		case MVT::f16:
	if (NumElements == 2) return MVT::v2f16;		if (NumElements == 2) return MVT::v2f16;
			if (NumElements == 4) return MVT::v4f16;
			if (NumElements == 8) return MVT::v8f16;
	break;		break;
	case MVT::f32:		case MVT::f32:
			if (NumElements == 1) return MVT::v1f32;
	if (NumElements == 2) return MVT::v2f32;		if (NumElements == 2) return MVT::v2f32;
	if (NumElements == 4) return MVT::v4f32;		if (NumElements == 4) return MVT::v4f32;
	if (NumElements == 8) return MVT::v8f32;		if (NumElements == 8) return MVT::v8f32;
	if (NumElements == 16) return MVT::v16f32;		if (NumElements == 16) return MVT::v16f32;
	break;		break;
	case MVT::f64:		case MVT::f64:
			if (NumElements == 1) return MVT::v1f64;
	if (NumElements == 2) return MVT::v2f64;		if (NumElements == 2) return MVT::v2f64;
	if (NumElements == 4) return MVT::v4f64;		if (NumElements == 4) return MVT::v4f64;
	if (NumElements == 8) return MVT::v8f64;		if (NumElements == 8) return MVT::v8f64;
	break;		break;
	}		}
	return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);		return (MVT::SimpleValueType)(MVT::INVALID_SIMPLE_VALUE_TYPE);
	}		}
	/// Return the value type corresponding to the specified type. This re turns		/// Return the value type corresponding to the specified type. This re turns
	/// all pointers as iPTR. If HandleUnknown is true, unknown types are		/// all pointers as iPTR. If HandleUnknown is true, unknown types are
End of changes. 26 change blocks.
	46 lines changed or deleted		73 lines changed or added

	ValueTypes.td		ValueTypes.td
	skipping to change at line 29		skipping to change at line 29
	int Value = value;		int Value = value;
	}		}
	def OtherVT: ValueType<0 , 0>; // "Other" value		def OtherVT: ValueType<0 , 0>; // "Other" value
	def i1 : ValueType<1 , 1>; // One bit boolean value		def i1 : ValueType<1 , 1>; // One bit boolean value
	def i8 : ValueType<8 , 2>; // 8-bit integer value		def i8 : ValueType<8 , 2>; // 8-bit integer value
	def i16 : ValueType<16 , 3>; // 16-bit integer value		def i16 : ValueType<16 , 3>; // 16-bit integer value
	def i32 : ValueType<32 , 4>; // 32-bit integer value		def i32 : ValueType<32 , 4>; // 32-bit integer value
	def i64 : ValueType<64 , 5>; // 64-bit integer value		def i64 : ValueType<64 , 5>; // 64-bit integer value
	def i128 : ValueType<128, 6>; // 128-bit integer value		def i128 : ValueType<128, 6>; // 128-bit integer value
	def f16 : ValueType<16 , 7>; // 32-bit floating point value		def f16 : ValueType<16 , 7>; // 16-bit floating point value
	def f32 : ValueType<32 , 8>; // 32-bit floating point value		def f32 : ValueType<32 , 8>; // 32-bit floating point value
	def f64 : ValueType<64 , 9>; // 64-bit floating point value		def f64 : ValueType<64 , 9>; // 64-bit floating point value
	def f80 : ValueType<80 , 10>; // 80-bit floating point value		def f80 : ValueType<80 , 10>; // 80-bit floating point value
	def f128 : ValueType<128, 11>; // 128-bit floating point value		def f128 : ValueType<128, 11>; // 128-bit floating point value
	def ppcf128: ValueType<128, 12>; // PPC 128-bit floating point value		def ppcf128: ValueType<128, 12>; // PPC 128-bit floating point value
	def v2i1 : ValueType<2 , 13>; // 2 x i1 vector value		def v2i1 : ValueType<2 , 13>; // 2 x i1 vector value
	def v4i1 : ValueType<4 , 14>; // 4 x i1 vector value		def v4i1 : ValueType<4 , 14>; // 4 x i1 vector value
	def v8i1 : ValueType<8 , 15>; // 8 x i1 vector value		def v8i1 : ValueType<8 , 15>; // 8 x i1 vector value
	def v16i1 : ValueType<16, 16>; // 16 x i1 vector value		def v16i1 : ValueType<16, 16>; // 16 x i1 vector value
	def v32i1 : ValueType<32 , 17>; // 32 x i1 vector value		def v32i1 : ValueType<32 , 17>; // 32 x i1 vector value
	def v64i1 : ValueType<64 , 18>; // 64 x i1 vector value		def v64i1 : ValueType<64 , 18>; // 64 x i1 vector value
	def v2i8 : ValueType<16 , 19>; // 2 x i8 vector value		def v1i8 : ValueType<16, 19>; // 1 x i8 vector value
	def v4i8 : ValueType<32 , 20>; // 4 x i8 vector value		def v2i8 : ValueType<16 , 20>; // 2 x i8 vector value
	def v8i8 : ValueType<64 , 21>; // 8 x i8 vector value		def v4i8 : ValueType<32 , 21>; // 4 x i8 vector value
	def v16i8 : ValueType<128, 22>; // 16 x i8 vector value		def v8i8 : ValueType<64 , 22>; // 8 x i8 vector value
	def v32i8 : ValueType<256, 23>; // 32 x i8 vector value		def v16i8 : ValueType<128, 23>; // 16 x i8 vector value
	def v64i8 : ValueType<512, 24>; // 64 x i8 vector value		def v32i8 : ValueType<256, 24>; // 32 x i8 vector value
	def v1i16 : ValueType<16 , 25>; // 1 x i16 vector value		def v64i8 : ValueType<512, 25>; // 64 x i8 vector value
	def v2i16 : ValueType<32 , 26>; // 2 x i16 vector value		def v1i16 : ValueType<16 , 26>; // 1 x i16 vector value
	def v4i16 : ValueType<64 , 27>; // 4 x i16 vector value		def v2i16 : ValueType<32 , 27>; // 2 x i16 vector value
	def v8i16 : ValueType<128, 28>; // 8 x i16 vector value		def v4i16 : ValueType<64 , 28>; // 4 x i16 vector value
	def v16i16 : ValueType<256, 29>; // 16 x i16 vector value		def v8i16 : ValueType<128, 29>; // 8 x i16 vector value
	def v32i16 : ValueType<512, 30>; // 32 x i16 vector value		def v16i16 : ValueType<256, 30>; // 16 x i16 vector value
	def v1i32 : ValueType<32 , 31>; // 1 x i32 vector value		def v32i16 : ValueType<512, 31>; // 32 x i16 vector value
	def v2i32 : ValueType<64 , 32>; // 2 x i32 vector value		def v1i32 : ValueType<32 , 32>; // 1 x i32 vector value
	def v4i32 : ValueType<128, 33>; // 4 x i32 vector value		def v2i32 : ValueType<64 , 33>; // 2 x i32 vector value
	def v8i32 : ValueType<256, 34>; // 8 x i32 vector value		def v4i32 : ValueType<128, 34>; // 4 x i32 vector value
	def v16i32 : ValueType<512, 35>; // 16 x i32 vector value		def v8i32 : ValueType<256, 35>; // 8 x i32 vector value
	def v1i64 : ValueType<64 , 36>; // 1 x i64 vector value		def v16i32 : ValueType<512, 36>; // 16 x i32 vector value
	def v2i64 : ValueType<128, 37>; // 2 x i64 vector value		def v1i64 : ValueType<64 , 37>; // 1 x i64 vector value
	def v4i64 : ValueType<256, 38>; // 4 x i64 vector value		def v2i64 : ValueType<128, 38>; // 2 x i64 vector value
	def v8i64 : ValueType<512, 39>; // 8 x i64 vector value		def v4i64 : ValueType<256, 39>; // 4 x i64 vector value
	def v16i64 : ValueType<1024,40>; // 16 x i64 vector value		def v8i64 : ValueType<512, 40>; // 8 x i64 vector value
			def v16i64 : ValueType<1024,41>; // 16 x i64 vector value
	def v2f16 : ValueType<32 , 41>; // 2 x f16 vector value
	def v2f32 : ValueType<64 , 42>; // 2 x f32 vector value		def v2f16 : ValueType<32 , 42>; // 2 x f16 vector value
	def v4f32 : ValueType<128, 43>; // 4 x f32 vector value		def v4f16 : ValueType<64 , 43>; // 4 x f16 vector value
	def v8f32 : ValueType<256, 44>; // 8 x f32 vector value		def v8f16 : ValueType<128, 44>; // 8 x f16 vector value
	def v16f32 : ValueType<512, 45>; // 16 x f32 vector value		def v1f32 : ValueType<32 , 45>; // 1 x f32 vector value
	def v2f64 : ValueType<128, 46>; // 2 x f64 vector value		def v2f32 : ValueType<64 , 46>; // 2 x f32 vector value
	def v4f64 : ValueType<256, 47>; // 4 x f64 vector value		def v4f32 : ValueType<128, 47>; // 4 x f32 vector value
	def v8f64 : ValueType<512, 48>; // 8 x f64 vector value		def v8f32 : ValueType<256, 48>; // 8 x f32 vector value
			def v16f32 : ValueType<512, 49>; // 16 x f32 vector value
	def x86mmx : ValueType<64 , 49>; // X86 MMX value		def v1f64 : ValueType<64, 50>; // 1 x f64 vector value
	def FlagVT : ValueType<0 , 50>; // Pre-RA sched glue		def v2f64 : ValueType<128, 51>; // 2 x f64 vector value
	def isVoid : ValueType<0 , 51>; // Produces no value		def v4f64 : ValueType<256, 52>; // 4 x f64 vector value
	def untyped: ValueType<8 , 52>; // Produces an untyped value		def v8f64 : ValueType<512, 53>; // 8 x f64 vector value
			def x86mmx : ValueType<64 , 54>; // X86 MMX value
			def FlagVT : ValueType<0 , 55>; // Pre-RA sched glue
			def isVoid : ValueType<0 , 56>; // Produces no value
			def untyped: ValueType<8 , 57>; // Produces an untyped value
	def MetadataVT: ValueType<0, 250>; // Metadata		def MetadataVT: ValueType<0, 250>; // Metadata
	// Pseudo valuetype mapped to the current pointer size to any address space .		// Pseudo valuetype mapped to the current pointer size to any address space .
	// Should only be used in TableGen.		// Should only be used in TableGen.
	def iPTRAny : ValueType<0, 251>;		def iPTRAny : ValueType<0, 251>;
	// Pseudo valuetype to represent "vector of any size"		// Pseudo valuetype to represent "vector of any size"
	def vAny : ValueType<0 , 252>;		def vAny : ValueType<0 , 252>;
	// Pseudo valuetype to represent "float of any format"		// Pseudo valuetype to represent "float of any format"
End of changes. 2 change blocks.
	37 lines changed or deleted		42 lines changed or added

	Vectorize.h		Vectorize.h
	skipping to change at line 117		skipping to change at line 117
	//		//
	// BBVectorize - A basic-block vectorization pass.		// BBVectorize - A basic-block vectorization pass.
	//		//
	BasicBlockPass *		BasicBlockPass *
	createBBVectorizePass(const VectorizeConfig &C = VectorizeConfig());		createBBVectorizePass(const VectorizeConfig &C = VectorizeConfig());
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// LoopVectorize - Create a loop vectorization pass.		// LoopVectorize - Create a loop vectorization pass.
	//		//
	Pass *createLoopVectorizePass();		Pass *createLoopVectorizePass(bool NoUnrolling = false);
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	//		//
	// SLPVectorizer - Create a bottom-up SLP vectorizer pass.		// SLPVectorizer - Create a bottom-up SLP vectorizer pass.
	//		//
	Pass *createSLPVectorizerPass();		Pass *createSLPVectorizerPass();
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	/// @brief Vectorize the BasicBlock.		/// @brief Vectorize the BasicBlock.
	///		///
End of changes. 1 change blocks.
	1 lines changed or deleted		1 lines changed or added

	YAMLParser.h		YAMLParser.h
	skipping to change at line 46		skipping to change at line 46
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_SUPPORT_YAMLPARSER_H		#ifndef LLVM_SUPPORT_YAMLPARSER_H
	#define LLVM_SUPPORT_YAMLPARSER_H		#define LLVM_SUPPORT_YAMLPARSER_H
	#include "llvm/ADT/OwningPtr.h"		#include "llvm/ADT/OwningPtr.h"
	#include "llvm/ADT/SmallString.h"		#include "llvm/ADT/SmallString.h"
	#include "llvm/ADT/StringRef.h"		#include "llvm/ADT/StringRef.h"
	#include "llvm/Support/Allocator.h"		#include "llvm/Support/Allocator.h"
	#include "llvm/Support/SMLoc.h"		#include "llvm/Support/SMLoc.h"
			#include <map>
	#include <limits>		#include <limits>
	#include <utility>		#include <utility>
	namespace llvm {		namespace llvm {
	class MemoryBuffer;		class MemoryBuffer;
	class SourceMgr;		class SourceMgr;
	class raw_ostream;		class raw_ostream;
	class Twine;		class Twine;
	namespace yaml {		namespace yaml {
	skipping to change at line 102		skipping to change at line 104
	return !failed();		return !failed();
	}		}
	void printError(Node *N, const Twine &Msg);		void printError(Node *N, const Twine &Msg);
	private:		private:
	OwningPtr<Scanner> scanner;		OwningPtr<Scanner> scanner;
	OwningPtr<Document> CurrentDoc;		OwningPtr<Document> CurrentDoc;
	friend class Document;		friend class Document;
	/// @brief Validate a %YAML x.x directive.
	void handleYAMLDirective(const Token &);
	};		};
	/// @brief Abstract base class for all Nodes.		/// @brief Abstract base class for all Nodes.
	class Node {		class Node {
			virtual void anchor();
	public:		public:
	enum NodeKind {		enum NodeKind {
	NK_Null,		NK_Null,
	NK_Scalar,		NK_Scalar,
	NK_KeyValue,		NK_KeyValue,
	NK_Mapping,		NK_Mapping,
	NK_Sequence,		NK_Sequence,
	NK_Alias		NK_Alias
	};		};
	Node(unsigned int Type, OwningPtr<Document>&, StringRef Anchor);		Node(unsigned int Type, OwningPtr<Document> &, StringRef Anchor,
			StringRef Tag);
	/// @brief Get the value of the anchor attached to this node. If it does not		/// @brief Get the value of the anchor attached to this node. If it does not
	/// have one, getAnchor().size() will be 0.		/// have one, getAnchor().size() will be 0.
	StringRef getAnchor() const { return Anchor; }		StringRef getAnchor() const { return Anchor; }
			/// \brief Get the tag as it was written in the document. This does not
			/// perform tag resolution.
			StringRef getRawTag() const { return Tag; }
			/// \brief Get the verbatium tag for a given Node. This performs tag reso
			luton
			/// and substitution.
			std::string getVerbatimTag() const;
	SMRange getSourceRange() const { return SourceRange; }		SMRange getSourceRange() const { return SourceRange; }
	void setSourceRange(SMRange SR) { SourceRange = SR; }		void setSourceRange(SMRange SR) { SourceRange = SR; }
	// These functions forward to Document and Scanner.		// These functions forward to Document and Scanner.
	Token &peekNext();		Token &peekNext();
	Token getNext();		Token getNext();
	Node *parseBlockNode();		Node *parseBlockNode();
	BumpPtrAllocator &getAllocator();		BumpPtrAllocator &getAllocator();
	void setError(const Twine &Message, Token &Location) const;		void setError(const Twine &Message, Token &Location) const;
	bool failed() const;		bool failed() const;
	skipping to change at line 161		skipping to change at line 170
	OwningPtr<Document> &Doc;		OwningPtr<Document> &Doc;
	SMRange SourceRange;		SMRange SourceRange;
	void operator delete(void *) throw() {}		void operator delete(void *) throw() {}
	virtual ~Node() {}		virtual ~Node() {}
	private:		private:
	unsigned int TypeID;		unsigned int TypeID;
	StringRef Anchor;		StringRef Anchor;
			/// \brief The tag as typed in the document.
			StringRef Tag;
	};		};
	/// @brief A null value.		/// @brief A null value.
	///		///
	/// Example:		/// Example:
	/// !!null null		/// !!null null
	class NullNode : public Node {		class NullNode : public Node {
			virtual void anchor();
	public:		public:
	NullNode(OwningPtr<Document> &D) : Node(NK_Null, D, StringRef()) {}		NullNode(OwningPtr<Document> &D)
			: Node(NK_Null, D, StringRef(), StringRef()) {}
	static inline bool classof(const Node *N) {		static inline bool classof(const Node *N) {
	return N->getType() == NK_Null;		return N->getType() == NK_Null;
	}		}
	};		};
	/// @brief A scalar node is an opaque datum that can be presented as a		/// @brief A scalar node is an opaque datum that can be presented as a
	/// series of zero or more Unicode scalar values.		/// series of zero or more Unicode scalar values.
	///		///
	/// Example:		/// Example:
	/// Adena		/// Adena
	class ScalarNode : public Node {		class ScalarNode : public Node {
			virtual void anchor();
	public:		public:
	ScalarNode(OwningPtr<Document> &D, StringRef Anchor, StringRef Val)		ScalarNode(OwningPtr<Document> &D, StringRef Anchor, StringRef Tag,
	: Node(NK_Scalar, D, Anchor)		StringRef Val)
	, Value(Val) {		: Node(NK_Scalar, D, Anchor, Tag), Value(Val) {
	SMLoc Start = SMLoc::getFromPointer(Val.begin());		SMLoc Start = SMLoc::getFromPointer(Val.begin());
	SMLoc End = SMLoc::getFromPointer(Val.end());		SMLoc End = SMLoc::getFromPointer(Val.end());
	SourceRange = SMRange(Start, End);		SourceRange = SMRange(Start, End);
	}		}
	// Return Value without any escaping or folding or other fun YAML stuff. This		// Return Value without any escaping or folding or other fun YAML stuff. This
	// is the exact bytes that are contained in the file (after conversion to		// is the exact bytes that are contained in the file (after conversion to
	// utf8).		// utf8).
	StringRef getRawValue() const { return Value; }		StringRef getRawValue() const { return Value; }
	skipping to change at line 223		skipping to change at line 237
	};		};
	/// @brief A key and value pair. While not technically a Node under the YAM L		/// @brief A key and value pair. While not technically a Node under the YAM L
	/// representation graph, it is easier to treat them this way.		/// representation graph, it is easier to treat them this way.
	///		///
	/// TODO: Consider making this not a child of Node.		/// TODO: Consider making this not a child of Node.
	///		///
	/// Example:		/// Example:
	/// Section: .text		/// Section: .text
	class KeyValueNode : public Node {		class KeyValueNode : public Node {
			virtual void anchor();
	public:		public:
	KeyValueNode(OwningPtr<Document> &D)		KeyValueNode(OwningPtr<Document> &D)
	: Node(NK_KeyValue, D, StringRef())		: Node(NK_KeyValue, D, StringRef(), StringRef())
	, Key(0)		, Key(0)
	, Value(0)		, Value(0)
	{}		{}
	/// @brief Parse and return the key.		/// @brief Parse and return the key.
	///		///
	/// This may be called multiple times.		/// This may be called multiple times.
	///		///
	/// @returns The key, or nullptr if failed() == true.		/// @returns The key, or nullptr if failed() == true.
	Node *getKey();		Node *getKey();
	skipping to change at line 334		skipping to change at line 349
	}		}
	/// @brief Represents a YAML map created from either a block map for a flow map.		/// @brief Represents a YAML map created from either a block map for a flow map.
	///		///
	/// This parses the YAML stream as increment() is called.		/// This parses the YAML stream as increment() is called.
	///		///
	/// Example:		/// Example:
	/// Name: _main		/// Name: _main
	/// Scope: Global		/// Scope: Global
	class MappingNode : public Node {		class MappingNode : public Node {
			virtual void anchor();
	public:		public:
	enum MappingType {		enum MappingType {
	MT_Block,		MT_Block,
	MT_Flow,		MT_Flow,
	MT_Inline ///< An inline mapping node is used for "[key: value]".		MT_Inline ///< An inline mapping node is used for "[key: value]".
	};		};
	MappingNode(OwningPtr<Document> &D, StringRef Anchor, MappingType MT)		MappingNode(OwningPtr<Document> &D, StringRef Anchor, StringRef Tag,
	: Node(NK_Mapping, D, Anchor)		MappingType MT)
	, Type(MT)		: Node(NK_Mapping, D, Anchor, Tag), Type(MT), IsAtBeginning(true),
	, IsAtBeginning(true)		IsAtEnd(false), CurrentEntry(0) {}
	, IsAtEnd(false)
	, CurrentEntry(0)
	{}
	friend class basic_collection_iterator<MappingNode, KeyValueNode>;		friend class basic_collection_iterator<MappingNode, KeyValueNode>;
	typedef basic_collection_iterator<MappingNode, KeyValueNode> iterator;		typedef basic_collection_iterator<MappingNode, KeyValueNode> iterator;
	template <class T> friend typename T::iterator yaml::begin(T &);		template <class T> friend typename T::iterator yaml::begin(T &);
	template <class T> friend void yaml::skip(T &);		template <class T> friend void yaml::skip(T &);
	iterator begin() {		iterator begin() {
	return yaml::begin(*this);		return yaml::begin(*this);
	}		}
	skipping to change at line 386		skipping to change at line 399
	/// @brief Represents a YAML sequence created from either a block sequence for a		/// @brief Represents a YAML sequence created from either a block sequence for a
	/// flow sequence.		/// flow sequence.
	///		///
	/// This parses the YAML stream as increment() is called.		/// This parses the YAML stream as increment() is called.
	///		///
	/// Example:		/// Example:
	/// - Hello		/// - Hello
	/// - World		/// - World
	class SequenceNode : public Node {		class SequenceNode : public Node {
			virtual void anchor();
	public:		public:
	enum SequenceType {		enum SequenceType {
	ST_Block,		ST_Block,
	ST_Flow,		ST_Flow,
	// Use for:		// Use for:
	//		//
	// key:		// key:
	// - val1		// - val1
	// - val2		// - val2
	//		//
	// As a BlockMappingEntry and BlockEnd are not created in this case.		// As a BlockMappingEntry and BlockEnd are not created in this case.
	ST_Indentless		ST_Indentless
	};		};
	SequenceNode(OwningPtr<Document> &D, StringRef Anchor, SequenceType ST)		SequenceNode(OwningPtr<Document> &D, StringRef Anchor, StringRef Tag,
	: Node(NK_Sequence, D, Anchor)		SequenceType ST)
	, SeqType(ST)		: Node(NK_Sequence, D, Anchor, Tag), SeqType(ST), IsAtBeginning(true)
	, IsAtBeginning(true)		,
	, IsAtEnd(false)		IsAtEnd(false),
	, WasPreviousTokenFlowEntry(true) // Start with an imaginary ','.		WasPreviousTokenFlowEntry(true), // Start with an imaginary ','.
	, CurrentEntry(0)		CurrentEntry(0) {}
	{}
	friend class basic_collection_iterator<SequenceNode, Node>;		friend class basic_collection_iterator<SequenceNode, Node>;
	typedef basic_collection_iterator<SequenceNode, Node> iterator;		typedef basic_collection_iterator<SequenceNode, Node> iterator;
	template <class T> friend typename T::iterator yaml::begin(T &);		template <class T> friend typename T::iterator yaml::begin(T &);
	template <class T> friend void yaml::skip(T &);		template <class T> friend void yaml::skip(T &);
	void increment();		void increment();
	iterator begin() {		iterator begin() {
	return yaml::begin(*this);		return yaml::begin(*this);
	skipping to change at line 443		skipping to change at line 455
	bool IsAtEnd;		bool IsAtEnd;
	bool WasPreviousTokenFlowEntry;		bool WasPreviousTokenFlowEntry;
	Node *CurrentEntry;		Node *CurrentEntry;
	};		};
	/// @brief Represents an alias to a Node with an anchor.		/// @brief Represents an alias to a Node with an anchor.
	///		///
	/// Example:		/// Example:
	/// *AnchorName		/// *AnchorName
	class AliasNode : public Node {		class AliasNode : public Node {
			virtual void anchor();
	public:		public:
	AliasNode(OwningPtr<Document> &D, StringRef Val)		AliasNode(OwningPtr<Document> &D, StringRef Val)
	: Node(NK_Alias, D, StringRef()), Name(Val) {}		: Node(NK_Alias, D, StringRef(), StringRef()), Name(Val) {}
	StringRef getName() const { return Name; }		StringRef getName() const { return Name; }
	Node *getTarget();		Node *getTarget();
	static inline bool classof(const Node *N) {		static inline bool classof(const Node *N) {
	return N->getType() == NK_Alias;		return N->getType() == NK_Alias;
	}		}
	private:		private:
	StringRef Name;		StringRef Name;
	skipping to change at line 478		skipping to change at line 491
	/// more. Return false otherwise.		/// more. Return false otherwise.
	bool skip();		bool skip();
	/// @brief Parse and return the root level node.		/// @brief Parse and return the root level node.
	Node *getRoot() {		Node *getRoot() {
	if (Root)		if (Root)
	return Root;		return Root;
	return Root = parseBlockNode();		return Root = parseBlockNode();
	}		}
			const std::map<StringRef, StringRef> &getTagMap() const {
			return TagMap;
			}
	private:		private:
	friend class Node;		friend class Node;
	friend class document_iterator;		friend class document_iterator;
	/// @brief Stream to read tokens from.		/// @brief Stream to read tokens from.
	Stream &stream;		Stream &stream;
	/// @brief Used to allocate nodes to. All are destroyed without calling t heir		/// @brief Used to allocate nodes to. All are destroyed without calling t heir
	/// destructor when the document is destroyed.		/// destructor when the document is destroyed.
	BumpPtrAllocator NodeAllocator;		BumpPtrAllocator NodeAllocator;
	/// @brief The root node. Used to support skipping a partially parsed		/// @brief The root node. Used to support skipping a partially parsed
	/// document.		/// document.
	Node *Root;		Node *Root;
			/// \brief Maps tag prefixes to their expansion.
			std::map<StringRef, StringRef> TagMap;
	Token &peekNext();		Token &peekNext();
	Token getNext();		Token getNext();
	void setError(const Twine &Message, Token &Location) const;		void setError(const Twine &Message, Token &Location) const;
	bool failed() const;		bool failed() const;
	void handleTagDirective(const Token &Tag) {
	// TODO: Track tags.
	}
	/// @brief Parse %BLAH directives and return true if any were encountered .		/// @brief Parse %BLAH directives and return true if any were encountered .
	bool parseDirectives();		bool parseDirectives();
			/// \brief Parse %YAML
			void parseYAMLDirective();
			/// \brief Parse %TAG
			void parseTAGDirective();
	/// @brief Consume the next token and error if it is not \a TK.		/// @brief Consume the next token and error if it is not \a TK.
	bool expectToken(int TK);		bool expectToken(int TK);
	};		};
	/// @brief Iterator abstraction for Documents over a Stream.		/// @brief Iterator abstraction for Documents over a Stream.
	class document_iterator {		class document_iterator {
	public:		public:
	document_iterator() : Doc(0) {}		document_iterator() : Doc(0) {}
	document_iterator(OwningPtr<Document> &D) : Doc(&D) {}		document_iterator(OwningPtr<Document> &D) : Doc(&D) {}
	bool operator ==(const document_iterator &Other) {		bool operator ==(const document_iterator &Other) {
	if (isAtEnd() || Other.isAtEnd())		if (isAtEnd() || Other.isAtEnd())
	return isAtEnd() && Other.isAtEnd();		return isAtEnd() && Other.isAtEnd();
	return *Doc == *Other.Doc;		return Doc == Other.Doc;
	}		}
	bool operator !=(const document_iterator &Other) {		bool operator !=(const document_iterator &Other) {
	return !(*this == Other);		return !(*this == Other);
	}		}
	document_iterator operator ++() {		document_iterator operator ++() {
	assert(Doc != 0 && "incrementing iterator past the end.");		assert(Doc != 0 && "incrementing iterator past the end.");
	if (!(*Doc)->skip()) {		if (!(*Doc)->skip()) {
	Doc->reset(0);		Doc->reset(0);
	} else {		} else {
	skipping to change at line 546		skipping to change at line 568
	Document &operator *() {		Document &operator *() {
	return *Doc->get();		return *Doc->get();
	}		}
	OwningPtr<Document> &operator ->() {		OwningPtr<Document> &operator ->() {
	return *Doc;		return *Doc;
	}		}
	private:		private:
	bool isAtEnd() const {		bool isAtEnd() const {
	return Doc == 0 || *Doc == 0;		return !Doc || !*Doc;
	}		}
	OwningPtr<Document> *Doc;		OwningPtr<Document> *Doc;
	};		};
	}		}
	}		}
	#endif		#endif
End of changes. 24 change blocks.
	31 lines changed or deleted		55 lines changed or added

	YAMLTraits.h		YAMLTraits.h
	skipping to change at line 16		skipping to change at line 16
	// License. See LICENSE.TXT for details.		// License. See LICENSE.TXT for details.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_SUPPORT_YAMLTRAITS_H		#ifndef LLVM_SUPPORT_YAMLTRAITS_H
	#define LLVM_SUPPORT_YAMLTRAITS_H		#define LLVM_SUPPORT_YAMLTRAITS_H
	#include "llvm/ADT/DenseMap.h"		#include "llvm/ADT/DenseMap.h"
	#include "llvm/ADT/DenseMapInfo.h"		#include "llvm/ADT/DenseMapInfo.h"
	#include "llvm/ADT/SmallVector.h"		#include "llvm/ADT/SmallVector.h"
	#include "llvm/ADT/StringExtras.h"		#include "llvm/ADT/StringMap.h"
	#include "llvm/ADT/StringRef.h"		#include "llvm/ADT/StringRef.h"
	#include "llvm/ADT/StringSwitch.h"		#include "llvm/ADT/StringSwitch.h"
	#include "llvm/ADT/Twine.h"		#include "llvm/ADT/Twine.h"
			#include "llvm/Support/Casting.h"
	#include "llvm/Support/Compiler.h"		#include "llvm/Support/Compiler.h"
	#include "llvm/Support/SourceMgr.h"		#include "llvm/Support/SourceMgr.h"
	#include "llvm/Support/YAMLParser.h"		#include "llvm/Support/YAMLParser.h"
	#include "llvm/Support/raw_ostream.h"		#include "llvm/Support/raw_ostream.h"
	#include "llvm/Support/system_error.h"		#include "llvm/Support/system_error.h"
	#include "llvm/Support/type_traits.h"		#include "llvm/Support/type_traits.h"
	namespace llvm {		namespace llvm {
	namespace yaml {		namespace yaml {
	skipping to change at line 297		skipping to change at line 298
	&& !has_SequenceTraits<T>::value		&& !has_SequenceTraits<T>::value
	&& !has_DocumentListTraits<T>::value > {};		&& !has_DocumentListTraits<T>::value > {};
	// Base class for Input and Output.		// Base class for Input and Output.
	class IO {		class IO {
	public:		public:
	IO(void *Ctxt=NULL);		IO(void *Ctxt=NULL);
	virtual ~IO();		virtual ~IO();
	virtual bool outputting() = 0;		virtual bool outputting() const = 0;
	virtual unsigned beginSequence() = 0;		virtual unsigned beginSequence() = 0;
	virtual bool preflightElement(unsigned, void *&) = 0;		virtual bool preflightElement(unsigned, void *&) = 0;
	virtual void postflightElement(void*) = 0;		virtual void postflightElement(void*) = 0;
	virtual void endSequence() = 0;		virtual void endSequence() = 0;
			virtual bool canElideEmptySequence() = 0;
	virtual unsigned beginFlowSequence() = 0;		virtual unsigned beginFlowSequence() = 0;
	virtual bool preflightFlowElement(unsigned, void *&) = 0;		virtual bool preflightFlowElement(unsigned, void *&) = 0;
	virtual void postflightFlowElement(void*) = 0;		virtual void postflightFlowElement(void*) = 0;
	virtual void endFlowSequence() = 0;		virtual void endFlowSequence() = 0;
			virtual bool mapTag(StringRef Tag, bool Default=false) = 0;
	virtual void beginMapping() = 0;		virtual void beginMapping() = 0;
	virtual void endMapping() = 0;		virtual void endMapping() = 0;
	virtual bool preflightKey(const char*, bool, bool, bool &, void *&) = 0;		virtual bool preflightKey(const char*, bool, bool, bool &, void *&) = 0;
	virtual void postflightKey(void*) = 0;		virtual void postflightKey(void*) = 0;
	virtual void beginEnumScalar() = 0;		virtual void beginEnumScalar() = 0;
	virtual bool matchEnumScalar(const char*, bool) = 0;		virtual bool matchEnumScalar(const char*, bool) = 0;
	virtual void endEnumScalar() = 0;		virtual void endEnumScalar() = 0;
	virtual bool beginBitSetScalar(bool &) = 0;		virtual bool beginBitSetScalar(bool &) = 0;
	skipping to change at line 368		skipping to change at line 371
	template <typename T>		template <typename T>
	void mapRequired(const char* Key, T& Val) {		void mapRequired(const char* Key, T& Val) {
	this->processKey(Key, Val, true);		this->processKey(Key, Val, true);
	}		}
	template <typename T>		template <typename T>
	typename llvm::enable_if_c<has_SequenceTraits<T>::value,void>::type		typename llvm::enable_if_c<has_SequenceTraits<T>::value,void>::type
	mapOptional(const char* Key, T& Val) {		mapOptional(const char* Key, T& Val) {
	// omit key/value instead of outputting empty sequence		// omit key/value instead of outputting empty sequence
	if ( this->outputting() && !(Val.begin() != Val.end()) )		if ( this->canElideEmptySequence() && !(Val.begin() != Val.end()) )
	return;		return;
	this->processKey(Key, Val, false);		this->processKey(Key, Val, false);
	}		}
	template <typename T>		template <typename T>
	typename llvm::enable_if_c<!has_SequenceTraits<T>::value,void>::type		typename llvm::enable_if_c<!has_SequenceTraits<T>::value,void>::type
	mapOptional(const char* Key, T& Val) {		mapOptional(const char* Key, T& Val) {
	this->processKey(Key, Val, false);		this->processKey(Key, Val, false);
	}		}
	skipping to change at line 651		skipping to change at line 654
	/// It works by using YAMLParser to do a syntax parse of the entire yaml		/// It works by using YAMLParser to do a syntax parse of the entire yaml
	/// document, then the Input class builds a graph of HNodes which wraps		/// document, then the Input class builds a graph of HNodes which wraps
	/// each yaml Node. The extra layer is buffering. The low level yaml		/// each yaml Node. The extra layer is buffering. The low level yaml
	/// parser only lets you look at each node once. The buffering layer lets		/// parser only lets you look at each node once. The buffering layer lets
	/// you search and interate multiple times. This is necessary because		/// you search and interate multiple times. This is necessary because
	/// the mapRequired() method calls may not be in the same order		/// the mapRequired() method calls may not be in the same order
	/// as the keys in the document.		/// as the keys in the document.
	///		///
	class Input : public IO {		class Input : public IO {
	public:		public:
	// Construct a yaml Input object from a StringRef and optional user-data.		// Construct a yaml Input object from a StringRef and optional
	Input(StringRef InputContent, void *Ctxt=NULL);		// user-data. The DiagHandler can be specified to provide
			// alternative error reporting.
			Input(StringRef InputContent,
			void *Ctxt = NULL,
			SourceMgr::DiagHandlerTy DiagHandler = NULL,
			void *DiagHandlerCtxt = NULL);
	~Input();		~Input();
	// Check if there was an syntax or semantic error during parsing.		// Check if there was an syntax or semantic error during parsing.
	llvm::error_code error();		llvm::error_code error();
	// To set alternate error reporting.		static bool classof(const IO *io) { return !io->outputting(); }
	void setDiagHandler(llvm::SourceMgr::DiagHandlerTy Handler, void *Ctxt =
	0);
	private:		private:
	virtual bool outputting();		virtual bool outputting() const;
			virtual bool mapTag(StringRef, bool);
	virtual void beginMapping();		virtual void beginMapping();
	virtual void endMapping();		virtual void endMapping();
	virtual bool preflightKey(const char *, bool, bool, bool &, void *&);		virtual bool preflightKey(const char *, bool, bool, bool &, void *&);
	virtual void postflightKey(void *);		virtual void postflightKey(void *);
	virtual unsigned beginSequence();		virtual unsigned beginSequence();
	virtual void endSequence();		virtual void endSequence();
	virtual bool preflightElement(unsigned index, void *&);		virtual bool preflightElement(unsigned index, void *&);
	virtual void postflightElement(void *);		virtual void postflightElement(void *);
	virtual unsigned beginFlowSequence();		virtual unsigned beginFlowSequence();
	virtual bool preflightFlowElement(unsigned , void *&);		virtual bool preflightFlowElement(unsigned , void *&);
	virtual void postflightFlowElement(void *);		virtual void postflightFlowElement(void *);
	virtual void endFlowSequence();		virtual void endFlowSequence();
	virtual void beginEnumScalar();		virtual void beginEnumScalar();
	virtual bool matchEnumScalar(const char*, bool);		virtual bool matchEnumScalar(const char*, bool);
	virtual void endEnumScalar();		virtual void endEnumScalar();
	virtual bool beginBitSetScalar(bool &);		virtual bool beginBitSetScalar(bool &);
	virtual bool bitSetMatch(const char *, bool );		virtual bool bitSetMatch(const char *, bool );
	virtual void endBitSetScalar();		virtual void endBitSetScalar();
	virtual void scalarString(StringRef &);		virtual void scalarString(StringRef &);
	virtual void setError(const Twine &message);		virtual void setError(const Twine &message);
			virtual bool canElideEmptySequence();
	class HNode {		class HNode {
			virtual void anchor();
	public:		public:
	HNode(Node *n) : _node(n) { }		HNode(Node *n) : _node(n) { }
	virtual ~HNode() { }		virtual ~HNode() { }
	static inline bool classof(const HNode *) { return true; }		static inline bool classof(const HNode *) { return true; }
	Node *_node;		Node *_node;
	};		};
	class EmptyHNode : public HNode {		class EmptyHNode : public HNode {
			virtual void anchor();
	public:		public:
	EmptyHNode(Node *n) : HNode(n) { }		EmptyHNode(Node *n) : HNode(n) { }
	virtual ~EmptyHNode() {}
	static inline bool classof(const HNode *n) {		static inline bool classof(const HNode *n) {
	return NullNode::classof(n->_node);		return NullNode::classof(n->_node);
	}		}
	static inline bool classof(const EmptyHNode *) { return true; }		static inline bool classof(const EmptyHNode *) { return true; }
	};		};
	class ScalarHNode : public HNode {		class ScalarHNode : public HNode {
			virtual void anchor();
	public:		public:
	ScalarHNode(Node *n, StringRef s) : HNode(n), _value(s) { }		ScalarHNode(Node *n, StringRef s) : HNode(n), _value(s) { }
	virtual ~ScalarHNode() { }
	StringRef value() const { return _value; }		StringRef value() const { return _value; }
	static inline bool classof(const HNode *n) {		static inline bool classof(const HNode *n) {
	return ScalarNode::classof(n->_node);		return ScalarNode::classof(n->_node);
	}		}
	static inline bool classof(const ScalarHNode *) { return true; }		static inline bool classof(const ScalarHNode *) { return true; }
	protected:		protected:
	StringRef _value;		StringRef _value;
	};		};
	skipping to change at line 728		skipping to change at line 738
	class MapHNode : public HNode {		class MapHNode : public HNode {
	public:		public:
	MapHNode(Node *n) : HNode(n) { }		MapHNode(Node *n) : HNode(n) { }
	virtual ~MapHNode();		virtual ~MapHNode();
	static inline bool classof(const HNode *n) {		static inline bool classof(const HNode *n) {
	return MappingNode::classof(n->_node);		return MappingNode::classof(n->_node);
	}		}
	static inline bool classof(const MapHNode *) { return true; }		static inline bool classof(const MapHNode *) { return true; }
	struct StrMappingInfo {		typedef llvm::StringMap<HNode*> NameToNode;
	static StringRef getEmptyKey() { return StringRef(); }
	static StringRef getTombstoneKey() { return StringRef(" ", 0); }
	static unsigned getHashValue(StringRef const val) {
	return llvm::HashString(val
	); }
	static bool isEqual(StringRef const lhs,
	StringRef const rhs) { return lhs.equals(rhs); }
	};
	typedef llvm::DenseMap<StringRef, HNode*, StrMappingInfo> NameToNode;
	bool isValidKey(StringRef key);		bool isValidKey(StringRef key);
	NameToNode Mapping;		NameToNode Mapping;
	llvm::SmallVector<const char*, 6> ValidKeys;		llvm::SmallVector<const char*, 6> ValidKeys;
	};		};
	class SequenceHNode : public HNode {		class SequenceHNode : public HNode {
	public:		public:
	SequenceHNode(Node *n) : HNode(n) { }		SequenceHNode(Node *n) : HNode(n) { }
	skipping to change at line 788		skipping to change at line 790
	///		///
	/// The Output class is used to generate a yaml document from in-memory str ucts		/// The Output class is used to generate a yaml document from in-memory str ucts
	/// and vectors.		/// and vectors.
	///		///
	class Output : public IO {		class Output : public IO {
	public:		public:
	Output(llvm::raw_ostream &, void *Ctxt=NULL);		Output(llvm::raw_ostream &, void *Ctxt=NULL);
	virtual ~Output();		virtual ~Output();
	virtual bool outputting();		static bool classof(const IO *io) { return io->outputting(); }
			virtual bool outputting() const;
			virtual bool mapTag(StringRef, bool);
	virtual void beginMapping();		virtual void beginMapping();
	virtual void endMapping();		virtual void endMapping();
	virtual bool preflightKey(const char *key, bool, bool, bool &, void *&);		virtual bool preflightKey(const char *key, bool, bool, bool &, void *&);
	virtual void postflightKey(void *);		virtual void postflightKey(void *);
	virtual unsigned beginSequence();		virtual unsigned beginSequence();
	virtual void endSequence();		virtual void endSequence();
	virtual bool preflightElement(unsigned, void *&);		virtual bool preflightElement(unsigned, void *&);
	virtual void postflightElement(void *);		virtual void postflightElement(void *);
	virtual unsigned beginFlowSequence();		virtual unsigned beginFlowSequence();
	virtual bool preflightFlowElement(unsigned, void *&);		virtual bool preflightFlowElement(unsigned, void *&);
	virtual void postflightFlowElement(void *);		virtual void postflightFlowElement(void *);
	virtual void endFlowSequence();		virtual void endFlowSequence();
	virtual void beginEnumScalar();		virtual void beginEnumScalar();
	virtual bool matchEnumScalar(const char*, bool);		virtual bool matchEnumScalar(const char*, bool);
	virtual void endEnumScalar();		virtual void endEnumScalar();
	virtual bool beginBitSetScalar(bool &);		virtual bool beginBitSetScalar(bool &);
	virtual bool bitSetMatch(const char *, bool );		virtual bool bitSetMatch(const char *, bool );
	virtual void endBitSetScalar();		virtual void endBitSetScalar();
	virtual void scalarString(StringRef &);		virtual void scalarString(StringRef &);
	virtual void setError(const Twine &message);		virtual void setError(const Twine &message);
			virtual bool canElideEmptySequence();
	public:		public:
	// These are only used by operator<<. They could be private		// These are only used by operator<<. They could be private
	// if that templated operator could be made a friend.		// if that templated operator could be made a friend.
	void beginDocuments();		void beginDocuments();
	bool preflightDocument(unsigned);		bool preflightDocument(unsigned);
	void postflightDocument();		void postflightDocument();
	void endDocuments();		void endDocuments();
	private:		private:
	void output(StringRef s);		void output(StringRef s);
	skipping to change at line 924		skipping to change at line 929
	yamlize(yin, docMap, true);		yamlize(yin, docMap, true);
	return yin;		return yin;
	}		}
	// Define non-member operator>> so that Input can stream in a sequence as		// Define non-member operator>> so that Input can stream in a sequence as
	// a document.		// a document.
	template <typename T>		template <typename T>
	inline		inline
	typename llvm::enable_if_c<has_SequenceTraits<T>::value,Input &>::type		typename llvm::enable_if_c<has_SequenceTraits<T>::value,Input &>::type
	operator>>(Input &yin, T &docSeq) {		operator>>(Input &yin, T &docSeq) {
	yin.setCurrentDocument();		if (yin.setCurrentDocument())
	yamlize(yin, docSeq, true);		yamlize(yin, docSeq, true);
	return yin;		return yin;
	}		}
	// Provide better error message about types missing a trait specialization		// Provide better error message about types missing a trait specialization
	template <typename T>		template <typename T>
	inline		inline
	typename llvm::enable_if_c<missingTraits<T>::value,Input &>::type		typename llvm::enable_if_c<missingTraits<T>::value,Input &>::type
	operator>>(Input &yin, T &docSeq) {		operator>>(Input &yin, T &docSeq) {
	char missing_yaml_trait_for_type[sizeof(MissingTrait<T>)];		char missing_yaml_trait_for_type[sizeof(MissingTrait<T>)];
	return yin;		return yin;
End of changes. 19 change blocks.
	25 lines changed or deleted		28 lines changed or added

	config.h		config.h
	/* include/llvm/Config/config.h. Generated from config.h.in by configure. */		/* include/llvm/Config/config.h. Generated from config.h.in by configure. */
	/* include/llvm/Config/config.h.in. Generated from autoconf/configure.ac b y autoheader. */		/* include/llvm/Config/config.h.in. Generated from autoconf/configure.ac b y autoheader. */
	#ifndef CONFIG_H		#ifndef CONFIG_H
	#define CONFIG_H		#define CONFIG_H
			/* Define if building universal (internal helper macro) */
			/* #undef AC_APPLE_UNIVERSAL_BUILD */
	/* Bug report URL. */		/* Bug report URL. */
	#define BUG_REPORT_URL "http://llvm.org/bugs/"		#define BUG_REPORT_URL "http://llvm.org/bugs/"
	/* Define if we have libxml2 */		/* Define if we have libxml2 */
	#define CLANG_HAVE_LIBXML 1		#define CLANG_HAVE_LIBXML 1
	/* Relative directory for resource files */		/* Relative directory for resource files */
	#define CLANG_RESOURCE_DIR ""		#define CLANG_RESOURCE_DIR ""
	/* Directories clang will search for headers */		/* Directories clang will search for headers */
	#define C_INCLUDE_DIRS ""		#define C_INCLUDE_DIRS ""
	/* Default <path> to all compiler invocations for --sysroot=<path>. */		/* Default <path> to all compiler invocations for --sysroot=<path>. */
	#define DEFAULT_SYSROOT ""		#define DEFAULT_SYSROOT ""
	/* Define if you want backtraces on crash */		/* Define if you want backtraces on crash */
	#define ENABLE_BACKTRACES 1		#define ENABLE_BACKTRACES 1
			/* Define to enable crash handling overrides */
			#define ENABLE_CRASH_OVERRIDES 1
	/* Define if position independent code is enabled */		/* Define if position independent code is enabled */
	#define ENABLE_PIC 1		#define ENABLE_PIC 1
	/* Define if timestamp information (e.g., __DATE__) is allowed */		/* Define if timestamp information (e.g., __DATE__) is allowed */
	#define ENABLE_TIMESTAMPS 1		#define ENABLE_TIMESTAMPS 1
	/* Directory where gcc is installed. */		/* Directory where gcc is installed. */
	#define GCC_INSTALL_PREFIX ""		#define GCC_INSTALL_PREFIX ""
	/* Define to 1 if you have the `arc4random' function. */		/* Define to 1 if you have the `arc4random' function. */
	skipping to change at line 55		skipping to change at line 61
	/* Define to 1 if you have the `argz_insert' function. */		/* Define to 1 if you have the `argz_insert' function. */
	#define HAVE_ARGZ_INSERT 1		#define HAVE_ARGZ_INSERT 1
	/* Define to 1 if you have the `argz_next' function. */		/* Define to 1 if you have the `argz_next' function. */
	#define HAVE_ARGZ_NEXT 1		#define HAVE_ARGZ_NEXT 1
	/* Define to 1 if you have the `argz_stringify' function. */		/* Define to 1 if you have the `argz_stringify' function. */
	#define HAVE_ARGZ_STRINGIFY 1		#define HAVE_ARGZ_STRINGIFY 1
	/* Define to 1 if you have the <assert.h> header file. */
	#define HAVE_ASSERT_H 1
	/* Define to 1 if you have the `backtrace' function. */		/* Define to 1 if you have the `backtrace' function. */
	#define HAVE_BACKTRACE 1		#define HAVE_BACKTRACE 1
	/* Define to 1 if you have the `bcopy' function. */
	/* #undef HAVE_BCOPY */
	/* Define to 1 if you have the `ceilf' function. */		/* Define to 1 if you have the `ceilf' function. */
	#define HAVE_CEILF 1		#define HAVE_CEILF 1
	/* Define if the neat program is available */		/* Define if the neat program is available */
	#define HAVE_CIRCO 1		#define HAVE_CIRCO 1
	/* Define to 1 if you have the `closedir' function. */		/* Define to 1 if you have the `closedir' function. */
	#define HAVE_CLOSEDIR 1		#define HAVE_CLOSEDIR 1
	/* Define to 1 if you have the <CrashReporterClient.h> header file. */		/* Define to 1 if you have the <CrashReporterClient.h> header file. */
	/* #undef HAVE_CRASHREPORTERCLIENT_H */		/* #undef HAVE_CRASHREPORTERCLIENT_H */
	/* can use __crashreporter_info__ */		/* can use __crashreporter_info__ */
	#define HAVE_CRASHREPORTER_INFO 0		#define HAVE_CRASHREPORTER_INFO 0
	/* Define to 1 if you have the <ctype.h> header file. */
	#define HAVE_CTYPE_H 1
	/* Define to 1 if you have the <cxxabi.h> header file. */		/* Define to 1 if you have the <cxxabi.h> header file. */
	#define HAVE_CXXABI_H 1		#define HAVE_CXXABI_H 1
	/* Define to 1 if you have the declaration of `FE_ALL_EXCEPT', and to 0 if you		/* Define to 1 if you have the declaration of `FE_ALL_EXCEPT', and to 0 if you
	don't. */		don't. */
	#define HAVE_DECL_FE_ALL_EXCEPT 1		#define HAVE_DECL_FE_ALL_EXCEPT 1
	/* Define to 1 if you have the declaration of `FE_INEXACT', and to 0 if you		/* Define to 1 if you have the declaration of `FE_INEXACT', and to 0 if you
	don't. */		don't. */
	#define HAVE_DECL_FE_INEXACT 1		#define HAVE_DECL_FE_INEXACT 1
	skipping to change at line 104		skipping to change at line 101
	don't. */		don't. */
	#define HAVE_DECL_STRERROR_S 0		#define HAVE_DECL_STRERROR_S 0
	/* Define to 1 if you have the <dirent.h> header file, and it defines `DIR' .		/* Define to 1 if you have the <dirent.h> header file, and it defines `DIR' .
	*/		*/
	#define HAVE_DIRENT_H 1		#define HAVE_DIRENT_H 1
	/* Define if you have the GNU dld library. */		/* Define if you have the GNU dld library. */
	/* #undef HAVE_DLD */		/* #undef HAVE_DLD */
	/* Define to 1 if you have the <dld.h> header file. */
	/* #undef HAVE_DLD_H */
	/* Define to 1 if you have the `dlerror' function. */		/* Define to 1 if you have the `dlerror' function. */
	#define HAVE_DLERROR 1		#define HAVE_DLERROR 1
	/* Define to 1 if you have the <dlfcn.h> header file. */		/* Define to 1 if you have the <dlfcn.h> header file. */
	#define HAVE_DLFCN_H 1		#define HAVE_DLFCN_H 1
	/* Define if dlopen() is available on this platform. */		/* Define if dlopen() is available on this platform. */
	#define HAVE_DLOPEN 1		#define HAVE_DLOPEN 1
	/* Define to 1 if you have the <dl.h> header file. */
	/* #undef HAVE_DL_H */
	/* Define if the dot program is available */		/* Define if the dot program is available */
	#define HAVE_DOT 1		#define HAVE_DOT 1
	/* Define if the dotty program is available */		/* Define if the dotty program is available */
	#define HAVE_DOTTY 1		#define HAVE_DOTTY 1
	/* Define if you have the _dyld_func_lookup function. */		/* Define if you have the _dyld_func_lookup function. */
	/* #undef HAVE_DYLD */		/* #undef HAVE_DYLD */
	/* Define to 1 if you have the <errno.h> header file. */		/* Define to 1 if you have the <errno.h> header file. */
	skipping to change at line 170		skipping to change at line 161
	/* Set to 1 if the finite function is found in <ieeefp.h> */		/* Set to 1 if the finite function is found in <ieeefp.h> */
	/* #undef HAVE_FINITE_IN_IEEEFP_H */		/* #undef HAVE_FINITE_IN_IEEEFP_H */
	/* Define to 1 if you have the `floorf' function. */		/* Define to 1 if you have the `floorf' function. */
	#define HAVE_FLOORF 1		#define HAVE_FLOORF 1
	/* Define to 1 if you have the `fmodf' function. */		/* Define to 1 if you have the `fmodf' function. */
	#define HAVE_FMODF 1		#define HAVE_FMODF 1
			/* Define to 1 if you have the `futimens' function. */
			#define HAVE_FUTIMENS 1
			/* Define to 1 if you have the `futimes' function. */
			#define HAVE_FUTIMES 1
	/* Define to 1 if you have the `getcwd' function. */		/* Define to 1 if you have the `getcwd' function. */
	#define HAVE_GETCWD 1		#define HAVE_GETCWD 1
	/* Define to 1 if you have the `getpagesize' function. */		/* Define to 1 if you have the `getpagesize' function. */
	#define HAVE_GETPAGESIZE 1		#define HAVE_GETPAGESIZE 1
	/* Define to 1 if you have the `getrlimit' function. */		/* Define to 1 if you have the `getrlimit' function. */
	#define HAVE_GETRLIMIT 1		#define HAVE_GETRLIMIT 1
	/* Define to 1 if you have the `getrusage' function. */		/* Define to 1 if you have the `getrusage' function. */
	skipping to change at line 191		skipping to change at line 188
	/* Define to 1 if you have the `gettimeofday' function. */		/* Define to 1 if you have the `gettimeofday' function. */
	#define HAVE_GETTIMEOFDAY 1		#define HAVE_GETTIMEOFDAY 1
	/* Define if the Graphviz program is available */		/* Define if the Graphviz program is available */
	/* #undef HAVE_GRAPHVIZ */		/* #undef HAVE_GRAPHVIZ */
	/* Define if the gv program is available */		/* Define if the gv program is available */
	/* #undef HAVE_GV */		/* #undef HAVE_GV */
	/* Define to 1 if you have the `index' function. */
	/* #undef HAVE_INDEX */
	/* Define to 1 if the system has the type `int64_t'. */		/* Define to 1 if the system has the type `int64_t'. */
	#define HAVE_INT64_T 1		#define HAVE_INT64_T 1
	/* Define to 1 if you have the <inttypes.h> header file. */		/* Define to 1 if you have the <inttypes.h> header file. */
	#define HAVE_INTTYPES_H 1		#define HAVE_INTTYPES_H 1
	/* Define to 1 if you have the `isatty' function. */		/* Define to 1 if you have the `isatty' function. */
	#define HAVE_ISATTY 1		#define HAVE_ISATTY 1
	/* Set to 1 if the isinf function is found in <cmath> */		/* Set to 1 if the isinf function is found in <cmath> */
	skipping to change at line 230		skipping to change at line 224
	/* Define to 1 if you have the `m' library (-lm). */		/* Define to 1 if you have the `m' library (-lm). */
	#define HAVE_LIBM 1		#define HAVE_LIBM 1
	/* Define to 1 if you have the `psapi' library (-lpsapi). */		/* Define to 1 if you have the `psapi' library (-lpsapi). */
	/* #undef HAVE_LIBPSAPI */		/* #undef HAVE_LIBPSAPI */
	/* Define to 1 if you have the `pthread' library (-lpthread). */		/* Define to 1 if you have the `pthread' library (-lpthread). */
	#define HAVE_LIBPTHREAD 1		#define HAVE_LIBPTHREAD 1
			/* Define to 1 if you have the `shell32' library (-lshell32). */
			/* #undef HAVE_LIBSHELL32 */
	/* Define to 1 if you have the `udis86' library (-ludis86). */		/* Define to 1 if you have the `udis86' library (-ludis86). */
	/* #undef HAVE_LIBUDIS86 */		/* #undef HAVE_LIBUDIS86 */
	/* Define to 1 if you have the `z' library (-lz). */		/* Define to 1 if you have the `z' library (-lz). */
	#define HAVE_LIBZ 1		#define HAVE_LIBZ 1
	/* Define to 1 if you have the <limits.h> header file. */		/* Define if you can use -rdynamic. */
	#define HAVE_LIMITS_H 1
	/* Define if you can use -Wl,-export-dynamic. */
	#define HAVE_LINK_EXPORT_DYNAMIC 1		#define HAVE_LINK_EXPORT_DYNAMIC 1
	/* Define to 1 if you have the <link.h> header file. */		/* Define to 1 if you have the <link.h> header file. */
	#define HAVE_LINK_H 1		#define HAVE_LINK_H 1
	/* Define if you can use -Wl,-R. to pass -R. to the linker, in order to add		/* Define if you can use -Wl,-R. to pass -R. to the linker, in order to add
	the current directory to the dynamic linker search path. */		the current directory to the dynamic linker search path. */
	#define HAVE_LINK_R 1		#define HAVE_LINK_R 1
	/* Define to 1 if you have the `log' function. */		/* Define to 1 if you have the `log' function. */
	skipping to change at line 279		skipping to change at line 273
	/* Define to 1 if you have the <malloc.h> header file. */		/* Define to 1 if you have the <malloc.h> header file. */
	#define HAVE_MALLOC_H 1		#define HAVE_MALLOC_H 1
	/* Define to 1 if you have the <malloc/malloc.h> header file. */		/* Define to 1 if you have the <malloc/malloc.h> header file. */
	/* #undef HAVE_MALLOC_MALLOC_H */		/* #undef HAVE_MALLOC_MALLOC_H */
	/* Define to 1 if you have the `malloc_zone_statistics' function. */		/* Define to 1 if you have the `malloc_zone_statistics' function. */
	/* #undef HAVE_MALLOC_ZONE_STATISTICS */		/* #undef HAVE_MALLOC_ZONE_STATISTICS */
	/* Define to 1 if you have the `memcpy' function. */
	#define HAVE_MEMCPY 1
	/* Define to 1 if you have the `memmove' function. */
	#define HAVE_MEMMOVE 1
	/* Define to 1 if you have the <memory.h> header file. */		/* Define to 1 if you have the <memory.h> header file. */
	#define HAVE_MEMORY_H 1		#define HAVE_MEMORY_H 1
	/* Define to 1 if you have the `mkdtemp' function. */		/* Define to 1 if you have the `mkdtemp' function. */
	#define HAVE_MKDTEMP 1		#define HAVE_MKDTEMP 1
	/* Define to 1 if you have the `mkstemp' function. */		/* Define to 1 if you have the `mkstemp' function. */
	#define HAVE_MKSTEMP 1		#define HAVE_MKSTEMP 1
	/* Define to 1 if you have the `mktemp' function. */		/* Define to 1 if you have the `mktemp' function. */
	skipping to change at line 355		skipping to change at line 343
	/* Define to 1 if srand48/lrand48/drand48 exist in <stdlib.h> */		/* Define to 1 if srand48/lrand48/drand48 exist in <stdlib.h> */
	#define HAVE_RAND48 1		#define HAVE_RAND48 1
	/* Define to 1 if you have the `readdir' function. */		/* Define to 1 if you have the `readdir' function. */
	#define HAVE_READDIR 1		#define HAVE_READDIR 1
	/* Define to 1 if you have the `realpath' function. */		/* Define to 1 if you have the `realpath' function. */
	#define HAVE_REALPATH 1		#define HAVE_REALPATH 1
	/* Define to 1 if you have the `rindex' function. */
	/* #undef HAVE_RINDEX */
	/* Define to 1 if you have the `rintf' function. */		/* Define to 1 if you have the `rintf' function. */
	#define HAVE_RINTF 1		#define HAVE_RINTF 1
	/* Define to 1 if you have the `round' function. */		/* Define to 1 if you have the `round' function. */
	#define HAVE_ROUND 1		#define HAVE_ROUND 1
	/* Define to 1 if you have the `roundf' function. */		/* Define to 1 if you have the `roundf' function. */
	#define HAVE_ROUNDF 1		#define HAVE_ROUNDF 1
	/* Define to 1 if you have the `sbrk' function. */		/* Define to 1 if you have the `sbrk' function. */
	skipping to change at line 397		skipping to change at line 382
	/* Define to 1 if you have the <signal.h> header file. */		/* Define to 1 if you have the <signal.h> header file. */
	#define HAVE_SIGNAL_H 1		#define HAVE_SIGNAL_H 1
	/* Define to 1 if you have the `sigsetjmp' function. */		/* Define to 1 if you have the `sigsetjmp' function. */
	/* #undef HAVE_SIGSETJMP */		/* #undef HAVE_SIGSETJMP */
	/* Define to 1 if you have the <stdint.h> header file. */		/* Define to 1 if you have the <stdint.h> header file. */
	#define HAVE_STDINT_H 1		#define HAVE_STDINT_H 1
	/* Define to 1 if you have the <stdio.h> header file. */
	#define HAVE_STDIO_H 1
	/* Define to 1 if you have the <stdlib.h> header file. */		/* Define to 1 if you have the <stdlib.h> header file. */
	#define HAVE_STDLIB_H 1		#define HAVE_STDLIB_H 1
	/* Set to 1 if the std::isinf function is found in <cmath> */		/* Set to 1 if the std::isinf function is found in <cmath> */
	#define HAVE_STD_ISINF_IN_CMATH 1		#define HAVE_STD_ISINF_IN_CMATH 1
	/* Set to 1 if the std::isnan function is found in <cmath> */		/* Set to 1 if the std::isnan function is found in <cmath> */
	#define HAVE_STD_ISNAN_IN_CMATH 1		#define HAVE_STD_ISNAN_IN_CMATH 1
	/* Define to 1 if you have the `strchr' function. */
	#define HAVE_STRCHR 1
	/* Define to 1 if you have the `strcmp' function. */
	#define HAVE_STRCMP 1
	/* Define to 1 if you have the `strdup' function. */
	#define HAVE_STRDUP 1
	/* Define to 1 if you have the `strerror' function. */		/* Define to 1 if you have the `strerror' function. */
	#define HAVE_STRERROR 1		#define HAVE_STRERROR 1
	/* Define to 1 if you have the `strerror_r' function. */		/* Define to 1 if you have the `strerror_r' function. */
	#define HAVE_STRERROR_R 1		#define HAVE_STRERROR_R 1
	/* Define to 1 if you have the <strings.h> header file. */		/* Define to 1 if you have the <strings.h> header file. */
	#define HAVE_STRINGS_H 1		#define HAVE_STRINGS_H 1
	/* Define to 1 if you have the <string.h> header file. */		/* Define to 1 if you have the <string.h> header file. */
	#define HAVE_STRING_H 1		#define HAVE_STRING_H 1
	/* Define to 1 if you have the `strrchr' function. */
	#define HAVE_STRRCHR 1
	/* Define to 1 if you have the `strtof' function. */		/* Define to 1 if you have the `strtof' function. */
	#define HAVE_STRTOF 1		#define HAVE_STRTOF 1
	/* Define to 1 if you have the `strtoll' function. */		/* Define to 1 if you have the `strtoll' function. */
	#define HAVE_STRTOLL 1		#define HAVE_STRTOLL 1
	/* Define to 1 if you have the `strtoq' function. */		/* Define to 1 if you have the `strtoq' function. */
	#define HAVE_STRTOQ 1		#define HAVE_STRTOQ 1
	/* Define to 1 if you have the `sysconf' function. */		/* Define to 1 if you have the `sysconf' function. */
	#define HAVE_SYSCONF 1		#define HAVE_SYSCONF 1
	/* Define to 1 if you have the <sys/dir.h> header file, and it defines `DIR '.		/* Define to 1 if you have the <sys/dir.h> header file, and it defines `DIR '.
	*/		*/
	/* #undef HAVE_SYS_DIR_H */		/* #undef HAVE_SYS_DIR_H */
	/* Define to 1 if you have the <sys/dl.h> header file. */
	/* #undef HAVE_SYS_DL_H */
	/* Define to 1 if you have the <sys/ioctl.h> header file. */		/* Define to 1 if you have the <sys/ioctl.h> header file. */
	#define HAVE_SYS_IOCTL_H 1		#define HAVE_SYS_IOCTL_H 1
	/* Define to 1 if you have the <sys/mman.h> header file. */		/* Define to 1 if you have the <sys/mman.h> header file. */
	#define HAVE_SYS_MMAN_H 1		#define HAVE_SYS_MMAN_H 1
	/* Define to 1 if you have the <sys/ndir.h> header file, and it defines `DI R'.		/* Define to 1 if you have the <sys/ndir.h> header file, and it defines `DI R'.
	*/		*/
	/* #undef HAVE_SYS_NDIR_H */		/* #undef HAVE_SYS_NDIR_H */
	skipping to change at line 483		skipping to change at line 450
	/* Define to 1 if you have the <sys/types.h> header file. */		/* Define to 1 if you have the <sys/types.h> header file. */
	#define HAVE_SYS_TYPES_H 1		#define HAVE_SYS_TYPES_H 1
	/* Define to 1 if you have the <sys/uio.h> header file. */		/* Define to 1 if you have the <sys/uio.h> header file. */
	#define HAVE_SYS_UIO_H 1		#define HAVE_SYS_UIO_H 1
	/* Define to 1 if you have <sys/wait.h> that is POSIX.1 compatible. */		/* Define to 1 if you have <sys/wait.h> that is POSIX.1 compatible. */
	#define HAVE_SYS_WAIT_H 1		#define HAVE_SYS_WAIT_H 1
			/* Define if the setupterm() function is supported this platform. */
			#define HAVE_TERMINFO 1
	/* Define to 1 if you have the <termios.h> header file. */		/* Define to 1 if you have the <termios.h> header file. */
	#define HAVE_TERMIOS_H 1		#define HAVE_TERMIOS_H 1
	/* Define if the neat program is available */		/* Define if the neat program is available */
	#define HAVE_TWOPI 1		#define HAVE_TWOPI 1
	/* Define to 1 if the system has the type `uint64_t'. */		/* Define to 1 if the system has the type `uint64_t'. */
	#define HAVE_UINT64_T 1		#define HAVE_UINT64_T 1
	/* Define to 1 if you have the <unistd.h> header file. */		/* Define to 1 if you have the <unistd.h> header file. */
	skipping to change at line 504		skipping to change at line 474
	/* Define to 1 if you have the <utime.h> header file. */		/* Define to 1 if you have the <utime.h> header file. */
	#define HAVE_UTIME_H 1		#define HAVE_UTIME_H 1
	/* Define to 1 if the system has the type `u_int64_t'. */		/* Define to 1 if the system has the type `u_int64_t'. */
	/* #undef HAVE_U_INT64_T */		/* #undef HAVE_U_INT64_T */
	/* Define to 1 if you have the <valgrind/valgrind.h> header file. */		/* Define to 1 if you have the <valgrind/valgrind.h> header file. */
	#define HAVE_VALGRIND_VALGRIND_H 1		#define HAVE_VALGRIND_VALGRIND_H 1
	/* Define to 1 if you have the <windows.h> header file. */
	/* #undef HAVE_WINDOWS_H */
	/* Define to 1 if you have the `writev' function. */		/* Define to 1 if you have the `writev' function. */
	#define HAVE_WRITEV 1		#define HAVE_WRITEV 1
	/* Define if the xdot.py program is available */		/* Define if the xdot program is available */
	/* #undef HAVE_XDOT_PY */		/* #undef HAVE_XDOT */
	/* Define to 1 if you have the <zlib.h> header file. */		/* Define to 1 if you have the <zlib.h> header file. */
	#define HAVE_ZLIB_H 1		#define HAVE_ZLIB_H 1
	/* Have host's _alloca */		/* Have host's _alloca */
	/* #undef HAVE__ALLOCA */		/* #undef HAVE__ALLOCA */
	/* Have host's __alloca */		/* Have host's __alloca */
	/* #undef HAVE___ALLOCA */		/* #undef HAVE___ALLOCA */
	skipping to change at line 571		skipping to change at line 538
	/* Have host's __umoddi3 */		/* Have host's __umoddi3 */
	/* #undef HAVE___UMODDI3 */		/* #undef HAVE___UMODDI3 */
	/* Have host's ___chkstk */		/* Have host's ___chkstk */
	/* #undef HAVE____CHKSTK */		/* #undef HAVE____CHKSTK */
	/* Linker version detected at compile time. */		/* Linker version detected at compile time. */
	#define HOST_LINK_VERSION "2.21.52.0.2.20110610"		#define HOST_LINK_VERSION "2.21.52.0.2.20110610"
	/* Installation directory for binary executables */		/* Installation directory for binary executables */
	#define LLVM_BINDIR "/home/ut/testing/llvm/3.3/bin"		#define LLVM_BINDIR "/home/ut/testing/llvm/3.4/bin"
	/* Time at which LLVM was configured */		/* Time at which LLVM was configured */
	#define LLVM_CONFIGTIME "Tue Jun 18 03:16:37 MSK 2013"		#define LLVM_CONFIGTIME "Fri Jan 10 04:30:55 MSK 2014"
	/* Installation directory for data files */		/* Installation directory for data files */
	#define LLVM_DATADIR "/home/ut/testing/llvm/3.3/share/llvm"		#define LLVM_DATADIR "/home/ut/testing/llvm/3.4/share/llvm"
	/* Target triple LLVM will generate code for by default */		/* Target triple LLVM will generate code for by default */
	#define LLVM_DEFAULT_TARGET_TRIPLE "i686-pc-linux-gnu"		#define LLVM_DEFAULT_TARGET_TRIPLE "i686-pc-linux-gnu"
	/* Installation directory for documentation */		/* Installation directory for documentation */
	#define LLVM_DOCSDIR "/home/ut/testing/llvm/3.3/share/doc/llvm"		#define LLVM_DOCSDIR "/home/ut/testing/llvm/3.4/share/doc/llvm"
	/* Define if threads enabled */		/* Define if threads enabled */
	#define LLVM_ENABLE_THREADS 1		#define LLVM_ENABLE_THREADS 1
	/* Define if zlib is enabled */		/* Define if zlib is enabled */
	#define LLVM_ENABLE_ZLIB 1		#define LLVM_ENABLE_ZLIB 1
	/* Installation directory for config files */		/* Installation directory for config files */
	#define LLVM_ETCDIR "/home/ut/testing/llvm/3.3/etc/llvm"		#define LLVM_ETCDIR "/home/ut/testing/llvm/3.4/etc/llvm"
	/* Has gcc/MSVC atomic intrinsics */		/* Has gcc/MSVC atomic intrinsics */
	#define LLVM_HAS_ATOMICS 1		#define LLVM_HAS_ATOMICS 1
	/* Host triple LLVM will be executed on */		/* Host triple LLVM will be executed on */
	#define LLVM_HOST_TRIPLE "i686-pc-linux-gnu"		#define LLVM_HOST_TRIPLE "i686-pc-linux-gnu"
	/* Installation directory for include files */		/* Installation directory for include files */
	#define LLVM_INCLUDEDIR "/home/ut/testing/llvm/3.3/include"		#define LLVM_INCLUDEDIR "/home/ut/testing/llvm/3.4/include"
	/* Installation directory for .info files */		/* Installation directory for .info files */
	#define LLVM_INFODIR "/home/ut/testing/llvm/3.3/info"		#define LLVM_INFODIR "/home/ut/testing/llvm/3.4/info"
	/* Installation directory for libraries */
	#define LLVM_LIBDIR "/home/ut/testing/llvm/3.3/lib"
	/* Installation directory for man pages */		/* Installation directory for man pages */
	#define LLVM_MANDIR "/home/ut/testing/llvm/3.3/man"		#define LLVM_MANDIR "/home/ut/testing/llvm/3.4/man"
	/* LLVM architecture name for the native architecture, if available */		/* LLVM architecture name for the native architecture, if available */
	#define LLVM_NATIVE_ARCH X86		#define LLVM_NATIVE_ARCH X86
	/* LLVM name for the native AsmParser init function, if available */		/* LLVM name for the native AsmParser init function, if available */
	#define LLVM_NATIVE_ASMPARSER LLVMInitializeX86AsmParser		#define LLVM_NATIVE_ASMPARSER LLVMInitializeX86AsmParser
	/* LLVM name for the native AsmPrinter init function, if available */		/* LLVM name for the native AsmPrinter init function, if available */
	#define LLVM_NATIVE_ASMPRINTER LLVMInitializeX86AsmPrinter		#define LLVM_NATIVE_ASMPRINTER LLVMInitializeX86AsmPrinter
	skipping to change at line 663		skipping to change at line 627
	/* Define to path to gv program if found or 'echo gv' otherwise */		/* Define to path to gv program if found or 'echo gv' otherwise */
	/* #undef LLVM_PATH_GV */		/* #undef LLVM_PATH_GV */
	/* Define to path to neato program if found or 'echo neato' otherwise */		/* Define to path to neato program if found or 'echo neato' otherwise */
	#define LLVM_PATH_NEATO "/usr/bin/neato"		#define LLVM_PATH_NEATO "/usr/bin/neato"
	/* Define to path to twopi program if found or 'echo twopi' otherwise */		/* Define to path to twopi program if found or 'echo twopi' otherwise */
	#define LLVM_PATH_TWOPI "/usr/bin/twopi"		#define LLVM_PATH_TWOPI "/usr/bin/twopi"
	/* Define to path to xdot.py program if found or 'echo xdot.py' otherwise *		/* Define to path to xdot program if found or 'echo xdot' otherwise */
	/		/* #undef LLVM_PATH_XDOT */
	/* #undef LLVM_PATH_XDOT_PY */
	/* Installation prefix directory */		/* Installation prefix directory */
	#define LLVM_PREFIX "/home/ut/testing/llvm/3.3"		#define LLVM_PREFIX "/home/ut/testing/llvm/3.4"
	/* Define if we have the Intel JIT API runtime support library */		/* Define if we have the Intel JIT API runtime support library */
	#define LLVM_USE_INTEL_JITEVENTS 0		#define LLVM_USE_INTEL_JITEVENTS 0
	/* Define if we have the oprofile JIT-support library */		/* Define if we have the oprofile JIT-support library */
	#define LLVM_USE_OPROFILE 0		#define LLVM_USE_OPROFILE 0
	/* Major version of the LLVM API */		/* Major version of the LLVM API */
	#define LLVM_VERSION_MAJOR 3		#define LLVM_VERSION_MAJOR 3
	/* Minor version of the LLVM API */		/* Minor version of the LLVM API */
	#define LLVM_VERSION_MINOR 3		#define LLVM_VERSION_MINOR 4
	/* Define if the OS needs help to load dependent libraries for dlopen(). */		/* Define if the OS needs help to load dependent libraries for dlopen(). */
	/* #undef LTDL_DLOPEN_DEPLIBS */		/* #undef LTDL_DLOPEN_DEPLIBS */
	/* Define to the sub-directory in which libtool stores uninstalled librarie s.		/* Define to the sub-directory in which libtool stores uninstalled librarie s.
	*/		*/
	#define LTDL_OBJDIR ".libs/"		#define LTDL_OBJDIR ".libs/"
	/* Define to the name of the environment variable that determines the dynam
	ic
	library search path. */
	#define LTDL_SHLIBPATH_VAR "LD_LIBRARY_PATH"
	/* Define to the extension used for shared libraries, say, ".so". */		/* Define to the extension used for shared libraries, say, ".so". */
	#define LTDL_SHLIB_EXT ".so"		#define LTDL_SHLIB_EXT ".so"
	/* Define to the system default library search path. */		/* Define to the system default library search path. */
	#define LTDL_SYSSEARCHPATH "/lib:/usr/lib:/usr/lib/atlas-sse:/usr/lib/atlas -sse3:/usr/lib/atlas:/usr/lib/paraview-mpi"		#define LTDL_SYSSEARCHPATH "/lib:/usr/lib:/usr/lib/atlas-sse:/usr/lib/atlas -sse3:/usr/lib/atlas:/usr/lib/paraview-mpi"
	/* Define if /dev/zero should be used when mapping RWX memory, or undefine if		/* Define if /dev/zero should be used when mapping RWX memory, or undefine if
	its not necessary */		its not necessary */
	/* #undef NEED_DEV_ZERO_FOR_MMAP */		/* #undef NEED_DEV_ZERO_FOR_MMAP */
	/* Define if dlsym() requires a leading underscore in symbol names. */		/* Define if dlsym() requires a leading underscore in symbol names. */
	/* #undef NEED_USCORE */		/* #undef NEED_USCORE */
	/* Define to the address where bug reports for this package should be sent. */		/* Define to the address where bug reports for this package should be sent. */
	#define PACKAGE_BUGREPORT "http://llvm.org/bugs/"		#define PACKAGE_BUGREPORT "http://llvm.org/bugs/"
	/* Define to the full name of this package. */		/* Define to the full name of this package. */
	#define PACKAGE_NAME "LLVM"		#define PACKAGE_NAME "LLVM"
	/* Define to the full name and version of this package. */		/* Define to the full name and version of this package. */
	#define PACKAGE_STRING "LLVM 3.3"		#define PACKAGE_STRING "LLVM 3.4"
	/* Define to the one symbol short name of this package. */		/* Define to the one symbol short name of this package. */
	#define PACKAGE_TARNAME "llvm"		#define PACKAGE_TARNAME "llvm"
			/* Define to the home page for this package. */
			/* #undef PACKAGE_URL */
	/* Define to the version of this package. */		/* Define to the version of this package. */
	#define PACKAGE_VERSION "3.3"		#define PACKAGE_VERSION "3.4"
	/* Define as the return type of signal handlers (`int' or `void'). */		/* Define as the return type of signal handlers (`int' or `void'). */
	#define RETSIGTYPE void		#define RETSIGTYPE void
	/* Define to 1 if the `S_IS*' macros in <sys/stat.h> do not work properly. */		/* Define to 1 if the `S_IS*' macros in <sys/stat.h> do not work properly. */
	/* #undef STAT_MACROS_BROKEN */		/* #undef STAT_MACROS_BROKEN */
	/* Define to 1 if you have the ANSI C header files. */		/* Define to 1 if you have the ANSI C header files. */
	#define STDC_HEADERS 1		#define STDC_HEADERS 1
	skipping to change at line 741		skipping to change at line 704
	/* Define to 1 if your <sys/time.h> declares `struct tm'. */		/* Define to 1 if your <sys/time.h> declares `struct tm'. */
	/* #undef TM_IN_SYS_TIME */		/* #undef TM_IN_SYS_TIME */
	/* Define if use udis86 library */		/* Define if use udis86 library */
	#define USE_UDIS86 0		#define USE_UDIS86 0
	/* Type of 1st arg on ELM Callback */		/* Type of 1st arg on ELM Callback */
	/* #undef WIN32_ELMCB_PCSTR */		/* #undef WIN32_ELMCB_PCSTR */
			/* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most
			significant byte first (like Motorola and SPARC, unlike Intel). */
			#if defined AC_APPLE_UNIVERSAL_BUILD
			# if defined __BIG_ENDIAN__
			# define WORDS_BIGENDIAN 1
			# endif
			#else
			# ifndef WORDS_BIGENDIAN
			/* # undef WORDS_BIGENDIAN */
			# endif
			#endif
	/* Define to empty if `const' does not conform to ANSI C. */		/* Define to empty if `const' does not conform to ANSI C. */
	/* #undef const */		/* #undef const */
	/* Define to a type to use for `error_t' if it is not otherwise available. */		/* Define to a type to use for `error_t' if it is not otherwise available. */
	/* #undef error_t */		/* #undef error_t */
	/* Define to `int' if <sys/types.h> does not define. */		/* Define to `int' if <sys/types.h> does not define. */
	/* #undef pid_t */		/* #undef pid_t */
	/* Define to `unsigned int' if <sys/types.h> does not define. */		/* Define to `unsigned int' if <sys/types.h> does not define. */
End of changes. 36 change blocks.
	77 lines changed or deleted		50 lines changed or added

	ilist.h		ilist.h
	skipping to change at line 382		skipping to change at line 382
	}		}
	// reverse iterator creation methods.		// reverse iterator creation methods.
	reverse_iterator rbegin() { return reverse_iterator(end()); }		reverse_iterator rbegin() { return reverse_iterator(end()); }
	const_reverse_iterator rbegin() const{ return const_reverse_iterator(end( )); }		const_reverse_iterator rbegin() const{ return const_reverse_iterator(end( )); }
	reverse_iterator rend() { return reverse_iterator(begin()); }		reverse_iterator rend() { return reverse_iterator(begin()); }
	const_reverse_iterator rend() const { return const_reverse_iterator(begin ());}		const_reverse_iterator rend() const { return const_reverse_iterator(begin ());}
	// Miscellaneous inspection routines.		// Miscellaneous inspection routines.
	size_type max_size() const { return size_type(-1); }		size_type max_size() const { return size_type(-1); }
	bool empty() const { return Head == 0 || Head == getTail(); }		bool LLVM_ATTRIBUTE_UNUSED_RESULT empty() const {
			return Head == 0 || Head == getTail();
			}
	// Front and back accessor functions...		// Front and back accessor functions...
	reference front() {		reference front() {
	assert(!empty() && "Called front() on empty list!");		assert(!empty() && "Called front() on empty list!");
	return *Head;		return *Head;
	}		}
	const_reference front() const {		const_reference front() const {
	assert(!empty() && "Called front() on empty list!");		assert(!empty() && "Called front() on empty list!");
	return *Head;		return *Head;
	}		}
	skipping to change at line 534		skipping to change at line 536
	setTail(ThisSentinel);		setTail(ThisSentinel);
	}		}
	}		}
	public:		public:
	//===-------------------------------------------------------------------- --===		//===-------------------------------------------------------------------- --===
	// Functionality derived from other functions defined above...		// Functionality derived from other functions defined above...
	//		//
	size_type size() const {		size_type LLVM_ATTRIBUTE_UNUSED_RESULT size() const {
	if (Head == 0) return 0; // Don't require construction of sentinel if e mpty.		if (Head == 0) return 0; // Don't require construction of sentinel if e mpty.
	return std::distance(begin(), end());		return std::distance(begin(), end());
	}		}
	iterator erase(iterator first, iterator last) {		iterator erase(iterator first, iterator last) {
	while (first != last)		while (first != last)
	first = erase(first);		first = erase(first);
	return last;		return last;
	}		}
End of changes. 2 change blocks.
	2 lines changed or deleted		4 lines changed or added

	llvm-config.h		llvm-config.h
	skipping to change at line 21		skipping to change at line 21
	/* This file enumerates all of the llvm variables from configure so that		/* This file enumerates all of the llvm variables from configure so that
	they can be in exported headers and won't override package specific		they can be in exported headers and won't override package specific
	directives. This is a C file so we can include it in the llvm-c headers . */		directives. This is a C file so we can include it in the llvm-c headers . */
	/* To avoid multiple inclusions of these variables when we include the expo rted		/* To avoid multiple inclusions of these variables when we include the expo rted
	headers and config.h, conditionally include these. */		headers and config.h, conditionally include these. */
	/* TODO: This is a bit of a hack. */		/* TODO: This is a bit of a hack. */
	#ifndef CONFIG_H		#ifndef CONFIG_H
	/* Installation directory for binary executables */		/* Installation directory for binary executables */
	#define LLVM_BINDIR "/home/ut/testing/llvm/3.3/bin"		#define LLVM_BINDIR "/home/ut/testing/llvm/3.4/bin"
	/* Time at which LLVM was configured */		/* Time at which LLVM was configured */
	#define LLVM_CONFIGTIME "Tue Jun 18 03:16:37 MSK 2013"		#define LLVM_CONFIGTIME "Fri Jan 10 04:30:55 MSK 2014"
	/* Installation directory for data files */		/* Installation directory for data files */
	#define LLVM_DATADIR "/home/ut/testing/llvm/3.3/share/llvm"		#define LLVM_DATADIR "/home/ut/testing/llvm/3.4/share/llvm"
	/* Target triple LLVM will generate code for by default */		/* Target triple LLVM will generate code for by default */
	#define LLVM_DEFAULT_TARGET_TRIPLE "i686-pc-linux-gnu"		#define LLVM_DEFAULT_TARGET_TRIPLE "i686-pc-linux-gnu"
	/* Installation directory for documentation */		/* Installation directory for documentation */
	#define LLVM_DOCSDIR "/home/ut/testing/llvm/3.3/share/doc/llvm"		#define LLVM_DOCSDIR "/home/ut/testing/llvm/3.4/share/doc/llvm"
	/* Define if threads enabled */		/* Define if threads enabled */
	#define LLVM_ENABLE_THREADS 1		#define LLVM_ENABLE_THREADS 1
	/* Installation directory for config files */		/* Installation directory for config files */
	#define LLVM_ETCDIR "/home/ut/testing/llvm/3.3/etc/llvm"		#define LLVM_ETCDIR "/home/ut/testing/llvm/3.4/etc/llvm"
	/* Has gcc/MSVC atomic intrinsics */		/* Has gcc/MSVC atomic intrinsics */
	#define LLVM_HAS_ATOMICS 1		#define LLVM_HAS_ATOMICS 1
	/* Host triple LLVM will be executed on */		/* Host triple LLVM will be executed on */
	#define LLVM_HOST_TRIPLE "i686-pc-linux-gnu"		#define LLVM_HOST_TRIPLE "i686-pc-linux-gnu"
	/* Installation directory for include files */		/* Installation directory for include files */
	#define LLVM_INCLUDEDIR "/home/ut/testing/llvm/3.3/include"		#define LLVM_INCLUDEDIR "/home/ut/testing/llvm/3.4/include"
	/* Installation directory for .info files */		/* Installation directory for .info files */
	#define LLVM_INFODIR "/home/ut/testing/llvm/3.3/info"		#define LLVM_INFODIR "/home/ut/testing/llvm/3.4/info"
	/* Installation directory for libraries */
	#define LLVM_LIBDIR "/home/ut/testing/llvm/3.3/lib"
	/* Installation directory for man pages */		/* Installation directory for man pages */
	#define LLVM_MANDIR "/home/ut/testing/llvm/3.3/man"		#define LLVM_MANDIR "/home/ut/testing/llvm/3.4/man"
	/* LLVM architecture name for the native architecture, if available */		/* LLVM architecture name for the native architecture, if available */
	#define LLVM_NATIVE_ARCH X86		#define LLVM_NATIVE_ARCH X86
	/* LLVM name for the native AsmParser init function, if available */		/* LLVM name for the native AsmParser init function, if available */
	#define LLVM_NATIVE_ASMPARSER LLVMInitializeX86AsmParser		#define LLVM_NATIVE_ASMPARSER LLVMInitializeX86AsmParser
	/* LLVM name for the native AsmPrinter init function, if available */		/* LLVM name for the native AsmPrinter init function, if available */
	#define LLVM_NATIVE_ASMPRINTER LLVMInitializeX86AsmPrinter		#define LLVM_NATIVE_ASMPRINTER LLVMInitializeX86AsmPrinter
	skipping to change at line 114		skipping to change at line 111
	/* Define to path to neato program if found or 'echo neato' otherwise */		/* Define to path to neato program if found or 'echo neato' otherwise */
	#define LLVM_PATH_NEATO "/usr/bin/neato"		#define LLVM_PATH_NEATO "/usr/bin/neato"
	/* Define to path to twopi program if found or 'echo twopi' otherwise */		/* Define to path to twopi program if found or 'echo twopi' otherwise */
	#define LLVM_PATH_TWOPI "/usr/bin/twopi"		#define LLVM_PATH_TWOPI "/usr/bin/twopi"
	/* Define to path to xdot.py program if found or 'echo xdot.py' otherwise * /		/* Define to path to xdot.py program if found or 'echo xdot.py' otherwise * /
	/* #undef LLVM_PATH_XDOT_PY */		/* #undef LLVM_PATH_XDOT_PY */
	/* Installation prefix directory */		/* Installation prefix directory */
	#define LLVM_PREFIX "/home/ut/testing/llvm/3.3"		#define LLVM_PREFIX "/home/ut/testing/llvm/3.4"
	/* Define if we have the Intel JIT API runtime support library */		/* Define if we have the Intel JIT API runtime support library */
	#define LLVM_USE_INTEL_JITEVENTS 0		#define LLVM_USE_INTEL_JITEVENTS 0
	/* Define if we have the oprofile JIT-support library */		/* Define if we have the oprofile JIT-support library */
	#define LLVM_USE_OPROFILE 0		#define LLVM_USE_OPROFILE 0
	/* Major version of the LLVM API */		/* Major version of the LLVM API */
	#define LLVM_VERSION_MAJOR 3		#define LLVM_VERSION_MAJOR 3
	/* Minor version of the LLVM API */		/* Minor version of the LLVM API */
	#define LLVM_VERSION_MINOR 3		#define LLVM_VERSION_MINOR 4
	#endif		#endif
End of changes. 10 change blocks.
	13 lines changed or deleted		10 lines changed or added

	lto.h		lto.h
	skipping to change at line 19		skipping to change at line 19
	|* *|		|* *|
	|* This header provides public interface to an abstract link time optimizat ion*|		|* This header provides public interface to an abstract link time optimizat ion*|
	|* library. LLVM provides an implementation of this interface for use with *|		|* library. LLVM provides an implementation of this interface for use with *|
	|* llvm bitcode files. *|		|* llvm bitcode files. *|
	|* *|		|* *|
	\*===---------------------------------------------------------------------- ===*/		\*===---------------------------------------------------------------------- ===*/
	#ifndef LLVM_C_LTO_H		#ifndef LLVM_C_LTO_H
	#define LLVM_C_LTO_H		#define LLVM_C_LTO_H
	#include <stdbool.h>
	#include <stddef.h>		#include <stddef.h>
	#include <unistd.h>		#include <sys/types.h>
			#ifndef __cplusplus
			#if !defined(_MSC_VER)
			#include <stdbool.h>
			typedef bool lto_bool_t;
			#else
			/* MSVC in particular does not have anything like _Bool or bool in C, but w
			e can
			at least make sure the type is the same size. The implementation side w
			ill
			use C++ bool. */
			typedef unsigned char lto_bool_t;
			#endif
			#else
			typedef bool lto_bool_t;
			#endif
	/**		/**
	* @defgroup LLVMCLTO LTO		* @defgroup LLVMCLTO LTO
	* @ingroup LLVMC		* @ingroup LLVMC
	*		*
	* @{		* @{
	*/		*/
	#define LTO_API_VERSION 4		#define LTO_API_VERSION 5
	typedef enum {		typedef enum {
	LTO_SYMBOL_ALIGNMENT_MASK = 0x0000001F, /* log2 of alignme nt */		LTO_SYMBOL_ALIGNMENT_MASK = 0x0000001F, /* log2 of alignme nt */
	LTO_SYMBOL_PERMISSIONS_MASK = 0x000000E0,		LTO_SYMBOL_PERMISSIONS_MASK = 0x000000E0,
	LTO_SYMBOL_PERMISSIONS_CODE = 0x000000A0,		LTO_SYMBOL_PERMISSIONS_CODE = 0x000000A0,
	LTO_SYMBOL_PERMISSIONS_DATA = 0x000000C0,		LTO_SYMBOL_PERMISSIONS_DATA = 0x000000C0,
	LTO_SYMBOL_PERMISSIONS_RODATA = 0x00000080,		LTO_SYMBOL_PERMISSIONS_RODATA = 0x00000080,
	LTO_SYMBOL_DEFINITION_MASK = 0x00000700,		LTO_SYMBOL_DEFINITION_MASK = 0x00000700,
	LTO_SYMBOL_DEFINITION_REGULAR = 0x00000100,		LTO_SYMBOL_DEFINITION_REGULAR = 0x00000100,
	LTO_SYMBOL_DEFINITION_TENTATIVE = 0x00000200,		LTO_SYMBOL_DEFINITION_TENTATIVE = 0x00000200,
	skipping to change at line 88		skipping to change at line 101
	/**		/**
	* Returns the last error string or NULL if last operation was successful.		* Returns the last error string or NULL if last operation was successful.
	*/		*/
	extern const char*		extern const char*
	lto_get_error_message(void);		lto_get_error_message(void);
	/**		/**
	* Checks if a file is a loadable object file.		* Checks if a file is a loadable object file.
	*/		*/
	extern bool		extern lto_bool_t
	lto_module_is_object_file(const char* path);		lto_module_is_object_file(const char* path);
	/**		/**
	* Checks if a file is a loadable object compiled for requested target.		* Checks if a file is a loadable object compiled for requested target.
	*/		*/
	extern bool		extern lto_bool_t
	lto_module_is_object_file_for_target(const char* path,		lto_module_is_object_file_for_target(const char* path,
	const char* target_triple_prefix);		const char* target_triple_prefix);
	/**		/**
	* Checks if a buffer is a loadable object file.		* Checks if a buffer is a loadable object file.
	*/		*/
	extern bool		extern lto_bool_t
	lto_module_is_object_file_in_memory(const void* mem, size_t length);		lto_module_is_object_file_in_memory(const void* mem, size_t length);
	/**		/**
	* Checks if a buffer is a loadable object compiled for requested target.		* Checks if a buffer is a loadable object compiled for requested target.
	*/		*/
	extern bool		extern lto_bool_t
	lto_module_is_object_file_in_memory_for_target(const void* mem, size_t leng th,		lto_module_is_object_file_in_memory_for_target(const void* mem, size_t leng th,
	const char* target_triple_pre fix);		const char* target_triple_pre fix);
	/**		/**
	* Loads an object file from disk.		* Loads an object file from disk.
	* Returns NULL on error (check lto_get_error_message() for details).		* Returns NULL on error (check lto_get_error_message() for details).
	*/		*/
	extern lto_module_t		extern lto_module_t
	lto_module_create(const char* path);		lto_module_create(const char* path);
	skipping to change at line 195		skipping to change at line 208
	* Frees all code generator and all memory it internally allocated.		* Frees all code generator and all memory it internally allocated.
	* Upon return the lto_code_gen_t is no longer valid.		* Upon return the lto_code_gen_t is no longer valid.
	*/		*/
	extern void		extern void
	lto_codegen_dispose(lto_code_gen_t);		lto_codegen_dispose(lto_code_gen_t);
	/**		/**
	* Add an object module to the set of modules for which code will be genera ted.		* Add an object module to the set of modules for which code will be genera ted.
	* Returns true on error (check lto_get_error_message() for details).		* Returns true on error (check lto_get_error_message() for details).
	*/		*/
	extern bool		extern lto_bool_t
	lto_codegen_add_module(lto_code_gen_t cg, lto_module_t mod);		lto_codegen_add_module(lto_code_gen_t cg, lto_module_t mod);
	/**		/**
	* Sets if debug info should be generated.		* Sets if debug info should be generated.
	* Returns true on error (check lto_get_error_message() for details).		* Returns true on error (check lto_get_error_message() for details).
	*/		*/
	extern bool		extern lto_bool_t
	lto_codegen_set_debug_model(lto_code_gen_t cg, lto_debug_model);		lto_codegen_set_debug_model(lto_code_gen_t cg, lto_debug_model);
	/**		/**
	* Sets which PIC code model to generated.		* Sets which PIC code model to generated.
	* Returns true on error (check lto_get_error_message() for details).		* Returns true on error (check lto_get_error_message() for details).
	*/		*/
	extern bool		extern lto_bool_t
	lto_codegen_set_pic_model(lto_code_gen_t cg, lto_codegen_model);		lto_codegen_set_pic_model(lto_code_gen_t cg, lto_codegen_model);
	/**		/**
	* Sets the cpu to generate code for.		* Sets the cpu to generate code for.
	*/		*/
	extern void		extern void
	lto_codegen_set_cpu(lto_code_gen_t cg, const char *cpu);		lto_codegen_set_cpu(lto_code_gen_t cg, const char *cpu);
	/**		/**
	* Sets the location of the assembler tool to run. If not set, libLTO		* Sets the location of the assembler tool to run. If not set, libLTO
	skipping to change at line 233		skipping to change at line 246
	lto_codegen_set_assembler_path(lto_code_gen_t cg, const char* path);		lto_codegen_set_assembler_path(lto_code_gen_t cg, const char* path);
	/**		/**
	* Sets extra arguments that libLTO should pass to the assembler.		* Sets extra arguments that libLTO should pass to the assembler.
	*/		*/
	extern void		extern void
	lto_codegen_set_assembler_args(lto_code_gen_t cg, const char **args,		lto_codegen_set_assembler_args(lto_code_gen_t cg, const char **args,
	int nargs);		int nargs);
	/**		/**
	* Adds to a list of all global symbols that must exist in the final		* Tells LTO optimization passes that this symbol must be preserved
	* generated code. If a function is not listed, it might be		* because it is referenced by native code or a command line option.
	* inlined into every usage and optimized away.
	*/		*/
	extern void		extern void
	lto_codegen_add_must_preserve_symbol(lto_code_gen_t cg, const char* symbol) ;		lto_codegen_add_must_preserve_symbol(lto_code_gen_t cg, const char* symbol) ;
	/**		/**
	* Writes a new object file at the specified path that contains the		* Writes a new object file at the specified path that contains the
	* merged contents of all modules added so far.		* merged contents of all modules added so far.
	* Returns true on error (check lto_get_error_message() for details).		* Returns true on error (check lto_get_error_message() for details).
	*/		*/
	extern bool		extern lto_bool_t
	lto_codegen_write_merged_modules(lto_code_gen_t cg, const char* path);		lto_codegen_write_merged_modules(lto_code_gen_t cg, const char* path);
	/**		/**
	* Generates code for all added modules into one native object file.		* Generates code for all added modules into one native object file.
	* On success returns a pointer to a generated mach-o/ELF buffer and		* On success returns a pointer to a generated mach-o/ELF buffer and
	* length set to the buffer size. The buffer is owned by the		* length set to the buffer size. The buffer is owned by the
	* lto_code_gen_t and will be freed when lto_codegen_dispose()		* lto_code_gen_t and will be freed when lto_codegen_dispose()
	* is called, or lto_codegen_compile() is called again.		* is called, or lto_codegen_compile() is called again.
	* On failure, returns NULL (check lto_get_error_message() for details).		* On failure, returns NULL (check lto_get_error_message() for details).
	*/		*/
	extern const void*		extern const void*
	lto_codegen_compile(lto_code_gen_t cg, size_t* length);		lto_codegen_compile(lto_code_gen_t cg, size_t* length);
	/**		/**
	* Generates code for all added modules into one native object file.		* Generates code for all added modules into one native object file.
	* The name of the file is written to name. Returns true on error.		* The name of the file is written to name. Returns true on error.
	*/		*/
	extern bool		extern lto_bool_t
	lto_codegen_compile_to_file(lto_code_gen_t cg, const char** name);		lto_codegen_compile_to_file(lto_code_gen_t cg, const char** name);
	/**		/**
	* Sets options to help debug codegen bugs.		* Sets options to help debug codegen bugs.
	*/		*/
	extern void		extern void
	lto_codegen_debug_options(lto_code_gen_t cg, const char *);		lto_codegen_debug_options(lto_code_gen_t cg, const char *);
	/**		/**
	* Initializes LLVM disassemblers.		* Initializes LLVM disassemblers.
End of changes. 13 change blocks.
	15 lines changed or deleted		29 lines changed or added

	raw_ostream.h		raw_ostream.h
	skipping to change at line 20		skipping to change at line 20
	// This file defines the raw_ostream class.		// This file defines the raw_ostream class.
	//		//
	//===---------------------------------------------------------------------- ===//		//===---------------------------------------------------------------------- ===//
	#ifndef LLVM_SUPPORT_RAW_OSTREAM_H		#ifndef LLVM_SUPPORT_RAW_OSTREAM_H
	#define LLVM_SUPPORT_RAW_OSTREAM_H		#define LLVM_SUPPORT_RAW_OSTREAM_H
	#include "llvm/ADT/StringRef.h"		#include "llvm/ADT/StringRef.h"
	#include "llvm/Support/Compiler.h"		#include "llvm/Support/Compiler.h"
	#include "llvm/Support/DataTypes.h"		#include "llvm/Support/DataTypes.h"
			#include "llvm/Support/FileSystem.h"
	namespace llvm {		namespace llvm {
	class format_object_base;		class format_object_base;
	template <typename T>		template <typename T>
	class SmallVectorImpl;		class SmallVectorImpl;
	/// raw_ostream - This class implements an extremely fast bulk output strea m		/// raw_ostream - This class implements an extremely fast bulk output strea m
	/// that can *only* output to a stream. It does not support seeking, reope ning,		/// that can *only* output to a stream. It does not support seeking, reope ning,
	/// rewinding, line buffered disciplines etc. It is a simple buffer that ou tputs		/// rewinding, line buffered disciplines etc. It is a simple buffer that ou tputs
	/// a chunk at a time.		/// a chunk at a time.
	skipping to change at line 337		skipping to change at line 338
	virtual uint64_t current_pos() const LLVM_OVERRIDE { return pos; }		virtual uint64_t current_pos() const LLVM_OVERRIDE { return pos; }
	/// preferred_buffer_size - Determine an efficient buffer size.		/// preferred_buffer_size - Determine an efficient buffer size.
	virtual size_t preferred_buffer_size() const LLVM_OVERRIDE;		virtual size_t preferred_buffer_size() const LLVM_OVERRIDE;
	/// error_detected - Set the flag indicating that an output error has		/// error_detected - Set the flag indicating that an output error has
	/// been encountered.		/// been encountered.
	void error_detected() { Error = true; }		void error_detected() { Error = true; }
	public:		public:
	enum {
	/// F_Excl - When opening a file, this flag makes raw_fd_ostream
	/// report an error if the file already exists.
	F_Excl = 1,
	/// F_Append - When opening a file, if it already exists append to the
	/// existing file instead of returning an error. This may not be speci
	fied
	/// with F_Excl.
	F_Append = 2,
	/// F_Binary - The file should be opened in binary mode on platforms th
	at
	/// make this distinction.
	F_Binary = 4
	};
	/// raw_fd_ostream - Open the specified file for writing. If an error occ urs,		/// raw_fd_ostream - Open the specified file for writing. If an error occ urs,
	/// information about the error is put into ErrorInfo, and the stream sho uld		/// information about the error is put into ErrorInfo, and the stream sho uld
	/// be immediately destroyed; the string will be empty if no error occurr ed.		/// be immediately destroyed; the string will be empty if no error occurr ed.
	/// This allows optional flags to control how the file will be opened.		/// This allows optional flags to control how the file will be opened.
	///		///
	/// As a special case, if Filename is "-", then the stream will use		/// As a special case, if Filename is "-", then the stream will use
	/// STDOUT_FILENO instead of opening a file. Note that it will still cons ider		/// STDOUT_FILENO instead of opening a file. Note that it will still cons ider
	/// itself to own the file descriptor. In particular, it will close the		/// itself to own the file descriptor. In particular, it will close the
	/// file descriptor when it is done (this is necessary to detect		/// file descriptor when it is done (this is necessary to detect
	/// output errors).		/// output errors).
	raw_fd_ostream(const char *Filename, std::string &ErrorInfo,		raw_fd_ostream(const char *Filename, std::string &ErrorInfo,
	unsigned Flags = 0);		sys::fs::OpenFlags Flags = sys::fs::F_None);
	/// raw_fd_ostream ctor - FD is the file descriptor that this writes to. If		/// raw_fd_ostream ctor - FD is the file descriptor that this writes to. If
	/// ShouldClose is true, this closes the file when the stream is destroye d.		/// ShouldClose is true, this closes the file when the stream is destroye d.
	raw_fd_ostream(int fd, bool shouldClose, bool unbuffered=false);		raw_fd_ostream(int fd, bool shouldClose, bool unbuffered=false);
	~raw_fd_ostream();		~raw_fd_ostream();
	/// close - Manually flush the stream and close the file.		/// close - Manually flush the stream and close the file.
	/// Note that this does not call fsync.		/// Note that this does not call fsync.
	void close();		void close();
End of changes. 3 change blocks.
	19 lines changed or deleted		2 lines changed or added

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