config.h   config.h 
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#define PCI_HAVE_PM_LINUX_SYSFS #define PCI_HAVE_PM_LINUX_SYSFS
#define PCI_HAVE_PM_LINUX_PROC #define PCI_HAVE_PM_LINUX_PROC
#define PCI_HAVE_LINUX_BYTEORDER_H #define PCI_HAVE_LINUX_BYTEORDER_H
#define PCI_PATH_PROC_BUS_PCI "/proc/bus/pci" #define PCI_PATH_PROC_BUS_PCI "/proc/bus/pci"
#define PCI_PATH_SYS_BUS_PCI "/sys/bus/pci" #define PCI_PATH_SYS_BUS_PCI "/sys/bus/pci"
#define PCI_HAVE_PM_INTEL_CONF #define PCI_HAVE_PM_INTEL_CONF
#define PCI_HAVE_64BIT_ADDRESS #define PCI_HAVE_64BIT_ADDRESS
#define PCI_HAVE_PM_DUMP #define PCI_HAVE_PM_DUMP
#define PCI_COMPRESSED_IDS #define PCI_COMPRESSED_IDS
#define PCI_IDS "pci.ids.gz" #define PCI_IDS "pci.ids.gz"
#define PCI_PATH_IDS_DIR "/home/andrey/upstream-tracker/testing/pciutils/2. #define PCI_PATH_IDS_DIR "/home/andrey/upstream-tracker/testing/pciutils/2.
2.6/share" 2.7/share"
#define PCILIB_VERSION "2.2.6" #define PCILIB_VERSION "2.2.7"
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 header.h   header.h 
/* /*
* The PCI Library -- PCI Header Structure (based on <linux/pci.h>) * The PCI Library -- PCI Header Structure (based on <linux/pci.h>)
* *
* Copyright (c) 1997--2005 Martin Mares <mj@ucw.cz> * Copyright (c) 1997--2007 Martin Mares <mj@ucw.cz>
* *
* Can be freely distributed and used under the terms of the GNU GPL. * Can be freely distributed and used under the terms of the GNU GPL.
*/ */
/* /*
* Under PCI, each device has 256 bytes of configuration address space, * Under PCI, each device has 256 bytes of configuration address space,
* of which the first 64 bytes are standardized as follows: * of which the first 64 bytes are standardized as follows:
*/ */
#define PCI_VENDOR_ID 0x00 /* 16 bits */ #define PCI_VENDOR_ID 0x00 /* 16 bits */
#define PCI_DEVICE_ID 0x02 /* 16 bits */ #define PCI_DEVICE_ID 0x02 /* 16 bits */
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#define PCI_COMMAND_IO 0x1 /* Enable response in I/O sp ace */ #define PCI_COMMAND_IO 0x1 /* Enable response in I/O sp ace */
#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space * / #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space * /
#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */ #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */ #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and inva lidate */ #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and inva lidate */
#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */ #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */ #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */ #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
#define PCI_COMMAND_SERR 0x100 /* Enable SERR */ #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
#define PCI_COMMAND_DISABLE_INTx 0x400 /* PCIE: Disable INTx interr upts */
#define PCI_STATUS 0x06 /* 16 bits */ #define PCI_STATUS 0x06 /* 16 bits */
#define PCI_STATUS_INTx 0x08 /* PCIE: INTx interrupt pending */
#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
#define PCI_STATUS_UDF 0x40 /* Support User Definable Fe atures [obsolete] */ #define PCI_STATUS_UDF 0x40 /* Support User Definable Fe atures [obsolete] */
#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
#define PCI_STATUS_PARITY 0x100 /* Detected parity error */ #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */ #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
#define PCI_STATUS_DEVSEL_FAST 0x000 #define PCI_STATUS_DEVSEL_FAST 0x000
#define PCI_STATUS_DEVSEL_MEDIUM 0x200 #define PCI_STATUS_DEVSEL_MEDIUM 0x200
#define PCI_STATUS_DEVSEL_SLOW 0x400 #define PCI_STATUS_DEVSEL_SLOW 0x400
#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */ #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
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#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */ #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
/* 0x3c-0x3d are same as for htype 0 */ /* 0x3c-0x3d are same as for htype 0 */
#define PCI_BRIDGE_CONTROL 0x3e #define PCI_BRIDGE_CONTROL 0x3e
#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on second ary interface */ #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on second ary interface */
#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on seconda ry interface */ #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on seconda ry interface */
#define PCI_BRIDGE_CTL_PRI_DISCARD_TIMER 0x100 /* PCI-X? */
#define PCI_BRIDGE_CTL_SEC_DISCARD_TIMER 0x200 /* PCI-X? */
#define PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS 0x400 /* PCI-X? */
#define PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN 0x800 /* PCI-X? */
/* Header type 2 (CardBus bridges) */ /* Header type 2 (CardBus bridges) */
/* 0x14-0x15 reserved */ /* 0x14-0x15 reserved */
#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */ #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */ #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */ #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */ #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */ #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
#define PCI_CB_MEMORY_BASE_0 0x1c #define PCI_CB_MEMORY_BASE_0 0x1c
#define PCI_CB_MEMORY_LIMIT_0 0x20 #define PCI_CB_MEMORY_LIMIT_0 0x20
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#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */ #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits ) */ #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits ) */
#define PCI_CAP_SIZEOF 4 #define PCI_CAP_SIZEOF 4
/* Capabilities residing in the PCI Express extended configuration space */ /* Capabilities residing in the PCI Express extended configuration space */
#define PCI_EXT_CAP_ID_AER 0x01 /* Advanced Error Reporting */ #define PCI_EXT_CAP_ID_AER 0x01 /* Advanced Error Reporting */
#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */ #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */
#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
#define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */ #define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */
#define PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */
#define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declar
ation */
#define PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
#define PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */
#define PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */
#define PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */
/* Power Management Registers */ /* Power Management Registers */
#define PCI_PM_CAP_VER_MASK 0x0007 /* Version (2=PM1.1) */ #define PCI_PM_CAP_VER_MASK 0x0007 /* Version (2=PM1.1) */
#define PCI_PM_CAP_PME_CLOCK 0x0008 /* Clock required for PME generation */ #define PCI_PM_CAP_PME_CLOCK 0x0008 /* Clock required for PME generation */
#define PCI_PM_CAP_DSI 0x0020 /* Device specific initializ ation required */ #define PCI_PM_CAP_DSI 0x0020 /* Device specific initializ ation required */
#define PCI_PM_CAP_AUX_C_MASK 0x01c0 /* Maximum aux current required in D 3cold */ #define PCI_PM_CAP_AUX_C_MASK 0x01c0 /* Maximum aux current required in D 3cold */
#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
#define PCI_PM_CAP_PME_D0 0x0800 /* PME can be asserted from D0 */ #define PCI_PM_CAP_PME_D0 0x0800 /* PME can be asserted from D0 */
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#define PCI_EXP_FLAGS 0x2 /* Capabilities register */ #define PCI_EXP_FLAGS 0x2 /* Capabilities register */
#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ #define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ #define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ #define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */ #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */ #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */
#define PCI_EXP_TYPE_ROOT_INT_EP 0x9 /* Root Complex Integrated Endpoint
*/
#define PCI_EXP_TYPE_ROOT_EC 0xa /* Root Complex Event Collector */
#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ #define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ #define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
#define PCI_EXP_DEVCAP 0x4 /* Device capabilities */ #define PCI_EXP_DEVCAP 0x4 /* Device capabilities */
#define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */ #define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
#define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */ #define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
#define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */ #define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
#define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */ #define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
#define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */ #define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */ #define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Prese nt */ #define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Prese nt */
#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present * / #define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present * /
#define PCI_EXP_DEVCAP_RBE 0x8000 /* Role-Based Error Reporting */
#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */ #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */ #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
#define PCI_EXP_DEVCAP_FLRESET 0x10000000 /* Function-Level Reset * /
#define PCI_EXP_DEVCTL 0x8 /* Device Control */ #define PCI_EXP_DEVCTL 0x8 /* Device Control */
#define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. * / #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. * /
#define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */ #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
#define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */ #define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
#define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */ #define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
#define PCI_EXP_DEVCTL_RELAXED 0x0010 /* Enable Relaxed Ordering * / #define PCI_EXP_DEVCTL_RELAXED 0x0010 /* Enable Relaxed Ordering * /
#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */ #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */ #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
#define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */ #define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */ #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
#define PCI_EXP_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */ #define PCI_EXP_DEVCTL_NOSNOOP 0x0800 /* Enable No Snoop */
#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */ #define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
#define PCI_EXP_DEVCTL_BCRE 0x8000 /* Bridge Configuration Retry Enable
*/
#define PCI_EXP_DEVCTL_FLRESET 0x8000 /* Function-Level Reset [bit
shared with BCRE] */
#define PCI_EXP_DEVSTA 0xa /* Device Status */ #define PCI_EXP_DEVSTA 0xa /* Device Status */
#define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */ #define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
#define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */ #define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
#define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */ #define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
#define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */ #define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
#define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */ #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
#define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */ #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
#define PCI_EXP_LNKCAP 0xc /* Link Capabilities */ #define PCI_EXP_LNKCAP 0xc /* Link Capabilities */
#define PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */ #define PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */
#define PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */ #define PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */
#define PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */ #define PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */
#define PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */ #define PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */
#define PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */ #define PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */
#define PCI_EXP_LNKCAP_CLOCKPM 0x40000 /* Clock Power Management */
#define PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting *
/
#define PCI_EXP_LNKCAP_DLLA 0x100000 /* Data Link Layer Active Reporting
*/
#define PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capa
bility */
#define PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */ #define PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */
#define PCI_EXP_LNKCTL 0x10 /* Link Control */ #define PCI_EXP_LNKCTL 0x10 /* Link Control */
#define PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */ #define PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */
#define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */ #define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
#define PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */ #define PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */
#define PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */ #define PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */
#define PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */ #define PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */
#define PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */ #define PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */
#define PCI_EXP_LNKCTL_CLOCKPM 0x0100 /* Clock Power Management */
#define PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width
Disable */
#define PCI_EXP_LNKCTL_BWMIE 0x0400 /* Bandwidth Mgmt Interrupt Enable *
/
#define PCI_EXP_LNKCTL_AUTBWIE 0x0800 /* Autonomous Bandwidth Mgmt
Interrupt Enable */
#define PCI_EXP_LNKSTA 0x12 /* Link Status */ #define PCI_EXP_LNKSTA 0x12 /* Link Status */
#define PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */ #define PCI_EXP_LNKSTA_SPEED 0x000f /* Negotiated Link Speed */
#define PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */ #define PCI_EXP_LNKSTA_WIDTH 0x03f0 /* Negotiated Link Width */
#define PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error */ #define PCI_EXP_LNKSTA_TR_ERR 0x0400 /* Training Error (obsolete) */
#define PCI_EXP_LNKSTA_TRAIN 0x0800 /* Link Training */ #define PCI_EXP_LNKSTA_TRAIN 0x0800 /* Link Training */
#define PCI_EXP_LNKSTA_SL_CLK 0x1000 /* Slot Clock Configuration */ #define PCI_EXP_LNKSTA_SL_CLK 0x1000 /* Slot Clock Configuration */
#define PCI_EXP_LNKSTA_DL_ACT 0x2000 /* Data Link Layer in DL_Active Stat
e */
#define PCI_EXP_LNKSTA_BWMGMT 0x4000 /* Bandwidth Mgmt Status */
#define PCI_EXP_LNKSTA_AUTBW 0x8000 /* Autonomous Bandwidth Mgmt Status
*/
#define PCI_EXP_SLTCAP 0x14 /* Slot Capabilities */ #define PCI_EXP_SLTCAP 0x14 /* Slot Capabilities */
#define PCI_EXP_SLTCAP_ATNB 0x0001 /* Attention Button Present */ #define PCI_EXP_SLTCAP_ATNB 0x0001 /* Attention Button Present */
#define PCI_EXP_SLTCAP_PWRC 0x0002 /* Power Controller Present */ #define PCI_EXP_SLTCAP_PWRC 0x0002 /* Power Controller Present */
#define PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */ #define PCI_EXP_SLTCAP_MRL 0x0004 /* MRL Sensor Present */
#define PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */ #define PCI_EXP_SLTCAP_ATNI 0x0008 /* Attention Indicator Present */
#define PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */ #define PCI_EXP_SLTCAP_PWRI 0x0010 /* Power Indicator Present */
#define PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */ #define PCI_EXP_SLTCAP_HPS 0x0020 /* Hot-Plug Surprise */
#define PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */ #define PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */
#define PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */ #define PCI_EXP_SLTCAP_PWR_VAL 0x00007f80 /* Slot Power Limit Value */
#define PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */ #define PCI_EXP_SLTCAP_PWR_SCL 0x00018000 /* Slot Power Limit Scale */
#define PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock P
resent */
#define PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support
*/
#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
#define PCI_EXP_SLTCTL 0x18 /* Slot Control */ #define PCI_EXP_SLTCTL 0x18 /* Slot Control */
#define PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable * / #define PCI_EXP_SLTCTL_ATNB 0x0001 /* Attention Button Pressed Enable * /
#define PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */ #define PCI_EXP_SLTCTL_PWRF 0x0002 /* Power Fault Detected Enable */
#define PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */ #define PCI_EXP_SLTCTL_MRLS 0x0004 /* MRL Sensor Changed Enable */
#define PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */ #define PCI_EXP_SLTCTL_PRSD 0x0008 /* Presence Detect Changed Enable */
#define PCI_EXP_SLTCTL_CMDC 0x0010 /* Command Completed Interrupt Enabl e */ #define PCI_EXP_SLTCTL_CMDC 0x0010 /* Command Completed Interrupt Enabl e */
#define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */ #define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
#define PCI_EXP_SLTCTL_ATNI 0x00C0 /* Attention Indicator Control */ #define PCI_EXP_SLTCTL_ATNI 0x00c0 /* Attention Indicator Control */
#define PCI_EXP_SLTCTL_PWRI 0x0300 /* Power Indicator Control */ #define PCI_EXP_SLTCTL_PWRI 0x0300 /* Power Indicator Control */
#define PCI_EXP_SLTCTL_PWRC 0x0400 /* Power Controller Control */ #define PCI_EXP_SLTCTL_PWRC 0x0400 /* Power Controller Control */
#define PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Con
trol */
#define PCI_EXP_SLTCTL_LLCHG 0x1000 /* Data Link Layer State Changed Ena
ble */
#define PCI_EXP_SLTSTA 0x1a /* Slot Status */ #define PCI_EXP_SLTSTA 0x1a /* Slot Status */
#define PCI_EXP_SLTSTA_ATNB 0x0001 /* Attention Button Pressed */
#define PCI_EXP_SLTSTA_PWRF 0x0002 /* Power Fault Detected */
#define PCI_EXP_SLTSTA_MRLS 0x0004 /* MRL Sensor Changed */
#define PCI_EXP_SLTSTA_PRSD 0x0008 /* Presence Detect Changed */
#define PCI_EXP_SLTSTA_CMDC 0x0010 /* Command Completed */
#define PCI_EXP_SLTSTA_MRL_ST 0x0020 /* MRL Sensor State */
#define PCI_EXP_SLTSTA_PRES 0x0040 /* Presence Detect State */
#define PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Sta
tus */
#define PCI_EXP_SLTSTA_LLCHG 0x0100 /* Data Link Layer State Changed */
#define PCI_EXP_RTCTL 0x1c /* Root Control */ #define PCI_EXP_RTCTL 0x1c /* Root Control */
#define PCI_EXP_RTCTL_SECEE 0x1 /* System Error on Correctable Error #define PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error
*/ */
#define PCI_EXP_RTCTL_SENFEE 0x1 /* System Error on Non-Fatal Error * #define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error *
/ /
#define PCI_EXP_RTCTL_SEFEE 0x1 /* System Error on Fatal Error */ #define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */
#define PCI_EXP_RTCTL_PMEIE 0x1 /* PME Interrupt Enable */ #define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
#define PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Statu
s Visible to SW */
#define PCI_EXP_RTCAP 0x1e /* Root Capabilities */
#define PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Statu
s Visible to SW */
#define PCI_EXP_RTSTA 0x20 /* Root Status */ #define PCI_EXP_RTSTA 0x20 /* Root Status */
#define PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
#define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
#define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
/* MSI-X */ /* MSI-X */
#define PCI_MSIX_ENABLE 0x8000 #define PCI_MSIX_ENABLE 0x8000
#define PCI_MSIX_MASK 0x4000 #define PCI_MSIX_MASK 0x4000
#define PCI_MSIX_TABSIZE 0x03ff #define PCI_MSIX_TABSIZE 0x03ff
#define PCI_MSIX_TABLE 4 #define PCI_MSIX_TABLE 4
#define PCI_MSIX_PBA 8 #define PCI_MSIX_PBA 8
#define PCI_MSIX_BIR 0x7 #define PCI_MSIX_BIR 0x7
/* Subsystem vendor/device ID for PCI bridges */ /* Subsystem vendor/device ID for PCI bridges */
 End of changes. 19 change blocks. 
9 lines changed or deleted 77 lines changed or added


 types.h   types.h 
skipping to change at line 14 skipping to change at line 14
* Copyright (c) 1997--2007 Martin Mares <mj@ucw.cz> * Copyright (c) 1997--2007 Martin Mares <mj@ucw.cz>
* *
* Can be freely distributed and used under the terms of the GNU GPL. * Can be freely distributed and used under the terms of the GNU GPL.
*/ */
#include <sys/types.h> #include <sys/types.h>
#ifndef PCI_HAVE_Uxx_TYPES #ifndef PCI_HAVE_Uxx_TYPES
#ifdef PCI_OS_WINDOWS #ifdef PCI_OS_WINDOWS
typedef unsigned __int8 u8; #include <windef.h>
typedef unsigned __int16 u16; typedef BYTE u8;
typedef unsigned __int32 u32; typedef WORD u16;
typedef DWORD u32;
#elif defined(PCI_HAVE_STDINT_H) #elif defined(PCI_HAVE_STDINT_H)
#include <stdint.h> #include <stdint.h>
typedef uint8_t u8; typedef uint8_t u8;
typedef uint16_t u16; typedef uint16_t u16;
typedef uint32_t u32; typedef uint32_t u32;
#else #else
typedef u_int8_t u8; typedef u_int8_t u8;
typedef u_int16_t u16; typedef u_int16_t u16;
typedef u_int32_t u32; typedef u_int32_t u32;
#endif #endif
 End of changes. 1 change blocks. 
3 lines changed or deleted 4 lines changed or added

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