pciutils: headers diff between 3.0.0 and 3.0.1 versions

	config.h	config.h
	#define PCI_ARCH_I386	#define PCI_ARCH_I386
	#define PCI_OS_LINUX	#define PCI_OS_LINUX
	#define PCI_HAVE_PM_LINUX_SYSFS	#define PCI_HAVE_PM_LINUX_SYSFS
	#define PCI_HAVE_PM_LINUX_PROC	#define PCI_HAVE_PM_LINUX_PROC
	#define PCI_HAVE_LINUX_BYTEORDER_H	#define PCI_HAVE_LINUX_BYTEORDER_H
	#define PCI_PATH_PROC_BUS_PCI "/proc/bus/pci"	#define PCI_PATH_PROC_BUS_PCI "/proc/bus/pci"
	#define PCI_PATH_SYS_BUS_PCI "/sys/bus/pci"	#define PCI_PATH_SYS_BUS_PCI "/sys/bus/pci"
	#define PCI_HAVE_PM_INTEL_CONF	#define PCI_HAVE_PM_INTEL_CONF
	#define PCI_HAVE_64BIT_ADDRESS	#define PCI_HAVE_64BIT_ADDRESS

	#define PCI_USE_DNS
	#define PCI_HAVE_PM_DUMP	#define PCI_HAVE_PM_DUMP
	#define PCI_COMPRESSED_IDS	#define PCI_COMPRESSED_IDS
	#define PCI_IDS "pci.ids.gz"	#define PCI_IDS "pci.ids.gz"

	#define PCI_PATH_IDS_DIR "/home/andrey/upstream-tracker/testing/pciutils/3. 0.0/share"	#define PCI_PATH_IDS_DIR "/home/andrey/upstream-tracker/testing/pciutils/3. 0.1/share"
	#define PCI_USE_DNS	#define PCI_USE_DNS
	#define PCI_ID_DOMAIN "pci.id.ucw.cz"	#define PCI_ID_DOMAIN "pci.id.ucw.cz"

	#define PCILIB_VERSION "3.0.0"	#define PCI_SHARED_LIB
		#define PCILIB_VERSION "3.0.1"

End of changes. 3 change blocks.
	2 lines changed or deleted	1 lines changed or added

	header.h	header.h

	skipping to change at line 222	skipping to change at line 222
	#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */	#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */
	#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */	#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
	#define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */	#define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */
	#define PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */	#define PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */
	#define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declar ation */	#define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declar ation */
	#define PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */	#define PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
	#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */	#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
	#define PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */	#define PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */
	#define PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */	#define PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */
	#define PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */	#define PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */

		#define PCI_EXT_CAP_ID_ARI 0x0e /* Alternative Routing-ID Interpreta
		tion */
		#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */

	/* Power Management Registers */	/* Power Management Registers */

	#define PCI_PM_CAP_VER_MASK 0x0007 /* Version (2=PM1.1) */	#define PCI_PM_CAP_VER_MASK 0x0007 /* Version (2=PM1.1) */
	#define PCI_PM_CAP_PME_CLOCK 0x0008 /* Clock required for PME generation */	#define PCI_PM_CAP_PME_CLOCK 0x0008 /* Clock required for PME generation */
	#define PCI_PM_CAP_DSI 0x0020 /* Device specific initializ ation required */	#define PCI_PM_CAP_DSI 0x0020 /* Device specific initializ ation required */
	#define PCI_PM_CAP_AUX_C_MASK 0x01c0 /* Maximum aux current required in D 3cold */	#define PCI_PM_CAP_AUX_C_MASK 0x01c0 /* Maximum aux current required in D 3cold */
	#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */	#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
	#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */	#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
	#define PCI_PM_CAP_PME_D0 0x0800 /* PME can be asserted from D0 */	#define PCI_PM_CAP_PME_D0 0x0800 /* PME can be asserted from D0 */

	skipping to change at line 828	skipping to change at line 830
	#define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error * /	#define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error * /
	#define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */	#define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */
	#define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */	#define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
	#define PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Statu s Visible to SW */	#define PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Statu s Visible to SW */
	#define PCI_EXP_RTCAP 0x1e /* Root Capabilities */	#define PCI_EXP_RTCAP 0x1e /* Root Capabilities */
	#define PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Statu s Visible to SW */	#define PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Statu s Visible to SW */
	#define PCI_EXP_RTSTA 0x20 /* Root Status */	#define PCI_EXP_RTSTA 0x20 /* Root Status */
	#define PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */	#define PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
	#define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */	#define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
	#define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */	#define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */

		#define PCI_EXP_DEVCAP2 0x24 /* Device capabiliti
		es 2 */
		#define PCI_EXP_DEVCTL2 0x28 /* Device Control */
		#define PCI_EXP_DEV2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ra
		nges Supported */
		#define PCI_EXP_DEV2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Va
		lue */
		#define PCI_EXP_DEV2_TIMEOUT_DIS 0x0010 /* Completion Timeout Disabl
		e Supported */
		#define PCI_EXP_DEV2_ARI 0x0020 /* ARI Forwarding */
		#define PCI_EXP_DEVSTA2 0x2a /* Device Status */
		#define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities
		*/
		#define PCI_EXP_LNKCTL2 0x30 /* Link Control */
		#define PCI_EXP_LNKCTL2_SPEED(x) ((x) & 0xf) /* Target Link Speed */
		#define PCI_EXP_LNKCTL2_CMPLNC 0x0010 /* Enter Compliance
		*/
		#define PCI_EXP_LNKCTL2_SPEED_DIS 0x0020 /* Hardware Autonomous Speed
		Disable */
		#define PCI_EXP_LNKCTL2_DEEMPHASIS(x) (((x) >> 6) & 1) /* Selectable De-em
		phasis */
		#define PCI_EXP_LNKCTL2_MARGIN(x) (((x) >> 7) & 7) /* Transmit Margin
		*/
		#define PCI_EXP_LNKCTL2_MOD_CMPLNC 0x0400 /* Enter Modified Compliance
		*/
		#define PCI_EXP_LNKCTL2_CMPLNC_SOS 0x0800 /* Compliance SOS */
		#define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 1) /* Compliance
		De-emphasis */
		#define PCI_EXP_LNKSTA2 0x32 /* Link Status */
		#define PCI_EXP_LINKSTA2_DEEMPHASIS(x) ((x) & 1) /* Current D
		e-emphasis Level */
		#define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities
		*/
		#define PCI_EXP_SLTCTL2 0x38 /* Slot Control */
		#define PCI_EXP_SLTSTA2 0x3a /* Slot Status */

	/* MSI-X */	/* MSI-X */
	#define PCI_MSIX_ENABLE 0x8000	#define PCI_MSIX_ENABLE 0x8000
	#define PCI_MSIX_MASK 0x4000	#define PCI_MSIX_MASK 0x4000
	#define PCI_MSIX_TABSIZE 0x03ff	#define PCI_MSIX_TABSIZE 0x03ff
	#define PCI_MSIX_TABLE 4	#define PCI_MSIX_TABLE 4
	#define PCI_MSIX_PBA 8	#define PCI_MSIX_PBA 8
	#define PCI_MSIX_BIR 0x7	#define PCI_MSIX_BIR 0x7

	/* Subsystem vendor/device ID for PCI bridges */	/* Subsystem vendor/device ID for PCI bridges */
	#define PCI_SSVID_VENDOR 4	#define PCI_SSVID_VENDOR 4
	#define PCI_SSVID_DEVICE 6	#define PCI_SSVID_DEVICE 6

	/* Advanced Error Reporting */	/* Advanced Error Reporting */
	#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */	#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */

	#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */	#define PCI_ERR_UNC_TRAIN 0x00000001 /* Undefined in PCIe rev1.1 & 2.0 spec */
	#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */	#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */

		#define PCI_ERR_UNC_SDES 0x00000020 /* Surprise Down Error */
	#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */	#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
	#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */	#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
	#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */	#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
	#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort * /	#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort * /
	#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */	#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
	#define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */	#define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
	#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */	#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
	#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */	#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
	#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */	#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */

		#define PCI_ERR_UNC_ACS_VIOL 0x00200000 /* ACS Violation */
	#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */	#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
	/* Same bits as above */	/* Same bits as above */
	#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */	#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
	/* Same bits as above */	/* Same bits as above */
	#define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */	#define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */
	#define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */	#define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */
	#define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */	#define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
	#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */	#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
	#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */	#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
	#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */	#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */

		#define PCI_ERR_COR_REP_ANFE 0x00002000 /* Advisory Non-Fatal Error */
	#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */	#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
	/* Same bits as above */	/* Same bits as above */
	#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */	#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
	#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */	#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
	#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable * /	#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable * /
	#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */	#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
	#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */	#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
	#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */	#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
	#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */	#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
	#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */	#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */

	skipping to change at line 899	skipping to change at line 926
	#define PCI_PWR_DATA 8 /* Data Register */	#define PCI_PWR_DATA 8 /* Data Register */
	#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */	#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
	#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */	#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
	#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */	#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
	#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */	#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
	#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */	#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
	#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */	#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
	#define PCI_PWR_CAP 12 /* Capability */	#define PCI_PWR_CAP 12 /* Capability */
	#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */	#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */


		/* Access Control Services */
		#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
		#define PCI_ACS_CAP_VALID 0x0001 /* ACS Source Validation */
		#define PCI_ACS_CAP_BLOCK 0x0002 /* ACS Translation Blocking */
		#define PCI_ACS_CAP_REQ_RED 0x0004 /* ACS P2P Request Redirect */
		#define PCI_ACS_CAP_CMPLT_RED 0x0008 /* ACS P2P Completion Redirect */
		#define PCI_ACS_CAP_FORWARD 0x0010 /* ACS Upstream Forwarding */
		#define PCI_ACS_CAP_EGRESS 0x0020 /* ACS P2P Egress Control */
		#define PCI_ACS_CAP_TRANS 0x0040 /* ACS Direct Translated P2P */
		#define PCI_ACS_CAP_VECTOR(x) (((x) >> 8) & 0xff) /* Egress Control Vector
		Size */
		#define PCI_ACS_CTRL 0x06 /* ACS Control Register */
		#define PCI_ACS_CTRL_VALID 0x0001 /* ACS Source Validation Enable */
		#define PCI_ACS_CTRL_BLOCK 0x0002 /* ACS Translation Blocking Enable *
		/
		#define PCI_ACS_CTRL_REQ_RED 0x0004 /* ACS P2P Request Redirect Enable *
		/
		#define PCI_ACS_CTRL_CMPLT_RED 0x0008 /* ACS P2P Completion Redirect Enabl
		e */
		#define PCI_ACS_CTRL_FORWARD 0x0010 /* ACS Upstream Forwarding Enable */
		#define PCI_ACS_CTRL_EGRESS 0x0020 /* ACS P2P Egress Control Enable */
		#define PCI_ACS_CTRL_TRANS 0x0040 /* ACS Direct Translated P2P Enable
		*/
		#define PCI_ACS_EGRESS_CTRL 0x08 /* Egress Control Vector */

		/* Alternative Routing-ID Interpretation */
		#define PCI_ARI_CAP 0x04 /* ARI Capability Register */
		#define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability *
		/
		#define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */
		#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number
		*/
		#define PCI_ARI_CTRL 0x06 /* ARI Control Register */
		#define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */
		#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */
		#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */

		/* Single Root I/O Virtualization */
		#define PCI_IOV_CAP 0x04 /* SR-IOV Capability Register */
		#define PCI_IOV_CAP_VFM 0x00000001 /* VF Migration Capable */
		#define PCI_IOV_CAP_IMN(x) ((x) >> 21) /* VF Migration Interrupt Messag
		e Number */
		#define PCI_IOV_CTRL 0x08 /* SR-IOV Control Register */
		#define PCI_IOV_CTRL_VFE 0x0001 /* VF Enable */
		#define PCI_IOV_CTRL_VFME 0x0002 /* VF Migration Enable */
		#define PCI_IOV_CTRL_VFMIE 0x0004 /* VF Migration Interrupt Enable */
		#define PCI_IOV_CTRL_MSE 0x0008 /* VF MSE */
		#define PCI_IOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */
		#define PCI_IOV_STATUS 0x0a /* SR-IOV Status Register */
		#define PCI_IOV_STATUS_MS 0x0001 /* VF Migration Status */
		#define PCI_IOV_INITIALVF 0x0c /* Number of VFs that are initially
		associated */
		#define PCI_IOV_TOTALVF 0x0e /* Maximum number of VFs tha
		t could be associated */
		#define PCI_IOV_NUMVF 0x10 /* Number of VFs that are available
		*/
		#define PCI_IOV_FDL 0x12 /* Function Dependency Link */
		#define PCI_IOV_OFFSET 0x14 /* First VF Offset */
		#define PCI_IOV_STRIDE 0x16 /* Routing ID offset from one VF to
		the next one */
		#define PCI_IOV_DID 0x1a /* VF Device ID */
		#define PCI_IOV_SUPPS 0x1c /* Supported Page Sizes */
		#define PCI_IOV_SYSPS 0x20 /* System Page Size */
		#define PCI_IOV_BAR_BASE 0x24 /* VF BAR0, VF BAR1, ... VF BAR5 */
		#define PCI_IOV_NUM_BAR 6 /* Number of VF BARs */
		#define PCI_IOV_MSAO 0x3c /* VF Migration State Array Offset *
		/
		#define PCI_IOV_MSA_BIR(x) ((x) & 7) /* VF Migration State BIR */
		#define PCI_IOV_MSA_OFFSET(x) ((x) & 0xfffffff8) /* VF Migration State Off
		set */

	/*	/*
	* The PCI interface treats multi-function devices as independent	* The PCI interface treats multi-function devices as independent
	* devices. The slot/function address of each device is encoded	* devices. The slot/function address of each device is encoded
	* in a single byte as follows:	* in a single byte as follows:
	*	*
	* 7:3 = slot	* 7:3 = slot
	* 2:0 = function	* 2:0 = function
	*/	*/
	#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) \| ((func) & 0x07))	#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) \| ((func) & 0x07))
	#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)	#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)

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	1 lines changed or deleted	113 lines changed or added

	pci.h	pci.h

	skipping to change at line 12	skipping to change at line 12
	* The PCI Library	* The PCI Library
	*	*
	* Copyright (c) 1997--2008 Martin Mares <mj@ucw.cz>	* Copyright (c) 1997--2008 Martin Mares <mj@ucw.cz>
	*	*
	* Can be freely distributed and used under the terms of the GNU GPL.	* Can be freely distributed and used under the terms of the GNU GPL.
	*/	*/

	#ifndef _PCI_LIB_H	#ifndef _PCI_LIB_H
	#define _PCI_LIB_H	#define _PCI_LIB_H


		#ifndef PCI_CONFIG_H
	#include "config.h"	#include "config.h"

		#endif

	#include "header.h"	#include "header.h"
	#include "types.h"	#include "types.h"

	#define PCI_LIB_VERSION 0x030000	#define PCI_LIB_VERSION 0x030000

	#ifndef PCI_ABI	#ifndef PCI_ABI
	#define PCI_ABI	#define PCI_ABI
	#endif	#endif

	/*	/*

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