| config.h | config.h | |||
|---|---|---|---|---|
| skipping to change at line 14 | skipping to change at line 14 | |||
| #define PCI_HAVE_PM_LINUX_SYSFS | #define PCI_HAVE_PM_LINUX_SYSFS | |||
| #define PCI_HAVE_PM_LINUX_PROC | #define PCI_HAVE_PM_LINUX_PROC | |||
| #define PCI_HAVE_LINUX_BYTEORDER_H | #define PCI_HAVE_LINUX_BYTEORDER_H | |||
| #define PCI_PATH_PROC_BUS_PCI "/proc/bus/pci" | #define PCI_PATH_PROC_BUS_PCI "/proc/bus/pci" | |||
| #define PCI_PATH_SYS_BUS_PCI "/sys/bus/pci" | #define PCI_PATH_SYS_BUS_PCI "/sys/bus/pci" | |||
| #define PCI_HAVE_PM_INTEL_CONF | #define PCI_HAVE_PM_INTEL_CONF | |||
| #define PCI_HAVE_64BIT_ADDRESS | #define PCI_HAVE_64BIT_ADDRESS | |||
| #define PCI_HAVE_PM_DUMP | #define PCI_HAVE_PM_DUMP | |||
| #define PCI_COMPRESSED_IDS | #define PCI_COMPRESSED_IDS | |||
| #define PCI_IDS "pci.ids.gz" | #define PCI_IDS "pci.ids.gz" | |||
| #define PCI_PATH_IDS_DIR "/home/andrey/upstream-tracker/testing/pciutils/3. 0.2/share" | #define PCI_PATH_IDS_DIR "/home/andrey/upstream-tracker/testing/pciutils/3. 0.3/share" | |||
| #define PCI_USE_DNS | #define PCI_USE_DNS | |||
| #define PCI_ID_DOMAIN "pci.id.ucw.cz" | #define PCI_ID_DOMAIN "pci.id.ucw.cz" | |||
| #define PCI_SHARED_LIB | #define PCI_SHARED_LIB | |||
| #define PCILIB_VERSION "3.0.2" | #define PCILIB_VERSION "3.0.3" | |||
| End of changes. 2 change blocks. | ||||
| 1 lines changed or deleted | 1 lines changed or added | |||
| header.h | header.h | |||
|---|---|---|---|---|
| skipping to change at line 190 | skipping to change at line 190 | |||
| #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mod e base address (ExCa) */ | #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mod e base address (ExCa) */ | |||
| /* 0x48-0x7f reserved */ | /* 0x48-0x7f reserved */ | |||
| /* Capability lists */ | /* Capability lists */ | |||
| #define PCI_CAP_LIST_ID 0 /* Capability ID */ | #define PCI_CAP_LIST_ID 0 /* Capability ID */ | |||
| #define PCI_CAP_ID_PM 0x01 /* Power Management */ | #define PCI_CAP_ID_PM 0x01 /* Power Management */ | |||
| #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ | #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */ | |||
| #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ | #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ | |||
| #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ | #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */ | |||
| #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interru pts */ | #define PCI_CAP_ID_MSI 0x05 /* Message Signaled Interrup ts */ | |||
| #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ | #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */ | |||
| #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ | #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ | |||
| #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ | #define PCI_CAP_ID_HT 0x08 /* HyperTransport */ | |||
| #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */ | #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */ | |||
| #define PCI_CAP_ID_DBG 0x0A /* Debug port */ | #define PCI_CAP_ID_DBG 0x0A /* Debug port */ | |||
| #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Contr ol */ | #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Contr ol */ | |||
| #define PCI_CAP_ID_HOTPLUG 0x0C /* PCI hot-plug */ | #define PCI_CAP_ID_HOTPLUG 0x0C /* PCI hot-plug */ | |||
| #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ | #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */ | |||
| #define PCI_CAP_ID_AGP3 0x0E /* AGP 8x */ | #define PCI_CAP_ID_AGP3 0x0E /* AGP 8x */ | |||
| #define PCI_CAP_ID_SECURE 0x0F /* Secure device (?) */ | #define PCI_CAP_ID_SECURE 0x0F /* Secure device (?) */ | |||
| skipping to change at line 290 | skipping to change at line 290 | |||
| #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate (4x in AGP3 mode) */ | #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate (4x in AGP3 mode) */ | |||
| #define PCI_AGP_SIZEOF 12 | #define PCI_AGP_SIZEOF 12 | |||
| /* Slot Identification */ | /* Slot Identification */ | |||
| #define PCI_SID_ESR 2 /* Expansion Slot Register */ | #define PCI_SID_ESR 2 /* Expansion Slot Register */ | |||
| #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots availab le */ | #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots availab le */ | |||
| #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ | #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ | |||
| #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ | #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ | |||
| /* Message Signalled Interrupts registers */ | /* Message Signaled Interrupts registers */ | |||
| #define PCI_MSI_FLAGS 2 /* Various flags */ | #define PCI_MSI_FLAGS 2 /* Various flags */ | |||
| #define PCI_MSI_FLAGS_MASK_BIT 0x100 /* interrupt masking & repor ting supported */ | #define PCI_MSI_FLAGS_MASK_BIT 0x100 /* interrupt masking & repor ting supported */ | |||
| #define PCI_MSI_FLAGS_64BIT 0x080 /* 64-bit addresses allowed */ | #define PCI_MSI_FLAGS_64BIT 0x080 /* 64-bit addresses allowed */ | |||
| #define PCI_MSI_FLAGS_QSIZE 0x070 /* Message queue size configured */ | #define PCI_MSI_FLAGS_QSIZE 0x070 /* Message queue size configured */ | |||
| #define PCI_MSI_FLAGS_QMASK 0x00e /* Maximum queue size available */ | #define PCI_MSI_FLAGS_QMASK 0x00e /* Maximum queue size available */ | |||
| #define PCI_MSI_FLAGS_ENABLE 0x001 /* MSI feature enabled */ | #define PCI_MSI_FLAGS_ENABLE 0x001 /* MSI feature enabled */ | |||
| #define PCI_MSI_RFU 3 /* Rest of capability flags */ | #define PCI_MSI_RFU 3 /* Rest of capability flags */ | |||
| #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ | #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */ | |||
| #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_6 4BIT set) */ | #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_6 4BIT set) */ | |||
| End of changes. 2 change blocks. | ||||
| 2 lines changed or deleted | 2 lines changed or added | |||