config.h   config.h 
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#define PCI_HAVE_PM_LINUX_SYSFS #define PCI_HAVE_PM_LINUX_SYSFS
#define PCI_HAVE_PM_LINUX_PROC #define PCI_HAVE_PM_LINUX_PROC
#define PCI_HAVE_LINUX_BYTEORDER_H #define PCI_HAVE_LINUX_BYTEORDER_H
#define PCI_PATH_PROC_BUS_PCI "/proc/bus/pci" #define PCI_PATH_PROC_BUS_PCI "/proc/bus/pci"
#define PCI_PATH_SYS_BUS_PCI "/sys/bus/pci" #define PCI_PATH_SYS_BUS_PCI "/sys/bus/pci"
#define PCI_HAVE_PM_INTEL_CONF #define PCI_HAVE_PM_INTEL_CONF
#define PCI_HAVE_64BIT_ADDRESS #define PCI_HAVE_64BIT_ADDRESS
#define PCI_HAVE_PM_DUMP #define PCI_HAVE_PM_DUMP
#define PCI_COMPRESSED_IDS #define PCI_COMPRESSED_IDS
#define PCI_IDS "pci.ids.gz" #define PCI_IDS "pci.ids.gz"
#define PCI_PATH_IDS_DIR "/home/andrey/upstream-tracker/testing/pciutils/3. 0.3/share" #define PCI_PATH_IDS_DIR "/home/andrey/upstream-tracker/testing/pciutils/3. 1.0/share"
#define PCI_USE_DNS #define PCI_USE_DNS
#define PCI_ID_DOMAIN "pci.id.ucw.cz" #define PCI_ID_DOMAIN "pci.id.ucw.cz"
#define PCI_SHARED_LIB #define PCI_SHARED_LIB
#define PCILIB_VERSION "3.0.3" #define PCILIB_VERSION "3.1.0"
 End of changes. 2 change blocks. 
1 lines changed or deleted 1 lines changed or added


 header.h   header.h 
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#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
#define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */ #define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */
#define PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */ #define PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */
#define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declar ation */ #define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declar ation */
#define PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */ #define PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */ #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
#define PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */ #define PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */
#define PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */ #define PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */
#define PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */ #define PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */
#define PCI_EXT_CAP_ID_ARI 0x0e /* Alternative Routing-ID Interpreta tion */ #define PCI_EXT_CAP_ID_ARI 0x0e /* Alternative Routing-ID Interpreta tion */
#define PCI_EXT_CAP_ID_ATS 0x0f /* Address Translation Service */
#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
/* Power Management Registers */ /* Power Management Registers */
#define PCI_PM_CAP_VER_MASK 0x0007 /* Version (2=PM1.1) */ #define PCI_PM_CAP_VER_MASK 0x0007 /* Version (2=PM1.1) */
#define PCI_PM_CAP_PME_CLOCK 0x0008 /* Clock required for PME generation */ #define PCI_PM_CAP_PME_CLOCK 0x0008 /* Clock required for PME generation */
#define PCI_PM_CAP_DSI 0x0020 /* Device specific initializ ation required */ #define PCI_PM_CAP_DSI 0x0020 /* Device specific initializ ation required */
#define PCI_PM_CAP_AUX_C_MASK 0x01c0 /* Maximum aux current required in D 3cold */ #define PCI_PM_CAP_AUX_C_MASK 0x01c0 /* Maximum aux current required in D 3cold */
#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
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#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */ #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transacti ons */ #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transacti ons */
#define PCI_AGP_COMMAND_GART64 0x0080 /* 64-bit GART entries enabl ed */ #define PCI_AGP_COMMAND_GART64 0x0080 /* 64-bit GART entries enabl ed */
#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow generation of 64-bit addr c ycles */ #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow generation of 64-bit addr c ycles */
#define PCI_AGP_COMMAND_FW 0x0010 /* Enable FW transfers */ #define PCI_AGP_COMMAND_FW 0x0010 /* Enable FW transfers */
#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate (RFU in AGP3 mode) */ #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate (RFU in AGP3 mode) */
#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate (8x in AGP3 mode) */ #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate (8x in AGP3 mode) */
#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate (4x in AGP3 mode) */ #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate (4x in AGP3 mode) */
#define PCI_AGP_SIZEOF 12 #define PCI_AGP_SIZEOF 12
/* Vital Product Data */
#define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates comp
letion */
#define PCI_VPD_DATA 4 /* 32-bits of data returned here */
/* Slot Identification */ /* Slot Identification */
#define PCI_SID_ESR 2 /* Expansion Slot Register */ #define PCI_SID_ESR 2 /* Expansion Slot Register */
#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots availab le */ #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots availab le */
#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
/* Message Signaled Interrupts registers */ /* Message Signaled Interrupts registers */
#define PCI_MSI_FLAGS 2 /* Various flags */ #define PCI_MSI_FLAGS 2 /* Various flags */
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/* Alternative Routing-ID Interpretation */ /* Alternative Routing-ID Interpretation */
#define PCI_ARI_CAP 0x04 /* ARI Capability Register */ #define PCI_ARI_CAP 0x04 /* ARI Capability Register */
#define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability * / #define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability * /
#define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */ #define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */
#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */ #define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */
#define PCI_ARI_CTRL 0x06 /* ARI Control Register */ #define PCI_ARI_CTRL 0x06 /* ARI Control Register */
#define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */ #define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */
#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */ #define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */
#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */ #define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */
/* Address Translation Service */
#define PCI_ATS_CAP 0x04 /* ATS Capability Register */
#define PCI_ATS_CAP_IQD(x) ((x) & 0x1f) /* Invalidate Queue Depth */
#define PCI_ATS_CTRL 0x06 /* ATS Control Register */
#define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) /* Smallest Translation Unit */
#define PCI_ATS_CTRL_ENABLE 0x8000 /* ATS Enable */
/* Single Root I/O Virtualization */ /* Single Root I/O Virtualization */
#define PCI_IOV_CAP 0x04 /* SR-IOV Capability Register */ #define PCI_IOV_CAP 0x04 /* SR-IOV Capability Register */
#define PCI_IOV_CAP_VFM 0x00000001 /* VF Migration Capable */ #define PCI_IOV_CAP_VFM 0x00000001 /* VF Migration Capable */
#define PCI_IOV_CAP_IMN(x) ((x) >> 21) /* VF Migration Interrupt Messag e Number */ #define PCI_IOV_CAP_IMN(x) ((x) >> 21) /* VF Migration Interrupt Messag e Number */
#define PCI_IOV_CTRL 0x08 /* SR-IOV Control Register */ #define PCI_IOV_CTRL 0x08 /* SR-IOV Control Register */
#define PCI_IOV_CTRL_VFE 0x0001 /* VF Enable */ #define PCI_IOV_CTRL_VFE 0x0001 /* VF Enable */
#define PCI_IOV_CTRL_VFME 0x0002 /* VF Migration Enable */ #define PCI_IOV_CTRL_VFME 0x0002 /* VF Migration Enable */
#define PCI_IOV_CTRL_VFMIE 0x0004 /* VF Migration Interrupt Enable */ #define PCI_IOV_CTRL_VFMIE 0x0004 /* VF Migration Interrupt Enable */
#define PCI_IOV_CTRL_MSE 0x0008 /* VF MSE */ #define PCI_IOV_CTRL_MSE 0x0008 /* VF MSE */
#define PCI_IOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */ #define PCI_IOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */
 End of changes. 3 change blocks. 
0 lines changed or deleted 16 lines changed or added


 pci.h   pci.h 
/* /*
* The PCI Library * The PCI Library
* *
* Copyright (c) 1997--2008 Martin Mares <mj@ucw.cz> * Copyright (c) 1997--2009 Martin Mares <mj@ucw.cz>
* *
* Can be freely distributed and used under the terms of the GNU GPL. * Can be freely distributed and used under the terms of the GNU GPL.
*/ */
#ifndef _PCI_LIB_H #ifndef _PCI_LIB_H
#define _PCI_LIB_H #define _PCI_LIB_H
#ifndef PCI_CONFIG_H #ifndef PCI_CONFIG_H
#include "config.h" #include "config.h"
#endif #endif
#include "header.h" #include "header.h"
#include "types.h" #include "types.h"
#define PCI_LIB_VERSION 0x030000 #define PCI_LIB_VERSION 0x030100
#ifndef PCI_ABI #ifndef PCI_ABI
#define PCI_ABI #define PCI_ABI
#endif #endif
/* /*
* PCI Access Structure * PCI Access Structure
*/ */
struct pci_methods; struct pci_methods;
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struct pci_dev *devices; /* Devices found on this bus */ struct pci_dev *devices; /* Devices found on this bus */
/* Fields used internally: */ /* Fields used internally: */
struct pci_methods *methods; struct pci_methods *methods;
struct pci_param *params; struct pci_param *params;
struct id_entry **id_hash; /* names.c */ struct id_entry **id_hash; /* names.c */
struct id_bucket *current_id_bucket; struct id_bucket *current_id_bucket;
int id_load_failed; int id_load_failed;
int id_cache_status; /* 0=not read, 1=read, 2=dirty */ int id_cache_status; /* 0=not read, 1=read, 2=dirty */
int fd; /* proc: fd */ int fd; /* proc/sys: fd for config space */
int fd_rw; /* proc: fd opened read-write */ int fd_rw; /* proc/sys: fd opened read-write */
struct pci_dev *cached_dev; /* proc: device the fd is for */ int fd_pos; /* proc/sys: current position */
int fd_pos; /* proc: current position */ int fd_vpd; /* sys: fd for VPD */
struct pci_dev *cached_dev; /* proc/sys: device the fds are for
*/
}; };
/* Initialize PCI access */ /* Initialize PCI access */
struct pci_access *pci_alloc(void) PCI_ABI; struct pci_access *pci_alloc(void) PCI_ABI;
void pci_init(struct pci_access *) PCI_ABI; void pci_init(struct pci_access *) PCI_ABI;
void pci_cleanup(struct pci_access *) PCI_ABI; void pci_cleanup(struct pci_access *) PCI_ABI;
/* Scanning of devices */ /* Scanning of devices */
void pci_scan_bus(struct pci_access *acc) PCI_ABI; void pci_scan_bus(struct pci_access *acc) PCI_ABI;
struct pci_dev *pci_get_dev(struct pci_access *acc, int domain, int bus, in t dev, int func) PCI_ABI; /* Raw access to specified device */ struct pci_dev *pci_get_dev(struct pci_access *acc, int domain, int bus, in t dev, int func) PCI_ABI; /* Raw access to specified device */
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/* These fields are set by pci_fill_info() */ /* These fields are set by pci_fill_info() */
int known_fields; /* Set of info fields already known */ int known_fields; /* Set of info fields already known */
u16 vendor_id, device_id; /* Identity of the device */ u16 vendor_id, device_id; /* Identity of the device */
u16 device_class; /* PCI device class */ u16 device_class; /* PCI device class */
int irq; /* IRQ number */ int irq; /* IRQ number */
pciaddr_t base_addr[6]; /* Base addresses */ pciaddr_t base_addr[6]; /* Base addresses */
pciaddr_t size[6]; /* Region sizes */ pciaddr_t size[6]; /* Region sizes */
pciaddr_t rom_base_addr; /* Expansion ROM base address */ pciaddr_t rom_base_addr; /* Expansion ROM base address */
pciaddr_t rom_size; /* Expansion ROM size */ pciaddr_t rom_size; /* Expansion ROM size */
struct pci_cap *first_cap; /* List of capabilities */
char *phy_slot; /* Physical slot */
/* Fields used internally: */ /* Fields used internally: */
struct pci_access *access; struct pci_access *access;
struct pci_methods *methods; struct pci_methods *methods;
u8 *cache; /* Cached config registers */ u8 *cache; /* Cached config registers */
int cache_len; int cache_len;
int hdrtype; /* Cached low 7 bits of header type, -1 if unknown */ int hdrtype; /* Cached low 7 bits of header type, -1 if unknown */
void *aux; /* Auxillary data */ void *aux; /* Auxillary data */
}; };
#define PCI_ADDR_IO_MASK (~(pciaddr_t) 0x3) #define PCI_ADDR_IO_MASK (~(pciaddr_t) 0x3)
#define PCI_ADDR_MEM_MASK (~(pciaddr_t) 0xf) #define PCI_ADDR_MEM_MASK (~(pciaddr_t) 0xf)
#define PCI_ADDR_FLAG_MASK 0xf
u8 pci_read_byte(struct pci_dev *, int pos) PCI_ABI; /* Access to configura tion space */ u8 pci_read_byte(struct pci_dev *, int pos) PCI_ABI; /* Access to configura tion space */
u16 pci_read_word(struct pci_dev *, int pos) PCI_ABI; u16 pci_read_word(struct pci_dev *, int pos) PCI_ABI;
u32 pci_read_long(struct pci_dev *, int pos) PCI_ABI; u32 pci_read_long(struct pci_dev *, int pos) PCI_ABI;
int pci_read_block(struct pci_dev *, int pos, u8 *buf, int len) PCI_ABI; int pci_read_block(struct pci_dev *, int pos, u8 *buf, int len) PCI_ABI;
int pci_read_vpd(struct pci_dev *d, int pos, u8 *buf, int len) PCI_ABI;
int pci_write_byte(struct pci_dev *, int pos, u8 data) PCI_ABI; int pci_write_byte(struct pci_dev *, int pos, u8 data) PCI_ABI;
int pci_write_word(struct pci_dev *, int pos, u16 data) PCI_ABI; int pci_write_word(struct pci_dev *, int pos, u16 data) PCI_ABI;
int pci_write_long(struct pci_dev *, int pos, u32 data) PCI_ABI; int pci_write_long(struct pci_dev *, int pos, u32 data) PCI_ABI;
int pci_write_block(struct pci_dev *, int pos, u8 *buf, int len) PCI_ABI; int pci_write_block(struct pci_dev *, int pos, u8 *buf, int len) PCI_ABI;
int pci_fill_info(struct pci_dev *, int flags) PCI_ABI; /* Fill in device i nformation */ int pci_fill_info(struct pci_dev *, int flags) PCI_ABI; /* Fill in device i nformation */
#define PCI_FILL_IDENT 1 #define PCI_FILL_IDENT 1
#define PCI_FILL_IRQ 2 #define PCI_FILL_IRQ 2
#define PCI_FILL_BASES 4 #define PCI_FILL_BASES 4
#define PCI_FILL_ROM_BASE 8 #define PCI_FILL_ROM_BASE 8
#define PCI_FILL_SIZES 16 #define PCI_FILL_SIZES 16
#define PCI_FILL_CLASS 32 #define PCI_FILL_CLASS 32
#define PCI_FILL_CAPS 64
#define PCI_FILL_EXT_CAPS 128
#define PCI_FILL_PHYS_SLOT 256
#define PCI_FILL_RESCAN 0x10000 #define PCI_FILL_RESCAN 0x10000
void pci_setup_cache(struct pci_dev *, u8 *cache, int len) PCI_ABI; void pci_setup_cache(struct pci_dev *, u8 *cache, int len) PCI_ABI;
/* /*
* Capabilities
*/
struct pci_cap {
struct pci_cap *next;
u16 id; /* PCI_CAP_ID_xxx */
u16 type; /* PCI_CAP_xxx */
unsigned int addr; /* Position in the config space */
};
#define PCI_CAP_NORMAL 1 /* Traditional PCI capabilities */
#define PCI_CAP_EXTENDED 2 /* PCIe extended capabilities */
struct pci_cap *pci_find_cap(struct pci_dev *, unsigned int id, unsigned in
t type) PCI_ABI;
/*
* Filters * Filters
*/ */
struct pci_filter { struct pci_filter {
int domain, bus, slot, func; /* -1 = ANY */ int domain, bus, slot, func; /* -1 = ANY */
int vendor, device; int vendor, device;
}; };
void pci_filter_init(struct pci_access *, struct pci_filter *) PCI_ABI; void pci_filter_init(struct pci_access *, struct pci_filter *) PCI_ABI;
char *pci_filter_parse_slot(struct pci_filter *, char *) PCI_ABI; char *pci_filter_parse_slot(struct pci_filter *, char *) PCI_ABI;
 End of changes. 8 change blocks. 
6 lines changed or deleted 32 lines changed or added

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