config.h   config.h 
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#define PCI_HAVE_PM_LINUX_SYSFS #define PCI_HAVE_PM_LINUX_SYSFS
#define PCI_HAVE_PM_LINUX_PROC #define PCI_HAVE_PM_LINUX_PROC
#define PCI_HAVE_LINUX_BYTEORDER_H #define PCI_HAVE_LINUX_BYTEORDER_H
#define PCI_PATH_PROC_BUS_PCI "/proc/bus/pci" #define PCI_PATH_PROC_BUS_PCI "/proc/bus/pci"
#define PCI_PATH_SYS_BUS_PCI "/sys/bus/pci" #define PCI_PATH_SYS_BUS_PCI "/sys/bus/pci"
#define PCI_HAVE_PM_INTEL_CONF #define PCI_HAVE_PM_INTEL_CONF
#define PCI_HAVE_64BIT_ADDRESS #define PCI_HAVE_64BIT_ADDRESS
#define PCI_HAVE_PM_DUMP #define PCI_HAVE_PM_DUMP
#define PCI_COMPRESSED_IDS #define PCI_COMPRESSED_IDS
#define PCI_IDS "pci.ids.gz" #define PCI_IDS "pci.ids.gz"
#define PCI_PATH_IDS_DIR "/home/andrey/upstream-tracker/testing/pciutils/3. 1.2/share" #define PCI_PATH_IDS_DIR "/home/andrey/upstream-tracker/testing/pciutils/3. 1.3/share"
#define PCI_USE_DNS #define PCI_USE_DNS
#define PCI_ID_DOMAIN "pci.id.ucw.cz" #define PCI_ID_DOMAIN "pci.id.ucw.cz"
#define PCI_SHARED_LIB #define PCI_SHARED_LIB
#define PCILIB_VERSION "3.1.2" #define PCILIB_VERSION "3.1.3"
 End of changes. 2 change blocks. 
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 header.h   header.h 
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#define PCI_PM_CAP_AUX_C_MASK 0x01c0 /* Maximum aux current required in D 3cold */ #define PCI_PM_CAP_AUX_C_MASK 0x01c0 /* Maximum aux current required in D 3cold */
#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
#define PCI_PM_CAP_PME_D0 0x0800 /* PME can be asserted from D0 */ #define PCI_PM_CAP_PME_D0 0x0800 /* PME can be asserted from D0 */
#define PCI_PM_CAP_PME_D1 0x1000 /* PME can be asserted from D1 */ #define PCI_PM_CAP_PME_D1 0x1000 /* PME can be asserted from D1 */
#define PCI_PM_CAP_PME_D2 0x2000 /* PME can be asserted from D2 */ #define PCI_PM_CAP_PME_D2 0x2000 /* PME can be asserted from D2 */
#define PCI_PM_CAP_PME_D3_HOT 0x4000 /* PME can be asserted from D3hot */ #define PCI_PM_CAP_PME_D3_HOT 0x4000 /* PME can be asserted from D3hot */
#define PCI_PM_CAP_PME_D3_COLD 0x8000 /* PME can be asserted from D3cold */ #define PCI_PM_CAP_PME_D3_COLD 0x8000 /* PME can be asserted from D3cold */
#define PCI_PM_CTRL 4 /* PM control and status register */ #define PCI_PM_CTRL 4 /* PM control and status register */
#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 t o D3) */ #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 t o D3) */
#define PCI_PM_CTRL_NO_SOFT_RST 0x0008 /* No Soft Reset from D3hot to D0 */
#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* PM table data index */ #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* PM table data index */
#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* PM table data scaling fac tor */ #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* PM table data scaling fac tor */
#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */ #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions */ #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions */
#define PCI_PM_PPB_B2_B3 0x40 /* If bridge enters D3hot, bus enter s: 0=B3, 1=B2 */ #define PCI_PM_PPB_B2_B3 0x40 /* If bridge enters D3hot, bus enter s: 0=B3, 1=B2 */
#define PCI_PM_BPCC_ENABLE 0x80 /* Secondary bus is power managed */ #define PCI_PM_BPCC_ENABLE 0x80 /* Secondary bus is power managed */
#define PCI_PM_DATA_REGISTER 7 /* PM table contents read here */ #define PCI_PM_DATA_REGISTER 7 /* PM table contents read here */
#define PCI_PM_SIZEOF 8 #define PCI_PM_SIZEOF 8
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#define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 1) /* Compliance De-emphasis */ #define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 1) /* Compliance De-emphasis */
#define PCI_EXP_LNKSTA2 0x32 /* Link Status */ #define PCI_EXP_LNKSTA2 0x32 /* Link Status */
#define PCI_EXP_LINKSTA2_DEEMPHASIS(x) ((x) & 1) /* Current D e-emphasis Level */ #define PCI_EXP_LINKSTA2_DEEMPHASIS(x) ((x) & 1) /* Current D e-emphasis Level */
#define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities */ #define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities */
#define PCI_EXP_SLTCTL2 0x38 /* Slot Control */ #define PCI_EXP_SLTCTL2 0x38 /* Slot Control */
#define PCI_EXP_SLTSTA2 0x3a /* Slot Status */ #define PCI_EXP_SLTSTA2 0x3a /* Slot Status */
/* MSI-X */ /* MSI-X */
#define PCI_MSIX_ENABLE 0x8000 #define PCI_MSIX_ENABLE 0x8000
#define PCI_MSIX_MASK 0x4000 #define PCI_MSIX_MASK 0x4000
#define PCI_MSIX_TABSIZE 0x03ff #define PCI_MSIX_TABSIZE 0x07ff
#define PCI_MSIX_TABLE 4 #define PCI_MSIX_TABLE 4
#define PCI_MSIX_PBA 8 #define PCI_MSIX_PBA 8
#define PCI_MSIX_BIR 0x7 #define PCI_MSIX_BIR 0x7
/* Subsystem vendor/device ID for PCI bridges */ /* Subsystem vendor/device ID for PCI bridges */
#define PCI_SSVID_VENDOR 4 #define PCI_SSVID_VENDOR 4
#define PCI_SSVID_DEVICE 6 #define PCI_SSVID_DEVICE 6
/* PCI Advanced Features */
#define PCI_AF_CAP 3
#define PCI_AF_CAP_TP 0x01
#define PCI_AF_CAP_FLR 0x02
#define PCI_AF_CTRL 4
#define PCI_AF_CTRL_FLR 0x01
#define PCI_AF_STATUS 5
#define PCI_AF_STATUS_TP 0x01
/* Advanced Error Reporting */ /* Advanced Error Reporting */
#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
#define PCI_ERR_UNC_TRAIN 0x00000001 /* Undefined in PCIe rev1.1 & 2.0 spec */ #define PCI_ERR_UNC_TRAIN 0x00000001 /* Undefined in PCIe rev1.1 & 2.0 spec */
#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ #define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
#define PCI_ERR_UNC_SDES 0x00000020 /* Surprise Down Error */ #define PCI_ERR_UNC_SDES 0x00000020 /* Surprise Down Error */
#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ #define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ #define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ #define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort * / #define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort * /
#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */ #define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
 End of changes. 3 change blocks. 
1 lines changed or deleted 11 lines changed or added


 pci.h   pci.h 
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struct pci_dev { struct pci_dev {
struct pci_dev *next; /* Next device in the chain */ struct pci_dev *next; /* Next device in the chain */
u16 domain; /* PCI domain (host bridge) */ u16 domain; /* PCI domain (host bridge) */
u8 bus, dev, func; /* Bus inside domain, device and fun ction */ u8 bus, dev, func; /* Bus inside domain, device and fun ction */
/* These fields are set by pci_fill_info() */ /* These fields are set by pci_fill_info() */
int known_fields; /* Set of info fields already known */ int known_fields; /* Set of info fields already known */
u16 vendor_id, device_id; /* Identity of the device */ u16 vendor_id, device_id; /* Identity of the device */
u16 device_class; /* PCI device class */ u16 device_class; /* PCI device class */
int irq; /* IRQ number */ int irq; /* IRQ number */
pciaddr_t base_addr[6]; /* Base addresses */ pciaddr_t base_addr[6]; /* Base addresses including flags in lower bits */
pciaddr_t size[6]; /* Region sizes */ pciaddr_t size[6]; /* Region sizes */
pciaddr_t rom_base_addr; /* Expansion ROM base address */ pciaddr_t rom_base_addr; /* Expansion ROM base address */
pciaddr_t rom_size; /* Expansion ROM size */ pciaddr_t rom_size; /* Expansion ROM size */
struct pci_cap *first_cap; /* List of capabilities */ struct pci_cap *first_cap; /* List of capabilities */
char *phy_slot; /* Physical slot */ char *phy_slot; /* Physical slot */
/* Fields used internally: */ /* Fields used internally: */
struct pci_access *access; struct pci_access *access;
struct pci_methods *methods; struct pci_methods *methods;
u8 *cache; /* Cached config registers */ u8 *cache; /* Cached config registers */
 End of changes. 1 change blocks. 
1 lines changed or deleted 1 lines changed or added

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