config.h   config.h 
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#define PCI_HAVE_PM_LINUX_SYSFS #define PCI_HAVE_PM_LINUX_SYSFS
#define PCI_HAVE_PM_LINUX_PROC #define PCI_HAVE_PM_LINUX_PROC
#define PCI_HAVE_LINUX_BYTEORDER_H #define PCI_HAVE_LINUX_BYTEORDER_H
#define PCI_PATH_PROC_BUS_PCI "/proc/bus/pci" #define PCI_PATH_PROC_BUS_PCI "/proc/bus/pci"
#define PCI_PATH_SYS_BUS_PCI "/sys/bus/pci" #define PCI_PATH_SYS_BUS_PCI "/sys/bus/pci"
#define PCI_HAVE_PM_INTEL_CONF #define PCI_HAVE_PM_INTEL_CONF
#define PCI_HAVE_64BIT_ADDRESS #define PCI_HAVE_64BIT_ADDRESS
#define PCI_HAVE_PM_DUMP #define PCI_HAVE_PM_DUMP
#define PCI_COMPRESSED_IDS #define PCI_COMPRESSED_IDS
#define PCI_IDS "pci.ids.gz" #define PCI_IDS "pci.ids.gz"
#define PCI_PATH_IDS_DIR "/home/andrey/upstream-tracker/testing/pciutils/3. 1.5/share" #define PCI_PATH_IDS_DIR "/home/andrey/upstream-tracker/testing/pciutils/3. 1.6/share"
#define PCI_USE_DNS #define PCI_USE_DNS
#define PCI_ID_DOMAIN "pci.id.ucw.cz" #define PCI_ID_DOMAIN "pci.id.ucw.cz"
#define PCI_SHARED_LIB #define PCI_SHARED_LIB
#define PCILIB_VERSION "3.1.5" #define PCILIB_VERSION "3.1.6"
 End of changes. 2 change blocks. 
1 lines changed or deleted 1 lines changed or added


 header.h   header.h 
/* /*
* The PCI Library -- PCI Header Structure (based on <linux/pci.h>) * The PCI Library -- PCI Header Structure (based on <linux/pci.h>)
* *
* Copyright (c) 1997--2007 Martin Mares <mj@ucw.cz> * Copyright (c) 1997--2010 Martin Mares <mj@ucw.cz>
* *
* Can be freely distributed and used under the terms of the GNU GPL. * Can be freely distributed and used under the terms of the GNU GPL.
*/ */
/* /*
* Under PCI, each device has 256 bytes of configuration address space, * Under PCI, each device has 256 bytes of configuration address space,
* of which the first 64 bytes are standardized as follows: * of which the first 64 bytes are standardized as follows:
*/ */
#define PCI_VENDOR_ID 0x00 /* 16 bits */ #define PCI_VENDOR_ID 0x00 /* 16 bits */
#define PCI_DEVICE_ID 0x02 /* 16 bits */ #define PCI_DEVICE_ID 0x02 /* 16 bits */
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/* Capabilities residing in the PCI Express extended configuration space */ /* Capabilities residing in the PCI Express extended configuration space */
#define PCI_EXT_CAP_ID_AER 0x01 /* Advanced Error Reporting */ #define PCI_EXT_CAP_ID_AER 0x01 /* Advanced Error Reporting */
#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */ #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel */
#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
#define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */ #define PCI_EXT_CAP_ID_PB 0x04 /* Power Budgeting */
#define PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */ #define PCI_EXT_CAP_ID_RCLINK 0x05 /* Root Complex Link Declaration */
#define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declar ation */ #define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declar ation */
#define PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */ #define PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */ #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
#define PCI_EXT_CAP_ID_VC2 0x09 /* Virtual Channel (2nd ID) */
#define PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */ #define PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */
#define PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */ #define PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */
#define PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */ #define PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */
#define PCI_EXT_CAP_ID_ARI 0x0e /* Alternative Routing-ID Interpreta tion */ #define PCI_EXT_CAP_ID_ARI 0x0e /* Alternative Routing-ID Interpreta tion */
#define PCI_EXT_CAP_ID_ATS 0x0f /* Address Translation Service */ #define PCI_EXT_CAP_ID_ATS 0x0f /* Address Translation Service */
#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
/*** Definitions of capabilities ***/
/* Power Management Registers */ /* Power Management Registers */
#define PCI_PM_CAP_VER_MASK 0x0007 /* Version (2=PM1.1) */ #define PCI_PM_CAP_VER_MASK 0x0007 /* Version (2=PM1.1) */
#define PCI_PM_CAP_PME_CLOCK 0x0008 /* Clock required for PME generation */ #define PCI_PM_CAP_PME_CLOCK 0x0008 /* Clock required for PME generation */
#define PCI_PM_CAP_DSI 0x0020 /* Device specific initializ ation required */ #define PCI_PM_CAP_DSI 0x0020 /* Device specific initializ ation required */
#define PCI_PM_CAP_AUX_C_MASK 0x01c0 /* Maximum aux current required in D 3cold */ #define PCI_PM_CAP_AUX_C_MASK 0x01c0 /* Maximum aux current required in D 3cold */
#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */ #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
#define PCI_PM_CAP_PME_D0 0x0800 /* PME can be asserted from D0 */ #define PCI_PM_CAP_PME_D0 0x0800 /* PME can be asserted from D0 */
#define PCI_PM_CAP_PME_D1 0x1000 /* PME can be asserted from D1 */ #define PCI_PM_CAP_PME_D1 0x1000 /* PME can be asserted from D1 */
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#define PCI_HT_RM_STS0 5 /* Status 0 Register */ #define PCI_HT_RM_STS0 5 /* Status 0 Register */
#define PCI_HT_RM_STS_RETSNT 0x01 /* Retry Sent */ #define PCI_HT_RM_STS_RETSNT 0x01 /* Retry Sent */
#define PCI_HT_RM_STS_CNTROL 0x02 /* Count Rollover */ #define PCI_HT_RM_STS_CNTROL 0x02 /* Count Rollover */
#define PCI_HT_RM_STS_SRCV 0x04 /* Stomp Received */ #define PCI_HT_RM_STS_SRCV 0x04 /* Stomp Received */
#define PCI_HT_RM_CTR1 6 /* Control 1 Register */ #define PCI_HT_RM_CTR1 6 /* Control 1 Register */
#define PCI_HT_RM_STS1 7 /* Status 1 Register */ #define PCI_HT_RM_STS1 7 /* Status 1 Register */
#define PCI_HT_RM_CNT0 8 /* Retry Count 0 Register */ #define PCI_HT_RM_CNT0 8 /* Retry Count 0 Register */
#define PCI_HT_RM_CNT1 10 /* Retry Count 1 Register */ #define PCI_HT_RM_CNT1 10 /* Retry Count 1 Register */
#define PCI_HT_RM_SIZEOF 12 #define PCI_HT_RM_SIZEOF 12
/* Vendor-Specific Capability (see PCI_EVNDR_xxx for the PCIe version) */
#define PCI_VNDR_LENGTH 2 /* Length byte */
/* PCI Express */ /* PCI Express */
#define PCI_EXP_FLAGS 0x2 /* Capabilities register */ #define PCI_EXP_FLAGS 0x2 /* Capabilities register */
#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ #define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ #define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ #define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */ #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
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/* PCI Advanced Features */ /* PCI Advanced Features */
#define PCI_AF_CAP 3 #define PCI_AF_CAP 3
#define PCI_AF_CAP_TP 0x01 #define PCI_AF_CAP_TP 0x01
#define PCI_AF_CAP_FLR 0x02 #define PCI_AF_CAP_FLR 0x02
#define PCI_AF_CTRL 4 #define PCI_AF_CTRL 4
#define PCI_AF_CTRL_FLR 0x01 #define PCI_AF_CTRL_FLR 0x01
#define PCI_AF_STATUS 5 #define PCI_AF_STATUS 5
#define PCI_AF_STATUS_TP 0x01 #define PCI_AF_STATUS_TP 0x01
/* SATA Host Bus Adapter */
#define PCI_SATA_HBA_BARS 4
#define PCI_SATA_HBA_REG0 8
/*** Definitions of extended capabilities ***/
/* Advanced Error Reporting */ /* Advanced Error Reporting */
#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
#define PCI_ERR_UNC_TRAIN 0x00000001 /* Undefined in PCIe rev1.1 & 2.0 spec */ #define PCI_ERR_UNC_TRAIN 0x00000001 /* Undefined in PCIe rev1.1 & 2.0 spec */
#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ #define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
#define PCI_ERR_UNC_SDES 0x00000020 /* Surprise Down Error */ #define PCI_ERR_UNC_SDES 0x00000020 /* Surprise Down Error */
#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ #define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */ #define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */ #define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort * / #define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort * /
#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */ #define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
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#define PCI_PWR_DATA 8 /* Data Register */ #define PCI_PWR_DATA 8 /* Data Register */
#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */ #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */ #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */ #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */ #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */ #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */ #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
#define PCI_PWR_CAP 12 /* Capability */ #define PCI_PWR_CAP 12 /* Capability */
#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
/* Root Complex Link */
#define PCI_RCLINK_ESD 4 /* Element Self Description */
#define PCI_RCLINK_LINK1 16 /* First Link Entry */
#define PCI_RCLINK_LINK_DESC 0 /* Link Entry: Description */
#define PCI_RCLINK_LINK_ADDR 8 /* Link Entry: Address (64-bit) */
#define PCI_RCLINK_LINK_SIZE 16 /* Link Entry: sizeof */
/* PCIe Vendor-Specific Capability */
#define PCI_EVNDR_HEADER 4 /* Vendor-Specific Header */
#define PCI_EVNDR_REGISTERS 8 /* Vendor-Specific Registers */
/* Access Control Services */ /* Access Control Services */
#define PCI_ACS_CAP 0x04 /* ACS Capability Register */ #define PCI_ACS_CAP 0x04 /* ACS Capability Register */
#define PCI_ACS_CAP_VALID 0x0001 /* ACS Source Validation */ #define PCI_ACS_CAP_VALID 0x0001 /* ACS Source Validation */
#define PCI_ACS_CAP_BLOCK 0x0002 /* ACS Translation Blocking */ #define PCI_ACS_CAP_BLOCK 0x0002 /* ACS Translation Blocking */
#define PCI_ACS_CAP_REQ_RED 0x0004 /* ACS P2P Request Redirect */ #define PCI_ACS_CAP_REQ_RED 0x0004 /* ACS P2P Request Redirect */
#define PCI_ACS_CAP_CMPLT_RED 0x0008 /* ACS P2P Completion Redirect */ #define PCI_ACS_CAP_CMPLT_RED 0x0008 /* ACS P2P Completion Redirect */
#define PCI_ACS_CAP_FORWARD 0x0010 /* ACS Upstream Forwarding */ #define PCI_ACS_CAP_FORWARD 0x0010 /* ACS Upstream Forwarding */
#define PCI_ACS_CAP_EGRESS 0x0020 /* ACS P2P Egress Control */ #define PCI_ACS_CAP_EGRESS 0x0020 /* ACS P2P Egress Control */
#define PCI_ACS_CAP_TRANS 0x0040 /* ACS Direct Translated P2P */ #define PCI_ACS_CAP_TRANS 0x0040 /* ACS Direct Translated P2P */
#define PCI_ACS_CAP_VECTOR(x) (((x) >> 8) & 0xff) /* Egress Control Vector Size */ #define PCI_ACS_CAP_VECTOR(x) (((x) >> 8) & 0xff) /* Egress Control Vector Size */
 End of changes. 6 change blocks. 
1 lines changed or deleted 24 lines changed or added

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