config.h   config.h 
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#define PCI_HAVE_PM_LINUX_SYSFS #define PCI_HAVE_PM_LINUX_SYSFS
#define PCI_HAVE_PM_LINUX_PROC #define PCI_HAVE_PM_LINUX_PROC
#define PCI_HAVE_LINUX_BYTEORDER_H #define PCI_HAVE_LINUX_BYTEORDER_H
#define PCI_PATH_PROC_BUS_PCI "/proc/bus/pci" #define PCI_PATH_PROC_BUS_PCI "/proc/bus/pci"
#define PCI_PATH_SYS_BUS_PCI "/sys/bus/pci" #define PCI_PATH_SYS_BUS_PCI "/sys/bus/pci"
#define PCI_HAVE_PM_INTEL_CONF #define PCI_HAVE_PM_INTEL_CONF
#define PCI_HAVE_64BIT_ADDRESS #define PCI_HAVE_64BIT_ADDRESS
#define PCI_HAVE_PM_DUMP #define PCI_HAVE_PM_DUMP
#define PCI_COMPRESSED_IDS #define PCI_COMPRESSED_IDS
#define PCI_IDS "pci.ids.gz" #define PCI_IDS "pci.ids.gz"
#define PCI_PATH_IDS_DIR "/home/andrey/upstream-tracker/testing/pciutils/3. 1.7/share" #define PCI_PATH_IDS_DIR "/home/andrey/upstream-tracker/testing/pciutils/3. 1.8/share"
#define PCI_USE_DNS #define PCI_USE_DNS
#define PCI_ID_DOMAIN "pci.id.ucw.cz" #define PCI_ID_DOMAIN "pci.id.ucw.cz"
#define PCI_SHARED_LIB #define PCI_SHARED_LIB
#define PCILIB_VERSION "3.1.7" #define PCILIB_VERSION "3.1.8"
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 header.h   header.h 
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#define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declar ation */ #define PCI_EXT_CAP_ID_RCILINK 0x06 /* Root Complex Internal Link Declar ation */
#define PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */ #define PCI_EXT_CAP_ID_RCECOLL 0x07 /* Root Complex Event Collector */
#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */ #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function Virtual Channel */
#define PCI_EXT_CAP_ID_VC2 0x09 /* Virtual Channel (2nd ID) */ #define PCI_EXT_CAP_ID_VC2 0x09 /* Virtual Channel (2nd ID) */
#define PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */ #define PCI_EXT_CAP_ID_RBCB 0x0a /* Root Bridge Control Block */
#define PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */ #define PCI_EXT_CAP_ID_VNDR 0x0b /* Vendor specific */
#define PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */ #define PCI_EXT_CAP_ID_ACS 0x0d /* Access Controls */
#define PCI_EXT_CAP_ID_ARI 0x0e /* Alternative Routing-ID Interpreta tion */ #define PCI_EXT_CAP_ID_ARI 0x0e /* Alternative Routing-ID Interpreta tion */
#define PCI_EXT_CAP_ID_ATS 0x0f /* Address Translation Service */ #define PCI_EXT_CAP_ID_ATS 0x0f /* Address Translation Service */
#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */ #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
#define PCI_EXT_CAP_ID_TPH 0x17 /* Transaction processing hints */
#define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */
/*** Definitions of capabilities ***/ /*** Definitions of capabilities ***/
/* Power Management Registers */ /* Power Management Registers */
#define PCI_PM_CAP_VER_MASK 0x0007 /* Version (2=PM1.1) */ #define PCI_PM_CAP_VER_MASK 0x0007 /* Version (2=PM1.1) */
#define PCI_PM_CAP_PME_CLOCK 0x0008 /* Clock required for PME generation */ #define PCI_PM_CAP_PME_CLOCK 0x0008 /* Clock required for PME generation */
#define PCI_PM_CAP_DSI 0x0020 /* Device specific initializ ation required */ #define PCI_PM_CAP_DSI 0x0020 /* Device specific initializ ation required */
#define PCI_PM_CAP_AUX_C_MASK 0x01c0 /* Maximum aux current required in D 3cold */ #define PCI_PM_CAP_AUX_C_MASK 0x01c0 /* Maximum aux current required in D 3cold */
#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */ #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
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#define PCI_IOV_STRIDE 0x16 /* Routing ID offset from one VF to the next one */ #define PCI_IOV_STRIDE 0x16 /* Routing ID offset from one VF to the next one */
#define PCI_IOV_DID 0x1a /* VF Device ID */ #define PCI_IOV_DID 0x1a /* VF Device ID */
#define PCI_IOV_SUPPS 0x1c /* Supported Page Sizes */ #define PCI_IOV_SUPPS 0x1c /* Supported Page Sizes */
#define PCI_IOV_SYSPS 0x20 /* System Page Size */ #define PCI_IOV_SYSPS 0x20 /* System Page Size */
#define PCI_IOV_BAR_BASE 0x24 /* VF BAR0, VF BAR1, ... VF BAR5 */ #define PCI_IOV_BAR_BASE 0x24 /* VF BAR0, VF BAR1, ... VF BAR5 */
#define PCI_IOV_NUM_BAR 6 /* Number of VF BARs */ #define PCI_IOV_NUM_BAR 6 /* Number of VF BARs */
#define PCI_IOV_MSAO 0x3c /* VF Migration State Array Offset * / #define PCI_IOV_MSAO 0x3c /* VF Migration State Array Offset * /
#define PCI_IOV_MSA_BIR(x) ((x) & 7) /* VF Migration State BIR */ #define PCI_IOV_MSA_BIR(x) ((x) & 7) /* VF Migration State BIR */
#define PCI_IOV_MSA_OFFSET(x) ((x) & 0xfffffff8) /* VF Migration State Off set */ #define PCI_IOV_MSA_OFFSET(x) ((x) & 0xfffffff8) /* VF Migration State Off set */
/* Transaction Processing Hints */
#define PCI_TPH_CAPABILITIES 4
#define PCI_TPH_INTVEC_SUP (1<<1) /* Supports interrupt vector mode */
#define PCI_TPH_DEV_SUP (1<<2) /* Device specific mode supp
orted */
#define PCI_TPH_EXT_REQ_SUP (1<<8) /* Supports extended requests */
#define PCI_TPH_ST_LOC_MASK (3<<9) /* Steering table location bits */
#define PCI_TPH_ST_NONE (0<<9) /* No steering table */
#define PCI_TPH_ST_CAP (1<<9) /* Steering table in TPH cap */
#define PCI_TPH_ST_MSIX (2<<9) /* Steering table in MSI-X table */
#define PCI_TPH_ST_SIZE_SHIFT (16) /* Encoded as size - 1 */
/* Latency Tolerance Reporting */
#define PCI_LTR_MAX_SNOOP 4 /* 16 bit value */
#define PCI_LTR_VALUE_MASK (0x3ff)
#define PCI_LTR_SCALE_SHIFT (10)
#define PCI_LTR_SCALE_MASK (7)
#define PCI_LTR_MAX_NOSNOOP 6 /* 16 bit value */
/* /*
* The PCI interface treats multi-function devices as independent * The PCI interface treats multi-function devices as independent
* devices. The slot/function address of each device is encoded * devices. The slot/function address of each device is encoded
* in a single byte as follows: * in a single byte as follows:
* *
* 7:3 = slot * 7:3 = slot
* 2:0 = function * 2:0 = function
*/ */
#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) #define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
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 types.h   types.h 
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#ifdef PCI_ARCH_SPARC64 #ifdef PCI_ARCH_SPARC64
/* On sparc64 Linux the kernel reports remapped port addresses and IRQ numb ers */ /* On sparc64 Linux the kernel reports remapped port addresses and IRQ numb ers */
#undef PCIADDR_PORT_FMT #undef PCIADDR_PORT_FMT
#define PCIADDR_PORT_FMT PCIADDR_T_FMT #define PCIADDR_PORT_FMT PCIADDR_T_FMT
#define PCIIRQ_FMT "%08x" #define PCIIRQ_FMT "%08x"
#else #else
#define PCIIRQ_FMT "%d" #define PCIIRQ_FMT "%d"
#endif #endif
#ifdef __GNUC__ #if defined(__GNUC__) && __GNUC__ > 2
#define PCI_PRINTF(x,y) __attribute__((format(printf, x, y))) #define PCI_PRINTF(x,y) __attribute__((format(printf, x, y)))
#else #else
#define PCI_PRINTF(x,y) #define PCI_PRINTF(x,y)
#endif #endif
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