| config.h | config.h | |||
|---|---|---|---|---|
| skipping to change at line 14 | skipping to change at line 14 | |||
| #define PCI_HAVE_PM_LINUX_SYSFS | #define PCI_HAVE_PM_LINUX_SYSFS | |||
| #define PCI_HAVE_PM_LINUX_PROC | #define PCI_HAVE_PM_LINUX_PROC | |||
| #define PCI_HAVE_LINUX_BYTEORDER_H | #define PCI_HAVE_LINUX_BYTEORDER_H | |||
| #define PCI_PATH_PROC_BUS_PCI "/proc/bus/pci" | #define PCI_PATH_PROC_BUS_PCI "/proc/bus/pci" | |||
| #define PCI_PATH_SYS_BUS_PCI "/sys/bus/pci" | #define PCI_PATH_SYS_BUS_PCI "/sys/bus/pci" | |||
| #define PCI_HAVE_PM_INTEL_CONF | #define PCI_HAVE_PM_INTEL_CONF | |||
| #define PCI_HAVE_64BIT_ADDRESS | #define PCI_HAVE_64BIT_ADDRESS | |||
| #define PCI_HAVE_PM_DUMP | #define PCI_HAVE_PM_DUMP | |||
| #define PCI_COMPRESSED_IDS | #define PCI_COMPRESSED_IDS | |||
| #define PCI_IDS "pci.ids.gz" | #define PCI_IDS "pci.ids.gz" | |||
| #define PCI_PATH_IDS_DIR "/home/andrey/upstream-tracker/testing/pciutils/3. 1.8/share" | #define PCI_PATH_IDS_DIR "/home/andrey/upstream-tracker/testing/pciutils/3. 1.9/share" | |||
| #define PCI_USE_DNS | #define PCI_USE_DNS | |||
| #define PCI_ID_DOMAIN "pci.id.ucw.cz" | #define PCI_ID_DOMAIN "pci.id.ucw.cz" | |||
| #define PCI_SHARED_LIB | #define PCI_SHARED_LIB | |||
| #define PCILIB_VERSION "3.1.8" | #define PCILIB_VERSION "3.1.9" | |||
| End of changes. 2 change blocks. | ||||
| 1 lines changed or deleted | 1 lines changed or added | |||
| header.h | header.h | |||
|---|---|---|---|---|
| skipping to change at line 863 | skipping to change at line 863 | |||
| #define PCI_EXP_DEVSTA2 0x2a /* Device Status */ | #define PCI_EXP_DEVSTA2 0x2a /* Device Status */ | |||
| #define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities */ | #define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities */ | |||
| #define PCI_EXP_LNKCTL2 0x30 /* Link Control */ | #define PCI_EXP_LNKCTL2 0x30 /* Link Control */ | |||
| #define PCI_EXP_LNKCTL2_SPEED(x) ((x) & 0xf) /* Target Link Speed */ | #define PCI_EXP_LNKCTL2_SPEED(x) ((x) & 0xf) /* Target Link Speed */ | |||
| #define PCI_EXP_LNKCTL2_CMPLNC 0x0010 /* Enter Compliance */ | #define PCI_EXP_LNKCTL2_CMPLNC 0x0010 /* Enter Compliance */ | |||
| #define PCI_EXP_LNKCTL2_SPEED_DIS 0x0020 /* Hardware Autonomous Speed Disable */ | #define PCI_EXP_LNKCTL2_SPEED_DIS 0x0020 /* Hardware Autonomous Speed Disable */ | |||
| #define PCI_EXP_LNKCTL2_DEEMPHASIS(x) (((x) >> 6) & 1) /* Selectable De-em phasis */ | #define PCI_EXP_LNKCTL2_DEEMPHASIS(x) (((x) >> 6) & 1) /* Selectable De-em phasis */ | |||
| #define PCI_EXP_LNKCTL2_MARGIN(x) (((x) >> 7) & 7) /* Transmit Margin */ | #define PCI_EXP_LNKCTL2_MARGIN(x) (((x) >> 7) & 7) /* Transmit Margin */ | |||
| #define PCI_EXP_LNKCTL2_MOD_CMPLNC 0x0400 /* Enter Modified Compliance */ | #define PCI_EXP_LNKCTL2_MOD_CMPLNC 0x0400 /* Enter Modified Compliance */ | |||
| #define PCI_EXP_LNKCTL2_CMPLNC_SOS 0x0800 /* Compliance SOS */ | #define PCI_EXP_LNKCTL2_CMPLNC_SOS 0x0800 /* Compliance SOS */ | |||
| #define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 1) /* Compliance De-emphasis */ | #define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 0xf) /* Complianc e De-emphasis */ | |||
| #define PCI_EXP_LNKSTA2 0x32 /* Link Status */ | #define PCI_EXP_LNKSTA2 0x32 /* Link Status */ | |||
| #define PCI_EXP_LINKSTA2_DEEMPHASIS(x) ((x) & 1) /* Current D e-emphasis Level */ | #define PCI_EXP_LINKSTA2_DEEMPHASIS(x) ((x) & 1) /* Current D e-emphasis Level */ | |||
| #define PCI_EXP_LINKSTA2_EQU_COMP 0x02 /* Equalization Complete */ | ||||
| #define PCI_EXP_LINKSTA2_EQU_PHASE1 0x04 /* Equalization Phase 1 Succ | ||||
| essful */ | ||||
| #define PCI_EXP_LINKSTA2_EQU_PHASE2 0x08 /* Equalization Phase 2 Succ | ||||
| essful */ | ||||
| #define PCI_EXP_LINKSTA2_EQU_PHASE3 0x10 /* Equalization Phase 3 Succ | ||||
| essful */ | ||||
| #define PCI_EXP_LINKSTA2_EQU_REQ 0x20 /* Link Equalization Request | ||||
| */ | ||||
| #define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities */ | #define PCI_EXP_SLTCAP2 0x34 /* Slot Capabilities */ | |||
| #define PCI_EXP_SLTCTL2 0x38 /* Slot Control */ | #define PCI_EXP_SLTCTL2 0x38 /* Slot Control */ | |||
| #define PCI_EXP_SLTSTA2 0x3a /* Slot Status */ | #define PCI_EXP_SLTSTA2 0x3a /* Slot Status */ | |||
| /* MSI-X */ | /* MSI-X */ | |||
| #define PCI_MSIX_ENABLE 0x8000 | #define PCI_MSIX_ENABLE 0x8000 | |||
| #define PCI_MSIX_MASK 0x4000 | #define PCI_MSIX_MASK 0x4000 | |||
| #define PCI_MSIX_TABSIZE 0x07ff | #define PCI_MSIX_TABSIZE 0x07ff | |||
| #define PCI_MSIX_TABLE 4 | #define PCI_MSIX_TABLE 4 | |||
| #define PCI_MSIX_PBA 8 | #define PCI_MSIX_PBA 8 | |||
| End of changes. 2 change blocks. | ||||
| 1 lines changed or deleted | 10 lines changed or added | |||