| config.h | config.h | |||
|---|---|---|---|---|
| skipping to change at line 14 | skipping to change at line 14 | |||
| #define PCI_HAVE_PM_LINUX_SYSFS | #define PCI_HAVE_PM_LINUX_SYSFS | |||
| #define PCI_HAVE_PM_LINUX_PROC | #define PCI_HAVE_PM_LINUX_PROC | |||
| #define PCI_HAVE_LINUX_BYTEORDER_H | #define PCI_HAVE_LINUX_BYTEORDER_H | |||
| #define PCI_PATH_PROC_BUS_PCI "/proc/bus/pci" | #define PCI_PATH_PROC_BUS_PCI "/proc/bus/pci" | |||
| #define PCI_PATH_SYS_BUS_PCI "/sys/bus/pci" | #define PCI_PATH_SYS_BUS_PCI "/sys/bus/pci" | |||
| #define PCI_HAVE_PM_INTEL_CONF | #define PCI_HAVE_PM_INTEL_CONF | |||
| #define PCI_HAVE_64BIT_ADDRESS | #define PCI_HAVE_64BIT_ADDRESS | |||
| #define PCI_HAVE_PM_DUMP | #define PCI_HAVE_PM_DUMP | |||
| #define PCI_COMPRESSED_IDS | #define PCI_COMPRESSED_IDS | |||
| #define PCI_IDS "pci.ids.gz" | #define PCI_IDS "pci.ids.gz" | |||
| #define PCI_PATH_IDS_DIR "/home/andrey/upstream-tracker/testing/pciutils/3. 1.9/share" | #define PCI_PATH_IDS_DIR "/home/andrey/upstream-tracker/testing/pciutils/3. 1.10/share" | |||
| #define PCI_USE_DNS | #define PCI_USE_DNS | |||
| #define PCI_ID_DOMAIN "pci.id.ucw.cz" | #define PCI_ID_DOMAIN "pci.id.ucw.cz" | |||
| #define PCI_SHARED_LIB | #define PCI_SHARED_LIB | |||
| #define PCILIB_VERSION "3.1.9" | #define PCILIB_VERSION "3.1.10" | |||
| End of changes. 2 change blocks. | ||||
| 1 lines changed or deleted | 1 lines changed or added | |||
| header.h | header.h | |||
|---|---|---|---|---|
| skipping to change at line 848 | skipping to change at line 848 | |||
| #define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */ | #define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */ | |||
| #define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */ | #define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */ | |||
| #define PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Statu s Visible to SW */ | #define PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Statu s Visible to SW */ | |||
| #define PCI_EXP_RTCAP 0x1e /* Root Capabilities */ | #define PCI_EXP_RTCAP 0x1e /* Root Capabilities */ | |||
| #define PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Statu s Visible to SW */ | #define PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Statu s Visible to SW */ | |||
| #define PCI_EXP_RTSTA 0x20 /* Root Status */ | #define PCI_EXP_RTSTA 0x20 /* Root Status */ | |||
| #define PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */ | #define PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */ | |||
| #define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */ | #define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */ | |||
| #define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */ | #define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */ | |||
| #define PCI_EXP_DEVCAP2 0x24 /* Device capabiliti es 2 */ | #define PCI_EXP_DEVCAP2 0x24 /* Device capabiliti es 2 */ | |||
| #define PCI_EXP_DEVCAP2_LTR 0x0800 /* LTR supported */ | ||||
| #define PCI_EXP_DEVCAP2_OBFF(x) (((x) >> 18) & 3) /* OBFF supported | ||||
| */ | ||||
| #define PCI_EXP_DEVCTL2 0x28 /* Device Control */ | #define PCI_EXP_DEVCTL2 0x28 /* Device Control */ | |||
| #define PCI_EXP_DEV2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ra nges Supported */ | #define PCI_EXP_DEV2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ra nges Supported */ | |||
| #define PCI_EXP_DEV2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Va lue */ | #define PCI_EXP_DEV2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Va lue */ | |||
| #define PCI_EXP_DEV2_TIMEOUT_DIS 0x0010 /* Completion Timeout Disabl e Supported */ | #define PCI_EXP_DEV2_TIMEOUT_DIS 0x0010 /* Completion Timeout Disabl e Supported */ | |||
| #define PCI_EXP_DEV2_ARI 0x0020 /* ARI Forwarding */ | #define PCI_EXP_DEV2_ARI 0x0020 /* ARI Forwarding */ | |||
| #define PCI_EXP_DEV2_LTR 0x0400 /* LTR enabled */ | ||||
| #define PCI_EXP_DEV2_OBFF(x) (((x) >> 13) & 3) /* OBFF enabled */ | ||||
| #define PCI_EXP_DEVSTA2 0x2a /* Device Status */ | #define PCI_EXP_DEVSTA2 0x2a /* Device Status */ | |||
| #define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities */ | #define PCI_EXP_LNKCAP2 0x2c /* Link Capabilities */ | |||
| #define PCI_EXP_LNKCTL2 0x30 /* Link Control */ | #define PCI_EXP_LNKCTL2 0x30 /* Link Control */ | |||
| #define PCI_EXP_LNKCTL2_SPEED(x) ((x) & 0xf) /* Target Link Speed */ | #define PCI_EXP_LNKCTL2_SPEED(x) ((x) & 0xf) /* Target Link Speed */ | |||
| #define PCI_EXP_LNKCTL2_CMPLNC 0x0010 /* Enter Compliance */ | #define PCI_EXP_LNKCTL2_CMPLNC 0x0010 /* Enter Compliance */ | |||
| #define PCI_EXP_LNKCTL2_SPEED_DIS 0x0020 /* Hardware Autonomous Speed Disable */ | #define PCI_EXP_LNKCTL2_SPEED_DIS 0x0020 /* Hardware Autonomous Speed Disable */ | |||
| #define PCI_EXP_LNKCTL2_DEEMPHASIS(x) (((x) >> 6) & 1) /* Selectable De-em phasis */ | #define PCI_EXP_LNKCTL2_DEEMPHASIS(x) (((x) >> 6) & 1) /* Selectable De-em phasis */ | |||
| #define PCI_EXP_LNKCTL2_MARGIN(x) (((x) >> 7) & 7) /* Transmit Margin */ | #define PCI_EXP_LNKCTL2_MARGIN(x) (((x) >> 7) & 7) /* Transmit Margin */ | |||
| #define PCI_EXP_LNKCTL2_MOD_CMPLNC 0x0400 /* Enter Modified Compliance */ | #define PCI_EXP_LNKCTL2_MOD_CMPLNC 0x0400 /* Enter Modified Compliance */ | |||
| #define PCI_EXP_LNKCTL2_CMPLNC_SOS 0x0800 /* Compliance SOS */ | #define PCI_EXP_LNKCTL2_CMPLNC_SOS 0x0800 /* Compliance SOS */ | |||
| End of changes. 2 change blocks. | ||||
| 0 lines changed or deleted | 5 lines changed or added | |||