config.h   config.h 
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#define PCI_HAVE_PM_INTEL_CONF #define PCI_HAVE_PM_INTEL_CONF
#define PCI_HAVE_64BIT_ADDRESS #define PCI_HAVE_64BIT_ADDRESS
#define PCI_HAVE_PM_DUMP #define PCI_HAVE_PM_DUMP
#define PCI_COMPRESSED_IDS #define PCI_COMPRESSED_IDS
#define PCI_IDS "pci.ids.gz" #define PCI_IDS "pci.ids.gz"
#define PCI_PATH_IDS_DIR "/usr/local/share" #define PCI_PATH_IDS_DIR "/usr/local/share"
#define PCI_USE_DNS #define PCI_USE_DNS
#define PCI_ID_DOMAIN "pci.id.ucw.cz" #define PCI_ID_DOMAIN "pci.id.ucw.cz"
#define PCI_USE_LIBKMOD #define PCI_USE_LIBKMOD
#define PCI_SHARED_LIB #define PCI_SHARED_LIB
#define PCILIB_VERSION "3.2.1" #define PCILIB_VERSION "3.3.0"
 End of changes. 1 change blocks. 
0 lines changed or deleted 0 lines changed or added


 header.h   header.h 
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#define PCI_EXP_LNKCAP 0xc /* Link Capabilities */ #define PCI_EXP_LNKCAP 0xc /* Link Capabilities */
#define PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */ #define PCI_EXP_LNKCAP_SPEED 0x0000f /* Maximum Link Speed */
#define PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */ #define PCI_EXP_LNKCAP_WIDTH 0x003f0 /* Maximum Link Width */
#define PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */ #define PCI_EXP_LNKCAP_ASPM 0x00c00 /* Active State Power Management */
#define PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */ #define PCI_EXP_LNKCAP_L0S 0x07000 /* L0s Acceptable Latency */
#define PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */ #define PCI_EXP_LNKCAP_L1 0x38000 /* L1 Acceptable Latency */
#define PCI_EXP_LNKCAP_CLOCKPM 0x40000 /* Clock Power Management */ #define PCI_EXP_LNKCAP_CLOCKPM 0x40000 /* Clock Power Management */
#define PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting * / #define PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting * /
#define PCI_EXP_LNKCAP_DLLA 0x100000 /* Data Link Layer Active Reporting */ #define PCI_EXP_LNKCAP_DLLA 0x100000 /* Data Link Layer Active Reporting */
#define PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capa bility */ #define PCI_EXP_LNKCAP_LBNC 0x200000 /* Link Bandwidth Notification Capa bility */
#define PCI_EXP_LNKCAP_AOC 0x400000 /* ASPM Optionality Compliance */
#define PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */ #define PCI_EXP_LNKCAP_PORT 0xff000000 /* Port Number */
#define PCI_EXP_LNKCTL 0x10 /* Link Control */ #define PCI_EXP_LNKCTL 0x10 /* Link Control */
#define PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */ #define PCI_EXP_LNKCTL_ASPM 0x0003 /* ASPM Control */
#define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */ #define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
#define PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */ #define PCI_EXP_LNKCTL_DISABLE 0x0010 /* Link Disable */
#define PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */ #define PCI_EXP_LNKCTL_RETRAIN 0x0020 /* Retrain Link */
#define PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */ #define PCI_EXP_LNKCTL_CLOCK 0x0040 /* Common Clock Configuration */
#define PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */ #define PCI_EXP_LNKCTL_XSYNCH 0x0080 /* Extended Synch */
#define PCI_EXP_LNKCTL_CLOCKPM 0x0100 /* Clock Power Management */ #define PCI_EXP_LNKCTL_CLOCKPM 0x0100 /* Clock Power Management */
#define PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width Disable */ #define PCI_EXP_LNKCTL_HWAUTWD 0x0200 /* Hardware Autonomous Width Disable */
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#define PCI_EXP_SLTSTA_PRES 0x0040 /* Presence Detect State */ #define PCI_EXP_SLTSTA_PRES 0x0040 /* Presence Detect State */
#define PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Sta tus */ #define PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Sta tus */
#define PCI_EXP_SLTSTA_LLCHG 0x0100 /* Data Link Layer State Changed */ #define PCI_EXP_SLTSTA_LLCHG 0x0100 /* Data Link Layer State Changed */
#define PCI_EXP_RTCTL 0x1c /* Root Control */ #define PCI_EXP_RTCTL 0x1c /* Root Control */
#define PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */ #define PCI_EXP_RTCTL_SECEE 0x0001 /* System Error on Correctable Error */
#define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error * / #define PCI_EXP_RTCTL_SENFEE 0x0002 /* System Error on Non-Fatal Error * /
#define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */ #define PCI_EXP_RTCTL_SEFEE 0x0004 /* System Error on Fatal Error */
#define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */ #define PCI_EXP_RTCTL_PMEIE 0x0008 /* PME Interrupt Enable */
#define PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Statu s Visible to SW */ #define PCI_EXP_RTCTL_CRSVIS 0x0010 /* Configuration Request Retry Statu s Visible to SW */
#define PCI_EXP_RTCAP 0x1e /* Root Capabilities */ #define PCI_EXP_RTCAP 0x1e /* Root Capabilities */
#define PCI_EXP_RTCAP_CRSVIS 0x0010 /* Configuration Request Retry Statu s Visible to SW */ #define PCI_EXP_RTCAP_CRSVIS 0x0001 /* Configuration Request Retry Statu s Visible to SW */
#define PCI_EXP_RTSTA 0x20 /* Root Status */ #define PCI_EXP_RTSTA 0x20 /* Root Status */
#define PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */ #define PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */
#define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */ #define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */
#define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */ #define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */
#define PCI_EXP_DEVCAP2 0x24 /* Device capabiliti es 2 */ #define PCI_EXP_DEVCAP2 0x24 /* Device capabiliti es 2 */
#define PCI_EXP_DEVCAP2_LTR 0x0800 /* LTR supported */ #define PCI_EXP_DEVCAP2_LTR 0x0800 /* LTR supported */
#define PCI_EXP_DEVCAP2_OBFF(x) (((x) >> 18) & 3) /* OBFF supported */ #define PCI_EXP_DEVCAP2_OBFF(x) (((x) >> 18) & 3) /* OBFF supported */
#define PCI_EXP_DEVCTL2 0x28 /* Device Control */ #define PCI_EXP_DEVCTL2 0x28 /* Device Control */
#define PCI_EXP_DEV2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ra nges Supported */ #define PCI_EXP_DEV2_TIMEOUT_RANGE(x) ((x) & 0xf) /* Completion Timeout Ra nges Supported */
#define PCI_EXP_DEV2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Va lue */ #define PCI_EXP_DEV2_TIMEOUT_VALUE(x) ((x) & 0xf) /* Completion Timeout Va lue */
 End of changes. 2 change blocks. 
1 lines changed or deleted 2 lines changed or added


 pci.h   pci.h 
/* /*
* The PCI Library * The PCI Library
* *
* Copyright (c) 1997--2013 Martin Mares <mj@ucw.cz> * Copyright (c) 1997--2014 Martin Mares <mj@ucw.cz>
* *
* Can be freely distributed and used under the terms of the GNU GPL. * Can be freely distributed and used under the terms of the GNU GPL.
*/ */
#ifndef _PCI_LIB_H #ifndef _PCI_LIB_H
#define _PCI_LIB_H #define _PCI_LIB_H
#ifndef PCI_CONFIG_H #ifndef PCI_CONFIG_H
#include "config.h" #include "config.h"
#endif #endif
#include "header.h" #include "header.h"
#include "types.h" #include "types.h"
#define PCI_LIB_VERSION 0x030200 #define PCI_LIB_VERSION 0x030300
#ifndef PCI_ABI #ifndef PCI_ABI
#define PCI_ABI #define PCI_ABI
#endif #endif
/* /*
* PCI Access Structure * PCI Access Structure
*/ */
struct pci_methods; struct pci_methods;
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/* Known access methods, remember to update access.c as well */ /* Known access methods, remember to update access.c as well */
PCI_ACCESS_AUTO, /* Autodetection */ PCI_ACCESS_AUTO, /* Autodetection */
PCI_ACCESS_SYS_BUS_PCI, /* Linux /sys/bus/pci */ PCI_ACCESS_SYS_BUS_PCI, /* Linux /sys/bus/pci */
PCI_ACCESS_PROC_BUS_PCI, /* Linux /proc/bus/pci */ PCI_ACCESS_PROC_BUS_PCI, /* Linux /proc/bus/pci */
PCI_ACCESS_I386_TYPE1, /* i386 ports, type 1 */ PCI_ACCESS_I386_TYPE1, /* i386 ports, type 1 */
PCI_ACCESS_I386_TYPE2, /* i386 ports, type 2 */ PCI_ACCESS_I386_TYPE2, /* i386 ports, type 2 */
PCI_ACCESS_FBSD_DEVICE, /* FreeBSD /dev/pci */ PCI_ACCESS_FBSD_DEVICE, /* FreeBSD /dev/pci */
PCI_ACCESS_AIX_DEVICE, /* /dev/pci0, /dev/bus0, etc. */ PCI_ACCESS_AIX_DEVICE, /* /dev/pci0, /dev/bus0, etc. */
PCI_ACCESS_NBSD_LIBPCI, /* NetBSD libpci */ PCI_ACCESS_NBSD_LIBPCI, /* NetBSD libpci */
PCI_ACCESS_OBSD_DEVICE, /* OpenBSD /dev/pci */ PCI_ACCESS_OBSD_DEVICE, /* OpenBSD /dev/pci */
PCI_ACCESS_DUMP, /* Dump file */ PCI_ACCESS_DUMP, /* Dump file */
PCI_ACCESS_DARWIN, /* Darwin */
PCI_ACCESS_MAX PCI_ACCESS_MAX
}; };
struct pci_access { struct pci_access {
/* Options you can change: */ /* Options you can change: */
unsigned int method; /* Access method */ unsigned int method; /* Access method */
int writeable; /* Open in read/write mode */ int writeable; /* Open in read/write mode */
int buscentric; /* Bus-centric view of the world */ int buscentric; /* Bus-centric view of the world */
char *id_file_name; /* Name of ID list file (use pci_set _name_list_path()) */ char *id_file_name; /* Name of ID list file (use pci_set _name_list_path()) */
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struct pci_dev *devices; /* Devices found on this bus */ struct pci_dev *devices; /* Devices found on this bus */
/* Fields used internally: */ /* Fields used internally: */
struct pci_methods *methods; struct pci_methods *methods;
struct pci_param *params; struct pci_param *params;
struct id_entry **id_hash; /* names.c */ struct id_entry **id_hash; /* names.c */
struct id_bucket *current_id_bucket; struct id_bucket *current_id_bucket;
int id_load_failed; int id_load_failed;
int id_cache_status; /* 0=not read, 1=read, 2=dirty */ int id_cache_status; /* 0=not read, 1=read, 2=dirty */
struct udev *id_udev; /* names-hwdb.c */
struct udev_hwdb *id_udev_hwdb;
int fd; /* proc/sys: fd for config space */ int fd; /* proc/sys: fd for config space */
int fd_rw; /* proc/sys: fd opened read-write */ int fd_rw; /* proc/sys: fd opened read-write */
int fd_pos; /* proc/sys: current position */ int fd_pos; /* proc/sys: current position */
int fd_vpd; /* sys: fd for VPD */ int fd_vpd; /* sys: fd for VPD */
struct pci_dev *cached_dev; /* proc/sys: device the fds are for */ struct pci_dev *cached_dev; /* proc/sys: device the fds are for */
}; };
/* Initialize PCI access */ /* Initialize PCI access */
struct pci_access *pci_alloc(void) PCI_ABI; struct pci_access *pci_alloc(void) PCI_ABI;
void pci_init(struct pci_access *) PCI_ABI; void pci_init(struct pci_access *) PCI_ABI;
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u16 vendor_id, device_id; /* Identity of the device */ u16 vendor_id, device_id; /* Identity of the device */
u16 device_class; /* PCI device class */ u16 device_class; /* PCI device class */
int irq; /* IRQ number */ int irq; /* IRQ number */
pciaddr_t base_addr[6]; /* Base addresses including flags in lower bits */ pciaddr_t base_addr[6]; /* Base addresses including flags in lower bits */
pciaddr_t size[6]; /* Region sizes */ pciaddr_t size[6]; /* Region sizes */
pciaddr_t rom_base_addr; /* Expansion ROM base address */ pciaddr_t rom_base_addr; /* Expansion ROM base address */
pciaddr_t rom_size; /* Expansion ROM size */ pciaddr_t rom_size; /* Expansion ROM size */
struct pci_cap *first_cap; /* List of capabilities */ struct pci_cap *first_cap; /* List of capabilities */
char *phy_slot; /* Physical slot */ char *phy_slot; /* Physical slot */
char *module_alias; /* Linux kernel module alias */ char *module_alias; /* Linux kernel module alias */
char *label; /* Device name as exported by BIOS * /
/* Fields used internally: */ /* Fields used internally: */
struct pci_access *access; struct pci_access *access;
struct pci_methods *methods; struct pci_methods *methods;
u8 *cache; /* Cached config registers */ u8 *cache; /* Cached config registers */
int cache_len; int cache_len;
int hdrtype; /* Cached low 7 bits of header type, -1 if unknown */ int hdrtype; /* Cached low 7 bits of header type, -1 if unknown */
void *aux; /* Auxillary data */ void *aux; /* Auxillary data */
}; };
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#define PCI_FILL_IDENT 1 #define PCI_FILL_IDENT 1
#define PCI_FILL_IRQ 2 #define PCI_FILL_IRQ 2
#define PCI_FILL_BASES 4 #define PCI_FILL_BASES 4
#define PCI_FILL_ROM_BASE 8 #define PCI_FILL_ROM_BASE 8
#define PCI_FILL_SIZES 16 #define PCI_FILL_SIZES 16
#define PCI_FILL_CLASS 32 #define PCI_FILL_CLASS 32
#define PCI_FILL_CAPS 64 #define PCI_FILL_CAPS 64
#define PCI_FILL_EXT_CAPS 128 #define PCI_FILL_EXT_CAPS 128
#define PCI_FILL_PHYS_SLOT 256 #define PCI_FILL_PHYS_SLOT 256
#define PCI_FILL_MODULE_ALIAS 512 #define PCI_FILL_MODULE_ALIAS 512
#define PCI_FILL_LABEL 1024
#define PCI_FILL_RESCAN 0x10000 #define PCI_FILL_RESCAN 0x10000
void pci_setup_cache(struct pci_dev *, u8 *cache, int len) PCI_ABI; void pci_setup_cache(struct pci_dev *, u8 *cache, int len) PCI_ABI;
/* /*
* Capabilities * Capabilities
*/ */
struct pci_cap { struct pci_cap {
struct pci_cap *next; struct pci_cap *next;
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#define PCI_CAP_EXTENDED 2 /* PCIe extended capabilities */ #define PCI_CAP_EXTENDED 2 /* PCIe extended capabilities */
struct pci_cap *pci_find_cap(struct pci_dev *, unsigned int id, unsigned in t type) PCI_ABI; struct pci_cap *pci_find_cap(struct pci_dev *, unsigned int id, unsigned in t type) PCI_ABI;
/* /*
* Filters * Filters
*/ */
struct pci_filter { struct pci_filter {
int domain, bus, slot, func; /* -1 = ANY */ int domain, bus, slot, func; /* -1 = ANY */
int vendor, device; int vendor, device, device_class;
int rfu[3];
}; };
void pci_filter_init(struct pci_access *, struct pci_filter *) PCI_ABI; void pci_filter_init(struct pci_access *, struct pci_filter *) PCI_ABI;
char *pci_filter_parse_slot(struct pci_filter *, char *) PCI_ABI; char *pci_filter_parse_slot(struct pci_filter *, char *) PCI_ABI;
char *pci_filter_parse_id(struct pci_filter *, char *) PCI_ABI; char *pci_filter_parse_id(struct pci_filter *, char *) PCI_ABI;
int pci_filter_match(struct pci_filter *, struct pci_dev *) PCI_ABI; int pci_filter_match(struct pci_filter *, struct pci_dev *) PCI_ABI;
/* /*
* Conversion of PCI ID's to names (according to the pci.ids file) * Conversion of PCI ID's to names (according to the pci.ids file)
* *
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PCI_LOOKUP_CLASS = 4, /* Device class (args: class ID) */ PCI_LOOKUP_CLASS = 4, /* Device class (args: class ID) */
PCI_LOOKUP_SUBSYSTEM = 8, PCI_LOOKUP_SUBSYSTEM = 8,
PCI_LOOKUP_PROGIF = 16, /* Programming interface (args: clas sID, prog_if) */ PCI_LOOKUP_PROGIF = 16, /* Programming interface (args: clas sID, prog_if) */
PCI_LOOKUP_NUMERIC = 0x10000, /* Want only formatted numbe rs; default if access->numeric_ids is set */ PCI_LOOKUP_NUMERIC = 0x10000, /* Want only formatted numbe rs; default if access->numeric_ids is set */
PCI_LOOKUP_NO_NUMBERS = 0x20000, /* Return NULL if not found in the d atabase; default is to print numerically */ PCI_LOOKUP_NO_NUMBERS = 0x20000, /* Return NULL if not found in the d atabase; default is to print numerically */
PCI_LOOKUP_MIXED = 0x40000, /* Include both numbers and names */ PCI_LOOKUP_MIXED = 0x40000, /* Include both numbers and names */
PCI_LOOKUP_NETWORK = 0x80000, /* Try to resolve unknown ID 's by DNS */ PCI_LOOKUP_NETWORK = 0x80000, /* Try to resolve unknown ID 's by DNS */
PCI_LOOKUP_SKIP_LOCAL = 0x100000, /* Do not consult local database */ PCI_LOOKUP_SKIP_LOCAL = 0x100000, /* Do not consult local database */
PCI_LOOKUP_CACHE = 0x200000, /* Consult the local cache before us ing DNS */ PCI_LOOKUP_CACHE = 0x200000, /* Consult the local cache before us ing DNS */
PCI_LOOKUP_REFRESH_CACHE = 0x400000, /* Forget all previously cached entr ies, but still allow updating the cache */ PCI_LOOKUP_REFRESH_CACHE = 0x400000, /* Forget all previously cached entr ies, but still allow updating the cache */
PCI_LOOKUP_NO_HWDB = 0x800000, /* Do not ask udev's hwdb */
}; };
#endif #endif
 End of changes. 8 change blocks. 
4 lines changed or deleted 11 lines changed or added

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